adapter.h revision 346934
1218792Snp/*- 2218792Snp * Copyright (c) 2011 Chelsio Communications, Inc. 3218792Snp * All rights reserved. 4218792Snp * Written by: Navdeep Parhar <np@FreeBSD.org> 5218792Snp * 6218792Snp * Redistribution and use in source and binary forms, with or without 7218792Snp * modification, are permitted provided that the following conditions 8218792Snp * are met: 9218792Snp * 1. Redistributions of source code must retain the above copyright 10218792Snp * notice, this list of conditions and the following disclaimer. 11218792Snp * 2. Redistributions in binary form must reproduce the above copyright 12218792Snp * notice, this list of conditions and the following disclaimer in the 13218792Snp * documentation and/or other materials provided with the distribution. 14218792Snp * 15218792Snp * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16218792Snp * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17218792Snp * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18218792Snp * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19218792Snp * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20218792Snp * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21218792Snp * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22218792Snp * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23218792Snp * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24218792Snp * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25218792Snp * SUCH DAMAGE. 26218792Snp * 27218792Snp * $FreeBSD: stable/11/sys/dev/cxgbe/adapter.h 346934 2019-04-29 22:16:33Z np $ 28218792Snp * 29218792Snp */ 30218792Snp 31218792Snp#ifndef __T4_ADAPTER_H__ 32218792Snp#define __T4_ADAPTER_H__ 33218792Snp 34228561Snp#include <sys/kernel.h> 35218792Snp#include <sys/bus.h> 36218792Snp#include <sys/rman.h> 37218792Snp#include <sys/types.h> 38257176Sglebius#include <sys/lock.h> 39218792Snp#include <sys/malloc.h> 40257176Sglebius#include <sys/rwlock.h> 41257176Sglebius#include <sys/sx.h> 42345664Sjhb#include <sys/vmem.h> 43257176Sglebius#include <vm/uma.h> 44257176Sglebius 45218792Snp#include <dev/pci/pcivar.h> 46218792Snp#include <dev/pci/pcireg.h> 47218792Snp#include <machine/bus.h> 48218792Snp#include <sys/socket.h> 49218792Snp#include <sys/sysctl.h> 50218792Snp#include <net/ethernet.h> 51218792Snp#include <net/if.h> 52257176Sglebius#include <net/if_var.h> 53218792Snp#include <net/if_media.h> 54235944Sbz#include <netinet/in.h> 55218792Snp#include <netinet/tcp_lro.h> 56218792Snp 57218792Snp#include "offload.h" 58301535Snp#include "t4_ioctl.h" 59266757Snp#include "common/t4_msg.h" 60228561Snp#include "firmware/t4fw_interface.h" 61218792Snp 62275733Snp#define KTR_CXGBE KTR_SPARE3 63218792SnpMALLOC_DECLARE(M_CXGBE); 64218792Snp#define CXGBE_UNIMPLEMENTED(s) \ 65218792Snp panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__) 66218792Snp 67218792Snp#if defined(__i386__) || defined(__amd64__) 68218792Snpstatic __inline void 69218792Snpprefetch(void *x) 70218792Snp{ 71218792Snp __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 72218792Snp} 73218792Snp#else 74339396Snp#define prefetch(x) __builtin_prefetch(x) 75218792Snp#endif 76218792Snp 77231115Snp#ifndef SYSCTL_ADD_UQUAD 78231115Snp#define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 79231115Snp#define sysctl_handle_64 sysctl_handle_quad 80231115Snp#define CTLTYPE_U64 CTLTYPE_QUAD 81231115Snp#endif 82231115Snp 83344858SjhbSYSCTL_DECL(_hw_cxgbe); 84344858Sjhb 85218792Snpstruct adapter; 86218792Snptypedef struct adapter adapter_t; 87218792Snp 88218792Snpenum { 89269411Snp /* 90269411Snp * All ingress queues use this entry size. Note that the firmware event 91269411Snp * queue and any iq expecting CPL_RX_PKT in the descriptor needs this to 92269411Snp * be at least 64. 93269411Snp */ 94269411Snp IQ_ESIZE = 64, 95269411Snp 96269411Snp /* Default queue sizes for all kinds of ingress queues */ 97218792Snp FW_IQ_QSIZE = 256, 98218792Snp RX_IQ_QSIZE = 1024, 99218792Snp 100269411Snp /* All egress queues use this entry size */ 101269411Snp EQ_ESIZE = 64, 102218792Snp 103269411Snp /* Default queue sizes for all kinds of egress queues */ 104346876Snp CTRL_EQ_QSIZE = 1024, 105269411Snp TX_EQ_QSIZE = 1024, 106269411Snp 107219392Snp#if MJUMPAGESIZE != MCLBYTES 108263317Snp SW_ZONE_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */ 109219392Snp#else 110263317Snp SW_ZONE_SIZES = 3, /* cluster, jumbo9k, jumbo16k */ 111219392Snp#endif 112275554Snp CL_METADATA_SIZE = CACHE_LINE_SIZE, 113218792Snp 114269411Snp SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / EQ_ESIZE, /* max WR size in desc */ 115276485Snp TX_SGL_SEGS = 39, 116276485Snp TX_SGL_SEGS_TSO = 38, 117346928Snp TX_SGL_SEGS_EO_TSO = 30, /* XXX: lower for IPv6. */ 118218792Snp TX_WR_FLITS = SGE_MAX_WR_LEN / 8 119218792Snp}; 120218792Snp 121218792Snpenum { 122219944Snp /* adapter intr_type */ 123219944Snp INTR_INTX = (1 << 0), 124219944Snp INTR_MSI = (1 << 1), 125219944Snp INTR_MSIX = (1 << 2) 126219944Snp}; 127219944Snp 128219944Snpenum { 129266757Snp XGMAC_MTU = (1 << 0), 130266757Snp XGMAC_PROMISC = (1 << 1), 131266757Snp XGMAC_ALLMULTI = (1 << 2), 132266757Snp XGMAC_VLANEX = (1 << 3), 133266757Snp XGMAC_UCADDR = (1 << 4), 134266757Snp XGMAC_MCADDRS = (1 << 5), 135266757Snp 136266757Snp XGMAC_ALL = 0xffff 137266757Snp}; 138266757Snp 139266757Snpenum { 140245274Snp /* flags understood by begin_synchronized_op */ 141245274Snp HOLD_LOCK = (1 << 0), 142245274Snp SLEEP_OK = (1 << 1), 143245274Snp INTR_OK = (1 << 2), 144245274Snp 145245274Snp /* flags understood by end_synchronized_op */ 146245274Snp LOCK_HELD = HOLD_LOCK, 147245274Snp}; 148245274Snp 149245274Snpenum { 150218792Snp /* adapter flags */ 151218792Snp FULL_INIT_DONE = (1 << 0), 152218792Snp FW_OK = (1 << 1), 153330307Snp CHK_MBOX_ACCESS = (1 << 2), 154228561Snp MASTER_PF = (1 << 3), 155228561Snp ADAP_SYSCTL_CTX = (1 << 4), 156278374Snp /* TOM_INIT_DONE= (1 << 5), No longer used */ 157255050Snp BUF_PACKING_OK = (1 << 6), 158306664Sjhb IS_VF = (1 << 7), 159218792Snp 160218792Snp CXGBE_BUSY = (1 << 9), 161218792Snp 162218792Snp /* port flags */ 163291665Sjhb HAS_TRACEQ = (1 << 3), 164334562Snp FIXED_IFMEDIA = (1 << 4), /* ifmedia list doesn't change. */ 165291665Sjhb 166291665Sjhb /* VI flags */ 167218792Snp DOOMED = (1 << 0), 168291665Sjhb VI_INIT_DONE = (1 << 1), 169291665Sjhb VI_SYSCTL_CTX = (1 << 2), 170284445Snp 171284445Snp /* adapter debug_flags */ 172330307Snp DF_DUMP_MBOX = (1 << 0), /* Log all mbox cmd/rpl. */ 173330307Snp DF_LOAD_FW_ANYTIME = (1 << 1), /* Allow LOAD_FW after init */ 174330307Snp DF_DISABLE_TCB_CACHE = (1 << 2), /* Disable TCB cache (T6+) */ 175218792Snp}; 176218792Snp 177291665Sjhb#define IS_DOOMED(vi) ((vi)->flags & DOOMED) 178291665Sjhb#define SET_DOOMED(vi) do {(vi)->flags |= DOOMED;} while (0) 179245274Snp#define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY) 180245274Snp#define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0) 181245274Snp#define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0) 182218792Snp 183291665Sjhbstruct vi_info { 184218792Snp device_t dev; 185291665Sjhb struct port_info *pi; 186218792Snp 187218792Snp struct ifnet *ifp; 188218792Snp 189218792Snp unsigned long flags; 190218792Snp int if_flags; 191218792Snp 192302110Snp uint16_t *rss, *nm_rss; 193309560Sjhb int smt_idx; /* for convenience */ 194218792Snp uint16_t viid; 195218792Snp int16_t xact_addr_filt;/* index of exact MAC address filter */ 196218792Snp uint16_t rss_size; /* size of VI's RSS table slice */ 197285648Snp uint16_t rss_base; /* start of VI's RSS table slice */ 198218792Snp 199291665Sjhb int nintr; 200291665Sjhb int first_intr; 201291665Sjhb 202218792Snp /* These need to be int as they are used in sysctl */ 203318854Snp int ntxq; /* # of tx queues */ 204318854Snp int first_txq; /* index of first tx queue */ 205318854Snp int rsrv_noflowq; /* Reserve queue 0 for non-flowid packets */ 206318854Snp int nrxq; /* # of rx queues */ 207318854Snp int first_rxq; /* index of first rx queue */ 208228561Snp int nofldtxq; /* # of offload tx queues */ 209228561Snp int first_ofld_txq; /* index of first offload tx queue */ 210228561Snp int nofldrxq; /* # of offload rx queues */ 211228561Snp int first_ofld_rxq; /* index of first offload rx queue */ 212302110Snp int nnmtxq; 213302110Snp int first_nm_txq; 214302110Snp int nnmrxq; 215302110Snp int first_nm_rxq; 216218792Snp int tmr_idx; 217330307Snp int ofld_tmr_idx; 218218792Snp int pktc_idx; 219330307Snp int ofld_pktc_idx; 220218792Snp int qsize_rxq; 221218792Snp int qsize_txq; 222218792Snp 223291665Sjhb struct timeval last_refreshed; 224291665Sjhb struct fw_vi_stats_vf stats; 225291665Sjhb 226291665Sjhb struct callout tick; 227291665Sjhb struct sysctl_ctx_list ctx; /* from ifconfig up to driver detach */ 228291665Sjhb 229291665Sjhb uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */ 230291665Sjhb}; 231291665Sjhb 232318850Snpstruct tx_ch_rl_params { 233318850Snp enum fw_sched_params_rate ratemode; /* %port (REL) or kbps (ABS) */ 234318850Snp uint32_t maxrate; 235318850Snp}; 236318850Snp 237301535Snpenum { 238346871Snp CLRL_USER = (1 << 0), /* allocated manually. */ 239346871Snp CLRL_SYNC = (1 << 1), /* sync hw update in progress. */ 240346871Snp CLRL_ASYNC = (1 << 2), /* async hw update requested. */ 241346871Snp CLRL_ERR = (1 << 3), /* last hw setup ended in error. */ 242301535Snp}; 243301535Snp 244318850Snpstruct tx_cl_rl_params { 245301535Snp int refcount; 246346871Snp uint8_t flags; 247318850Snp enum fw_sched_params_rate ratemode; /* %port REL or ABS value */ 248318850Snp enum fw_sched_params_unit rateunit; /* kbps or pps (when ABS) */ 249318850Snp enum fw_sched_params_mode mode; /* aggr or per-flow */ 250318850Snp uint32_t maxrate; 251318850Snp uint16_t pktsize; 252346871Snp uint16_t burstsize; 253301535Snp}; 254301535Snp 255318850Snp/* Tx scheduler parameters for a channel/port */ 256318850Snpstruct tx_sched_params { 257318850Snp /* Channel Rate Limiter */ 258318850Snp struct tx_ch_rl_params ch_rl; 259318850Snp 260318850Snp /* Class WRR */ 261318850Snp /* XXX */ 262318850Snp 263346871Snp /* Class Rate Limiter (including the default pktsize and burstsize). */ 264346871Snp int pktsize; 265346871Snp int burstsize; 266318850Snp struct tx_cl_rl_params cl_rl[]; 267318850Snp}; 268318850Snp 269291665Sjhbstruct port_info { 270291665Sjhb device_t dev; 271291665Sjhb struct adapter *adapter; 272291665Sjhb 273291665Sjhb struct vi_info *vi; 274291665Sjhb int nvi; 275291665Sjhb int up_vis; 276291665Sjhb int uld_vis; 277291665Sjhb 278318850Snp struct tx_sched_params *sched_params; 279301535Snp 280291665Sjhb struct mtx pi_lock; 281291665Sjhb char lockname[16]; 282291665Sjhb unsigned long flags; 283291665Sjhb 284291665Sjhb uint8_t lport; /* associated offload logical port */ 285291665Sjhb int8_t mdio_addr; 286291665Sjhb uint8_t port_type; 287291665Sjhb uint8_t mod_type; 288291665Sjhb uint8_t port_id; 289291665Sjhb uint8_t tx_chan; 290330307Snp uint8_t mps_bg_map; /* rx MPS buffer group bitmap */ 291330307Snp uint8_t rx_e_chan_map; /* rx TP e-channel bitmap */ 292291665Sjhb 293218792Snp struct link_config link_cfg; 294330307Snp struct ifmedia media; 295218792Snp 296272200Snp struct timeval last_refreshed; 297272200Snp struct port_stats stats; 298272200Snp u_int tnl_cong_drops; 299276485Snp u_int tx_parse_error; 300345664Sjhb u_long tx_tls_records; 301345664Sjhb u_long tx_tls_octets; 302345664Sjhb u_long rx_tls_records; 303345664Sjhb u_long rx_tls_octets; 304272200Snp 305218792Snp struct callout tick; 306218792Snp}; 307218792Snp 308291665Sjhb#define IS_MAIN_VI(vi) ((vi) == &((vi)->pi->vi[0])) 309291665Sjhb 310263317Snp/* Where the cluster came from, how it has been carved up. */ 311263317Snpstruct cluster_layout { 312263317Snp int8_t zidx; 313263317Snp int8_t hwidx; 314263317Snp uint16_t region1; /* mbufs laid out within this region */ 315263317Snp /* region2 is the DMA region */ 316263317Snp uint16_t region3; /* cluster_metadata within this region */ 317263317Snp}; 318263317Snp 319263317Snpstruct cluster_metadata { 320263317Snp u_int refcount; 321263317Snp struct fl_sdesc *sd; /* For debug only. Could easily be stale */ 322218792Snp}; 323218792Snp 324263317Snpstruct fl_sdesc { 325263317Snp caddr_t cl; 326268971Snp uint16_t nmbuf; /* # of driver originated mbufs with ref on cluster */ 327263317Snp struct cluster_layout cll; 328263317Snp}; 329263317Snp 330218792Snpstruct tx_desc { 331218792Snp __be64 flit[8]; 332218792Snp}; 333218792Snp 334218792Snpstruct tx_sdesc { 335276485Snp struct mbuf *m; /* m_nextpkt linked chain of frames */ 336218792Snp uint8_t desc_used; /* # of hardware descriptors used by the WR */ 337218792Snp}; 338218792Snp 339269411Snp 340269411Snp#define IQ_PAD (IQ_ESIZE - sizeof(struct rsp_ctrl) - sizeof(struct rss_header)) 341269411Snpstruct iq_desc { 342269411Snp struct rss_header rss; 343269411Snp uint8_t cpl[IQ_PAD]; 344269411Snp struct rsp_ctrl rsp; 345269411Snp}; 346269411Snp#undef IQ_PAD 347269411SnpCTASSERT(sizeof(struct iq_desc) == IQ_ESIZE); 348269411Snp 349218792Snpenum { 350218792Snp /* iq flags */ 351228561Snp IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */ 352228561Snp IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */ 353330307Snp /* 1 << 2 Used to be IQ_INTR */ 354228561Snp IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */ 355318842Snp IQ_ADJ_CREDIT = (1 << 4), /* hw is off by 1 credit for this iq */ 356220649Snp 357220649Snp /* iq state */ 358220649Snp IQS_DISABLED = 0, 359220649Snp IQS_BUSY = 1, 360220649Snp IQS_IDLE = 2, 361302110Snp 362302110Snp /* netmap related flags */ 363302110Snp NM_OFF = 0, 364302110Snp NM_ON = 1, 365302110Snp NM_BUSY = 2, 366218792Snp}; 367218792Snp 368346852Snpenum { 369346852Snp CPL_COOKIE_RESERVED = 0, 370346852Snp CPL_COOKIE_FILTER, 371346852Snp CPL_COOKIE_DDP0, 372346852Snp CPL_COOKIE_DDP1, 373346852Snp CPL_COOKIE_TOM, 374346855Snp CPL_COOKIE_HASHFILTER, 375346863Snp CPL_COOKIE_ETHOFLD, 376346852Snp CPL_COOKIE_AVAILABLE3, 377346852Snp 378346852Snp NUM_CPL_COOKIES = 8 /* Limited by M_COOKIE. Do not increase. */ 379346852Snp}; 380346852Snp 381302339Snpstruct sge_iq; 382302339Snpstruct rss_header; 383302339Snptypedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *, 384302339Snp struct mbuf *); 385302339Snptypedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *); 386302339Snptypedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *); 387302339Snp 388218792Snp/* 389218792Snp * Ingress Queue: T4 is producer, driver is consumer. 390218792Snp */ 391218792Snpstruct sge_iq { 392219290Snp uint32_t flags; 393228561Snp volatile int state; 394218792Snp struct adapter *adapter; 395269411Snp struct iq_desc *desc; /* KVA of descriptor ring */ 396269411Snp int8_t intr_pktc_idx; /* packet count threshold index */ 397218792Snp uint8_t gen; /* generation bit */ 398218792Snp uint8_t intr_params; /* interrupt holdoff parameters */ 399228561Snp uint8_t intr_next; /* XXX: holdoff for next interrupt */ 400218792Snp uint16_t qsize; /* size (# of entries) of the queue */ 401269411Snp uint16_t sidx; /* index of the entry with the status page */ 402218792Snp uint16_t cidx; /* consumer index */ 403228561Snp uint16_t cntxt_id; /* SGE context id for the iq */ 404269411Snp uint16_t abs_id; /* absolute SGE id for the iq */ 405228561Snp 406228561Snp STAILQ_ENTRY(sge_iq) link; 407269411Snp 408269411Snp bus_dma_tag_t desc_tag; 409269411Snp bus_dmamap_t desc_map; 410269411Snp bus_addr_t ba; /* bus address of descriptor ring */ 411218792Snp}; 412218792Snp 413218792Snpenum { 414228561Snp EQ_CTRL = 1, 415228561Snp EQ_ETH = 2, 416228561Snp EQ_OFLD = 3, 417228561Snp 418218792Snp /* eq flags */ 419276485Snp EQ_TYPEMASK = 0x3, /* 2 lsbits hold the type (see above) */ 420276485Snp EQ_ALLOCATED = (1 << 2), /* firmware resources allocated */ 421276485Snp EQ_ENABLED = (1 << 3), /* open for business */ 422318854Snp EQ_QFLUSH = (1 << 4), /* if_qflush in progress */ 423218792Snp}; 424218792Snp 425248925Snp/* Listed in order of preference. Update t4_sysctls too if you change these */ 426249392Snpenum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB}; 427248925Snp 428218792Snp/* 429218792Snp * Egress Queue: driver is producer, T4 is consumer. 430218792Snp * 431218792Snp * Note: A free list is an egress queue (driver produces the buffers and T4 432218792Snp * consumes them) but it's special enough to have its own struct (see sge_fl). 433218792Snp */ 434218792Snpstruct sge_eq { 435228561Snp unsigned int flags; /* MUST be first */ 436228561Snp unsigned int cntxt_id; /* SGE context id for the eq */ 437306664Sjhb unsigned int abs_id; /* absolute SGE id for the eq */ 438218792Snp struct mtx eq_lock; 439218792Snp 440218792Snp struct tx_desc *desc; /* KVA of descriptor ring */ 441339396Snp uint8_t doorbells; 442248925Snp volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */ 443248925Snp u_int udb_qid; /* relative qid within the doorbell page */ 444276485Snp uint16_t sidx; /* index of the entry with the status page */ 445218792Snp uint16_t cidx; /* consumer idx (desc idx) */ 446218792Snp uint16_t pidx; /* producer idx (desc idx) */ 447276485Snp uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 448276485Snp uint16_t dbidx; /* pidx of the most recent doorbell */ 449219288Snp uint16_t iqid; /* iq that gets egr_update for the eq */ 450228561Snp uint8_t tx_chan; /* tx channel used by the eq */ 451276485Snp volatile u_int equiq; /* EQUIQ outstanding */ 452228561Snp 453276485Snp bus_dma_tag_t desc_tag; 454276485Snp bus_dmamap_t desc_map; 455276485Snp bus_addr_t ba; /* bus address of descriptor ring */ 456276485Snp char lockname[16]; 457220873Snp}; 458218792Snp 459263317Snpstruct sw_zone_info { 460263317Snp uma_zone_t zone; /* zone that this cluster comes from */ 461263317Snp int size; /* size of cluster: 2K, 4K, 9K, 16K, etc. */ 462263317Snp int type; /* EXT_xxx type of the cluster */ 463263317Snp int8_t head_hwidx; 464263317Snp int8_t tail_hwidx; 465255050Snp}; 466255050Snp 467263317Snpstruct hw_buf_info { 468263317Snp int8_t zidx; /* backpointer to zone; -ve means unused */ 469263317Snp int8_t next; /* next hwidx for this zone; -1 means no more */ 470263317Snp int size; 471263317Snp}; 472263317Snp 473228561Snpenum { 474296603Snp NUM_MEMWIN = 3, 475296603Snp 476296603Snp MEMWIN0_APERTURE = 2048, 477296603Snp MEMWIN0_BASE = 0x1b800, 478296603Snp 479296603Snp MEMWIN1_APERTURE = 32768, 480296603Snp MEMWIN1_BASE = 0x28000, 481296603Snp 482296603Snp MEMWIN2_APERTURE_T4 = 65536, 483296603Snp MEMWIN2_BASE_T4 = 0x30000, 484296603Snp 485296603Snp MEMWIN2_APERTURE_T5 = 128 * 1024, 486296603Snp MEMWIN2_BASE_T5 = 0x60000, 487296603Snp}; 488296603Snp 489296603Snpstruct memwin { 490296603Snp struct rwlock mw_lock __aligned(CACHE_LINE_SIZE); 491296603Snp uint32_t mw_base; /* constant after setup_memwin */ 492296603Snp uint32_t mw_aperture; /* ditto */ 493296603Snp uint32_t mw_curpos; /* protected by mw_lock */ 494296603Snp}; 495296603Snp 496296603Snpenum { 497228561Snp FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */ 498228561Snp FL_DOOMED = (1 << 1), /* about to be destroyed */ 499255050Snp FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */ 500269428Snp FL_BUF_RESUME = (1 << 3), /* resume from the middle of the frame */ 501228561Snp}; 502228561Snp 503269428Snp#define FL_RUNNING_LOW(fl) \ 504269428Snp (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) <= fl->lowat) 505269428Snp#define FL_NOT_RUNNING_LOW(fl) \ 506269428Snp (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) >= 2 * fl->lowat) 507228561Snp 508218792Snpstruct sge_fl { 509218792Snp struct mtx fl_lock; 510218792Snp __be64 *desc; /* KVA of descriptor ring, ptr to addresses */ 511218792Snp struct fl_sdesc *sdesc; /* KVA of software descriptor ring */ 512269428Snp struct cluster_layout cll_def; /* default refill zone, layout */ 513269428Snp uint16_t lowat; /* # of buffers <= this means fl needs help */ 514269428Snp int flags; 515269428Snp uint16_t buf_boundary; 516263317Snp 517269428Snp /* The 16b idx all deal with hw descriptors */ 518269428Snp uint16_t dbidx; /* hw pidx after last doorbell */ 519269428Snp uint16_t sidx; /* index of status page */ 520269428Snp volatile uint16_t hw_cidx; 521263317Snp 522269428Snp /* The 32b idx are all buffer idx, not hardware descriptor idx */ 523269428Snp uint32_t cidx; /* consumer index */ 524269428Snp uint32_t pidx; /* producer index */ 525269428Snp 526269428Snp uint32_t dbval; 527269428Snp u_int rx_offset; /* offset in fl buf (when buffer packing) */ 528269428Snp volatile uint32_t *udb; 529269428Snp 530263317Snp uint64_t mbuf_allocated;/* # of mbuf allocated from zone_mbuf */ 531263317Snp uint64_t mbuf_inlined; /* # of mbuf created within clusters */ 532263317Snp uint64_t cl_allocated; /* # of clusters allocated */ 533263317Snp uint64_t cl_recycled; /* # of clusters recycled */ 534263317Snp uint64_t cl_fast_recycled; /* # of clusters recycled (fast) */ 535269428Snp 536269428Snp /* These 3 are valid when FL_BUF_RESUME is set, stale otherwise. */ 537269428Snp struct mbuf *m0; 538269428Snp struct mbuf **pnext; 539269428Snp u_int remaining; 540269428Snp 541269428Snp uint16_t qsize; /* # of hw descriptors (status page included) */ 542269428Snp uint16_t cntxt_id; /* SGE context id for the freelist */ 543269428Snp TAILQ_ENTRY(sge_fl) link; /* All starving freelists */ 544269428Snp bus_dma_tag_t desc_tag; 545269428Snp bus_dmamap_t desc_map; 546269428Snp char lockname[16]; 547269428Snp bus_addr_t ba; /* bus address of descriptor ring */ 548269428Snp struct cluster_layout cll_alt; /* alternate refill zone, layout */ 549218792Snp}; 550218792Snp 551276485Snpstruct mp_ring; 552276485Snp 553220873Snp/* txq: SGE egress queue + what's needed for Ethernet NIC */ 554218792Snpstruct sge_txq { 555218792Snp struct sge_eq eq; /* MUST be first */ 556220873Snp 557220873Snp struct ifnet *ifp; /* the interface this txq belongs to */ 558276485Snp struct mp_ring *r; /* tx software ring */ 559220873Snp struct tx_sdesc *sdesc; /* KVA of software descriptor ring */ 560276485Snp struct sglist *gl; 561276485Snp __be32 cpl_ctrl0; /* for convenience */ 562301628Snp int tc_idx; /* traffic class */ 563218792Snp 564276485Snp struct task tx_reclaim_task; 565218792Snp /* stats for common events first */ 566218792Snp 567218792Snp uint64_t txcsum; /* # of times hardware assisted with checksum */ 568237819Snp uint64_t tso_wrs; /* # of TSO work requests */ 569218792Snp uint64_t vlan_insertion;/* # of times VLAN tag was inserted */ 570218792Snp uint64_t imm_wrs; /* # of work requests with immediate data */ 571218792Snp uint64_t sgl_wrs; /* # of work requests with direct SGL */ 572218792Snp uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */ 573276485Snp uint64_t txpkts0_wrs; /* # of type0 coalesced tx work requests */ 574276485Snp uint64_t txpkts1_wrs; /* # of type1 coalesced tx work requests */ 575276485Snp uint64_t txpkts0_pkts; /* # of frames in type0 coalesced tx WRs */ 576276485Snp uint64_t txpkts1_pkts; /* # of frames in type1 coalesced tx WRs */ 577218792Snp 578218792Snp /* stats for not-that-common events */ 579220873Snp} __aligned(CACHE_LINE_SIZE); 580218792Snp 581218792Snp/* rxq: SGE ingress queue + SGE free list + miscellaneous items */ 582218792Snpstruct sge_rxq { 583218792Snp struct sge_iq iq; /* MUST be first */ 584228561Snp struct sge_fl fl; /* MUST follow iq */ 585218792Snp 586219290Snp struct ifnet *ifp; /* the interface this rxq belongs to */ 587237819Snp#if defined(INET) || defined(INET6) 588218792Snp struct lro_ctrl lro; /* LRO state */ 589219290Snp#endif 590218792Snp 591218792Snp /* stats for common events first */ 592218792Snp 593218792Snp uint64_t rxcsum; /* # of times hardware assisted with checksum */ 594218792Snp uint64_t vlan_extraction;/* # of times VLAN tag was extracted */ 595218792Snp 596218792Snp /* stats for not-that-common events */ 597218792Snp 598218792Snp} __aligned(CACHE_LINE_SIZE); 599218792Snp 600237263Snpstatic inline struct sge_rxq * 601237263Snpiq_to_rxq(struct sge_iq *iq) 602237263Snp{ 603237263Snp 604241733Sed return (__containerof(iq, struct sge_rxq, iq)); 605237263Snp} 606237263Snp 607237263Snp 608228561Snp/* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */ 609228561Snpstruct sge_ofld_rxq { 610228561Snp struct sge_iq iq; /* MUST be first */ 611228561Snp struct sge_fl fl; /* MUST follow iq */ 612228561Snp} __aligned(CACHE_LINE_SIZE); 613237263Snp 614237263Snpstatic inline struct sge_ofld_rxq * 615237263Snpiq_to_ofld_rxq(struct sge_iq *iq) 616237263Snp{ 617237263Snp 618241733Sed return (__containerof(iq, struct sge_ofld_rxq, iq)); 619237263Snp} 620228561Snp 621237263Snpstruct wrqe { 622237263Snp STAILQ_ENTRY(wrqe) link; 623237263Snp struct sge_wrq *wrq; 624237263Snp int wr_len; 625276485Snp char wr[] __aligned(16); 626237263Snp}; 627237263Snp 628276485Snpstruct wrq_cookie { 629276485Snp TAILQ_ENTRY(wrq_cookie) link; 630276485Snp int ndesc; 631276485Snp int pidx; 632276485Snp}; 633276485Snp 634228561Snp/* 635228561Snp * wrq: SGE egress queue that is given prebuilt work requests. Both the control 636228561Snp * and offload tx queues are of this type. 637228561Snp */ 638228561Snpstruct sge_wrq { 639220873Snp struct sge_eq eq; /* MUST be first */ 640220873Snp 641228561Snp struct adapter *adapter; 642276485Snp struct task wrq_tx_task; 643228561Snp 644276485Snp /* Tx desc reserved but WR not "committed" yet. */ 645276485Snp TAILQ_HEAD(wrq_incomplete_wrs , wrq_cookie) incomplete_wrs; 646276485Snp 647276485Snp /* List of WRs ready to go out as soon as descriptors are available. */ 648237263Snp STAILQ_HEAD(, wrqe) wr_list; 649276485Snp u_int nwr_pending; 650276485Snp u_int ndesc_needed; 651237263Snp 652220873Snp /* stats for common events first */ 653220873Snp 654276485Snp uint64_t tx_wrs_direct; /* # of WRs written directly to desc ring. */ 655276485Snp uint64_t tx_wrs_ss; /* # of WRs copied from scratch space. */ 656276485Snp uint64_t tx_wrs_copied; /* # of WRs queued and copied to desc ring. */ 657220873Snp 658220873Snp /* stats for not-that-common events */ 659220873Snp 660276485Snp /* 661276485Snp * Scratch space for work requests that wrap around after reaching the 662298955Spfg * status page, and some information about the last WR that used it. 663276485Snp */ 664276485Snp uint16_t ss_pidx; 665276485Snp uint16_t ss_len; 666276485Snp uint8_t ss[SGE_MAX_WR_LEN]; 667276485Snp 668220873Snp} __aligned(CACHE_LINE_SIZE); 669220873Snp 670266757Snp 671266757Snpstruct sge_nm_rxq { 672346875Snp volatile int nm_state; /* NM_OFF, NM_ON, or NM_BUSY */ 673291665Sjhb struct vi_info *vi; 674266757Snp 675269411Snp struct iq_desc *iq_desc; 676266757Snp uint16_t iq_abs_id; 677266757Snp uint16_t iq_cntxt_id; 678266757Snp uint16_t iq_cidx; 679266757Snp uint16_t iq_sidx; 680266757Snp uint8_t iq_gen; 681266757Snp 682266757Snp __be64 *fl_desc; 683266757Snp uint16_t fl_cntxt_id; 684266757Snp uint32_t fl_cidx; 685266757Snp uint32_t fl_pidx; 686266757Snp uint32_t fl_sidx; 687266757Snp uint32_t fl_db_val; 688266757Snp u_int fl_hwidx:4; 689266757Snp 690266757Snp u_int nid; /* netmap ring # for this queue */ 691266757Snp 692266757Snp /* infrequently used items after this */ 693266757Snp 694266757Snp bus_dma_tag_t iq_desc_tag; 695266757Snp bus_dmamap_t iq_desc_map; 696266757Snp bus_addr_t iq_ba; 697266757Snp int intr_idx; 698266757Snp 699266757Snp bus_dma_tag_t fl_desc_tag; 700266757Snp bus_dmamap_t fl_desc_map; 701266757Snp bus_addr_t fl_ba; 702266757Snp} __aligned(CACHE_LINE_SIZE); 703266757Snp 704266757Snpstruct sge_nm_txq { 705266757Snp struct tx_desc *desc; 706266757Snp uint16_t cidx; 707266757Snp uint16_t pidx; 708266757Snp uint16_t sidx; 709266757Snp uint16_t equiqidx; /* EQUIQ last requested at this pidx */ 710266757Snp uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 711266757Snp uint16_t dbidx; /* pidx of the most recent doorbell */ 712339396Snp uint8_t doorbells; 713266757Snp volatile uint32_t *udb; 714266757Snp u_int udb_qid; 715266757Snp u_int cntxt_id; 716266757Snp __be32 cpl_ctrl0; /* for convenience */ 717266757Snp u_int nid; /* netmap ring # for this queue */ 718266757Snp 719266757Snp /* infrequently used items after this */ 720266757Snp 721266757Snp bus_dma_tag_t desc_tag; 722266757Snp bus_dmamap_t desc_map; 723266757Snp bus_addr_t ba; 724266757Snp int iqidx; 725266757Snp} __aligned(CACHE_LINE_SIZE); 726266757Snp 727218792Snpstruct sge { 728228561Snp int nrxq; /* total # of Ethernet rx queues */ 729318854Snp int ntxq; /* total # of Ethernet tx queues */ 730228561Snp int nofldrxq; /* total # of TOE rx queues */ 731228561Snp int nofldtxq; /* total # of TOE tx queues */ 732266757Snp int nnmrxq; /* total # of netmap rx queues */ 733266757Snp int nnmtxq; /* total # of netmap tx queues */ 734228561Snp int niq; /* total # of ingress queues */ 735228561Snp int neq; /* total # of egress queues */ 736218792Snp 737218792Snp struct sge_iq fwq; /* Firmware event queue */ 738228561Snp struct sge_wrq *ctrlq; /* Control queues */ 739218792Snp struct sge_txq *txq; /* NIC tx queues */ 740218792Snp struct sge_rxq *rxq; /* NIC rx queues */ 741228561Snp struct sge_wrq *ofld_txq; /* TOE tx queues */ 742228561Snp struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */ 743266757Snp struct sge_nm_txq *nm_txq; /* netmap tx queues */ 744266757Snp struct sge_nm_rxq *nm_rxq; /* netmap rx queues */ 745218792Snp 746306664Sjhb uint16_t iq_start; /* first cntxt_id */ 747306664Sjhb uint16_t iq_base; /* first abs_id */ 748306664Sjhb int eq_start; /* first cntxt_id */ 749306664Sjhb int eq_base; /* first abs_id */ 750218792Snp struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */ 751218792Snp struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */ 752255050Snp 753263317Snp int8_t safe_hwidx1; /* may not have room for metadata */ 754263317Snp int8_t safe_hwidx2; /* with room for metadata and maybe more */ 755263317Snp struct sw_zone_info sw_zone_info[SW_ZONE_SIZES]; 756263317Snp struct hw_buf_info hw_buf_info[SGE_FLBUF_SIZES]; 757218792Snp}; 758218792Snp 759309560Sjhbstruct devnames { 760309560Sjhb const char *nexus_name; 761309560Sjhb const char *ifnet_name; 762309560Sjhb const char *vi_ifnet_name; 763309560Sjhb const char *pf03_drv_name; 764309560Sjhb const char *vf_nexus_name; 765309560Sjhb const char *vf_ifnet_name; 766309560Sjhb}; 767309560Sjhb 768346934Snpstruct clip_entry; 769346934Snp 770218792Snpstruct adapter { 771228561Snp SLIST_ENTRY(adapter) link; 772218792Snp device_t dev; 773218792Snp struct cdev *cdev; 774309560Sjhb const struct devnames *names; 775218792Snp 776218792Snp /* PCIe register resources */ 777218792Snp int regs_rid; 778218792Snp struct resource *regs_res; 779218792Snp int msix_rid; 780218792Snp struct resource *msix_res; 781218792Snp bus_space_handle_t bh; 782218792Snp bus_space_tag_t bt; 783218792Snp bus_size_t mmio_len; 784248925Snp int udbs_rid; 785248925Snp struct resource *udbs_res; 786248925Snp volatile uint8_t *udbs_base; 787218792Snp 788218792Snp unsigned int pf; 789218792Snp unsigned int mbox; 790296489Snp unsigned int vpd_busy; 791296489Snp unsigned int vpd_flag; 792218792Snp 793218792Snp /* Interrupt information */ 794218792Snp int intr_type; 795218792Snp int intr_count; 796218792Snp struct irq { 797218792Snp struct resource *res; 798218792Snp int rid; 799218792Snp void *tag; 800302110Snp struct sge_rxq *rxq; 801302110Snp struct sge_nm_rxq *nm_rxq; 802302110Snp } __aligned(CACHE_LINE_SIZE) *irq; 803306664Sjhb int sge_gts_reg; 804306664Sjhb int sge_kdoorbell_reg; 805218792Snp 806218792Snp bus_dma_tag_t dmat; /* Parent DMA tag */ 807218792Snp 808218792Snp struct sge sge; 809255015Snp int lro_timeout; 810302339Snp int sc_do_rxcopy; 811218792Snp 812296383Snp struct taskqueue *tq[MAX_NCHAN]; /* General purpose taskqueues */ 813218792Snp struct port_info *port[MAX_NPORTS]; 814330307Snp uint8_t chan_map[MAX_NCHAN]; /* channel -> port */ 815218792Snp 816346934Snp struct mtx clip_table_lock; 817346934Snp TAILQ_HEAD(, clip_entry) clip_table; 818346934Snp int clip_gen; 819346934Snp 820237263Snp void *tom_softc; /* (struct tom_data *) */ 821228561Snp struct tom_tunables tt; 822346805Snp struct t4_offload_policy *policy; 823346805Snp struct rwlock policy_lock; 824346805Snp 825346805Snp void *iwarp_softc; /* (struct c4iw_dev *) */ 826331769Shselasky struct iw_tunables iwt; 827292736Snp void *iscsi_ulp_softc; /* (struct cxgbei_data *) */ 828345040Sjhb void *ccr_softc; /* (struct ccr_softc *) */ 829222509Snp struct l2t_data *l2t; /* L2 table */ 830346855Snp struct smt_data *smt; /* Source MAC Table */ 831218792Snp struct tid_info tids; 832345664Sjhb vmem_t *key_map; 833218792Snp 834339396Snp uint8_t doorbells; 835278374Snp int offload_map; /* ports with IFCAP_TOE enabled */ 836278374Snp int active_ulds; /* ULDs activated on this adapter */ 837218792Snp int flags; 838284445Snp int debug_flags; 839218792Snp 840253691Snp char ifp_lockname[16]; 841253691Snp struct mtx ifp_lock; 842253691Snp struct ifnet *ifp; /* tracer ifp */ 843253691Snp struct ifmedia media; 844253691Snp int traceq; /* iq used by all tracers, -1 if none */ 845253691Snp int tracer_valid; /* bitmap of valid tracers */ 846253691Snp int tracer_enabled; /* bitmap of enabled tracers */ 847253691Snp 848296641Snp char fw_version[16]; 849296641Snp char tp_version[16]; 850309458Sjhb char er_version[16]; 851309458Sjhb char bs_version[16]; 852245936Snp char cfg_file[32]; 853245936Snp u_int cfcsum; 854218792Snp struct adapter_params params; 855296383Snp const struct chip_params *chip_params; 856218792Snp struct t4_virt_res vres; 857218792Snp 858296710Snp uint16_t nbmcaps; 859228561Snp uint16_t linkcaps; 860296710Snp uint16_t switchcaps; 861228561Snp uint16_t niccaps; 862228561Snp uint16_t toecaps; 863228561Snp uint16_t rdmacaps; 864309560Sjhb uint16_t cryptocaps; 865228561Snp uint16_t iscsicaps; 866228561Snp uint16_t fcoecaps; 867220873Snp 868228561Snp struct sysctl_ctx_list ctx; /* from adapter_full_init to full_uninit */ 869228561Snp 870218792Snp struct mtx sc_lock; 871218792Snp char lockname[16]; 872228561Snp 873228561Snp /* Starving free lists */ 874228561Snp struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */ 875228561Snp TAILQ_HEAD(, sge_fl) sfl; 876228561Snp struct callout sfl_callout; 877228561Snp 878296552Snp struct mtx reg_lock; /* for indirect register access */ 879272200Snp 880296603Snp struct memwin memwin[NUM_MEMWIN]; /* memory windows */ 881296603Snp 882318850Snp struct mtx tc_lock; 883318850Snp struct task tc_task; 884318850Snp 885245274Snp const char *last_op; 886245274Snp const void *last_op_thr; 887286926Snp int last_op_flags; 888218792Snp}; 889218792Snp 890218792Snp#define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock) 891218792Snp#define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock) 892218792Snp#define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED) 893218792Snp#define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED) 894218792Snp 895245274Snp#define ASSERT_SYNCHRONIZED_OP(sc) \ 896245274Snp KASSERT(IS_BUSY(sc) && \ 897245274Snp (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \ 898245274Snp ("%s: operation not synchronized.", __func__)) 899245274Snp 900218792Snp#define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock) 901218792Snp#define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock) 902218792Snp#define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED) 903218792Snp#define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED) 904218792Snp 905218792Snp#define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock) 906218792Snp#define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock) 907218792Snp#define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock) 908218792Snp#define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED) 909218792Snp#define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED) 910218792Snp 911218792Snp#define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl) 912218792Snp#define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl) 913218792Snp#define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl) 914218792Snp#define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl) 915218792Snp 916218792Snp#define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock) 917218792Snp#define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock) 918218792Snp#define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock) 919218792Snp#define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED) 920218792Snp#define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED) 921218792Snp 922218792Snp#define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq) 923218792Snp#define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq) 924218792Snp#define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq) 925218792Snp#define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq) 926218792Snp#define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq) 927218792Snp 928284445Snp#define CH_DUMP_MBOX(sc, mbox, data_reg) \ 929284445Snp do { \ 930284445Snp if (sc->debug_flags & DF_DUMP_MBOX) { \ 931284445Snp log(LOG_NOTICE, \ 932284445Snp "%s mbox %u: %016llx %016llx %016llx %016llx " \ 933284445Snp "%016llx %016llx %016llx %016llx\n", \ 934284445Snp device_get_nameunit(sc->dev), mbox, \ 935284445Snp (unsigned long long)t4_read_reg64(sc, data_reg), \ 936284445Snp (unsigned long long)t4_read_reg64(sc, data_reg + 8), \ 937284445Snp (unsigned long long)t4_read_reg64(sc, data_reg + 16), \ 938284445Snp (unsigned long long)t4_read_reg64(sc, data_reg + 24), \ 939284445Snp (unsigned long long)t4_read_reg64(sc, data_reg + 32), \ 940284445Snp (unsigned long long)t4_read_reg64(sc, data_reg + 40), \ 941284445Snp (unsigned long long)t4_read_reg64(sc, data_reg + 48), \ 942284445Snp (unsigned long long)t4_read_reg64(sc, data_reg + 56)); \ 943284445Snp } \ 944284445Snp } while (0) 945284445Snp 946291665Sjhb#define for_each_txq(vi, iter, q) \ 947291665Sjhb for (q = &vi->pi->adapter->sge.txq[vi->first_txq], iter = 0; \ 948291665Sjhb iter < vi->ntxq; ++iter, ++q) 949291665Sjhb#define for_each_rxq(vi, iter, q) \ 950291665Sjhb for (q = &vi->pi->adapter->sge.rxq[vi->first_rxq], iter = 0; \ 951291665Sjhb iter < vi->nrxq; ++iter, ++q) 952291665Sjhb#define for_each_ofld_txq(vi, iter, q) \ 953291665Sjhb for (q = &vi->pi->adapter->sge.ofld_txq[vi->first_ofld_txq], iter = 0; \ 954291665Sjhb iter < vi->nofldtxq; ++iter, ++q) 955291665Sjhb#define for_each_ofld_rxq(vi, iter, q) \ 956291665Sjhb for (q = &vi->pi->adapter->sge.ofld_rxq[vi->first_ofld_rxq], iter = 0; \ 957291665Sjhb iter < vi->nofldrxq; ++iter, ++q) 958291665Sjhb#define for_each_nm_txq(vi, iter, q) \ 959302110Snp for (q = &vi->pi->adapter->sge.nm_txq[vi->first_nm_txq], iter = 0; \ 960302110Snp iter < vi->nnmtxq; ++iter, ++q) 961291665Sjhb#define for_each_nm_rxq(vi, iter, q) \ 962302110Snp for (q = &vi->pi->adapter->sge.nm_rxq[vi->first_nm_rxq], iter = 0; \ 963302110Snp iter < vi->nnmrxq; ++iter, ++q) 964291665Sjhb#define for_each_vi(_pi, _iter, _vi) \ 965291665Sjhb for ((_vi) = (_pi)->vi, (_iter) = 0; (_iter) < (_pi)->nvi; \ 966291665Sjhb ++(_iter), ++(_vi)) 967218792Snp 968269428Snp#define IDXINCR(idx, incr, wrap) do { \ 969269428Snp idx = wrap - idx > incr ? idx + incr : incr - (wrap - idx); \ 970269411Snp} while (0) 971269411Snp#define IDXDIFF(head, tail, wrap) \ 972269428Snp ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 973269411Snp 974222510Snp/* One for errors, one for firmware events */ 975222510Snp#define T4_EXTRA_INTR 2 976218792Snp 977306664Sjhb/* One for firmware events */ 978306664Sjhb#define T4VF_EXTRA_INTR 1 979306664Sjhb 980330307Snpstatic inline int 981330307Snpforwarding_intr_to_fwq(struct adapter *sc) 982330307Snp{ 983330307Snp 984330307Snp return (sc->intr_count == 1); 985330307Snp} 986330307Snp 987218792Snpstatic inline uint32_t 988218792Snpt4_read_reg(struct adapter *sc, uint32_t reg) 989218792Snp{ 990237263Snp 991218792Snp return bus_space_read_4(sc->bt, sc->bh, reg); 992218792Snp} 993218792Snp 994218792Snpstatic inline void 995218792Snpt4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val) 996218792Snp{ 997237263Snp 998218792Snp bus_space_write_4(sc->bt, sc->bh, reg, val); 999218792Snp} 1000218792Snp 1001218792Snpstatic inline uint64_t 1002218792Snpt4_read_reg64(struct adapter *sc, uint32_t reg) 1003218792Snp{ 1004237263Snp 1005311260Snp#ifdef __LP64__ 1006311260Snp return bus_space_read_8(sc->bt, sc->bh, reg); 1007311260Snp#else 1008311260Snp return (uint64_t)bus_space_read_4(sc->bt, sc->bh, reg) + 1009311260Snp ((uint64_t)bus_space_read_4(sc->bt, sc->bh, reg + 4) << 32); 1010311260Snp 1011311260Snp#endif 1012218792Snp} 1013218792Snp 1014218792Snpstatic inline void 1015218792Snpt4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val) 1016218792Snp{ 1017237263Snp 1018311260Snp#ifdef __LP64__ 1019311260Snp bus_space_write_8(sc->bt, sc->bh, reg, val); 1020311260Snp#else 1021311260Snp bus_space_write_4(sc->bt, sc->bh, reg, val); 1022311260Snp bus_space_write_4(sc->bt, sc->bh, reg + 4, val>> 32); 1023311260Snp#endif 1024218792Snp} 1025218792Snp 1026218792Snpstatic inline void 1027218792Snpt4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val) 1028218792Snp{ 1029237263Snp 1030218792Snp *val = pci_read_config(sc->dev, reg, 1); 1031218792Snp} 1032218792Snp 1033218792Snpstatic inline void 1034218792Snpt4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val) 1035218792Snp{ 1036237263Snp 1037218792Snp pci_write_config(sc->dev, reg, val, 1); 1038218792Snp} 1039218792Snp 1040218792Snpstatic inline void 1041218792Snpt4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val) 1042218792Snp{ 1043237263Snp 1044218792Snp *val = pci_read_config(sc->dev, reg, 2); 1045218792Snp} 1046218792Snp 1047218792Snpstatic inline void 1048218792Snpt4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val) 1049218792Snp{ 1050237263Snp 1051218792Snp pci_write_config(sc->dev, reg, val, 2); 1052218792Snp} 1053218792Snp 1054218792Snpstatic inline void 1055218792Snpt4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val) 1056218792Snp{ 1057237263Snp 1058218792Snp *val = pci_read_config(sc->dev, reg, 4); 1059218792Snp} 1060218792Snp 1061218792Snpstatic inline void 1062218792Snpt4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val) 1063218792Snp{ 1064237263Snp 1065218792Snp pci_write_config(sc->dev, reg, val, 4); 1066218792Snp} 1067218792Snp 1068218792Snpstatic inline struct port_info * 1069218792Snpadap2pinfo(struct adapter *sc, int idx) 1070218792Snp{ 1071237263Snp 1072218792Snp return (sc->port[idx]); 1073218792Snp} 1074218792Snp 1075218792Snpstatic inline void 1076330307Snpt4_os_set_hw_addr(struct port_info *pi, uint8_t hw_addr[]) 1077218792Snp{ 1078237263Snp 1079330307Snp bcopy(hw_addr, pi->vi[0].hw_addr, ETHER_ADDR_LEN); 1080218792Snp} 1081218792Snp 1082248925Snpstatic inline int 1083248925Snptx_resume_threshold(struct sge_eq *eq) 1084228561Snp{ 1085237263Snp 1086276485Snp /* not quite the same as qsize / 4, but this will do. */ 1087276485Snp return (eq->sidx / 4); 1088228561Snp} 1089228561Snp 1090296481Snpstatic inline int 1091296481Snpt4_use_ldst(struct adapter *sc) 1092296481Snp{ 1093296481Snp 1094296481Snp#ifdef notyet 1095296481Snp return (sc->flags & FW_OK || !sc->use_bd); 1096296481Snp#else 1097296481Snp return (0); 1098296481Snp#endif 1099296481Snp} 1100296481Snp 1101219286Snp/* t4_main.c */ 1102330307Snpextern int t4_ntxq; 1103330307Snpextern int t4_nrxq; 1104306664Sjhbextern int t4_intr_types; 1105330307Snpextern int t4_tmr_idx; 1106330307Snpextern int t4_pktc_idx; 1107306664Sjhbextern unsigned int t4_qsize_rxq; 1108306664Sjhbextern unsigned int t4_qsize_txq; 1109306664Sjhbextern device_method_t cxgbe_methods[]; 1110306664Sjhb 1111218792Snpint t4_os_find_pci_capability(struct adapter *, int); 1112218792Snpint t4_os_pci_save_state(struct adapter *); 1113218792Snpint t4_os_pci_restore_state(struct adapter *); 1114330307Snpvoid t4_os_portmod_changed(struct port_info *); 1115330307Snpvoid t4_os_link_changed(struct port_info *); 1116228561Snpvoid t4_iterate(void (*)(struct adapter *, void *), void *); 1117309560Sjhbvoid t4_init_devnames(struct adapter *); 1118306664Sjhbvoid t4_add_adapter(struct adapter *); 1119345664Sjhbvoid t4_aes_getdeckey(void *, const void *, unsigned int); 1120306664Sjhbint t4_detach_common(device_t); 1121306664Sjhbint t4_map_bars_0_and_4(struct adapter *); 1122306664Sjhbint t4_map_bar_2(struct adapter *); 1123306664Sjhbint t4_setup_intr_handlers(struct adapter *); 1124306664Sjhbvoid t4_sysctls(struct adapter *); 1125291665Sjhbint begin_synchronized_op(struct adapter *, struct vi_info *, int, char *); 1126291665Sjhbvoid doom_vi(struct adapter *, struct vi_info *); 1127245274Snpvoid end_synchronized_op(struct adapter *, int); 1128266757Snpint update_mac_settings(struct ifnet *, int); 1129266757Snpint adapter_full_init(struct adapter *); 1130266757Snpint adapter_full_uninit(struct adapter *); 1131291665Sjhbuint64_t cxgbe_get_counter(struct ifnet *, ift_counter); 1132291665Sjhbint vi_full_init(struct vi_info *); 1133291665Sjhbint vi_full_uninit(struct vi_info *); 1134291665Sjhbvoid vi_sysctls(struct vi_info *); 1135291665Sjhbvoid vi_tick(void *); 1136346848Snpint rw_via_memwin(struct adapter *, int, uint32_t, uint32_t *, int, int); 1137346849Snpint alloc_atid_tab(struct tid_info *, int); 1138346849Snpvoid free_atid_tab(struct tid_info *); 1139346849Snpint alloc_atid(struct adapter *, void *); 1140346849Snpvoid *lookup_atid(struct adapter *, int); 1141346849Snpvoid free_atid(struct adapter *, int); 1142346850Snpvoid release_tid(struct adapter *, int, struct sge_wrq *); 1143346883Snpint cxgbe_media_change(struct ifnet *); 1144346883Snpvoid cxgbe_media_status(struct ifnet *, struct ifmediareq *); 1145218792Snp 1146266757Snp#ifdef DEV_NETMAP 1147266757Snp/* t4_netmap.c */ 1148346875Snpstruct sge_nm_rxq; 1149302110Snpvoid cxgbe_nm_attach(struct vi_info *); 1150302110Snpvoid cxgbe_nm_detach(struct vi_info *); 1151346875Snpvoid service_nm_rxq(struct sge_nm_rxq *); 1152266757Snp#endif 1153266757Snp 1154219286Snp/* t4_sge.c */ 1155219392Snpvoid t4_sge_modload(void); 1156269032Snpvoid t4_sge_modunload(void); 1157269032Snpuint64_t t4_sge_extfree_refs(void); 1158248925Snpvoid t4_tweak_chip_settings(struct adapter *); 1159248925Snpint t4_read_chip_settings(struct adapter *); 1160218792Snpint t4_create_dma_tag(struct adapter *); 1161253829Snpvoid t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *, 1162253829Snp struct sysctl_oid_list *); 1163218792Snpint t4_destroy_dma_tag(struct adapter *); 1164220873Snpint t4_setup_adapter_queues(struct adapter *); 1165220873Snpint t4_teardown_adapter_queues(struct adapter *); 1166291665Sjhbint t4_setup_vi_queues(struct vi_info *); 1167291665Sjhbint t4_teardown_vi_queues(struct vi_info *); 1168218792Snpvoid t4_intr_all(void *); 1169222510Snpvoid t4_intr(void *); 1170346875Snp#ifdef DEV_NETMAP 1171346875Snpvoid t4_nm_intr(void *); 1172302110Snpvoid t4_vi_intr(void *); 1173346875Snp#endif 1174218792Snpvoid t4_intr_err(void *); 1175218792Snpvoid t4_intr_evt(void *); 1176237263Snpvoid t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *); 1177218792Snpvoid t4_update_fl_bufsize(struct ifnet *); 1178306664Sjhbint parse_pkt(struct adapter *, struct mbuf **); 1179276485Snpvoid *start_wrq_wr(struct sge_wrq *, int, struct wrq_cookie *); 1180276485Snpvoid commit_wrq_wr(struct sge_wrq *, void *, struct wrq_cookie *); 1181285221Snpint tnl_cong(struct port_info *, int); 1182346852Snpvoid t4_register_an_handler(an_handler_t); 1183346852Snpvoid t4_register_fw_msg_handler(int, fw_msg_handler_t); 1184346852Snpvoid t4_register_cpl_handler(int, cpl_handler_t); 1185346852Snpvoid t4_register_shared_cpl_handler(int, cpl_handler_t, int); 1186218792Snp 1187253691Snp/* t4_tracer.c */ 1188253691Snpstruct t4_tracer; 1189253691Snpvoid t4_tracer_modload(void); 1190253691Snpvoid t4_tracer_modunload(void); 1191253691Snpvoid t4_tracer_port_detach(struct adapter *); 1192253691Snpint t4_get_tracer(struct adapter *, struct t4_tracer *); 1193253691Snpint t4_set_tracer(struct adapter *, struct t4_tracer *); 1194253691Snpint t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1195253691Snpint t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1196253691Snp 1197318850Snp/* t4_sched.c */ 1198318850Snpint t4_set_sched_class(struct adapter *, struct t4_sched_params *); 1199318850Snpint t4_set_sched_queue(struct adapter *, struct t4_sched_queue *); 1200318850Snpint t4_init_tx_sched(struct adapter *); 1201318850Snpint t4_free_tx_sched(struct adapter *); 1202318850Snpvoid t4_update_tx_sched(struct adapter *); 1203318850Snpint t4_reserve_cl_rl_kbps(struct adapter *, int, u_int, int *); 1204346871Snpvoid t4_release_cl_rl(struct adapter *, int, int); 1205346871Snpint sysctl_tc(SYSCTL_HANDLER_ARGS); 1206346871Snpint sysctl_tc_params(SYSCTL_HANDLER_ARGS); 1207318850Snp 1208346855Snp/* t4_filter.c */ 1209346855Snpint get_filter_mode(struct adapter *, uint32_t *); 1210346855Snpint set_filter_mode(struct adapter *, uint32_t); 1211346855Snpint get_filter(struct adapter *, struct t4_filter *); 1212346855Snpint set_filter(struct adapter *, struct t4_filter *); 1213346855Snpint del_filter(struct adapter *, struct t4_filter *); 1214346855Snpint t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1215346855Snpint t4_hashfilter_ao_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1216346855Snpint t4_hashfilter_tcb_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1217346855Snpint t4_del_hashfilter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1218346877Snpvoid free_hftid_hash(struct tid_info *); 1219346855Snp 1220237263Snpstatic inline struct wrqe * 1221237263Snpalloc_wrqe(int wr_len, struct sge_wrq *wrq) 1222228561Snp{ 1223237263Snp int len = offsetof(struct wrqe, wr) + wr_len; 1224237263Snp struct wrqe *wr; 1225228561Snp 1226237263Snp wr = malloc(len, M_CXGBE, M_NOWAIT); 1227237263Snp if (__predict_false(wr == NULL)) 1228237263Snp return (NULL); 1229237263Snp wr->wr_len = wr_len; 1230237263Snp wr->wrq = wrq; 1231237263Snp return (wr); 1232237263Snp} 1233237263Snp 1234237263Snpstatic inline void * 1235237263Snpwrtod(struct wrqe *wr) 1236237263Snp{ 1237237263Snp return (&wr->wr[0]); 1238237263Snp} 1239237263Snp 1240237263Snpstatic inline void 1241237263Snpfree_wrqe(struct wrqe *wr) 1242237263Snp{ 1243237263Snp free(wr, M_CXGBE); 1244237263Snp} 1245237263Snp 1246237263Snpstatic inline void 1247237263Snpt4_wrq_tx(struct adapter *sc, struct wrqe *wr) 1248237263Snp{ 1249237263Snp struct sge_wrq *wrq = wr->wrq; 1250237263Snp 1251228561Snp TXQ_LOCK(wrq); 1252237263Snp t4_wrq_tx_locked(sc, wrq, wr); 1253228561Snp TXQ_UNLOCK(wrq); 1254228561Snp} 1255228561Snp 1256346848Snpstatic inline int 1257346848Snpread_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val, 1258346848Snp int len) 1259346848Snp{ 1260346848Snp 1261346848Snp return (rw_via_memwin(sc, idx, addr, val, len, 0)); 1262346848Snp} 1263346848Snp 1264346848Snpstatic inline int 1265346848Snpwrite_via_memwin(struct adapter *sc, int idx, uint32_t addr, 1266346848Snp const uint32_t *val, int len) 1267346848Snp{ 1268346848Snp 1269346848Snp return (rw_via_memwin(sc, idx, addr, (void *)(uintptr_t)val, len, 1)); 1270346848Snp} 1271218792Snp#endif 1272