adapter.h revision 346871
1218792Snp/*- 2218792Snp * Copyright (c) 2011 Chelsio Communications, Inc. 3218792Snp * All rights reserved. 4218792Snp * Written by: Navdeep Parhar <np@FreeBSD.org> 5218792Snp * 6218792Snp * Redistribution and use in source and binary forms, with or without 7218792Snp * modification, are permitted provided that the following conditions 8218792Snp * are met: 9218792Snp * 1. Redistributions of source code must retain the above copyright 10218792Snp * notice, this list of conditions and the following disclaimer. 11218792Snp * 2. Redistributions in binary form must reproduce the above copyright 12218792Snp * notice, this list of conditions and the following disclaimer in the 13218792Snp * documentation and/or other materials provided with the distribution. 14218792Snp * 15218792Snp * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16218792Snp * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17218792Snp * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18218792Snp * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19218792Snp * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20218792Snp * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21218792Snp * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22218792Snp * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23218792Snp * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24218792Snp * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25218792Snp * SUCH DAMAGE. 26218792Snp * 27218792Snp * $FreeBSD: stable/11/sys/dev/cxgbe/adapter.h 346871 2019-04-29 03:10:58Z np $ 28218792Snp * 29218792Snp */ 30218792Snp 31218792Snp#ifndef __T4_ADAPTER_H__ 32218792Snp#define __T4_ADAPTER_H__ 33218792Snp 34228561Snp#include <sys/kernel.h> 35218792Snp#include <sys/bus.h> 36218792Snp#include <sys/rman.h> 37218792Snp#include <sys/types.h> 38257176Sglebius#include <sys/lock.h> 39218792Snp#include <sys/malloc.h> 40257176Sglebius#include <sys/rwlock.h> 41257176Sglebius#include <sys/sx.h> 42345664Sjhb#include <sys/vmem.h> 43257176Sglebius#include <vm/uma.h> 44257176Sglebius 45218792Snp#include <dev/pci/pcivar.h> 46218792Snp#include <dev/pci/pcireg.h> 47218792Snp#include <machine/bus.h> 48218792Snp#include <sys/socket.h> 49218792Snp#include <sys/sysctl.h> 50218792Snp#include <net/ethernet.h> 51218792Snp#include <net/if.h> 52257176Sglebius#include <net/if_var.h> 53218792Snp#include <net/if_media.h> 54235944Sbz#include <netinet/in.h> 55218792Snp#include <netinet/tcp_lro.h> 56218792Snp 57218792Snp#include "offload.h" 58301535Snp#include "t4_ioctl.h" 59266757Snp#include "common/t4_msg.h" 60228561Snp#include "firmware/t4fw_interface.h" 61218792Snp 62275733Snp#define KTR_CXGBE KTR_SPARE3 63218792SnpMALLOC_DECLARE(M_CXGBE); 64218792Snp#define CXGBE_UNIMPLEMENTED(s) \ 65218792Snp panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__) 66218792Snp 67218792Snp#if defined(__i386__) || defined(__amd64__) 68218792Snpstatic __inline void 69218792Snpprefetch(void *x) 70218792Snp{ 71218792Snp __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 72218792Snp} 73218792Snp#else 74339396Snp#define prefetch(x) __builtin_prefetch(x) 75218792Snp#endif 76218792Snp 77231115Snp#ifndef SYSCTL_ADD_UQUAD 78231115Snp#define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 79231115Snp#define sysctl_handle_64 sysctl_handle_quad 80231115Snp#define CTLTYPE_U64 CTLTYPE_QUAD 81231115Snp#endif 82231115Snp 83344858SjhbSYSCTL_DECL(_hw_cxgbe); 84344858Sjhb 85218792Snpstruct adapter; 86218792Snptypedef struct adapter adapter_t; 87218792Snp 88218792Snpenum { 89269411Snp /* 90269411Snp * All ingress queues use this entry size. Note that the firmware event 91269411Snp * queue and any iq expecting CPL_RX_PKT in the descriptor needs this to 92269411Snp * be at least 64. 93269411Snp */ 94269411Snp IQ_ESIZE = 64, 95269411Snp 96269411Snp /* Default queue sizes for all kinds of ingress queues */ 97218792Snp FW_IQ_QSIZE = 256, 98218792Snp RX_IQ_QSIZE = 1024, 99218792Snp 100269411Snp /* All egress queues use this entry size */ 101269411Snp EQ_ESIZE = 64, 102218792Snp 103269411Snp /* Default queue sizes for all kinds of egress queues */ 104269411Snp CTRL_EQ_QSIZE = 128, 105269411Snp TX_EQ_QSIZE = 1024, 106269411Snp 107219392Snp#if MJUMPAGESIZE != MCLBYTES 108263317Snp SW_ZONE_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */ 109219392Snp#else 110263317Snp SW_ZONE_SIZES = 3, /* cluster, jumbo9k, jumbo16k */ 111219392Snp#endif 112275554Snp CL_METADATA_SIZE = CACHE_LINE_SIZE, 113218792Snp 114269411Snp SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / EQ_ESIZE, /* max WR size in desc */ 115276485Snp TX_SGL_SEGS = 39, 116276485Snp TX_SGL_SEGS_TSO = 38, 117218792Snp TX_WR_FLITS = SGE_MAX_WR_LEN / 8 118218792Snp}; 119218792Snp 120218792Snpenum { 121219944Snp /* adapter intr_type */ 122219944Snp INTR_INTX = (1 << 0), 123219944Snp INTR_MSI = (1 << 1), 124219944Snp INTR_MSIX = (1 << 2) 125219944Snp}; 126219944Snp 127219944Snpenum { 128266757Snp XGMAC_MTU = (1 << 0), 129266757Snp XGMAC_PROMISC = (1 << 1), 130266757Snp XGMAC_ALLMULTI = (1 << 2), 131266757Snp XGMAC_VLANEX = (1 << 3), 132266757Snp XGMAC_UCADDR = (1 << 4), 133266757Snp XGMAC_MCADDRS = (1 << 5), 134266757Snp 135266757Snp XGMAC_ALL = 0xffff 136266757Snp}; 137266757Snp 138266757Snpenum { 139245274Snp /* flags understood by begin_synchronized_op */ 140245274Snp HOLD_LOCK = (1 << 0), 141245274Snp SLEEP_OK = (1 << 1), 142245274Snp INTR_OK = (1 << 2), 143245274Snp 144245274Snp /* flags understood by end_synchronized_op */ 145245274Snp LOCK_HELD = HOLD_LOCK, 146245274Snp}; 147245274Snp 148245274Snpenum { 149218792Snp /* adapter flags */ 150218792Snp FULL_INIT_DONE = (1 << 0), 151218792Snp FW_OK = (1 << 1), 152330307Snp CHK_MBOX_ACCESS = (1 << 2), 153228561Snp MASTER_PF = (1 << 3), 154228561Snp ADAP_SYSCTL_CTX = (1 << 4), 155278374Snp /* TOM_INIT_DONE= (1 << 5), No longer used */ 156255050Snp BUF_PACKING_OK = (1 << 6), 157306664Sjhb IS_VF = (1 << 7), 158218792Snp 159218792Snp CXGBE_BUSY = (1 << 9), 160218792Snp 161218792Snp /* port flags */ 162291665Sjhb HAS_TRACEQ = (1 << 3), 163334562Snp FIXED_IFMEDIA = (1 << 4), /* ifmedia list doesn't change. */ 164291665Sjhb 165291665Sjhb /* VI flags */ 166218792Snp DOOMED = (1 << 0), 167291665Sjhb VI_INIT_DONE = (1 << 1), 168291665Sjhb VI_SYSCTL_CTX = (1 << 2), 169284445Snp 170284445Snp /* adapter debug_flags */ 171330307Snp DF_DUMP_MBOX = (1 << 0), /* Log all mbox cmd/rpl. */ 172330307Snp DF_LOAD_FW_ANYTIME = (1 << 1), /* Allow LOAD_FW after init */ 173330307Snp DF_DISABLE_TCB_CACHE = (1 << 2), /* Disable TCB cache (T6+) */ 174218792Snp}; 175218792Snp 176291665Sjhb#define IS_DOOMED(vi) ((vi)->flags & DOOMED) 177291665Sjhb#define SET_DOOMED(vi) do {(vi)->flags |= DOOMED;} while (0) 178245274Snp#define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY) 179245274Snp#define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0) 180245274Snp#define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0) 181218792Snp 182291665Sjhbstruct vi_info { 183218792Snp device_t dev; 184291665Sjhb struct port_info *pi; 185218792Snp 186218792Snp struct ifnet *ifp; 187218792Snp 188218792Snp unsigned long flags; 189218792Snp int if_flags; 190218792Snp 191302110Snp uint16_t *rss, *nm_rss; 192309560Sjhb int smt_idx; /* for convenience */ 193218792Snp uint16_t viid; 194218792Snp int16_t xact_addr_filt;/* index of exact MAC address filter */ 195218792Snp uint16_t rss_size; /* size of VI's RSS table slice */ 196285648Snp uint16_t rss_base; /* start of VI's RSS table slice */ 197218792Snp 198291665Sjhb eventhandler_tag vlan_c; 199291665Sjhb 200291665Sjhb int nintr; 201291665Sjhb int first_intr; 202291665Sjhb 203218792Snp /* These need to be int as they are used in sysctl */ 204318854Snp int ntxq; /* # of tx queues */ 205318854Snp int first_txq; /* index of first tx queue */ 206318854Snp int rsrv_noflowq; /* Reserve queue 0 for non-flowid packets */ 207318854Snp int nrxq; /* # of rx queues */ 208318854Snp int first_rxq; /* index of first rx queue */ 209228561Snp int nofldtxq; /* # of offload tx queues */ 210228561Snp int first_ofld_txq; /* index of first offload tx queue */ 211228561Snp int nofldrxq; /* # of offload rx queues */ 212228561Snp int first_ofld_rxq; /* index of first offload rx queue */ 213302110Snp int nnmtxq; 214302110Snp int first_nm_txq; 215302110Snp int nnmrxq; 216302110Snp int first_nm_rxq; 217218792Snp int tmr_idx; 218330307Snp int ofld_tmr_idx; 219218792Snp int pktc_idx; 220330307Snp int ofld_pktc_idx; 221218792Snp int qsize_rxq; 222218792Snp int qsize_txq; 223218792Snp 224291665Sjhb struct timeval last_refreshed; 225291665Sjhb struct fw_vi_stats_vf stats; 226291665Sjhb 227291665Sjhb struct callout tick; 228291665Sjhb struct sysctl_ctx_list ctx; /* from ifconfig up to driver detach */ 229291665Sjhb 230291665Sjhb uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */ 231291665Sjhb}; 232291665Sjhb 233318850Snpstruct tx_ch_rl_params { 234318850Snp enum fw_sched_params_rate ratemode; /* %port (REL) or kbps (ABS) */ 235318850Snp uint32_t maxrate; 236318850Snp}; 237318850Snp 238301535Snpenum { 239346871Snp CLRL_USER = (1 << 0), /* allocated manually. */ 240346871Snp CLRL_SYNC = (1 << 1), /* sync hw update in progress. */ 241346871Snp CLRL_ASYNC = (1 << 2), /* async hw update requested. */ 242346871Snp CLRL_ERR = (1 << 3), /* last hw setup ended in error. */ 243301535Snp}; 244301535Snp 245318850Snpstruct tx_cl_rl_params { 246301535Snp int refcount; 247346871Snp uint8_t flags; 248318850Snp enum fw_sched_params_rate ratemode; /* %port REL or ABS value */ 249318850Snp enum fw_sched_params_unit rateunit; /* kbps or pps (when ABS) */ 250318850Snp enum fw_sched_params_mode mode; /* aggr or per-flow */ 251318850Snp uint32_t maxrate; 252318850Snp uint16_t pktsize; 253346871Snp uint16_t burstsize; 254301535Snp}; 255301535Snp 256318850Snp/* Tx scheduler parameters for a channel/port */ 257318850Snpstruct tx_sched_params { 258318850Snp /* Channel Rate Limiter */ 259318850Snp struct tx_ch_rl_params ch_rl; 260318850Snp 261318850Snp /* Class WRR */ 262318850Snp /* XXX */ 263318850Snp 264346871Snp /* Class Rate Limiter (including the default pktsize and burstsize). */ 265346871Snp int pktsize; 266346871Snp int burstsize; 267318850Snp struct tx_cl_rl_params cl_rl[]; 268318850Snp}; 269318850Snp 270291665Sjhbstruct port_info { 271291665Sjhb device_t dev; 272291665Sjhb struct adapter *adapter; 273291665Sjhb 274291665Sjhb struct vi_info *vi; 275291665Sjhb int nvi; 276291665Sjhb int up_vis; 277291665Sjhb int uld_vis; 278291665Sjhb 279318850Snp struct tx_sched_params *sched_params; 280301535Snp 281291665Sjhb struct mtx pi_lock; 282291665Sjhb char lockname[16]; 283291665Sjhb unsigned long flags; 284291665Sjhb 285291665Sjhb uint8_t lport; /* associated offload logical port */ 286291665Sjhb int8_t mdio_addr; 287291665Sjhb uint8_t port_type; 288291665Sjhb uint8_t mod_type; 289291665Sjhb uint8_t port_id; 290291665Sjhb uint8_t tx_chan; 291330307Snp uint8_t mps_bg_map; /* rx MPS buffer group bitmap */ 292330307Snp uint8_t rx_e_chan_map; /* rx TP e-channel bitmap */ 293291665Sjhb 294218792Snp struct link_config link_cfg; 295330307Snp struct ifmedia media; 296218792Snp 297272200Snp struct timeval last_refreshed; 298272200Snp struct port_stats stats; 299272200Snp u_int tnl_cong_drops; 300276485Snp u_int tx_parse_error; 301345664Sjhb u_long tx_tls_records; 302345664Sjhb u_long tx_tls_octets; 303345664Sjhb u_long rx_tls_records; 304345664Sjhb u_long rx_tls_octets; 305272200Snp 306218792Snp struct callout tick; 307218792Snp}; 308218792Snp 309291665Sjhb#define IS_MAIN_VI(vi) ((vi) == &((vi)->pi->vi[0])) 310291665Sjhb 311263317Snp/* Where the cluster came from, how it has been carved up. */ 312263317Snpstruct cluster_layout { 313263317Snp int8_t zidx; 314263317Snp int8_t hwidx; 315263317Snp uint16_t region1; /* mbufs laid out within this region */ 316263317Snp /* region2 is the DMA region */ 317263317Snp uint16_t region3; /* cluster_metadata within this region */ 318263317Snp}; 319263317Snp 320263317Snpstruct cluster_metadata { 321263317Snp u_int refcount; 322263317Snp struct fl_sdesc *sd; /* For debug only. Could easily be stale */ 323218792Snp}; 324218792Snp 325263317Snpstruct fl_sdesc { 326263317Snp caddr_t cl; 327268971Snp uint16_t nmbuf; /* # of driver originated mbufs with ref on cluster */ 328263317Snp struct cluster_layout cll; 329263317Snp}; 330263317Snp 331218792Snpstruct tx_desc { 332218792Snp __be64 flit[8]; 333218792Snp}; 334218792Snp 335218792Snpstruct tx_sdesc { 336276485Snp struct mbuf *m; /* m_nextpkt linked chain of frames */ 337218792Snp uint8_t desc_used; /* # of hardware descriptors used by the WR */ 338218792Snp}; 339218792Snp 340269411Snp 341269411Snp#define IQ_PAD (IQ_ESIZE - sizeof(struct rsp_ctrl) - sizeof(struct rss_header)) 342269411Snpstruct iq_desc { 343269411Snp struct rss_header rss; 344269411Snp uint8_t cpl[IQ_PAD]; 345269411Snp struct rsp_ctrl rsp; 346269411Snp}; 347269411Snp#undef IQ_PAD 348269411SnpCTASSERT(sizeof(struct iq_desc) == IQ_ESIZE); 349269411Snp 350218792Snpenum { 351218792Snp /* iq flags */ 352228561Snp IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */ 353228561Snp IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */ 354330307Snp /* 1 << 2 Used to be IQ_INTR */ 355228561Snp IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */ 356318842Snp IQ_ADJ_CREDIT = (1 << 4), /* hw is off by 1 credit for this iq */ 357220649Snp 358220649Snp /* iq state */ 359220649Snp IQS_DISABLED = 0, 360220649Snp IQS_BUSY = 1, 361220649Snp IQS_IDLE = 2, 362302110Snp 363302110Snp /* netmap related flags */ 364302110Snp NM_OFF = 0, 365302110Snp NM_ON = 1, 366302110Snp NM_BUSY = 2, 367218792Snp}; 368218792Snp 369346852Snpenum { 370346852Snp CPL_COOKIE_RESERVED = 0, 371346852Snp CPL_COOKIE_FILTER, 372346852Snp CPL_COOKIE_DDP0, 373346852Snp CPL_COOKIE_DDP1, 374346852Snp CPL_COOKIE_TOM, 375346855Snp CPL_COOKIE_HASHFILTER, 376346863Snp CPL_COOKIE_ETHOFLD, 377346852Snp CPL_COOKIE_AVAILABLE3, 378346852Snp 379346852Snp NUM_CPL_COOKIES = 8 /* Limited by M_COOKIE. Do not increase. */ 380346852Snp}; 381346852Snp 382302339Snpstruct sge_iq; 383302339Snpstruct rss_header; 384302339Snptypedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *, 385302339Snp struct mbuf *); 386302339Snptypedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *); 387302339Snptypedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *); 388302339Snp 389218792Snp/* 390218792Snp * Ingress Queue: T4 is producer, driver is consumer. 391218792Snp */ 392218792Snpstruct sge_iq { 393219290Snp uint32_t flags; 394228561Snp volatile int state; 395218792Snp struct adapter *adapter; 396269411Snp struct iq_desc *desc; /* KVA of descriptor ring */ 397269411Snp int8_t intr_pktc_idx; /* packet count threshold index */ 398218792Snp uint8_t gen; /* generation bit */ 399218792Snp uint8_t intr_params; /* interrupt holdoff parameters */ 400228561Snp uint8_t intr_next; /* XXX: holdoff for next interrupt */ 401218792Snp uint16_t qsize; /* size (# of entries) of the queue */ 402269411Snp uint16_t sidx; /* index of the entry with the status page */ 403218792Snp uint16_t cidx; /* consumer index */ 404228561Snp uint16_t cntxt_id; /* SGE context id for the iq */ 405269411Snp uint16_t abs_id; /* absolute SGE id for the iq */ 406228561Snp 407228561Snp STAILQ_ENTRY(sge_iq) link; 408269411Snp 409269411Snp bus_dma_tag_t desc_tag; 410269411Snp bus_dmamap_t desc_map; 411269411Snp bus_addr_t ba; /* bus address of descriptor ring */ 412218792Snp}; 413218792Snp 414218792Snpenum { 415228561Snp EQ_CTRL = 1, 416228561Snp EQ_ETH = 2, 417228561Snp EQ_OFLD = 3, 418228561Snp 419218792Snp /* eq flags */ 420276485Snp EQ_TYPEMASK = 0x3, /* 2 lsbits hold the type (see above) */ 421276485Snp EQ_ALLOCATED = (1 << 2), /* firmware resources allocated */ 422276485Snp EQ_ENABLED = (1 << 3), /* open for business */ 423318854Snp EQ_QFLUSH = (1 << 4), /* if_qflush in progress */ 424218792Snp}; 425218792Snp 426248925Snp/* Listed in order of preference. Update t4_sysctls too if you change these */ 427249392Snpenum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB}; 428248925Snp 429218792Snp/* 430218792Snp * Egress Queue: driver is producer, T4 is consumer. 431218792Snp * 432218792Snp * Note: A free list is an egress queue (driver produces the buffers and T4 433218792Snp * consumes them) but it's special enough to have its own struct (see sge_fl). 434218792Snp */ 435218792Snpstruct sge_eq { 436228561Snp unsigned int flags; /* MUST be first */ 437228561Snp unsigned int cntxt_id; /* SGE context id for the eq */ 438306664Sjhb unsigned int abs_id; /* absolute SGE id for the eq */ 439218792Snp struct mtx eq_lock; 440218792Snp 441218792Snp struct tx_desc *desc; /* KVA of descriptor ring */ 442339396Snp uint8_t doorbells; 443248925Snp volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */ 444248925Snp u_int udb_qid; /* relative qid within the doorbell page */ 445276485Snp uint16_t sidx; /* index of the entry with the status page */ 446218792Snp uint16_t cidx; /* consumer idx (desc idx) */ 447218792Snp uint16_t pidx; /* producer idx (desc idx) */ 448276485Snp uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 449276485Snp uint16_t dbidx; /* pidx of the most recent doorbell */ 450219288Snp uint16_t iqid; /* iq that gets egr_update for the eq */ 451228561Snp uint8_t tx_chan; /* tx channel used by the eq */ 452276485Snp volatile u_int equiq; /* EQUIQ outstanding */ 453228561Snp 454276485Snp bus_dma_tag_t desc_tag; 455276485Snp bus_dmamap_t desc_map; 456276485Snp bus_addr_t ba; /* bus address of descriptor ring */ 457276485Snp char lockname[16]; 458220873Snp}; 459218792Snp 460263317Snpstruct sw_zone_info { 461263317Snp uma_zone_t zone; /* zone that this cluster comes from */ 462263317Snp int size; /* size of cluster: 2K, 4K, 9K, 16K, etc. */ 463263317Snp int type; /* EXT_xxx type of the cluster */ 464263317Snp int8_t head_hwidx; 465263317Snp int8_t tail_hwidx; 466255050Snp}; 467255050Snp 468263317Snpstruct hw_buf_info { 469263317Snp int8_t zidx; /* backpointer to zone; -ve means unused */ 470263317Snp int8_t next; /* next hwidx for this zone; -1 means no more */ 471263317Snp int size; 472263317Snp}; 473263317Snp 474228561Snpenum { 475296603Snp NUM_MEMWIN = 3, 476296603Snp 477296603Snp MEMWIN0_APERTURE = 2048, 478296603Snp MEMWIN0_BASE = 0x1b800, 479296603Snp 480296603Snp MEMWIN1_APERTURE = 32768, 481296603Snp MEMWIN1_BASE = 0x28000, 482296603Snp 483296603Snp MEMWIN2_APERTURE_T4 = 65536, 484296603Snp MEMWIN2_BASE_T4 = 0x30000, 485296603Snp 486296603Snp MEMWIN2_APERTURE_T5 = 128 * 1024, 487296603Snp MEMWIN2_BASE_T5 = 0x60000, 488296603Snp}; 489296603Snp 490296603Snpstruct memwin { 491296603Snp struct rwlock mw_lock __aligned(CACHE_LINE_SIZE); 492296603Snp uint32_t mw_base; /* constant after setup_memwin */ 493296603Snp uint32_t mw_aperture; /* ditto */ 494296603Snp uint32_t mw_curpos; /* protected by mw_lock */ 495296603Snp}; 496296603Snp 497296603Snpenum { 498228561Snp FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */ 499228561Snp FL_DOOMED = (1 << 1), /* about to be destroyed */ 500255050Snp FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */ 501269428Snp FL_BUF_RESUME = (1 << 3), /* resume from the middle of the frame */ 502228561Snp}; 503228561Snp 504269428Snp#define FL_RUNNING_LOW(fl) \ 505269428Snp (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) <= fl->lowat) 506269428Snp#define FL_NOT_RUNNING_LOW(fl) \ 507269428Snp (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) >= 2 * fl->lowat) 508228561Snp 509218792Snpstruct sge_fl { 510218792Snp struct mtx fl_lock; 511218792Snp __be64 *desc; /* KVA of descriptor ring, ptr to addresses */ 512218792Snp struct fl_sdesc *sdesc; /* KVA of software descriptor ring */ 513269428Snp struct cluster_layout cll_def; /* default refill zone, layout */ 514269428Snp uint16_t lowat; /* # of buffers <= this means fl needs help */ 515269428Snp int flags; 516269428Snp uint16_t buf_boundary; 517263317Snp 518269428Snp /* The 16b idx all deal with hw descriptors */ 519269428Snp uint16_t dbidx; /* hw pidx after last doorbell */ 520269428Snp uint16_t sidx; /* index of status page */ 521269428Snp volatile uint16_t hw_cidx; 522263317Snp 523269428Snp /* The 32b idx are all buffer idx, not hardware descriptor idx */ 524269428Snp uint32_t cidx; /* consumer index */ 525269428Snp uint32_t pidx; /* producer index */ 526269428Snp 527269428Snp uint32_t dbval; 528269428Snp u_int rx_offset; /* offset in fl buf (when buffer packing) */ 529269428Snp volatile uint32_t *udb; 530269428Snp 531263317Snp uint64_t mbuf_allocated;/* # of mbuf allocated from zone_mbuf */ 532263317Snp uint64_t mbuf_inlined; /* # of mbuf created within clusters */ 533263317Snp uint64_t cl_allocated; /* # of clusters allocated */ 534263317Snp uint64_t cl_recycled; /* # of clusters recycled */ 535263317Snp uint64_t cl_fast_recycled; /* # of clusters recycled (fast) */ 536269428Snp 537269428Snp /* These 3 are valid when FL_BUF_RESUME is set, stale otherwise. */ 538269428Snp struct mbuf *m0; 539269428Snp struct mbuf **pnext; 540269428Snp u_int remaining; 541269428Snp 542269428Snp uint16_t qsize; /* # of hw descriptors (status page included) */ 543269428Snp uint16_t cntxt_id; /* SGE context id for the freelist */ 544269428Snp TAILQ_ENTRY(sge_fl) link; /* All starving freelists */ 545269428Snp bus_dma_tag_t desc_tag; 546269428Snp bus_dmamap_t desc_map; 547269428Snp char lockname[16]; 548269428Snp bus_addr_t ba; /* bus address of descriptor ring */ 549269428Snp struct cluster_layout cll_alt; /* alternate refill zone, layout */ 550218792Snp}; 551218792Snp 552276485Snpstruct mp_ring; 553276485Snp 554220873Snp/* txq: SGE egress queue + what's needed for Ethernet NIC */ 555218792Snpstruct sge_txq { 556218792Snp struct sge_eq eq; /* MUST be first */ 557220873Snp 558220873Snp struct ifnet *ifp; /* the interface this txq belongs to */ 559276485Snp struct mp_ring *r; /* tx software ring */ 560220873Snp struct tx_sdesc *sdesc; /* KVA of software descriptor ring */ 561276485Snp struct sglist *gl; 562276485Snp __be32 cpl_ctrl0; /* for convenience */ 563301628Snp int tc_idx; /* traffic class */ 564218792Snp 565276485Snp struct task tx_reclaim_task; 566218792Snp /* stats for common events first */ 567218792Snp 568218792Snp uint64_t txcsum; /* # of times hardware assisted with checksum */ 569237819Snp uint64_t tso_wrs; /* # of TSO work requests */ 570218792Snp uint64_t vlan_insertion;/* # of times VLAN tag was inserted */ 571218792Snp uint64_t imm_wrs; /* # of work requests with immediate data */ 572218792Snp uint64_t sgl_wrs; /* # of work requests with direct SGL */ 573218792Snp uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */ 574276485Snp uint64_t txpkts0_wrs; /* # of type0 coalesced tx work requests */ 575276485Snp uint64_t txpkts1_wrs; /* # of type1 coalesced tx work requests */ 576276485Snp uint64_t txpkts0_pkts; /* # of frames in type0 coalesced tx WRs */ 577276485Snp uint64_t txpkts1_pkts; /* # of frames in type1 coalesced tx WRs */ 578218792Snp 579218792Snp /* stats for not-that-common events */ 580220873Snp} __aligned(CACHE_LINE_SIZE); 581218792Snp 582218792Snp/* rxq: SGE ingress queue + SGE free list + miscellaneous items */ 583218792Snpstruct sge_rxq { 584218792Snp struct sge_iq iq; /* MUST be first */ 585228561Snp struct sge_fl fl; /* MUST follow iq */ 586218792Snp 587219290Snp struct ifnet *ifp; /* the interface this rxq belongs to */ 588237819Snp#if defined(INET) || defined(INET6) 589218792Snp struct lro_ctrl lro; /* LRO state */ 590219290Snp#endif 591218792Snp 592218792Snp /* stats for common events first */ 593218792Snp 594218792Snp uint64_t rxcsum; /* # of times hardware assisted with checksum */ 595218792Snp uint64_t vlan_extraction;/* # of times VLAN tag was extracted */ 596218792Snp 597218792Snp /* stats for not-that-common events */ 598218792Snp 599218792Snp} __aligned(CACHE_LINE_SIZE); 600218792Snp 601237263Snpstatic inline struct sge_rxq * 602237263Snpiq_to_rxq(struct sge_iq *iq) 603237263Snp{ 604237263Snp 605241733Sed return (__containerof(iq, struct sge_rxq, iq)); 606237263Snp} 607237263Snp 608237263Snp 609228561Snp/* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */ 610228561Snpstruct sge_ofld_rxq { 611228561Snp struct sge_iq iq; /* MUST be first */ 612228561Snp struct sge_fl fl; /* MUST follow iq */ 613228561Snp} __aligned(CACHE_LINE_SIZE); 614237263Snp 615237263Snpstatic inline struct sge_ofld_rxq * 616237263Snpiq_to_ofld_rxq(struct sge_iq *iq) 617237263Snp{ 618237263Snp 619241733Sed return (__containerof(iq, struct sge_ofld_rxq, iq)); 620237263Snp} 621228561Snp 622237263Snpstruct wrqe { 623237263Snp STAILQ_ENTRY(wrqe) link; 624237263Snp struct sge_wrq *wrq; 625237263Snp int wr_len; 626276485Snp char wr[] __aligned(16); 627237263Snp}; 628237263Snp 629276485Snpstruct wrq_cookie { 630276485Snp TAILQ_ENTRY(wrq_cookie) link; 631276485Snp int ndesc; 632276485Snp int pidx; 633276485Snp}; 634276485Snp 635228561Snp/* 636228561Snp * wrq: SGE egress queue that is given prebuilt work requests. Both the control 637228561Snp * and offload tx queues are of this type. 638228561Snp */ 639228561Snpstruct sge_wrq { 640220873Snp struct sge_eq eq; /* MUST be first */ 641220873Snp 642228561Snp struct adapter *adapter; 643276485Snp struct task wrq_tx_task; 644228561Snp 645276485Snp /* Tx desc reserved but WR not "committed" yet. */ 646276485Snp TAILQ_HEAD(wrq_incomplete_wrs , wrq_cookie) incomplete_wrs; 647276485Snp 648276485Snp /* List of WRs ready to go out as soon as descriptors are available. */ 649237263Snp STAILQ_HEAD(, wrqe) wr_list; 650276485Snp u_int nwr_pending; 651276485Snp u_int ndesc_needed; 652237263Snp 653220873Snp /* stats for common events first */ 654220873Snp 655276485Snp uint64_t tx_wrs_direct; /* # of WRs written directly to desc ring. */ 656276485Snp uint64_t tx_wrs_ss; /* # of WRs copied from scratch space. */ 657276485Snp uint64_t tx_wrs_copied; /* # of WRs queued and copied to desc ring. */ 658220873Snp 659220873Snp /* stats for not-that-common events */ 660220873Snp 661276485Snp /* 662276485Snp * Scratch space for work requests that wrap around after reaching the 663298955Spfg * status page, and some information about the last WR that used it. 664276485Snp */ 665276485Snp uint16_t ss_pidx; 666276485Snp uint16_t ss_len; 667276485Snp uint8_t ss[SGE_MAX_WR_LEN]; 668276485Snp 669220873Snp} __aligned(CACHE_LINE_SIZE); 670220873Snp 671266757Snp 672266757Snpstruct sge_nm_rxq { 673291665Sjhb struct vi_info *vi; 674266757Snp 675269411Snp struct iq_desc *iq_desc; 676266757Snp uint16_t iq_abs_id; 677266757Snp uint16_t iq_cntxt_id; 678266757Snp uint16_t iq_cidx; 679266757Snp uint16_t iq_sidx; 680266757Snp uint8_t iq_gen; 681266757Snp 682266757Snp __be64 *fl_desc; 683266757Snp uint16_t fl_cntxt_id; 684266757Snp uint32_t fl_cidx; 685266757Snp uint32_t fl_pidx; 686266757Snp uint32_t fl_sidx; 687266757Snp uint32_t fl_db_val; 688266757Snp u_int fl_hwidx:4; 689266757Snp 690266757Snp u_int nid; /* netmap ring # for this queue */ 691266757Snp 692266757Snp /* infrequently used items after this */ 693266757Snp 694266757Snp bus_dma_tag_t iq_desc_tag; 695266757Snp bus_dmamap_t iq_desc_map; 696266757Snp bus_addr_t iq_ba; 697266757Snp int intr_idx; 698266757Snp 699266757Snp bus_dma_tag_t fl_desc_tag; 700266757Snp bus_dmamap_t fl_desc_map; 701266757Snp bus_addr_t fl_ba; 702266757Snp} __aligned(CACHE_LINE_SIZE); 703266757Snp 704266757Snpstruct sge_nm_txq { 705266757Snp struct tx_desc *desc; 706266757Snp uint16_t cidx; 707266757Snp uint16_t pidx; 708266757Snp uint16_t sidx; 709266757Snp uint16_t equiqidx; /* EQUIQ last requested at this pidx */ 710266757Snp uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 711266757Snp uint16_t dbidx; /* pidx of the most recent doorbell */ 712339396Snp uint8_t doorbells; 713266757Snp volatile uint32_t *udb; 714266757Snp u_int udb_qid; 715266757Snp u_int cntxt_id; 716266757Snp __be32 cpl_ctrl0; /* for convenience */ 717266757Snp u_int nid; /* netmap ring # for this queue */ 718266757Snp 719266757Snp /* infrequently used items after this */ 720266757Snp 721266757Snp bus_dma_tag_t desc_tag; 722266757Snp bus_dmamap_t desc_map; 723266757Snp bus_addr_t ba; 724266757Snp int iqidx; 725266757Snp} __aligned(CACHE_LINE_SIZE); 726266757Snp 727218792Snpstruct sge { 728228561Snp int nrxq; /* total # of Ethernet rx queues */ 729318854Snp int ntxq; /* total # of Ethernet tx queues */ 730228561Snp int nofldrxq; /* total # of TOE rx queues */ 731228561Snp int nofldtxq; /* total # of TOE tx queues */ 732266757Snp int nnmrxq; /* total # of netmap rx queues */ 733266757Snp int nnmtxq; /* total # of netmap tx queues */ 734228561Snp int niq; /* total # of ingress queues */ 735228561Snp int neq; /* total # of egress queues */ 736218792Snp 737218792Snp struct sge_iq fwq; /* Firmware event queue */ 738228561Snp struct sge_wrq mgmtq; /* Management queue (control queue) */ 739228561Snp struct sge_wrq *ctrlq; /* Control queues */ 740218792Snp struct sge_txq *txq; /* NIC tx queues */ 741218792Snp struct sge_rxq *rxq; /* NIC rx queues */ 742228561Snp struct sge_wrq *ofld_txq; /* TOE tx queues */ 743228561Snp struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */ 744266757Snp struct sge_nm_txq *nm_txq; /* netmap tx queues */ 745266757Snp struct sge_nm_rxq *nm_rxq; /* netmap rx queues */ 746218792Snp 747306664Sjhb uint16_t iq_start; /* first cntxt_id */ 748306664Sjhb uint16_t iq_base; /* first abs_id */ 749306664Sjhb int eq_start; /* first cntxt_id */ 750306664Sjhb int eq_base; /* first abs_id */ 751218792Snp struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */ 752218792Snp struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */ 753255050Snp 754263317Snp int8_t safe_hwidx1; /* may not have room for metadata */ 755263317Snp int8_t safe_hwidx2; /* with room for metadata and maybe more */ 756263317Snp struct sw_zone_info sw_zone_info[SW_ZONE_SIZES]; 757263317Snp struct hw_buf_info hw_buf_info[SGE_FLBUF_SIZES]; 758218792Snp}; 759218792Snp 760309560Sjhbstruct devnames { 761309560Sjhb const char *nexus_name; 762309560Sjhb const char *ifnet_name; 763309560Sjhb const char *vi_ifnet_name; 764309560Sjhb const char *pf03_drv_name; 765309560Sjhb const char *vf_nexus_name; 766309560Sjhb const char *vf_ifnet_name; 767309560Sjhb}; 768309560Sjhb 769218792Snpstruct adapter { 770228561Snp SLIST_ENTRY(adapter) link; 771218792Snp device_t dev; 772218792Snp struct cdev *cdev; 773309560Sjhb const struct devnames *names; 774218792Snp 775218792Snp /* PCIe register resources */ 776218792Snp int regs_rid; 777218792Snp struct resource *regs_res; 778218792Snp int msix_rid; 779218792Snp struct resource *msix_res; 780218792Snp bus_space_handle_t bh; 781218792Snp bus_space_tag_t bt; 782218792Snp bus_size_t mmio_len; 783248925Snp int udbs_rid; 784248925Snp struct resource *udbs_res; 785248925Snp volatile uint8_t *udbs_base; 786218792Snp 787218792Snp unsigned int pf; 788218792Snp unsigned int mbox; 789296489Snp unsigned int vpd_busy; 790296489Snp unsigned int vpd_flag; 791218792Snp 792218792Snp /* Interrupt information */ 793218792Snp int intr_type; 794218792Snp int intr_count; 795218792Snp struct irq { 796218792Snp struct resource *res; 797218792Snp int rid; 798302110Snp volatile int nm_state; /* NM_OFF, NM_ON, or NM_BUSY */ 799218792Snp void *tag; 800302110Snp struct sge_rxq *rxq; 801302110Snp struct sge_nm_rxq *nm_rxq; 802302110Snp } __aligned(CACHE_LINE_SIZE) *irq; 803306664Sjhb int sge_gts_reg; 804306664Sjhb int sge_kdoorbell_reg; 805218792Snp 806218792Snp bus_dma_tag_t dmat; /* Parent DMA tag */ 807218792Snp 808218792Snp struct sge sge; 809255015Snp int lro_timeout; 810302339Snp int sc_do_rxcopy; 811218792Snp 812296383Snp struct taskqueue *tq[MAX_NCHAN]; /* General purpose taskqueues */ 813218792Snp struct port_info *port[MAX_NPORTS]; 814330307Snp uint8_t chan_map[MAX_NCHAN]; /* channel -> port */ 815218792Snp 816237263Snp void *tom_softc; /* (struct tom_data *) */ 817228561Snp struct tom_tunables tt; 818346805Snp struct t4_offload_policy *policy; 819346805Snp struct rwlock policy_lock; 820346805Snp 821346805Snp void *iwarp_softc; /* (struct c4iw_dev *) */ 822331769Shselasky struct iw_tunables iwt; 823292736Snp void *iscsi_ulp_softc; /* (struct cxgbei_data *) */ 824345040Sjhb void *ccr_softc; /* (struct ccr_softc *) */ 825222509Snp struct l2t_data *l2t; /* L2 table */ 826346855Snp struct smt_data *smt; /* Source MAC Table */ 827218792Snp struct tid_info tids; 828345664Sjhb vmem_t *key_map; 829218792Snp 830339396Snp uint8_t doorbells; 831278374Snp int offload_map; /* ports with IFCAP_TOE enabled */ 832278374Snp int active_ulds; /* ULDs activated on this adapter */ 833218792Snp int flags; 834284445Snp int debug_flags; 835218792Snp 836253691Snp char ifp_lockname[16]; 837253691Snp struct mtx ifp_lock; 838253691Snp struct ifnet *ifp; /* tracer ifp */ 839253691Snp struct ifmedia media; 840253691Snp int traceq; /* iq used by all tracers, -1 if none */ 841253691Snp int tracer_valid; /* bitmap of valid tracers */ 842253691Snp int tracer_enabled; /* bitmap of enabled tracers */ 843253691Snp 844296641Snp char fw_version[16]; 845296641Snp char tp_version[16]; 846309458Sjhb char er_version[16]; 847309458Sjhb char bs_version[16]; 848245936Snp char cfg_file[32]; 849245936Snp u_int cfcsum; 850218792Snp struct adapter_params params; 851296383Snp const struct chip_params *chip_params; 852218792Snp struct t4_virt_res vres; 853218792Snp 854296710Snp uint16_t nbmcaps; 855228561Snp uint16_t linkcaps; 856296710Snp uint16_t switchcaps; 857228561Snp uint16_t niccaps; 858228561Snp uint16_t toecaps; 859228561Snp uint16_t rdmacaps; 860309560Sjhb uint16_t cryptocaps; 861228561Snp uint16_t iscsicaps; 862228561Snp uint16_t fcoecaps; 863220873Snp 864228561Snp struct sysctl_ctx_list ctx; /* from adapter_full_init to full_uninit */ 865228561Snp 866218792Snp struct mtx sc_lock; 867218792Snp char lockname[16]; 868228561Snp 869228561Snp /* Starving free lists */ 870228561Snp struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */ 871228561Snp TAILQ_HEAD(, sge_fl) sfl; 872228561Snp struct callout sfl_callout; 873228561Snp 874296552Snp struct mtx reg_lock; /* for indirect register access */ 875272200Snp 876296603Snp struct memwin memwin[NUM_MEMWIN]; /* memory windows */ 877296603Snp 878318850Snp struct mtx tc_lock; 879318850Snp struct task tc_task; 880318850Snp 881245274Snp const char *last_op; 882245274Snp const void *last_op_thr; 883286926Snp int last_op_flags; 884218792Snp}; 885218792Snp 886218792Snp#define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock) 887218792Snp#define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock) 888218792Snp#define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED) 889218792Snp#define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED) 890218792Snp 891245274Snp#define ASSERT_SYNCHRONIZED_OP(sc) \ 892245274Snp KASSERT(IS_BUSY(sc) && \ 893245274Snp (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \ 894245274Snp ("%s: operation not synchronized.", __func__)) 895245274Snp 896218792Snp#define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock) 897218792Snp#define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock) 898218792Snp#define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED) 899218792Snp#define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED) 900218792Snp 901218792Snp#define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock) 902218792Snp#define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock) 903218792Snp#define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock) 904218792Snp#define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED) 905218792Snp#define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED) 906218792Snp 907218792Snp#define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl) 908218792Snp#define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl) 909218792Snp#define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl) 910218792Snp#define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl) 911218792Snp 912218792Snp#define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock) 913218792Snp#define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock) 914218792Snp#define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock) 915218792Snp#define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED) 916218792Snp#define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED) 917218792Snp 918218792Snp#define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq) 919218792Snp#define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq) 920218792Snp#define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq) 921218792Snp#define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq) 922218792Snp#define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq) 923218792Snp 924284445Snp#define CH_DUMP_MBOX(sc, mbox, data_reg) \ 925284445Snp do { \ 926284445Snp if (sc->debug_flags & DF_DUMP_MBOX) { \ 927284445Snp log(LOG_NOTICE, \ 928284445Snp "%s mbox %u: %016llx %016llx %016llx %016llx " \ 929284445Snp "%016llx %016llx %016llx %016llx\n", \ 930284445Snp device_get_nameunit(sc->dev), mbox, \ 931284445Snp (unsigned long long)t4_read_reg64(sc, data_reg), \ 932284445Snp (unsigned long long)t4_read_reg64(sc, data_reg + 8), \ 933284445Snp (unsigned long long)t4_read_reg64(sc, data_reg + 16), \ 934284445Snp (unsigned long long)t4_read_reg64(sc, data_reg + 24), \ 935284445Snp (unsigned long long)t4_read_reg64(sc, data_reg + 32), \ 936284445Snp (unsigned long long)t4_read_reg64(sc, data_reg + 40), \ 937284445Snp (unsigned long long)t4_read_reg64(sc, data_reg + 48), \ 938284445Snp (unsigned long long)t4_read_reg64(sc, data_reg + 56)); \ 939284445Snp } \ 940284445Snp } while (0) 941284445Snp 942291665Sjhb#define for_each_txq(vi, iter, q) \ 943291665Sjhb for (q = &vi->pi->adapter->sge.txq[vi->first_txq], iter = 0; \ 944291665Sjhb iter < vi->ntxq; ++iter, ++q) 945291665Sjhb#define for_each_rxq(vi, iter, q) \ 946291665Sjhb for (q = &vi->pi->adapter->sge.rxq[vi->first_rxq], iter = 0; \ 947291665Sjhb iter < vi->nrxq; ++iter, ++q) 948291665Sjhb#define for_each_ofld_txq(vi, iter, q) \ 949291665Sjhb for (q = &vi->pi->adapter->sge.ofld_txq[vi->first_ofld_txq], iter = 0; \ 950291665Sjhb iter < vi->nofldtxq; ++iter, ++q) 951291665Sjhb#define for_each_ofld_rxq(vi, iter, q) \ 952291665Sjhb for (q = &vi->pi->adapter->sge.ofld_rxq[vi->first_ofld_rxq], iter = 0; \ 953291665Sjhb iter < vi->nofldrxq; ++iter, ++q) 954291665Sjhb#define for_each_nm_txq(vi, iter, q) \ 955302110Snp for (q = &vi->pi->adapter->sge.nm_txq[vi->first_nm_txq], iter = 0; \ 956302110Snp iter < vi->nnmtxq; ++iter, ++q) 957291665Sjhb#define for_each_nm_rxq(vi, iter, q) \ 958302110Snp for (q = &vi->pi->adapter->sge.nm_rxq[vi->first_nm_rxq], iter = 0; \ 959302110Snp iter < vi->nnmrxq; ++iter, ++q) 960291665Sjhb#define for_each_vi(_pi, _iter, _vi) \ 961291665Sjhb for ((_vi) = (_pi)->vi, (_iter) = 0; (_iter) < (_pi)->nvi; \ 962291665Sjhb ++(_iter), ++(_vi)) 963218792Snp 964269428Snp#define IDXINCR(idx, incr, wrap) do { \ 965269428Snp idx = wrap - idx > incr ? idx + incr : incr - (wrap - idx); \ 966269411Snp} while (0) 967269411Snp#define IDXDIFF(head, tail, wrap) \ 968269428Snp ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 969269411Snp 970222510Snp/* One for errors, one for firmware events */ 971222510Snp#define T4_EXTRA_INTR 2 972218792Snp 973306664Sjhb/* One for firmware events */ 974306664Sjhb#define T4VF_EXTRA_INTR 1 975306664Sjhb 976330307Snpstatic inline int 977330307Snpforwarding_intr_to_fwq(struct adapter *sc) 978330307Snp{ 979330307Snp 980330307Snp return (sc->intr_count == 1); 981330307Snp} 982330307Snp 983218792Snpstatic inline uint32_t 984218792Snpt4_read_reg(struct adapter *sc, uint32_t reg) 985218792Snp{ 986237263Snp 987218792Snp return bus_space_read_4(sc->bt, sc->bh, reg); 988218792Snp} 989218792Snp 990218792Snpstatic inline void 991218792Snpt4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val) 992218792Snp{ 993237263Snp 994218792Snp bus_space_write_4(sc->bt, sc->bh, reg, val); 995218792Snp} 996218792Snp 997218792Snpstatic inline uint64_t 998218792Snpt4_read_reg64(struct adapter *sc, uint32_t reg) 999218792Snp{ 1000237263Snp 1001311260Snp#ifdef __LP64__ 1002311260Snp return bus_space_read_8(sc->bt, sc->bh, reg); 1003311260Snp#else 1004311260Snp return (uint64_t)bus_space_read_4(sc->bt, sc->bh, reg) + 1005311260Snp ((uint64_t)bus_space_read_4(sc->bt, sc->bh, reg + 4) << 32); 1006311260Snp 1007311260Snp#endif 1008218792Snp} 1009218792Snp 1010218792Snpstatic inline void 1011218792Snpt4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val) 1012218792Snp{ 1013237263Snp 1014311260Snp#ifdef __LP64__ 1015311260Snp bus_space_write_8(sc->bt, sc->bh, reg, val); 1016311260Snp#else 1017311260Snp bus_space_write_4(sc->bt, sc->bh, reg, val); 1018311260Snp bus_space_write_4(sc->bt, sc->bh, reg + 4, val>> 32); 1019311260Snp#endif 1020218792Snp} 1021218792Snp 1022218792Snpstatic inline void 1023218792Snpt4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val) 1024218792Snp{ 1025237263Snp 1026218792Snp *val = pci_read_config(sc->dev, reg, 1); 1027218792Snp} 1028218792Snp 1029218792Snpstatic inline void 1030218792Snpt4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val) 1031218792Snp{ 1032237263Snp 1033218792Snp pci_write_config(sc->dev, reg, val, 1); 1034218792Snp} 1035218792Snp 1036218792Snpstatic inline void 1037218792Snpt4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val) 1038218792Snp{ 1039237263Snp 1040218792Snp *val = pci_read_config(sc->dev, reg, 2); 1041218792Snp} 1042218792Snp 1043218792Snpstatic inline void 1044218792Snpt4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val) 1045218792Snp{ 1046237263Snp 1047218792Snp pci_write_config(sc->dev, reg, val, 2); 1048218792Snp} 1049218792Snp 1050218792Snpstatic inline void 1051218792Snpt4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val) 1052218792Snp{ 1053237263Snp 1054218792Snp *val = pci_read_config(sc->dev, reg, 4); 1055218792Snp} 1056218792Snp 1057218792Snpstatic inline void 1058218792Snpt4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val) 1059218792Snp{ 1060237263Snp 1061218792Snp pci_write_config(sc->dev, reg, val, 4); 1062218792Snp} 1063218792Snp 1064218792Snpstatic inline struct port_info * 1065218792Snpadap2pinfo(struct adapter *sc, int idx) 1066218792Snp{ 1067237263Snp 1068218792Snp return (sc->port[idx]); 1069218792Snp} 1070218792Snp 1071218792Snpstatic inline void 1072330307Snpt4_os_set_hw_addr(struct port_info *pi, uint8_t hw_addr[]) 1073218792Snp{ 1074237263Snp 1075330307Snp bcopy(hw_addr, pi->vi[0].hw_addr, ETHER_ADDR_LEN); 1076218792Snp} 1077218792Snp 1078248925Snpstatic inline int 1079248925Snptx_resume_threshold(struct sge_eq *eq) 1080228561Snp{ 1081237263Snp 1082276485Snp /* not quite the same as qsize / 4, but this will do. */ 1083276485Snp return (eq->sidx / 4); 1084228561Snp} 1085228561Snp 1086296481Snpstatic inline int 1087296481Snpt4_use_ldst(struct adapter *sc) 1088296481Snp{ 1089296481Snp 1090296481Snp#ifdef notyet 1091296481Snp return (sc->flags & FW_OK || !sc->use_bd); 1092296481Snp#else 1093296481Snp return (0); 1094296481Snp#endif 1095296481Snp} 1096296481Snp 1097219286Snp/* t4_main.c */ 1098330307Snpextern int t4_ntxq; 1099330307Snpextern int t4_nrxq; 1100306664Sjhbextern int t4_intr_types; 1101330307Snpextern int t4_tmr_idx; 1102330307Snpextern int t4_pktc_idx; 1103306664Sjhbextern unsigned int t4_qsize_rxq; 1104306664Sjhbextern unsigned int t4_qsize_txq; 1105306664Sjhbextern device_method_t cxgbe_methods[]; 1106306664Sjhb 1107218792Snpint t4_os_find_pci_capability(struct adapter *, int); 1108218792Snpint t4_os_pci_save_state(struct adapter *); 1109218792Snpint t4_os_pci_restore_state(struct adapter *); 1110330307Snpvoid t4_os_portmod_changed(struct port_info *); 1111330307Snpvoid t4_os_link_changed(struct port_info *); 1112228561Snpvoid t4_iterate(void (*)(struct adapter *, void *), void *); 1113309560Sjhbvoid t4_init_devnames(struct adapter *); 1114306664Sjhbvoid t4_add_adapter(struct adapter *); 1115345664Sjhbvoid t4_aes_getdeckey(void *, const void *, unsigned int); 1116306664Sjhbint t4_detach_common(device_t); 1117306664Sjhbint t4_map_bars_0_and_4(struct adapter *); 1118306664Sjhbint t4_map_bar_2(struct adapter *); 1119306664Sjhbint t4_setup_intr_handlers(struct adapter *); 1120306664Sjhbvoid t4_sysctls(struct adapter *); 1121291665Sjhbint begin_synchronized_op(struct adapter *, struct vi_info *, int, char *); 1122291665Sjhbvoid doom_vi(struct adapter *, struct vi_info *); 1123245274Snpvoid end_synchronized_op(struct adapter *, int); 1124266757Snpint update_mac_settings(struct ifnet *, int); 1125266757Snpint adapter_full_init(struct adapter *); 1126266757Snpint adapter_full_uninit(struct adapter *); 1127291665Sjhbuint64_t cxgbe_get_counter(struct ifnet *, ift_counter); 1128291665Sjhbint vi_full_init(struct vi_info *); 1129291665Sjhbint vi_full_uninit(struct vi_info *); 1130291665Sjhbvoid vi_sysctls(struct vi_info *); 1131291665Sjhbvoid vi_tick(void *); 1132346848Snpint rw_via_memwin(struct adapter *, int, uint32_t, uint32_t *, int, int); 1133346849Snpint alloc_atid_tab(struct tid_info *, int); 1134346849Snpvoid free_atid_tab(struct tid_info *); 1135346849Snpint alloc_atid(struct adapter *, void *); 1136346849Snpvoid *lookup_atid(struct adapter *, int); 1137346849Snpvoid free_atid(struct adapter *, int); 1138346850Snpvoid release_tid(struct adapter *, int, struct sge_wrq *); 1139218792Snp 1140266757Snp#ifdef DEV_NETMAP 1141266757Snp/* t4_netmap.c */ 1142302110Snpvoid cxgbe_nm_attach(struct vi_info *); 1143302110Snpvoid cxgbe_nm_detach(struct vi_info *); 1144266757Snpvoid t4_nm_intr(void *); 1145266757Snp#endif 1146266757Snp 1147219286Snp/* t4_sge.c */ 1148219392Snpvoid t4_sge_modload(void); 1149269032Snpvoid t4_sge_modunload(void); 1150269032Snpuint64_t t4_sge_extfree_refs(void); 1151248925Snpvoid t4_tweak_chip_settings(struct adapter *); 1152248925Snpint t4_read_chip_settings(struct adapter *); 1153218792Snpint t4_create_dma_tag(struct adapter *); 1154253829Snpvoid t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *, 1155253829Snp struct sysctl_oid_list *); 1156218792Snpint t4_destroy_dma_tag(struct adapter *); 1157220873Snpint t4_setup_adapter_queues(struct adapter *); 1158220873Snpint t4_teardown_adapter_queues(struct adapter *); 1159291665Sjhbint t4_setup_vi_queues(struct vi_info *); 1160291665Sjhbint t4_teardown_vi_queues(struct vi_info *); 1161218792Snpvoid t4_intr_all(void *); 1162222510Snpvoid t4_intr(void *); 1163302110Snpvoid t4_vi_intr(void *); 1164218792Snpvoid t4_intr_err(void *); 1165218792Snpvoid t4_intr_evt(void *); 1166237263Snpvoid t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *); 1167218792Snpvoid t4_update_fl_bufsize(struct ifnet *); 1168306664Sjhbint parse_pkt(struct adapter *, struct mbuf **); 1169276485Snpvoid *start_wrq_wr(struct sge_wrq *, int, struct wrq_cookie *); 1170276485Snpvoid commit_wrq_wr(struct sge_wrq *, void *, struct wrq_cookie *); 1171285221Snpint tnl_cong(struct port_info *, int); 1172346852Snpvoid t4_register_an_handler(an_handler_t); 1173346852Snpvoid t4_register_fw_msg_handler(int, fw_msg_handler_t); 1174346852Snpvoid t4_register_cpl_handler(int, cpl_handler_t); 1175346852Snpvoid t4_register_shared_cpl_handler(int, cpl_handler_t, int); 1176218792Snp 1177253691Snp/* t4_tracer.c */ 1178253691Snpstruct t4_tracer; 1179253691Snpvoid t4_tracer_modload(void); 1180253691Snpvoid t4_tracer_modunload(void); 1181253691Snpvoid t4_tracer_port_detach(struct adapter *); 1182253691Snpint t4_get_tracer(struct adapter *, struct t4_tracer *); 1183253691Snpint t4_set_tracer(struct adapter *, struct t4_tracer *); 1184253691Snpint t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1185253691Snpint t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1186253691Snp 1187318850Snp/* t4_sched.c */ 1188318850Snpint t4_set_sched_class(struct adapter *, struct t4_sched_params *); 1189318850Snpint t4_set_sched_queue(struct adapter *, struct t4_sched_queue *); 1190318850Snpint t4_init_tx_sched(struct adapter *); 1191318850Snpint t4_free_tx_sched(struct adapter *); 1192318850Snpvoid t4_update_tx_sched(struct adapter *); 1193318850Snpint t4_reserve_cl_rl_kbps(struct adapter *, int, u_int, int *); 1194346871Snpvoid t4_release_cl_rl(struct adapter *, int, int); 1195346871Snpint sysctl_tc(SYSCTL_HANDLER_ARGS); 1196346871Snpint sysctl_tc_params(SYSCTL_HANDLER_ARGS); 1197318850Snp 1198346855Snp/* t4_filter.c */ 1199346855Snpint get_filter_mode(struct adapter *, uint32_t *); 1200346855Snpint set_filter_mode(struct adapter *, uint32_t); 1201346855Snpint get_filter(struct adapter *, struct t4_filter *); 1202346855Snpint set_filter(struct adapter *, struct t4_filter *); 1203346855Snpint del_filter(struct adapter *, struct t4_filter *); 1204346855Snpint t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1205346855Snpint t4_hashfilter_ao_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1206346855Snpint t4_hashfilter_tcb_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1207346855Snpint t4_del_hashfilter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1208346855Snpvoid free_hftid_tab(struct tid_info *); 1209346855Snp 1210237263Snpstatic inline struct wrqe * 1211237263Snpalloc_wrqe(int wr_len, struct sge_wrq *wrq) 1212228561Snp{ 1213237263Snp int len = offsetof(struct wrqe, wr) + wr_len; 1214237263Snp struct wrqe *wr; 1215228561Snp 1216237263Snp wr = malloc(len, M_CXGBE, M_NOWAIT); 1217237263Snp if (__predict_false(wr == NULL)) 1218237263Snp return (NULL); 1219237263Snp wr->wr_len = wr_len; 1220237263Snp wr->wrq = wrq; 1221237263Snp return (wr); 1222237263Snp} 1223237263Snp 1224237263Snpstatic inline void * 1225237263Snpwrtod(struct wrqe *wr) 1226237263Snp{ 1227237263Snp return (&wr->wr[0]); 1228237263Snp} 1229237263Snp 1230237263Snpstatic inline void 1231237263Snpfree_wrqe(struct wrqe *wr) 1232237263Snp{ 1233237263Snp free(wr, M_CXGBE); 1234237263Snp} 1235237263Snp 1236237263Snpstatic inline void 1237237263Snpt4_wrq_tx(struct adapter *sc, struct wrqe *wr) 1238237263Snp{ 1239237263Snp struct sge_wrq *wrq = wr->wrq; 1240237263Snp 1241228561Snp TXQ_LOCK(wrq); 1242237263Snp t4_wrq_tx_locked(sc, wrq, wr); 1243228561Snp TXQ_UNLOCK(wrq); 1244228561Snp} 1245228561Snp 1246346848Snpstatic inline int 1247346848Snpread_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val, 1248346848Snp int len) 1249346848Snp{ 1250346848Snp 1251346848Snp return (rw_via_memwin(sc, idx, addr, val, len, 0)); 1252346848Snp} 1253346848Snp 1254346848Snpstatic inline int 1255346848Snpwrite_via_memwin(struct adapter *sc, int idx, uint32_t addr, 1256346848Snp const uint32_t *val, int len) 1257346848Snp{ 1258346848Snp 1259346848Snp return (rw_via_memwin(sc, idx, addr, (void *)(uintptr_t)val, len, 1)); 1260346848Snp} 1261218792Snp#endif 1262