adapter.h revision 318850
1261268Sjhb/*- 2330449Seadler * Copyright (c) 2011 Chelsio Communications, Inc. 3330449Seadler * All rights reserved. 4281887Sjhb * Written by: Navdeep Parhar <np@FreeBSD.org> 5261268Sjhb * 6261268Sjhb * Redistribution and use in source and binary forms, with or without 7261268Sjhb * modification, are permitted provided that the following conditions 8261268Sjhb * are met: 9261268Sjhb * 1. Redistributions of source code must retain the above copyright 10261268Sjhb * notice, this list of conditions and the following disclaimer. 11261268Sjhb * 2. Redistributions in binary form must reproduce the above copyright 12261268Sjhb * notice, this list of conditions and the following disclaimer in the 13261268Sjhb * documentation and/or other materials provided with the distribution. 14261268Sjhb * 15261268Sjhb * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16261268Sjhb * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17261268Sjhb * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18261268Sjhb * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19261268Sjhb * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20261268Sjhb * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21261268Sjhb * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22261268Sjhb * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23261268Sjhb * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24261268Sjhb * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25261268Sjhb * SUCH DAMAGE. 26261268Sjhb * 27261268Sjhb * $FreeBSD: stable/11/sys/dev/cxgbe/adapter.h 318850 2017-05-25 01:40:40Z np $ 28261268Sjhb * 29261268Sjhb */ 30261268Sjhb 31261268Sjhb#ifndef __T4_ADAPTER_H__ 32261268Sjhb#define __T4_ADAPTER_H__ 33261268Sjhb 34261268Sjhb#include <sys/kernel.h> 35321411Smav#include <sys/bus.h> 36321411Smav#include <sys/rman.h> 37261268Sjhb#include <sys/types.h> 38261268Sjhb#include <sys/lock.h> 39261268Sjhb#include <sys/malloc.h> 40261268Sjhb#include <sys/rwlock.h> 41321411Smav#include <sys/sx.h> 42261268Sjhb#include <vm/uma.h> 43261268Sjhb 44#include <dev/pci/pcivar.h> 45#include <dev/pci/pcireg.h> 46#include <machine/bus.h> 47#include <sys/socket.h> 48#include <sys/sysctl.h> 49#include <net/ethernet.h> 50#include <net/if.h> 51#include <net/if_var.h> 52#include <net/if_media.h> 53#include <netinet/in.h> 54#include <netinet/tcp_lro.h> 55 56#include "offload.h" 57#include "t4_ioctl.h" 58#include "common/t4_msg.h" 59#include "firmware/t4fw_interface.h" 60 61#define KTR_CXGBE KTR_SPARE3 62MALLOC_DECLARE(M_CXGBE); 63#define CXGBE_UNIMPLEMENTED(s) \ 64 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__) 65 66#if defined(__i386__) || defined(__amd64__) 67static __inline void 68prefetch(void *x) 69{ 70 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 71} 72#else 73#define prefetch(x) 74#endif 75 76#ifndef SYSCTL_ADD_UQUAD 77#define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 78#define sysctl_handle_64 sysctl_handle_quad 79#define CTLTYPE_U64 CTLTYPE_QUAD 80#endif 81 82#if (__FreeBSD_version >= 900030) || \ 83 ((__FreeBSD_version >= 802507) && (__FreeBSD_version < 900000)) 84#define SBUF_DRAIN 1 85#endif 86 87struct adapter; 88typedef struct adapter adapter_t; 89 90enum { 91 /* 92 * All ingress queues use this entry size. Note that the firmware event 93 * queue and any iq expecting CPL_RX_PKT in the descriptor needs this to 94 * be at least 64. 95 */ 96 IQ_ESIZE = 64, 97 98 /* Default queue sizes for all kinds of ingress queues */ 99 FW_IQ_QSIZE = 256, 100 RX_IQ_QSIZE = 1024, 101 102 /* All egress queues use this entry size */ 103 EQ_ESIZE = 64, 104 105 /* Default queue sizes for all kinds of egress queues */ 106 CTRL_EQ_QSIZE = 128, 107 TX_EQ_QSIZE = 1024, 108 109#if MJUMPAGESIZE != MCLBYTES 110 SW_ZONE_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */ 111#else 112 SW_ZONE_SIZES = 3, /* cluster, jumbo9k, jumbo16k */ 113#endif 114 CL_METADATA_SIZE = CACHE_LINE_SIZE, 115 116 SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / EQ_ESIZE, /* max WR size in desc */ 117 TX_SGL_SEGS = 39, 118 TX_SGL_SEGS_TSO = 38, 119 TX_WR_FLITS = SGE_MAX_WR_LEN / 8 120}; 121 122enum { 123 /* adapter intr_type */ 124 INTR_INTX = (1 << 0), 125 INTR_MSI = (1 << 1), 126 INTR_MSIX = (1 << 2) 127}; 128 129enum { 130 XGMAC_MTU = (1 << 0), 131 XGMAC_PROMISC = (1 << 1), 132 XGMAC_ALLMULTI = (1 << 2), 133 XGMAC_VLANEX = (1 << 3), 134 XGMAC_UCADDR = (1 << 4), 135 XGMAC_MCADDRS = (1 << 5), 136 137 XGMAC_ALL = 0xffff 138}; 139 140enum { 141 /* flags understood by begin_synchronized_op */ 142 HOLD_LOCK = (1 << 0), 143 SLEEP_OK = (1 << 1), 144 INTR_OK = (1 << 2), 145 146 /* flags understood by end_synchronized_op */ 147 LOCK_HELD = HOLD_LOCK, 148}; 149 150enum { 151 /* adapter flags */ 152 FULL_INIT_DONE = (1 << 0), 153 FW_OK = (1 << 1), 154 /* INTR_DIRECT = (1 << 2), No longer used. */ 155 MASTER_PF = (1 << 3), 156 ADAP_SYSCTL_CTX = (1 << 4), 157 /* TOM_INIT_DONE= (1 << 5), No longer used */ 158 BUF_PACKING_OK = (1 << 6), 159 IS_VF = (1 << 7), 160 161 CXGBE_BUSY = (1 << 9), 162 163 /* port flags */ 164 HAS_TRACEQ = (1 << 3), 165 166 /* VI flags */ 167 DOOMED = (1 << 0), 168 VI_INIT_DONE = (1 << 1), 169 VI_SYSCTL_CTX = (1 << 2), 170 INTR_RXQ = (1 << 4), /* All NIC rxq's take interrupts */ 171 INTR_OFLD_RXQ = (1 << 5), /* All TOE rxq's take interrupts */ 172 INTR_ALL = (INTR_RXQ | INTR_OFLD_RXQ), 173 174 /* adapter debug_flags */ 175 DF_DUMP_MBOX = (1 << 0), 176}; 177 178#define IS_DOOMED(vi) ((vi)->flags & DOOMED) 179#define SET_DOOMED(vi) do {(vi)->flags |= DOOMED;} while (0) 180#define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY) 181#define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0) 182#define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0) 183 184struct vi_info { 185 device_t dev; 186 struct port_info *pi; 187 188 struct ifnet *ifp; 189 struct ifmedia media; 190 191 unsigned long flags; 192 int if_flags; 193 194 uint16_t *rss, *nm_rss; 195 int smt_idx; /* for convenience */ 196 uint16_t viid; 197 int16_t xact_addr_filt;/* index of exact MAC address filter */ 198 uint16_t rss_size; /* size of VI's RSS table slice */ 199 uint16_t rss_base; /* start of VI's RSS table slice */ 200 201 eventhandler_tag vlan_c; 202 203 int nintr; 204 int first_intr; 205 206 /* These need to be int as they are used in sysctl */ 207 int ntxq; /* # of tx queues */ 208 int first_txq; /* index of first tx queue */ 209 int rsrv_noflowq; /* Reserve queue 0 for non-flowid packets */ 210 int nrxq; /* # of rx queues */ 211 int first_rxq; /* index of first rx queue */ 212 int nofldtxq; /* # of offload tx queues */ 213 int first_ofld_txq; /* index of first offload tx queue */ 214 int nofldrxq; /* # of offload rx queues */ 215 int first_ofld_rxq; /* index of first offload rx queue */ 216 int nnmtxq; 217 int first_nm_txq; 218 int nnmrxq; 219 int first_nm_rxq; 220 int tmr_idx; 221 int pktc_idx; 222 int qsize_rxq; 223 int qsize_txq; 224 225 struct timeval last_refreshed; 226 struct fw_vi_stats_vf stats; 227 228 struct callout tick; 229 struct sysctl_ctx_list ctx; /* from ifconfig up to driver detach */ 230 231 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */ 232}; 233 234struct tx_ch_rl_params { 235 enum fw_sched_params_rate ratemode; /* %port (REL) or kbps (ABS) */ 236 uint32_t maxrate; 237}; 238 239enum { 240 TX_CLRL_REFRESH = (1 << 0), /* Need to update hardware state. */ 241 TX_CLRL_ERROR = (1 << 1), /* Error, hardware state unknown. */ 242}; 243 244struct tx_cl_rl_params { 245 int refcount; 246 u_int flags; 247 enum fw_sched_params_rate ratemode; /* %port REL or ABS value */ 248 enum fw_sched_params_unit rateunit; /* kbps or pps (when ABS) */ 249 enum fw_sched_params_mode mode; /* aggr or per-flow */ 250 uint32_t maxrate; 251 uint16_t pktsize; 252}; 253 254/* Tx scheduler parameters for a channel/port */ 255struct tx_sched_params { 256 /* Channel Rate Limiter */ 257 struct tx_ch_rl_params ch_rl; 258 259 /* Class WRR */ 260 /* XXX */ 261 262 /* Class Rate Limiter */ 263 struct tx_cl_rl_params cl_rl[]; 264}; 265 266struct port_info { 267 device_t dev; 268 struct adapter *adapter; 269 270 struct vi_info *vi; 271 int nvi; 272 int up_vis; 273 int uld_vis; 274 275 struct tx_sched_params *sched_params; 276 277 struct mtx pi_lock; 278 char lockname[16]; 279 unsigned long flags; 280 281 uint8_t lport; /* associated offload logical port */ 282 int8_t mdio_addr; 283 uint8_t port_type; 284 uint8_t mod_type; 285 uint8_t port_id; 286 uint8_t tx_chan; 287 uint8_t rx_chan_map; /* rx MPS channel bitmap */ 288 289 struct link_config link_cfg; 290 291 struct timeval last_refreshed; 292 struct port_stats stats; 293 u_int tnl_cong_drops; 294 u_int tx_parse_error; 295 296 struct callout tick; 297}; 298 299#define IS_MAIN_VI(vi) ((vi) == &((vi)->pi->vi[0])) 300 301/* Where the cluster came from, how it has been carved up. */ 302struct cluster_layout { 303 int8_t zidx; 304 int8_t hwidx; 305 uint16_t region1; /* mbufs laid out within this region */ 306 /* region2 is the DMA region */ 307 uint16_t region3; /* cluster_metadata within this region */ 308}; 309 310struct cluster_metadata { 311 u_int refcount; 312 struct fl_sdesc *sd; /* For debug only. Could easily be stale */ 313}; 314 315struct fl_sdesc { 316 caddr_t cl; 317 uint16_t nmbuf; /* # of driver originated mbufs with ref on cluster */ 318 struct cluster_layout cll; 319}; 320 321struct tx_desc { 322 __be64 flit[8]; 323}; 324 325struct tx_sdesc { 326 struct mbuf *m; /* m_nextpkt linked chain of frames */ 327 uint8_t desc_used; /* # of hardware descriptors used by the WR */ 328}; 329 330 331#define IQ_PAD (IQ_ESIZE - sizeof(struct rsp_ctrl) - sizeof(struct rss_header)) 332struct iq_desc { 333 struct rss_header rss; 334 uint8_t cpl[IQ_PAD]; 335 struct rsp_ctrl rsp; 336}; 337#undef IQ_PAD 338CTASSERT(sizeof(struct iq_desc) == IQ_ESIZE); 339 340enum { 341 /* iq flags */ 342 IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */ 343 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */ 344 IQ_INTR = (1 << 2), /* iq takes direct interrupt */ 345 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */ 346 IQ_ADJ_CREDIT = (1 << 4), /* hw is off by 1 credit for this iq */ 347 348 /* iq state */ 349 IQS_DISABLED = 0, 350 IQS_BUSY = 1, 351 IQS_IDLE = 2, 352 353 /* netmap related flags */ 354 NM_OFF = 0, 355 NM_ON = 1, 356 NM_BUSY = 2, 357}; 358 359struct sge_iq; 360struct rss_header; 361typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *, 362 struct mbuf *); 363typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *); 364typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *); 365 366/* 367 * Ingress Queue: T4 is producer, driver is consumer. 368 */ 369struct sge_iq { 370 uint32_t flags; 371 volatile int state; 372 struct adapter *adapter; 373 cpl_handler_t set_tcb_rpl; 374 cpl_handler_t l2t_write_rpl; 375 struct iq_desc *desc; /* KVA of descriptor ring */ 376 int8_t intr_pktc_idx; /* packet count threshold index */ 377 uint8_t gen; /* generation bit */ 378 uint8_t intr_params; /* interrupt holdoff parameters */ 379 uint8_t intr_next; /* XXX: holdoff for next interrupt */ 380 uint16_t qsize; /* size (# of entries) of the queue */ 381 uint16_t sidx; /* index of the entry with the status page */ 382 uint16_t cidx; /* consumer index */ 383 uint16_t cntxt_id; /* SGE context id for the iq */ 384 uint16_t abs_id; /* absolute SGE id for the iq */ 385 386 STAILQ_ENTRY(sge_iq) link; 387 388 bus_dma_tag_t desc_tag; 389 bus_dmamap_t desc_map; 390 bus_addr_t ba; /* bus address of descriptor ring */ 391}; 392 393enum { 394 EQ_CTRL = 1, 395 EQ_ETH = 2, 396 EQ_OFLD = 3, 397 398 /* eq flags */ 399 EQ_TYPEMASK = 0x3, /* 2 lsbits hold the type (see above) */ 400 EQ_ALLOCATED = (1 << 2), /* firmware resources allocated */ 401 EQ_ENABLED = (1 << 3), /* open for business */ 402}; 403 404/* Listed in order of preference. Update t4_sysctls too if you change these */ 405enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB}; 406 407/* 408 * Egress Queue: driver is producer, T4 is consumer. 409 * 410 * Note: A free list is an egress queue (driver produces the buffers and T4 411 * consumes them) but it's special enough to have its own struct (see sge_fl). 412 */ 413struct sge_eq { 414 unsigned int flags; /* MUST be first */ 415 unsigned int cntxt_id; /* SGE context id for the eq */ 416 unsigned int abs_id; /* absolute SGE id for the eq */ 417 struct mtx eq_lock; 418 419 struct tx_desc *desc; /* KVA of descriptor ring */ 420 uint16_t doorbells; 421 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */ 422 u_int udb_qid; /* relative qid within the doorbell page */ 423 uint16_t sidx; /* index of the entry with the status page */ 424 uint16_t cidx; /* consumer idx (desc idx) */ 425 uint16_t pidx; /* producer idx (desc idx) */ 426 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 427 uint16_t dbidx; /* pidx of the most recent doorbell */ 428 uint16_t iqid; /* iq that gets egr_update for the eq */ 429 uint8_t tx_chan; /* tx channel used by the eq */ 430 volatile u_int equiq; /* EQUIQ outstanding */ 431 432 bus_dma_tag_t desc_tag; 433 bus_dmamap_t desc_map; 434 bus_addr_t ba; /* bus address of descriptor ring */ 435 char lockname[16]; 436}; 437 438struct sw_zone_info { 439 uma_zone_t zone; /* zone that this cluster comes from */ 440 int size; /* size of cluster: 2K, 4K, 9K, 16K, etc. */ 441 int type; /* EXT_xxx type of the cluster */ 442 int8_t head_hwidx; 443 int8_t tail_hwidx; 444}; 445 446struct hw_buf_info { 447 int8_t zidx; /* backpointer to zone; -ve means unused */ 448 int8_t next; /* next hwidx for this zone; -1 means no more */ 449 int size; 450}; 451 452enum { 453 NUM_MEMWIN = 3, 454 455 MEMWIN0_APERTURE = 2048, 456 MEMWIN0_BASE = 0x1b800, 457 458 MEMWIN1_APERTURE = 32768, 459 MEMWIN1_BASE = 0x28000, 460 461 MEMWIN2_APERTURE_T4 = 65536, 462 MEMWIN2_BASE_T4 = 0x30000, 463 464 MEMWIN2_APERTURE_T5 = 128 * 1024, 465 MEMWIN2_BASE_T5 = 0x60000, 466}; 467 468struct memwin { 469 struct rwlock mw_lock __aligned(CACHE_LINE_SIZE); 470 uint32_t mw_base; /* constant after setup_memwin */ 471 uint32_t mw_aperture; /* ditto */ 472 uint32_t mw_curpos; /* protected by mw_lock */ 473}; 474 475enum { 476 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */ 477 FL_DOOMED = (1 << 1), /* about to be destroyed */ 478 FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */ 479 FL_BUF_RESUME = (1 << 3), /* resume from the middle of the frame */ 480}; 481 482#define FL_RUNNING_LOW(fl) \ 483 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) <= fl->lowat) 484#define FL_NOT_RUNNING_LOW(fl) \ 485 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) >= 2 * fl->lowat) 486 487struct sge_fl { 488 struct mtx fl_lock; 489 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */ 490 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */ 491 struct cluster_layout cll_def; /* default refill zone, layout */ 492 uint16_t lowat; /* # of buffers <= this means fl needs help */ 493 int flags; 494 uint16_t buf_boundary; 495 496 /* The 16b idx all deal with hw descriptors */ 497 uint16_t dbidx; /* hw pidx after last doorbell */ 498 uint16_t sidx; /* index of status page */ 499 volatile uint16_t hw_cidx; 500 501 /* The 32b idx are all buffer idx, not hardware descriptor idx */ 502 uint32_t cidx; /* consumer index */ 503 uint32_t pidx; /* producer index */ 504 505 uint32_t dbval; 506 u_int rx_offset; /* offset in fl buf (when buffer packing) */ 507 volatile uint32_t *udb; 508 509 uint64_t mbuf_allocated;/* # of mbuf allocated from zone_mbuf */ 510 uint64_t mbuf_inlined; /* # of mbuf created within clusters */ 511 uint64_t cl_allocated; /* # of clusters allocated */ 512 uint64_t cl_recycled; /* # of clusters recycled */ 513 uint64_t cl_fast_recycled; /* # of clusters recycled (fast) */ 514 515 /* These 3 are valid when FL_BUF_RESUME is set, stale otherwise. */ 516 struct mbuf *m0; 517 struct mbuf **pnext; 518 u_int remaining; 519 520 uint16_t qsize; /* # of hw descriptors (status page included) */ 521 uint16_t cntxt_id; /* SGE context id for the freelist */ 522 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */ 523 bus_dma_tag_t desc_tag; 524 bus_dmamap_t desc_map; 525 char lockname[16]; 526 bus_addr_t ba; /* bus address of descriptor ring */ 527 struct cluster_layout cll_alt; /* alternate refill zone, layout */ 528}; 529 530struct mp_ring; 531 532/* txq: SGE egress queue + what's needed for Ethernet NIC */ 533struct sge_txq { 534 struct sge_eq eq; /* MUST be first */ 535 536 struct ifnet *ifp; /* the interface this txq belongs to */ 537 struct mp_ring *r; /* tx software ring */ 538 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */ 539 struct sglist *gl; 540 __be32 cpl_ctrl0; /* for convenience */ 541 int tc_idx; /* traffic class */ 542 543 struct task tx_reclaim_task; 544 /* stats for common events first */ 545 546 uint64_t txcsum; /* # of times hardware assisted with checksum */ 547 uint64_t tso_wrs; /* # of TSO work requests */ 548 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */ 549 uint64_t imm_wrs; /* # of work requests with immediate data */ 550 uint64_t sgl_wrs; /* # of work requests with direct SGL */ 551 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */ 552 uint64_t txpkts0_wrs; /* # of type0 coalesced tx work requests */ 553 uint64_t txpkts1_wrs; /* # of type1 coalesced tx work requests */ 554 uint64_t txpkts0_pkts; /* # of frames in type0 coalesced tx WRs */ 555 uint64_t txpkts1_pkts; /* # of frames in type1 coalesced tx WRs */ 556 557 /* stats for not-that-common events */ 558} __aligned(CACHE_LINE_SIZE); 559 560/* rxq: SGE ingress queue + SGE free list + miscellaneous items */ 561struct sge_rxq { 562 struct sge_iq iq; /* MUST be first */ 563 struct sge_fl fl; /* MUST follow iq */ 564 565 struct ifnet *ifp; /* the interface this rxq belongs to */ 566#if defined(INET) || defined(INET6) 567 struct lro_ctrl lro; /* LRO state */ 568#endif 569 570 /* stats for common events first */ 571 572 uint64_t rxcsum; /* # of times hardware assisted with checksum */ 573 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */ 574 575 /* stats for not-that-common events */ 576 577} __aligned(CACHE_LINE_SIZE); 578 579static inline struct sge_rxq * 580iq_to_rxq(struct sge_iq *iq) 581{ 582 583 return (__containerof(iq, struct sge_rxq, iq)); 584} 585 586 587/* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */ 588struct sge_ofld_rxq { 589 struct sge_iq iq; /* MUST be first */ 590 struct sge_fl fl; /* MUST follow iq */ 591} __aligned(CACHE_LINE_SIZE); 592 593static inline struct sge_ofld_rxq * 594iq_to_ofld_rxq(struct sge_iq *iq) 595{ 596 597 return (__containerof(iq, struct sge_ofld_rxq, iq)); 598} 599 600struct wrqe { 601 STAILQ_ENTRY(wrqe) link; 602 struct sge_wrq *wrq; 603 int wr_len; 604 char wr[] __aligned(16); 605}; 606 607struct wrq_cookie { 608 TAILQ_ENTRY(wrq_cookie) link; 609 int ndesc; 610 int pidx; 611}; 612 613/* 614 * wrq: SGE egress queue that is given prebuilt work requests. Both the control 615 * and offload tx queues are of this type. 616 */ 617struct sge_wrq { 618 struct sge_eq eq; /* MUST be first */ 619 620 struct adapter *adapter; 621 struct task wrq_tx_task; 622 623 /* Tx desc reserved but WR not "committed" yet. */ 624 TAILQ_HEAD(wrq_incomplete_wrs , wrq_cookie) incomplete_wrs; 625 626 /* List of WRs ready to go out as soon as descriptors are available. */ 627 STAILQ_HEAD(, wrqe) wr_list; 628 u_int nwr_pending; 629 u_int ndesc_needed; 630 631 /* stats for common events first */ 632 633 uint64_t tx_wrs_direct; /* # of WRs written directly to desc ring. */ 634 uint64_t tx_wrs_ss; /* # of WRs copied from scratch space. */ 635 uint64_t tx_wrs_copied; /* # of WRs queued and copied to desc ring. */ 636 637 /* stats for not-that-common events */ 638 639 /* 640 * Scratch space for work requests that wrap around after reaching the 641 * status page, and some information about the last WR that used it. 642 */ 643 uint16_t ss_pidx; 644 uint16_t ss_len; 645 uint8_t ss[SGE_MAX_WR_LEN]; 646 647} __aligned(CACHE_LINE_SIZE); 648 649 650struct sge_nm_rxq { 651 struct vi_info *vi; 652 653 struct iq_desc *iq_desc; 654 uint16_t iq_abs_id; 655 uint16_t iq_cntxt_id; 656 uint16_t iq_cidx; 657 uint16_t iq_sidx; 658 uint8_t iq_gen; 659 660 __be64 *fl_desc; 661 uint16_t fl_cntxt_id; 662 uint32_t fl_cidx; 663 uint32_t fl_pidx; 664 uint32_t fl_sidx; 665 uint32_t fl_db_val; 666 u_int fl_hwidx:4; 667 668 u_int nid; /* netmap ring # for this queue */ 669 670 /* infrequently used items after this */ 671 672 bus_dma_tag_t iq_desc_tag; 673 bus_dmamap_t iq_desc_map; 674 bus_addr_t iq_ba; 675 int intr_idx; 676 677 bus_dma_tag_t fl_desc_tag; 678 bus_dmamap_t fl_desc_map; 679 bus_addr_t fl_ba; 680} __aligned(CACHE_LINE_SIZE); 681 682struct sge_nm_txq { 683 struct tx_desc *desc; 684 uint16_t cidx; 685 uint16_t pidx; 686 uint16_t sidx; 687 uint16_t equiqidx; /* EQUIQ last requested at this pidx */ 688 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 689 uint16_t dbidx; /* pidx of the most recent doorbell */ 690 uint16_t doorbells; 691 volatile uint32_t *udb; 692 u_int udb_qid; 693 u_int cntxt_id; 694 __be32 cpl_ctrl0; /* for convenience */ 695 u_int nid; /* netmap ring # for this queue */ 696 697 /* infrequently used items after this */ 698 699 bus_dma_tag_t desc_tag; 700 bus_dmamap_t desc_map; 701 bus_addr_t ba; 702 int iqidx; 703} __aligned(CACHE_LINE_SIZE); 704 705struct sge { 706 int nrxq; /* total # of Ethernet rx queues */ 707 int ntxq; /* total # of Ethernet tx tx queues */ 708 int nofldrxq; /* total # of TOE rx queues */ 709 int nofldtxq; /* total # of TOE tx queues */ 710 int nnmrxq; /* total # of netmap rx queues */ 711 int nnmtxq; /* total # of netmap tx queues */ 712 int niq; /* total # of ingress queues */ 713 int neq; /* total # of egress queues */ 714 715 struct sge_iq fwq; /* Firmware event queue */ 716 struct sge_wrq mgmtq; /* Management queue (control queue) */ 717 struct sge_wrq *ctrlq; /* Control queues */ 718 struct sge_txq *txq; /* NIC tx queues */ 719 struct sge_rxq *rxq; /* NIC rx queues */ 720 struct sge_wrq *ofld_txq; /* TOE tx queues */ 721 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */ 722 struct sge_nm_txq *nm_txq; /* netmap tx queues */ 723 struct sge_nm_rxq *nm_rxq; /* netmap rx queues */ 724 725 uint16_t iq_start; /* first cntxt_id */ 726 uint16_t iq_base; /* first abs_id */ 727 int eq_start; /* first cntxt_id */ 728 int eq_base; /* first abs_id */ 729 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */ 730 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */ 731 732 int8_t safe_hwidx1; /* may not have room for metadata */ 733 int8_t safe_hwidx2; /* with room for metadata and maybe more */ 734 struct sw_zone_info sw_zone_info[SW_ZONE_SIZES]; 735 struct hw_buf_info hw_buf_info[SGE_FLBUF_SIZES]; 736}; 737 738struct devnames { 739 const char *nexus_name; 740 const char *ifnet_name; 741 const char *vi_ifnet_name; 742 const char *pf03_drv_name; 743 const char *vf_nexus_name; 744 const char *vf_ifnet_name; 745}; 746 747struct adapter { 748 SLIST_ENTRY(adapter) link; 749 device_t dev; 750 struct cdev *cdev; 751 const struct devnames *names; 752 753 /* PCIe register resources */ 754 int regs_rid; 755 struct resource *regs_res; 756 int msix_rid; 757 struct resource *msix_res; 758 bus_space_handle_t bh; 759 bus_space_tag_t bt; 760 bus_size_t mmio_len; 761 int udbs_rid; 762 struct resource *udbs_res; 763 volatile uint8_t *udbs_base; 764 765 unsigned int pf; 766 unsigned int mbox; 767 unsigned int vpd_busy; 768 unsigned int vpd_flag; 769 770 /* Interrupt information */ 771 int intr_type; 772 int intr_count; 773 struct irq { 774 struct resource *res; 775 int rid; 776 volatile int nm_state; /* NM_OFF, NM_ON, or NM_BUSY */ 777 void *tag; 778 struct sge_rxq *rxq; 779 struct sge_nm_rxq *nm_rxq; 780 } __aligned(CACHE_LINE_SIZE) *irq; 781 int sge_gts_reg; 782 int sge_kdoorbell_reg; 783 784 bus_dma_tag_t dmat; /* Parent DMA tag */ 785 786 struct sge sge; 787 int lro_timeout; 788 int sc_do_rxcopy; 789 790 struct taskqueue *tq[MAX_NCHAN]; /* General purpose taskqueues */ 791 struct port_info *port[MAX_NPORTS]; 792 uint8_t chan_map[MAX_NCHAN]; 793 794 void *tom_softc; /* (struct tom_data *) */ 795 struct tom_tunables tt; 796 void *iwarp_softc; /* (struct c4iw_dev *) */ 797 void *iscsi_ulp_softc; /* (struct cxgbei_data *) */ 798 struct l2t_data *l2t; /* L2 table */ 799 struct tid_info tids; 800 801 uint16_t doorbells; 802 int offload_map; /* ports with IFCAP_TOE enabled */ 803 int active_ulds; /* ULDs activated on this adapter */ 804 int flags; 805 int debug_flags; 806 807 char ifp_lockname[16]; 808 struct mtx ifp_lock; 809 struct ifnet *ifp; /* tracer ifp */ 810 struct ifmedia media; 811 int traceq; /* iq used by all tracers, -1 if none */ 812 int tracer_valid; /* bitmap of valid tracers */ 813 int tracer_enabled; /* bitmap of enabled tracers */ 814 815 char fw_version[16]; 816 char tp_version[16]; 817 char er_version[16]; 818 char bs_version[16]; 819 char cfg_file[32]; 820 u_int cfcsum; 821 struct adapter_params params; 822 const struct chip_params *chip_params; 823 struct t4_virt_res vres; 824 825 uint16_t nbmcaps; 826 uint16_t linkcaps; 827 uint16_t switchcaps; 828 uint16_t niccaps; 829 uint16_t toecaps; 830 uint16_t rdmacaps; 831 uint16_t cryptocaps; 832 uint16_t iscsicaps; 833 uint16_t fcoecaps; 834 835 struct sysctl_ctx_list ctx; /* from adapter_full_init to full_uninit */ 836 837 struct mtx sc_lock; 838 char lockname[16]; 839 840 /* Starving free lists */ 841 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */ 842 TAILQ_HEAD(, sge_fl) sfl; 843 struct callout sfl_callout; 844 845 struct mtx reg_lock; /* for indirect register access */ 846 847 struct memwin memwin[NUM_MEMWIN]; /* memory windows */ 848 849 struct mtx tc_lock; 850 struct task tc_task; 851 852 const char *last_op; 853 const void *last_op_thr; 854 int last_op_flags; 855}; 856 857#define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock) 858#define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock) 859#define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED) 860#define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED) 861 862#define ASSERT_SYNCHRONIZED_OP(sc) \ 863 KASSERT(IS_BUSY(sc) && \ 864 (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \ 865 ("%s: operation not synchronized.", __func__)) 866 867#define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock) 868#define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock) 869#define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED) 870#define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED) 871 872#define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock) 873#define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock) 874#define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock) 875#define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED) 876#define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED) 877 878#define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl) 879#define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl) 880#define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl) 881#define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl) 882 883#define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock) 884#define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock) 885#define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock) 886#define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED) 887#define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED) 888 889#define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq) 890#define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq) 891#define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq) 892#define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq) 893#define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq) 894 895#define CH_DUMP_MBOX(sc, mbox, data_reg) \ 896 do { \ 897 if (sc->debug_flags & DF_DUMP_MBOX) { \ 898 log(LOG_NOTICE, \ 899 "%s mbox %u: %016llx %016llx %016llx %016llx " \ 900 "%016llx %016llx %016llx %016llx\n", \ 901 device_get_nameunit(sc->dev), mbox, \ 902 (unsigned long long)t4_read_reg64(sc, data_reg), \ 903 (unsigned long long)t4_read_reg64(sc, data_reg + 8), \ 904 (unsigned long long)t4_read_reg64(sc, data_reg + 16), \ 905 (unsigned long long)t4_read_reg64(sc, data_reg + 24), \ 906 (unsigned long long)t4_read_reg64(sc, data_reg + 32), \ 907 (unsigned long long)t4_read_reg64(sc, data_reg + 40), \ 908 (unsigned long long)t4_read_reg64(sc, data_reg + 48), \ 909 (unsigned long long)t4_read_reg64(sc, data_reg + 56)); \ 910 } \ 911 } while (0) 912 913#define for_each_txq(vi, iter, q) \ 914 for (q = &vi->pi->adapter->sge.txq[vi->first_txq], iter = 0; \ 915 iter < vi->ntxq; ++iter, ++q) 916#define for_each_rxq(vi, iter, q) \ 917 for (q = &vi->pi->adapter->sge.rxq[vi->first_rxq], iter = 0; \ 918 iter < vi->nrxq; ++iter, ++q) 919#define for_each_ofld_txq(vi, iter, q) \ 920 for (q = &vi->pi->adapter->sge.ofld_txq[vi->first_ofld_txq], iter = 0; \ 921 iter < vi->nofldtxq; ++iter, ++q) 922#define for_each_ofld_rxq(vi, iter, q) \ 923 for (q = &vi->pi->adapter->sge.ofld_rxq[vi->first_ofld_rxq], iter = 0; \ 924 iter < vi->nofldrxq; ++iter, ++q) 925#define for_each_nm_txq(vi, iter, q) \ 926 for (q = &vi->pi->adapter->sge.nm_txq[vi->first_nm_txq], iter = 0; \ 927 iter < vi->nnmtxq; ++iter, ++q) 928#define for_each_nm_rxq(vi, iter, q) \ 929 for (q = &vi->pi->adapter->sge.nm_rxq[vi->first_nm_rxq], iter = 0; \ 930 iter < vi->nnmrxq; ++iter, ++q) 931#define for_each_vi(_pi, _iter, _vi) \ 932 for ((_vi) = (_pi)->vi, (_iter) = 0; (_iter) < (_pi)->nvi; \ 933 ++(_iter), ++(_vi)) 934 935#define IDXINCR(idx, incr, wrap) do { \ 936 idx = wrap - idx > incr ? idx + incr : incr - (wrap - idx); \ 937} while (0) 938#define IDXDIFF(head, tail, wrap) \ 939 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 940 941/* One for errors, one for firmware events */ 942#define T4_EXTRA_INTR 2 943 944/* One for firmware events */ 945#define T4VF_EXTRA_INTR 1 946 947static inline uint32_t 948t4_read_reg(struct adapter *sc, uint32_t reg) 949{ 950 951 return bus_space_read_4(sc->bt, sc->bh, reg); 952} 953 954static inline void 955t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val) 956{ 957 958 bus_space_write_4(sc->bt, sc->bh, reg, val); 959} 960 961static inline uint64_t 962t4_read_reg64(struct adapter *sc, uint32_t reg) 963{ 964 965#ifdef __LP64__ 966 return bus_space_read_8(sc->bt, sc->bh, reg); 967#else 968 return (uint64_t)bus_space_read_4(sc->bt, sc->bh, reg) + 969 ((uint64_t)bus_space_read_4(sc->bt, sc->bh, reg + 4) << 32); 970 971#endif 972} 973 974static inline void 975t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val) 976{ 977 978#ifdef __LP64__ 979 bus_space_write_8(sc->bt, sc->bh, reg, val); 980#else 981 bus_space_write_4(sc->bt, sc->bh, reg, val); 982 bus_space_write_4(sc->bt, sc->bh, reg + 4, val>> 32); 983#endif 984} 985 986static inline void 987t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val) 988{ 989 990 *val = pci_read_config(sc->dev, reg, 1); 991} 992 993static inline void 994t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val) 995{ 996 997 pci_write_config(sc->dev, reg, val, 1); 998} 999 1000static inline void 1001t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val) 1002{ 1003 1004 *val = pci_read_config(sc->dev, reg, 2); 1005} 1006 1007static inline void 1008t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val) 1009{ 1010 1011 pci_write_config(sc->dev, reg, val, 2); 1012} 1013 1014static inline void 1015t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val) 1016{ 1017 1018 *val = pci_read_config(sc->dev, reg, 4); 1019} 1020 1021static inline void 1022t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val) 1023{ 1024 1025 pci_write_config(sc->dev, reg, val, 4); 1026} 1027 1028static inline struct port_info * 1029adap2pinfo(struct adapter *sc, int idx) 1030{ 1031 1032 return (sc->port[idx]); 1033} 1034 1035static inline void 1036t4_os_set_hw_addr(struct adapter *sc, int idx, uint8_t hw_addr[]) 1037{ 1038 1039 bcopy(hw_addr, sc->port[idx]->vi[0].hw_addr, ETHER_ADDR_LEN); 1040} 1041 1042static inline bool 1043is_10G_port(const struct port_info *pi) 1044{ 1045 1046 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) != 0); 1047} 1048 1049static inline bool 1050is_25G_port(const struct port_info *pi) 1051{ 1052 1053 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_25G) != 0); 1054} 1055 1056static inline bool 1057is_40G_port(const struct port_info *pi) 1058{ 1059 1060 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G) != 0); 1061} 1062 1063static inline bool 1064is_100G_port(const struct port_info *pi) 1065{ 1066 1067 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_100G) != 0); 1068} 1069 1070static inline int 1071port_top_speed(const struct port_info *pi) 1072{ 1073 1074 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100G) 1075 return (100); 1076 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G) 1077 return (40); 1078 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_25G) 1079 return (25); 1080 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) 1081 return (10); 1082 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_1G) 1083 return (1); 1084 1085 return (0); 1086} 1087 1088static inline int 1089tx_resume_threshold(struct sge_eq *eq) 1090{ 1091 1092 /* not quite the same as qsize / 4, but this will do. */ 1093 return (eq->sidx / 4); 1094} 1095 1096static inline int 1097t4_use_ldst(struct adapter *sc) 1098{ 1099 1100#ifdef notyet 1101 return (sc->flags & FW_OK || !sc->use_bd); 1102#else 1103 return (0); 1104#endif 1105} 1106 1107/* t4_main.c */ 1108extern int t4_ntxq10g; 1109extern int t4_nrxq10g; 1110extern int t4_ntxq1g; 1111extern int t4_nrxq1g; 1112extern int t4_intr_types; 1113extern int t4_tmr_idx_10g; 1114extern int t4_pktc_idx_10g; 1115extern int t4_tmr_idx_1g; 1116extern int t4_pktc_idx_1g; 1117extern unsigned int t4_qsize_rxq; 1118extern unsigned int t4_qsize_txq; 1119extern device_method_t cxgbe_methods[]; 1120 1121int t4_os_find_pci_capability(struct adapter *, int); 1122int t4_os_pci_save_state(struct adapter *); 1123int t4_os_pci_restore_state(struct adapter *); 1124void t4_os_portmod_changed(const struct adapter *, int); 1125void t4_os_link_changed(struct adapter *, int, int); 1126void t4_iterate(void (*)(struct adapter *, void *), void *); 1127void t4_init_devnames(struct adapter *); 1128void t4_add_adapter(struct adapter *); 1129int t4_detach_common(device_t); 1130int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1131int t4_map_bars_0_and_4(struct adapter *); 1132int t4_map_bar_2(struct adapter *); 1133int t4_setup_intr_handlers(struct adapter *); 1134void t4_sysctls(struct adapter *); 1135int begin_synchronized_op(struct adapter *, struct vi_info *, int, char *); 1136void doom_vi(struct adapter *, struct vi_info *); 1137void end_synchronized_op(struct adapter *, int); 1138int update_mac_settings(struct ifnet *, int); 1139int adapter_full_init(struct adapter *); 1140int adapter_full_uninit(struct adapter *); 1141uint64_t cxgbe_get_counter(struct ifnet *, ift_counter); 1142int vi_full_init(struct vi_info *); 1143int vi_full_uninit(struct vi_info *); 1144void vi_sysctls(struct vi_info *); 1145void vi_tick(void *); 1146 1147#ifdef DEV_NETMAP 1148/* t4_netmap.c */ 1149void cxgbe_nm_attach(struct vi_info *); 1150void cxgbe_nm_detach(struct vi_info *); 1151void t4_nm_intr(void *); 1152#endif 1153 1154/* t4_sge.c */ 1155void t4_sge_modload(void); 1156void t4_sge_modunload(void); 1157uint64_t t4_sge_extfree_refs(void); 1158void t4_tweak_chip_settings(struct adapter *); 1159int t4_read_chip_settings(struct adapter *); 1160int t4_create_dma_tag(struct adapter *); 1161void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *, 1162 struct sysctl_oid_list *); 1163int t4_destroy_dma_tag(struct adapter *); 1164int t4_setup_adapter_queues(struct adapter *); 1165int t4_teardown_adapter_queues(struct adapter *); 1166int t4_setup_vi_queues(struct vi_info *); 1167int t4_teardown_vi_queues(struct vi_info *); 1168void t4_intr_all(void *); 1169void t4_intr(void *); 1170void t4_vi_intr(void *); 1171void t4_intr_err(void *); 1172void t4_intr_evt(void *); 1173void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *); 1174void t4_update_fl_bufsize(struct ifnet *); 1175int parse_pkt(struct adapter *, struct mbuf **); 1176void *start_wrq_wr(struct sge_wrq *, int, struct wrq_cookie *); 1177void commit_wrq_wr(struct sge_wrq *, void *, struct wrq_cookie *); 1178int tnl_cong(struct port_info *, int); 1179int t4_register_an_handler(an_handler_t); 1180int t4_register_fw_msg_handler(int, fw_msg_handler_t); 1181int t4_register_cpl_handler(int, cpl_handler_t); 1182 1183/* t4_tracer.c */ 1184struct t4_tracer; 1185void t4_tracer_modload(void); 1186void t4_tracer_modunload(void); 1187void t4_tracer_port_detach(struct adapter *); 1188int t4_get_tracer(struct adapter *, struct t4_tracer *); 1189int t4_set_tracer(struct adapter *, struct t4_tracer *); 1190int t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1191int t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1192 1193/* t4_sched.c */ 1194int t4_set_sched_class(struct adapter *, struct t4_sched_params *); 1195int t4_set_sched_queue(struct adapter *, struct t4_sched_queue *); 1196int t4_init_tx_sched(struct adapter *); 1197int t4_free_tx_sched(struct adapter *); 1198void t4_update_tx_sched(struct adapter *); 1199int t4_reserve_cl_rl_kbps(struct adapter *, int, u_int, int *); 1200void t4_release_cl_rl_kbps(struct adapter *, int, int); 1201 1202static inline struct wrqe * 1203alloc_wrqe(int wr_len, struct sge_wrq *wrq) 1204{ 1205 int len = offsetof(struct wrqe, wr) + wr_len; 1206 struct wrqe *wr; 1207 1208 wr = malloc(len, M_CXGBE, M_NOWAIT); 1209 if (__predict_false(wr == NULL)) 1210 return (NULL); 1211 wr->wr_len = wr_len; 1212 wr->wrq = wrq; 1213 return (wr); 1214} 1215 1216static inline void * 1217wrtod(struct wrqe *wr) 1218{ 1219 return (&wr->wr[0]); 1220} 1221 1222static inline void 1223free_wrqe(struct wrqe *wr) 1224{ 1225 free(wr, M_CXGBE); 1226} 1227 1228static inline void 1229t4_wrq_tx(struct adapter *sc, struct wrqe *wr) 1230{ 1231 struct sge_wrq *wrq = wr->wrq; 1232 1233 TXQ_LOCK(wrq); 1234 t4_wrq_tx_locked(sc, wrq, wr); 1235 TXQ_UNLOCK(wrq); 1236} 1237 1238#endif 1239