1167514Skmacy/************************************************************************** 2167514Skmacy 3167514SkmacyCopyright (c) 2007, Chelsio Inc. 4167514SkmacyAll rights reserved. 5167514Skmacy 6167514SkmacyRedistribution and use in source and binary forms, with or without 7167514Skmacymodification, are permitted provided that the following conditions are met: 8167514Skmacy 9167514Skmacy 1. Redistributions of source code must retain the above copyright notice, 10167514Skmacy this list of conditions and the following disclaimer. 11167514Skmacy 12170076Skmacy 2. Neither the name of the Chelsio Corporation nor the names of its 13167514Skmacy contributors may be used to endorse or promote products derived from 14167514Skmacy this software without specific prior written permission. 15167514Skmacy 16167514SkmacyTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17167514SkmacyAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18167514SkmacyIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19167514SkmacyARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 20167514SkmacyLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21167514SkmacyCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22167514SkmacySUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23167514SkmacyINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24167514SkmacyCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25167514SkmacyARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26167514SkmacyPOSSIBILITY OF SUCH DAMAGE. 27167514Skmacy 28167514Skmacy$FreeBSD$ 29167514Skmacy 30167514Skmacy***************************************************************************/ 31167514Skmacy 32167514Skmacy/* This file is automatically generated --- do not edit */ 33167514Skmacy 34167514Skmacy#ifndef _TCB_DEFS_H 35167514Skmacy#define _TCB_DEFS_H 36167514Skmacy 37167514Skmacy#define W_TCB_T_STATE 0 38167514Skmacy#define S_TCB_T_STATE 0 39167514Skmacy#define M_TCB_T_STATE 0xfULL 40167514Skmacy#define V_TCB_T_STATE(x) ((x) << S_TCB_T_STATE) 41167514Skmacy 42167514Skmacy#define W_TCB_TIMER 0 43167514Skmacy#define S_TCB_TIMER 4 44167514Skmacy#define M_TCB_TIMER 0x1ULL 45167514Skmacy#define V_TCB_TIMER(x) ((x) << S_TCB_TIMER) 46167514Skmacy 47167514Skmacy#define W_TCB_DACK_TIMER 0 48167514Skmacy#define S_TCB_DACK_TIMER 5 49167514Skmacy#define M_TCB_DACK_TIMER 0x1ULL 50167514Skmacy#define V_TCB_DACK_TIMER(x) ((x) << S_TCB_DACK_TIMER) 51167514Skmacy 52167514Skmacy#define W_TCB_DEL_FLAG 0 53167514Skmacy#define S_TCB_DEL_FLAG 6 54167514Skmacy#define M_TCB_DEL_FLAG 0x1ULL 55167514Skmacy#define V_TCB_DEL_FLAG(x) ((x) << S_TCB_DEL_FLAG) 56167514Skmacy 57167514Skmacy#define W_TCB_L2T_IX 0 58167514Skmacy#define S_TCB_L2T_IX 7 59167514Skmacy#define M_TCB_L2T_IX 0x7ffULL 60167514Skmacy#define V_TCB_L2T_IX(x) ((x) << S_TCB_L2T_IX) 61167514Skmacy 62167514Skmacy#define W_TCB_SMAC_SEL 0 63167514Skmacy#define S_TCB_SMAC_SEL 18 64167514Skmacy#define M_TCB_SMAC_SEL 0x3ULL 65167514Skmacy#define V_TCB_SMAC_SEL(x) ((x) << S_TCB_SMAC_SEL) 66167514Skmacy 67167514Skmacy#define W_TCB_TOS 0 68167514Skmacy#define S_TCB_TOS 20 69167514Skmacy#define M_TCB_TOS 0x3fULL 70167514Skmacy#define V_TCB_TOS(x) ((x) << S_TCB_TOS) 71167514Skmacy 72167514Skmacy#define W_TCB_MAX_RT 0 73167514Skmacy#define S_TCB_MAX_RT 26 74167514Skmacy#define M_TCB_MAX_RT 0xfULL 75167514Skmacy#define V_TCB_MAX_RT(x) ((x) << S_TCB_MAX_RT) 76167514Skmacy 77167514Skmacy#define W_TCB_T_RXTSHIFT 0 78167514Skmacy#define S_TCB_T_RXTSHIFT 30 79167514Skmacy#define M_TCB_T_RXTSHIFT 0xfULL 80167514Skmacy#define V_TCB_T_RXTSHIFT(x) ((x) << S_TCB_T_RXTSHIFT) 81167514Skmacy 82167514Skmacy#define W_TCB_T_DUPACKS 1 83167514Skmacy#define S_TCB_T_DUPACKS 2 84167514Skmacy#define M_TCB_T_DUPACKS 0xfULL 85167514Skmacy#define V_TCB_T_DUPACKS(x) ((x) << S_TCB_T_DUPACKS) 86167514Skmacy 87167514Skmacy#define W_TCB_T_MAXSEG 1 88167514Skmacy#define S_TCB_T_MAXSEG 6 89167514Skmacy#define M_TCB_T_MAXSEG 0xfULL 90167514Skmacy#define V_TCB_T_MAXSEG(x) ((x) << S_TCB_T_MAXSEG) 91167514Skmacy 92167514Skmacy#define W_TCB_T_FLAGS1 1 93167514Skmacy#define S_TCB_T_FLAGS1 10 94167514Skmacy#define M_TCB_T_FLAGS1 0xffffffffULL 95167514Skmacy#define V_TCB_T_FLAGS1(x) ((x) << S_TCB_T_FLAGS1) 96167514Skmacy 97167514Skmacy#define W_TCB_T_FLAGS2 2 98167514Skmacy#define S_TCB_T_FLAGS2 10 99167514Skmacy#define M_TCB_T_FLAGS2 0x7fULL 100167514Skmacy#define V_TCB_T_FLAGS2(x) ((x) << S_TCB_T_FLAGS2) 101167514Skmacy 102167514Skmacy#define W_TCB_SND_SCALE 2 103167514Skmacy#define S_TCB_SND_SCALE 17 104167514Skmacy#define M_TCB_SND_SCALE 0xfULL 105167514Skmacy#define V_TCB_SND_SCALE(x) ((x) << S_TCB_SND_SCALE) 106167514Skmacy 107167514Skmacy#define W_TCB_RCV_SCALE 2 108167514Skmacy#define S_TCB_RCV_SCALE 21 109167514Skmacy#define M_TCB_RCV_SCALE 0xfULL 110167514Skmacy#define V_TCB_RCV_SCALE(x) ((x) << S_TCB_RCV_SCALE) 111167514Skmacy 112167514Skmacy#define W_TCB_SND_UNA_RAW 2 113167514Skmacy#define S_TCB_SND_UNA_RAW 25 114167514Skmacy#define M_TCB_SND_UNA_RAW 0x7ffffffULL 115167514Skmacy#define V_TCB_SND_UNA_RAW(x) ((x) << S_TCB_SND_UNA_RAW) 116167514Skmacy 117167514Skmacy#define W_TCB_SND_NXT_RAW 3 118167514Skmacy#define S_TCB_SND_NXT_RAW 20 119167514Skmacy#define M_TCB_SND_NXT_RAW 0x7ffffffULL 120167514Skmacy#define V_TCB_SND_NXT_RAW(x) ((x) << S_TCB_SND_NXT_RAW) 121167514Skmacy 122167514Skmacy#define W_TCB_RCV_NXT 4 123167514Skmacy#define S_TCB_RCV_NXT 15 124167514Skmacy#define M_TCB_RCV_NXT 0xffffffffULL 125167514Skmacy#define V_TCB_RCV_NXT(x) ((x) << S_TCB_RCV_NXT) 126167514Skmacy 127167514Skmacy#define W_TCB_RCV_ADV 5 128167514Skmacy#define S_TCB_RCV_ADV 15 129167514Skmacy#define M_TCB_RCV_ADV 0xffffULL 130167514Skmacy#define V_TCB_RCV_ADV(x) ((x) << S_TCB_RCV_ADV) 131167514Skmacy 132167514Skmacy#define W_TCB_SND_MAX_RAW 5 133167514Skmacy#define S_TCB_SND_MAX_RAW 31 134167514Skmacy#define M_TCB_SND_MAX_RAW 0x7ffffffULL 135167514Skmacy#define V_TCB_SND_MAX_RAW(x) ((x) << S_TCB_SND_MAX_RAW) 136167514Skmacy 137167514Skmacy#define W_TCB_SND_CWND 6 138167514Skmacy#define S_TCB_SND_CWND 26 139167514Skmacy#define M_TCB_SND_CWND 0x7ffffffULL 140167514Skmacy#define V_TCB_SND_CWND(x) ((x) << S_TCB_SND_CWND) 141167514Skmacy 142167514Skmacy#define W_TCB_SND_SSTHRESH 7 143167514Skmacy#define S_TCB_SND_SSTHRESH 21 144167514Skmacy#define M_TCB_SND_SSTHRESH 0x7ffffffULL 145167514Skmacy#define V_TCB_SND_SSTHRESH(x) ((x) << S_TCB_SND_SSTHRESH) 146167514Skmacy 147167514Skmacy#define W_TCB_T_RTT_TS_RECENT_AGE 8 148167514Skmacy#define S_TCB_T_RTT_TS_RECENT_AGE 16 149167514Skmacy#define M_TCB_T_RTT_TS_RECENT_AGE 0xffffffffULL 150167514Skmacy#define V_TCB_T_RTT_TS_RECENT_AGE(x) ((x) << S_TCB_T_RTT_TS_RECENT_AGE) 151167514Skmacy 152167514Skmacy#define W_TCB_T_RTSEQ_RECENT 9 153167514Skmacy#define S_TCB_T_RTSEQ_RECENT 16 154167514Skmacy#define M_TCB_T_RTSEQ_RECENT 0xffffffffULL 155167514Skmacy#define V_TCB_T_RTSEQ_RECENT(x) ((x) << S_TCB_T_RTSEQ_RECENT) 156167514Skmacy 157167514Skmacy#define W_TCB_T_SRTT 10 158167514Skmacy#define S_TCB_T_SRTT 16 159167514Skmacy#define M_TCB_T_SRTT 0xffffULL 160167514Skmacy#define V_TCB_T_SRTT(x) ((x) << S_TCB_T_SRTT) 161167514Skmacy 162167514Skmacy#define W_TCB_T_RTTVAR 11 163167514Skmacy#define S_TCB_T_RTTVAR 0 164167514Skmacy#define M_TCB_T_RTTVAR 0xffffULL 165167514Skmacy#define V_TCB_T_RTTVAR(x) ((x) << S_TCB_T_RTTVAR) 166167514Skmacy 167167514Skmacy#define W_TCB_TS_LAST_ACK_SENT_RAW 11 168167514Skmacy#define S_TCB_TS_LAST_ACK_SENT_RAW 16 169167514Skmacy#define M_TCB_TS_LAST_ACK_SENT_RAW 0x7ffffffULL 170167514Skmacy#define V_TCB_TS_LAST_ACK_SENT_RAW(x) ((x) << S_TCB_TS_LAST_ACK_SENT_RAW) 171167514Skmacy 172167514Skmacy#define W_TCB_DIP 12 173167514Skmacy#define S_TCB_DIP 11 174167514Skmacy#define M_TCB_DIP 0xffffffffULL 175167514Skmacy#define V_TCB_DIP(x) ((x) << S_TCB_DIP) 176167514Skmacy 177167514Skmacy#define W_TCB_SIP 13 178167514Skmacy#define S_TCB_SIP 11 179167514Skmacy#define M_TCB_SIP 0xffffffffULL 180167514Skmacy#define V_TCB_SIP(x) ((x) << S_TCB_SIP) 181167514Skmacy 182167514Skmacy#define W_TCB_DP 14 183167514Skmacy#define S_TCB_DP 11 184167514Skmacy#define M_TCB_DP 0xffffULL 185167514Skmacy#define V_TCB_DP(x) ((x) << S_TCB_DP) 186167514Skmacy 187167514Skmacy#define W_TCB_SP 14 188167514Skmacy#define S_TCB_SP 27 189167514Skmacy#define M_TCB_SP 0xffffULL 190167514Skmacy#define V_TCB_SP(x) ((x) << S_TCB_SP) 191167514Skmacy 192167514Skmacy#define W_TCB_TIMESTAMP 15 193167514Skmacy#define S_TCB_TIMESTAMP 11 194167514Skmacy#define M_TCB_TIMESTAMP 0xffffffffULL 195167514Skmacy#define V_TCB_TIMESTAMP(x) ((x) << S_TCB_TIMESTAMP) 196167514Skmacy 197167514Skmacy#define W_TCB_TIMESTAMP_OFFSET 16 198167514Skmacy#define S_TCB_TIMESTAMP_OFFSET 11 199167514Skmacy#define M_TCB_TIMESTAMP_OFFSET 0xfULL 200167514Skmacy#define V_TCB_TIMESTAMP_OFFSET(x) ((x) << S_TCB_TIMESTAMP_OFFSET) 201167514Skmacy 202167514Skmacy#define W_TCB_TX_MAX 16 203167514Skmacy#define S_TCB_TX_MAX 15 204167514Skmacy#define M_TCB_TX_MAX 0xffffffffULL 205167514Skmacy#define V_TCB_TX_MAX(x) ((x) << S_TCB_TX_MAX) 206167514Skmacy 207167514Skmacy#define W_TCB_TX_HDR_PTR_RAW 17 208167514Skmacy#define S_TCB_TX_HDR_PTR_RAW 15 209167514Skmacy#define M_TCB_TX_HDR_PTR_RAW 0x1ffffULL 210167514Skmacy#define V_TCB_TX_HDR_PTR_RAW(x) ((x) << S_TCB_TX_HDR_PTR_RAW) 211167514Skmacy 212167514Skmacy#define W_TCB_TX_LAST_PTR_RAW 18 213167514Skmacy#define S_TCB_TX_LAST_PTR_RAW 0 214167514Skmacy#define M_TCB_TX_LAST_PTR_RAW 0x1ffffULL 215167514Skmacy#define V_TCB_TX_LAST_PTR_RAW(x) ((x) << S_TCB_TX_LAST_PTR_RAW) 216167514Skmacy 217167514Skmacy#define W_TCB_TX_COMPACT 18 218167514Skmacy#define S_TCB_TX_COMPACT 17 219167514Skmacy#define M_TCB_TX_COMPACT 0x1ULL 220167514Skmacy#define V_TCB_TX_COMPACT(x) ((x) << S_TCB_TX_COMPACT) 221167514Skmacy 222167514Skmacy#define W_TCB_RX_COMPACT 18 223167514Skmacy#define S_TCB_RX_COMPACT 18 224167514Skmacy#define M_TCB_RX_COMPACT 0x1ULL 225167514Skmacy#define V_TCB_RX_COMPACT(x) ((x) << S_TCB_RX_COMPACT) 226167514Skmacy 227167514Skmacy#define W_TCB_RCV_WND 18 228167514Skmacy#define S_TCB_RCV_WND 19 229167514Skmacy#define M_TCB_RCV_WND 0x7ffffffULL 230167514Skmacy#define V_TCB_RCV_WND(x) ((x) << S_TCB_RCV_WND) 231167514Skmacy 232167514Skmacy#define W_TCB_RX_HDR_OFFSET 19 233167514Skmacy#define S_TCB_RX_HDR_OFFSET 14 234167514Skmacy#define M_TCB_RX_HDR_OFFSET 0x7ffffffULL 235167514Skmacy#define V_TCB_RX_HDR_OFFSET(x) ((x) << S_TCB_RX_HDR_OFFSET) 236167514Skmacy 237167514Skmacy#define W_TCB_RX_FRAG0_START_IDX_RAW 20 238167514Skmacy#define S_TCB_RX_FRAG0_START_IDX_RAW 9 239167514Skmacy#define M_TCB_RX_FRAG0_START_IDX_RAW 0x7ffffffULL 240167514Skmacy#define V_TCB_RX_FRAG0_START_IDX_RAW(x) ((x) << S_TCB_RX_FRAG0_START_IDX_RAW) 241167514Skmacy 242167514Skmacy#define W_TCB_RX_FRAG1_START_IDX_OFFSET 21 243167514Skmacy#define S_TCB_RX_FRAG1_START_IDX_OFFSET 4 244167514Skmacy#define M_TCB_RX_FRAG1_START_IDX_OFFSET 0x7ffffffULL 245167514Skmacy#define V_TCB_RX_FRAG1_START_IDX_OFFSET(x) ((x) << S_TCB_RX_FRAG1_START_IDX_OFFSET) 246167514Skmacy 247167514Skmacy#define W_TCB_RX_FRAG0_LEN 21 248167514Skmacy#define S_TCB_RX_FRAG0_LEN 31 249167514Skmacy#define M_TCB_RX_FRAG0_LEN 0x7ffffffULL 250167514Skmacy#define V_TCB_RX_FRAG0_LEN(x) ((x) << S_TCB_RX_FRAG0_LEN) 251167514Skmacy 252167514Skmacy#define W_TCB_RX_FRAG1_LEN 22 253167514Skmacy#define S_TCB_RX_FRAG1_LEN 26 254167514Skmacy#define M_TCB_RX_FRAG1_LEN 0x7ffffffULL 255167514Skmacy#define V_TCB_RX_FRAG1_LEN(x) ((x) << S_TCB_RX_FRAG1_LEN) 256167514Skmacy 257167514Skmacy#define W_TCB_NEWRENO_RECOVER 23 258167514Skmacy#define S_TCB_NEWRENO_RECOVER 21 259167514Skmacy#define M_TCB_NEWRENO_RECOVER 0x7ffffffULL 260167514Skmacy#define V_TCB_NEWRENO_RECOVER(x) ((x) << S_TCB_NEWRENO_RECOVER) 261167514Skmacy 262167514Skmacy#define W_TCB_PDU_HAVE_LEN 24 263167514Skmacy#define S_TCB_PDU_HAVE_LEN 16 264167514Skmacy#define M_TCB_PDU_HAVE_LEN 0x1ULL 265167514Skmacy#define V_TCB_PDU_HAVE_LEN(x) ((x) << S_TCB_PDU_HAVE_LEN) 266167514Skmacy 267167514Skmacy#define W_TCB_PDU_LEN 24 268167514Skmacy#define S_TCB_PDU_LEN 17 269167514Skmacy#define M_TCB_PDU_LEN 0xffffULL 270167514Skmacy#define V_TCB_PDU_LEN(x) ((x) << S_TCB_PDU_LEN) 271167514Skmacy 272167514Skmacy#define W_TCB_RX_QUIESCE 25 273167514Skmacy#define S_TCB_RX_QUIESCE 1 274167514Skmacy#define M_TCB_RX_QUIESCE 0x1ULL 275167514Skmacy#define V_TCB_RX_QUIESCE(x) ((x) << S_TCB_RX_QUIESCE) 276167514Skmacy 277167514Skmacy#define W_TCB_RX_PTR_RAW 25 278167514Skmacy#define S_TCB_RX_PTR_RAW 2 279167514Skmacy#define M_TCB_RX_PTR_RAW 0x1ffffULL 280167514Skmacy#define V_TCB_RX_PTR_RAW(x) ((x) << S_TCB_RX_PTR_RAW) 281167514Skmacy 282167514Skmacy#define W_TCB_CPU_NO 25 283167514Skmacy#define S_TCB_CPU_NO 19 284167514Skmacy#define M_TCB_CPU_NO 0x7fULL 285167514Skmacy#define V_TCB_CPU_NO(x) ((x) << S_TCB_CPU_NO) 286167514Skmacy 287167514Skmacy#define W_TCB_ULP_TYPE 25 288167514Skmacy#define S_TCB_ULP_TYPE 26 289167514Skmacy#define M_TCB_ULP_TYPE 0xfULL 290167514Skmacy#define V_TCB_ULP_TYPE(x) ((x) << S_TCB_ULP_TYPE) 291167514Skmacy 292167514Skmacy#define W_TCB_RX_FRAG1_PTR_RAW 25 293167514Skmacy#define S_TCB_RX_FRAG1_PTR_RAW 30 294167514Skmacy#define M_TCB_RX_FRAG1_PTR_RAW 0x1ffffULL 295167514Skmacy#define V_TCB_RX_FRAG1_PTR_RAW(x) ((x) << S_TCB_RX_FRAG1_PTR_RAW) 296167514Skmacy 297167514Skmacy#define W_TCB_RX_FRAG2_START_IDX_OFFSET_RAW 26 298167514Skmacy#define S_TCB_RX_FRAG2_START_IDX_OFFSET_RAW 15 299167514Skmacy#define M_TCB_RX_FRAG2_START_IDX_OFFSET_RAW 0x7ffffffULL 300167514Skmacy#define V_TCB_RX_FRAG2_START_IDX_OFFSET_RAW(x) ((x) << S_TCB_RX_FRAG2_START_IDX_OFFSET_RAW) 301167514Skmacy 302167514Skmacy#define W_TCB_RX_FRAG2_PTR_RAW 27 303167514Skmacy#define S_TCB_RX_FRAG2_PTR_RAW 10 304167514Skmacy#define M_TCB_RX_FRAG2_PTR_RAW 0x1ffffULL 305167514Skmacy#define V_TCB_RX_FRAG2_PTR_RAW(x) ((x) << S_TCB_RX_FRAG2_PTR_RAW) 306167514Skmacy 307167514Skmacy#define W_TCB_RX_FRAG2_LEN_RAW 27 308167514Skmacy#define S_TCB_RX_FRAG2_LEN_RAW 27 309167514Skmacy#define M_TCB_RX_FRAG2_LEN_RAW 0x7ffffffULL 310167514Skmacy#define V_TCB_RX_FRAG2_LEN_RAW(x) ((x) << S_TCB_RX_FRAG2_LEN_RAW) 311167514Skmacy 312167514Skmacy#define W_TCB_RX_FRAG3_PTR_RAW 28 313167514Skmacy#define S_TCB_RX_FRAG3_PTR_RAW 22 314167514Skmacy#define M_TCB_RX_FRAG3_PTR_RAW 0x1ffffULL 315167514Skmacy#define V_TCB_RX_FRAG3_PTR_RAW(x) ((x) << S_TCB_RX_FRAG3_PTR_RAW) 316167514Skmacy 317167514Skmacy#define W_TCB_RX_FRAG3_LEN_RAW 29 318167514Skmacy#define S_TCB_RX_FRAG3_LEN_RAW 7 319167514Skmacy#define M_TCB_RX_FRAG3_LEN_RAW 0x7ffffffULL 320167514Skmacy#define V_TCB_RX_FRAG3_LEN_RAW(x) ((x) << S_TCB_RX_FRAG3_LEN_RAW) 321167514Skmacy 322167514Skmacy#define W_TCB_RX_FRAG3_START_IDX_OFFSET_RAW 30 323167514Skmacy#define S_TCB_RX_FRAG3_START_IDX_OFFSET_RAW 2 324167514Skmacy#define M_TCB_RX_FRAG3_START_IDX_OFFSET_RAW 0x7ffffffULL 325167514Skmacy#define V_TCB_RX_FRAG3_START_IDX_OFFSET_RAW(x) ((x) << S_TCB_RX_FRAG3_START_IDX_OFFSET_RAW) 326167514Skmacy 327167514Skmacy#define W_TCB_PDU_HDR_LEN 30 328167514Skmacy#define S_TCB_PDU_HDR_LEN 29 329167514Skmacy#define M_TCB_PDU_HDR_LEN 0xffULL 330167514Skmacy#define V_TCB_PDU_HDR_LEN(x) ((x) << S_TCB_PDU_HDR_LEN) 331167514Skmacy 332167514Skmacy#define W_TCB_SLUSH1 31 333167514Skmacy#define S_TCB_SLUSH1 5 334167514Skmacy#define M_TCB_SLUSH1 0x7ffffULL 335167514Skmacy#define V_TCB_SLUSH1(x) ((x) << S_TCB_SLUSH1) 336167514Skmacy 337167514Skmacy#define W_TCB_ULP_RAW 31 338167514Skmacy#define S_TCB_ULP_RAW 24 339167514Skmacy#define M_TCB_ULP_RAW 0xffULL 340167514Skmacy#define V_TCB_ULP_RAW(x) ((x) << S_TCB_ULP_RAW) 341167514Skmacy 342167514Skmacy#define W_TCB_DDP_RDMAP_VERSION 25 343167514Skmacy#define S_TCB_DDP_RDMAP_VERSION 30 344167514Skmacy#define M_TCB_DDP_RDMAP_VERSION 0x1ULL 345167514Skmacy#define V_TCB_DDP_RDMAP_VERSION(x) ((x) << S_TCB_DDP_RDMAP_VERSION) 346167514Skmacy 347167514Skmacy#define W_TCB_MARKER_ENABLE_RX 25 348167514Skmacy#define S_TCB_MARKER_ENABLE_RX 31 349167514Skmacy#define M_TCB_MARKER_ENABLE_RX 0x1ULL 350167514Skmacy#define V_TCB_MARKER_ENABLE_RX(x) ((x) << S_TCB_MARKER_ENABLE_RX) 351167514Skmacy 352167514Skmacy#define W_TCB_MARKER_ENABLE_TX 26 353167514Skmacy#define S_TCB_MARKER_ENABLE_TX 0 354167514Skmacy#define M_TCB_MARKER_ENABLE_TX 0x1ULL 355167514Skmacy#define V_TCB_MARKER_ENABLE_TX(x) ((x) << S_TCB_MARKER_ENABLE_TX) 356167514Skmacy 357167514Skmacy#define W_TCB_CRC_ENABLE 26 358167514Skmacy#define S_TCB_CRC_ENABLE 1 359167514Skmacy#define M_TCB_CRC_ENABLE 0x1ULL 360167514Skmacy#define V_TCB_CRC_ENABLE(x) ((x) << S_TCB_CRC_ENABLE) 361167514Skmacy 362167514Skmacy#define W_TCB_IRS_ULP 26 363167514Skmacy#define S_TCB_IRS_ULP 2 364167514Skmacy#define M_TCB_IRS_ULP 0x1ffULL 365167514Skmacy#define V_TCB_IRS_ULP(x) ((x) << S_TCB_IRS_ULP) 366167514Skmacy 367167514Skmacy#define W_TCB_ISS_ULP 26 368167514Skmacy#define S_TCB_ISS_ULP 11 369167514Skmacy#define M_TCB_ISS_ULP 0x1ffULL 370167514Skmacy#define V_TCB_ISS_ULP(x) ((x) << S_TCB_ISS_ULP) 371167514Skmacy 372167514Skmacy#define W_TCB_TX_PDU_LEN 26 373167514Skmacy#define S_TCB_TX_PDU_LEN 20 374167514Skmacy#define M_TCB_TX_PDU_LEN 0x3fffULL 375167514Skmacy#define V_TCB_TX_PDU_LEN(x) ((x) << S_TCB_TX_PDU_LEN) 376167514Skmacy 377167514Skmacy#define W_TCB_TX_PDU_OUT 27 378167514Skmacy#define S_TCB_TX_PDU_OUT 2 379167514Skmacy#define M_TCB_TX_PDU_OUT 0x1ULL 380167514Skmacy#define V_TCB_TX_PDU_OUT(x) ((x) << S_TCB_TX_PDU_OUT) 381167514Skmacy 382167514Skmacy#define W_TCB_CQ_IDX_SQ 27 383167514Skmacy#define S_TCB_CQ_IDX_SQ 3 384167514Skmacy#define M_TCB_CQ_IDX_SQ 0xffffULL 385167514Skmacy#define V_TCB_CQ_IDX_SQ(x) ((x) << S_TCB_CQ_IDX_SQ) 386167514Skmacy 387167514Skmacy#define W_TCB_CQ_IDX_RQ 27 388167514Skmacy#define S_TCB_CQ_IDX_RQ 19 389167514Skmacy#define M_TCB_CQ_IDX_RQ 0xffffULL 390167514Skmacy#define V_TCB_CQ_IDX_RQ(x) ((x) << S_TCB_CQ_IDX_RQ) 391167514Skmacy 392167514Skmacy#define W_TCB_QP_ID 28 393167514Skmacy#define S_TCB_QP_ID 3 394167514Skmacy#define M_TCB_QP_ID 0xffffULL 395167514Skmacy#define V_TCB_QP_ID(x) ((x) << S_TCB_QP_ID) 396167514Skmacy 397167514Skmacy#define W_TCB_PD_ID 28 398167514Skmacy#define S_TCB_PD_ID 19 399167514Skmacy#define M_TCB_PD_ID 0xffffULL 400167514Skmacy#define V_TCB_PD_ID(x) ((x) << S_TCB_PD_ID) 401167514Skmacy 402167514Skmacy#define W_TCB_STAG 29 403167514Skmacy#define S_TCB_STAG 3 404167514Skmacy#define M_TCB_STAG 0xffffffffULL 405167514Skmacy#define V_TCB_STAG(x) ((x) << S_TCB_STAG) 406167514Skmacy 407167514Skmacy#define W_TCB_RQ_START 30 408167514Skmacy#define S_TCB_RQ_START 3 409167514Skmacy#define M_TCB_RQ_START 0x3ffffffULL 410167514Skmacy#define V_TCB_RQ_START(x) ((x) << S_TCB_RQ_START) 411167514Skmacy 412167514Skmacy#define W_TCB_RQ_MSN 30 413167514Skmacy#define S_TCB_RQ_MSN 29 414167514Skmacy#define M_TCB_RQ_MSN 0x3ffULL 415167514Skmacy#define V_TCB_RQ_MSN(x) ((x) << S_TCB_RQ_MSN) 416167514Skmacy 417167514Skmacy#define W_TCB_RQ_MAX_OFFSET 31 418167514Skmacy#define S_TCB_RQ_MAX_OFFSET 7 419167514Skmacy#define M_TCB_RQ_MAX_OFFSET 0xfULL 420167514Skmacy#define V_TCB_RQ_MAX_OFFSET(x) ((x) << S_TCB_RQ_MAX_OFFSET) 421167514Skmacy 422167514Skmacy#define W_TCB_RQ_WRITE_PTR 31 423167514Skmacy#define S_TCB_RQ_WRITE_PTR 11 424167514Skmacy#define M_TCB_RQ_WRITE_PTR 0x3ffULL 425167514Skmacy#define V_TCB_RQ_WRITE_PTR(x) ((x) << S_TCB_RQ_WRITE_PTR) 426167514Skmacy 427167514Skmacy#define W_TCB_INB_WRITE_PERM 31 428167514Skmacy#define S_TCB_INB_WRITE_PERM 21 429167514Skmacy#define M_TCB_INB_WRITE_PERM 0x1ULL 430167514Skmacy#define V_TCB_INB_WRITE_PERM(x) ((x) << S_TCB_INB_WRITE_PERM) 431167514Skmacy 432167514Skmacy#define W_TCB_INB_READ_PERM 31 433167514Skmacy#define S_TCB_INB_READ_PERM 22 434167514Skmacy#define M_TCB_INB_READ_PERM 0x1ULL 435167514Skmacy#define V_TCB_INB_READ_PERM(x) ((x) << S_TCB_INB_READ_PERM) 436167514Skmacy 437167514Skmacy#define W_TCB_ORD_L_BIT_VLD 31 438167514Skmacy#define S_TCB_ORD_L_BIT_VLD 23 439167514Skmacy#define M_TCB_ORD_L_BIT_VLD 0x1ULL 440167514Skmacy#define V_TCB_ORD_L_BIT_VLD(x) ((x) << S_TCB_ORD_L_BIT_VLD) 441167514Skmacy 442167514Skmacy#define W_TCB_RDMAP_OPCODE 31 443167514Skmacy#define S_TCB_RDMAP_OPCODE 24 444167514Skmacy#define M_TCB_RDMAP_OPCODE 0xfULL 445167514Skmacy#define V_TCB_RDMAP_OPCODE(x) ((x) << S_TCB_RDMAP_OPCODE) 446167514Skmacy 447167514Skmacy#define W_TCB_TX_FLUSH 31 448167514Skmacy#define S_TCB_TX_FLUSH 28 449167514Skmacy#define M_TCB_TX_FLUSH 0x1ULL 450167514Skmacy#define V_TCB_TX_FLUSH(x) ((x) << S_TCB_TX_FLUSH) 451167514Skmacy 452167514Skmacy#define W_TCB_TX_OOS_RXMT 31 453167514Skmacy#define S_TCB_TX_OOS_RXMT 29 454167514Skmacy#define M_TCB_TX_OOS_RXMT 0x1ULL 455167514Skmacy#define V_TCB_TX_OOS_RXMT(x) ((x) << S_TCB_TX_OOS_RXMT) 456167514Skmacy 457167514Skmacy#define W_TCB_TX_OOS_TXMT 31 458167514Skmacy#define S_TCB_TX_OOS_TXMT 30 459167514Skmacy#define M_TCB_TX_OOS_TXMT 0x1ULL 460167514Skmacy#define V_TCB_TX_OOS_TXMT(x) ((x) << S_TCB_TX_OOS_TXMT) 461167514Skmacy 462167514Skmacy#define W_TCB_SLUSH_AUX2 31 463167514Skmacy#define S_TCB_SLUSH_AUX2 31 464167514Skmacy#define M_TCB_SLUSH_AUX2 0x1ULL 465167514Skmacy#define V_TCB_SLUSH_AUX2(x) ((x) << S_TCB_SLUSH_AUX2) 466167514Skmacy 467167514Skmacy#define W_TCB_RX_FRAG1_PTR_RAW2 25 468167514Skmacy#define S_TCB_RX_FRAG1_PTR_RAW2 30 469167514Skmacy#define M_TCB_RX_FRAG1_PTR_RAW2 0x1ffffULL 470167514Skmacy#define V_TCB_RX_FRAG1_PTR_RAW2(x) ((x) << S_TCB_RX_FRAG1_PTR_RAW2) 471167514Skmacy 472167514Skmacy#define W_TCB_RX_DDP_FLAGS 26 473167514Skmacy#define S_TCB_RX_DDP_FLAGS 15 474167514Skmacy#define M_TCB_RX_DDP_FLAGS 0xffffULL 475167514Skmacy#define V_TCB_RX_DDP_FLAGS(x) ((x) << S_TCB_RX_DDP_FLAGS) 476167514Skmacy 477167514Skmacy#define W_TCB_SLUSH_AUX3 26 478167514Skmacy#define S_TCB_SLUSH_AUX3 31 479167514Skmacy#define M_TCB_SLUSH_AUX3 0x1ffULL 480167514Skmacy#define V_TCB_SLUSH_AUX3(x) ((x) << S_TCB_SLUSH_AUX3) 481167514Skmacy 482167514Skmacy#define W_TCB_RX_DDP_BUF0_OFFSET 27 483167514Skmacy#define S_TCB_RX_DDP_BUF0_OFFSET 8 484167514Skmacy#define M_TCB_RX_DDP_BUF0_OFFSET 0x3fffffULL 485167514Skmacy#define V_TCB_RX_DDP_BUF0_OFFSET(x) ((x) << S_TCB_RX_DDP_BUF0_OFFSET) 486167514Skmacy 487167514Skmacy#define W_TCB_RX_DDP_BUF0_LEN 27 488167514Skmacy#define S_TCB_RX_DDP_BUF0_LEN 30 489167514Skmacy#define M_TCB_RX_DDP_BUF0_LEN 0x3fffffULL 490167514Skmacy#define V_TCB_RX_DDP_BUF0_LEN(x) ((x) << S_TCB_RX_DDP_BUF0_LEN) 491167514Skmacy 492167514Skmacy#define W_TCB_RX_DDP_BUF1_OFFSET 28 493167514Skmacy#define S_TCB_RX_DDP_BUF1_OFFSET 20 494167514Skmacy#define M_TCB_RX_DDP_BUF1_OFFSET 0x3fffffULL 495167514Skmacy#define V_TCB_RX_DDP_BUF1_OFFSET(x) ((x) << S_TCB_RX_DDP_BUF1_OFFSET) 496167514Skmacy 497167514Skmacy#define W_TCB_RX_DDP_BUF1_LEN 29 498167514Skmacy#define S_TCB_RX_DDP_BUF1_LEN 10 499167514Skmacy#define M_TCB_RX_DDP_BUF1_LEN 0x3fffffULL 500167514Skmacy#define V_TCB_RX_DDP_BUF1_LEN(x) ((x) << S_TCB_RX_DDP_BUF1_LEN) 501167514Skmacy 502167514Skmacy#define W_TCB_RX_DDP_BUF0_TAG 30 503167514Skmacy#define S_TCB_RX_DDP_BUF0_TAG 0 504167514Skmacy#define M_TCB_RX_DDP_BUF0_TAG 0xffffffffULL 505167514Skmacy#define V_TCB_RX_DDP_BUF0_TAG(x) ((x) << S_TCB_RX_DDP_BUF0_TAG) 506167514Skmacy 507167514Skmacy#define W_TCB_RX_DDP_BUF1_TAG 31 508167514Skmacy#define S_TCB_RX_DDP_BUF1_TAG 0 509167514Skmacy#define M_TCB_RX_DDP_BUF1_TAG 0xffffffffULL 510167514Skmacy#define V_TCB_RX_DDP_BUF1_TAG(x) ((x) << S_TCB_RX_DDP_BUF1_TAG) 511167514Skmacy 512167514Skmacy#define S_TF_DACK 10 513167514Skmacy#define V_TF_DACK(x) ((x) << S_TF_DACK) 514167514Skmacy 515167514Skmacy#define S_TF_NAGLE 11 516167514Skmacy#define V_TF_NAGLE(x) ((x) << S_TF_NAGLE) 517167514Skmacy 518167514Skmacy#define S_TF_RECV_SCALE 12 519167514Skmacy#define V_TF_RECV_SCALE(x) ((x) << S_TF_RECV_SCALE) 520167514Skmacy 521167514Skmacy#define S_TF_RECV_TSTMP 13 522167514Skmacy#define V_TF_RECV_TSTMP(x) ((x) << S_TF_RECV_TSTMP) 523167514Skmacy 524167514Skmacy#define S_TF_RECV_SACK 14 525167514Skmacy#define V_TF_RECV_SACK(x) ((x) << S_TF_RECV_SACK) 526167514Skmacy 527167514Skmacy#define S_TF_TURBO 15 528167514Skmacy#define V_TF_TURBO(x) ((x) << S_TF_TURBO) 529167514Skmacy 530167514Skmacy#define S_TF_KEEPALIVE 16 531167514Skmacy#define V_TF_KEEPALIVE(x) ((x) << S_TF_KEEPALIVE) 532167514Skmacy 533167514Skmacy#define S_TF_TCAM_BYPASS 17 534167514Skmacy#define V_TF_TCAM_BYPASS(x) ((x) << S_TF_TCAM_BYPASS) 535167514Skmacy 536167514Skmacy#define S_TF_CORE_FIN 18 537167514Skmacy#define V_TF_CORE_FIN(x) ((x) << S_TF_CORE_FIN) 538167514Skmacy 539167514Skmacy#define S_TF_CORE_MORE 19 540167514Skmacy#define V_TF_CORE_MORE(x) ((x) << S_TF_CORE_MORE) 541167514Skmacy 542167514Skmacy#define S_TF_MIGRATING 20 543167514Skmacy#define V_TF_MIGRATING(x) ((x) << S_TF_MIGRATING) 544167514Skmacy 545167514Skmacy#define S_TF_ACTIVE_OPEN 21 546167514Skmacy#define V_TF_ACTIVE_OPEN(x) ((x) << S_TF_ACTIVE_OPEN) 547167514Skmacy 548167514Skmacy#define S_TF_ASK_MODE 22 549167514Skmacy#define V_TF_ASK_MODE(x) ((x) << S_TF_ASK_MODE) 550167514Skmacy 551167514Skmacy#define S_TF_NON_OFFLOAD 23 552167514Skmacy#define V_TF_NON_OFFLOAD(x) ((x) << S_TF_NON_OFFLOAD) 553167514Skmacy 554167514Skmacy#define S_TF_MOD_SCHD 24 555167514Skmacy#define V_TF_MOD_SCHD(x) ((x) << S_TF_MOD_SCHD) 556167514Skmacy 557167514Skmacy#define S_TF_MOD_SCHD_REASON0 25 558167514Skmacy#define V_TF_MOD_SCHD_REASON0(x) ((x) << S_TF_MOD_SCHD_REASON0) 559167514Skmacy 560167514Skmacy#define S_TF_MOD_SCHD_REASON1 26 561167514Skmacy#define V_TF_MOD_SCHD_REASON1(x) ((x) << S_TF_MOD_SCHD_REASON1) 562167514Skmacy 563167514Skmacy#define S_TF_MOD_SCHD_RX 27 564167514Skmacy#define V_TF_MOD_SCHD_RX(x) ((x) << S_TF_MOD_SCHD_RX) 565167514Skmacy 566167514Skmacy#define S_TF_CORE_PUSH 28 567167514Skmacy#define V_TF_CORE_PUSH(x) ((x) << S_TF_CORE_PUSH) 568167514Skmacy 569167514Skmacy#define S_TF_RCV_COALESCE_ENABLE 29 570167514Skmacy#define V_TF_RCV_COALESCE_ENABLE(x) ((x) << S_TF_RCV_COALESCE_ENABLE) 571167514Skmacy 572167514Skmacy#define S_TF_RCV_COALESCE_PUSH 30 573167514Skmacy#define V_TF_RCV_COALESCE_PUSH(x) ((x) << S_TF_RCV_COALESCE_PUSH) 574167514Skmacy 575167514Skmacy#define S_TF_RCV_COALESCE_LAST_PSH 31 576167514Skmacy#define V_TF_RCV_COALESCE_LAST_PSH(x) ((x) << S_TF_RCV_COALESCE_LAST_PSH) 577167514Skmacy 578167514Skmacy#define S_TF_RCV_COALESCE_HEARTBEAT 32 579167514Skmacy#define V_TF_RCV_COALESCE_HEARTBEAT(x) ((x) << S_TF_RCV_COALESCE_HEARTBEAT) 580167514Skmacy 581167514Skmacy#define S_TF_LOCK_TID 33 582167514Skmacy#define V_TF_LOCK_TID(x) ((x) << S_TF_LOCK_TID) 583167514Skmacy 584167514Skmacy#define S_TF_DACK_MSS 34 585167514Skmacy#define V_TF_DACK_MSS(x) ((x) << S_TF_DACK_MSS) 586167514Skmacy 587167514Skmacy#define S_TF_CCTRL_SEL0 35 588167514Skmacy#define V_TF_CCTRL_SEL0(x) ((x) << S_TF_CCTRL_SEL0) 589167514Skmacy 590167514Skmacy#define S_TF_CCTRL_SEL1 36 591167514Skmacy#define V_TF_CCTRL_SEL1(x) ((x) << S_TF_CCTRL_SEL1) 592167514Skmacy 593167514Skmacy#define S_TF_TCP_NEWRENO_FAST_RECOVERY 37 594167514Skmacy#define V_TF_TCP_NEWRENO_FAST_RECOVERY(x) ((x) << S_TF_TCP_NEWRENO_FAST_RECOVERY) 595167514Skmacy 596167514Skmacy#define S_TF_TX_PACE_AUTO 38 597167514Skmacy#define V_TF_TX_PACE_AUTO(x) ((x) << S_TF_TX_PACE_AUTO) 598167514Skmacy 599167514Skmacy#define S_TF_PEER_FIN_HELD 39 600167514Skmacy#define V_TF_PEER_FIN_HELD(x) ((x) << S_TF_PEER_FIN_HELD) 601167514Skmacy 602167514Skmacy#define S_TF_CORE_URG 40 603167514Skmacy#define V_TF_CORE_URG(x) ((x) << S_TF_CORE_URG) 604167514Skmacy 605167514Skmacy#define S_TF_RDMA_ERROR 41 606167514Skmacy#define V_TF_RDMA_ERROR(x) ((x) << S_TF_RDMA_ERROR) 607167514Skmacy 608167514Skmacy#define S_TF_SSWS_DISABLED 42 609167514Skmacy#define V_TF_SSWS_DISABLED(x) ((x) << S_TF_SSWS_DISABLED) 610167514Skmacy 611167514Skmacy#define S_TF_DUPACK_COUNT_ODD 43 612167514Skmacy#define V_TF_DUPACK_COUNT_ODD(x) ((x) << S_TF_DUPACK_COUNT_ODD) 613167514Skmacy 614167514Skmacy#define S_TF_TX_CHANNEL 44 615167514Skmacy#define V_TF_TX_CHANNEL(x) ((x) << S_TF_TX_CHANNEL) 616167514Skmacy 617167514Skmacy#define S_TF_RX_CHANNEL 45 618167514Skmacy#define V_TF_RX_CHANNEL(x) ((x) << S_TF_RX_CHANNEL) 619167514Skmacy 620167514Skmacy#define S_TF_TX_PACE_FIXED 46 621167514Skmacy#define V_TF_TX_PACE_FIXED(x) ((x) << S_TF_TX_PACE_FIXED) 622167514Skmacy 623167514Skmacy#define S_TF_RDMA_FLM_ERROR 47 624167514Skmacy#define V_TF_RDMA_FLM_ERROR(x) ((x) << S_TF_RDMA_FLM_ERROR) 625167514Skmacy 626167514Skmacy#define S_TF_RX_FLOW_CONTROL_DISABLE 48 627167514Skmacy#define V_TF_RX_FLOW_CONTROL_DISABLE(x) ((x) << S_TF_RX_FLOW_CONTROL_DISABLE) 628167514Skmacy 629167514Skmacy#define S_TF_DDP_INDICATE_OUT 15 630167514Skmacy#define V_TF_DDP_INDICATE_OUT(x) ((x) << S_TF_DDP_INDICATE_OUT) 631167514Skmacy 632167514Skmacy#define S_TF_DDP_ACTIVE_BUF 16 633167514Skmacy#define V_TF_DDP_ACTIVE_BUF(x) ((x) << S_TF_DDP_ACTIVE_BUF) 634167514Skmacy 635167514Skmacy#define S_TF_DDP_BUF0_VALID 17 636167514Skmacy#define V_TF_DDP_BUF0_VALID(x) ((x) << S_TF_DDP_BUF0_VALID) 637167514Skmacy 638167514Skmacy#define S_TF_DDP_BUF1_VALID 18 639167514Skmacy#define V_TF_DDP_BUF1_VALID(x) ((x) << S_TF_DDP_BUF1_VALID) 640167514Skmacy 641167514Skmacy#define S_TF_DDP_BUF0_INDICATE 19 642167514Skmacy#define V_TF_DDP_BUF0_INDICATE(x) ((x) << S_TF_DDP_BUF0_INDICATE) 643167514Skmacy 644167514Skmacy#define S_TF_DDP_BUF1_INDICATE 20 645167514Skmacy#define V_TF_DDP_BUF1_INDICATE(x) ((x) << S_TF_DDP_BUF1_INDICATE) 646167514Skmacy 647167514Skmacy#define S_TF_DDP_PUSH_DISABLE_0 21 648167514Skmacy#define V_TF_DDP_PUSH_DISABLE_0(x) ((x) << S_TF_DDP_PUSH_DISABLE_0) 649167514Skmacy 650167514Skmacy#define S_TF_DDP_PUSH_DISABLE_1 22 651167514Skmacy#define V_TF_DDP_PUSH_DISABLE_1(x) ((x) << S_TF_DDP_PUSH_DISABLE_1) 652167514Skmacy 653167514Skmacy#define S_TF_DDP_OFF 23 654167514Skmacy#define V_TF_DDP_OFF(x) ((x) << S_TF_DDP_OFF) 655167514Skmacy 656167514Skmacy#define S_TF_DDP_WAIT_FRAG 24 657167514Skmacy#define V_TF_DDP_WAIT_FRAG(x) ((x) << S_TF_DDP_WAIT_FRAG) 658167514Skmacy 659167514Skmacy#define S_TF_DDP_BUF_INF 25 660167514Skmacy#define V_TF_DDP_BUF_INF(x) ((x) << S_TF_DDP_BUF_INF) 661167514Skmacy 662167514Skmacy#define S_TF_DDP_RX2TX 26 663167514Skmacy#define V_TF_DDP_RX2TX(x) ((x) << S_TF_DDP_RX2TX) 664167514Skmacy 665167514Skmacy#define S_TF_DDP_BUF0_FLUSH 27 666167514Skmacy#define V_TF_DDP_BUF0_FLUSH(x) ((x) << S_TF_DDP_BUF0_FLUSH) 667167514Skmacy 668167514Skmacy#define S_TF_DDP_BUF1_FLUSH 28 669167514Skmacy#define V_TF_DDP_BUF1_FLUSH(x) ((x) << S_TF_DDP_BUF1_FLUSH) 670167514Skmacy 671176472Skmacy#define S_TF_DDP_PSH_NO_INVALIDATE0 29 672176472Skmacy#define V_TF_DDP_PSH_NO_INVALIDATE0(x) ((x) << S_TF_DDP_PSH_NO_INVALIDATE0) 673167514Skmacy 674176472Skmacy#define S_TF_DDP_PSH_NO_INVALIDATE1 30 675176472Skmacy#define V_TF_DDP_PSH_NO_INVALIDATE1(x) ((x) << S_TF_DDP_PSH_NO_INVALIDATE1) 676176472Skmacy 677167514Skmacy#endif /* _TCB_DEFS_H */ 678