ct.c revision 240325
1/* $NecBSD: ct.c,v 1.13.12.5 2001/06/26 07:31:53 honda Exp $ */ 2 3#include <sys/cdefs.h> 4__FBSDID("$FreeBSD: head/sys/dev/ct/ct.c 240325 2012-09-10 18:49:49Z jhb $"); 5/* $NetBSD$ */ 6 7#define CT_DEBUG 8#define CT_IO_CONTROL_FLAGS (CT_USE_CCSEQ | CT_FAST_INTR) 9 10/*- 11 * [NetBSD for NEC PC-98 series] 12 * Copyright (c) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001 13 * NetBSD/pc98 porting staff. All rights reserved. 14 * 15 * Copyright (c) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001 16 * Naofumi HONDA. All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions 20 * are met: 21 * 1. Redistributions of source code must retain the above copyright 22 * notice, this list of conditions and the following disclaimer. 23 * 2. Redistributions in binary form must reproduce the above copyright 24 * notice, this list of conditions and the following disclaimer in the 25 * documentation and/or other materials provided with the distribution. 26 * 3. The name of the author may not be used to endorse or promote products 27 * derived from this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 30 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 31 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 32 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 33 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 34 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 35 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 36 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 37 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 38 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 39 * POSSIBILITY OF SUCH DAMAGE. 40 */ 41 42#include <sys/param.h> 43#include <sys/systm.h> 44#include <sys/kernel.h> 45#include <sys/bio.h> 46#include <sys/buf.h> 47#include <sys/queue.h> 48#include <sys/malloc.h> 49#include <sys/errno.h> 50 51#include <machine/bus.h> 52 53#include <cam/scsi/scsi_low.h> 54 55#include <dev/ic/wd33c93reg.h> 56#include <dev/ct/ctvar.h> 57#include <dev/ct/ct_machdep.h> 58 59#define CT_NTARGETS 8 60#define CT_NLUNS 8 61#define CT_RESET_DEFAULT 2000 62#define CT_DELAY_MAX (2 * 1000 * 1000) 63#define CT_DELAY_INTERVAL (1) 64 65/*************************************************** 66 * DEBUG 67 ***************************************************/ 68#ifdef CT_DEBUG 69int ct_debug; 70#endif /* CT_DEBUG */ 71 72/*************************************************** 73 * IO control 74 ***************************************************/ 75#define CT_USE_CCSEQ 0x0100 76#define CT_FAST_INTR 0x0200 77 78u_int ct_io_control = CT_IO_CONTROL_FLAGS; 79 80/*************************************************** 81 * default data 82 ***************************************************/ 83u_int8_t cthw_cmdlevel[256] = { 84/* 0 1 2 3 4 5 6 7 8 9 A B C E D F */ 85/*0*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,1 ,0 ,1 ,0 ,0 ,0 ,0 ,0 , 86/*1*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 , 87/*2*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,1 ,0 ,1 ,0 ,0 ,0 ,0 ,0 , 88/*3*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 , 89/*4*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 , 90/*5*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 , 91/*6*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 , 92/*7*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 , 93/*8*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 , 94/*9*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 , 95/*A*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 , 96/*B*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 , 97/*C*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 , 98/*D*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 , 99/*E*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 , 100/*F*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 , 101}; 102 103#if 0 104/* default synch data table */ 105/* A 10 6.6 5.0 4.0 3.3 2.8 2.5 2.0 M/s */ 106/* X 100 150 200 250 300 350 400 500 ns */ 107static struct ct_synch_data ct_synch_data_FSCSI[] = { 108 {25, 0xa0}, {37, 0xb0}, {50, 0x20}, {62, 0xd0}, {75, 0x30}, 109 {87, 0xf0}, {100, 0x40}, {125, 0x50}, {0, 0} 110}; 111 112static struct ct_synch_data ct_synch_data_SCSI[] = { 113 {50, 0x20}, {75, 0x30}, {100, 0x40}, {125, 0x50}, {0, 0} 114}; 115#endif 116/*************************************************** 117 * DEVICE STRUCTURE 118 ***************************************************/ 119extern struct cfdriver ct_cd; 120 121/***************************************************************** 122 * Interface functions 123 *****************************************************************/ 124static int ct_xfer(struct ct_softc *, u_int8_t *, int, int, u_int *); 125static void ct_io_xfer(struct ct_softc *); 126static int ct_reselected(struct ct_softc *, u_int8_t); 127static void ct_phase_error(struct ct_softc *, u_int8_t); 128static int ct_start_selection(struct ct_softc *, struct slccb *); 129static int ct_msg(struct ct_softc *, struct targ_info *, u_int); 130static int ct_world_start(struct ct_softc *, int); 131static __inline void cthw_phase_bypass(struct ct_softc *, u_int8_t); 132static int cthw_chip_reset(struct ct_bus_access_handle *, int *, int, int); 133static void cthw_bus_reset(struct ct_softc *); 134static int ct_ccb_nexus_establish(struct ct_softc *); 135static int ct_lun_nexus_establish(struct ct_softc *); 136static int ct_target_nexus_establish(struct ct_softc *, int, int); 137static void cthw_attention(struct ct_softc *); 138static int ct_targ_init(struct ct_softc *, struct targ_info *, int); 139static int ct_unbusy(struct ct_softc *); 140static void ct_attention(struct ct_softc *); 141static struct ct_synch_data *ct_make_synch_table(struct ct_softc *); 142static int ct_catch_intr(struct ct_softc *); 143 144struct scsi_low_funcs ct_funcs = { 145 SC_LOW_INIT_T ct_world_start, 146 SC_LOW_BUSRST_T cthw_bus_reset, 147 SC_LOW_TARG_INIT_T ct_targ_init, 148 SC_LOW_LUN_INIT_T NULL, 149 150 SC_LOW_SELECT_T ct_start_selection, 151 SC_LOW_NEXUS_T ct_lun_nexus_establish, 152 SC_LOW_NEXUS_T ct_ccb_nexus_establish, 153 154 SC_LOW_ATTEN_T cthw_attention, 155 SC_LOW_MSG_T ct_msg, 156 157 SC_LOW_TIMEOUT_T NULL, 158 SC_LOW_POLL_T ctintr, 159 160 NULL, /* SC_LOW_POWER_T cthw_power, */ 161}; 162 163/************************************************** 164 * HW functions 165 **************************************************/ 166static __inline void 167cthw_phase_bypass(ct, ph) 168 struct ct_softc *ct; 169 u_int8_t ph; 170{ 171 struct ct_bus_access_handle *chp = &ct->sc_ch; 172 173 ct_cr_write_1(chp, wd3s_cph, ph); 174 ct_cr_write_1(chp, wd3s_cmd, WD3S_SELECT_ATN_TFR); 175} 176 177static void 178cthw_bus_reset(ct) 179 struct ct_softc *ct; 180{ 181 182 /* 183 * wd33c93 does not have bus reset function. 184 */ 185 if (ct->ct_bus_reset != NULL) 186 ((*ct->ct_bus_reset) (ct)); 187} 188 189static int 190cthw_chip_reset(chp, chiprevp, chipclk, hostid) 191 struct ct_bus_access_handle *chp; 192 int *chiprevp; 193 int chipclk, hostid; 194{ 195#define CT_SELTIMEOUT_20MHz_REGV (0x80) 196 u_int8_t aux, regv; 197 u_int seltout; 198 int wc; 199 200 /* issue abort cmd */ 201 ct_cr_write_1(chp, wd3s_cmd, WD3S_ABORT); 202 DELAY(1000); /* 1ms wait */ 203 (void) ct_stat_read_1(chp); 204 (void) ct_cr_read_1(chp, wd3s_stat); 205 206 /* setup chip registers */ 207 regv = 0; 208 seltout = CT_SELTIMEOUT_20MHz_REGV; 209 switch (chipclk) 210 { 211 case 8: 212 case 10: 213 seltout = (seltout * chipclk) / 20; 214 regv = IDR_FS_8_10; 215 break; 216 217 case 12: 218 case 15: 219 seltout = (seltout * chipclk) / 20; 220 regv = IDR_FS_12_15; 221 break; 222 223 case 16: 224 case 20: 225 seltout = (seltout * chipclk) / 20; 226 regv = IDR_FS_16_20; 227 break; 228 229 default: 230 panic("ct: illegal chip clk rate"); 231 break; 232 } 233 234 regv |= IDR_EHP | hostid | IDR_RAF | IDR_EAF; 235 ct_cr_write_1(chp, wd3s_oid, regv); 236 237 ct_cr_write_1(chp, wd3s_cmd, WD3S_RESET); 238 for (wc = CT_RESET_DEFAULT; wc > 0; wc --) 239 { 240 aux = ct_stat_read_1(chp); 241 if (aux != 0xff && (aux & STR_INT)) 242 { 243 regv = ct_cr_read_1(chp, wd3s_stat); 244 if (regv == BSR_RESET || regv == BSR_AFM_RESET) 245 break; 246 247 ct_cr_write_1(chp, wd3s_cmd, WD3S_RESET); 248 } 249 DELAY(1); 250 } 251 if (wc == 0) 252 return ENXIO; 253 254 ct_cr_write_1(chp, wd3s_tout, seltout); 255 ct_cr_write_1(chp, wd3s_sid, SIDR_RESEL); 256 ct_cr_write_1(chp, wd3s_ctrl, CR_DEFAULT); 257 ct_cr_write_1(chp, wd3s_synch, 0); 258 if (chiprevp != NULL) 259 { 260 *chiprevp = CT_WD33C93; 261 if (regv == BSR_RESET) 262 goto out; 263 264 *chiprevp = CT_WD33C93_A; 265 ct_cr_write_1(chp, wd3s_qtag, 0xaa); 266 if (ct_cr_read_1(chp, wd3s_qtag) != 0xaa) 267 { 268 ct_cr_write_1(chp, wd3s_qtag, 0x0); 269 goto out; 270 } 271 ct_cr_write_1(chp, wd3s_qtag, 0x55); 272 if (ct_cr_read_1(chp, wd3s_qtag) != 0x55) 273 { 274 ct_cr_write_1(chp, wd3s_qtag, 0x0); 275 goto out; 276 } 277 ct_cr_write_1(chp, wd3s_qtag, 0x0); 278 *chiprevp = CT_WD33C93_B; 279 } 280 281out: 282 (void) ct_stat_read_1(chp); 283 (void) ct_cr_read_1(chp, wd3s_stat); 284 return 0; 285} 286 287static struct ct_synch_data * 288ct_make_synch_table(ct) 289 struct ct_softc *ct; 290{ 291 struct ct_synch_data *sdtp, *sdp; 292 u_int base, i, period; 293 294 sdtp = sdp = &ct->sc_default_sdt[0]; 295 296 if ((ct->sc_chipclk % 5) == 0) 297 base = 1000 / (5 * 2); /* 5 MHz type */ 298 else 299 base = 1000 / (4 * 2); /* 4 MHz type */ 300 301 if (ct->sc_chiprev >= CT_WD33C93_B) 302 { 303 /* fast scsi */ 304 for (i = 2; i < 8; i ++, sdp ++) 305 { 306 period = (base * i) / 2; 307 if (period >= 200) /* 5 MHz */ 308 break; 309 sdp->cs_period = period / 4; 310 sdp->cs_syncr = (i * 0x10) | 0x80; 311 } 312 } 313 314 for (i = 2; i < 8; i ++, sdp ++) 315 { 316 period = (base * i); 317 if (period > 500) /* 2 MHz */ 318 break; 319 sdp->cs_period = period / 4; 320 sdp->cs_syncr = (i * 0x10); 321 } 322 323 sdp->cs_period = 0; 324 sdp->cs_syncr = 0; 325 return sdtp; 326} 327 328/************************************************** 329 * Attach & Probe 330 **************************************************/ 331int 332ctprobesubr(chp, dvcfg, hsid, chipclk, chiprevp) 333 struct ct_bus_access_handle *chp; 334 u_int dvcfg, chipclk; 335 int hsid; 336 int *chiprevp; 337{ 338 339#if 0 340 if ((ct_stat_read_1(chp) & STR_BSY) != 0) 341 return 0; 342#endif 343 if (cthw_chip_reset(chp, chiprevp, chipclk, hsid) != 0) 344 return 0; 345 return 1; 346} 347 348void 349ctattachsubr(ct) 350 struct ct_softc *ct; 351{ 352 struct scsi_low_softc *slp = &ct->sc_sclow; 353 354 ct->sc_tmaxcnt = SCSI_LOW_MIN_TOUT * 1000 * 1000; /* default */ 355 slp->sl_funcs = &ct_funcs; 356 slp->sl_flags |= HW_READ_PADDING; 357 (void) scsi_low_attach(slp, 0, CT_NTARGETS, CT_NLUNS, 358 sizeof(struct ct_targ_info), 0); 359} 360 361/************************************************** 362 * SCSI LOW interface functions 363 **************************************************/ 364static void 365cthw_attention(ct) 366 struct ct_softc *ct; 367{ 368 struct ct_bus_access_handle *chp = &ct->sc_ch; 369 370 ct->sc_atten = 1; 371 if ((ct_stat_read_1(chp) & (STR_BSY | STR_CIP)) != 0) 372 return; 373 374 ct_cr_write_1(chp, wd3s_cmd, WD3S_ASSERT_ATN); 375 DELAY(10); 376 if ((ct_stat_read_1(chp) & STR_LCI) == 0) 377 ct->sc_atten = 0; 378 ct_unbusy(ct); 379 return; 380} 381 382static void 383ct_attention(ct) 384 struct ct_softc *ct; 385{ 386 struct scsi_low_softc *slp = &ct->sc_sclow; 387 388 if (slp->sl_atten == 0) 389 { 390 ct_unbusy(ct); 391 scsi_low_attention(slp); 392 } 393 else if (ct->sc_atten != 0) 394 { 395 ct_unbusy(ct); 396 cthw_attention(ct); 397 } 398} 399 400static int 401ct_targ_init(ct, ti, action) 402 struct ct_softc *ct; 403 struct targ_info *ti; 404 int action; 405{ 406 struct ct_targ_info *cti = (void *) ti; 407 408 if (action == SCSI_LOW_INFO_ALLOC || action == SCSI_LOW_INFO_REVOKE) 409 { 410 if (ct->sc_sdp == NULL) 411 { 412 ct->sc_sdp = ct_make_synch_table(ct); 413 } 414 415 switch (ct->sc_chiprev) 416 { 417 default: 418 ti->ti_maxsynch.offset = 5; 419 break; 420 421 case CT_WD33C93_A: 422 case CT_AM33C93_A: 423 ti->ti_maxsynch.offset = 12; 424 break; 425 426 case CT_WD33C93_B: 427 case CT_WD33C93_C: 428 ti->ti_maxsynch.offset = 12; 429 break; 430 } 431 432 ti->ti_maxsynch.period = ct->sc_sdp[0].cs_period; 433 ti->ti_width = SCSI_LOW_BUS_WIDTH_8; 434 cti->cti_syncreg = 0; 435 } 436 437 return 0; 438} 439 440static int 441ct_world_start(ct, fdone) 442 struct ct_softc *ct; 443 int fdone; 444{ 445 struct scsi_low_softc *slp = &ct->sc_sclow; 446 struct ct_bus_access_handle *chp = &ct->sc_ch; 447 448 if (ct->sc_sdp == NULL) 449 { 450 ct->sc_sdp = ct_make_synch_table(ct); 451 } 452 453 if (slp->sl_cfgflags & CFG_NOPARITY) 454 ct->sc_creg = CR_DEFAULT; 455 else 456 ct->sc_creg = CR_DEFAULT_HP; 457 458 if (ct->sc_dma & CT_DMA_DMASTART) 459 (*ct->ct_dma_xfer_stop) (ct); 460 if (ct->sc_dma & CT_DMA_PIOSTART) 461 (*ct->ct_pio_xfer_stop) (ct); 462 ct->sc_dma = 0; 463 ct->sc_atten = 0; 464 465 cthw_chip_reset(chp, NULL, ct->sc_chipclk, slp->sl_hostid); 466 scsi_low_bus_reset(slp); 467 cthw_chip_reset(chp, NULL, ct->sc_chipclk, slp->sl_hostid); 468 469 return 0; 470} 471 472static int 473ct_start_selection(ct, cb) 474 struct ct_softc *ct; 475 struct slccb *cb; 476{ 477 struct scsi_low_softc *slp = &ct->sc_sclow; 478 struct ct_bus_access_handle *chp = &ct->sc_ch; 479 480 struct targ_info *ti = slp->sl_Tnexus; 481 struct lun_info *li = slp->sl_Lnexus; 482 int s, satok; 483 u_int8_t cmd; 484 485 ct->sc_tmaxcnt = cb->ccb_tcmax * 1000 * 1000; 486 ct->sc_atten = 0; 487 satok = 0; 488 489 if (scsi_low_is_disconnect_ok(cb) != 0) 490 { 491 if (ct->sc_chiprev >= CT_WD33C93_A) 492 satok = 1; 493 else if (cthw_cmdlevel[slp->sl_scp.scp_cmd[0]] != 0) 494 satok = 1; 495 } 496 497 if (satok != 0 && 498 scsi_low_is_msgout_continue(ti, SCSI_LOW_MSG_IDENTIFY) == 0) 499 { 500 cmd = WD3S_SELECT_ATN_TFR; 501 ct->sc_satgo = CT_SAT_GOING; 502 } 503 else 504 { 505 cmd = WD3S_SELECT_ATN; 506 ct->sc_satgo = 0; 507 } 508 509 if ((ct_stat_read_1(chp) & (STR_BSY | STR_INT | STR_CIP)) != 0) 510 return SCSI_LOW_START_FAIL; 511 512 if ((ct->sc_satgo & CT_SAT_GOING) != 0) 513 { 514 (void) scsi_low_msgout(slp, ti, SCSI_LOW_MSGOUT_INIT); 515 scsi_low_cmd(slp, ti); 516 ct_cr_write_1(chp, wd3s_oid, slp->sl_scp.scp_cmdlen); 517 ct_write_cmds(chp, slp->sl_scp.scp_cmd, slp->sl_scp.scp_cmdlen); 518 } 519 else 520 { 521 /* anyway attention assert */ 522 SCSI_LOW_ASSERT_ATN(slp); 523 } 524 525 ct_target_nexus_establish(ct, li->li_lun, slp->sl_scp.scp_direction); 526 527 s = splhigh(); 528 if ((ct_stat_read_1(chp) & (STR_BSY | STR_INT | STR_CIP)) == 0) 529 { 530 /* XXX: 531 * Reload a lun again here. 532 */ 533 ct_cr_write_1(chp, wd3s_lun, li->li_lun); 534 ct_cr_write_1(chp, wd3s_cmd, cmd); 535 if ((ct_stat_read_1(chp) & STR_LCI) == 0) 536 { 537 splx(s); 538 SCSI_LOW_SETUP_PHASE(ti, PH_SELSTART); 539 return SCSI_LOW_START_OK; 540 } 541 } 542 splx(s); 543 return SCSI_LOW_START_FAIL; 544} 545 546static int 547ct_msg(ct, ti, msg) 548 struct ct_softc *ct; 549 struct targ_info *ti; 550 u_int msg; 551{ 552 struct ct_bus_access_handle *chp = &ct->sc_ch; 553 struct ct_targ_info *cti = (void *) ti; 554 struct ct_synch_data *csp = ct->sc_sdp; 555 u_int offset, period; 556 int error; 557 558 if ((msg & SCSI_LOW_MSG_WIDE) != 0) 559 { 560 if (ti->ti_width != SCSI_LOW_BUS_WIDTH_8) 561 { 562 ti->ti_width = SCSI_LOW_BUS_WIDTH_8; 563 return EINVAL; 564 } 565 return 0; 566 } 567 568 if ((msg & SCSI_LOW_MSG_SYNCH) == 0) 569 return 0; 570 571 offset = ti->ti_maxsynch.offset; 572 period = ti->ti_maxsynch.period; 573 for ( ; csp->cs_period != 0; csp ++) 574 { 575 if (period == csp->cs_period) 576 break; 577 } 578 579 if (ti->ti_maxsynch.period != 0 && csp->cs_period == 0) 580 { 581 ti->ti_maxsynch.period = 0; 582 ti->ti_maxsynch.offset = 0; 583 cti->cti_syncreg = 0; 584 error = EINVAL; 585 } 586 else 587 { 588 cti->cti_syncreg = ((offset & 0x0f) | csp->cs_syncr); 589 error = 0; 590 } 591 592 if (ct->ct_synch_setup != 0) 593 (*ct->ct_synch_setup) (ct, ti); 594 ct_cr_write_1(chp, wd3s_synch, cti->cti_syncreg); 595 return error; 596} 597 598/************************************************* 599 * <DATA PHASE> 600 *************************************************/ 601static int 602ct_xfer(ct, data, len, direction, statp) 603 struct ct_softc *ct; 604 u_int8_t *data; 605 int len, direction; 606 u_int *statp; 607{ 608 struct ct_bus_access_handle *chp = &ct->sc_ch; 609 int wc; 610 register u_int8_t aux; 611 612 *statp = 0; 613 if (len == 1) 614 { 615 ct_cr_write_1(chp, wd3s_cmd, WD3S_SBT | WD3S_TFR_INFO); 616 } 617 else 618 { 619 cthw_set_count(chp, len); 620 ct_cr_write_1(chp, wd3s_cmd, WD3S_TFR_INFO); 621 } 622 623 aux = ct_stat_read_1(chp); 624 if ((aux & STR_LCI) != 0) 625 { 626 cthw_set_count(chp, 0); 627 return len; 628 } 629 630 for (wc = 0; wc < ct->sc_tmaxcnt; wc ++) 631 { 632 /* check data ready */ 633 if ((aux & (STR_BSY | STR_DBR)) == (STR_BSY | STR_DBR)) 634 { 635 if (direction == SCSI_LOW_READ) 636 { 637 *data = ct_cr_read_1(chp, wd3s_data); 638 if ((aux & STR_PE) != 0) 639 *statp |= SCSI_LOW_DATA_PE; 640 } 641 else 642 { 643 ct_cr_write_1(chp, wd3s_data, *data); 644 } 645 len --; 646 if (len <= 0) 647 break; 648 data ++; 649 } 650 else 651 { 652 DELAY(1); 653 } 654 655 /* check phase miss */ 656 aux = ct_stat_read_1(chp); 657 if ((aux & STR_INT) != 0) 658 break; 659 } 660 return len; 661} 662 663#define CT_PADDING_BUF_SIZE 32 664 665static void 666ct_io_xfer(ct) 667 struct ct_softc *ct; 668{ 669 struct scsi_low_softc *slp = &ct->sc_sclow; 670 struct ct_bus_access_handle *chp = &ct->sc_ch; 671 struct sc_p *sp = &slp->sl_scp; 672 u_int stat; 673 int len; 674 u_int8_t pbuf[CT_PADDING_BUF_SIZE]; 675 676 /* polling mode */ 677 ct_cr_write_1(chp, wd3s_ctrl, ct->sc_creg); 678 679 if (sp->scp_datalen <= 0) 680 { 681 slp->sl_error |= PDMAERR; 682 683 if (slp->sl_scp.scp_direction == SCSI_LOW_WRITE) 684 bzero(pbuf, CT_PADDING_BUF_SIZE); 685 ct_xfer(ct, pbuf, CT_PADDING_BUF_SIZE, 686 sp->scp_direction, &stat); 687 } 688 else 689 { 690 len = ct_xfer(ct, sp->scp_data, sp->scp_datalen, 691 sp->scp_direction, &stat); 692 sp->scp_data += (sp->scp_datalen - len); 693 sp->scp_datalen = len; 694 } 695} 696 697/************************************************** 698 * <PHASE ERROR> 699 **************************************************/ 700struct ct_err { 701 u_char *pe_msg; 702 u_int pe_err; 703 u_int pe_errmsg; 704 int pe_done; 705}; 706 707struct ct_err ct_cmderr[] = { 708/*0*/ { "illegal cmd", FATALIO, SCSI_LOW_MSG_ABORT, 1}, 709/*1*/ { "unexpected bus free", FATALIO, 0, 1}, 710/*2*/ { NULL, SELTIMEOUTIO, 0, 1}, 711/*3*/ { "scsi bus parity error", PARITYERR, SCSI_LOW_MSG_ERROR, 0}, 712/*4*/ { "scsi bus parity error", PARITYERR, SCSI_LOW_MSG_ERROR, 0}, 713/*5*/ { "unknown" , FATALIO, SCSI_LOW_MSG_ABORT, 1}, 714/*6*/ { "miss reselection (target mode)", FATALIO, SCSI_LOW_MSG_ABORT, 0}, 715/*7*/ { "wrong status byte", PARITYERR, SCSI_LOW_MSG_ERROR, 0}, 716}; 717 718static void 719ct_phase_error(ct, scsi_status) 720 struct ct_softc *ct; 721 u_int8_t scsi_status; 722{ 723 struct scsi_low_softc *slp = &ct->sc_sclow; 724 struct targ_info *ti = slp->sl_Tnexus; 725 struct ct_err *pep; 726 u_int msg = 0; 727 728 if ((scsi_status & BSR_CM) == BSR_CMDERR && 729 (scsi_status & BSR_PHVALID) == 0) 730 { 731 pep = &ct_cmderr[scsi_status & BSR_PM]; 732 slp->sl_error |= pep->pe_err; 733 if ((pep->pe_err & PARITYERR) != 0) 734 { 735 if (ti->ti_phase == PH_MSGIN) 736 msg = SCSI_LOW_MSG_PARITY; 737 else 738 msg = SCSI_LOW_MSG_ERROR; 739 } 740 else 741 msg = pep->pe_errmsg; 742 743 if (msg != 0) 744 scsi_low_assert_msg(slp, slp->sl_Tnexus, msg, 1); 745 746 if (pep->pe_msg != NULL) 747 { 748 device_printf(slp->sl_dev, "phase error: %s", 749 pep->pe_msg); 750 scsi_low_print(slp, slp->sl_Tnexus); 751 } 752 753 if (pep->pe_done != 0) 754 scsi_low_disconnected(slp, ti); 755 } 756 else 757 { 758 slp->sl_error |= FATALIO; 759 scsi_low_restart(slp, SCSI_LOW_RESTART_HARD, "phase error"); 760 } 761} 762 763/************************************************** 764 * ### SCSI PHASE SEQUENCER ### 765 **************************************************/ 766static int 767ct_reselected(ct, scsi_status) 768 struct ct_softc *ct; 769 u_int8_t scsi_status; 770{ 771 struct scsi_low_softc *slp = &ct->sc_sclow; 772 struct ct_bus_access_handle *chp = &ct->sc_ch; 773 struct targ_info *ti; 774 u_int sid; 775 u_int8_t regv; 776 777 ct->sc_atten = 0; 778 ct->sc_satgo &= ~CT_SAT_GOING; 779 regv = ct_cr_read_1(chp, wd3s_sid); 780 if ((regv & SIDR_VALID) == 0) 781 return EJUSTRETURN; 782 783 sid = regv & SIDR_IDM; 784 if ((ti = scsi_low_reselected(slp, sid)) == NULL) 785 return EJUSTRETURN; 786 787 ct_target_nexus_establish(ct, 0, SCSI_LOW_READ); 788 if (scsi_status != BSR_AFM_RESEL) 789 return EJUSTRETURN; 790 791 SCSI_LOW_SETUP_PHASE(ti, PH_MSGIN); 792 regv = ct_cr_read_1(chp, wd3s_data); 793 if (scsi_low_msgin(slp, ti, (u_int) regv) == 0) 794 { 795 if (scsi_low_is_msgout_continue(ti, 0) != 0) 796 { 797 /* XXX: scsi_low_attetion */ 798 scsi_low_attention(slp); 799 } 800 } 801 802 if (ct->sc_atten != 0) 803 { 804 ct_attention(ct); 805 } 806 807 ct_cr_write_1(chp, wd3s_cmd, WD3S_NEGATE_ACK); 808 return EJUSTRETURN; 809} 810 811static int 812ct_target_nexus_establish(ct, lun, dir) 813 struct ct_softc *ct; 814 int lun, dir; 815{ 816 struct scsi_low_softc *slp = &ct->sc_sclow; 817 struct ct_bus_access_handle *chp = &ct->sc_ch; 818 struct targ_info *ti = slp->sl_Tnexus; 819 struct ct_targ_info *cti = (void *) ti; 820 821 if (dir == SCSI_LOW_WRITE) 822 ct_cr_write_1(chp, wd3s_did, ti->ti_id); 823 else 824 ct_cr_write_1(chp, wd3s_did, ti->ti_id | DIDR_DPD); 825 ct_cr_write_1(chp, wd3s_lun, lun); 826 ct_cr_write_1(chp, wd3s_ctrl, ct->sc_creg | CR_DMA); 827 ct_cr_write_1(chp, wd3s_cph, 0); 828 ct_cr_write_1(chp, wd3s_synch, cti->cti_syncreg); 829 cthw_set_count(chp, 0); 830 return 0; 831} 832 833static int 834ct_lun_nexus_establish(ct) 835 struct ct_softc *ct; 836{ 837 struct scsi_low_softc *slp = &ct->sc_sclow; 838 struct ct_bus_access_handle *chp = &ct->sc_ch; 839 struct lun_info *li = slp->sl_Lnexus; 840 841 ct_cr_write_1(chp, wd3s_lun, li->li_lun); 842 return 0; 843} 844 845static int 846ct_ccb_nexus_establish(ct) 847 struct ct_softc *ct; 848{ 849 struct scsi_low_softc *slp = &ct->sc_sclow; 850 struct ct_bus_access_handle *chp = &ct->sc_ch; 851 struct lun_info *li = slp->sl_Lnexus; 852 struct targ_info *ti = slp->sl_Tnexus; 853 struct ct_targ_info *cti = (void *) ti; 854 struct slccb *cb = slp->sl_Qnexus; 855 856 ct->sc_tmaxcnt = cb->ccb_tcmax * 1000 * 1000; 857 858 if ((ct->sc_satgo & CT_SAT_GOING) != 0) 859 { 860 ct_cr_write_1(chp, wd3s_oid, slp->sl_scp.scp_cmdlen); 861 ct_write_cmds(chp, slp->sl_scp.scp_cmd, slp->sl_scp.scp_cmdlen); 862 } 863 if (slp->sl_scp.scp_direction == SCSI_LOW_WRITE) 864 ct_cr_write_1(chp, wd3s_did, ti->ti_id); 865 else 866 ct_cr_write_1(chp, wd3s_did, ti->ti_id | DIDR_DPD); 867 ct_cr_write_1(chp, wd3s_lun, li->li_lun); 868 ct_cr_write_1(chp, wd3s_synch, cti->cti_syncreg); 869 return 0; 870} 871 872static int 873ct_unbusy(ct) 874 struct ct_softc *ct; 875{ 876 struct scsi_low_softc *slp = &ct->sc_sclow; 877 struct ct_bus_access_handle *chp = &ct->sc_ch; 878 int wc; 879 register u_int8_t regv; 880 881 for (wc = 0; wc < CT_DELAY_MAX / CT_DELAY_INTERVAL; wc ++) 882 { 883 regv = ct_stat_read_1(chp); 884 if ((regv & (STR_BSY | STR_CIP)) == 0) 885 return 0; 886 if (regv == (u_int8_t) -1) 887 return EIO; 888 889 DELAY(CT_DELAY_INTERVAL); 890 } 891 892 device_printf(slp->sl_dev, "unbusy timeout\n"); 893 return EBUSY; 894} 895 896static int 897ct_catch_intr(ct) 898 struct ct_softc *ct; 899{ 900 struct ct_bus_access_handle *chp = &ct->sc_ch; 901 int wc; 902 register u_int8_t regv; 903 904 for (wc = 0; wc < CT_DELAY_MAX / CT_DELAY_INTERVAL; wc ++) 905 { 906 regv = ct_stat_read_1(chp); 907 if ((regv & (STR_INT | STR_BSY | STR_CIP)) == STR_INT) 908 return 0; 909 910 DELAY(CT_DELAY_INTERVAL); 911 } 912 return EJUSTRETURN; 913} 914 915int 916ctintr(arg) 917 void *arg; 918{ 919 struct ct_softc *ct = arg; 920 struct scsi_low_softc *slp = &ct->sc_sclow; 921 struct ct_bus_access_handle *chp = &ct->sc_ch; 922 struct targ_info *ti; 923 struct buf *bp; 924 u_int derror, flags; 925 int len, satgo, error; 926 u_int8_t scsi_status, regv; 927 928again: 929 if (slp->sl_flags & HW_INACTIVE) 930 return 0; 931 932 /************************************************** 933 * Get status & bus phase 934 **************************************************/ 935 if ((ct_stat_read_1(chp) & STR_INT) == 0) 936 return 0; 937 938 scsi_status = ct_cr_read_1(chp, wd3s_stat); 939 if (scsi_status == ((u_int8_t) -1)) 940 return 1; 941 942 /************************************************** 943 * Check reselection, or nexus 944 **************************************************/ 945 if (scsi_status == BSR_RESEL || scsi_status == BSR_AFM_RESEL) 946 { 947 if (ct_reselected(ct, scsi_status) == EJUSTRETURN) 948 return 1; 949 } 950 951 if ((ti = slp->sl_Tnexus) == NULL) 952 return 1; 953 954 /************************************************** 955 * Debug section 956 **************************************************/ 957#ifdef CT_DEBUG 958 if (ct_debug > 0) 959 { 960 scsi_low_print(slp, NULL); 961 device_printf(slp->sl_dev, "scsi_status 0x%x\n\n", 962 (u_int) scsi_status); 963#ifdef KDB 964 if (ct_debug > 1) 965 kdb_enter(KDB_WHY_CAM, "ct"); 966#endif /* KDB */ 967 } 968#endif /* CT_DEBUG */ 969 970 /************************************************** 971 * Internal scsi phase 972 **************************************************/ 973 satgo = ct->sc_satgo; 974 ct->sc_satgo &= ~CT_SAT_GOING; 975 976 switch (ti->ti_phase) 977 { 978 case PH_SELSTART: 979 if ((satgo & CT_SAT_GOING) == 0) 980 { 981 if (scsi_status != BSR_SELECTED) 982 { 983 ct_phase_error(ct, scsi_status); 984 return 1; 985 } 986 scsi_low_arbit_win(slp); 987 SCSI_LOW_SETUP_PHASE(ti, PH_SELECTED); 988 return 1; 989 } 990 else 991 { 992 scsi_low_arbit_win(slp); 993 SCSI_LOW_SETUP_PHASE(ti, PH_MSGOUT); /* XXX */ 994 } 995 break; 996 997 case PH_RESEL: 998 if ((scsi_status & BSR_PHVALID) == 0 || 999 (scsi_status & BSR_PM) != BSR_MSGIN) 1000 { 1001 scsi_low_restart(slp, SCSI_LOW_RESTART_HARD, 1002 "phase miss after reselect"); 1003 return 1; 1004 } 1005 break; 1006 1007 default: 1008 if (slp->sl_flags & HW_PDMASTART) 1009 { 1010 slp->sl_flags &= ~HW_PDMASTART; 1011 if (ct->sc_dma & CT_DMA_DMASTART) 1012 { 1013 (*ct->ct_dma_xfer_stop) (ct); 1014 ct->sc_dma &= ~CT_DMA_DMASTART; 1015 } 1016 else if (ct->sc_dma & CT_DMA_PIOSTART) 1017 { 1018 (*ct->ct_pio_xfer_stop) (ct); 1019 ct->sc_dma &= ~CT_DMA_PIOSTART; 1020 } 1021 else 1022 { 1023 scsi_low_data_finish(slp); 1024 } 1025 } 1026 break; 1027 } 1028 1029 /************************************************** 1030 * parse scsi phase 1031 **************************************************/ 1032 if (scsi_status & BSR_PHVALID) 1033 { 1034 /************************************************** 1035 * Normal SCSI phase. 1036 **************************************************/ 1037 if ((scsi_status & BSR_CM) == BSR_CMDABT) 1038 { 1039 ct_phase_error(ct, scsi_status); 1040 return 1; 1041 } 1042 1043 switch (scsi_status & BSR_PM) 1044 { 1045 case BSR_DATAOUT: 1046 SCSI_LOW_SETUP_PHASE(ti, PH_DATA); 1047 if (scsi_low_data(slp, ti, &bp, SCSI_LOW_WRITE) != 0) 1048 { 1049 ct_attention(ct); 1050 } 1051 goto common_data_phase; 1052 1053 case BSR_DATAIN: 1054 SCSI_LOW_SETUP_PHASE(ti, PH_DATA); 1055 if (scsi_low_data(slp, ti, &bp, SCSI_LOW_READ) != 0) 1056 { 1057 ct_attention(ct); 1058 } 1059 1060common_data_phase: 1061 if (slp->sl_scp.scp_datalen > 0) 1062 { 1063 slp->sl_flags |= HW_PDMASTART; 1064 if ((ct->sc_xmode & CT_XMODE_PIO) != 0) 1065 { 1066 error = (*ct->ct_pio_xfer_start) (ct); 1067 if (error == 0) 1068 { 1069 ct->sc_dma |= CT_DMA_PIOSTART; 1070 return 1; 1071 } 1072 } 1073 1074 if ((ct->sc_xmode & CT_XMODE_DMA) != 0) 1075 { 1076 error = (*ct->ct_dma_xfer_start) (ct); 1077 if (error == 0) 1078 { 1079 ct->sc_dma |= CT_DMA_DMASTART; 1080 return 1; 1081 } 1082 } 1083 } 1084 else 1085 { 1086 if (slp->sl_scp.scp_direction == SCSI_LOW_READ) 1087 { 1088 if (!(slp->sl_flags & HW_READ_PADDING)) 1089 { 1090 device_printf(slp->sl_dev, 1091 "read padding required\n"); 1092 return 1; 1093 } 1094 } 1095 else 1096 { 1097 if (!(slp->sl_flags & HW_WRITE_PADDING)) 1098 { 1099 device_printf(slp->sl_dev, 1100 "write padding required\n"); 1101 return 1; 1102 } 1103 } 1104 slp->sl_flags |= HW_PDMASTART; 1105 } 1106 1107 ct_io_xfer(ct); 1108 return 1; 1109 1110 case BSR_CMDOUT: 1111 SCSI_LOW_SETUP_PHASE(ti, PH_CMD); 1112 if (scsi_low_cmd(slp, ti) != 0) 1113 { 1114 ct_attention(ct); 1115 } 1116 1117 if (ct_xfer(ct, slp->sl_scp.scp_cmd, 1118 slp->sl_scp.scp_cmdlen, 1119 SCSI_LOW_WRITE, &derror) != 0) 1120 { 1121 device_printf(slp->sl_dev, 1122 "scsi cmd xfer short\n"); 1123 } 1124 return 1; 1125 1126 case BSR_STATIN: 1127 SCSI_LOW_SETUP_PHASE(ti, PH_STAT); 1128 if ((ct_io_control & CT_USE_CCSEQ) != 0) 1129 { 1130 if (scsi_low_is_msgout_continue(ti, 0) != 0 || 1131 ct->sc_atten != 0) 1132 { 1133 ct_xfer(ct, ®v, 1, SCSI_LOW_READ, 1134 &derror); 1135 scsi_low_statusin(slp, ti, 1136 regv | derror); 1137 } 1138 else 1139 { 1140 ct->sc_satgo |= CT_SAT_GOING; 1141 cthw_set_count(chp, 0); 1142 cthw_phase_bypass(ct, 0x41); 1143 } 1144 } 1145 else 1146 { 1147 ct_xfer(ct, ®v, 1, SCSI_LOW_READ, &derror); 1148 scsi_low_statusin(slp, ti, regv | derror); 1149 } 1150 return 1; 1151 1152 case BSR_UNSPINFO0: 1153 case BSR_UNSPINFO1: 1154 device_printf(slp->sl_dev, "illegal bus phase (0x%x)\n", 1155 (u_int) scsi_status); 1156 scsi_low_print(slp, ti); 1157 return 1; 1158 1159 case BSR_MSGOUT: 1160 SCSI_LOW_SETUP_PHASE(ti, PH_MSGOUT); 1161 flags = SCSI_LOW_MSGOUT_UNIFY; 1162 if (ti->ti_ophase != ti->ti_phase) 1163 flags |= SCSI_LOW_MSGOUT_INIT; 1164 len = scsi_low_msgout(slp, ti, flags); 1165 1166 if (len > 1 && slp->sl_atten == 0) 1167 { 1168 ct_attention(ct); 1169 } 1170 1171 if (ct_xfer(ct, ti->ti_msgoutstr, len, 1172 SCSI_LOW_WRITE, &derror) != 0) 1173 { 1174 device_printf(slp->sl_dev, 1175 "scsi msgout xfer short\n"); 1176 } 1177 SCSI_LOW_DEASSERT_ATN(slp); 1178 ct->sc_atten = 0; 1179 return 1; 1180 1181 case BSR_MSGIN:/* msg in */ 1182 SCSI_LOW_SETUP_PHASE(ti, PH_MSGIN); 1183 1184 ct_xfer(ct, ®v, 1, SCSI_LOW_READ, &derror); 1185 if (scsi_low_msgin(slp, ti, regv | derror) == 0) 1186 { 1187 if (scsi_low_is_msgout_continue(ti, 0) != 0) 1188 { 1189 /* XXX: scsi_low_attetion */ 1190 scsi_low_attention(slp); 1191 } 1192 } 1193 1194 if ((ct_io_control & CT_FAST_INTR) != 0) 1195 { 1196 if (ct_catch_intr(ct) == 0) 1197 goto again; 1198 } 1199 return 1; 1200 } 1201 } 1202 else 1203 { 1204 /************************************************** 1205 * Special SCSI phase 1206 **************************************************/ 1207 switch (scsi_status) 1208 { 1209 case BSR_SATSDP: /* SAT with save data pointer */ 1210 SCSI_LOW_SETUP_PHASE(ti, PH_MSGIN); 1211 ct->sc_satgo |= CT_SAT_GOING; 1212 scsi_low_msgin(slp, ti, MSG_SAVESP); 1213 cthw_phase_bypass(ct, 0x41); 1214 return 1; 1215 1216 case BSR_SATFIN: /* SAT COMPLETE */ 1217 /* 1218 * emulate statusin => msgin 1219 */ 1220 SCSI_LOW_SETUP_PHASE(ti, PH_STAT); 1221 scsi_low_statusin(slp, ti, ct_cr_read_1(chp, wd3s_lun)); 1222 1223 SCSI_LOW_SETUP_PHASE(ti, PH_MSGIN); 1224 scsi_low_msgin(slp, ti, MSG_COMP); 1225 1226 scsi_low_disconnected(slp, ti); 1227 return 1; 1228 1229 case BSR_ACKREQ: /* negate ACK */ 1230 if (ct->sc_atten != 0) 1231 { 1232 ct_attention(ct); 1233 } 1234 1235 ct_cr_write_1(chp, wd3s_cmd, WD3S_NEGATE_ACK); 1236 if ((ct_io_control & CT_FAST_INTR) != 0) 1237 { 1238 /* XXX: 1239 * Should clear a pending interrupt and 1240 * sync with a next interrupt! 1241 */ 1242 ct_catch_intr(ct); 1243 } 1244 return 1; 1245 1246 case BSR_DISC: /* disconnect */ 1247 if (slp->sl_msgphase == MSGPH_NULL && 1248 (satgo & CT_SAT_GOING) != 0) 1249 { 1250 /* 1251 * emulate disconnect msg 1252 */ 1253 SCSI_LOW_SETUP_PHASE(ti, PH_MSGIN); 1254 scsi_low_msgin(slp, ti, MSG_DISCON); 1255 } 1256 scsi_low_disconnected(slp, ti); 1257 return 1; 1258 1259 default: 1260 break; 1261 } 1262 } 1263 1264 ct_phase_error(ct, scsi_status); 1265 return 1; 1266} 1267