cpuctl.c revision 347700
1/*- 2 * Copyright (c) 2006-2008 Stanislav Sedov <stas@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 */ 27 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD: stable/11/sys/dev/cpuctl/cpuctl.c 347700 2019-05-16 14:42:16Z markj $"); 30 31#include <sys/param.h> 32#include <sys/systm.h> 33#include <sys/conf.h> 34#include <sys/fcntl.h> 35#include <sys/ioccom.h> 36#include <sys/malloc.h> 37#include <sys/module.h> 38#include <sys/mutex.h> 39#include <sys/priv.h> 40#include <sys/proc.h> 41#include <sys/queue.h> 42#include <sys/sched.h> 43#include <sys/kernel.h> 44#include <sys/sysctl.h> 45#include <sys/uio.h> 46#include <sys/pcpu.h> 47#include <sys/smp.h> 48#include <sys/pmckern.h> 49#include <sys/cpuctl.h> 50 51#include <machine/cpufunc.h> 52#include <machine/md_var.h> 53#include <machine/specialreg.h> 54#include <x86/ucode.h> 55 56static d_open_t cpuctl_open; 57static d_ioctl_t cpuctl_ioctl; 58 59#define CPUCTL_VERSION 1 60 61#ifdef CPUCTL_DEBUG 62# define DPRINTF(format,...) printf(format, __VA_ARGS__); 63#else 64# define DPRINTF(...) 65#endif 66 67#define UCODE_SIZE_MAX (4 * 1024 * 1024) 68 69static int cpuctl_do_msr(int cpu, cpuctl_msr_args_t *data, u_long cmd, 70 struct thread *td); 71static int cpuctl_do_cpuid(int cpu, cpuctl_cpuid_args_t *data, 72 struct thread *td); 73static int cpuctl_do_cpuid_count(int cpu, cpuctl_cpuid_count_args_t *data, 74 struct thread *td); 75static int cpuctl_do_eval_cpu_features(int cpu, struct thread *td); 76static int cpuctl_do_update(int cpu, cpuctl_update_args_t *data, 77 struct thread *td); 78static int update_intel(int cpu, cpuctl_update_args_t *args, 79 struct thread *td); 80static int update_amd(int cpu, cpuctl_update_args_t *args, struct thread *td); 81static int update_via(int cpu, cpuctl_update_args_t *args, 82 struct thread *td); 83 84static struct cdev **cpuctl_devs; 85static MALLOC_DEFINE(M_CPUCTL, "cpuctl", "CPUCTL buffer"); 86 87static struct cdevsw cpuctl_cdevsw = { 88 .d_version = D_VERSION, 89 .d_open = cpuctl_open, 90 .d_ioctl = cpuctl_ioctl, 91 .d_name = "cpuctl", 92}; 93 94/* 95 * This function checks if specified cpu enabled or not. 96 */ 97static int 98cpu_enabled(int cpu) 99{ 100 101 return (pmc_cpu_is_disabled(cpu) == 0); 102} 103 104/* 105 * Check if the current thread is bound to a specific cpu. 106 */ 107static int 108cpu_sched_is_bound(struct thread *td) 109{ 110 int ret; 111 112 thread_lock(td); 113 ret = sched_is_bound(td); 114 thread_unlock(td); 115 return (ret); 116} 117 118/* 119 * Switch to target cpu to run. 120 */ 121static void 122set_cpu(int cpu, struct thread *td) 123{ 124 125 KASSERT(cpu >= 0 && cpu <= mp_maxid && cpu_enabled(cpu), 126 ("[cpuctl,%d]: bad cpu number %d", __LINE__, cpu)); 127 thread_lock(td); 128 sched_bind(td, cpu); 129 thread_unlock(td); 130 KASSERT(td->td_oncpu == cpu, 131 ("[cpuctl,%d]: cannot bind to target cpu %d on cpu %d", __LINE__, 132 cpu, td->td_oncpu)); 133} 134 135static void 136restore_cpu(int oldcpu, int is_bound, struct thread *td) 137{ 138 139 KASSERT(oldcpu >= 0 && oldcpu <= mp_maxid && cpu_enabled(oldcpu), 140 ("[cpuctl,%d]: bad cpu number %d", __LINE__, oldcpu)); 141 thread_lock(td); 142 if (is_bound == 0) 143 sched_unbind(td); 144 else 145 sched_bind(td, oldcpu); 146 thread_unlock(td); 147} 148 149int 150cpuctl_ioctl(struct cdev *dev, u_long cmd, caddr_t data, 151 int flags, struct thread *td) 152{ 153 int cpu, ret; 154 155 cpu = dev2unit(dev); 156 if (cpu > mp_maxid || !cpu_enabled(cpu)) { 157 DPRINTF("[cpuctl,%d]: bad cpu number %d\n", __LINE__, cpu); 158 return (ENXIO); 159 } 160 /* Require write flag for "write" requests. */ 161 if ((cmd == CPUCTL_MSRCBIT || cmd == CPUCTL_MSRSBIT || 162 cmd == CPUCTL_UPDATE || cmd == CPUCTL_WRMSR || 163 cmd == CPUCTL_EVAL_CPU_FEATURES) && 164 (flags & FWRITE) == 0) 165 return (EPERM); 166 switch (cmd) { 167 case CPUCTL_RDMSR: 168 ret = cpuctl_do_msr(cpu, (cpuctl_msr_args_t *)data, cmd, td); 169 break; 170 case CPUCTL_MSRSBIT: 171 case CPUCTL_MSRCBIT: 172 case CPUCTL_WRMSR: 173 ret = priv_check(td, PRIV_CPUCTL_WRMSR); 174 if (ret != 0) 175 goto fail; 176 ret = cpuctl_do_msr(cpu, (cpuctl_msr_args_t *)data, cmd, td); 177 break; 178 case CPUCTL_CPUID: 179 ret = cpuctl_do_cpuid(cpu, (cpuctl_cpuid_args_t *)data, td); 180 break; 181 case CPUCTL_UPDATE: 182 ret = priv_check(td, PRIV_CPUCTL_UPDATE); 183 if (ret != 0) 184 goto fail; 185 ret = cpuctl_do_update(cpu, (cpuctl_update_args_t *)data, td); 186 break; 187 case CPUCTL_CPUID_COUNT: 188 ret = cpuctl_do_cpuid_count(cpu, 189 (cpuctl_cpuid_count_args_t *)data, td); 190 break; 191 case CPUCTL_EVAL_CPU_FEATURES: 192 ret = cpuctl_do_eval_cpu_features(cpu, td); 193 break; 194 default: 195 ret = EINVAL; 196 break; 197 } 198fail: 199 return (ret); 200} 201 202/* 203 * Actually perform cpuid operation. 204 */ 205static int 206cpuctl_do_cpuid_count(int cpu, cpuctl_cpuid_count_args_t *data, 207 struct thread *td) 208{ 209 int is_bound = 0; 210 int oldcpu; 211 212 KASSERT(cpu >= 0 && cpu <= mp_maxid, 213 ("[cpuctl,%d]: bad cpu number %d", __LINE__, cpu)); 214 215 /* Explicitly clear cpuid data to avoid returning stale info. */ 216 bzero(data->data, sizeof(data->data)); 217 DPRINTF("[cpuctl,%d]: retrieving cpuid lev %#0x type %#0x for %d cpu\n", 218 __LINE__, data->level, data->level_type, cpu); 219#ifdef __i386__ 220 if (cpu_id == 0) 221 return (ENODEV); 222#endif 223 oldcpu = td->td_oncpu; 224 is_bound = cpu_sched_is_bound(td); 225 set_cpu(cpu, td); 226 cpuid_count(data->level, data->level_type, data->data); 227 restore_cpu(oldcpu, is_bound, td); 228 return (0); 229} 230 231static int 232cpuctl_do_cpuid(int cpu, cpuctl_cpuid_args_t *data, struct thread *td) 233{ 234 cpuctl_cpuid_count_args_t cdata; 235 int error; 236 237 cdata.level = data->level; 238 /* Override the level type. */ 239 cdata.level_type = 0; 240 error = cpuctl_do_cpuid_count(cpu, &cdata, td); 241 bcopy(cdata.data, data->data, sizeof(data->data)); /* Ignore error */ 242 return (error); 243} 244 245/* 246 * Actually perform MSR operations. 247 */ 248static int 249cpuctl_do_msr(int cpu, cpuctl_msr_args_t *data, u_long cmd, struct thread *td) 250{ 251 uint64_t reg; 252 int is_bound = 0; 253 int oldcpu; 254 int ret; 255 256 KASSERT(cpu >= 0 && cpu <= mp_maxid, 257 ("[cpuctl,%d]: bad cpu number %d", __LINE__, cpu)); 258 259 /* 260 * Explicitly clear cpuid data to avoid returning stale 261 * info 262 */ 263 DPRINTF("[cpuctl,%d]: operating on MSR %#0x for %d cpu\n", __LINE__, 264 data->msr, cpu); 265#ifdef __i386__ 266 if ((cpu_feature & CPUID_MSR) == 0) 267 return (ENODEV); 268#endif 269 oldcpu = td->td_oncpu; 270 is_bound = cpu_sched_is_bound(td); 271 set_cpu(cpu, td); 272 if (cmd == CPUCTL_RDMSR) { 273 data->data = 0; 274 ret = rdmsr_safe(data->msr, &data->data); 275 } else if (cmd == CPUCTL_WRMSR) { 276 ret = wrmsr_safe(data->msr, data->data); 277 } else if (cmd == CPUCTL_MSRSBIT) { 278 critical_enter(); 279 ret = rdmsr_safe(data->msr, ®); 280 if (ret == 0) 281 ret = wrmsr_safe(data->msr, reg | data->data); 282 critical_exit(); 283 } else if (cmd == CPUCTL_MSRCBIT) { 284 critical_enter(); 285 ret = rdmsr_safe(data->msr, ®); 286 if (ret == 0) 287 ret = wrmsr_safe(data->msr, reg & ~data->data); 288 critical_exit(); 289 } else 290 panic("[cpuctl,%d]: unknown operation requested: %lu", 291 __LINE__, cmd); 292 restore_cpu(oldcpu, is_bound, td); 293 return (ret); 294} 295 296/* 297 * Actually perform microcode update. 298 */ 299static int 300cpuctl_do_update(int cpu, cpuctl_update_args_t *data, struct thread *td) 301{ 302 cpuctl_cpuid_args_t args = { 303 .level = 0, 304 }; 305 char vendor[13]; 306 int ret; 307 308 KASSERT(cpu >= 0 && cpu <= mp_maxid, 309 ("[cpuctl,%d]: bad cpu number %d", __LINE__, cpu)); 310 DPRINTF("[cpuctl,%d]: XXX %d", __LINE__, cpu); 311 312 ret = cpuctl_do_cpuid(cpu, &args, td); 313 if (ret != 0) 314 return (ret); 315 ((uint32_t *)vendor)[0] = args.data[1]; 316 ((uint32_t *)vendor)[1] = args.data[3]; 317 ((uint32_t *)vendor)[2] = args.data[2]; 318 vendor[12] = '\0'; 319 if (strncmp(vendor, INTEL_VENDOR_ID, sizeof(INTEL_VENDOR_ID)) == 0) 320 ret = update_intel(cpu, data, td); 321 else if(strncmp(vendor, AMD_VENDOR_ID, sizeof(AMD_VENDOR_ID)) == 0) 322 ret = update_amd(cpu, data, td); 323 else if(strncmp(vendor, CENTAUR_VENDOR_ID, sizeof(CENTAUR_VENDOR_ID)) 324 == 0) 325 ret = update_via(cpu, data, td); 326 else 327 ret = ENXIO; 328 return (ret); 329} 330 331static int 332update_intel(int cpu, cpuctl_update_args_t *args, struct thread *td) 333{ 334 void *ptr; 335 int is_bound, oldcpu, ret; 336 337 if (args->size == 0 || args->data == NULL) { 338 DPRINTF("[cpuctl,%d]: zero-sized firmware image", __LINE__); 339 return (EINVAL); 340 } 341 if (args->size > UCODE_SIZE_MAX) { 342 DPRINTF("[cpuctl,%d]: firmware image too large", __LINE__); 343 return (EINVAL); 344 } 345 346 /* 347 * 16 byte alignment required. Rely on the fact that 348 * malloc(9) always returns the pointer aligned at least on 349 * the size of the allocation. 350 */ 351 ptr = malloc(args->size + 16, M_CPUCTL, M_WAITOK); 352 if (copyin(args->data, ptr, args->size) != 0) { 353 DPRINTF("[cpuctl,%d]: copyin %p->%p of %zd bytes failed", 354 __LINE__, args->data, ptr, args->size); 355 ret = EFAULT; 356 goto out; 357 } 358 oldcpu = td->td_oncpu; 359 is_bound = cpu_sched_is_bound(td); 360 set_cpu(cpu, td); 361 critical_enter(); 362 363 ret = ucode_intel_load(ptr, true, NULL, NULL); 364 365 critical_exit(); 366 restore_cpu(oldcpu, is_bound, td); 367 368 /* 369 * Replace any existing update. This ensures that the new update 370 * will be reloaded automatically during ACPI resume. 371 */ 372 if (ret == 0) 373 ptr = ucode_update(ptr); 374 375out: 376 free(ptr, M_CPUCTL); 377 return (ret); 378} 379 380/* 381 * NB: MSR 0xc0010020, MSR_K8_UCODE_UPDATE, is not documented by AMD. 382 * Coreboot, illumos and Linux source code was used to understand 383 * its workings. 384 */ 385static void 386amd_ucode_wrmsr(void *ucode_ptr) 387{ 388 uint32_t tmp[4]; 389 390 wrmsr_safe(MSR_K8_UCODE_UPDATE, (uintptr_t)ucode_ptr); 391 do_cpuid(0, tmp); 392} 393 394static int 395update_amd(int cpu, cpuctl_update_args_t *args, struct thread *td) 396{ 397 void *ptr; 398 int ret; 399 400 if (args->size == 0 || args->data == NULL) { 401 DPRINTF("[cpuctl,%d]: zero-sized firmware image", __LINE__); 402 return (EINVAL); 403 } 404 if (args->size > UCODE_SIZE_MAX) { 405 DPRINTF("[cpuctl,%d]: firmware image too large", __LINE__); 406 return (EINVAL); 407 } 408 409 /* 410 * 16 byte alignment required. Rely on the fact that 411 * malloc(9) always returns the pointer aligned at least on 412 * the size of the allocation. 413 */ 414 ptr = malloc(args->size + 16, M_CPUCTL, M_ZERO | M_WAITOK); 415 if (copyin(args->data, ptr, args->size) != 0) { 416 DPRINTF("[cpuctl,%d]: copyin %p->%p of %zd bytes failed", 417 __LINE__, args->data, ptr, args->size); 418 ret = EFAULT; 419 goto fail; 420 } 421 smp_rendezvous(NULL, amd_ucode_wrmsr, NULL, ptr); 422 ret = 0; 423fail: 424 free(ptr, M_CPUCTL); 425 return (ret); 426} 427 428static int 429update_via(int cpu, cpuctl_update_args_t *args, struct thread *td) 430{ 431 void *ptr; 432 uint64_t rev0, rev1, res; 433 uint32_t tmp[4]; 434 int is_bound; 435 int oldcpu; 436 int ret; 437 438 if (args->size == 0 || args->data == NULL) { 439 DPRINTF("[cpuctl,%d]: zero-sized firmware image", __LINE__); 440 return (EINVAL); 441 } 442 if (args->size > UCODE_SIZE_MAX) { 443 DPRINTF("[cpuctl,%d]: firmware image too large", __LINE__); 444 return (EINVAL); 445 } 446 447 /* 448 * 4 byte alignment required. 449 */ 450 ptr = malloc(args->size, M_CPUCTL, M_WAITOK); 451 if (copyin(args->data, ptr, args->size) != 0) { 452 DPRINTF("[cpuctl,%d]: copyin %p->%p of %zd bytes failed", 453 __LINE__, args->data, ptr, args->size); 454 ret = EFAULT; 455 goto fail; 456 } 457 oldcpu = td->td_oncpu; 458 is_bound = cpu_sched_is_bound(td); 459 set_cpu(cpu, td); 460 critical_enter(); 461 rdmsr_safe(MSR_BIOS_SIGN, &rev0); /* Get current microcode revision. */ 462 463 /* 464 * Perform update. 465 */ 466 wrmsr_safe(MSR_BIOS_UPDT_TRIG, (uintptr_t)(ptr)); 467 do_cpuid(1, tmp); 468 469 /* 470 * Result are in low byte of MSR FCR5: 471 * 0x00: No update has been attempted since RESET. 472 * 0x01: The last attempted update was successful. 473 * 0x02: The last attempted update was unsuccessful due to a bad 474 * environment. No update was loaded and any preexisting 475 * patches are still active. 476 * 0x03: The last attempted update was not applicable to this processor. 477 * No update was loaded and any preexisting patches are still 478 * active. 479 * 0x04: The last attempted update was not successful due to an invalid 480 * update data block. No update was loaded and any preexisting 481 * patches are still active 482 */ 483 rdmsr_safe(0x1205, &res); 484 res &= 0xff; 485 critical_exit(); 486 rdmsr_safe(MSR_BIOS_SIGN, &rev1); /* Get new microcode revision. */ 487 restore_cpu(oldcpu, is_bound, td); 488 489 DPRINTF("[cpu,%d]: rev0=%x rev1=%x res=%x\n", __LINE__, 490 (unsigned)(rev0 >> 32), (unsigned)(rev1 >> 32), (unsigned)res); 491 492 if (res != 0x01) 493 ret = EINVAL; 494 else 495 ret = 0; 496fail: 497 free(ptr, M_CPUCTL); 498 return (ret); 499} 500 501static int 502cpuctl_do_eval_cpu_features(int cpu, struct thread *td) 503{ 504 int is_bound = 0; 505 int oldcpu; 506 507 KASSERT(cpu >= 0 && cpu <= mp_maxid, 508 ("[cpuctl,%d]: bad cpu number %d", __LINE__, cpu)); 509 510#ifdef __i386__ 511 if (cpu_id == 0) 512 return (ENODEV); 513#endif 514 oldcpu = td->td_oncpu; 515 is_bound = cpu_sched_is_bound(td); 516 set_cpu(cpu, td); 517 identify_cpu1(); 518 identify_cpu2(); 519 hw_ibrs_recalculate(); 520 restore_cpu(oldcpu, is_bound, td); 521 hw_ssb_recalculate(true); 522 hw_mds_recalculate(); 523 printcpuinfo(); 524 return (0); 525} 526 527 528int 529cpuctl_open(struct cdev *dev, int flags, int fmt __unused, struct thread *td) 530{ 531 int ret = 0; 532 int cpu; 533 534 cpu = dev2unit(dev); 535 if (cpu > mp_maxid || !cpu_enabled(cpu)) { 536 DPRINTF("[cpuctl,%d]: incorrect cpu number %d\n", __LINE__, 537 cpu); 538 return (ENXIO); 539 } 540 if (flags & FWRITE) 541 ret = securelevel_gt(td->td_ucred, 0); 542 return (ret); 543} 544 545static int 546cpuctl_modevent(module_t mod __unused, int type, void *data __unused) 547{ 548 int cpu; 549 550 switch(type) { 551 case MOD_LOAD: 552 if (bootverbose) 553 printf("cpuctl: access to MSR registers/cpuid info.\n"); 554 cpuctl_devs = malloc(sizeof(*cpuctl_devs) * (mp_maxid + 1), M_CPUCTL, 555 M_WAITOK | M_ZERO); 556 CPU_FOREACH(cpu) 557 if (cpu_enabled(cpu)) 558 cpuctl_devs[cpu] = make_dev(&cpuctl_cdevsw, cpu, 559 UID_ROOT, GID_KMEM, 0640, "cpuctl%d", cpu); 560 break; 561 case MOD_UNLOAD: 562 CPU_FOREACH(cpu) { 563 if (cpuctl_devs[cpu] != NULL) 564 destroy_dev(cpuctl_devs[cpu]); 565 } 566 free(cpuctl_devs, M_CPUCTL); 567 break; 568 case MOD_SHUTDOWN: 569 break; 570 default: 571 return (EOPNOTSUPP); 572 } 573 return (0); 574} 575 576DEV_MODULE(cpuctl, cpuctl_modevent, NULL); 577MODULE_VERSION(cpuctl, CPUCTL_VERSION); 578