cesa.c revision 301224
1/*- 2 * Copyright (C) 2009-2011 Semihalf. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27/* 28 * CESA SRAM Memory Map: 29 * 30 * +------------------------+ <= sc->sc_sram_base_va + CESA_SRAM_SIZE 31 * | | 32 * | DATA | 33 * | | 34 * +------------------------+ <= sc->sc_sram_base_va + CESA_DATA(0) 35 * | struct cesa_sa_data | 36 * +------------------------+ 37 * | struct cesa_sa_hdesc | 38 * +------------------------+ <= sc->sc_sram_base_va 39 */ 40 41#include <sys/cdefs.h> 42__FBSDID("$FreeBSD: head/sys/dev/cesa/cesa.c 301224 2016-06-02 18:39:33Z zbb $"); 43 44#include <sys/param.h> 45#include <sys/systm.h> 46#include <sys/bus.h> 47#include <sys/endian.h> 48#include <sys/kernel.h> 49#include <sys/lock.h> 50#include <sys/mbuf.h> 51#include <sys/module.h> 52#include <sys/mutex.h> 53#include <sys/rman.h> 54 55#include <machine/bus.h> 56#include <machine/intr.h> 57#include <machine/resource.h> 58#include <machine/fdt.h> 59 60#include <dev/fdt/fdt_common.h> 61#include <dev/ofw/ofw_bus.h> 62#include <dev/ofw/ofw_bus_subr.h> 63 64#include <sys/md5.h> 65#include <crypto/sha1.h> 66#include <crypto/sha2/sha256.h> 67#include <crypto/rijndael/rijndael.h> 68#include <opencrypto/cryptodev.h> 69#include "cryptodev_if.h" 70 71#include <arm/mv/mvreg.h> 72#include <arm/mv/mvwin.h> 73#include <arm/mv/mvvar.h> 74#include "cesa.h" 75 76static int cesa_probe(device_t); 77static int cesa_attach(device_t); 78static int cesa_detach(device_t); 79static void cesa_intr(void *); 80static int cesa_newsession(device_t, u_int32_t *, struct cryptoini *); 81static int cesa_freesession(device_t, u_int64_t); 82static int cesa_process(device_t, struct cryptop *, int); 83static int decode_win_cesa_setup(struct cesa_softc *sc); 84 85static struct resource_spec cesa_res_spec[] = { 86 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 87 { SYS_RES_MEMORY, 1, RF_ACTIVE }, 88 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 89 { -1, 0 } 90}; 91 92static device_method_t cesa_methods[] = { 93 /* Device interface */ 94 DEVMETHOD(device_probe, cesa_probe), 95 DEVMETHOD(device_attach, cesa_attach), 96 DEVMETHOD(device_detach, cesa_detach), 97 98 /* Crypto device methods */ 99 DEVMETHOD(cryptodev_newsession, cesa_newsession), 100 DEVMETHOD(cryptodev_freesession,cesa_freesession), 101 DEVMETHOD(cryptodev_process, cesa_process), 102 103 DEVMETHOD_END 104}; 105 106static driver_t cesa_driver = { 107 "cesa", 108 cesa_methods, 109 sizeof (struct cesa_softc) 110}; 111static devclass_t cesa_devclass; 112 113DRIVER_MODULE(cesa, simplebus, cesa_driver, cesa_devclass, 0, 0); 114MODULE_DEPEND(cesa, crypto, 1, 1, 1); 115 116static void 117cesa_dump_cshd(struct cesa_softc *sc, struct cesa_sa_hdesc *cshd) 118{ 119#ifdef DEBUG 120 device_t dev; 121 122 dev = sc->sc_dev; 123 device_printf(dev, "CESA SA Hardware Descriptor:\n"); 124 device_printf(dev, "\t\tconfig: 0x%08X\n", cshd->cshd_config); 125 device_printf(dev, "\t\te_src: 0x%08X\n", cshd->cshd_enc_src); 126 device_printf(dev, "\t\te_dst: 0x%08X\n", cshd->cshd_enc_dst); 127 device_printf(dev, "\t\te_dlen: 0x%08X\n", cshd->cshd_enc_dlen); 128 device_printf(dev, "\t\te_key: 0x%08X\n", cshd->cshd_enc_key); 129 device_printf(dev, "\t\te_iv_1: 0x%08X\n", cshd->cshd_enc_iv); 130 device_printf(dev, "\t\te_iv_2: 0x%08X\n", cshd->cshd_enc_iv_buf); 131 device_printf(dev, "\t\tm_src: 0x%08X\n", cshd->cshd_mac_src); 132 device_printf(dev, "\t\tm_dst: 0x%08X\n", cshd->cshd_mac_dst); 133 device_printf(dev, "\t\tm_dlen: 0x%08X\n", cshd->cshd_mac_dlen); 134 device_printf(dev, "\t\tm_tlen: 0x%08X\n", cshd->cshd_mac_total_dlen); 135 device_printf(dev, "\t\tm_iv_i: 0x%08X\n", cshd->cshd_mac_iv_in); 136 device_printf(dev, "\t\tm_iv_o: 0x%08X\n", cshd->cshd_mac_iv_out); 137#endif 138} 139 140static void 141cesa_alloc_dma_mem_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 142{ 143 struct cesa_dma_mem *cdm; 144 145 if (error) 146 return; 147 148 KASSERT(nseg == 1, ("Got wrong number of DMA segments, should be 1.")); 149 cdm = arg; 150 cdm->cdm_paddr = segs->ds_addr; 151} 152 153static int 154cesa_alloc_dma_mem(struct cesa_softc *sc, struct cesa_dma_mem *cdm, 155 bus_size_t size) 156{ 157 int error; 158 159 KASSERT(cdm->cdm_vaddr == NULL, 160 ("%s(): DMA memory descriptor in use.", __func__)); 161 162 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), /* parent */ 163 PAGE_SIZE, 0, /* alignment, boundary */ 164 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 165 BUS_SPACE_MAXADDR, /* highaddr */ 166 NULL, NULL, /* filtfunc, filtfuncarg */ 167 size, 1, /* maxsize, nsegments */ 168 size, 0, /* maxsegsz, flags */ 169 NULL, NULL, /* lockfunc, lockfuncarg */ 170 &cdm->cdm_tag); /* dmat */ 171 if (error) { 172 device_printf(sc->sc_dev, "failed to allocate busdma tag, error" 173 " %i!\n", error); 174 175 goto err1; 176 } 177 178 error = bus_dmamem_alloc(cdm->cdm_tag, &cdm->cdm_vaddr, 179 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &cdm->cdm_map); 180 if (error) { 181 device_printf(sc->sc_dev, "failed to allocate DMA safe" 182 " memory, error %i!\n", error); 183 184 goto err2; 185 } 186 187 error = bus_dmamap_load(cdm->cdm_tag, cdm->cdm_map, cdm->cdm_vaddr, 188 size, cesa_alloc_dma_mem_cb, cdm, BUS_DMA_NOWAIT); 189 if (error) { 190 device_printf(sc->sc_dev, "cannot get address of the DMA" 191 " memory, error %i\n", error); 192 193 goto err3; 194 } 195 196 return (0); 197err3: 198 bus_dmamem_free(cdm->cdm_tag, cdm->cdm_vaddr, cdm->cdm_map); 199err2: 200 bus_dma_tag_destroy(cdm->cdm_tag); 201err1: 202 cdm->cdm_vaddr = NULL; 203 return (error); 204} 205 206static void 207cesa_free_dma_mem(struct cesa_dma_mem *cdm) 208{ 209 210 bus_dmamap_unload(cdm->cdm_tag, cdm->cdm_map); 211 bus_dmamem_free(cdm->cdm_tag, cdm->cdm_vaddr, cdm->cdm_map); 212 bus_dma_tag_destroy(cdm->cdm_tag); 213 cdm->cdm_vaddr = NULL; 214} 215 216static void 217cesa_sync_dma_mem(struct cesa_dma_mem *cdm, bus_dmasync_op_t op) 218{ 219 220 /* Sync only if dma memory is valid */ 221 if (cdm->cdm_vaddr != NULL) 222 bus_dmamap_sync(cdm->cdm_tag, cdm->cdm_map, op); 223} 224 225static void 226cesa_sync_desc(struct cesa_softc *sc, bus_dmasync_op_t op) 227{ 228 229 cesa_sync_dma_mem(&sc->sc_tdesc_cdm, op); 230 cesa_sync_dma_mem(&sc->sc_sdesc_cdm, op); 231 cesa_sync_dma_mem(&sc->sc_requests_cdm, op); 232} 233 234static struct cesa_session * 235cesa_alloc_session(struct cesa_softc *sc) 236{ 237 struct cesa_session *cs; 238 239 CESA_GENERIC_ALLOC_LOCKED(sc, cs, sessions); 240 241 return (cs); 242} 243 244static struct cesa_session * 245cesa_get_session(struct cesa_softc *sc, uint32_t sid) 246{ 247 248 if (sid >= CESA_SESSIONS) 249 return (NULL); 250 251 return (&sc->sc_sessions[sid]); 252} 253 254static void 255cesa_free_session(struct cesa_softc *sc, struct cesa_session *cs) 256{ 257 258 CESA_GENERIC_FREE_LOCKED(sc, cs, sessions); 259} 260 261static struct cesa_request * 262cesa_alloc_request(struct cesa_softc *sc) 263{ 264 struct cesa_request *cr; 265 266 CESA_GENERIC_ALLOC_LOCKED(sc, cr, requests); 267 if (!cr) 268 return (NULL); 269 270 STAILQ_INIT(&cr->cr_tdesc); 271 STAILQ_INIT(&cr->cr_sdesc); 272 273 return (cr); 274} 275 276static void 277cesa_free_request(struct cesa_softc *sc, struct cesa_request *cr) 278{ 279 280 /* Free TDMA descriptors assigned to this request */ 281 CESA_LOCK(sc, tdesc); 282 STAILQ_CONCAT(&sc->sc_free_tdesc, &cr->cr_tdesc); 283 CESA_UNLOCK(sc, tdesc); 284 285 /* Free SA descriptors assigned to this request */ 286 CESA_LOCK(sc, sdesc); 287 STAILQ_CONCAT(&sc->sc_free_sdesc, &cr->cr_sdesc); 288 CESA_UNLOCK(sc, sdesc); 289 290 /* Unload DMA memory associated with request */ 291 if (cr->cr_dmap_loaded) { 292 bus_dmamap_unload(sc->sc_data_dtag, cr->cr_dmap); 293 cr->cr_dmap_loaded = 0; 294 } 295 296 CESA_GENERIC_FREE_LOCKED(sc, cr, requests); 297} 298 299static void 300cesa_enqueue_request(struct cesa_softc *sc, struct cesa_request *cr) 301{ 302 303 CESA_LOCK(sc, requests); 304 STAILQ_INSERT_TAIL(&sc->sc_ready_requests, cr, cr_stq); 305 CESA_UNLOCK(sc, requests); 306} 307 308static struct cesa_tdma_desc * 309cesa_alloc_tdesc(struct cesa_softc *sc) 310{ 311 struct cesa_tdma_desc *ctd; 312 313 CESA_GENERIC_ALLOC_LOCKED(sc, ctd, tdesc); 314 315 if (!ctd) 316 device_printf(sc->sc_dev, "TDMA descriptors pool exhaused. " 317 "Consider increasing CESA_TDMA_DESCRIPTORS.\n"); 318 319 return (ctd); 320} 321 322static struct cesa_sa_desc * 323cesa_alloc_sdesc(struct cesa_softc *sc, struct cesa_request *cr) 324{ 325 struct cesa_sa_desc *csd; 326 327 CESA_GENERIC_ALLOC_LOCKED(sc, csd, sdesc); 328 if (!csd) { 329 device_printf(sc->sc_dev, "SA descriptors pool exhaused. " 330 "Consider increasing CESA_SA_DESCRIPTORS.\n"); 331 return (NULL); 332 } 333 334 STAILQ_INSERT_TAIL(&cr->cr_sdesc, csd, csd_stq); 335 336 /* Fill-in SA descriptor with default values */ 337 csd->csd_cshd->cshd_enc_key = CESA_SA_DATA(csd_key); 338 csd->csd_cshd->cshd_enc_iv = CESA_SA_DATA(csd_iv); 339 csd->csd_cshd->cshd_enc_iv_buf = CESA_SA_DATA(csd_iv); 340 csd->csd_cshd->cshd_enc_src = 0; 341 csd->csd_cshd->cshd_enc_dst = 0; 342 csd->csd_cshd->cshd_enc_dlen = 0; 343 csd->csd_cshd->cshd_mac_dst = CESA_SA_DATA(csd_hash); 344 csd->csd_cshd->cshd_mac_iv_in = CESA_SA_DATA(csd_hiv_in); 345 csd->csd_cshd->cshd_mac_iv_out = CESA_SA_DATA(csd_hiv_out); 346 csd->csd_cshd->cshd_mac_src = 0; 347 csd->csd_cshd->cshd_mac_dlen = 0; 348 349 return (csd); 350} 351 352static struct cesa_tdma_desc * 353cesa_tdma_copy(struct cesa_softc *sc, bus_addr_t dst, bus_addr_t src, 354 bus_size_t size) 355{ 356 struct cesa_tdma_desc *ctd; 357 358 ctd = cesa_alloc_tdesc(sc); 359 if (!ctd) 360 return (NULL); 361 362 ctd->ctd_cthd->cthd_dst = dst; 363 ctd->ctd_cthd->cthd_src = src; 364 ctd->ctd_cthd->cthd_byte_count = size; 365 366 /* Handle special control packet */ 367 if (size != 0) 368 ctd->ctd_cthd->cthd_flags = CESA_CTHD_OWNED; 369 else 370 ctd->ctd_cthd->cthd_flags = 0; 371 372 return (ctd); 373} 374 375static struct cesa_tdma_desc * 376cesa_tdma_copyin_sa_data(struct cesa_softc *sc, struct cesa_request *cr) 377{ 378 379 return (cesa_tdma_copy(sc, sc->sc_sram_base_pa + 380 sizeof(struct cesa_sa_hdesc), cr->cr_csd_paddr, 381 sizeof(struct cesa_sa_data))); 382} 383 384static struct cesa_tdma_desc * 385cesa_tdma_copyout_sa_data(struct cesa_softc *sc, struct cesa_request *cr) 386{ 387 388 return (cesa_tdma_copy(sc, cr->cr_csd_paddr, sc->sc_sram_base_pa + 389 sizeof(struct cesa_sa_hdesc), sizeof(struct cesa_sa_data))); 390} 391 392static struct cesa_tdma_desc * 393cesa_tdma_copy_sdesc(struct cesa_softc *sc, struct cesa_sa_desc *csd) 394{ 395 396 return (cesa_tdma_copy(sc, sc->sc_sram_base_pa, csd->csd_cshd_paddr, 397 sizeof(struct cesa_sa_hdesc))); 398} 399 400static void 401cesa_append_tdesc(struct cesa_request *cr, struct cesa_tdma_desc *ctd) 402{ 403 struct cesa_tdma_desc *ctd_prev; 404 405 if (!STAILQ_EMPTY(&cr->cr_tdesc)) { 406 ctd_prev = STAILQ_LAST(&cr->cr_tdesc, cesa_tdma_desc, ctd_stq); 407 ctd_prev->ctd_cthd->cthd_next = ctd->ctd_cthd_paddr; 408 } 409 410 ctd->ctd_cthd->cthd_next = 0; 411 STAILQ_INSERT_TAIL(&cr->cr_tdesc, ctd, ctd_stq); 412} 413 414static int 415cesa_append_packet(struct cesa_softc *sc, struct cesa_request *cr, 416 struct cesa_packet *cp, struct cesa_sa_desc *csd) 417{ 418 struct cesa_tdma_desc *ctd, *tmp; 419 420 /* Copy SA descriptor for this packet */ 421 ctd = cesa_tdma_copy_sdesc(sc, csd); 422 if (!ctd) 423 return (ENOMEM); 424 425 cesa_append_tdesc(cr, ctd); 426 427 /* Copy data to be processed */ 428 STAILQ_FOREACH_SAFE(ctd, &cp->cp_copyin, ctd_stq, tmp) 429 cesa_append_tdesc(cr, ctd); 430 STAILQ_INIT(&cp->cp_copyin); 431 432 /* Insert control descriptor */ 433 ctd = cesa_tdma_copy(sc, 0, 0, 0); 434 if (!ctd) 435 return (ENOMEM); 436 437 cesa_append_tdesc(cr, ctd); 438 439 /* Copy back results */ 440 STAILQ_FOREACH_SAFE(ctd, &cp->cp_copyout, ctd_stq, tmp) 441 cesa_append_tdesc(cr, ctd); 442 STAILQ_INIT(&cp->cp_copyout); 443 444 return (0); 445} 446 447static int 448cesa_set_mkey(struct cesa_session *cs, int alg, const uint8_t *mkey, int mklen) 449{ 450 uint8_t ipad[CESA_MAX_HMAC_BLOCK_LEN]; 451 uint8_t opad[CESA_MAX_HMAC_BLOCK_LEN]; 452 SHA1_CTX sha1ctx; 453 SHA256_CTX sha256ctx; 454 MD5_CTX md5ctx; 455 uint32_t *hout; 456 uint32_t *hin; 457 int i; 458 459 memset(ipad, HMAC_IPAD_VAL, CESA_MAX_HMAC_BLOCK_LEN); 460 memset(opad, HMAC_OPAD_VAL, CESA_MAX_HMAC_BLOCK_LEN); 461 for (i = 0; i < mklen; i++) { 462 ipad[i] ^= mkey[i]; 463 opad[i] ^= mkey[i]; 464 } 465 466 hin = (uint32_t *)cs->cs_hiv_in; 467 hout = (uint32_t *)cs->cs_hiv_out; 468 469 switch (alg) { 470 case CRYPTO_MD5_HMAC: 471 MD5Init(&md5ctx); 472 MD5Update(&md5ctx, ipad, MD5_HMAC_BLOCK_LEN); 473 memcpy(hin, md5ctx.state, sizeof(md5ctx.state)); 474 MD5Init(&md5ctx); 475 MD5Update(&md5ctx, opad, MD5_HMAC_BLOCK_LEN); 476 memcpy(hout, md5ctx.state, sizeof(md5ctx.state)); 477 break; 478 case CRYPTO_SHA1_HMAC: 479 SHA1Init(&sha1ctx); 480 SHA1Update(&sha1ctx, ipad, SHA1_HMAC_BLOCK_LEN); 481 memcpy(hin, sha1ctx.h.b32, sizeof(sha1ctx.h.b32)); 482 SHA1Init(&sha1ctx); 483 SHA1Update(&sha1ctx, opad, SHA1_HMAC_BLOCK_LEN); 484 memcpy(hout, sha1ctx.h.b32, sizeof(sha1ctx.h.b32)); 485 break; 486 case CRYPTO_SHA2_256_HMAC: 487 SHA256_Init(&sha256ctx); 488 SHA256_Update(&sha256ctx, ipad, SHA2_256_HMAC_BLOCK_LEN); 489 memcpy(hin, sha256ctx.state, sizeof(sha256ctx.state)); 490 SHA256_Init(&sha256ctx); 491 SHA256_Update(&sha256ctx, opad, SHA2_256_HMAC_BLOCK_LEN); 492 memcpy(hout, sha256ctx.state, sizeof(sha256ctx.state)); 493 break; 494 default: 495 return (EINVAL); 496 } 497 498 for (i = 0; i < CESA_MAX_HASH_LEN / sizeof(uint32_t); i++) { 499 hin[i] = htobe32(hin[i]); 500 hout[i] = htobe32(hout[i]); 501 } 502 503 return (0); 504} 505 506static int 507cesa_prep_aes_key(struct cesa_session *cs) 508{ 509 uint32_t ek[4 * (RIJNDAEL_MAXNR + 1)]; 510 uint32_t *dkey; 511 int i; 512 513 rijndaelKeySetupEnc(ek, cs->cs_key, cs->cs_klen * 8); 514 515 cs->cs_config &= ~CESA_CSH_AES_KLEN_MASK; 516 dkey = (uint32_t *)cs->cs_aes_dkey; 517 518 switch (cs->cs_klen) { 519 case 16: 520 cs->cs_config |= CESA_CSH_AES_KLEN_128; 521 for (i = 0; i < 4; i++) 522 *dkey++ = htobe32(ek[4 * 10 + i]); 523 break; 524 case 24: 525 cs->cs_config |= CESA_CSH_AES_KLEN_192; 526 for (i = 0; i < 4; i++) 527 *dkey++ = htobe32(ek[4 * 12 + i]); 528 for (i = 0; i < 2; i++) 529 *dkey++ = htobe32(ek[4 * 11 + 2 + i]); 530 break; 531 case 32: 532 cs->cs_config |= CESA_CSH_AES_KLEN_256; 533 for (i = 0; i < 4; i++) 534 *dkey++ = htobe32(ek[4 * 14 + i]); 535 for (i = 0; i < 4; i++) 536 *dkey++ = htobe32(ek[4 * 13 + i]); 537 break; 538 default: 539 return (EINVAL); 540 } 541 542 return (0); 543} 544 545static int 546cesa_is_hash(int alg) 547{ 548 549 switch (alg) { 550 case CRYPTO_MD5: 551 case CRYPTO_MD5_HMAC: 552 case CRYPTO_SHA1: 553 case CRYPTO_SHA1_HMAC: 554 case CRYPTO_SHA2_256_HMAC: 555 return (1); 556 default: 557 return (0); 558 } 559} 560 561static void 562cesa_start_packet(struct cesa_packet *cp, unsigned int size) 563{ 564 565 cp->cp_size = size; 566 cp->cp_offset = 0; 567 STAILQ_INIT(&cp->cp_copyin); 568 STAILQ_INIT(&cp->cp_copyout); 569} 570 571static int 572cesa_fill_packet(struct cesa_softc *sc, struct cesa_packet *cp, 573 bus_dma_segment_t *seg) 574{ 575 struct cesa_tdma_desc *ctd; 576 unsigned int bsize; 577 578 /* Calculate size of block copy */ 579 bsize = MIN(seg->ds_len, cp->cp_size - cp->cp_offset); 580 581 if (bsize > 0) { 582 ctd = cesa_tdma_copy(sc, sc->sc_sram_base_pa + 583 CESA_DATA(cp->cp_offset), seg->ds_addr, bsize); 584 if (!ctd) 585 return (-ENOMEM); 586 587 STAILQ_INSERT_TAIL(&cp->cp_copyin, ctd, ctd_stq); 588 589 ctd = cesa_tdma_copy(sc, seg->ds_addr, sc->sc_sram_base_pa + 590 CESA_DATA(cp->cp_offset), bsize); 591 if (!ctd) 592 return (-ENOMEM); 593 594 STAILQ_INSERT_TAIL(&cp->cp_copyout, ctd, ctd_stq); 595 596 seg->ds_len -= bsize; 597 seg->ds_addr += bsize; 598 cp->cp_offset += bsize; 599 } 600 601 return (bsize); 602} 603 604static void 605cesa_create_chain_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 606{ 607 unsigned int mpsize, fragmented; 608 unsigned int mlen, mskip, tmlen; 609 struct cesa_chain_info *cci; 610 unsigned int elen, eskip; 611 unsigned int skip, len; 612 struct cesa_sa_desc *csd; 613 struct cesa_request *cr; 614 struct cesa_softc *sc; 615 struct cesa_packet cp; 616 bus_dma_segment_t seg; 617 uint32_t config; 618 int size; 619 620 cci = arg; 621 sc = cci->cci_sc; 622 cr = cci->cci_cr; 623 624 if (error) { 625 cci->cci_error = error; 626 return; 627 } 628 629 elen = cci->cci_enc ? cci->cci_enc->crd_len : 0; 630 eskip = cci->cci_enc ? cci->cci_enc->crd_skip : 0; 631 mlen = cci->cci_mac ? cci->cci_mac->crd_len : 0; 632 mskip = cci->cci_mac ? cci->cci_mac->crd_skip : 0; 633 634 if (elen && mlen && 635 ((eskip > mskip && ((eskip - mskip) & (cr->cr_cs->cs_ivlen - 1))) || 636 (mskip > eskip && ((mskip - eskip) & (cr->cr_cs->cs_mblen - 1))) || 637 (eskip > (mskip + mlen)) || (mskip > (eskip + elen)))) { 638 /* 639 * Data alignment in the request does not meet CESA requiremnts 640 * for combined encryption/decryption and hashing. We have to 641 * split the request to separate operations and process them 642 * one by one. 643 */ 644 config = cci->cci_config; 645 if ((config & CESA_CSHD_OP_MASK) == CESA_CSHD_MAC_AND_ENC) { 646 config &= ~CESA_CSHD_OP_MASK; 647 648 cci->cci_config = config | CESA_CSHD_MAC; 649 cci->cci_enc = NULL; 650 cci->cci_mac = cr->cr_mac; 651 cesa_create_chain_cb(cci, segs, nseg, cci->cci_error); 652 653 cci->cci_config = config | CESA_CSHD_ENC; 654 cci->cci_enc = cr->cr_enc; 655 cci->cci_mac = NULL; 656 cesa_create_chain_cb(cci, segs, nseg, cci->cci_error); 657 } else { 658 config &= ~CESA_CSHD_OP_MASK; 659 660 cci->cci_config = config | CESA_CSHD_ENC; 661 cci->cci_enc = cr->cr_enc; 662 cci->cci_mac = NULL; 663 cesa_create_chain_cb(cci, segs, nseg, cci->cci_error); 664 665 cci->cci_config = config | CESA_CSHD_MAC; 666 cci->cci_enc = NULL; 667 cci->cci_mac = cr->cr_mac; 668 cesa_create_chain_cb(cci, segs, nseg, cci->cci_error); 669 } 670 671 return; 672 } 673 674 tmlen = mlen; 675 fragmented = 0; 676 mpsize = CESA_MAX_PACKET_SIZE; 677 mpsize &= ~((cr->cr_cs->cs_ivlen - 1) | (cr->cr_cs->cs_mblen - 1)); 678 679 if (elen && mlen) { 680 skip = MIN(eskip, mskip); 681 len = MAX(elen + eskip, mlen + mskip) - skip; 682 } else if (elen) { 683 skip = eskip; 684 len = elen; 685 } else { 686 skip = mskip; 687 len = mlen; 688 } 689 690 /* Start first packet in chain */ 691 cesa_start_packet(&cp, MIN(mpsize, len)); 692 693 while (nseg-- && len > 0) { 694 seg = *(segs++); 695 696 /* 697 * Skip data in buffer on which neither ENC nor MAC operation 698 * is requested. 699 */ 700 if (skip > 0) { 701 size = MIN(skip, seg.ds_len); 702 skip -= size; 703 704 seg.ds_addr += size; 705 seg.ds_len -= size; 706 707 if (eskip > 0) 708 eskip -= size; 709 710 if (mskip > 0) 711 mskip -= size; 712 713 if (seg.ds_len == 0) 714 continue; 715 } 716 717 while (1) { 718 /* 719 * Fill in current packet with data. Break if there is 720 * no more data in current DMA segment or an error 721 * occurred. 722 */ 723 size = cesa_fill_packet(sc, &cp, &seg); 724 if (size <= 0) { 725 error = -size; 726 break; 727 } 728 729 len -= size; 730 731 /* If packet is full, append it to the chain */ 732 if (cp.cp_size == cp.cp_offset) { 733 csd = cesa_alloc_sdesc(sc, cr); 734 if (!csd) { 735 error = ENOMEM; 736 break; 737 } 738 739 /* Create SA descriptor for this packet */ 740 csd->csd_cshd->cshd_config = cci->cci_config; 741 csd->csd_cshd->cshd_mac_total_dlen = tmlen; 742 743 /* 744 * Enable fragmentation if request will not fit 745 * into one packet. 746 */ 747 if (len > 0) { 748 if (!fragmented) { 749 fragmented = 1; 750 csd->csd_cshd->cshd_config |= 751 CESA_CSHD_FRAG_FIRST; 752 } else 753 csd->csd_cshd->cshd_config |= 754 CESA_CSHD_FRAG_MIDDLE; 755 } else if (fragmented) 756 csd->csd_cshd->cshd_config |= 757 CESA_CSHD_FRAG_LAST; 758 759 if (eskip < cp.cp_size && elen > 0) { 760 csd->csd_cshd->cshd_enc_src = 761 CESA_DATA(eskip); 762 csd->csd_cshd->cshd_enc_dst = 763 CESA_DATA(eskip); 764 csd->csd_cshd->cshd_enc_dlen = 765 MIN(elen, cp.cp_size - eskip); 766 } 767 768 if (mskip < cp.cp_size && mlen > 0) { 769 csd->csd_cshd->cshd_mac_src = 770 CESA_DATA(mskip); 771 csd->csd_cshd->cshd_mac_dlen = 772 MIN(mlen, cp.cp_size - mskip); 773 } 774 775 elen -= csd->csd_cshd->cshd_enc_dlen; 776 eskip -= MIN(eskip, cp.cp_size); 777 mlen -= csd->csd_cshd->cshd_mac_dlen; 778 mskip -= MIN(mskip, cp.cp_size); 779 780 cesa_dump_cshd(sc, csd->csd_cshd); 781 782 /* Append packet to the request */ 783 error = cesa_append_packet(sc, cr, &cp, csd); 784 if (error) 785 break; 786 787 /* Start a new packet, as current is full */ 788 cesa_start_packet(&cp, MIN(mpsize, len)); 789 } 790 } 791 792 if (error) 793 break; 794 } 795 796 if (error) { 797 /* 798 * Move all allocated resources to the request. They will be 799 * freed later. 800 */ 801 STAILQ_CONCAT(&cr->cr_tdesc, &cp.cp_copyin); 802 STAILQ_CONCAT(&cr->cr_tdesc, &cp.cp_copyout); 803 cci->cci_error = error; 804 } 805} 806 807static void 808cesa_create_chain_cb2(void *arg, bus_dma_segment_t *segs, int nseg, 809 bus_size_t size, int error) 810{ 811 812 cesa_create_chain_cb(arg, segs, nseg, error); 813} 814 815static int 816cesa_create_chain(struct cesa_softc *sc, struct cesa_request *cr) 817{ 818 struct cesa_chain_info cci; 819 struct cesa_tdma_desc *ctd; 820 uint32_t config; 821 int error; 822 823 error = 0; 824 CESA_LOCK_ASSERT(sc, sessions); 825 826 /* Create request metadata */ 827 if (cr->cr_enc) { 828 if (cr->cr_enc->crd_alg == CRYPTO_AES_CBC && 829 (cr->cr_enc->crd_flags & CRD_F_ENCRYPT) == 0) 830 memcpy(cr->cr_csd->csd_key, cr->cr_cs->cs_aes_dkey, 831 cr->cr_cs->cs_klen); 832 else 833 memcpy(cr->cr_csd->csd_key, cr->cr_cs->cs_key, 834 cr->cr_cs->cs_klen); 835 } 836 837 if (cr->cr_mac) { 838 memcpy(cr->cr_csd->csd_hiv_in, cr->cr_cs->cs_hiv_in, 839 CESA_MAX_HASH_LEN); 840 memcpy(cr->cr_csd->csd_hiv_out, cr->cr_cs->cs_hiv_out, 841 CESA_MAX_HASH_LEN); 842 } 843 844 ctd = cesa_tdma_copyin_sa_data(sc, cr); 845 if (!ctd) 846 return (ENOMEM); 847 848 cesa_append_tdesc(cr, ctd); 849 850 /* Prepare SA configuration */ 851 config = cr->cr_cs->cs_config; 852 853 if (cr->cr_enc && (cr->cr_enc->crd_flags & CRD_F_ENCRYPT) == 0) 854 config |= CESA_CSHD_DECRYPT; 855 if (cr->cr_enc && !cr->cr_mac) 856 config |= CESA_CSHD_ENC; 857 if (!cr->cr_enc && cr->cr_mac) 858 config |= CESA_CSHD_MAC; 859 if (cr->cr_enc && cr->cr_mac) 860 config |= (config & CESA_CSHD_DECRYPT) ? CESA_CSHD_MAC_AND_ENC : 861 CESA_CSHD_ENC_AND_MAC; 862 863 /* Create data packets */ 864 cci.cci_sc = sc; 865 cci.cci_cr = cr; 866 cci.cci_enc = cr->cr_enc; 867 cci.cci_mac = cr->cr_mac; 868 cci.cci_config = config; 869 cci.cci_error = 0; 870 871 if (cr->cr_crp->crp_flags & CRYPTO_F_IOV) 872 error = bus_dmamap_load_uio(sc->sc_data_dtag, 873 cr->cr_dmap, (struct uio *)cr->cr_crp->crp_buf, 874 cesa_create_chain_cb2, &cci, BUS_DMA_NOWAIT); 875 else if (cr->cr_crp->crp_flags & CRYPTO_F_IMBUF) 876 error = bus_dmamap_load_mbuf(sc->sc_data_dtag, 877 cr->cr_dmap, (struct mbuf *)cr->cr_crp->crp_buf, 878 cesa_create_chain_cb2, &cci, BUS_DMA_NOWAIT); 879 else 880 error = bus_dmamap_load(sc->sc_data_dtag, 881 cr->cr_dmap, cr->cr_crp->crp_buf, 882 cr->cr_crp->crp_ilen, cesa_create_chain_cb, &cci, 883 BUS_DMA_NOWAIT); 884 885 if (!error) 886 cr->cr_dmap_loaded = 1; 887 888 if (cci.cci_error) 889 error = cci.cci_error; 890 891 if (error) 892 return (error); 893 894 /* Read back request metadata */ 895 ctd = cesa_tdma_copyout_sa_data(sc, cr); 896 if (!ctd) 897 return (ENOMEM); 898 899 cesa_append_tdesc(cr, ctd); 900 901 return (0); 902} 903 904static void 905cesa_execute(struct cesa_softc *sc) 906{ 907 struct cesa_tdma_desc *prev_ctd, *ctd; 908 struct cesa_request *prev_cr, *cr; 909 910 CESA_LOCK(sc, requests); 911 912 /* 913 * If ready list is empty, there is nothing to execute. If queued list 914 * is not empty, the hardware is busy and we cannot start another 915 * execution. 916 */ 917 if (STAILQ_EMPTY(&sc->sc_ready_requests) || 918 !STAILQ_EMPTY(&sc->sc_queued_requests)) { 919 CESA_UNLOCK(sc, requests); 920 return; 921 } 922 923 /* Move all ready requests to queued list */ 924 STAILQ_CONCAT(&sc->sc_queued_requests, &sc->sc_ready_requests); 925 STAILQ_INIT(&sc->sc_ready_requests); 926 927 /* Create one execution chain from all requests on the list */ 928 if (STAILQ_FIRST(&sc->sc_queued_requests) != 929 STAILQ_LAST(&sc->sc_queued_requests, cesa_request, cr_stq)) { 930 prev_cr = NULL; 931 cesa_sync_dma_mem(&sc->sc_tdesc_cdm, BUS_DMASYNC_POSTREAD | 932 BUS_DMASYNC_POSTWRITE); 933 934 STAILQ_FOREACH(cr, &sc->sc_queued_requests, cr_stq) { 935 if (prev_cr) { 936 ctd = STAILQ_FIRST(&cr->cr_tdesc); 937 prev_ctd = STAILQ_LAST(&prev_cr->cr_tdesc, 938 cesa_tdma_desc, ctd_stq); 939 940 prev_ctd->ctd_cthd->cthd_next = 941 ctd->ctd_cthd_paddr; 942 } 943 944 prev_cr = cr; 945 } 946 947 cesa_sync_dma_mem(&sc->sc_tdesc_cdm, BUS_DMASYNC_PREREAD | 948 BUS_DMASYNC_PREWRITE); 949 } 950 951 /* Start chain execution in hardware */ 952 cr = STAILQ_FIRST(&sc->sc_queued_requests); 953 ctd = STAILQ_FIRST(&cr->cr_tdesc); 954 955 CESA_TDMA_WRITE(sc, CESA_TDMA_ND, ctd->ctd_cthd_paddr); 956#if defined (SOC_MV_ARMADA38X) 957 CESA_REG_WRITE(sc, CESA_SA_CMD, CESA_SA_CMD_ACTVATE | CESA_SA_CMD_SHA2); 958#else 959 CESA_REG_WRITE(sc, CESA_SA_CMD, CESA_SA_CMD_ACTVATE); 960#endif 961 962 CESA_UNLOCK(sc, requests); 963} 964 965static int 966cesa_setup_sram(struct cesa_softc *sc) 967{ 968 phandle_t sram_node; 969 ihandle_t sram_ihandle; 970 pcell_t sram_handle, sram_reg[2]; 971 int rv; 972 973 rv = OF_getprop(ofw_bus_get_node(sc->sc_dev), "sram-handle", 974 (void *)&sram_handle, sizeof(sram_handle)); 975 if (rv <= 0) 976 return (rv); 977 978 sram_ihandle = (ihandle_t)sram_handle; 979 sram_ihandle = fdt32_to_cpu(sram_ihandle); 980 sram_node = OF_instance_to_package(sram_ihandle); 981 982 rv = OF_getprop(sram_node, "reg", (void *)sram_reg, sizeof(sram_reg)); 983 if (rv <= 0) 984 return (rv); 985 986 sc->sc_sram_base_pa = fdt32_to_cpu(sram_reg[0]); 987 /* Store SRAM size to be able to unmap in detach() */ 988 sc->sc_sram_size = fdt32_to_cpu(sram_reg[1]); 989 990#if defined(SOC_MV_ARMADA38X) 991 /* SRAM memory was not mapped in platform_sram_devmap(), map it now */ 992 rv = bus_space_map(fdtbus_bs_tag, sc->sc_sram_base_pa, sc->sc_sram_size, 993 0, &(sc->sc_sram_base_va)); 994 if (rv != 0) 995 return (rv); 996#endif 997 return (0); 998} 999 1000static int 1001cesa_probe(device_t dev) 1002{ 1003 1004 if (!ofw_bus_status_okay(dev)) 1005 return (ENXIO); 1006 1007 if (!ofw_bus_is_compatible(dev, "mrvl,cesa")) 1008 return (ENXIO); 1009 1010 device_set_desc(dev, "Marvell Cryptographic Engine and Security " 1011 "Accelerator"); 1012 1013 return (BUS_PROBE_DEFAULT); 1014} 1015 1016static int 1017cesa_attach(device_t dev) 1018{ 1019 struct cesa_softc *sc; 1020 uint32_t d, r; 1021 int error; 1022 int i; 1023 1024 sc = device_get_softc(dev); 1025 sc->sc_blocked = 0; 1026 sc->sc_error = 0; 1027 sc->sc_dev = dev; 1028 1029 /* Check if CESA peripheral device has power turned on */ 1030#if defined(SOC_MV_KIRKWOOD) 1031 if (soc_power_ctrl_get(CPU_PM_CTRL_CRYPTO) == CPU_PM_CTRL_CRYPTO) { 1032 device_printf(dev, "not powered on\n"); 1033 return (ENXIO); 1034 } 1035#else 1036 if (soc_power_ctrl_get(CPU_PM_CTRL_CRYPTO) != CPU_PM_CTRL_CRYPTO) { 1037 device_printf(dev, "not powered on\n"); 1038 return (ENXIO); 1039 } 1040#endif 1041 soc_id(&d, &r); 1042 1043 switch (d) { 1044 case MV_DEV_88F6281: 1045 case MV_DEV_88F6282: 1046 sc->sc_tperr = 0; 1047 break; 1048 case MV_DEV_MV78100: 1049 case MV_DEV_MV78100_Z0: 1050 sc->sc_tperr = CESA_ICR_TPERR; 1051 break; 1052 default: 1053 return (ENXIO); 1054 } 1055 1056 /* Initialize mutexes */ 1057 mtx_init(&sc->sc_sc_lock, device_get_nameunit(dev), 1058 "CESA Shared Data", MTX_DEF); 1059 mtx_init(&sc->sc_tdesc_lock, device_get_nameunit(dev), 1060 "CESA TDMA Descriptors Pool", MTX_DEF); 1061 mtx_init(&sc->sc_sdesc_lock, device_get_nameunit(dev), 1062 "CESA SA Descriptors Pool", MTX_DEF); 1063 mtx_init(&sc->sc_requests_lock, device_get_nameunit(dev), 1064 "CESA Requests Pool", MTX_DEF); 1065 mtx_init(&sc->sc_sessions_lock, device_get_nameunit(dev), 1066 "CESA Sessions Pool", MTX_DEF); 1067 1068 /* Allocate I/O and IRQ resources */ 1069 error = bus_alloc_resources(dev, cesa_res_spec, sc->sc_res); 1070 if (error) { 1071 device_printf(dev, "could not allocate resources\n"); 1072 goto err0; 1073 } 1074 1075 /* Setup CESA decoding windows */ 1076 error = decode_win_cesa_setup(sc); 1077 if (error) { 1078 device_printf(dev, "could not setup decoding windows\n"); 1079 goto err1; 1080 } 1081 1082 /* Acquire SRAM base address */ 1083 error = cesa_setup_sram(sc); 1084 if (error) { 1085 device_printf(dev, "could not setup SRAM\n"); 1086 goto err1; 1087 } 1088 1089 /* Setup interrupt handler */ 1090 error = bus_setup_intr(dev, sc->sc_res[RES_CESA_IRQ], INTR_TYPE_NET | 1091 INTR_MPSAFE, NULL, cesa_intr, sc, &(sc->sc_icookie)); 1092 if (error) { 1093 device_printf(dev, "could not setup engine completion irq\n"); 1094 goto err2; 1095 } 1096 1097 /* Create DMA tag for processed data */ 1098 error = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1099 1, 0, /* alignment, boundary */ 1100 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1101 BUS_SPACE_MAXADDR, /* highaddr */ 1102 NULL, NULL, /* filtfunc, filtfuncarg */ 1103 CESA_MAX_REQUEST_SIZE, /* maxsize */ 1104 CESA_MAX_FRAGMENTS, /* nsegments */ 1105 CESA_MAX_REQUEST_SIZE, 0, /* maxsegsz, flags */ 1106 NULL, NULL, /* lockfunc, lockfuncarg */ 1107 &sc->sc_data_dtag); /* dmat */ 1108 if (error) 1109 goto err3; 1110 1111 /* Initialize data structures: TDMA Descriptors Pool */ 1112 error = cesa_alloc_dma_mem(sc, &sc->sc_tdesc_cdm, 1113 CESA_TDMA_DESCRIPTORS * sizeof(struct cesa_tdma_hdesc)); 1114 if (error) 1115 goto err4; 1116 1117 STAILQ_INIT(&sc->sc_free_tdesc); 1118 for (i = 0; i < CESA_TDMA_DESCRIPTORS; i++) { 1119 sc->sc_tdesc[i].ctd_cthd = 1120 (struct cesa_tdma_hdesc *)(sc->sc_tdesc_cdm.cdm_vaddr) + i; 1121 sc->sc_tdesc[i].ctd_cthd_paddr = sc->sc_tdesc_cdm.cdm_paddr + 1122 (i * sizeof(struct cesa_tdma_hdesc)); 1123 STAILQ_INSERT_TAIL(&sc->sc_free_tdesc, &sc->sc_tdesc[i], 1124 ctd_stq); 1125 } 1126 1127 /* Initialize data structures: SA Descriptors Pool */ 1128 error = cesa_alloc_dma_mem(sc, &sc->sc_sdesc_cdm, 1129 CESA_SA_DESCRIPTORS * sizeof(struct cesa_sa_hdesc)); 1130 if (error) 1131 goto err5; 1132 1133 STAILQ_INIT(&sc->sc_free_sdesc); 1134 for (i = 0; i < CESA_SA_DESCRIPTORS; i++) { 1135 sc->sc_sdesc[i].csd_cshd = 1136 (struct cesa_sa_hdesc *)(sc->sc_sdesc_cdm.cdm_vaddr) + i; 1137 sc->sc_sdesc[i].csd_cshd_paddr = sc->sc_sdesc_cdm.cdm_paddr + 1138 (i * sizeof(struct cesa_sa_hdesc)); 1139 STAILQ_INSERT_TAIL(&sc->sc_free_sdesc, &sc->sc_sdesc[i], 1140 csd_stq); 1141 } 1142 1143 /* Initialize data structures: Requests Pool */ 1144 error = cesa_alloc_dma_mem(sc, &sc->sc_requests_cdm, 1145 CESA_REQUESTS * sizeof(struct cesa_sa_data)); 1146 if (error) 1147 goto err6; 1148 1149 STAILQ_INIT(&sc->sc_free_requests); 1150 STAILQ_INIT(&sc->sc_ready_requests); 1151 STAILQ_INIT(&sc->sc_queued_requests); 1152 for (i = 0; i < CESA_REQUESTS; i++) { 1153 sc->sc_requests[i].cr_csd = 1154 (struct cesa_sa_data *)(sc->sc_requests_cdm.cdm_vaddr) + i; 1155 sc->sc_requests[i].cr_csd_paddr = 1156 sc->sc_requests_cdm.cdm_paddr + 1157 (i * sizeof(struct cesa_sa_data)); 1158 1159 /* Preallocate DMA maps */ 1160 error = bus_dmamap_create(sc->sc_data_dtag, 0, 1161 &sc->sc_requests[i].cr_dmap); 1162 if (error && i > 0) { 1163 i--; 1164 do { 1165 bus_dmamap_destroy(sc->sc_data_dtag, 1166 sc->sc_requests[i].cr_dmap); 1167 } while (i--); 1168 1169 goto err7; 1170 } 1171 1172 STAILQ_INSERT_TAIL(&sc->sc_free_requests, &sc->sc_requests[i], 1173 cr_stq); 1174 } 1175 1176 /* Initialize data structures: Sessions Pool */ 1177 STAILQ_INIT(&sc->sc_free_sessions); 1178 for (i = 0; i < CESA_SESSIONS; i++) { 1179 sc->sc_sessions[i].cs_sid = i; 1180 STAILQ_INSERT_TAIL(&sc->sc_free_sessions, &sc->sc_sessions[i], 1181 cs_stq); 1182 } 1183 1184 /* 1185 * Initialize TDMA: 1186 * - Burst limit: 128 bytes, 1187 * - Outstanding reads enabled, 1188 * - No byte-swap. 1189 */ 1190 CESA_TDMA_WRITE(sc, CESA_TDMA_CR, CESA_TDMA_CR_DBL128 | 1191 CESA_TDMA_CR_SBL128 | CESA_TDMA_CR_ORDEN | CESA_TDMA_CR_NBS | 1192#if defined (SOC_MV_ARMADA38X) 1193 CESA_TDMA_NUM_OUTSTAND | 1194#endif 1195 CESA_TDMA_CR_ENABLE); 1196 1197 /* 1198 * Initialize SA: 1199 * - SA descriptor is present at beginning of CESA SRAM, 1200 * - Multi-packet chain mode, 1201 * - Cooperation with TDMA enabled. 1202 */ 1203 CESA_REG_WRITE(sc, CESA_SA_DPR, 0); 1204 CESA_REG_WRITE(sc, CESA_SA_CR, CESA_SA_CR_ACTIVATE_TDMA | 1205 CESA_SA_CR_WAIT_FOR_TDMA | CESA_SA_CR_MULTI_MODE); 1206 1207 /* Unmask interrupts */ 1208 CESA_REG_WRITE(sc, CESA_ICR, 0); 1209 CESA_REG_WRITE(sc, CESA_ICM, CESA_ICM_ACCTDMA | sc->sc_tperr); 1210 CESA_TDMA_WRITE(sc, CESA_TDMA_ECR, 0); 1211 CESA_TDMA_WRITE(sc, CESA_TDMA_EMR, CESA_TDMA_EMR_MISS | 1212 CESA_TDMA_EMR_DOUBLE_HIT | CESA_TDMA_EMR_BOTH_HIT | 1213 CESA_TDMA_EMR_DATA_ERROR); 1214 1215 /* Register in OCF */ 1216 sc->sc_cid = crypto_get_driverid(dev, CRYPTOCAP_F_HARDWARE); 1217 if (sc->sc_cid) { 1218 device_printf(dev, "could not get crypto driver id\n"); 1219 goto err8; 1220 } 1221 1222 crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0); 1223 crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0); 1224 crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0); 1225 crypto_register(sc->sc_cid, CRYPTO_MD5, 0, 0); 1226 crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0); 1227 crypto_register(sc->sc_cid, CRYPTO_SHA1, 0, 0); 1228 crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0); 1229 crypto_register(sc->sc_cid, CRYPTO_SHA2_256_HMAC, 0, 0); 1230 1231 return (0); 1232err8: 1233 for (i = 0; i < CESA_REQUESTS; i++) 1234 bus_dmamap_destroy(sc->sc_data_dtag, 1235 sc->sc_requests[i].cr_dmap); 1236err7: 1237 cesa_free_dma_mem(&sc->sc_requests_cdm); 1238err6: 1239 cesa_free_dma_mem(&sc->sc_sdesc_cdm); 1240err5: 1241 cesa_free_dma_mem(&sc->sc_tdesc_cdm); 1242err4: 1243 bus_dma_tag_destroy(sc->sc_data_dtag); 1244err3: 1245 bus_teardown_intr(dev, sc->sc_res[RES_CESA_IRQ], sc->sc_icookie); 1246err2: 1247#if defined(SOC_MV_ARMADA38X) 1248 bus_space_unmap(fdtbus_bs_tag, sc->sc_sram_base_va, sc->sc_sram_size); 1249#endif 1250err1: 1251 bus_release_resources(dev, cesa_res_spec, sc->sc_res); 1252err0: 1253 mtx_destroy(&sc->sc_sessions_lock); 1254 mtx_destroy(&sc->sc_requests_lock); 1255 mtx_destroy(&sc->sc_sdesc_lock); 1256 mtx_destroy(&sc->sc_tdesc_lock); 1257 mtx_destroy(&sc->sc_sc_lock); 1258 return (ENXIO); 1259} 1260 1261static int 1262cesa_detach(device_t dev) 1263{ 1264 struct cesa_softc *sc; 1265 int i; 1266 1267 sc = device_get_softc(dev); 1268 1269 /* TODO: Wait for queued requests completion before shutdown. */ 1270 1271 /* Mask interrupts */ 1272 CESA_REG_WRITE(sc, CESA_ICM, 0); 1273 CESA_TDMA_WRITE(sc, CESA_TDMA_EMR, 0); 1274 1275 /* Unregister from OCF */ 1276 crypto_unregister_all(sc->sc_cid); 1277 1278 /* Free DMA Maps */ 1279 for (i = 0; i < CESA_REQUESTS; i++) 1280 bus_dmamap_destroy(sc->sc_data_dtag, 1281 sc->sc_requests[i].cr_dmap); 1282 1283 /* Free DMA Memory */ 1284 cesa_free_dma_mem(&sc->sc_requests_cdm); 1285 cesa_free_dma_mem(&sc->sc_sdesc_cdm); 1286 cesa_free_dma_mem(&sc->sc_tdesc_cdm); 1287 1288 /* Free DMA Tag */ 1289 bus_dma_tag_destroy(sc->sc_data_dtag); 1290 1291 /* Stop interrupt */ 1292 bus_teardown_intr(dev, sc->sc_res[RES_CESA_IRQ], sc->sc_icookie); 1293 1294 /* Relase I/O and IRQ resources */ 1295 bus_release_resources(dev, cesa_res_spec, sc->sc_res); 1296 1297#if defined(SOC_MV_ARMADA38X) 1298 /* Unmap SRAM memory */ 1299 bus_space_unmap(fdtbus_bs_tag, sc->sc_sram_base_va, sc->sc_sram_size); 1300#endif 1301 /* Destroy mutexes */ 1302 mtx_destroy(&sc->sc_sessions_lock); 1303 mtx_destroy(&sc->sc_requests_lock); 1304 mtx_destroy(&sc->sc_sdesc_lock); 1305 mtx_destroy(&sc->sc_tdesc_lock); 1306 mtx_destroy(&sc->sc_sc_lock); 1307 1308 return (0); 1309} 1310 1311static void 1312cesa_intr(void *arg) 1313{ 1314 STAILQ_HEAD(, cesa_request) requests; 1315 struct cesa_request *cr, *tmp; 1316 struct cesa_softc *sc; 1317 uint32_t ecr, icr; 1318 int blocked; 1319 1320 sc = arg; 1321 1322 /* Ack interrupt */ 1323 ecr = CESA_TDMA_READ(sc, CESA_TDMA_ECR); 1324 CESA_TDMA_WRITE(sc, CESA_TDMA_ECR, 0); 1325 icr = CESA_REG_READ(sc, CESA_ICR); 1326 CESA_REG_WRITE(sc, CESA_ICR, 0); 1327 1328 /* Check for TDMA errors */ 1329 if (ecr & CESA_TDMA_ECR_MISS) { 1330 device_printf(sc->sc_dev, "TDMA Miss error detected!\n"); 1331 sc->sc_error = EIO; 1332 } 1333 1334 if (ecr & CESA_TDMA_ECR_DOUBLE_HIT) { 1335 device_printf(sc->sc_dev, "TDMA Double Hit error detected!\n"); 1336 sc->sc_error = EIO; 1337 } 1338 1339 if (ecr & CESA_TDMA_ECR_BOTH_HIT) { 1340 device_printf(sc->sc_dev, "TDMA Both Hit error detected!\n"); 1341 sc->sc_error = EIO; 1342 } 1343 1344 if (ecr & CESA_TDMA_ECR_DATA_ERROR) { 1345 device_printf(sc->sc_dev, "TDMA Data error detected!\n"); 1346 sc->sc_error = EIO; 1347 } 1348 1349 /* Check for CESA errors */ 1350 if (icr & sc->sc_tperr) { 1351 device_printf(sc->sc_dev, "CESA SRAM Parity error detected!\n"); 1352 sc->sc_error = EIO; 1353 } 1354 1355 /* If there is nothing more to do, return */ 1356 if ((icr & CESA_ICR_ACCTDMA) == 0) 1357 return; 1358 1359 /* Get all finished requests */ 1360 CESA_LOCK(sc, requests); 1361 STAILQ_INIT(&requests); 1362 STAILQ_CONCAT(&requests, &sc->sc_queued_requests); 1363 STAILQ_INIT(&sc->sc_queued_requests); 1364 CESA_UNLOCK(sc, requests); 1365 1366 /* Execute all ready requests */ 1367 cesa_execute(sc); 1368 1369 /* Process completed requests */ 1370 cesa_sync_dma_mem(&sc->sc_requests_cdm, BUS_DMASYNC_POSTREAD | 1371 BUS_DMASYNC_POSTWRITE); 1372 1373 STAILQ_FOREACH_SAFE(cr, &requests, cr_stq, tmp) { 1374 bus_dmamap_sync(sc->sc_data_dtag, cr->cr_dmap, 1375 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1376 1377 cr->cr_crp->crp_etype = sc->sc_error; 1378 if (cr->cr_mac) 1379 crypto_copyback(cr->cr_crp->crp_flags, 1380 cr->cr_crp->crp_buf, cr->cr_mac->crd_inject, 1381 cr->cr_cs->cs_hlen, cr->cr_csd->csd_hash); 1382 1383 crypto_done(cr->cr_crp); 1384 cesa_free_request(sc, cr); 1385 } 1386 1387 cesa_sync_dma_mem(&sc->sc_requests_cdm, BUS_DMASYNC_PREREAD | 1388 BUS_DMASYNC_PREWRITE); 1389 1390 sc->sc_error = 0; 1391 1392 /* Unblock driver if it ran out of resources */ 1393 CESA_LOCK(sc, sc); 1394 blocked = sc->sc_blocked; 1395 sc->sc_blocked = 0; 1396 CESA_UNLOCK(sc, sc); 1397 1398 if (blocked) 1399 crypto_unblock(sc->sc_cid, blocked); 1400} 1401 1402static int 1403cesa_newsession(device_t dev, uint32_t *sidp, struct cryptoini *cri) 1404{ 1405 struct cesa_session *cs; 1406 struct cesa_softc *sc; 1407 struct cryptoini *enc; 1408 struct cryptoini *mac; 1409 int error; 1410 1411 sc = device_get_softc(dev); 1412 enc = NULL; 1413 mac = NULL; 1414 error = 0; 1415 1416 /* Check and parse input */ 1417 if (cesa_is_hash(cri->cri_alg)) 1418 mac = cri; 1419 else 1420 enc = cri; 1421 1422 cri = cri->cri_next; 1423 1424 if (cri) { 1425 if (!enc && !cesa_is_hash(cri->cri_alg)) 1426 enc = cri; 1427 1428 if (!mac && cesa_is_hash(cri->cri_alg)) 1429 mac = cri; 1430 1431 if (cri->cri_next || !(enc && mac)) 1432 return (EINVAL); 1433 } 1434 1435 if ((enc && (enc->cri_klen / 8) > CESA_MAX_KEY_LEN) || 1436 (mac && (mac->cri_klen / 8) > CESA_MAX_MKEY_LEN)) 1437 return (E2BIG); 1438 1439 /* Allocate session */ 1440 cs = cesa_alloc_session(sc); 1441 if (!cs) 1442 return (ENOMEM); 1443 1444 /* Prepare CESA configuration */ 1445 cs->cs_config = 0; 1446 cs->cs_ivlen = 1; 1447 cs->cs_mblen = 1; 1448 1449 if (enc) { 1450 switch (enc->cri_alg) { 1451 case CRYPTO_AES_CBC: 1452 cs->cs_config |= CESA_CSHD_AES | CESA_CSHD_CBC; 1453 cs->cs_ivlen = AES_BLOCK_LEN; 1454 break; 1455 case CRYPTO_DES_CBC: 1456 cs->cs_config |= CESA_CSHD_DES | CESA_CSHD_CBC; 1457 cs->cs_ivlen = DES_BLOCK_LEN; 1458 break; 1459 case CRYPTO_3DES_CBC: 1460 cs->cs_config |= CESA_CSHD_3DES | CESA_CSHD_3DES_EDE | 1461 CESA_CSHD_CBC; 1462 cs->cs_ivlen = DES3_BLOCK_LEN; 1463 break; 1464 default: 1465 error = EINVAL; 1466 break; 1467 } 1468 } 1469 1470 if (!error && mac) { 1471 switch (mac->cri_alg) { 1472 case CRYPTO_MD5: 1473 cs->cs_mblen = 1; 1474 cs->cs_hlen = (mac->cri_mlen == 0) ? MD5_HASH_LEN : 1475 mac->cri_mlen; 1476 cs->cs_config |= CESA_CSHD_MD5; 1477 break; 1478 case CRYPTO_MD5_HMAC: 1479 cs->cs_mblen = MD5_HMAC_BLOCK_LEN; 1480 cs->cs_hlen = (mac->cri_mlen == 0) ? MD5_HASH_LEN : 1481 mac->cri_mlen; 1482 cs->cs_config |= CESA_CSHD_MD5_HMAC; 1483 if (cs->cs_hlen == CESA_HMAC_TRUNC_LEN) 1484 cs->cs_config |= CESA_CSHD_96_BIT_HMAC; 1485 break; 1486 case CRYPTO_SHA1: 1487 cs->cs_mblen = 1; 1488 cs->cs_hlen = (mac->cri_mlen == 0) ? SHA1_HASH_LEN : 1489 mac->cri_mlen; 1490 cs->cs_config |= CESA_CSHD_SHA1; 1491 break; 1492 case CRYPTO_SHA1_HMAC: 1493 cs->cs_mblen = SHA1_HMAC_BLOCK_LEN; 1494 cs->cs_hlen = (mac->cri_mlen == 0) ? SHA1_HASH_LEN : 1495 mac->cri_mlen; 1496 cs->cs_config |= CESA_CSHD_SHA1_HMAC; 1497 if (cs->cs_hlen == CESA_HMAC_TRUNC_LEN) 1498 cs->cs_config |= CESA_CSHD_96_BIT_HMAC; 1499 break; 1500 case CRYPTO_SHA2_256_HMAC: 1501 cs->cs_mblen = SHA2_256_HMAC_BLOCK_LEN; 1502 cs->cs_hlen = (mac->cri_mlen == 0) ? SHA2_256_HASH_LEN : 1503 mac->cri_mlen; 1504 cs->cs_config |= CESA_CSHD_SHA2_256_HMAC; 1505 break; 1506 default: 1507 error = EINVAL; 1508 break; 1509 } 1510 } 1511 1512 /* Save cipher key */ 1513 if (!error && enc && enc->cri_key) { 1514 cs->cs_klen = enc->cri_klen / 8; 1515 memcpy(cs->cs_key, enc->cri_key, cs->cs_klen); 1516 if (enc->cri_alg == CRYPTO_AES_CBC) 1517 error = cesa_prep_aes_key(cs); 1518 } 1519 1520 /* Save digest key */ 1521 if (!error && mac && mac->cri_key) 1522 error = cesa_set_mkey(cs, mac->cri_alg, mac->cri_key, 1523 mac->cri_klen / 8); 1524 1525 if (error) { 1526 cesa_free_session(sc, cs); 1527 return (EINVAL); 1528 } 1529 1530 *sidp = cs->cs_sid; 1531 1532 return (0); 1533} 1534 1535static int 1536cesa_freesession(device_t dev, uint64_t tid) 1537{ 1538 struct cesa_session *cs; 1539 struct cesa_softc *sc; 1540 1541 sc = device_get_softc(dev); 1542 cs = cesa_get_session(sc, CRYPTO_SESID2LID(tid)); 1543 if (!cs) 1544 return (EINVAL); 1545 1546 /* Free session */ 1547 cesa_free_session(sc, cs); 1548 1549 return (0); 1550} 1551 1552static int 1553cesa_process(device_t dev, struct cryptop *crp, int hint) 1554{ 1555 struct cesa_request *cr; 1556 struct cesa_session *cs; 1557 struct cryptodesc *crd; 1558 struct cryptodesc *enc; 1559 struct cryptodesc *mac; 1560 struct cesa_softc *sc; 1561 int error; 1562 1563 sc = device_get_softc(dev); 1564 crd = crp->crp_desc; 1565 enc = NULL; 1566 mac = NULL; 1567 error = 0; 1568 1569 /* Check session ID */ 1570 cs = cesa_get_session(sc, CRYPTO_SESID2LID(crp->crp_sid)); 1571 if (!cs) { 1572 crp->crp_etype = EINVAL; 1573 crypto_done(crp); 1574 return (0); 1575 } 1576 1577 /* Check and parse input */ 1578 if (crp->crp_ilen > CESA_MAX_REQUEST_SIZE) { 1579 crp->crp_etype = E2BIG; 1580 crypto_done(crp); 1581 return (0); 1582 } 1583 1584 if (cesa_is_hash(crd->crd_alg)) 1585 mac = crd; 1586 else 1587 enc = crd; 1588 1589 crd = crd->crd_next; 1590 1591 if (crd) { 1592 if (!enc && !cesa_is_hash(crd->crd_alg)) 1593 enc = crd; 1594 1595 if (!mac && cesa_is_hash(crd->crd_alg)) 1596 mac = crd; 1597 1598 if (crd->crd_next || !(enc && mac)) { 1599 crp->crp_etype = EINVAL; 1600 crypto_done(crp); 1601 return (0); 1602 } 1603 } 1604 1605 /* 1606 * Get request descriptor. Block driver if there is no free 1607 * descriptors in pool. 1608 */ 1609 cr = cesa_alloc_request(sc); 1610 if (!cr) { 1611 CESA_LOCK(sc, sc); 1612 sc->sc_blocked = CRYPTO_SYMQ; 1613 CESA_UNLOCK(sc, sc); 1614 return (ERESTART); 1615 } 1616 1617 /* Prepare request */ 1618 cr->cr_crp = crp; 1619 cr->cr_enc = enc; 1620 cr->cr_mac = mac; 1621 cr->cr_cs = cs; 1622 1623 CESA_LOCK(sc, sessions); 1624 cesa_sync_desc(sc, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1625 1626 if (enc && enc->crd_flags & CRD_F_ENCRYPT) { 1627 if (enc->crd_flags & CRD_F_IV_EXPLICIT) 1628 memcpy(cr->cr_csd->csd_iv, enc->crd_iv, cs->cs_ivlen); 1629 else 1630 arc4rand(cr->cr_csd->csd_iv, cs->cs_ivlen, 0); 1631 1632 if ((enc->crd_flags & CRD_F_IV_PRESENT) == 0) 1633 crypto_copyback(crp->crp_flags, crp->crp_buf, 1634 enc->crd_inject, cs->cs_ivlen, cr->cr_csd->csd_iv); 1635 } else if (enc) { 1636 if (enc->crd_flags & CRD_F_IV_EXPLICIT) 1637 memcpy(cr->cr_csd->csd_iv, enc->crd_iv, cs->cs_ivlen); 1638 else 1639 crypto_copydata(crp->crp_flags, crp->crp_buf, 1640 enc->crd_inject, cs->cs_ivlen, cr->cr_csd->csd_iv); 1641 } 1642 1643 if (enc && enc->crd_flags & CRD_F_KEY_EXPLICIT) { 1644 if ((enc->crd_klen / 8) <= CESA_MAX_KEY_LEN) { 1645 cs->cs_klen = enc->crd_klen / 8; 1646 memcpy(cs->cs_key, enc->crd_key, cs->cs_klen); 1647 if (enc->crd_alg == CRYPTO_AES_CBC) 1648 error = cesa_prep_aes_key(cs); 1649 } else 1650 error = E2BIG; 1651 } 1652 1653 if (!error && mac && mac->crd_flags & CRD_F_KEY_EXPLICIT) { 1654 if ((mac->crd_klen / 8) <= CESA_MAX_MKEY_LEN) 1655 error = cesa_set_mkey(cs, mac->crd_alg, mac->crd_key, 1656 mac->crd_klen / 8); 1657 else 1658 error = E2BIG; 1659 } 1660 1661 /* Convert request to chain of TDMA and SA descriptors */ 1662 if (!error) 1663 error = cesa_create_chain(sc, cr); 1664 1665 cesa_sync_desc(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1666 CESA_UNLOCK(sc, sessions); 1667 1668 if (error) { 1669 cesa_free_request(sc, cr); 1670 crp->crp_etype = error; 1671 crypto_done(crp); 1672 return (0); 1673 } 1674 1675 bus_dmamap_sync(sc->sc_data_dtag, cr->cr_dmap, BUS_DMASYNC_PREREAD | 1676 BUS_DMASYNC_PREWRITE); 1677 1678 /* Enqueue request to execution */ 1679 cesa_enqueue_request(sc, cr); 1680 1681 /* Start execution, if we have no more requests in queue */ 1682 if ((hint & CRYPTO_HINT_MORE) == 0) 1683 cesa_execute(sc); 1684 1685 return (0); 1686} 1687 1688/* 1689 * Set CESA TDMA decode windows. 1690 */ 1691static int 1692decode_win_cesa_setup(struct cesa_softc *sc) 1693{ 1694 struct mem_region availmem_regions[FDT_MEM_REGIONS]; 1695 int availmem_regions_sz; 1696 uint32_t br, cr, i; 1697 1698 /* Grab physical memory regions information from DTS */ 1699 if (fdt_get_mem_regions(availmem_regions, &availmem_regions_sz, 1700 NULL) != 0) 1701 return (ENXIO); 1702 1703 if (availmem_regions_sz > MV_WIN_CESA_MAX) { 1704 device_printf(sc->sc_dev, "Too much memory regions, cannot " 1705 " set CESA windows to cover whole DRAM \n"); 1706 return (ENXIO); 1707 } 1708 1709 /* Disable and clear all CESA windows */ 1710 for (i = 0; i < MV_WIN_CESA_MAX; i++) { 1711 CESA_TDMA_WRITE(sc, MV_WIN_CESA_BASE(i), 0); 1712 CESA_TDMA_WRITE(sc, MV_WIN_CESA_CTRL(i), 0); 1713 } 1714 1715 /* Fill CESA TDMA decoding windows with information acquired from DTS */ 1716 for (i = 0; i < availmem_regions_sz; i++) { 1717 br = availmem_regions[i].mr_start; 1718 cr = availmem_regions[i].mr_size; 1719 1720 /* Don't add entries with size lower than 64KB */ 1721 if (cr & 0xffff0000) { 1722 cr = (((cr - 1) & 0xffff0000) | 1723 (MV_WIN_DDR_ATTR(i) << MV_WIN_CPU_ATTR_SHIFT) | 1724 (MV_WIN_DDR_TARGET << MV_WIN_CPU_TARGET_SHIFT) | 1725 MV_WIN_CPU_ENABLE_BIT); 1726 CESA_TDMA_WRITE(sc, MV_WIN_CESA_BASE(i), br); 1727 CESA_TDMA_WRITE(sc, MV_WIN_CESA_CTRL(i), cr); 1728 } 1729 } 1730 1731 return (0); 1732} 1733 1734