cesa.c revision 296257
1227730Sraj/*- 2227730Sraj * Copyright (C) 2009-2011 Semihalf. 3227730Sraj * All rights reserved. 4227730Sraj * 5227730Sraj * Redistribution and use in source and binary forms, with or without 6227730Sraj * modification, are permitted provided that the following conditions 7227730Sraj * are met: 8227730Sraj * 1. Redistributions of source code must retain the above copyright 9227730Sraj * notice, this list of conditions and the following disclaimer. 10227730Sraj * 2. Redistributions in binary form must reproduce the above copyright 11227730Sraj * notice, this list of conditions and the following disclaimer in the 12227730Sraj * documentation and/or other materials provided with the distribution. 13227730Sraj * 14227730Sraj * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15227730Sraj * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16227730Sraj * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17227730Sraj * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18227730Sraj * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19227730Sraj * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20227730Sraj * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21227730Sraj * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22227730Sraj * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23227730Sraj * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24227730Sraj * SUCH DAMAGE. 25227730Sraj */ 26227730Sraj 27227730Sraj/* 28227730Sraj * CESA SRAM Memory Map: 29227730Sraj * 30227730Sraj * +------------------------+ <= sc->sc_sram_base + CESA_SRAM_SIZE 31227730Sraj * | | 32227730Sraj * | DATA | 33227730Sraj * | | 34227730Sraj * +------------------------+ <= sc->sc_sram_base + CESA_DATA(0) 35227730Sraj * | struct cesa_sa_data | 36227730Sraj * +------------------------+ 37227730Sraj * | struct cesa_sa_hdesc | 38227730Sraj * +------------------------+ <= sc->sc_sram_base 39227730Sraj */ 40227730Sraj 41227730Sraj#include <sys/cdefs.h> 42227730Sraj__FBSDID("$FreeBSD: head/sys/dev/cesa/cesa.c 296257 2016-03-01 09:45:27Z andrew $"); 43227730Sraj 44227730Sraj#include <sys/param.h> 45227730Sraj#include <sys/systm.h> 46227730Sraj#include <sys/bus.h> 47227730Sraj#include <sys/endian.h> 48227730Sraj#include <sys/kernel.h> 49227730Sraj#include <sys/lock.h> 50227730Sraj#include <sys/mbuf.h> 51227730Sraj#include <sys/module.h> 52227730Sraj#include <sys/mutex.h> 53227730Sraj#include <sys/rman.h> 54227730Sraj 55227730Sraj#include <machine/bus.h> 56227730Sraj#include <machine/intr.h> 57227730Sraj#include <machine/resource.h> 58227730Sraj 59227730Sraj#include <dev/fdt/fdt_common.h> 60227730Sraj#include <dev/ofw/ofw_bus.h> 61227730Sraj#include <dev/ofw/ofw_bus_subr.h> 62227730Sraj 63227730Sraj#include <sys/md5.h> 64227730Sraj#include <crypto/sha1.h> 65227730Sraj#include <crypto/rijndael/rijndael.h> 66227730Sraj#include <opencrypto/cryptodev.h> 67227730Sraj#include "cryptodev_if.h" 68227730Sraj 69227730Sraj#include <arm/mv/mvreg.h> 70227730Sraj#include <arm/mv/mvwin.h> 71227730Sraj#include <arm/mv/mvvar.h> 72227730Sraj#include "cesa.h" 73227730Sraj 74227730Srajstatic int cesa_probe(device_t); 75227730Srajstatic int cesa_attach(device_t); 76227730Srajstatic int cesa_detach(device_t); 77227730Srajstatic void cesa_intr(void *); 78227730Srajstatic int cesa_newsession(device_t, u_int32_t *, struct cryptoini *); 79227730Srajstatic int cesa_freesession(device_t, u_int64_t); 80227730Srajstatic int cesa_process(device_t, struct cryptop *, int); 81250291Sgberstatic int decode_win_cesa_setup(struct cesa_softc *sc); 82227730Sraj 83227730Srajstatic struct resource_spec cesa_res_spec[] = { 84227730Sraj { SYS_RES_MEMORY, 0, RF_ACTIVE }, 85227730Sraj { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 86227730Sraj { -1, 0 } 87227730Sraj}; 88227730Sraj 89227730Srajstatic device_method_t cesa_methods[] = { 90227730Sraj /* Device interface */ 91227730Sraj DEVMETHOD(device_probe, cesa_probe), 92227730Sraj DEVMETHOD(device_attach, cesa_attach), 93227730Sraj DEVMETHOD(device_detach, cesa_detach), 94227730Sraj 95227730Sraj /* Crypto device methods */ 96227730Sraj DEVMETHOD(cryptodev_newsession, cesa_newsession), 97227730Sraj DEVMETHOD(cryptodev_freesession,cesa_freesession), 98227730Sraj DEVMETHOD(cryptodev_process, cesa_process), 99227730Sraj 100227843Smarius DEVMETHOD_END 101227730Sraj}; 102227730Sraj 103227730Srajstatic driver_t cesa_driver = { 104227730Sraj "cesa", 105227730Sraj cesa_methods, 106227730Sraj sizeof (struct cesa_softc) 107227730Sraj}; 108227730Srajstatic devclass_t cesa_devclass; 109227730Sraj 110227730SrajDRIVER_MODULE(cesa, simplebus, cesa_driver, cesa_devclass, 0, 0); 111227730SrajMODULE_DEPEND(cesa, crypto, 1, 1, 1); 112227730Sraj 113227730Srajstatic void 114227730Srajcesa_dump_cshd(struct cesa_softc *sc, struct cesa_sa_hdesc *cshd) 115227730Sraj{ 116227730Sraj#ifdef DEBUG 117227730Sraj device_t dev; 118227730Sraj 119227730Sraj dev = sc->sc_dev; 120227730Sraj device_printf(dev, "CESA SA Hardware Descriptor:\n"); 121227730Sraj device_printf(dev, "\t\tconfig: 0x%08X\n", cshd->cshd_config); 122227730Sraj device_printf(dev, "\t\te_src: 0x%08X\n", cshd->cshd_enc_src); 123227730Sraj device_printf(dev, "\t\te_dst: 0x%08X\n", cshd->cshd_enc_dst); 124227730Sraj device_printf(dev, "\t\te_dlen: 0x%08X\n", cshd->cshd_enc_dlen); 125227730Sraj device_printf(dev, "\t\te_key: 0x%08X\n", cshd->cshd_enc_key); 126227730Sraj device_printf(dev, "\t\te_iv_1: 0x%08X\n", cshd->cshd_enc_iv); 127227730Sraj device_printf(dev, "\t\te_iv_2: 0x%08X\n", cshd->cshd_enc_iv_buf); 128227730Sraj device_printf(dev, "\t\tm_src: 0x%08X\n", cshd->cshd_mac_src); 129227730Sraj device_printf(dev, "\t\tm_dst: 0x%08X\n", cshd->cshd_mac_dst); 130227730Sraj device_printf(dev, "\t\tm_dlen: 0x%08X\n", cshd->cshd_mac_dlen); 131227730Sraj device_printf(dev, "\t\tm_tlen: 0x%08X\n", cshd->cshd_mac_total_dlen); 132227730Sraj device_printf(dev, "\t\tm_iv_i: 0x%08X\n", cshd->cshd_mac_iv_in); 133227730Sraj device_printf(dev, "\t\tm_iv_o: 0x%08X\n", cshd->cshd_mac_iv_out); 134227730Sraj#endif 135227730Sraj} 136227730Sraj 137227730Srajstatic void 138227730Srajcesa_alloc_dma_mem_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 139227730Sraj{ 140227730Sraj struct cesa_dma_mem *cdm; 141227730Sraj 142227730Sraj if (error) 143227730Sraj return; 144227730Sraj 145227730Sraj KASSERT(nseg == 1, ("Got wrong number of DMA segments, should be 1.")); 146227730Sraj cdm = arg; 147227730Sraj cdm->cdm_paddr = segs->ds_addr; 148227730Sraj} 149227730Sraj 150227730Srajstatic int 151227730Srajcesa_alloc_dma_mem(struct cesa_softc *sc, struct cesa_dma_mem *cdm, 152227730Sraj bus_size_t size) 153227730Sraj{ 154227730Sraj int error; 155227730Sraj 156227730Sraj KASSERT(cdm->cdm_vaddr == NULL, 157227730Sraj ("%s(): DMA memory descriptor in use.", __func__)); 158227730Sraj 159232883Sscottl error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), /* parent */ 160227730Sraj PAGE_SIZE, 0, /* alignment, boundary */ 161227730Sraj BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 162227730Sraj BUS_SPACE_MAXADDR, /* highaddr */ 163227730Sraj NULL, NULL, /* filtfunc, filtfuncarg */ 164227730Sraj size, 1, /* maxsize, nsegments */ 165227730Sraj size, 0, /* maxsegsz, flags */ 166227730Sraj NULL, NULL, /* lockfunc, lockfuncarg */ 167227730Sraj &cdm->cdm_tag); /* dmat */ 168227730Sraj if (error) { 169227730Sraj device_printf(sc->sc_dev, "failed to allocate busdma tag, error" 170227730Sraj " %i!\n", error); 171227730Sraj 172227730Sraj goto err1; 173227730Sraj } 174227730Sraj 175227730Sraj error = bus_dmamem_alloc(cdm->cdm_tag, &cdm->cdm_vaddr, 176227730Sraj BUS_DMA_NOWAIT | BUS_DMA_ZERO, &cdm->cdm_map); 177227730Sraj if (error) { 178227730Sraj device_printf(sc->sc_dev, "failed to allocate DMA safe" 179227730Sraj " memory, error %i!\n", error); 180227730Sraj 181227730Sraj goto err2; 182227730Sraj } 183227730Sraj 184227730Sraj error = bus_dmamap_load(cdm->cdm_tag, cdm->cdm_map, cdm->cdm_vaddr, 185227730Sraj size, cesa_alloc_dma_mem_cb, cdm, BUS_DMA_NOWAIT); 186227730Sraj if (error) { 187227730Sraj device_printf(sc->sc_dev, "cannot get address of the DMA" 188227730Sraj " memory, error %i\n", error); 189227730Sraj 190227730Sraj goto err3; 191227730Sraj } 192227730Sraj 193227730Sraj return (0); 194227730Srajerr3: 195227730Sraj bus_dmamem_free(cdm->cdm_tag, cdm->cdm_vaddr, cdm->cdm_map); 196227730Srajerr2: 197227730Sraj bus_dma_tag_destroy(cdm->cdm_tag); 198227730Srajerr1: 199227730Sraj cdm->cdm_vaddr = NULL; 200227730Sraj return (error); 201227730Sraj} 202227730Sraj 203227730Srajstatic void 204227730Srajcesa_free_dma_mem(struct cesa_dma_mem *cdm) 205227730Sraj{ 206227730Sraj 207227730Sraj bus_dmamap_unload(cdm->cdm_tag, cdm->cdm_map); 208227730Sraj bus_dmamem_free(cdm->cdm_tag, cdm->cdm_vaddr, cdm->cdm_map); 209227730Sraj bus_dma_tag_destroy(cdm->cdm_tag); 210227730Sraj cdm->cdm_vaddr = NULL; 211227730Sraj} 212227730Sraj 213227730Srajstatic void 214227730Srajcesa_sync_dma_mem(struct cesa_dma_mem *cdm, bus_dmasync_op_t op) 215227730Sraj{ 216227730Sraj 217227730Sraj /* Sync only if dma memory is valid */ 218227730Sraj if (cdm->cdm_vaddr != NULL) 219227730Sraj bus_dmamap_sync(cdm->cdm_tag, cdm->cdm_map, op); 220227730Sraj} 221227730Sraj 222227730Srajstatic void 223227730Srajcesa_sync_desc(struct cesa_softc *sc, bus_dmasync_op_t op) 224227730Sraj{ 225227730Sraj 226227730Sraj cesa_sync_dma_mem(&sc->sc_tdesc_cdm, op); 227227730Sraj cesa_sync_dma_mem(&sc->sc_sdesc_cdm, op); 228227730Sraj cesa_sync_dma_mem(&sc->sc_requests_cdm, op); 229227730Sraj} 230227730Sraj 231227730Srajstatic struct cesa_session * 232227730Srajcesa_alloc_session(struct cesa_softc *sc) 233227730Sraj{ 234227730Sraj struct cesa_session *cs; 235227730Sraj 236227730Sraj CESA_GENERIC_ALLOC_LOCKED(sc, cs, sessions); 237227730Sraj 238227730Sraj return (cs); 239227730Sraj} 240227730Sraj 241227730Srajstatic struct cesa_session * 242227730Srajcesa_get_session(struct cesa_softc *sc, uint32_t sid) 243227730Sraj{ 244227730Sraj 245227730Sraj if (sid >= CESA_SESSIONS) 246227730Sraj return (NULL); 247227730Sraj 248227730Sraj return (&sc->sc_sessions[sid]); 249227730Sraj} 250227730Sraj 251227730Srajstatic void 252227730Srajcesa_free_session(struct cesa_softc *sc, struct cesa_session *cs) 253227730Sraj{ 254227730Sraj 255227730Sraj CESA_GENERIC_FREE_LOCKED(sc, cs, sessions); 256227730Sraj} 257227730Sraj 258227730Srajstatic struct cesa_request * 259227730Srajcesa_alloc_request(struct cesa_softc *sc) 260227730Sraj{ 261227730Sraj struct cesa_request *cr; 262227730Sraj 263227730Sraj CESA_GENERIC_ALLOC_LOCKED(sc, cr, requests); 264227730Sraj if (!cr) 265227730Sraj return (NULL); 266227730Sraj 267227730Sraj STAILQ_INIT(&cr->cr_tdesc); 268227730Sraj STAILQ_INIT(&cr->cr_sdesc); 269227730Sraj 270227730Sraj return (cr); 271227730Sraj} 272227730Sraj 273227730Srajstatic void 274227730Srajcesa_free_request(struct cesa_softc *sc, struct cesa_request *cr) 275227730Sraj{ 276227730Sraj 277227730Sraj /* Free TDMA descriptors assigned to this request */ 278227730Sraj CESA_LOCK(sc, tdesc); 279227730Sraj STAILQ_CONCAT(&sc->sc_free_tdesc, &cr->cr_tdesc); 280227730Sraj CESA_UNLOCK(sc, tdesc); 281227730Sraj 282227730Sraj /* Free SA descriptors assigned to this request */ 283227730Sraj CESA_LOCK(sc, sdesc); 284227730Sraj STAILQ_CONCAT(&sc->sc_free_sdesc, &cr->cr_sdesc); 285227730Sraj CESA_UNLOCK(sc, sdesc); 286227730Sraj 287227730Sraj /* Unload DMA memory asociated with request */ 288227730Sraj if (cr->cr_dmap_loaded) { 289227730Sraj bus_dmamap_unload(sc->sc_data_dtag, cr->cr_dmap); 290227730Sraj cr->cr_dmap_loaded = 0; 291227730Sraj } 292227730Sraj 293227730Sraj CESA_GENERIC_FREE_LOCKED(sc, cr, requests); 294227730Sraj} 295227730Sraj 296227730Srajstatic void 297227730Srajcesa_enqueue_request(struct cesa_softc *sc, struct cesa_request *cr) 298227730Sraj{ 299227730Sraj 300227730Sraj CESA_LOCK(sc, requests); 301227730Sraj STAILQ_INSERT_TAIL(&sc->sc_ready_requests, cr, cr_stq); 302227730Sraj CESA_UNLOCK(sc, requests); 303227730Sraj} 304227730Sraj 305227730Srajstatic struct cesa_tdma_desc * 306227730Srajcesa_alloc_tdesc(struct cesa_softc *sc) 307227730Sraj{ 308227730Sraj struct cesa_tdma_desc *ctd; 309227730Sraj 310227730Sraj CESA_GENERIC_ALLOC_LOCKED(sc, ctd, tdesc); 311227730Sraj 312227730Sraj if (!ctd) 313227730Sraj device_printf(sc->sc_dev, "TDMA descriptors pool exhaused. " 314227730Sraj "Consider increasing CESA_TDMA_DESCRIPTORS.\n"); 315227730Sraj 316227730Sraj return (ctd); 317227730Sraj} 318227730Sraj 319227730Srajstatic struct cesa_sa_desc * 320227730Srajcesa_alloc_sdesc(struct cesa_softc *sc, struct cesa_request *cr) 321227730Sraj{ 322227730Sraj struct cesa_sa_desc *csd; 323227730Sraj 324227730Sraj CESA_GENERIC_ALLOC_LOCKED(sc, csd, sdesc); 325227730Sraj if (!csd) { 326227730Sraj device_printf(sc->sc_dev, "SA descriptors pool exhaused. " 327227730Sraj "Consider increasing CESA_SA_DESCRIPTORS.\n"); 328227730Sraj return (NULL); 329227730Sraj } 330227730Sraj 331227730Sraj STAILQ_INSERT_TAIL(&cr->cr_sdesc, csd, csd_stq); 332227730Sraj 333227730Sraj /* Fill-in SA descriptor with default values */ 334227730Sraj csd->csd_cshd->cshd_enc_key = CESA_SA_DATA(csd_key); 335227730Sraj csd->csd_cshd->cshd_enc_iv = CESA_SA_DATA(csd_iv); 336227730Sraj csd->csd_cshd->cshd_enc_iv_buf = CESA_SA_DATA(csd_iv); 337227730Sraj csd->csd_cshd->cshd_enc_src = 0; 338227730Sraj csd->csd_cshd->cshd_enc_dst = 0; 339227730Sraj csd->csd_cshd->cshd_enc_dlen = 0; 340227730Sraj csd->csd_cshd->cshd_mac_dst = CESA_SA_DATA(csd_hash); 341227730Sraj csd->csd_cshd->cshd_mac_iv_in = CESA_SA_DATA(csd_hiv_in); 342227730Sraj csd->csd_cshd->cshd_mac_iv_out = CESA_SA_DATA(csd_hiv_out); 343227730Sraj csd->csd_cshd->cshd_mac_src = 0; 344227730Sraj csd->csd_cshd->cshd_mac_dlen = 0; 345227730Sraj 346227730Sraj return (csd); 347227730Sraj} 348227730Sraj 349227730Srajstatic struct cesa_tdma_desc * 350227730Srajcesa_tdma_copy(struct cesa_softc *sc, bus_addr_t dst, bus_addr_t src, 351227730Sraj bus_size_t size) 352227730Sraj{ 353227730Sraj struct cesa_tdma_desc *ctd; 354227730Sraj 355227730Sraj ctd = cesa_alloc_tdesc(sc); 356227730Sraj if (!ctd) 357227730Sraj return (NULL); 358227730Sraj 359227730Sraj ctd->ctd_cthd->cthd_dst = dst; 360227730Sraj ctd->ctd_cthd->cthd_src = src; 361227730Sraj ctd->ctd_cthd->cthd_byte_count = size; 362227730Sraj 363227730Sraj /* Handle special control packet */ 364227730Sraj if (size != 0) 365227730Sraj ctd->ctd_cthd->cthd_flags = CESA_CTHD_OWNED; 366227730Sraj else 367227730Sraj ctd->ctd_cthd->cthd_flags = 0; 368227730Sraj 369227730Sraj return (ctd); 370227730Sraj} 371227730Sraj 372227730Srajstatic struct cesa_tdma_desc * 373227730Srajcesa_tdma_copyin_sa_data(struct cesa_softc *sc, struct cesa_request *cr) 374227730Sraj{ 375227730Sraj 376227730Sraj return (cesa_tdma_copy(sc, sc->sc_sram_base + 377227730Sraj sizeof(struct cesa_sa_hdesc), cr->cr_csd_paddr, 378227730Sraj sizeof(struct cesa_sa_data))); 379227730Sraj} 380227730Sraj 381227730Srajstatic struct cesa_tdma_desc * 382227730Srajcesa_tdma_copyout_sa_data(struct cesa_softc *sc, struct cesa_request *cr) 383227730Sraj{ 384227730Sraj 385227730Sraj return (cesa_tdma_copy(sc, cr->cr_csd_paddr, sc->sc_sram_base + 386227730Sraj sizeof(struct cesa_sa_hdesc), sizeof(struct cesa_sa_data))); 387227730Sraj} 388227730Sraj 389227730Srajstatic struct cesa_tdma_desc * 390227730Srajcesa_tdma_copy_sdesc(struct cesa_softc *sc, struct cesa_sa_desc *csd) 391227730Sraj{ 392227730Sraj 393227730Sraj return (cesa_tdma_copy(sc, sc->sc_sram_base, csd->csd_cshd_paddr, 394227730Sraj sizeof(struct cesa_sa_hdesc))); 395227730Sraj} 396227730Sraj 397227730Srajstatic void 398227730Srajcesa_append_tdesc(struct cesa_request *cr, struct cesa_tdma_desc *ctd) 399227730Sraj{ 400227730Sraj struct cesa_tdma_desc *ctd_prev; 401227730Sraj 402227730Sraj if (!STAILQ_EMPTY(&cr->cr_tdesc)) { 403227730Sraj ctd_prev = STAILQ_LAST(&cr->cr_tdesc, cesa_tdma_desc, ctd_stq); 404227730Sraj ctd_prev->ctd_cthd->cthd_next = ctd->ctd_cthd_paddr; 405227730Sraj } 406227730Sraj 407227730Sraj ctd->ctd_cthd->cthd_next = 0; 408227730Sraj STAILQ_INSERT_TAIL(&cr->cr_tdesc, ctd, ctd_stq); 409227730Sraj} 410227730Sraj 411227730Srajstatic int 412227730Srajcesa_append_packet(struct cesa_softc *sc, struct cesa_request *cr, 413227730Sraj struct cesa_packet *cp, struct cesa_sa_desc *csd) 414227730Sraj{ 415227730Sraj struct cesa_tdma_desc *ctd, *tmp; 416227730Sraj 417227730Sraj /* Copy SA descriptor for this packet */ 418227730Sraj ctd = cesa_tdma_copy_sdesc(sc, csd); 419227730Sraj if (!ctd) 420227730Sraj return (ENOMEM); 421227730Sraj 422227730Sraj cesa_append_tdesc(cr, ctd); 423227730Sraj 424227730Sraj /* Copy data to be processed */ 425227730Sraj STAILQ_FOREACH_SAFE(ctd, &cp->cp_copyin, ctd_stq, tmp) 426227730Sraj cesa_append_tdesc(cr, ctd); 427227730Sraj STAILQ_INIT(&cp->cp_copyin); 428227730Sraj 429227730Sraj /* Insert control descriptor */ 430227730Sraj ctd = cesa_tdma_copy(sc, 0, 0, 0); 431227730Sraj if (!ctd) 432227730Sraj return (ENOMEM); 433227730Sraj 434227730Sraj cesa_append_tdesc(cr, ctd); 435227730Sraj 436227730Sraj /* Copy back results */ 437227730Sraj STAILQ_FOREACH_SAFE(ctd, &cp->cp_copyout, ctd_stq, tmp) 438227730Sraj cesa_append_tdesc(cr, ctd); 439227730Sraj STAILQ_INIT(&cp->cp_copyout); 440227730Sraj 441227730Sraj return (0); 442227730Sraj} 443227730Sraj 444227730Srajstatic int 445227730Srajcesa_set_mkey(struct cesa_session *cs, int alg, const uint8_t *mkey, int mklen) 446227730Sraj{ 447227730Sraj uint8_t ipad[CESA_MAX_HMAC_BLOCK_LEN]; 448227730Sraj uint8_t opad[CESA_MAX_HMAC_BLOCK_LEN]; 449227730Sraj SHA1_CTX sha1ctx; 450227730Sraj MD5_CTX md5ctx; 451227730Sraj uint32_t *hout; 452227730Sraj uint32_t *hin; 453227730Sraj int i; 454227730Sraj 455227730Sraj memset(ipad, HMAC_IPAD_VAL, CESA_MAX_HMAC_BLOCK_LEN); 456227730Sraj memset(opad, HMAC_OPAD_VAL, CESA_MAX_HMAC_BLOCK_LEN); 457227730Sraj for (i = 0; i < mklen; i++) { 458227730Sraj ipad[i] ^= mkey[i]; 459227730Sraj opad[i] ^= mkey[i]; 460227730Sraj } 461227730Sraj 462227730Sraj hin = (uint32_t *)cs->cs_hiv_in; 463227730Sraj hout = (uint32_t *)cs->cs_hiv_out; 464227730Sraj 465227730Sraj switch (alg) { 466227730Sraj case CRYPTO_MD5_HMAC: 467227730Sraj MD5Init(&md5ctx); 468227730Sraj MD5Update(&md5ctx, ipad, MD5_HMAC_BLOCK_LEN); 469227730Sraj memcpy(hin, md5ctx.state, sizeof(md5ctx.state)); 470227730Sraj MD5Init(&md5ctx); 471227730Sraj MD5Update(&md5ctx, opad, MD5_HMAC_BLOCK_LEN); 472227730Sraj memcpy(hout, md5ctx.state, sizeof(md5ctx.state)); 473227730Sraj break; 474227730Sraj case CRYPTO_SHA1_HMAC: 475227730Sraj SHA1Init(&sha1ctx); 476227730Sraj SHA1Update(&sha1ctx, ipad, SHA1_HMAC_BLOCK_LEN); 477227730Sraj memcpy(hin, sha1ctx.h.b32, sizeof(sha1ctx.h.b32)); 478227730Sraj SHA1Init(&sha1ctx); 479227730Sraj SHA1Update(&sha1ctx, opad, SHA1_HMAC_BLOCK_LEN); 480227730Sraj memcpy(hout, sha1ctx.h.b32, sizeof(sha1ctx.h.b32)); 481227730Sraj break; 482227730Sraj default: 483227730Sraj return (EINVAL); 484227730Sraj } 485227730Sraj 486227730Sraj for (i = 0; i < CESA_MAX_HASH_LEN / sizeof(uint32_t); i++) { 487227730Sraj hin[i] = htobe32(hin[i]); 488227730Sraj hout[i] = htobe32(hout[i]); 489227730Sraj } 490227730Sraj 491227730Sraj return (0); 492227730Sraj} 493227730Sraj 494227730Srajstatic int 495227730Srajcesa_prep_aes_key(struct cesa_session *cs) 496227730Sraj{ 497227730Sraj uint32_t ek[4 * (RIJNDAEL_MAXNR + 1)]; 498227730Sraj uint32_t *dkey; 499227730Sraj int i; 500227730Sraj 501227730Sraj rijndaelKeySetupEnc(ek, cs->cs_key, cs->cs_klen * 8); 502227730Sraj 503227730Sraj cs->cs_config &= ~CESA_CSH_AES_KLEN_MASK; 504227730Sraj dkey = (uint32_t *)cs->cs_aes_dkey; 505227730Sraj 506227730Sraj switch (cs->cs_klen) { 507227730Sraj case 16: 508227730Sraj cs->cs_config |= CESA_CSH_AES_KLEN_128; 509227730Sraj for (i = 0; i < 4; i++) 510227730Sraj *dkey++ = htobe32(ek[4 * 10 + i]); 511227730Sraj break; 512227730Sraj case 24: 513227730Sraj cs->cs_config |= CESA_CSH_AES_KLEN_192; 514227730Sraj for (i = 0; i < 4; i++) 515227730Sraj *dkey++ = htobe32(ek[4 * 12 + i]); 516227730Sraj for (i = 0; i < 2; i++) 517227730Sraj *dkey++ = htobe32(ek[4 * 11 + 2 + i]); 518227730Sraj break; 519227730Sraj case 32: 520227730Sraj cs->cs_config |= CESA_CSH_AES_KLEN_256; 521227730Sraj for (i = 0; i < 4; i++) 522227730Sraj *dkey++ = htobe32(ek[4 * 14 + i]); 523227730Sraj for (i = 0; i < 4; i++) 524227730Sraj *dkey++ = htobe32(ek[4 * 13 + i]); 525227730Sraj break; 526227730Sraj default: 527227730Sraj return (EINVAL); 528227730Sraj } 529227730Sraj 530227730Sraj return (0); 531227730Sraj} 532227730Sraj 533227730Srajstatic int 534227730Srajcesa_is_hash(int alg) 535227730Sraj{ 536227730Sraj 537227730Sraj switch (alg) { 538227730Sraj case CRYPTO_MD5: 539227730Sraj case CRYPTO_MD5_HMAC: 540227730Sraj case CRYPTO_SHA1: 541227730Sraj case CRYPTO_SHA1_HMAC: 542227730Sraj return (1); 543227730Sraj default: 544227730Sraj return (0); 545227730Sraj } 546227730Sraj} 547227730Sraj 548227730Srajstatic void 549227730Srajcesa_start_packet(struct cesa_packet *cp, unsigned int size) 550227730Sraj{ 551227730Sraj 552227730Sraj cp->cp_size = size; 553227730Sraj cp->cp_offset = 0; 554227730Sraj STAILQ_INIT(&cp->cp_copyin); 555227730Sraj STAILQ_INIT(&cp->cp_copyout); 556227730Sraj} 557227730Sraj 558227730Srajstatic int 559227730Srajcesa_fill_packet(struct cesa_softc *sc, struct cesa_packet *cp, 560227730Sraj bus_dma_segment_t *seg) 561227730Sraj{ 562227730Sraj struct cesa_tdma_desc *ctd; 563227730Sraj unsigned int bsize; 564227730Sraj 565227730Sraj /* Calculate size of block copy */ 566227730Sraj bsize = MIN(seg->ds_len, cp->cp_size - cp->cp_offset); 567227730Sraj 568227730Sraj if (bsize > 0) { 569227730Sraj ctd = cesa_tdma_copy(sc, sc->sc_sram_base + 570227730Sraj CESA_DATA(cp->cp_offset), seg->ds_addr, bsize); 571227730Sraj if (!ctd) 572227730Sraj return (-ENOMEM); 573227730Sraj 574227730Sraj STAILQ_INSERT_TAIL(&cp->cp_copyin, ctd, ctd_stq); 575227730Sraj 576227730Sraj ctd = cesa_tdma_copy(sc, seg->ds_addr, sc->sc_sram_base + 577227730Sraj CESA_DATA(cp->cp_offset), bsize); 578227730Sraj if (!ctd) 579227730Sraj return (-ENOMEM); 580227730Sraj 581227730Sraj STAILQ_INSERT_TAIL(&cp->cp_copyout, ctd, ctd_stq); 582227730Sraj 583227730Sraj seg->ds_len -= bsize; 584227730Sraj seg->ds_addr += bsize; 585227730Sraj cp->cp_offset += bsize; 586227730Sraj } 587227730Sraj 588227730Sraj return (bsize); 589227730Sraj} 590227730Sraj 591227730Srajstatic void 592227730Srajcesa_create_chain_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 593227730Sraj{ 594227730Sraj unsigned int mpsize, fragmented; 595227730Sraj unsigned int mlen, mskip, tmlen; 596227730Sraj struct cesa_chain_info *cci; 597227730Sraj unsigned int elen, eskip; 598227730Sraj unsigned int skip, len; 599227730Sraj struct cesa_sa_desc *csd; 600227730Sraj struct cesa_request *cr; 601227730Sraj struct cesa_softc *sc; 602227730Sraj struct cesa_packet cp; 603227730Sraj bus_dma_segment_t seg; 604227730Sraj uint32_t config; 605227730Sraj int size; 606227730Sraj 607227730Sraj cci = arg; 608227730Sraj sc = cci->cci_sc; 609227730Sraj cr = cci->cci_cr; 610227730Sraj 611227730Sraj if (error) { 612227730Sraj cci->cci_error = error; 613227730Sraj return; 614227730Sraj } 615227730Sraj 616227730Sraj elen = cci->cci_enc ? cci->cci_enc->crd_len : 0; 617227730Sraj eskip = cci->cci_enc ? cci->cci_enc->crd_skip : 0; 618227730Sraj mlen = cci->cci_mac ? cci->cci_mac->crd_len : 0; 619227730Sraj mskip = cci->cci_mac ? cci->cci_mac->crd_skip : 0; 620227730Sraj 621227730Sraj if (elen && mlen && 622227730Sraj ((eskip > mskip && ((eskip - mskip) & (cr->cr_cs->cs_ivlen - 1))) || 623227730Sraj (mskip > eskip && ((mskip - eskip) & (cr->cr_cs->cs_mblen - 1))) || 624227730Sraj (eskip > (mskip + mlen)) || (mskip > (eskip + elen)))) { 625227730Sraj /* 626227730Sraj * Data alignment in the request does not meet CESA requiremnts 627227730Sraj * for combined encryption/decryption and hashing. We have to 628227730Sraj * split the request to separate operations and process them 629227730Sraj * one by one. 630227730Sraj */ 631227730Sraj config = cci->cci_config; 632227730Sraj if ((config & CESA_CSHD_OP_MASK) == CESA_CSHD_MAC_AND_ENC) { 633227730Sraj config &= ~CESA_CSHD_OP_MASK; 634227730Sraj 635227730Sraj cci->cci_config = config | CESA_CSHD_MAC; 636227730Sraj cci->cci_enc = NULL; 637227730Sraj cci->cci_mac = cr->cr_mac; 638227730Sraj cesa_create_chain_cb(cci, segs, nseg, cci->cci_error); 639227730Sraj 640227730Sraj cci->cci_config = config | CESA_CSHD_ENC; 641227730Sraj cci->cci_enc = cr->cr_enc; 642227730Sraj cci->cci_mac = NULL; 643227730Sraj cesa_create_chain_cb(cci, segs, nseg, cci->cci_error); 644227730Sraj } else { 645227730Sraj config &= ~CESA_CSHD_OP_MASK; 646227730Sraj 647227730Sraj cci->cci_config = config | CESA_CSHD_ENC; 648227730Sraj cci->cci_enc = cr->cr_enc; 649227730Sraj cci->cci_mac = NULL; 650227730Sraj cesa_create_chain_cb(cci, segs, nseg, cci->cci_error); 651227730Sraj 652227730Sraj cci->cci_config = config | CESA_CSHD_MAC; 653227730Sraj cci->cci_enc = NULL; 654227730Sraj cci->cci_mac = cr->cr_mac; 655227730Sraj cesa_create_chain_cb(cci, segs, nseg, cci->cci_error); 656227730Sraj } 657227730Sraj 658227730Sraj return; 659227730Sraj } 660227730Sraj 661227730Sraj tmlen = mlen; 662227730Sraj fragmented = 0; 663227730Sraj mpsize = CESA_MAX_PACKET_SIZE; 664227730Sraj mpsize &= ~((cr->cr_cs->cs_ivlen - 1) | (cr->cr_cs->cs_mblen - 1)); 665227730Sraj 666227730Sraj if (elen && mlen) { 667227730Sraj skip = MIN(eskip, mskip); 668227730Sraj len = MAX(elen + eskip, mlen + mskip) - skip; 669227730Sraj } else if (elen) { 670227730Sraj skip = eskip; 671227730Sraj len = elen; 672227730Sraj } else { 673227730Sraj skip = mskip; 674227730Sraj len = mlen; 675227730Sraj } 676227730Sraj 677227730Sraj /* Start first packet in chain */ 678227730Sraj cesa_start_packet(&cp, MIN(mpsize, len)); 679227730Sraj 680227730Sraj while (nseg-- && len > 0) { 681227730Sraj seg = *(segs++); 682227730Sraj 683227730Sraj /* 684227730Sraj * Skip data in buffer on which neither ENC nor MAC operation 685227730Sraj * is requested. 686227730Sraj */ 687227730Sraj if (skip > 0) { 688227730Sraj size = MIN(skip, seg.ds_len); 689227730Sraj skip -= size; 690227730Sraj 691227730Sraj seg.ds_addr += size; 692227730Sraj seg.ds_len -= size; 693227730Sraj 694227730Sraj if (eskip > 0) 695227730Sraj eskip -= size; 696227730Sraj 697227730Sraj if (mskip > 0) 698227730Sraj mskip -= size; 699227730Sraj 700227730Sraj if (seg.ds_len == 0) 701227730Sraj continue; 702227730Sraj } 703227730Sraj 704227730Sraj while (1) { 705227730Sraj /* 706227730Sraj * Fill in current packet with data. Break if there is 707227730Sraj * no more data in current DMA segment or an error 708227730Sraj * occured. 709227730Sraj */ 710227730Sraj size = cesa_fill_packet(sc, &cp, &seg); 711227730Sraj if (size <= 0) { 712227730Sraj error = -size; 713227730Sraj break; 714227730Sraj } 715227730Sraj 716227730Sraj len -= size; 717227730Sraj 718227730Sraj /* If packet is full, append it to the chain */ 719227730Sraj if (cp.cp_size == cp.cp_offset) { 720227730Sraj csd = cesa_alloc_sdesc(sc, cr); 721227730Sraj if (!csd) { 722227730Sraj error = ENOMEM; 723227730Sraj break; 724227730Sraj } 725227730Sraj 726227730Sraj /* Create SA descriptor for this packet */ 727227730Sraj csd->csd_cshd->cshd_config = cci->cci_config; 728227730Sraj csd->csd_cshd->cshd_mac_total_dlen = tmlen; 729227730Sraj 730227730Sraj /* 731227730Sraj * Enable fragmentation if request will not fit 732227730Sraj * into one packet. 733227730Sraj */ 734227730Sraj if (len > 0) { 735227730Sraj if (!fragmented) { 736227730Sraj fragmented = 1; 737227730Sraj csd->csd_cshd->cshd_config |= 738227730Sraj CESA_CSHD_FRAG_FIRST; 739227730Sraj } else 740227730Sraj csd->csd_cshd->cshd_config |= 741227730Sraj CESA_CSHD_FRAG_MIDDLE; 742227730Sraj } else if (fragmented) 743227730Sraj csd->csd_cshd->cshd_config |= 744227730Sraj CESA_CSHD_FRAG_LAST; 745227730Sraj 746227730Sraj if (eskip < cp.cp_size && elen > 0) { 747227730Sraj csd->csd_cshd->cshd_enc_src = 748227730Sraj CESA_DATA(eskip); 749227730Sraj csd->csd_cshd->cshd_enc_dst = 750227730Sraj CESA_DATA(eskip); 751227730Sraj csd->csd_cshd->cshd_enc_dlen = 752227730Sraj MIN(elen, cp.cp_size - eskip); 753227730Sraj } 754227730Sraj 755227730Sraj if (mskip < cp.cp_size && mlen > 0) { 756227730Sraj csd->csd_cshd->cshd_mac_src = 757227730Sraj CESA_DATA(mskip); 758227730Sraj csd->csd_cshd->cshd_mac_dlen = 759227730Sraj MIN(mlen, cp.cp_size - mskip); 760227730Sraj } 761227730Sraj 762227730Sraj elen -= csd->csd_cshd->cshd_enc_dlen; 763227730Sraj eskip -= MIN(eskip, cp.cp_size); 764227730Sraj mlen -= csd->csd_cshd->cshd_mac_dlen; 765227730Sraj mskip -= MIN(mskip, cp.cp_size); 766227730Sraj 767227730Sraj cesa_dump_cshd(sc, csd->csd_cshd); 768227730Sraj 769227730Sraj /* Append packet to the request */ 770227730Sraj error = cesa_append_packet(sc, cr, &cp, csd); 771227730Sraj if (error) 772227730Sraj break; 773227730Sraj 774227730Sraj /* Start a new packet, as current is full */ 775227730Sraj cesa_start_packet(&cp, MIN(mpsize, len)); 776227730Sraj } 777227730Sraj } 778227730Sraj 779227730Sraj if (error) 780227730Sraj break; 781227730Sraj } 782227730Sraj 783227730Sraj if (error) { 784227730Sraj /* 785227730Sraj * Move all allocated resources to the request. They will be 786227730Sraj * freed later. 787227730Sraj */ 788227730Sraj STAILQ_CONCAT(&cr->cr_tdesc, &cp.cp_copyin); 789227730Sraj STAILQ_CONCAT(&cr->cr_tdesc, &cp.cp_copyout); 790227730Sraj cci->cci_error = error; 791227730Sraj } 792227730Sraj} 793227730Sraj 794227730Srajstatic void 795227730Srajcesa_create_chain_cb2(void *arg, bus_dma_segment_t *segs, int nseg, 796227730Sraj bus_size_t size, int error) 797227730Sraj{ 798227730Sraj 799227730Sraj cesa_create_chain_cb(arg, segs, nseg, error); 800227730Sraj} 801227730Sraj 802227730Srajstatic int 803227730Srajcesa_create_chain(struct cesa_softc *sc, struct cesa_request *cr) 804227730Sraj{ 805227730Sraj struct cesa_chain_info cci; 806227730Sraj struct cesa_tdma_desc *ctd; 807227730Sraj uint32_t config; 808227730Sraj int error; 809227730Sraj 810227730Sraj error = 0; 811227730Sraj CESA_LOCK_ASSERT(sc, sessions); 812227730Sraj 813227730Sraj /* Create request metadata */ 814227730Sraj if (cr->cr_enc) { 815227730Sraj if (cr->cr_enc->crd_alg == CRYPTO_AES_CBC && 816227730Sraj (cr->cr_enc->crd_flags & CRD_F_ENCRYPT) == 0) 817227730Sraj memcpy(cr->cr_csd->csd_key, cr->cr_cs->cs_aes_dkey, 818227730Sraj cr->cr_cs->cs_klen); 819227730Sraj else 820227730Sraj memcpy(cr->cr_csd->csd_key, cr->cr_cs->cs_key, 821227730Sraj cr->cr_cs->cs_klen); 822227730Sraj } 823227730Sraj 824227730Sraj if (cr->cr_mac) { 825227730Sraj memcpy(cr->cr_csd->csd_hiv_in, cr->cr_cs->cs_hiv_in, 826227730Sraj CESA_MAX_HASH_LEN); 827227730Sraj memcpy(cr->cr_csd->csd_hiv_out, cr->cr_cs->cs_hiv_out, 828227730Sraj CESA_MAX_HASH_LEN); 829227730Sraj } 830227730Sraj 831227730Sraj ctd = cesa_tdma_copyin_sa_data(sc, cr); 832227730Sraj if (!ctd) 833227730Sraj return (ENOMEM); 834227730Sraj 835227730Sraj cesa_append_tdesc(cr, ctd); 836227730Sraj 837227730Sraj /* Prepare SA configuration */ 838227730Sraj config = cr->cr_cs->cs_config; 839227730Sraj 840227730Sraj if (cr->cr_enc && (cr->cr_enc->crd_flags & CRD_F_ENCRYPT) == 0) 841227730Sraj config |= CESA_CSHD_DECRYPT; 842227730Sraj if (cr->cr_enc && !cr->cr_mac) 843227730Sraj config |= CESA_CSHD_ENC; 844227730Sraj if (!cr->cr_enc && cr->cr_mac) 845227730Sraj config |= CESA_CSHD_MAC; 846227730Sraj if (cr->cr_enc && cr->cr_mac) 847227730Sraj config |= (config & CESA_CSHD_DECRYPT) ? CESA_CSHD_MAC_AND_ENC : 848227730Sraj CESA_CSHD_ENC_AND_MAC; 849227730Sraj 850227730Sraj /* Create data packets */ 851227730Sraj cci.cci_sc = sc; 852227730Sraj cci.cci_cr = cr; 853227730Sraj cci.cci_enc = cr->cr_enc; 854227730Sraj cci.cci_mac = cr->cr_mac; 855227730Sraj cci.cci_config = config; 856227730Sraj cci.cci_error = 0; 857227730Sraj 858227730Sraj if (cr->cr_crp->crp_flags & CRYPTO_F_IOV) 859227730Sraj error = bus_dmamap_load_uio(sc->sc_data_dtag, 860227730Sraj cr->cr_dmap, (struct uio *)cr->cr_crp->crp_buf, 861227730Sraj cesa_create_chain_cb2, &cci, BUS_DMA_NOWAIT); 862227730Sraj else if (cr->cr_crp->crp_flags & CRYPTO_F_IMBUF) 863227730Sraj error = bus_dmamap_load_mbuf(sc->sc_data_dtag, 864227730Sraj cr->cr_dmap, (struct mbuf *)cr->cr_crp->crp_buf, 865227730Sraj cesa_create_chain_cb2, &cci, BUS_DMA_NOWAIT); 866227730Sraj else 867227730Sraj error = bus_dmamap_load(sc->sc_data_dtag, 868227730Sraj cr->cr_dmap, cr->cr_crp->crp_buf, 869227730Sraj cr->cr_crp->crp_ilen, cesa_create_chain_cb, &cci, 870227730Sraj BUS_DMA_NOWAIT); 871227730Sraj 872227730Sraj if (!error) 873227730Sraj cr->cr_dmap_loaded = 1; 874227730Sraj 875227730Sraj if (cci.cci_error) 876227730Sraj error = cci.cci_error; 877227730Sraj 878227730Sraj if (error) 879227730Sraj return (error); 880227730Sraj 881227730Sraj /* Read back request metadata */ 882227730Sraj ctd = cesa_tdma_copyout_sa_data(sc, cr); 883227730Sraj if (!ctd) 884227730Sraj return (ENOMEM); 885227730Sraj 886227730Sraj cesa_append_tdesc(cr, ctd); 887227730Sraj 888227730Sraj return (0); 889227730Sraj} 890227730Sraj 891227730Srajstatic void 892227730Srajcesa_execute(struct cesa_softc *sc) 893227730Sraj{ 894227730Sraj struct cesa_tdma_desc *prev_ctd, *ctd; 895227730Sraj struct cesa_request *prev_cr, *cr; 896227730Sraj 897227730Sraj CESA_LOCK(sc, requests); 898227730Sraj 899227730Sraj /* 900227730Sraj * If ready list is empty, there is nothing to execute. If queued list 901227730Sraj * is not empty, the hardware is busy and we cannot start another 902227730Sraj * execution. 903227730Sraj */ 904227730Sraj if (STAILQ_EMPTY(&sc->sc_ready_requests) || 905227730Sraj !STAILQ_EMPTY(&sc->sc_queued_requests)) { 906227730Sraj CESA_UNLOCK(sc, requests); 907227730Sraj return; 908227730Sraj } 909227730Sraj 910227730Sraj /* Move all ready requests to queued list */ 911227730Sraj STAILQ_CONCAT(&sc->sc_queued_requests, &sc->sc_ready_requests); 912227730Sraj STAILQ_INIT(&sc->sc_ready_requests); 913227730Sraj 914227730Sraj /* Create one execution chain from all requests on the list */ 915227730Sraj if (STAILQ_FIRST(&sc->sc_queued_requests) != 916227730Sraj STAILQ_LAST(&sc->sc_queued_requests, cesa_request, cr_stq)) { 917227730Sraj prev_cr = NULL; 918227730Sraj cesa_sync_dma_mem(&sc->sc_tdesc_cdm, BUS_DMASYNC_POSTREAD | 919227730Sraj BUS_DMASYNC_POSTWRITE); 920227730Sraj 921227730Sraj STAILQ_FOREACH(cr, &sc->sc_queued_requests, cr_stq) { 922227730Sraj if (prev_cr) { 923227730Sraj ctd = STAILQ_FIRST(&cr->cr_tdesc); 924227730Sraj prev_ctd = STAILQ_LAST(&prev_cr->cr_tdesc, 925227730Sraj cesa_tdma_desc, ctd_stq); 926227730Sraj 927227730Sraj prev_ctd->ctd_cthd->cthd_next = 928227730Sraj ctd->ctd_cthd_paddr; 929227730Sraj } 930227730Sraj 931227730Sraj prev_cr = cr; 932227730Sraj } 933227730Sraj 934227730Sraj cesa_sync_dma_mem(&sc->sc_tdesc_cdm, BUS_DMASYNC_PREREAD | 935227730Sraj BUS_DMASYNC_PREWRITE); 936227730Sraj } 937227730Sraj 938227730Sraj /* Start chain execution in hardware */ 939227730Sraj cr = STAILQ_FIRST(&sc->sc_queued_requests); 940227730Sraj ctd = STAILQ_FIRST(&cr->cr_tdesc); 941227730Sraj 942227730Sraj CESA_WRITE(sc, CESA_TDMA_ND, ctd->ctd_cthd_paddr); 943227730Sraj CESA_WRITE(sc, CESA_SA_CMD, CESA_SA_CMD_ACTVATE); 944227730Sraj 945227730Sraj CESA_UNLOCK(sc, requests); 946227730Sraj} 947227730Sraj 948227730Srajstatic int 949227730Srajcesa_setup_sram(struct cesa_softc *sc) 950227730Sraj{ 951227730Sraj phandle_t sram_node; 952227730Sraj ihandle_t sram_ihandle; 953227730Sraj pcell_t sram_handle, sram_reg; 954227730Sraj 955227730Sraj if (OF_getprop(ofw_bus_get_node(sc->sc_dev), "sram-handle", 956227730Sraj (void *)&sram_handle, sizeof(sram_handle)) <= 0) 957227730Sraj return (ENXIO); 958227730Sraj 959227730Sraj sram_ihandle = (ihandle_t)sram_handle; 960227730Sraj sram_ihandle = fdt32_to_cpu(sram_ihandle); 961227730Sraj sram_node = OF_instance_to_package(sram_ihandle); 962227730Sraj 963227730Sraj if (OF_getprop(sram_node, "reg", (void *)&sram_reg, 964227730Sraj sizeof(sram_reg)) <= 0) 965227730Sraj return (ENXIO); 966227730Sraj 967227730Sraj sc->sc_sram_base = fdt32_to_cpu(sram_reg); 968227730Sraj 969227730Sraj return (0); 970227730Sraj} 971227730Sraj 972227730Srajstatic int 973227730Srajcesa_probe(device_t dev) 974227730Sraj{ 975261410Sian 976261410Sian if (!ofw_bus_status_okay(dev)) 977261410Sian return (ENXIO); 978261410Sian 979227730Sraj if (!ofw_bus_is_compatible(dev, "mrvl,cesa")) 980227730Sraj return (ENXIO); 981227730Sraj 982227730Sraj device_set_desc(dev, "Marvell Cryptographic Engine and Security " 983227730Sraj "Accelerator"); 984227730Sraj 985227730Sraj return (BUS_PROBE_DEFAULT); 986227730Sraj} 987227730Sraj 988227730Srajstatic int 989227730Srajcesa_attach(device_t dev) 990227730Sraj{ 991227730Sraj struct cesa_softc *sc; 992227730Sraj uint32_t d, r; 993227730Sraj int error; 994227730Sraj int i; 995227730Sraj 996227730Sraj sc = device_get_softc(dev); 997227730Sraj sc->sc_blocked = 0; 998227730Sraj sc->sc_error = 0; 999227730Sraj sc->sc_dev = dev; 1000227730Sraj 1001250291Sgber /* Check if CESA peripheral device has power turned on */ 1002257326Srrs#if defined(SOC_MV_KIRKWOOD) 1003257326Srrs if (soc_power_ctrl_get(CPU_PM_CTRL_CRYPTO) == CPU_PM_CTRL_CRYPTO) { 1004257326Srrs device_printf(dev, "not powered on\n"); 1005257326Srrs return (ENXIO); 1006257326Srrs } 1007257326Srrs#else 1008250291Sgber if (soc_power_ctrl_get(CPU_PM_CTRL_CRYPTO) != CPU_PM_CTRL_CRYPTO) { 1009250291Sgber device_printf(dev, "not powered on\n"); 1010250291Sgber return (ENXIO); 1011227730Sraj } 1012257326Srrs#endif 1013227730Sraj soc_id(&d, &r); 1014227730Sraj 1015227730Sraj switch (d) { 1016227730Sraj case MV_DEV_88F6281: 1017238873Shrs case MV_DEV_88F6282: 1018227730Sraj sc->sc_tperr = 0; 1019227730Sraj break; 1020227730Sraj case MV_DEV_MV78100: 1021227730Sraj case MV_DEV_MV78100_Z0: 1022227730Sraj sc->sc_tperr = CESA_ICR_TPERR; 1023227730Sraj break; 1024227730Sraj default: 1025227730Sraj return (ENXIO); 1026227730Sraj } 1027227730Sraj 1028227730Sraj /* Initialize mutexes */ 1029227730Sraj mtx_init(&sc->sc_sc_lock, device_get_nameunit(dev), 1030227730Sraj "CESA Shared Data", MTX_DEF); 1031227730Sraj mtx_init(&sc->sc_tdesc_lock, device_get_nameunit(dev), 1032227730Sraj "CESA TDMA Descriptors Pool", MTX_DEF); 1033227730Sraj mtx_init(&sc->sc_sdesc_lock, device_get_nameunit(dev), 1034227730Sraj "CESA SA Descriptors Pool", MTX_DEF); 1035227730Sraj mtx_init(&sc->sc_requests_lock, device_get_nameunit(dev), 1036227730Sraj "CESA Requests Pool", MTX_DEF); 1037227730Sraj mtx_init(&sc->sc_sessions_lock, device_get_nameunit(dev), 1038227730Sraj "CESA Sessions Pool", MTX_DEF); 1039227730Sraj 1040227730Sraj /* Allocate I/O and IRQ resources */ 1041227730Sraj error = bus_alloc_resources(dev, cesa_res_spec, sc->sc_res); 1042227730Sraj if (error) { 1043227730Sraj device_printf(dev, "could not allocate resources\n"); 1044227730Sraj goto err0; 1045227730Sraj } 1046227730Sraj 1047227730Sraj sc->sc_bsh = rman_get_bushandle(*(sc->sc_res)); 1048227730Sraj sc->sc_bst = rman_get_bustag(*(sc->sc_res)); 1049227730Sraj 1050250291Sgber /* Setup CESA decoding windows */ 1051250291Sgber error = decode_win_cesa_setup(sc); 1052250291Sgber if (error) { 1053250291Sgber device_printf(dev, "could not setup decoding windows\n"); 1054250291Sgber goto err1; 1055250291Sgber } 1056250291Sgber 1057250291Sgber /* Acquire SRAM base address */ 1058250291Sgber error = cesa_setup_sram(sc); 1059250291Sgber if (error) { 1060250291Sgber device_printf(dev, "could not setup SRAM\n"); 1061250291Sgber goto err1; 1062250291Sgber } 1063250291Sgber 1064227730Sraj /* Setup interrupt handler */ 1065227730Sraj error = bus_setup_intr(dev, sc->sc_res[1], INTR_TYPE_NET | INTR_MPSAFE, 1066227730Sraj NULL, cesa_intr, sc, &(sc->sc_icookie)); 1067227730Sraj if (error) { 1068227730Sraj device_printf(dev, "could not setup engine completion irq\n"); 1069227730Sraj goto err1; 1070227730Sraj } 1071227730Sraj 1072227730Sraj /* Create DMA tag for processed data */ 1073232883Sscottl error = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1074227730Sraj 1, 0, /* alignment, boundary */ 1075227730Sraj BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1076227730Sraj BUS_SPACE_MAXADDR, /* highaddr */ 1077227730Sraj NULL, NULL, /* filtfunc, filtfuncarg */ 1078227730Sraj CESA_MAX_REQUEST_SIZE, /* maxsize */ 1079227730Sraj CESA_MAX_FRAGMENTS, /* nsegments */ 1080227730Sraj CESA_MAX_REQUEST_SIZE, 0, /* maxsegsz, flags */ 1081227730Sraj NULL, NULL, /* lockfunc, lockfuncarg */ 1082227730Sraj &sc->sc_data_dtag); /* dmat */ 1083227730Sraj if (error) 1084227730Sraj goto err2; 1085227730Sraj 1086227730Sraj /* Initialize data structures: TDMA Descriptors Pool */ 1087227730Sraj error = cesa_alloc_dma_mem(sc, &sc->sc_tdesc_cdm, 1088227730Sraj CESA_TDMA_DESCRIPTORS * sizeof(struct cesa_tdma_hdesc)); 1089227730Sraj if (error) 1090227730Sraj goto err3; 1091227730Sraj 1092227730Sraj STAILQ_INIT(&sc->sc_free_tdesc); 1093227730Sraj for (i = 0; i < CESA_TDMA_DESCRIPTORS; i++) { 1094227730Sraj sc->sc_tdesc[i].ctd_cthd = 1095227730Sraj (struct cesa_tdma_hdesc *)(sc->sc_tdesc_cdm.cdm_vaddr) + i; 1096227730Sraj sc->sc_tdesc[i].ctd_cthd_paddr = sc->sc_tdesc_cdm.cdm_paddr + 1097227730Sraj (i * sizeof(struct cesa_tdma_hdesc)); 1098227730Sraj STAILQ_INSERT_TAIL(&sc->sc_free_tdesc, &sc->sc_tdesc[i], 1099227730Sraj ctd_stq); 1100227730Sraj } 1101227730Sraj 1102227730Sraj /* Initialize data structures: SA Descriptors Pool */ 1103227730Sraj error = cesa_alloc_dma_mem(sc, &sc->sc_sdesc_cdm, 1104227730Sraj CESA_SA_DESCRIPTORS * sizeof(struct cesa_sa_hdesc)); 1105227730Sraj if (error) 1106227730Sraj goto err4; 1107227730Sraj 1108227730Sraj STAILQ_INIT(&sc->sc_free_sdesc); 1109227730Sraj for (i = 0; i < CESA_SA_DESCRIPTORS; i++) { 1110227730Sraj sc->sc_sdesc[i].csd_cshd = 1111227730Sraj (struct cesa_sa_hdesc *)(sc->sc_sdesc_cdm.cdm_vaddr) + i; 1112227730Sraj sc->sc_sdesc[i].csd_cshd_paddr = sc->sc_sdesc_cdm.cdm_paddr + 1113227730Sraj (i * sizeof(struct cesa_sa_hdesc)); 1114227730Sraj STAILQ_INSERT_TAIL(&sc->sc_free_sdesc, &sc->sc_sdesc[i], 1115227730Sraj csd_stq); 1116227730Sraj } 1117227730Sraj 1118227730Sraj /* Initialize data structures: Requests Pool */ 1119227730Sraj error = cesa_alloc_dma_mem(sc, &sc->sc_requests_cdm, 1120227730Sraj CESA_REQUESTS * sizeof(struct cesa_sa_data)); 1121227730Sraj if (error) 1122227730Sraj goto err5; 1123227730Sraj 1124227730Sraj STAILQ_INIT(&sc->sc_free_requests); 1125227730Sraj STAILQ_INIT(&sc->sc_ready_requests); 1126227730Sraj STAILQ_INIT(&sc->sc_queued_requests); 1127227730Sraj for (i = 0; i < CESA_REQUESTS; i++) { 1128227730Sraj sc->sc_requests[i].cr_csd = 1129227730Sraj (struct cesa_sa_data *)(sc->sc_requests_cdm.cdm_vaddr) + i; 1130227730Sraj sc->sc_requests[i].cr_csd_paddr = 1131227730Sraj sc->sc_requests_cdm.cdm_paddr + 1132227730Sraj (i * sizeof(struct cesa_sa_data)); 1133227730Sraj 1134227730Sraj /* Preallocate DMA maps */ 1135227730Sraj error = bus_dmamap_create(sc->sc_data_dtag, 0, 1136227730Sraj &sc->sc_requests[i].cr_dmap); 1137227730Sraj if (error && i > 0) { 1138227730Sraj i--; 1139227730Sraj do { 1140227730Sraj bus_dmamap_destroy(sc->sc_data_dtag, 1141227730Sraj sc->sc_requests[i].cr_dmap); 1142227730Sraj } while (i--); 1143227730Sraj 1144227730Sraj goto err6; 1145227730Sraj } 1146227730Sraj 1147227730Sraj STAILQ_INSERT_TAIL(&sc->sc_free_requests, &sc->sc_requests[i], 1148227730Sraj cr_stq); 1149227730Sraj } 1150227730Sraj 1151227730Sraj /* Initialize data structures: Sessions Pool */ 1152227730Sraj STAILQ_INIT(&sc->sc_free_sessions); 1153227730Sraj for (i = 0; i < CESA_SESSIONS; i++) { 1154227730Sraj sc->sc_sessions[i].cs_sid = i; 1155227730Sraj STAILQ_INSERT_TAIL(&sc->sc_free_sessions, &sc->sc_sessions[i], 1156227730Sraj cs_stq); 1157227730Sraj } 1158227730Sraj 1159227730Sraj /* 1160227730Sraj * Initialize TDMA: 1161227730Sraj * - Burst limit: 128 bytes, 1162227730Sraj * - Outstanding reads enabled, 1163227730Sraj * - No byte-swap. 1164227730Sraj */ 1165227730Sraj CESA_WRITE(sc, CESA_TDMA_CR, CESA_TDMA_CR_DBL128 | CESA_TDMA_CR_SBL128 | 1166227730Sraj CESA_TDMA_CR_ORDEN | CESA_TDMA_CR_NBS | CESA_TDMA_CR_ENABLE); 1167227730Sraj 1168227730Sraj /* 1169227730Sraj * Initialize SA: 1170227730Sraj * - SA descriptor is present at beginning of CESA SRAM, 1171227730Sraj * - Multi-packet chain mode, 1172227730Sraj * - Cooperation with TDMA enabled. 1173227730Sraj */ 1174227730Sraj CESA_WRITE(sc, CESA_SA_DPR, 0); 1175227730Sraj CESA_WRITE(sc, CESA_SA_CR, CESA_SA_CR_ACTIVATE_TDMA | 1176227730Sraj CESA_SA_CR_WAIT_FOR_TDMA | CESA_SA_CR_MULTI_MODE); 1177227730Sraj 1178227730Sraj /* Unmask interrupts */ 1179227730Sraj CESA_WRITE(sc, CESA_ICR, 0); 1180227730Sraj CESA_WRITE(sc, CESA_ICM, CESA_ICM_ACCTDMA | sc->sc_tperr); 1181227730Sraj CESA_WRITE(sc, CESA_TDMA_ECR, 0); 1182227730Sraj CESA_WRITE(sc, CESA_TDMA_EMR, CESA_TDMA_EMR_MISS | 1183227730Sraj CESA_TDMA_EMR_DOUBLE_HIT | CESA_TDMA_EMR_BOTH_HIT | 1184227730Sraj CESA_TDMA_EMR_DATA_ERROR); 1185227730Sraj 1186227730Sraj /* Register in OCF */ 1187227730Sraj sc->sc_cid = crypto_get_driverid(dev, CRYPTOCAP_F_HARDWARE); 1188227730Sraj if (sc->sc_cid) { 1189227730Sraj device_printf(dev, "could not get crypto driver id\n"); 1190227730Sraj goto err7; 1191227730Sraj } 1192227730Sraj 1193227730Sraj crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0); 1194227730Sraj crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0); 1195227730Sraj crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0); 1196227730Sraj crypto_register(sc->sc_cid, CRYPTO_MD5, 0, 0); 1197227730Sraj crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0); 1198227730Sraj crypto_register(sc->sc_cid, CRYPTO_SHA1, 0, 0); 1199227730Sraj crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0); 1200227730Sraj 1201227730Sraj return (0); 1202227730Srajerr7: 1203227730Sraj for (i = 0; i < CESA_REQUESTS; i++) 1204227730Sraj bus_dmamap_destroy(sc->sc_data_dtag, 1205227730Sraj sc->sc_requests[i].cr_dmap); 1206227730Srajerr6: 1207227730Sraj cesa_free_dma_mem(&sc->sc_requests_cdm); 1208227730Srajerr5: 1209227730Sraj cesa_free_dma_mem(&sc->sc_sdesc_cdm); 1210227730Srajerr4: 1211227730Sraj cesa_free_dma_mem(&sc->sc_tdesc_cdm); 1212227730Srajerr3: 1213227730Sraj bus_dma_tag_destroy(sc->sc_data_dtag); 1214227730Srajerr2: 1215227730Sraj bus_teardown_intr(dev, sc->sc_res[1], sc->sc_icookie); 1216227730Srajerr1: 1217227730Sraj bus_release_resources(dev, cesa_res_spec, sc->sc_res); 1218227730Srajerr0: 1219227730Sraj mtx_destroy(&sc->sc_sessions_lock); 1220227730Sraj mtx_destroy(&sc->sc_requests_lock); 1221227730Sraj mtx_destroy(&sc->sc_sdesc_lock); 1222227730Sraj mtx_destroy(&sc->sc_tdesc_lock); 1223227730Sraj mtx_destroy(&sc->sc_sc_lock); 1224227730Sraj return (ENXIO); 1225227730Sraj} 1226227730Sraj 1227227730Srajstatic int 1228227730Srajcesa_detach(device_t dev) 1229227730Sraj{ 1230227730Sraj struct cesa_softc *sc; 1231227730Sraj int i; 1232227730Sraj 1233227730Sraj sc = device_get_softc(dev); 1234227730Sraj 1235227730Sraj /* TODO: Wait for queued requests completion before shutdown. */ 1236227730Sraj 1237227730Sraj /* Mask interrupts */ 1238227730Sraj CESA_WRITE(sc, CESA_ICM, 0); 1239227730Sraj CESA_WRITE(sc, CESA_TDMA_EMR, 0); 1240227730Sraj 1241227730Sraj /* Unregister from OCF */ 1242227730Sraj crypto_unregister_all(sc->sc_cid); 1243227730Sraj 1244227730Sraj /* Free DMA Maps */ 1245227730Sraj for (i = 0; i < CESA_REQUESTS; i++) 1246227730Sraj bus_dmamap_destroy(sc->sc_data_dtag, 1247227730Sraj sc->sc_requests[i].cr_dmap); 1248227730Sraj 1249227730Sraj /* Free DMA Memory */ 1250227730Sraj cesa_free_dma_mem(&sc->sc_requests_cdm); 1251227730Sraj cesa_free_dma_mem(&sc->sc_sdesc_cdm); 1252227730Sraj cesa_free_dma_mem(&sc->sc_tdesc_cdm); 1253227730Sraj 1254227730Sraj /* Free DMA Tag */ 1255227730Sraj bus_dma_tag_destroy(sc->sc_data_dtag); 1256227730Sraj 1257227730Sraj /* Stop interrupt */ 1258227730Sraj bus_teardown_intr(dev, sc->sc_res[1], sc->sc_icookie); 1259227730Sraj 1260227730Sraj /* Relase I/O and IRQ resources */ 1261227730Sraj bus_release_resources(dev, cesa_res_spec, sc->sc_res); 1262227730Sraj 1263227730Sraj /* Destory mutexes */ 1264227730Sraj mtx_destroy(&sc->sc_sessions_lock); 1265227730Sraj mtx_destroy(&sc->sc_requests_lock); 1266227730Sraj mtx_destroy(&sc->sc_sdesc_lock); 1267227730Sraj mtx_destroy(&sc->sc_tdesc_lock); 1268227730Sraj mtx_destroy(&sc->sc_sc_lock); 1269227730Sraj 1270227730Sraj return (0); 1271227730Sraj} 1272227730Sraj 1273227730Srajstatic void 1274227730Srajcesa_intr(void *arg) 1275227730Sraj{ 1276227730Sraj STAILQ_HEAD(, cesa_request) requests; 1277227730Sraj struct cesa_request *cr, *tmp; 1278227730Sraj struct cesa_softc *sc; 1279227730Sraj uint32_t ecr, icr; 1280227730Sraj int blocked; 1281227730Sraj 1282227730Sraj sc = arg; 1283227730Sraj 1284227730Sraj /* Ack interrupt */ 1285227730Sraj ecr = CESA_READ(sc, CESA_TDMA_ECR); 1286227730Sraj CESA_WRITE(sc, CESA_TDMA_ECR, 0); 1287227730Sraj icr = CESA_READ(sc, CESA_ICR); 1288227730Sraj CESA_WRITE(sc, CESA_ICR, 0); 1289227730Sraj 1290227730Sraj /* Check for TDMA errors */ 1291227730Sraj if (ecr & CESA_TDMA_ECR_MISS) { 1292227730Sraj device_printf(sc->sc_dev, "TDMA Miss error detected!\n"); 1293227730Sraj sc->sc_error = EIO; 1294227730Sraj } 1295227730Sraj 1296227730Sraj if (ecr & CESA_TDMA_ECR_DOUBLE_HIT) { 1297227730Sraj device_printf(sc->sc_dev, "TDMA Double Hit error detected!\n"); 1298227730Sraj sc->sc_error = EIO; 1299227730Sraj } 1300227730Sraj 1301227730Sraj if (ecr & CESA_TDMA_ECR_BOTH_HIT) { 1302227730Sraj device_printf(sc->sc_dev, "TDMA Both Hit error detected!\n"); 1303227730Sraj sc->sc_error = EIO; 1304227730Sraj } 1305227730Sraj 1306227730Sraj if (ecr & CESA_TDMA_ECR_DATA_ERROR) { 1307227730Sraj device_printf(sc->sc_dev, "TDMA Data error detected!\n"); 1308227730Sraj sc->sc_error = EIO; 1309227730Sraj } 1310227730Sraj 1311227730Sraj /* Check for CESA errors */ 1312227730Sraj if (icr & sc->sc_tperr) { 1313227730Sraj device_printf(sc->sc_dev, "CESA SRAM Parity error detected!\n"); 1314227730Sraj sc->sc_error = EIO; 1315227730Sraj } 1316227730Sraj 1317227730Sraj /* If there is nothing more to do, return */ 1318227730Sraj if ((icr & CESA_ICR_ACCTDMA) == 0) 1319227730Sraj return; 1320227730Sraj 1321227730Sraj /* Get all finished requests */ 1322227730Sraj CESA_LOCK(sc, requests); 1323227730Sraj STAILQ_INIT(&requests); 1324227730Sraj STAILQ_CONCAT(&requests, &sc->sc_queued_requests); 1325227730Sraj STAILQ_INIT(&sc->sc_queued_requests); 1326227730Sraj CESA_UNLOCK(sc, requests); 1327227730Sraj 1328227730Sraj /* Execute all ready requests */ 1329227730Sraj cesa_execute(sc); 1330227730Sraj 1331227730Sraj /* Process completed requests */ 1332227730Sraj cesa_sync_dma_mem(&sc->sc_requests_cdm, BUS_DMASYNC_POSTREAD | 1333227730Sraj BUS_DMASYNC_POSTWRITE); 1334227730Sraj 1335227730Sraj STAILQ_FOREACH_SAFE(cr, &requests, cr_stq, tmp) { 1336227730Sraj bus_dmamap_sync(sc->sc_data_dtag, cr->cr_dmap, 1337227730Sraj BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1338227730Sraj 1339227730Sraj cr->cr_crp->crp_etype = sc->sc_error; 1340227730Sraj if (cr->cr_mac) 1341227730Sraj crypto_copyback(cr->cr_crp->crp_flags, 1342227730Sraj cr->cr_crp->crp_buf, cr->cr_mac->crd_inject, 1343227730Sraj cr->cr_cs->cs_hlen, cr->cr_csd->csd_hash); 1344227730Sraj 1345227730Sraj crypto_done(cr->cr_crp); 1346227730Sraj cesa_free_request(sc, cr); 1347227730Sraj } 1348227730Sraj 1349227730Sraj cesa_sync_dma_mem(&sc->sc_requests_cdm, BUS_DMASYNC_PREREAD | 1350227730Sraj BUS_DMASYNC_PREWRITE); 1351227730Sraj 1352227730Sraj sc->sc_error = 0; 1353227730Sraj 1354227730Sraj /* Unblock driver if it ran out of resources */ 1355227730Sraj CESA_LOCK(sc, sc); 1356227730Sraj blocked = sc->sc_blocked; 1357227730Sraj sc->sc_blocked = 0; 1358227730Sraj CESA_UNLOCK(sc, sc); 1359227730Sraj 1360227730Sraj if (blocked) 1361227730Sraj crypto_unblock(sc->sc_cid, blocked); 1362227730Sraj} 1363227730Sraj 1364227730Srajstatic int 1365227730Srajcesa_newsession(device_t dev, uint32_t *sidp, struct cryptoini *cri) 1366227730Sraj{ 1367227730Sraj struct cesa_session *cs; 1368227730Sraj struct cesa_softc *sc; 1369227730Sraj struct cryptoini *enc; 1370227730Sraj struct cryptoini *mac; 1371227730Sraj int error; 1372227730Sraj 1373227730Sraj sc = device_get_softc(dev); 1374227730Sraj enc = NULL; 1375227730Sraj mac = NULL; 1376227730Sraj error = 0; 1377227730Sraj 1378227730Sraj /* Check and parse input */ 1379227730Sraj if (cesa_is_hash(cri->cri_alg)) 1380227730Sraj mac = cri; 1381227730Sraj else 1382227730Sraj enc = cri; 1383227730Sraj 1384227730Sraj cri = cri->cri_next; 1385227730Sraj 1386227730Sraj if (cri) { 1387227730Sraj if (!enc && !cesa_is_hash(cri->cri_alg)) 1388227730Sraj enc = cri; 1389227730Sraj 1390227730Sraj if (!mac && cesa_is_hash(cri->cri_alg)) 1391227730Sraj mac = cri; 1392227730Sraj 1393227730Sraj if (cri->cri_next || !(enc && mac)) 1394227730Sraj return (EINVAL); 1395227730Sraj } 1396227730Sraj 1397227730Sraj if ((enc && (enc->cri_klen / 8) > CESA_MAX_KEY_LEN) || 1398227730Sraj (mac && (mac->cri_klen / 8) > CESA_MAX_MKEY_LEN)) 1399227730Sraj return (E2BIG); 1400227730Sraj 1401227730Sraj /* Allocate session */ 1402227730Sraj cs = cesa_alloc_session(sc); 1403227730Sraj if (!cs) 1404227730Sraj return (ENOMEM); 1405227730Sraj 1406227730Sraj /* Prepare CESA configuration */ 1407227730Sraj cs->cs_config = 0; 1408227730Sraj cs->cs_ivlen = 1; 1409227730Sraj cs->cs_mblen = 1; 1410227730Sraj 1411227730Sraj if (enc) { 1412227730Sraj switch (enc->cri_alg) { 1413227730Sraj case CRYPTO_AES_CBC: 1414227730Sraj cs->cs_config |= CESA_CSHD_AES | CESA_CSHD_CBC; 1415227730Sraj cs->cs_ivlen = AES_BLOCK_LEN; 1416227730Sraj break; 1417227730Sraj case CRYPTO_DES_CBC: 1418227730Sraj cs->cs_config |= CESA_CSHD_DES | CESA_CSHD_CBC; 1419227730Sraj cs->cs_ivlen = DES_BLOCK_LEN; 1420227730Sraj break; 1421227730Sraj case CRYPTO_3DES_CBC: 1422227730Sraj cs->cs_config |= CESA_CSHD_3DES | CESA_CSHD_3DES_EDE | 1423227730Sraj CESA_CSHD_CBC; 1424227730Sraj cs->cs_ivlen = DES3_BLOCK_LEN; 1425227730Sraj break; 1426227730Sraj default: 1427227730Sraj error = EINVAL; 1428227730Sraj break; 1429227730Sraj } 1430227730Sraj } 1431227730Sraj 1432227730Sraj if (!error && mac) { 1433227730Sraj switch (mac->cri_alg) { 1434227730Sraj case CRYPTO_MD5: 1435227730Sraj cs->cs_config |= CESA_CSHD_MD5; 1436227730Sraj cs->cs_mblen = 1; 1437227730Sraj cs->cs_hlen = MD5_HASH_LEN; 1438227730Sraj break; 1439227730Sraj case CRYPTO_MD5_HMAC: 1440227730Sraj cs->cs_config |= CESA_CSHD_MD5_HMAC; 1441227730Sraj cs->cs_mblen = MD5_HMAC_BLOCK_LEN; 1442227730Sraj cs->cs_hlen = CESA_HMAC_HASH_LENGTH; 1443227730Sraj break; 1444227730Sraj case CRYPTO_SHA1: 1445227730Sraj cs->cs_config |= CESA_CSHD_SHA1; 1446227730Sraj cs->cs_mblen = 1; 1447227730Sraj cs->cs_hlen = SHA1_HASH_LEN; 1448227730Sraj break; 1449227730Sraj case CRYPTO_SHA1_HMAC: 1450227730Sraj cs->cs_config |= CESA_CSHD_SHA1_HMAC; 1451227730Sraj cs->cs_mblen = SHA1_HMAC_BLOCK_LEN; 1452227730Sraj cs->cs_hlen = CESA_HMAC_HASH_LENGTH; 1453227730Sraj break; 1454227730Sraj default: 1455227730Sraj error = EINVAL; 1456227730Sraj break; 1457227730Sraj } 1458227730Sraj } 1459227730Sraj 1460227730Sraj /* Save cipher key */ 1461227730Sraj if (!error && enc && enc->cri_key) { 1462227730Sraj cs->cs_klen = enc->cri_klen / 8; 1463227730Sraj memcpy(cs->cs_key, enc->cri_key, cs->cs_klen); 1464227730Sraj if (enc->cri_alg == CRYPTO_AES_CBC) 1465227730Sraj error = cesa_prep_aes_key(cs); 1466227730Sraj } 1467227730Sraj 1468227730Sraj /* Save digest key */ 1469227730Sraj if (!error && mac && mac->cri_key) 1470227730Sraj error = cesa_set_mkey(cs, mac->cri_alg, mac->cri_key, 1471227730Sraj mac->cri_klen / 8); 1472227730Sraj 1473227730Sraj if (error) { 1474227730Sraj cesa_free_session(sc, cs); 1475227730Sraj return (EINVAL); 1476227730Sraj } 1477227730Sraj 1478227730Sraj *sidp = cs->cs_sid; 1479227730Sraj 1480227730Sraj return (0); 1481227730Sraj} 1482227730Sraj 1483227730Srajstatic int 1484227730Srajcesa_freesession(device_t dev, uint64_t tid) 1485227730Sraj{ 1486227730Sraj struct cesa_session *cs; 1487227730Sraj struct cesa_softc *sc; 1488227730Sraj 1489227730Sraj sc = device_get_softc(dev); 1490227730Sraj cs = cesa_get_session(sc, CRYPTO_SESID2LID(tid)); 1491227730Sraj if (!cs) 1492227730Sraj return (EINVAL); 1493227730Sraj 1494227730Sraj /* Free session */ 1495227730Sraj cesa_free_session(sc, cs); 1496227730Sraj 1497227730Sraj return (0); 1498227730Sraj} 1499227730Sraj 1500227730Srajstatic int 1501227730Srajcesa_process(device_t dev, struct cryptop *crp, int hint) 1502227730Sraj{ 1503227730Sraj struct cesa_request *cr; 1504227730Sraj struct cesa_session *cs; 1505227730Sraj struct cryptodesc *crd; 1506227730Sraj struct cryptodesc *enc; 1507227730Sraj struct cryptodesc *mac; 1508227730Sraj struct cesa_softc *sc; 1509227730Sraj int error; 1510227730Sraj 1511227730Sraj sc = device_get_softc(dev); 1512227730Sraj crd = crp->crp_desc; 1513227730Sraj enc = NULL; 1514227730Sraj mac = NULL; 1515227730Sraj error = 0; 1516227730Sraj 1517227730Sraj /* Check session ID */ 1518227730Sraj cs = cesa_get_session(sc, CRYPTO_SESID2LID(crp->crp_sid)); 1519227730Sraj if (!cs) { 1520227730Sraj crp->crp_etype = EINVAL; 1521227730Sraj crypto_done(crp); 1522227730Sraj return (0); 1523227730Sraj } 1524227730Sraj 1525227730Sraj /* Check and parse input */ 1526227730Sraj if (crp->crp_ilen > CESA_MAX_REQUEST_SIZE) { 1527227730Sraj crp->crp_etype = E2BIG; 1528227730Sraj crypto_done(crp); 1529227730Sraj return (0); 1530227730Sraj } 1531227730Sraj 1532227730Sraj if (cesa_is_hash(crd->crd_alg)) 1533227730Sraj mac = crd; 1534227730Sraj else 1535227730Sraj enc = crd; 1536227730Sraj 1537227730Sraj crd = crd->crd_next; 1538227730Sraj 1539227730Sraj if (crd) { 1540227730Sraj if (!enc && !cesa_is_hash(crd->crd_alg)) 1541227730Sraj enc = crd; 1542227730Sraj 1543227730Sraj if (!mac && cesa_is_hash(crd->crd_alg)) 1544227730Sraj mac = crd; 1545227730Sraj 1546227730Sraj if (crd->crd_next || !(enc && mac)) { 1547227730Sraj crp->crp_etype = EINVAL; 1548227730Sraj crypto_done(crp); 1549227730Sraj return (0); 1550227730Sraj } 1551227730Sraj } 1552227730Sraj 1553227730Sraj /* 1554227730Sraj * Get request descriptor. Block driver if there is no free 1555227730Sraj * descriptors in pool. 1556227730Sraj */ 1557227730Sraj cr = cesa_alloc_request(sc); 1558227730Sraj if (!cr) { 1559227730Sraj CESA_LOCK(sc, sc); 1560227730Sraj sc->sc_blocked = CRYPTO_SYMQ; 1561227730Sraj CESA_UNLOCK(sc, sc); 1562227730Sraj return (ERESTART); 1563227730Sraj } 1564227730Sraj 1565227730Sraj /* Prepare request */ 1566227730Sraj cr->cr_crp = crp; 1567227730Sraj cr->cr_enc = enc; 1568227730Sraj cr->cr_mac = mac; 1569227730Sraj cr->cr_cs = cs; 1570227730Sraj 1571227730Sraj CESA_LOCK(sc, sessions); 1572227730Sraj cesa_sync_desc(sc, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1573227730Sraj 1574227730Sraj if (enc && enc->crd_flags & CRD_F_ENCRYPT) { 1575227730Sraj if (enc->crd_flags & CRD_F_IV_EXPLICIT) 1576227730Sraj memcpy(cr->cr_csd->csd_iv, enc->crd_iv, cs->cs_ivlen); 1577227730Sraj else 1578227730Sraj arc4rand(cr->cr_csd->csd_iv, cs->cs_ivlen, 0); 1579227730Sraj 1580227730Sraj if ((enc->crd_flags & CRD_F_IV_PRESENT) == 0) 1581227730Sraj crypto_copyback(crp->crp_flags, crp->crp_buf, 1582227730Sraj enc->crd_inject, cs->cs_ivlen, cr->cr_csd->csd_iv); 1583227730Sraj } else if (enc) { 1584227730Sraj if (enc->crd_flags & CRD_F_IV_EXPLICIT) 1585227730Sraj memcpy(cr->cr_csd->csd_iv, enc->crd_iv, cs->cs_ivlen); 1586227730Sraj else 1587227730Sraj crypto_copydata(crp->crp_flags, crp->crp_buf, 1588227730Sraj enc->crd_inject, cs->cs_ivlen, cr->cr_csd->csd_iv); 1589227730Sraj } 1590227730Sraj 1591227730Sraj if (enc && enc->crd_flags & CRD_F_KEY_EXPLICIT) { 1592227730Sraj if ((enc->crd_klen / 8) <= CESA_MAX_KEY_LEN) { 1593227730Sraj cs->cs_klen = enc->crd_klen / 8; 1594227730Sraj memcpy(cs->cs_key, enc->crd_key, cs->cs_klen); 1595227730Sraj if (enc->crd_alg == CRYPTO_AES_CBC) 1596227730Sraj error = cesa_prep_aes_key(cs); 1597227730Sraj } else 1598227730Sraj error = E2BIG; 1599227730Sraj } 1600227730Sraj 1601227730Sraj if (!error && mac && mac->crd_flags & CRD_F_KEY_EXPLICIT) { 1602227730Sraj if ((mac->crd_klen / 8) <= CESA_MAX_MKEY_LEN) 1603227730Sraj error = cesa_set_mkey(cs, mac->crd_alg, mac->crd_key, 1604227730Sraj mac->crd_klen / 8); 1605227730Sraj else 1606227730Sraj error = E2BIG; 1607227730Sraj } 1608227730Sraj 1609227730Sraj /* Convert request to chain of TDMA and SA descriptors */ 1610227730Sraj if (!error) 1611227730Sraj error = cesa_create_chain(sc, cr); 1612227730Sraj 1613227730Sraj cesa_sync_desc(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1614227730Sraj CESA_UNLOCK(sc, sessions); 1615227730Sraj 1616227730Sraj if (error) { 1617227730Sraj cesa_free_request(sc, cr); 1618227730Sraj crp->crp_etype = error; 1619227730Sraj crypto_done(crp); 1620227730Sraj return (0); 1621227730Sraj } 1622227730Sraj 1623227730Sraj bus_dmamap_sync(sc->sc_data_dtag, cr->cr_dmap, BUS_DMASYNC_PREREAD | 1624227730Sraj BUS_DMASYNC_PREWRITE); 1625227730Sraj 1626227730Sraj /* Enqueue request to execution */ 1627227730Sraj cesa_enqueue_request(sc, cr); 1628227730Sraj 1629227730Sraj /* Start execution, if we have no more requests in queue */ 1630227730Sraj if ((hint & CRYPTO_HINT_MORE) == 0) 1631227730Sraj cesa_execute(sc); 1632227730Sraj 1633227730Sraj return (0); 1634227730Sraj} 1635250291Sgber 1636250291Sgber/* 1637250291Sgber * Set CESA TDMA decode windows. 1638250291Sgber */ 1639250291Sgberstatic int 1640250291Sgberdecode_win_cesa_setup(struct cesa_softc *sc) 1641250291Sgber{ 1642250291Sgber struct mem_region availmem_regions[FDT_MEM_REGIONS]; 1643250291Sgber int availmem_regions_sz; 1644296189Swma uint32_t br, cr, i; 1645250291Sgber 1646250291Sgber /* Grab physical memory regions information from DTS */ 1647250291Sgber if (fdt_get_mem_regions(availmem_regions, &availmem_regions_sz, 1648296257Sandrew NULL) != 0) 1649250291Sgber return (ENXIO); 1650250291Sgber 1651250291Sgber if (availmem_regions_sz > MV_WIN_CESA_MAX) { 1652250291Sgber device_printf(sc->sc_dev, "Too much memory regions, cannot " 1653250291Sgber " set CESA windows to cover whole DRAM \n"); 1654250291Sgber return (ENXIO); 1655250291Sgber } 1656250291Sgber 1657250291Sgber /* Disable and clear all CESA windows */ 1658250291Sgber for (i = 0; i < MV_WIN_CESA_MAX; i++) { 1659250291Sgber CESA_WRITE(sc, MV_WIN_CESA_BASE(i), 0); 1660250291Sgber CESA_WRITE(sc, MV_WIN_CESA_CTRL(i), 0); 1661250291Sgber } 1662250291Sgber 1663250291Sgber /* Fill CESA TDMA decoding windows with information acquired from DTS */ 1664250291Sgber for (i = 0; i < availmem_regions_sz; i++) { 1665250291Sgber br = availmem_regions[i].mr_start; 1666250291Sgber cr = availmem_regions[i].mr_size; 1667250291Sgber 1668250291Sgber /* Don't add entries with size lower than 64KB */ 1669250291Sgber if (cr & 0xffff0000) { 1670250291Sgber cr = (((cr - 1) & 0xffff0000) | 1671250291Sgber (MV_WIN_DDR_ATTR(i) << MV_WIN_CPU_ATTR_SHIFT) | 1672250291Sgber (MV_WIN_DDR_TARGET << MV_WIN_CPU_TARGET_SHIFT) | 1673250291Sgber MV_WIN_CPU_ENABLE_BIT); 1674250291Sgber CESA_WRITE(sc, MV_WIN_CESA_BASE(i), br); 1675250291Sgber CESA_WRITE(sc, MV_WIN_CESA_CTRL(i), cr); 1676250291Sgber } 1677250291Sgber } 1678250291Sgber 1679250291Sgber return (0); 1680250291Sgber} 1681250291Sgber 1682