if_cas.c revision 194246
1/*- 2 * Copyright (C) 2001 Eduardo Horvath. 3 * Copyright (c) 2001-2003 Thomas Moestl 4 * Copyright (c) 2007-2009 Marius Strobl <marius@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * from: NetBSD: gem.c,v 1.21 2002/06/01 23:50:58 lukem Exp 29 * from: FreeBSD: if_gem.c 182060 2008-08-23 15:03:26Z marius 30 */ 31 32#include <sys/cdefs.h> 33__FBSDID("$FreeBSD: head/sys/dev/cas/if_cas.c 194246 2009-06-15 18:22:41Z marius $"); 34 35/* 36 * driver for Sun Cassini/Cassini+ and National Semiconductor DP83065 37 * Saturn Gigabit Ethernet controllers 38 */ 39 40#if 0 41#define CAS_DEBUG 42#endif 43 44#include <sys/param.h> 45#include <sys/systm.h> 46#include <sys/bus.h> 47#include <sys/callout.h> 48#include <sys/endian.h> 49#include <sys/mbuf.h> 50#include <sys/malloc.h> 51#include <sys/kernel.h> 52#include <sys/lock.h> 53#include <sys/module.h> 54#include <sys/mutex.h> 55#include <sys/refcount.h> 56#include <sys/resource.h> 57#include <sys/rman.h> 58#include <sys/socket.h> 59#include <sys/sockio.h> 60#include <sys/rman.h> 61 62#include <net/bpf.h> 63#include <net/ethernet.h> 64#include <net/if.h> 65#include <net/if_arp.h> 66#include <net/if_dl.h> 67#include <net/if_media.h> 68#include <net/if_types.h> 69#include <net/if_vlan_var.h> 70 71#include <netinet/in.h> 72#include <netinet/in_systm.h> 73#include <netinet/ip.h> 74#include <netinet/tcp.h> 75#include <netinet/udp.h> 76 77#include <machine/bus.h> 78#if defined(__powerpc__) || defined(__sparc64__) 79#include <dev/ofw/openfirm.h> 80#include <machine/ofw_machdep.h> 81#endif 82#include <machine/resource.h> 83 84#include <dev/mii/mii.h> 85#include <dev/mii/miivar.h> 86 87#include <dev/cas/if_casreg.h> 88#include <dev/cas/if_casvar.h> 89 90#include <dev/pci/pcireg.h> 91#include <dev/pci/pcivar.h> 92 93#include "miibus_if.h" 94 95#define RINGASSERT(n , min, max) \ 96 CTASSERT(powerof2(n) && (n) >= (min) && (n) <= (max)) 97 98RINGASSERT(CAS_NRXCOMP, 128, 32768); 99RINGASSERT(CAS_NRXDESC, 32, 8192); 100RINGASSERT(CAS_NRXDESC2, 32, 8192); 101RINGASSERT(CAS_NTXDESC, 32, 8192); 102 103#undef RINGASSERT 104 105#define CCDASSERT(m, a) \ 106 CTASSERT((offsetof(struct cas_control_data, m) & ((a) - 1)) == 0) 107 108CCDASSERT(ccd_rxcomps, CAS_RX_COMP_ALIGN); 109CCDASSERT(ccd_rxdescs, CAS_RX_DESC_ALIGN); 110CCDASSERT(ccd_rxdescs2, CAS_RX_DESC_ALIGN); 111 112#undef CCDASSERT 113 114#define CAS_TRIES 10000 115 116/* 117 * According to documentation, the hardware has support for basic TCP 118 * checksum offloading only, in practice this can be also used for UDP 119 * however (i.e. the problem of previous Sun NICs that a checksum of 0x0 120 * is not converted to 0xffff no longer exists). 121 */ 122#define CAS_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 123 124static inline void cas_add_rxdesc(struct cas_softc *sc, u_int idx); 125static int cas_attach(struct cas_softc *sc); 126static int cas_bitwait(struct cas_softc *sc, bus_addr_t r, uint32_t clr, 127 uint32_t set); 128static void cas_cddma_callback(void *xsc, bus_dma_segment_t *segs, 129 int nsegs, int error); 130static void cas_detach(struct cas_softc *sc); 131static int cas_disable_rx(struct cas_softc *sc); 132static int cas_disable_tx(struct cas_softc *sc); 133static void cas_eint(struct cas_softc *sc, u_int status); 134static void cas_free(void *arg1, void* arg2); 135static void cas_init(void *xsc); 136static void cas_init_locked(struct cas_softc *sc); 137static void cas_init_regs(struct cas_softc *sc); 138static void cas_intr(void *v); 139static int cas_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data); 140static int cas_load_txmbuf(struct cas_softc *sc, struct mbuf **m_head); 141static int cas_mediachange(struct ifnet *ifp); 142static void cas_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr); 143static void cas_meminit(struct cas_softc *sc); 144static void cas_mifinit(struct cas_softc *sc); 145static int cas_mii_readreg(device_t dev, int phy, int reg); 146static void cas_mii_statchg(device_t dev); 147static int cas_mii_writereg(device_t dev, int phy, int reg, int val); 148static void cas_reset(struct cas_softc *sc); 149static int cas_reset_rx(struct cas_softc *sc); 150static int cas_reset_tx(struct cas_softc *sc); 151static void cas_resume(struct cas_softc *sc); 152static u_int cas_descsize(u_int sz); 153static void cas_rint(struct cas_softc *sc); 154static void cas_rint_timeout(void *arg); 155static inline void cas_rxcksum(struct mbuf *m, uint16_t cksum); 156static inline void cas_rxcompinit(struct cas_rx_comp *rxcomp); 157static u_int cas_rxcompsize(u_int sz); 158static void cas_rxdma_callback(void *xsc, bus_dma_segment_t *segs, 159 int nsegs, int error); 160static void cas_setladrf(struct cas_softc *sc); 161static void cas_start(struct ifnet *ifp); 162static void cas_start_locked(struct ifnet *ifp); 163static void cas_stop(struct ifnet *ifp); 164static void cas_suspend(struct cas_softc *sc); 165static void cas_tick(void *arg); 166static void cas_tint(struct cas_softc *sc); 167static inline void cas_txkick(struct cas_softc *sc); 168static int cas_watchdog(struct cas_softc *sc); 169 170static devclass_t cas_devclass; 171 172MODULE_DEPEND(cas, ether, 1, 1, 1); 173MODULE_DEPEND(cas, miibus, 1, 1, 1); 174 175#ifdef CAS_DEBUG 176#include <sys/ktr.h> 177#define KTR_CAS KTR_CT2 178#endif 179 180static int 181cas_attach(struct cas_softc *sc) 182{ 183 struct cas_txsoft *txs; 184 struct ifnet *ifp; 185 int error, i; 186 uint32_t v; 187 188 /* Set up ifnet structure. */ 189 ifp = sc->sc_ifp = if_alloc(IFT_ETHER); 190 if (ifp == NULL) 191 return (ENOSPC); 192 ifp->if_softc = sc; 193 if_initname(ifp, device_get_name(sc->sc_dev), 194 device_get_unit(sc->sc_dev)); 195 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 196 ifp->if_start = cas_start; 197 ifp->if_ioctl = cas_ioctl; 198 ifp->if_init = cas_init; 199 IFQ_SET_MAXLEN(&ifp->if_snd, CAS_TXQUEUELEN); 200 ifp->if_snd.ifq_drv_maxlen = CAS_TXQUEUELEN; 201 IFQ_SET_READY(&ifp->if_snd); 202 203 callout_init_mtx(&sc->sc_tick_ch, &sc->sc_mtx, 0); 204 callout_init_mtx(&sc->sc_rx_ch, &sc->sc_mtx, 0); 205 206 /* Make sure the chip is stopped. */ 207 cas_reset(sc); 208 209 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 210 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 211 BUS_SPACE_MAXSIZE, 0, BUS_SPACE_MAXSIZE, 0, NULL, NULL, 212 &sc->sc_pdmatag); 213 if (error != 0) 214 goto fail_ifnet; 215 216 error = bus_dma_tag_create(sc->sc_pdmatag, 1, 0, 217 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 218 CAS_PAGE_SIZE, 1, CAS_PAGE_SIZE, 0, NULL, NULL, &sc->sc_rdmatag); 219 if (error != 0) 220 goto fail_ptag; 221 222 error = bus_dma_tag_create(sc->sc_pdmatag, 1, 0, 223 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 224 MCLBYTES * CAS_NTXSEGS, CAS_NTXSEGS, MCLBYTES, 225 BUS_DMA_ALLOCNOW, NULL, NULL, &sc->sc_tdmatag); 226 if (error != 0) 227 goto fail_rtag; 228 229 error = bus_dma_tag_create(sc->sc_pdmatag, CAS_TX_DESC_ALIGN, 0, 230 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 231 sizeof(struct cas_control_data), 1, 232 sizeof(struct cas_control_data), 0, 233 NULL, NULL, &sc->sc_cdmatag); 234 if (error != 0) 235 goto fail_ttag; 236 237 /* 238 * Allocate the control data structures, create and load the 239 * DMA map for it. 240 */ 241 if ((error = bus_dmamem_alloc(sc->sc_cdmatag, 242 (void **)&sc->sc_control_data, 243 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 244 &sc->sc_cddmamap)) != 0) { 245 device_printf(sc->sc_dev, 246 "unable to allocate control data, error = %d\n", error); 247 goto fail_ctag; 248 } 249 250 sc->sc_cddma = 0; 251 if ((error = bus_dmamap_load(sc->sc_cdmatag, sc->sc_cddmamap, 252 sc->sc_control_data, sizeof(struct cas_control_data), 253 cas_cddma_callback, sc, 0)) != 0 || sc->sc_cddma == 0) { 254 device_printf(sc->sc_dev, 255 "unable to load control data DMA map, error = %d\n", 256 error); 257 goto fail_cmem; 258 } 259 260 /* 261 * Initialize the transmit job descriptors. 262 */ 263 STAILQ_INIT(&sc->sc_txfreeq); 264 STAILQ_INIT(&sc->sc_txdirtyq); 265 266 /* 267 * Create the transmit buffer DMA maps. 268 */ 269 error = ENOMEM; 270 for (i = 0; i < CAS_TXQUEUELEN; i++) { 271 txs = &sc->sc_txsoft[i]; 272 txs->txs_mbuf = NULL; 273 txs->txs_ndescs = 0; 274 if ((error = bus_dmamap_create(sc->sc_tdmatag, 0, 275 &txs->txs_dmamap)) != 0) { 276 device_printf(sc->sc_dev, 277 "unable to create TX DMA map %d, error = %d\n", 278 i, error); 279 goto fail_txd; 280 } 281 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 282 } 283 284 /* 285 * Allocate the receive buffers, create and load the DMA maps 286 * for them. 287 */ 288 for (i = 0; i < CAS_NRXDESC; i++) { 289 if ((error = bus_dmamem_alloc(sc->sc_rdmatag, 290 &sc->sc_rxdsoft[i].rxds_buf, BUS_DMA_WAITOK, 291 &sc->sc_rxdsoft[i].rxds_dmamap)) != 0) { 292 device_printf(sc->sc_dev, 293 "unable to allocate RX buffer %d, error = %d\n", 294 i, error); 295 goto fail_rxmem; 296 } 297 298 sc->sc_rxdptr = i; 299 sc->sc_rxdsoft[i].rxds_paddr = 0; 300 if ((error = bus_dmamap_load(sc->sc_rdmatag, 301 sc->sc_rxdsoft[i].rxds_dmamap, sc->sc_rxdsoft[i].rxds_buf, 302 CAS_PAGE_SIZE, cas_rxdma_callback, sc, 0)) != 0 || 303 sc->sc_rxdsoft[i].rxds_paddr == 0) { 304 device_printf(sc->sc_dev, 305 "unable to load RX DMA map %d, error = %d\n", 306 i, error); 307 goto fail_rxmap; 308 } 309 } 310 311 CAS_WRITE_4(sc, CAS_PCS_DATAPATH, CAS_PCS_DATAPATH_MII); 312 313 cas_mifinit(sc); 314 315 /* 316 * Look for an external PHY. 317 */ 318 error = ENXIO; 319 v = CAS_READ_4(sc, CAS_MIF_CONF); 320 if ((v & CAS_MIF_CONF_MDI1) != 0) { 321 v |= CAS_MIF_CONF_PHY_SELECT; 322 CAS_WRITE_4(sc, CAS_MIF_CONF, v); 323 switch (sc->sc_variant) { 324 default: 325 sc->sc_phyad = -1; 326 break; 327 } 328 error = mii_phy_probe(sc->sc_dev, &sc->sc_miibus, 329 cas_mediachange, cas_mediastatus); 330 } 331 332 /* 333 * Fall back on an internal PHY if no external PHY was found. 334 */ 335 if (error != 0 && (v & CAS_MIF_CONF_MDI0) != 0) { 336 v &= ~CAS_MIF_CONF_PHY_SELECT; 337 CAS_WRITE_4(sc, CAS_MIF_CONF, v); 338 switch (sc->sc_variant) { 339 default: 340 sc->sc_phyad = -1; 341 break; 342 } 343 error = mii_phy_probe(sc->sc_dev, &sc->sc_miibus, 344 cas_mediachange, cas_mediastatus); 345 } 346 347 /* 348 * Try the external PCS SERDES if we didn't find any PHYs. 349 */ 350 if (error != 0) { 351 CAS_WRITE_4(sc, CAS_PCS_DATAPATH, CAS_PCS_DATAPATH_SERDES); 352 CAS_WRITE_4(sc, CAS_PCS_SERDES_CTRL, CAS_PCS_SERDES_CTRL_ESD); 353 CAS_WRITE_4(sc, CAS_PCS_CONF_EN, CAS_PCS_CONF_EN); 354 sc->sc_flags |= CAS_SERDES; 355 sc->sc_phyad = CAS_PHYAD_EXTERNAL; 356 error = mii_phy_probe(sc->sc_dev, &sc->sc_miibus, 357 cas_mediachange, cas_mediastatus); 358 } 359 360 if (error != 0) { 361 device_printf(sc->sc_dev, "PHY probe failed: %d\n", error); 362 goto fail_rxmap; 363 } 364 sc->sc_mii = device_get_softc(sc->sc_miibus); 365 366 /* 367 * From this point forward, the attachment cannot fail. A failure 368 * before this point releases all resources that may have been 369 * allocated. 370 */ 371 372 /* Announce FIFO sizes. */ 373 v = CAS_READ_4(sc, CAS_TX_FIFO_SIZE); 374 device_printf(sc->sc_dev, "%ukB RX FIFO, %ukB TX FIFO\n", 375 CAS_RX_FIFO_SIZE / 1024, v / 16); 376 377 /* Attach the interface. */ 378 ether_ifattach(ifp, sc->sc_enaddr); 379 380 /* 381 * Tell the upper layer(s) we support long frames/checksum offloads. 382 */ 383 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 384 ifp->if_capabilities = IFCAP_VLAN_MTU; 385 if ((sc->sc_flags & CAS_NO_CSUM) == 0) { 386 ifp->if_capabilities |= IFCAP_HWCSUM; 387 ifp->if_hwassist = CAS_CSUM_FEATURES; 388 } 389 ifp->if_capenable = ifp->if_capabilities; 390 391 return (0); 392 393 /* 394 * Free any resources we've allocated during the failed attach 395 * attempt. Do this in reverse order and fall through. 396 */ 397 fail_rxmap: 398 for (i = 0; i < CAS_NRXDESC; i++) 399 if (sc->sc_rxdsoft[i].rxds_paddr != 0) 400 bus_dmamap_unload(sc->sc_rdmatag, 401 sc->sc_rxdsoft[i].rxds_dmamap); 402 fail_rxmem: 403 for (i = 0; i < CAS_NRXDESC; i++) 404 if (sc->sc_rxdsoft[i].rxds_buf != NULL) 405 bus_dmamem_free(sc->sc_rdmatag, 406 sc->sc_rxdsoft[i].rxds_buf, 407 sc->sc_rxdsoft[i].rxds_dmamap); 408 fail_txd: 409 for (i = 0; i < CAS_TXQUEUELEN; i++) 410 if (sc->sc_txsoft[i].txs_dmamap != NULL) 411 bus_dmamap_destroy(sc->sc_tdmatag, 412 sc->sc_txsoft[i].txs_dmamap); 413 bus_dmamap_unload(sc->sc_cdmatag, sc->sc_cddmamap); 414 fail_cmem: 415 bus_dmamem_free(sc->sc_cdmatag, sc->sc_control_data, 416 sc->sc_cddmamap); 417 fail_ctag: 418 bus_dma_tag_destroy(sc->sc_cdmatag); 419 fail_ttag: 420 bus_dma_tag_destroy(sc->sc_tdmatag); 421 fail_rtag: 422 bus_dma_tag_destroy(sc->sc_rdmatag); 423 fail_ptag: 424 bus_dma_tag_destroy(sc->sc_pdmatag); 425 fail_ifnet: 426 if_free(ifp); 427 return (error); 428} 429 430static void 431cas_detach(struct cas_softc *sc) 432{ 433 struct ifnet *ifp = sc->sc_ifp; 434 int i; 435 436 CAS_LOCK(sc); 437 cas_stop(ifp); 438 CAS_UNLOCK(sc); 439 callout_drain(&sc->sc_tick_ch); 440 callout_drain(&sc->sc_rx_ch); 441 ether_ifdetach(ifp); 442 if_free(ifp); 443 device_delete_child(sc->sc_dev, sc->sc_miibus); 444 445 for (i = 0; i < CAS_NRXDESC; i++) 446 if (sc->sc_rxdsoft[i].rxds_dmamap != NULL) 447 bus_dmamap_sync(sc->sc_rdmatag, 448 sc->sc_rxdsoft[i].rxds_dmamap, 449 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 450 for (i = 0; i < CAS_NRXDESC; i++) 451 if (sc->sc_rxdsoft[i].rxds_paddr != 0) 452 bus_dmamap_unload(sc->sc_rdmatag, 453 sc->sc_rxdsoft[i].rxds_dmamap); 454 for (i = 0; i < CAS_NRXDESC; i++) 455 if (sc->sc_rxdsoft[i].rxds_buf != NULL) 456 bus_dmamem_free(sc->sc_rdmatag, 457 sc->sc_rxdsoft[i].rxds_buf, 458 sc->sc_rxdsoft[i].rxds_dmamap); 459 for (i = 0; i < CAS_TXQUEUELEN; i++) 460 if (sc->sc_txsoft[i].txs_dmamap != NULL) 461 bus_dmamap_destroy(sc->sc_tdmatag, 462 sc->sc_txsoft[i].txs_dmamap); 463 CAS_CDSYNC(sc, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 464 bus_dmamap_unload(sc->sc_cdmatag, sc->sc_cddmamap); 465 bus_dmamem_free(sc->sc_cdmatag, sc->sc_control_data, 466 sc->sc_cddmamap); 467 bus_dma_tag_destroy(sc->sc_cdmatag); 468 bus_dma_tag_destroy(sc->sc_tdmatag); 469 bus_dma_tag_destroy(sc->sc_rdmatag); 470 bus_dma_tag_destroy(sc->sc_pdmatag); 471} 472 473static void 474cas_suspend(struct cas_softc *sc) 475{ 476 struct ifnet *ifp = sc->sc_ifp; 477 478 CAS_LOCK(sc); 479 cas_stop(ifp); 480 CAS_UNLOCK(sc); 481} 482 483static void 484cas_resume(struct cas_softc *sc) 485{ 486 struct ifnet *ifp = sc->sc_ifp; 487 488 CAS_LOCK(sc); 489 /* 490 * On resume all registers have to be initialized again like 491 * after power-on. 492 */ 493 sc->sc_flags &= ~CAS_INITED; 494 if (ifp->if_flags & IFF_UP) 495 cas_init_locked(sc); 496 CAS_UNLOCK(sc); 497} 498 499static inline void 500cas_rxcksum(struct mbuf *m, uint16_t cksum) 501{ 502 struct ether_header *eh; 503 struct ip *ip; 504 struct udphdr *uh; 505 uint16_t *opts; 506 int32_t hlen, len, pktlen; 507 uint32_t temp32; 508 509 pktlen = m->m_pkthdr.len; 510 if (pktlen < sizeof(struct ether_header) + sizeof(struct ip)) 511 return; 512 eh = mtod(m, struct ether_header *); 513 if (eh->ether_type != htons(ETHERTYPE_IP)) 514 return; 515 ip = (struct ip *)(eh + 1); 516 if (ip->ip_v != IPVERSION) 517 return; 518 519 hlen = ip->ip_hl << 2; 520 pktlen -= sizeof(struct ether_header); 521 if (hlen < sizeof(struct ip)) 522 return; 523 if (ntohs(ip->ip_len) < hlen) 524 return; 525 if (ntohs(ip->ip_len) != pktlen) 526 return; 527 if (ip->ip_off & htons(IP_MF | IP_OFFMASK)) 528 return; /* Cannot handle fragmented packet. */ 529 530 switch (ip->ip_p) { 531 case IPPROTO_TCP: 532 if (pktlen < (hlen + sizeof(struct tcphdr))) 533 return; 534 break; 535 case IPPROTO_UDP: 536 if (pktlen < (hlen + sizeof(struct udphdr))) 537 return; 538 uh = (struct udphdr *)((uint8_t *)ip + hlen); 539 if (uh->uh_sum == 0) 540 return; /* no checksum */ 541 break; 542 default: 543 return; 544 } 545 546 cksum = ~cksum; 547 /* checksum fixup for IP options */ 548 len = hlen - sizeof(struct ip); 549 if (len > 0) { 550 opts = (uint16_t *)(ip + 1); 551 for (; len > 0; len -= sizeof(uint16_t), opts++) { 552 temp32 = cksum - *opts; 553 temp32 = (temp32 >> 16) + (temp32 & 65535); 554 cksum = temp32 & 65535; 555 } 556 } 557 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 558 m->m_pkthdr.csum_data = cksum; 559} 560 561static void 562cas_cddma_callback(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 563{ 564 struct cas_softc *sc = xsc; 565 566 if (error != 0) 567 return; 568 if (nsegs != 1) 569 panic("%s: bad control buffer segment count", __func__); 570 sc->sc_cddma = segs[0].ds_addr; 571} 572 573static void 574cas_rxdma_callback(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 575{ 576 struct cas_softc *sc = xsc; 577 578 if (error != 0) 579 return; 580 if (nsegs != 1) 581 panic("%s: bad RX buffer segment count", __func__); 582 sc->sc_rxdsoft[sc->sc_rxdptr].rxds_paddr = segs[0].ds_addr; 583} 584 585static void 586cas_tick(void *arg) 587{ 588 struct cas_softc *sc = arg; 589 struct ifnet *ifp; 590 uint32_t v; 591 592 CAS_LOCK_ASSERT(sc, MA_OWNED); 593 594 ifp = sc->sc_ifp; 595 /* 596 * Unload collision and error counters. 597 */ 598 ifp->if_collisions += 599 CAS_READ_4(sc, CAS_MAC_NORM_COLL_CNT) + 600 CAS_READ_4(sc, CAS_MAC_FIRST_COLL_CNT); 601 v = CAS_READ_4(sc, CAS_MAC_EXCESS_COLL_CNT) + 602 CAS_READ_4(sc, CAS_MAC_LATE_COLL_CNT); 603 ifp->if_collisions += v; 604 ifp->if_oerrors += v; 605 ifp->if_ierrors += 606 CAS_READ_4(sc, CAS_MAC_RX_LEN_ERR_CNT) + 607 CAS_READ_4(sc, CAS_MAC_RX_ALIGN_ERR) + 608 CAS_READ_4(sc, CAS_MAC_RX_CRC_ERR_CNT) + 609 CAS_READ_4(sc, CAS_MAC_RX_CODE_VIOL); 610 611 /* 612 * Then clear the hardware counters. 613 */ 614 CAS_WRITE_4(sc, CAS_MAC_NORM_COLL_CNT, 0); 615 CAS_WRITE_4(sc, CAS_MAC_FIRST_COLL_CNT, 0); 616 CAS_WRITE_4(sc, CAS_MAC_EXCESS_COLL_CNT, 0); 617 CAS_WRITE_4(sc, CAS_MAC_LATE_COLL_CNT, 0); 618 CAS_WRITE_4(sc, CAS_MAC_RX_LEN_ERR_CNT, 0); 619 CAS_WRITE_4(sc, CAS_MAC_RX_ALIGN_ERR, 0); 620 CAS_WRITE_4(sc, CAS_MAC_RX_CRC_ERR_CNT, 0); 621 CAS_WRITE_4(sc, CAS_MAC_RX_CODE_VIOL, 0); 622 623 mii_tick(sc->sc_mii); 624 625 if (cas_watchdog(sc) == EJUSTRETURN) 626 return; 627 628 callout_reset(&sc->sc_tick_ch, hz, cas_tick, sc); 629} 630 631static int 632cas_bitwait(struct cas_softc *sc, bus_addr_t r, uint32_t clr, uint32_t set) 633{ 634 int i; 635 uint32_t reg; 636 637 for (i = CAS_TRIES; i--; DELAY(100)) { 638 reg = CAS_READ_4(sc, r); 639 if ((reg & clr) == 0 && (reg & set) == set) 640 return (1); 641 } 642 return (0); 643} 644 645static void 646cas_reset(struct cas_softc *sc) 647{ 648 649#ifdef CAS_DEBUG 650 CTR2(KTR_CAS, "%s: %s", device_get_name(sc->sc_dev), __func__); 651#endif 652 /* Disable all interrupts in order to avoid spurious ones. */ 653 CAS_WRITE_4(sc, CAS_INTMASK, 0xffffffff); 654 655 cas_reset_rx(sc); 656 cas_reset_tx(sc); 657 658 /* 659 * Do a full reset modulo the result of the last auto-negotiation 660 * when using the SERDES. 661 */ 662 CAS_WRITE_4(sc, CAS_RESET, CAS_RESET_RX | CAS_RESET_TX | 663 ((sc->sc_flags & CAS_SERDES) != 0 ? CAS_RESET_PCS_DIS : 0)); 664 CAS_BARRIER(sc, CAS_RESET, 4, 665 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 666 DELAY(3000); 667 if (!cas_bitwait(sc, CAS_RESET, CAS_RESET_RX | CAS_RESET_TX, 0)) 668 device_printf(sc->sc_dev, "cannot reset device\n"); 669} 670 671static void 672cas_stop(struct ifnet *ifp) 673{ 674 struct cas_softc *sc = ifp->if_softc; 675 struct cas_txsoft *txs; 676 677#ifdef CAS_DEBUG 678 CTR2(KTR_CAS, "%s: %s", device_get_name(sc->sc_dev), __func__); 679#endif 680 681 callout_stop(&sc->sc_tick_ch); 682 callout_stop(&sc->sc_rx_ch); 683 684 /* Disable all interrupts in order to avoid spurious ones. */ 685 CAS_WRITE_4(sc, CAS_INTMASK, 0xffffffff); 686 687 cas_reset_tx(sc); 688 cas_reset_rx(sc); 689 690 /* 691 * Release any queued transmit buffers. 692 */ 693 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 694 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 695 if (txs->txs_ndescs != 0) { 696 bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap, 697 BUS_DMASYNC_POSTWRITE); 698 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap); 699 if (txs->txs_mbuf != NULL) { 700 m_freem(txs->txs_mbuf); 701 txs->txs_mbuf = NULL; 702 } 703 } 704 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 705 } 706 707 /* 708 * Mark the interface down and cancel the watchdog timer. 709 */ 710 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 711 sc->sc_flags &= ~CAS_LINK; 712 sc->sc_wdog_timer = 0; 713} 714 715static int 716cas_reset_rx(struct cas_softc *sc) 717{ 718 719 /* 720 * Resetting while DMA is in progress can cause a bus hang, so we 721 * disable DMA first. 722 */ 723 cas_disable_rx(sc); 724 CAS_WRITE_4(sc, CAS_RX_CONF, 0); 725 CAS_BARRIER(sc, CAS_RX_CONF, 4, 726 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 727 if (!cas_bitwait(sc, CAS_RX_CONF, CAS_RX_CONF_RXDMA_EN, 0)) 728 device_printf(sc->sc_dev, "cannot disable RX DMA\n"); 729 730 /* Finally, reset the ERX. */ 731 CAS_WRITE_4(sc, CAS_RESET, CAS_RESET_RX | 732 ((sc->sc_flags & CAS_SERDES) != 0 ? CAS_RESET_PCS_DIS : 0)); 733 CAS_BARRIER(sc, CAS_RESET, 4, 734 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 735 if (!cas_bitwait(sc, CAS_RESET, CAS_RESET_RX | CAS_RESET_TX, 0)) { 736 device_printf(sc->sc_dev, "cannot reset receiver\n"); 737 return (1); 738 } 739 return (0); 740} 741 742static int 743cas_reset_tx(struct cas_softc *sc) 744{ 745 746 /* 747 * Resetting while DMA is in progress can cause a bus hang, so we 748 * disable DMA first. 749 */ 750 cas_disable_tx(sc); 751 CAS_WRITE_4(sc, CAS_TX_CONF, 0); 752 CAS_BARRIER(sc, CAS_TX_CONF, 4, 753 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 754 if (!cas_bitwait(sc, CAS_TX_CONF, CAS_TX_CONF_TXDMA_EN, 0)) 755 device_printf(sc->sc_dev, "cannot disable TX DMA\n"); 756 757 /* Finally, reset the ETX. */ 758 CAS_WRITE_4(sc, CAS_RESET, CAS_RESET_TX | 759 ((sc->sc_flags & CAS_SERDES) != 0 ? CAS_RESET_PCS_DIS : 0)); 760 CAS_BARRIER(sc, CAS_RESET, 4, 761 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 762 if (!cas_bitwait(sc, CAS_RESET, CAS_RESET_RX | CAS_RESET_TX, 0)) { 763 device_printf(sc->sc_dev, "cannot reset transmitter\n"); 764 return (1); 765 } 766 return (0); 767} 768 769static int 770cas_disable_rx(struct cas_softc *sc) 771{ 772 773 CAS_WRITE_4(sc, CAS_MAC_RX_CONF, 774 CAS_READ_4(sc, CAS_MAC_RX_CONF) & ~CAS_MAC_RX_CONF_EN); 775 CAS_BARRIER(sc, CAS_MAC_RX_CONF, 4, 776 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 777 return (cas_bitwait(sc, CAS_MAC_RX_CONF, CAS_MAC_RX_CONF_EN, 0)); 778} 779 780static int 781cas_disable_tx(struct cas_softc *sc) 782{ 783 784 CAS_WRITE_4(sc, CAS_MAC_TX_CONF, 785 CAS_READ_4(sc, CAS_MAC_TX_CONF) & ~CAS_MAC_TX_CONF_EN); 786 CAS_BARRIER(sc, CAS_MAC_TX_CONF, 4, 787 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 788 return (cas_bitwait(sc, CAS_MAC_TX_CONF, CAS_MAC_TX_CONF_EN, 0)); 789} 790 791static inline void 792cas_rxcompinit(struct cas_rx_comp *rxcomp) 793{ 794 795 rxcomp->crc_word1 = 0; 796 rxcomp->crc_word2 = 0; 797 rxcomp->crc_word3 = 798 htole64(CAS_SET(ETHER_HDR_LEN + sizeof(struct ip), CAS_RC3_CSO)); 799 rxcomp->crc_word4 = htole64(CAS_RC4_ZERO); 800} 801 802static void 803cas_meminit(struct cas_softc *sc) 804{ 805 int i; 806 807 CAS_LOCK_ASSERT(sc, MA_OWNED); 808 809 /* 810 * Initialize the transmit descriptor ring. 811 */ 812 for (i = 0; i < CAS_NTXDESC; i++) { 813 sc->sc_txdescs[i].cd_flags = 0; 814 sc->sc_txdescs[i].cd_buf_ptr = 0; 815 } 816 sc->sc_txfree = CAS_MAXTXFREE; 817 sc->sc_txnext = 0; 818 sc->sc_txwin = 0; 819 820 /* 821 * Initialize the receive completion ring. 822 */ 823 for (i = 0; i < CAS_NRXCOMP; i++) 824 cas_rxcompinit(&sc->sc_rxcomps[i]); 825 sc->sc_rxcptr = 0; 826 827 /* 828 * Initialize the first receive descriptor ring. We leave 829 * the second one zeroed as we don't actually use it. 830 */ 831 for (i = 0; i < CAS_NRXDESC; i++) 832 CAS_INIT_RXDESC(sc, i, i); 833 sc->sc_rxdptr = 0; 834 835 CAS_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 836} 837 838static u_int 839cas_descsize(u_int sz) 840{ 841 842 switch (sz) { 843 case 32: 844 return (CAS_DESC_32); 845 case 64: 846 return (CAS_DESC_64); 847 case 128: 848 return (CAS_DESC_128); 849 case 256: 850 return (CAS_DESC_256); 851 case 512: 852 return (CAS_DESC_512); 853 case 1024: 854 return (CAS_DESC_1K); 855 case 2048: 856 return (CAS_DESC_2K); 857 case 4096: 858 return (CAS_DESC_4K); 859 case 8192: 860 return (CAS_DESC_8K); 861 default: 862 printf("%s: invalid descriptor ring size %d\n", __func__, sz); 863 return (CAS_DESC_32); 864 } 865} 866 867static u_int 868cas_rxcompsize(u_int sz) 869{ 870 871 switch (sz) { 872 case 128: 873 return (CAS_RX_CONF_COMP_128); 874 case 256: 875 return (CAS_RX_CONF_COMP_256); 876 case 512: 877 return (CAS_RX_CONF_COMP_512); 878 case 1024: 879 return (CAS_RX_CONF_COMP_1K); 880 case 2048: 881 return (CAS_RX_CONF_COMP_2K); 882 case 4096: 883 return (CAS_RX_CONF_COMP_4K); 884 case 8192: 885 return (CAS_RX_CONF_COMP_8K); 886 case 16384: 887 return (CAS_RX_CONF_COMP_16K); 888 case 32768: 889 return (CAS_RX_CONF_COMP_32K); 890 default: 891 printf("%s: invalid dcompletion ring size %d\n", __func__, sz); 892 return (CAS_RX_CONF_COMP_128); 893 } 894} 895 896static void 897cas_init(void *xsc) 898{ 899 struct cas_softc *sc = xsc; 900 901 CAS_LOCK(sc); 902 cas_init_locked(sc); 903 CAS_UNLOCK(sc); 904} 905 906/* 907 * Initialization of interface; set up initialization block 908 * and transmit/receive descriptor rings. 909 */ 910static void 911cas_init_locked(struct cas_softc *sc) 912{ 913 struct ifnet *ifp = sc->sc_ifp; 914 uint32_t v; 915 916 CAS_LOCK_ASSERT(sc, MA_OWNED); 917 918#ifdef CAS_DEBUG 919 CTR2(KTR_CAS, "%s: %s: calling stop", device_get_name(sc->sc_dev), 920 __func__); 921#endif 922 /* 923 * Initialization sequence. The numbered steps below correspond 924 * to the sequence outlined in section 6.3.5.1 in the Ethernet 925 * Channel Engine manual (part of the PCIO manual). 926 * See also the STP2002-STQ document from Sun Microsystems. 927 */ 928 929 /* step 1 & 2. Reset the Ethernet Channel. */ 930 cas_stop(ifp); 931 cas_reset(sc); 932#ifdef CAS_DEBUG 933 CTR2(KTR_CAS, "%s: %s: restarting", device_get_name(sc->sc_dev), 934 __func__); 935#endif 936 937 /* Re-initialize the MIF. */ 938 cas_mifinit(sc); 939 940 /* step 3. Setup data structures in host memory. */ 941 cas_meminit(sc); 942 943 /* step 4. TX MAC registers & counters */ 944 cas_init_regs(sc); 945 946 /* step 5. RX MAC registers & counters */ 947 cas_setladrf(sc); 948 949 /* step 6 & 7. Program Ring Base Addresses. */ 950 CAS_WRITE_4(sc, CAS_TX_DESC3_BASE_HI, 951 (((uint64_t)CAS_CDTXDADDR(sc, 0)) >> 32)); 952 CAS_WRITE_4(sc, CAS_TX_DESC3_BASE_LO, 953 CAS_CDTXDADDR(sc, 0) & 0xffffffff); 954 955 CAS_WRITE_4(sc, CAS_RX_COMP_BASE_HI, 956 (((uint64_t)CAS_CDRXCADDR(sc, 0)) >> 32)); 957 CAS_WRITE_4(sc, CAS_RX_COMP_BASE_LO, 958 CAS_CDRXCADDR(sc, 0) & 0xffffffff); 959 960 CAS_WRITE_4(sc, CAS_RX_DESC_BASE_HI, 961 (((uint64_t)CAS_CDRXDADDR(sc, 0)) >> 32)); 962 CAS_WRITE_4(sc, CAS_RX_DESC_BASE_LO, 963 CAS_CDRXDADDR(sc, 0) & 0xffffffff); 964 965 if ((sc->sc_flags & CAS_REG_PLUS) != 0) { 966 CAS_WRITE_4(sc, CAS_RX_DESC2_BASE_HI, 967 (((uint64_t)CAS_CDRXD2ADDR(sc, 0)) >> 32)); 968 CAS_WRITE_4(sc, CAS_RX_DESC2_BASE_LO, 969 CAS_CDRXD2ADDR(sc, 0) & 0xffffffff); 970 } 971 972#ifdef CAS_DEBUG 973 CTR5(KTR_CAS, 974 "loading TXDR %lx, RXCR %lx, RXDR %lx, RXD2R %lx, cddma %lx", 975 CAS_CDTXDADDR(sc, 0), CAS_CDRXCADDR(sc, 0), CAS_CDRXDADDR(sc, 0), 976 CAS_CDRXD2ADDR(sc, 0), sc->sc_cddma); 977#endif 978 979 /* step 8. Global Configuration & Interrupt Masks */ 980 981 /* Disable weighted round robin. */ 982 CAS_WRITE_4(sc, CAS_CAW, CAS_CAW_RR_DIS); 983 984 /* 985 * Enable infinite bursts for revisions without PCI issues if 986 * applicable. Doing so greatly improves the TX performance on 987 * !__sparc64__. 988 */ 989 CAS_WRITE_4(sc, CAS_INF_BURST, 990#if !defined(__sparc64__) 991 (sc->sc_flags & CAS_TABORT) == 0 ? CAS_INF_BURST_EN : 992#endif 993 0); 994 995 /* Set up interrupts. */ 996 CAS_WRITE_4(sc, CAS_INTMASK, 997 ~(CAS_INTR_TX_INT_ME | CAS_INTR_TX_ALL | CAS_INTR_TX_TAG_ERR | 998 CAS_INTR_RX_DONE | CAS_INTR_RX_BUF_NA | CAS_INTR_RX_TAG_ERR | 999 CAS_INTR_RX_COMP_FULL | CAS_INTR_RX_BUF_AEMPTY | 1000 CAS_INTR_RX_COMP_AFULL | CAS_INTR_RX_LEN_MMATCH | 1001 CAS_INTR_PCI_ERROR_INT 1002#ifdef CAS_DEBUG 1003 | CAS_INTR_PCS_INT | CAS_INTR_MIF 1004#endif 1005 )); 1006 CAS_WRITE_4(sc, CAS_MAC_RX_MASK, ~CAS_MAC_RX_OVERFLOW); 1007 CAS_WRITE_4(sc, CAS_MAC_TX_MASK, 1008 ~(CAS_MAC_TX_UNDERRUN | CAS_MAC_TX_MAX_PKT_ERR)); 1009#ifdef CAS_DEBUG 1010 CAS_WRITE_4(sc, CAS_MAC_CTRL_MASK, 1011 ~(CAS_MAC_CTRL_PAUSE_RCVD | CAS_MAC_CTRL_PAUSE | 1012 CAS_MAC_CTRL_NON_PAUSE)); 1013#else 1014 CAS_WRITE_4(sc, CAS_MAC_CTRL_MASK, 1015 CAS_MAC_CTRL_PAUSE_RCVD | CAS_MAC_CTRL_PAUSE | 1016 CAS_MAC_CTRL_NON_PAUSE); 1017#endif 1018 1019 /* Enable PCI error interrupts. */ 1020 CAS_WRITE_4(sc, CAS_ERROR_MASK, 1021 ~(CAS_ERROR_DTRTO | CAS_ERROR_OTHER | CAS_ERROR_DMAW_ZERO | 1022 CAS_ERROR_DMAR_ZERO | CAS_ERROR_RTRTO)); 1023 1024 /* Enable PCI error interrupts in BIM configuration. */ 1025 CAS_WRITE_4(sc, CAS_BIM_CONF, 1026 CAS_BIM_CONF_DPAR_EN | CAS_BIM_CONF_RMA_EN | CAS_BIM_CONF_RTA_EN); 1027 1028 /* 1029 * step 9. ETX Configuration: encode receive descriptor ring size, 1030 * enable DMA and disable pre-interrupt writeback completion. 1031 */ 1032 v = cas_descsize(CAS_NTXDESC) << CAS_TX_CONF_DESC3_SHFT; 1033 CAS_WRITE_4(sc, CAS_TX_CONF, v | CAS_TX_CONF_TXDMA_EN | 1034 CAS_TX_CONF_RDPP_DIS | CAS_TX_CONF_PICWB_DIS); 1035 1036 /* step 10. ERX Configuration */ 1037 1038 /* 1039 * Encode receive completion and descriptor ring sizes, set the 1040 * swivel offset. 1041 */ 1042 v = cas_rxcompsize(CAS_NRXCOMP) << CAS_RX_CONF_COMP_SHFT; 1043 v |= cas_descsize(CAS_NRXDESC) << CAS_RX_CONF_DESC_SHFT; 1044 if ((sc->sc_flags & CAS_REG_PLUS) != 0) 1045 v |= cas_descsize(CAS_NRXDESC2) << CAS_RX_CONF_DESC2_SHFT; 1046 CAS_WRITE_4(sc, CAS_RX_CONF, 1047 v | (ETHER_ALIGN << CAS_RX_CONF_SOFF_SHFT)); 1048 1049 /* Set the PAUSE thresholds. We use the maximum OFF threshold. */ 1050 CAS_WRITE_4(sc, CAS_RX_PTHRS, 1051 ((111 * 64) << CAS_RX_PTHRS_XOFF_SHFT) | 1052 ((15 * 64) << CAS_RX_PTHRS_XON_SHFT)); 1053 1054 /* RX blanking */ 1055 CAS_WRITE_4(sc, CAS_RX_BLANK, 1056 (15 << CAS_RX_BLANK_TIME_SHFT) | (5 << CAS_RX_BLANK_PKTS_SHFT)); 1057 1058 /* Set RX_COMP_AFULL threshold to half of the RX completions. */ 1059 CAS_WRITE_4(sc, CAS_RX_AEMPTY_THRS, 1060 (CAS_NRXCOMP / 2) << CAS_RX_AEMPTY_COMP_SHFT); 1061 1062 /* Initialize the RX page size register as appropriate for 8k. */ 1063 CAS_WRITE_4(sc, CAS_RX_PSZ, 1064 (CAS_RX_PSZ_8K << CAS_RX_PSZ_SHFT) | 1065 (4 << CAS_RX_PSZ_MB_CNT_SHFT) | 1066 (CAS_RX_PSZ_MB_STRD_2K << CAS_RX_PSZ_MB_STRD_SHFT) | 1067 (CAS_RX_PSZ_MB_OFF_64 << CAS_RX_PSZ_MB_OFF_SHFT)); 1068 1069 /* Disable RX random early detection. */ 1070 CAS_WRITE_4(sc, CAS_RX_RED, 0); 1071 1072 /* Zero the RX reassembly DMA table. */ 1073 for (v = 0; v <= CAS_RX_REAS_DMA_ADDR_LC; v++) { 1074 CAS_WRITE_4(sc, CAS_RX_REAS_DMA_ADDR, v); 1075 CAS_WRITE_4(sc, CAS_RX_REAS_DMA_DATA_LO, 0); 1076 CAS_WRITE_4(sc, CAS_RX_REAS_DMA_DATA_MD, 0); 1077 CAS_WRITE_4(sc, CAS_RX_REAS_DMA_DATA_HI, 0); 1078 } 1079 1080 /* Ensure the RX control FIFO and RX IPP FIFO addresses are zero. */ 1081 CAS_WRITE_4(sc, CAS_RX_CTRL_FIFO, 0); 1082 CAS_WRITE_4(sc, CAS_RX_IPP_ADDR, 0); 1083 1084 /* Finally, enable RX DMA. */ 1085 CAS_WRITE_4(sc, CAS_RX_CONF, 1086 CAS_READ_4(sc, CAS_RX_CONF) | CAS_RX_CONF_RXDMA_EN); 1087 1088 /* step 11. Configure Media. */ 1089 1090 /* step 12. RX_MAC Configuration Register */ 1091 v = CAS_READ_4(sc, CAS_MAC_RX_CONF) & ~CAS_MAC_RX_CONF_STRPPAD; 1092 v |= CAS_MAC_RX_CONF_EN | CAS_MAC_RX_CONF_STRPFCS; 1093 CAS_WRITE_4(sc, CAS_MAC_RX_CONF, 0); 1094 CAS_BARRIER(sc, CAS_MAC_RX_CONF, 4, 1095 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1096 if (!cas_bitwait(sc, CAS_MAC_RX_CONF, CAS_MAC_RX_CONF_EN, 0)) 1097 device_printf(sc->sc_dev, "cannot configure RX MAC\n"); 1098 CAS_WRITE_4(sc, CAS_MAC_RX_CONF, v); 1099 1100 /* step 13. TX_MAC Configuration Register */ 1101 v = CAS_READ_4(sc, CAS_MAC_TX_CONF); 1102 v |= CAS_MAC_TX_CONF_EN; 1103 CAS_WRITE_4(sc, CAS_MAC_TX_CONF, 0); 1104 CAS_BARRIER(sc, CAS_MAC_TX_CONF, 4, 1105 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1106 if (!cas_bitwait(sc, CAS_MAC_TX_CONF, CAS_MAC_TX_CONF_EN, 0)) 1107 device_printf(sc->sc_dev, "cannot configure TX MAC\n"); 1108 CAS_WRITE_4(sc, CAS_MAC_TX_CONF, v); 1109 1110 /* step 14. Issue Transmit Pending command. */ 1111 1112 /* step 15. Give the reciever a swift kick. */ 1113 CAS_WRITE_4(sc, CAS_RX_KICK, CAS_NRXDESC - 4); 1114 CAS_WRITE_4(sc, CAS_RX_COMP_TAIL, 0); 1115 if ((sc->sc_flags & CAS_REG_PLUS) != 0) 1116 CAS_WRITE_4(sc, CAS_RX_KICK2, CAS_NRXDESC2 - 4); 1117 1118 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1119 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1120 1121 mii_mediachg(sc->sc_mii); 1122 1123 /* Start the one second timer. */ 1124 sc->sc_wdog_timer = 0; 1125 callout_reset(&sc->sc_tick_ch, hz, cas_tick, sc); 1126} 1127 1128static int 1129cas_load_txmbuf(struct cas_softc *sc, struct mbuf **m_head) 1130{ 1131 bus_dma_segment_t txsegs[CAS_NTXSEGS]; 1132 struct cas_txsoft *txs; 1133 struct ip *ip; 1134 struct mbuf *m; 1135 uint64_t cflags; 1136 int error, nexttx, nsegs, offset, seg; 1137 1138 CAS_LOCK_ASSERT(sc, MA_OWNED); 1139 1140 /* Get a work queue entry. */ 1141 if ((txs = STAILQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1142 /* Ran out of descriptors. */ 1143 return (ENOBUFS); 1144 } 1145 1146 cflags = 0; 1147 if (((*m_head)->m_pkthdr.csum_flags & CAS_CSUM_FEATURES) != 0) { 1148 if (M_WRITABLE(*m_head) == 0) { 1149 m = m_dup(*m_head, M_DONTWAIT); 1150 m_freem(*m_head); 1151 *m_head = m; 1152 if (m == NULL) 1153 return (ENOBUFS); 1154 } 1155 offset = sizeof(struct ether_header); 1156 m = m_pullup(*m_head, offset + sizeof(struct ip)); 1157 if (m == NULL) { 1158 *m_head = NULL; 1159 return (ENOBUFS); 1160 } 1161 ip = (struct ip *)(mtod(m, caddr_t) + offset); 1162 offset += (ip->ip_hl << 2); 1163 cflags = (offset << CAS_TD_CKSUM_START_SHFT) | 1164 ((offset + m->m_pkthdr.csum_data) << 1165 CAS_TD_CKSUM_STUFF_SHFT) | CAS_TD_CKSUM_EN; 1166 *m_head = m; 1167 } 1168 1169 error = bus_dmamap_load_mbuf_sg(sc->sc_tdmatag, txs->txs_dmamap, 1170 *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT); 1171 if (error == EFBIG) { 1172 m = m_collapse(*m_head, M_DONTWAIT, CAS_NTXSEGS); 1173 if (m == NULL) { 1174 m_freem(*m_head); 1175 *m_head = NULL; 1176 return (ENOBUFS); 1177 } 1178 *m_head = m; 1179 error = bus_dmamap_load_mbuf_sg(sc->sc_tdmatag, 1180 txs->txs_dmamap, *m_head, txsegs, &nsegs, 1181 BUS_DMA_NOWAIT); 1182 if (error != 0) { 1183 m_freem(*m_head); 1184 *m_head = NULL; 1185 return (error); 1186 } 1187 } else if (error != 0) 1188 return (error); 1189 /* If nsegs is wrong then the stack is corrupt. */ 1190 KASSERT(nsegs <= CAS_NTXSEGS, 1191 ("%s: too many DMA segments (%d)", __func__, nsegs)); 1192 if (nsegs == 0) { 1193 m_freem(*m_head); 1194 *m_head = NULL; 1195 return (EIO); 1196 } 1197 1198 /* 1199 * Ensure we have enough descriptors free to describe 1200 * the packet. Note, we always reserve one descriptor 1201 * at the end of the ring as a termination point, in 1202 * order to prevent wrap-around. 1203 */ 1204 if (nsegs > sc->sc_txfree - 1) { 1205 txs->txs_ndescs = 0; 1206 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap); 1207 return (ENOBUFS); 1208 } 1209 1210 txs->txs_ndescs = nsegs; 1211 txs->txs_firstdesc = sc->sc_txnext; 1212 nexttx = txs->txs_firstdesc; 1213 for (seg = 0; seg < nsegs; seg++, nexttx = CAS_NEXTTX(nexttx)) { 1214#ifdef CAS_DEBUG 1215 CTR6(KTR_CAS, 1216 "%s: mapping seg %d (txd %d), len %lx, addr %#lx (%#lx)", 1217 __func__, seg, nexttx, txsegs[seg].ds_len, 1218 txsegs[seg].ds_addr, htole64(txsegs[seg].ds_addr)); 1219#endif 1220 sc->sc_txdescs[nexttx].cd_buf_ptr = 1221 htole64(txsegs[seg].ds_addr); 1222 KASSERT(txsegs[seg].ds_len < 1223 CAS_TD_BUF_LEN_MASK >> CAS_TD_BUF_LEN_SHFT, 1224 ("%s: segment size too large!", __func__)); 1225 sc->sc_txdescs[nexttx].cd_flags = 1226 htole64(txsegs[seg].ds_len << CAS_TD_BUF_LEN_SHFT); 1227 txs->txs_lastdesc = nexttx; 1228 } 1229 1230 /* Set EOF on the last descriptor. */ 1231#ifdef CAS_DEBUG 1232 CTR3(KTR_CAS, "%s: end of frame at segment %d, TX %d", 1233 __func__, seg, nexttx); 1234#endif 1235 sc->sc_txdescs[txs->txs_lastdesc].cd_flags |= 1236 htole64(CAS_TD_END_OF_FRAME); 1237 1238 /* Lastly set SOF on the first descriptor. */ 1239#ifdef CAS_DEBUG 1240 CTR3(KTR_CAS, "%s: start of frame at segment %d, TX %d", 1241 __func__, seg, nexttx); 1242#endif 1243 if (sc->sc_txwin += nsegs > CAS_NTXSEGS * 2 / 3) { 1244 sc->sc_txwin = 0; 1245 sc->sc_txdescs[txs->txs_firstdesc].cd_flags |= 1246 htole64(cflags | CAS_TD_START_OF_FRAME | CAS_TD_INT_ME); 1247 } else 1248 sc->sc_txdescs[txs->txs_firstdesc].cd_flags |= 1249 htole64(cflags | CAS_TD_START_OF_FRAME); 1250 1251 /* Sync the DMA map. */ 1252 bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap, 1253 BUS_DMASYNC_PREWRITE); 1254 1255#ifdef CAS_DEBUG 1256 CTR4(KTR_CAS, "%s: setting firstdesc=%d, lastdesc=%d, ndescs=%d", 1257 __func__, txs->txs_firstdesc, txs->txs_lastdesc, 1258 txs->txs_ndescs); 1259#endif 1260 STAILQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1261 STAILQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1262 txs->txs_mbuf = *m_head; 1263 1264 sc->sc_txnext = CAS_NEXTTX(txs->txs_lastdesc); 1265 sc->sc_txfree -= txs->txs_ndescs; 1266 1267 return (0); 1268} 1269 1270static void 1271cas_init_regs(struct cas_softc *sc) 1272{ 1273 int i; 1274 const u_char *laddr = IF_LLADDR(sc->sc_ifp); 1275 1276 CAS_LOCK_ASSERT(sc, MA_OWNED); 1277 1278 /* These registers are not cleared on reset. */ 1279 if ((sc->sc_flags & CAS_INITED) == 0) { 1280 /* magic values */ 1281 CAS_WRITE_4(sc, CAS_MAC_IPG0, 0); 1282 CAS_WRITE_4(sc, CAS_MAC_IPG1, 8); 1283 CAS_WRITE_4(sc, CAS_MAC_IPG2, 4); 1284 1285 /* min frame length */ 1286 CAS_WRITE_4(sc, CAS_MAC_MIN_FRAME, ETHER_MIN_LEN); 1287 /* max frame length and max burst size */ 1288 CAS_WRITE_4(sc, CAS_MAC_MAX_BF, 1289 ((ETHER_MAX_LEN_JUMBO + ETHER_VLAN_ENCAP_LEN) << 1290 CAS_MAC_MAX_BF_FRM_SHFT) | 1291 (0x2000 << CAS_MAC_MAX_BF_BST_SHFT)); 1292 1293 /* more magic values */ 1294 CAS_WRITE_4(sc, CAS_MAC_PREAMBLE_LEN, 0x7); 1295 CAS_WRITE_4(sc, CAS_MAC_JAM_SIZE, 0x4); 1296 CAS_WRITE_4(sc, CAS_MAC_ATTEMPT_LIMIT, 0x10); 1297 CAS_WRITE_4(sc, CAS_MAC_CTRL_TYPE, 0x8088); 1298 1299 /* random number seed */ 1300 CAS_WRITE_4(sc, CAS_MAC_RANDOM_SEED, 1301 ((laddr[5] << 8) | laddr[4]) & 0x3ff); 1302 1303 /* secondary MAC addresses: 0:0:0:0:0:0 */ 1304 for (i = CAS_MAC_ADDR3; i <= CAS_MAC_ADDR41; 1305 i += CAS_MAC_ADDR4 - CAS_MAC_ADDR3) 1306 CAS_WRITE_4(sc, i, 0); 1307 1308 /* MAC control address: 01:80:c2:00:00:01 */ 1309 CAS_WRITE_4(sc, CAS_MAC_ADDR42, 0x0001); 1310 CAS_WRITE_4(sc, CAS_MAC_ADDR43, 0xc200); 1311 CAS_WRITE_4(sc, CAS_MAC_ADDR44, 0x0180); 1312 1313 /* MAC filter address: 0:0:0:0:0:0 */ 1314 CAS_WRITE_4(sc, CAS_MAC_AFILTER0, 0); 1315 CAS_WRITE_4(sc, CAS_MAC_AFILTER1, 0); 1316 CAS_WRITE_4(sc, CAS_MAC_AFILTER2, 0); 1317 CAS_WRITE_4(sc, CAS_MAC_AFILTER_MASK1_2, 0); 1318 CAS_WRITE_4(sc, CAS_MAC_AFILTER_MASK0, 0); 1319 1320 /* Zero the hash table. */ 1321 for (i = CAS_MAC_HASH0; i <= CAS_MAC_HASH15; 1322 i += CAS_MAC_HASH1 - CAS_MAC_HASH0) 1323 CAS_WRITE_4(sc, i, 0); 1324 1325 sc->sc_flags |= CAS_INITED; 1326 } 1327 1328 /* Counters need to be zeroed. */ 1329 CAS_WRITE_4(sc, CAS_MAC_NORM_COLL_CNT, 0); 1330 CAS_WRITE_4(sc, CAS_MAC_FIRST_COLL_CNT, 0); 1331 CAS_WRITE_4(sc, CAS_MAC_EXCESS_COLL_CNT, 0); 1332 CAS_WRITE_4(sc, CAS_MAC_LATE_COLL_CNT, 0); 1333 CAS_WRITE_4(sc, CAS_MAC_DEFER_TMR_CNT, 0); 1334 CAS_WRITE_4(sc, CAS_MAC_PEAK_ATTEMPTS, 0); 1335 CAS_WRITE_4(sc, CAS_MAC_RX_FRAME_COUNT, 0); 1336 CAS_WRITE_4(sc, CAS_MAC_RX_LEN_ERR_CNT, 0); 1337 CAS_WRITE_4(sc, CAS_MAC_RX_ALIGN_ERR, 0); 1338 CAS_WRITE_4(sc, CAS_MAC_RX_CRC_ERR_CNT, 0); 1339 CAS_WRITE_4(sc, CAS_MAC_RX_CODE_VIOL, 0); 1340 1341 /* Set XOFF PAUSE time. */ 1342 CAS_WRITE_4(sc, CAS_MAC_SPC, 0x1BF0 << CAS_MAC_SPC_TIME_SHFT); 1343 1344 /* Set the station address. */ 1345 CAS_WRITE_4(sc, CAS_MAC_ADDR0, (laddr[4] << 8) | laddr[5]); 1346 CAS_WRITE_4(sc, CAS_MAC_ADDR1, (laddr[2] << 8) | laddr[3]); 1347 CAS_WRITE_4(sc, CAS_MAC_ADDR2, (laddr[0] << 8) | laddr[1]); 1348 1349 /* Enable MII outputs. */ 1350 CAS_WRITE_4(sc, CAS_MAC_XIF_CONF, CAS_MAC_XIF_CONF_TX_OE); 1351} 1352 1353static void 1354cas_start(struct ifnet *ifp) 1355{ 1356 struct cas_softc *sc = ifp->if_softc; 1357 1358 CAS_LOCK(sc); 1359 cas_start_locked(ifp); 1360 CAS_UNLOCK(sc); 1361} 1362 1363static inline void 1364cas_txkick(struct cas_softc *sc) 1365{ 1366 1367 /* 1368 * Update the TX kick register. This register has to point to the 1369 * descriptor after the last valid one and for optimum performance 1370 * should be incremented in multiples of 4 (the DMA engine fetches/ 1371 * updates descriptors in batches of 4). 1372 */ 1373#ifdef CAS_DEBUG 1374 CTR3(KTR_CAS, "%s: %s: kicking TX %d", 1375 device_get_name(sc->sc_dev), __func__, sc->sc_txnext); 1376#endif 1377 CAS_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1378 CAS_WRITE_4(sc, CAS_TX_KICK3, sc->sc_txnext); 1379} 1380 1381static void 1382cas_start_locked(struct ifnet *ifp) 1383{ 1384 struct cas_softc *sc = ifp->if_softc; 1385 struct mbuf *m; 1386 int kicked, ntx; 1387 1388 CAS_LOCK_ASSERT(sc, MA_OWNED); 1389 1390 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1391 IFF_DRV_RUNNING || (sc->sc_flags & CAS_LINK) == 0) 1392 return; 1393 1394#ifdef CAS_DEBUG 1395 CTR4(KTR_CAS, "%s: %s: txfree %d, txnext %d", 1396 device_get_name(sc->sc_dev), __func__, sc->sc_txfree, 1397 sc->sc_txnext); 1398#endif 1399 ntx = 0; 1400 kicked = 0; 1401 for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && sc->sc_txfree > 1;) { 1402 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 1403 if (m == NULL) 1404 break; 1405 if (cas_load_txmbuf(sc, &m) != 0) { 1406 if (m == NULL) 1407 break; 1408 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1409 IFQ_DRV_PREPEND(&ifp->if_snd, m); 1410 break; 1411 } 1412 if ((sc->sc_txnext % 4) == 0) { 1413 cas_txkick(sc); 1414 kicked = 1; 1415 } else 1416 kicked = 0; 1417 ntx++; 1418 BPF_MTAP(ifp, m); 1419 } 1420 1421 if (ntx > 0) { 1422 if (kicked == 0) 1423 cas_txkick(sc); 1424#ifdef CAS_DEBUG 1425 CTR2(KTR_CAS, "%s: packets enqueued, OWN on %d", 1426 device_get_name(sc->sc_dev), sc->sc_txnext); 1427#endif 1428 1429 /* Set a watchdog timer in case the chip flakes out. */ 1430 sc->sc_wdog_timer = 5; 1431#ifdef CAS_DEBUG 1432 CTR3(KTR_CAS, "%s: %s: watchdog %d", 1433 device_get_name(sc->sc_dev), __func__, 1434 sc->sc_wdog_timer); 1435#endif 1436 } 1437} 1438 1439static void 1440cas_tint(struct cas_softc *sc) 1441{ 1442 struct ifnet *ifp = sc->sc_ifp; 1443 struct cas_txsoft *txs; 1444 int progress; 1445 uint32_t txlast; 1446#ifdef CAS_DEBUG 1447 int i; 1448 1449 CAS_LOCK_ASSERT(sc, MA_OWNED); 1450 1451 CTR2(KTR_CAS, "%s: %s", device_get_name(sc->sc_dev), __func__); 1452#endif 1453 1454 /* 1455 * Go through our TX list and free mbufs for those 1456 * frames that have been transmitted. 1457 */ 1458 progress = 0; 1459 CAS_CDSYNC(sc, BUS_DMASYNC_POSTREAD); 1460 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1461#ifdef CAS_DEBUG 1462 if ((ifp->if_flags & IFF_DEBUG) != 0) { 1463 printf(" txsoft %p transmit chain:\n", txs); 1464 for (i = txs->txs_firstdesc;; i = CAS_NEXTTX(i)) { 1465 printf("descriptor %d: ", i); 1466 printf("cd_flags: 0x%016llx\t", 1467 (long long)le64toh( 1468 sc->sc_txdescs[i].cd_flags)); 1469 printf("cd_buf_ptr: 0x%016llx\n", 1470 (long long)le64toh( 1471 sc->sc_txdescs[i].cd_buf_ptr)); 1472 if (i == txs->txs_lastdesc) 1473 break; 1474 } 1475 } 1476#endif 1477 1478 /* 1479 * In theory, we could harvest some descriptors before 1480 * the ring is empty, but that's a bit complicated. 1481 * 1482 * CAS_TX_COMPn points to the last descriptor 1483 * processed + 1. 1484 */ 1485 txlast = CAS_READ_4(sc, CAS_TX_COMP3); 1486#ifdef CAS_DEBUG 1487 CTR4(KTR_CAS, "%s: txs->txs_firstdesc = %d, " 1488 "txs->txs_lastdesc = %d, txlast = %d", 1489 __func__, txs->txs_firstdesc, txs->txs_lastdesc, txlast); 1490#endif 1491 if (txs->txs_firstdesc <= txs->txs_lastdesc) { 1492 if ((txlast >= txs->txs_firstdesc) && 1493 (txlast <= txs->txs_lastdesc)) 1494 break; 1495 } else { 1496 /* Ick -- this command wraps. */ 1497 if ((txlast >= txs->txs_firstdesc) || 1498 (txlast <= txs->txs_lastdesc)) 1499 break; 1500 } 1501 1502#ifdef CAS_DEBUG 1503 CTR1(KTR_CAS, "%s: releasing a descriptor", __func__); 1504#endif 1505 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1506 1507 sc->sc_txfree += txs->txs_ndescs; 1508 1509 bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap, 1510 BUS_DMASYNC_POSTWRITE); 1511 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap); 1512 if (txs->txs_mbuf != NULL) { 1513 m_freem(txs->txs_mbuf); 1514 txs->txs_mbuf = NULL; 1515 } 1516 1517 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1518 1519 ifp->if_opackets++; 1520 progress = 1; 1521 } 1522 1523#ifdef CAS_DEBUG 1524 CTR4(KTR_CAS, "%s: CAS_TX_STATE_MACHINE %x CAS_TX_DESC_BASE %llx " 1525 "CAS_TX_COMP3 %x", 1526 __func__, CAS_READ_4(sc, CAS_TX_STATE_MACHINE), 1527 ((long long)CAS_READ_4(sc, CAS_TX_DESC_BASE_HI3) << 32) | 1528 CAS_READ_4(sc, CAS_TX_DESC_BASE_LO3), 1529 CAS_READ_4(sc, CAS_TX_COMP3)); 1530#endif 1531 1532 if (progress) { 1533 if (sc->sc_txfree == CAS_NTXDESC - 1) 1534 sc->sc_txwin = 0; 1535 1536 /* 1537 * We freed some descriptors, so reset IFF_DRV_OACTIVE 1538 * and restart. 1539 */ 1540 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1541 if (STAILQ_EMPTY(&sc->sc_txdirtyq)) 1542 sc->sc_wdog_timer = 0; 1543 cas_start_locked(ifp); 1544 } 1545 1546#ifdef CAS_DEBUG 1547 CTR3(KTR_CAS, "%s: %s: watchdog %d", 1548 device_get_name(sc->sc_dev), __func__, sc->sc_wdog_timer); 1549#endif 1550} 1551 1552static void 1553cas_rint_timeout(void *arg) 1554{ 1555 struct cas_softc *sc = arg; 1556 1557 CAS_LOCK_ASSERT(sc, MA_OWNED); 1558 1559 cas_rint(sc); 1560} 1561 1562static void 1563cas_rint(struct cas_softc *sc) 1564{ 1565 struct cas_rxdsoft *rxds, *rxds2; 1566 struct ifnet *ifp = sc->sc_ifp; 1567 struct mbuf *m, *m2; 1568 uint64_t word1, word2, word3, word4; 1569 uint32_t rxhead; 1570 u_int idx, idx2, len, off, skip; 1571 1572 CAS_LOCK_ASSERT(sc, MA_OWNED); 1573 1574 callout_stop(&sc->sc_rx_ch); 1575 1576#ifdef CAS_DEBUG 1577 CTR2(KTR_CAS, "%s: %s", device_get_name(sc->sc_dev), __func__); 1578#endif 1579 1580#define PRINTWORD(n, delimiter) \ 1581 printf("word ## n: 0x%016llx%c", (long long)word ## n, delimiter) 1582 1583#define SKIPASSERT(n) \ 1584 KASSERT(sc->sc_rxcomps[sc->sc_rxcptr].crc_word ## n == 0, \ 1585 ("%s: word ## n not 0", __func__)) 1586 1587#define WORDTOH(n) \ 1588 word ## n = le64toh(sc->sc_rxcomps[sc->sc_rxcptr].crc_word ## n) 1589 1590 /* 1591 * Read the completion head register once. This limits 1592 * how long the following loop can execute. 1593 */ 1594 rxhead = CAS_READ_4(sc, CAS_RX_COMP_HEAD); 1595#ifdef CAS_DEBUG 1596 CTR4(KTR_CAS, "%s: sc->sc_rxcptr %d, sc->sc_rxdptr %d, head %d", 1597 __func__, sc->rxcptr, sc->sc_rxdptr, rxhead); 1598#endif 1599 skip = 0; 1600 CAS_CDSYNC(sc, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1601 for (; sc->sc_rxcptr != rxhead; 1602 sc->sc_rxcptr = CAS_NEXTRXCOMP(sc->sc_rxcptr)) { 1603 if (skip != 0) { 1604 SKIPASSERT(1); 1605 SKIPASSERT(2); 1606 SKIPASSERT(3); 1607 1608 --skip; 1609 goto skip; 1610 } 1611 1612 WORDTOH(1); 1613 WORDTOH(2); 1614 WORDTOH(3); 1615 WORDTOH(4); 1616 1617#ifdef CAS_DEBUG 1618 if ((ifp->if_flags & IFF_DEBUG) != 0) { 1619 printf(" completion %d: ", sc->sc_rxcptr); 1620 PRINTWORD(1, '\t'); 1621 PRINTWORD(2, '\t'); 1622 PRINTWORD(3, '\t'); 1623 PRINTWORD(4, '\n'); 1624 } 1625#endif 1626 1627 if (__predict_false( 1628 (word1 & CAS_RC1_TYPE_MASK) == CAS_RC1_TYPE_HW || 1629 (word4 & CAS_RC4_ZERO) != 0)) { 1630 /* 1631 * The descriptor is still marked as owned, although 1632 * it is supposed to have completed. This has been 1633 * observed on some machines. Just exiting here 1634 * might leave the packet sitting around until another 1635 * one arrives to trigger a new interrupt, which is 1636 * generally undesirable, so set up a timeout. 1637 */ 1638 callout_reset(&sc->sc_rx_ch, CAS_RXOWN_TICKS, 1639 cas_rint_timeout, sc); 1640 break; 1641 } 1642 1643 if (__predict_false( 1644 (word4 & (CAS_RC4_BAD | CAS_RC4_LEN_MMATCH)) != 0)) { 1645 ifp->if_ierrors++; 1646 device_printf(sc->sc_dev, 1647 "receive error: CRC error\n"); 1648 continue; 1649 } 1650 1651 KASSERT(CAS_GET(word1, CAS_RC1_DATA_SIZE) == 0 || 1652 CAS_GET(word2, CAS_RC2_HDR_SIZE) == 0, 1653 ("%s: data and header present", __func__)); 1654 KASSERT((word1 & CAS_RC1_SPLIT_PKT) == 0 || 1655 CAS_GET(word2, CAS_RC2_HDR_SIZE) == 0, 1656 ("%s: split and header present", __func__)); 1657 KASSERT(CAS_GET(word1, CAS_RC1_DATA_SIZE) == 0 || 1658 (word1 & CAS_RC1_RELEASE_HDR) == 0, 1659 ("%s: data present but header release", __func__)); 1660 KASSERT(CAS_GET(word2, CAS_RC2_HDR_SIZE) == 0 || 1661 (word1 & CAS_RC1_RELEASE_DATA) == 0, 1662 ("%s: header present but data release", __func__)); 1663 1664 if ((len = CAS_GET(word2, CAS_RC2_HDR_SIZE)) != 0) { 1665 idx = CAS_GET(word2, CAS_RC2_HDR_INDEX); 1666 off = CAS_GET(word2, CAS_RC2_HDR_OFF); 1667#ifdef CAS_DEBUG 1668 CTR4(KTR_CAS, "%s: hdr at idx %d, off %d, len %d", 1669 __func__, idx, off, len); 1670#endif 1671 rxds = &sc->sc_rxdsoft[idx]; 1672 MGETHDR(m, M_DONTWAIT, MT_DATA); 1673 if (m != NULL) { 1674 refcount_acquire(&rxds->rxds_refcount); 1675 bus_dmamap_sync(sc->sc_rdmatag, 1676 rxds->rxds_dmamap, BUS_DMASYNC_POSTREAD); 1677 MEXTADD(m, (caddr_t)rxds->rxds_buf + 1678 off * 256 + ETHER_ALIGN, len, cas_free, 1679#if __FreeBSD_version < 800016 1680 rxds, 1681#else 1682 sc, (void *)(uintptr_t)idx, 1683#endif 1684 M_RDONLY, EXT_NET_DRV); 1685 if ((m->m_flags & M_EXT) == 0) { 1686 m_freem(m); 1687 m = NULL; 1688 } 1689 } 1690 if (m != NULL) { 1691 m->m_pkthdr.rcvif = ifp; 1692 m->m_pkthdr.len = m->m_len = len; 1693 ifp->if_ipackets++; 1694 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 1695 cas_rxcksum(m, CAS_GET(word4, 1696 CAS_RC4_TCP_CSUM)); 1697 /* Pass it on. */ 1698 CAS_UNLOCK(sc); 1699 (*ifp->if_input)(ifp, m); 1700 CAS_LOCK(sc); 1701 } else 1702 ifp->if_ierrors++; 1703 1704 if ((word1 & CAS_RC1_RELEASE_HDR) != 0 && 1705 refcount_release(&rxds->rxds_refcount) != 0) 1706 cas_add_rxdesc(sc, idx); 1707 } else if ((len = CAS_GET(word1, CAS_RC1_DATA_SIZE)) != 0) { 1708 idx = CAS_GET(word1, CAS_RC1_DATA_INDEX); 1709 off = CAS_GET(word1, CAS_RC1_DATA_OFF); 1710#ifdef CAS_DEBUG 1711 CTR4(KTR_CAS, "%s: data at idx %d, off %d, len %d", 1712 __func__, idx, off, len); 1713#endif 1714 rxds = &sc->sc_rxdsoft[idx]; 1715 MGETHDR(m, M_DONTWAIT, MT_DATA); 1716 if (m != NULL) { 1717 refcount_acquire(&rxds->rxds_refcount); 1718 off += ETHER_ALIGN; 1719 m->m_len = min(CAS_PAGE_SIZE - off, len); 1720 bus_dmamap_sync(sc->sc_rdmatag, 1721 rxds->rxds_dmamap, BUS_DMASYNC_POSTREAD); 1722 MEXTADD(m, (caddr_t)rxds->rxds_buf + off, 1723 m->m_len, cas_free, 1724#if __FreeBSD_version < 800016 1725 rxds, 1726#else 1727 sc, (void *)(uintptr_t)idx, 1728#endif 1729 M_RDONLY, EXT_NET_DRV); 1730 if ((m->m_flags & M_EXT) == 0) { 1731 m_freem(m); 1732 m = NULL; 1733 } 1734 } 1735 idx2 = 0; 1736 rxds2 = NULL; 1737 if ((word1 & CAS_RC1_SPLIT_PKT) != 0) { 1738 KASSERT((word1 & CAS_RC1_RELEASE_NEXT) != 0, 1739 ("%s: split but no release next", 1740 __func__)); 1741 1742 idx2 = CAS_GET(word2, CAS_RC2_NEXT_INDEX); 1743#ifdef CAS_DEBUG 1744 CTR2(KTR_CAS, "%s: split at idx %d", 1745 __func__, idx2); 1746#endif 1747 rxds2 = &sc->sc_rxdsoft[idx2]; 1748 MGET(m2, M_DONTWAIT, MT_DATA); 1749 if (m2 != NULL) { 1750 refcount_acquire( 1751 &rxds2->rxds_refcount); 1752 m2->m_len = len - m->m_len; 1753 bus_dmamap_sync(sc->sc_rdmatag, 1754 rxds2->rxds_dmamap, 1755 BUS_DMASYNC_POSTREAD); 1756 MEXTADD(m2, (caddr_t)rxds2->rxds_buf, 1757 m2->m_len, cas_free, 1758#if __FreeBSD_version < 800016 1759 rxds2, 1760#else 1761 sc, (void *)(uintptr_t)idx2, 1762#endif 1763 M_RDONLY, EXT_NET_DRV); 1764 if ((m2->m_flags & M_EXT) == 0) { 1765 m_freem(m2); 1766 m2 = NULL; 1767 } 1768 } 1769 if (m2 != NULL) 1770 m->m_next = m2; 1771 else { 1772 m_freem(m); 1773 m = NULL; 1774 } 1775 } 1776 if (m != NULL) { 1777 m->m_pkthdr.rcvif = ifp; 1778 m->m_pkthdr.len = len; 1779 ifp->if_ipackets++; 1780 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 1781 cas_rxcksum(m, CAS_GET(word4, 1782 CAS_RC4_TCP_CSUM)); 1783 /* Pass it on. */ 1784 CAS_UNLOCK(sc); 1785 (*ifp->if_input)(ifp, m); 1786 CAS_LOCK(sc); 1787 } else 1788 ifp->if_ierrors++; 1789 1790 if ((word1 & CAS_RC1_RELEASE_DATA) != 0 && 1791 refcount_release(&rxds->rxds_refcount) != 0) 1792 cas_add_rxdesc(sc, idx); 1793 if ((word1 & CAS_RC1_SPLIT_PKT) != 0 && 1794 refcount_release(&rxds2->rxds_refcount) != 0) 1795 cas_add_rxdesc(sc, idx2); 1796 } 1797 1798 skip = CAS_GET(word1, CAS_RC1_SKIP); 1799 1800 skip: 1801 cas_rxcompinit(&sc->sc_rxcomps[sc->sc_rxcptr]); 1802 } 1803 CAS_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1804 CAS_WRITE_4(sc, CAS_RX_COMP_TAIL, sc->sc_rxcptr); 1805 1806#undef PRINTWORD 1807#undef SKIPASSERT 1808#undef WORDTOH 1809 1810#ifdef CAS_DEBUG 1811 CTR4(KTR_CAS, "%s: done sc->sc_rxcptr %d, sc->sc_rxdptr %d, head %d", 1812 __func__, sc->rxcptr, sc->sc_rxdptr, 1813 CAS_READ_4(sc, CAS_RX_COMP_HEAD)); 1814#endif 1815} 1816 1817static void 1818cas_free(void *arg1, void *arg2) 1819{ 1820 struct cas_rxdsoft *rxds; 1821 struct cas_softc *sc; 1822 u_int idx, locked; 1823 1824#if __FreeBSD_version < 800016 1825 rxds = arg2; 1826 sc = rxds->rxds_sc; 1827 idx = rxds->rxds_idx; 1828#else 1829 sc = arg1; 1830 idx = (uintptr_t)arg2; 1831 rxds = &sc->sc_rxdsoft[idx]; 1832#endif 1833 if (refcount_release(&rxds->rxds_refcount) == 0) 1834 return; 1835 1836 /* 1837 * NB: this function can be called via m_freem(9) within 1838 * this driver! 1839 */ 1840 if ((locked = CAS_LOCK_OWNED(sc)) == 0) 1841 CAS_LOCK(sc); 1842 cas_add_rxdesc(sc, idx); 1843 if (locked == 0) 1844 CAS_UNLOCK(sc); 1845} 1846 1847static inline void 1848cas_add_rxdesc(struct cas_softc *sc, u_int idx) 1849{ 1850 1851 CAS_LOCK_ASSERT(sc, MA_OWNED); 1852 1853 bus_dmamap_sync(sc->sc_rdmatag, sc->sc_rxdsoft[idx].rxds_dmamap, 1854 BUS_DMASYNC_PREREAD); 1855 CAS_UPDATE_RXDESC(sc, sc->sc_rxdptr, idx); 1856 sc->sc_rxdptr = CAS_NEXTRXDESC(sc->sc_rxdptr); 1857 1858 /* 1859 * Update the RX kick register. This register has to point to the 1860 * descriptor after the last valid one (before the current batch) 1861 * and for optimum performance should be incremented in multiples 1862 * of 4 (the DMA engine fetches/updates descriptors in batches of 4). 1863 */ 1864 if ((sc->sc_rxdptr % 4) == 0) { 1865 CAS_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1866 CAS_WRITE_4(sc, CAS_RX_KICK, 1867 (sc->sc_rxdptr + CAS_NRXDESC - 4) & CAS_NRXDESC_MASK); 1868 } 1869} 1870 1871static void 1872cas_eint(struct cas_softc *sc, u_int status) 1873{ 1874 1875 sc->sc_ifp->if_ierrors++; 1876 1877 device_printf(sc->sc_dev, "%s: status 0x%x", __func__, status); 1878 if ((status & CAS_INTR_PCI_ERROR_INT) != 0) { 1879 status = CAS_READ_4(sc, CAS_ERROR_STATUS); 1880 printf(", PCI bus error 0x%x", status); 1881 if ((status & CAS_ERROR_OTHER) != 0) { 1882 status = pci_read_config(sc->sc_dev, PCIR_STATUS, 2); 1883 printf(", PCI status 0x%x", status); 1884 pci_write_config(sc->sc_dev, PCIR_STATUS, status, 2); 1885 } 1886 } 1887 printf("\n"); 1888 1889 cas_init_locked(sc); 1890 cas_start_locked(sc->sc_ifp); 1891} 1892 1893static void 1894cas_intr(void *v) 1895{ 1896 struct cas_softc *sc = v; 1897 uint32_t status, status2; 1898 1899 status = CAS_READ_4(sc, CAS_STATUS); 1900 if (__predict_false((status & CAS_INTR_SUMMARY) == 0)) 1901 return; 1902 1903 CAS_LOCK(sc); 1904 1905#ifdef CAS_DEBUG 1906 CTR4(KTR_CAS, "%s: %s: cplt %x, status %x", 1907 device_get_name(sc->sc_dev), __func__, 1908 (status >> CAS_STATUS_TX_COMP3_SHIFT), (u_int)status); 1909 1910 /* 1911 * PCS interrupts must be cleared, otherwise no traffic is passed! 1912 */ 1913 if ((status & CAS_INTR_PCS_INT) != 0) { 1914 status2 = 1915 CAS_READ_4(sc, CAS_PCS_INTR_STATUS) | 1916 CAS_READ_4(sc, CAS_PCS_INTR_STATUS); 1917 if ((status2 & CAS_PCS_INTR_LINK) != 0) 1918 device_printf(sc->sc_dev, 1919 "%s: PCS link status changed\n", __func__); 1920 } 1921 if ((status & CAS_MAC_CTRL_STATUS) != 0) { 1922 status2 = CAS_READ_4(sc, CAS_MAC_CTRL_STATUS); 1923 if ((status2 & CAS_MAC_CTRL_PAUSE) != 0) 1924 device_printf(sc->sc_dev, 1925 "%s: PAUSE received (PAUSE time %d slots)\n", 1926 __func__, 1927 (status2 & CAS_MAC_CTRL_STATUS_PT_MASK) >> 1928 CAS_MAC_CTRL_STATUS_PT_SHFT); 1929 if ((status2 & CAS_MAC_CTRL_PAUSE) != 0) 1930 device_printf(sc->sc_dev, 1931 "%s: transited to PAUSE state\n", __func__); 1932 if ((status2 & CAS_MAC_CTRL_NON_PAUSE) != 0) 1933 device_printf(sc->sc_dev, 1934 "%s: transited to non-PAUSE state\n", __func__); 1935 } 1936 if ((status & CAS_INTR_MIF) != 0) 1937 device_printf(sc->sc_dev, "%s: MIF interrupt\n", __func__); 1938#endif 1939 1940 if (__predict_false((status & 1941 (CAS_INTR_TX_TAG_ERR | CAS_INTR_RX_TAG_ERR | 1942 CAS_INTR_RX_LEN_MMATCH | CAS_INTR_PCI_ERROR_INT)) != 0)) { 1943 cas_eint(sc, status); 1944 CAS_UNLOCK(sc); 1945 return; 1946 } 1947 1948 if (__predict_false(status & CAS_INTR_TX_MAC_INT)) { 1949 status2 = CAS_READ_4(sc, CAS_MAC_TX_STATUS); 1950 if ((status2 & 1951 (CAS_MAC_TX_UNDERRUN | CAS_MAC_TX_MAX_PKT_ERR)) != 0) 1952 sc->sc_ifp->if_oerrors++; 1953 else if ((status2 & ~CAS_MAC_TX_FRAME_XMTD) != 0) 1954 device_printf(sc->sc_dev, 1955 "MAC TX fault, status %x\n", status2); 1956 } 1957 1958 if (__predict_false(status & CAS_INTR_RX_MAC_INT)) { 1959 status2 = CAS_READ_4(sc, CAS_MAC_RX_STATUS); 1960 if ((status2 & CAS_MAC_RX_OVERFLOW) != 0) 1961 sc->sc_ifp->if_ierrors++; 1962 else if ((status2 & ~CAS_MAC_RX_FRAME_RCVD) != 0) 1963 device_printf(sc->sc_dev, 1964 "MAC RX fault, status %x\n", status2); 1965 } 1966 1967 if ((status & 1968 (CAS_INTR_RX_DONE | CAS_INTR_RX_BUF_NA | CAS_INTR_RX_COMP_FULL | 1969 CAS_INTR_RX_BUF_AEMPTY | CAS_INTR_RX_COMP_AFULL)) != 0) { 1970 cas_rint(sc); 1971 if (__predict_false((status & 1972 (CAS_INTR_RX_BUF_NA | CAS_INTR_RX_COMP_FULL | 1973 CAS_INTR_RX_BUF_AEMPTY | CAS_INTR_RX_COMP_AFULL)) != 0)) 1974 device_printf(sc->sc_dev, 1975 "RX fault, status %x\n", status); 1976 } 1977 1978 if ((status & 1979 (CAS_INTR_TX_INT_ME | CAS_INTR_TX_ALL | CAS_INTR_TX_DONE)) != 0) 1980 cas_tint(sc); 1981 1982 CAS_UNLOCK(sc); 1983} 1984 1985static int 1986cas_watchdog(struct cas_softc *sc) 1987{ 1988 struct ifnet *ifp = sc->sc_ifp; 1989 1990 CAS_LOCK_ASSERT(sc, MA_OWNED); 1991 1992#ifdef CAS_DEBUG 1993 CTR4(KTR_CAS, 1994 "%s: CAS_RX_CONFIG %x CAS_MAC_RX_STATUS %x CAS_MAC_RX_CONFIG %x", 1995 __func__, CAS_READ_4(sc, CAS_RX_CONFIG), 1996 CAS_READ_4(sc, CAS_MAC_RX_STATUS), 1997 CAS_READ_4(sc, CAS_MAC_RX_CONFIG)); 1998 CTR4(KTR_CAS, 1999 "%s: CAS_TX_CONFIG %x CAS_MAC_TX_STATUS %x CAS_MAC_TX_CONFIG %x", 2000 __func__, CAS_READ_4(sc, CAS_TX_CONFIG), 2001 CAS_READ_4(sc, CAS_MAC_TX_STATUS), 2002 CAS_READ_4(sc, CAS_MAC_TX_CONFIG)); 2003#endif 2004 2005 if (sc->sc_wdog_timer == 0 || --sc->sc_wdog_timer != 0) 2006 return (0); 2007 2008 if ((sc->sc_flags & CAS_LINK) != 0) 2009 device_printf(sc->sc_dev, "device timeout\n"); 2010 else if (bootverbose) 2011 device_printf(sc->sc_dev, "device timeout (no link)\n"); 2012 ++ifp->if_oerrors; 2013 2014 /* Try to get more packets going. */ 2015 cas_init_locked(sc); 2016 cas_start_locked(ifp); 2017 return (EJUSTRETURN); 2018} 2019 2020static void 2021cas_mifinit(struct cas_softc *sc) 2022{ 2023 2024 /* Configure the MIF in frame mode. */ 2025 CAS_WRITE_4(sc, CAS_MIF_CONF, 2026 CAS_READ_4(sc, CAS_MIF_CONF) & ~CAS_MIF_CONF_BB_MODE); 2027} 2028 2029/* 2030 * MII interface 2031 * 2032 * The MII interface supports at least three different operating modes: 2033 * 2034 * Bitbang mode is implemented using data, clock and output enable registers. 2035 * 2036 * Frame mode is implemented by loading a complete frame into the frame 2037 * register and polling the valid bit for completion. 2038 * 2039 * Polling mode uses the frame register but completion is indicated by 2040 * an interrupt. 2041 * 2042 */ 2043static int 2044cas_mii_readreg(device_t dev, int phy, int reg) 2045{ 2046 struct cas_softc *sc; 2047 int n; 2048 uint32_t v; 2049 2050#ifdef CAS_DEBUG_PHY 2051 printf("%s: phy %d reg %d\n", __func__, phy, reg); 2052#endif 2053 2054 sc = device_get_softc(dev); 2055 if (sc->sc_phyad != -1 && phy != sc->sc_phyad) 2056 return (0); 2057 2058 if ((sc->sc_flags & CAS_SERDES) != 0) { 2059 switch (reg) { 2060 case MII_BMCR: 2061 reg = CAS_PCS_CTRL; 2062 break; 2063 case MII_BMSR: 2064 reg = CAS_PCS_STATUS; 2065 break; 2066 case MII_PHYIDR1: 2067 case MII_PHYIDR2: 2068 return (0); 2069 case MII_ANAR: 2070 reg = CAS_PCS_ANAR; 2071 break; 2072 case MII_ANLPAR: 2073 reg = CAS_PCS_ANLPAR; 2074 break; 2075 case MII_EXTSR: 2076 return (EXTSR_1000XFDX | EXTSR_1000XHDX); 2077 default: 2078 device_printf(sc->sc_dev, 2079 "%s: unhandled register %d\n", __func__, reg); 2080 return (0); 2081 } 2082 return (CAS_READ_4(sc, reg)); 2083 } 2084 2085 /* Construct the frame command. */ 2086 v = CAS_MIF_FRAME_READ | 2087 (phy << CAS_MIF_FRAME_PHY_SHFT) | 2088 (reg << CAS_MIF_FRAME_REG_SHFT); 2089 2090 CAS_WRITE_4(sc, CAS_MIF_FRAME, v); 2091 CAS_BARRIER(sc, CAS_MIF_FRAME, 4, 2092 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2093 for (n = 0; n < 100; n++) { 2094 DELAY(1); 2095 v = CAS_READ_4(sc, CAS_MIF_FRAME); 2096 if (v & CAS_MIF_FRAME_TA_LSB) 2097 return (v & CAS_MIF_FRAME_DATA); 2098 } 2099 2100 device_printf(sc->sc_dev, "%s: timed out\n", __func__); 2101 return (0); 2102} 2103 2104static int 2105cas_mii_writereg(device_t dev, int phy, int reg, int val) 2106{ 2107 struct cas_softc *sc; 2108 int n; 2109 uint32_t v; 2110 2111#ifdef CAS_DEBUG_PHY 2112 printf("%s: phy %d reg %d val %x\n", phy, reg, val, __func__); 2113#endif 2114 2115 sc = device_get_softc(dev); 2116 if (sc->sc_phyad != -1 && phy != sc->sc_phyad) 2117 return (0); 2118 2119 if ((sc->sc_flags & CAS_SERDES) != 0) { 2120 switch (reg) { 2121 case MII_BMSR: 2122 reg = CAS_PCS_STATUS; 2123 break; 2124 case MII_BMCR: 2125 reg = CAS_PCS_CTRL; 2126 if ((val & CAS_PCS_CTRL_RESET) == 0) 2127 break; 2128 CAS_WRITE_4(sc, CAS_PCS_CTRL, val); 2129 CAS_BARRIER(sc, CAS_PCS_CTRL, 4, 2130 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2131 if (!cas_bitwait(sc, CAS_PCS_CTRL, 2132 CAS_PCS_CTRL_RESET, 0)) 2133 device_printf(sc->sc_dev, 2134 "cannot reset PCS\n"); 2135 /* FALLTHROUGH */ 2136 case MII_ANAR: 2137 CAS_WRITE_4(sc, CAS_PCS_CONF, 0); 2138 CAS_BARRIER(sc, CAS_PCS_CONF, 4, 2139 BUS_SPACE_BARRIER_WRITE); 2140 CAS_WRITE_4(sc, CAS_PCS_ANAR, val); 2141 CAS_WRITE_4(sc, CAS_PCS_SERDES_CTRL, 2142 CAS_PCS_SERDES_CTRL_ESD); 2143 CAS_WRITE_4(sc, CAS_PCS_CONF, 2144 CAS_PCS_CONF_EN); 2145 return (0); 2146 case MII_ANLPAR: 2147 reg = CAS_PCS_ANLPAR; 2148 break; 2149 default: 2150 device_printf(sc->sc_dev, 2151 "%s: unhandled register %d\n", __func__, reg); 2152 return (0); 2153 } 2154 CAS_WRITE_4(sc, reg, val); 2155 return (0); 2156 } 2157 2158 /* Construct the frame command. */ 2159 v = CAS_MIF_FRAME_WRITE | 2160 (phy << CAS_MIF_FRAME_PHY_SHFT) | 2161 (reg << CAS_MIF_FRAME_REG_SHFT) | 2162 (val & CAS_MIF_FRAME_DATA); 2163 2164 CAS_WRITE_4(sc, CAS_MIF_FRAME, v); 2165 CAS_BARRIER(sc, CAS_MIF_FRAME, 4, 2166 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2167 for (n = 0; n < 100; n++) { 2168 DELAY(1); 2169 v = CAS_READ_4(sc, CAS_MIF_FRAME); 2170 if (v & CAS_MIF_FRAME_TA_LSB) 2171 return (1); 2172 } 2173 2174 device_printf(sc->sc_dev, "%s: timed out\n", __func__); 2175 return (0); 2176} 2177 2178static void 2179cas_mii_statchg(device_t dev) 2180{ 2181 struct cas_softc *sc; 2182 struct ifnet *ifp; 2183 int gigabit; 2184 uint32_t rxcfg, txcfg, v; 2185 2186 sc = device_get_softc(dev); 2187 ifp = sc->sc_ifp; 2188 2189 CAS_LOCK_ASSERT(sc, MA_OWNED); 2190 2191#ifdef CAS_DEBUG 2192 if ((ifp->if_flags & IFF_DEBUG) != 0) 2193 device_printf(sc->sc_dev, "%s: status change: PHY = %d\n", 2194 __func__, sc->sc_phyad); 2195#endif 2196 2197 if ((sc->sc_mii->mii_media_status & IFM_ACTIVE) != 0 && 2198 IFM_SUBTYPE(sc->sc_mii->mii_media_active) != IFM_NONE) 2199 sc->sc_flags |= CAS_LINK; 2200 else 2201 sc->sc_flags &= ~CAS_LINK; 2202 2203 switch (IFM_SUBTYPE(sc->sc_mii->mii_media_active)) { 2204 case IFM_1000_SX: 2205 case IFM_1000_LX: 2206 case IFM_1000_CX: 2207 case IFM_1000_T: 2208 gigabit = 1; 2209 break; 2210 default: 2211 gigabit = 0; 2212 } 2213 2214 /* 2215 * The configuration done here corresponds to the steps F) and 2216 * G) and as far as enabling of RX and TX MAC goes also step H) 2217 * of the initialization sequence outlined in section 11.2.1 of 2218 * the Cassini+ ASIC Specification. 2219 */ 2220 2221 rxcfg = CAS_READ_4(sc, CAS_MAC_RX_CONF); 2222 rxcfg &= ~(CAS_MAC_RX_CONF_EN | CAS_MAC_RX_CONF_CARR); 2223 txcfg = CAS_MAC_TX_CONF_EN_IPG0 | CAS_MAC_TX_CONF_NGU | 2224 CAS_MAC_TX_CONF_NGUL; 2225 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0) 2226 txcfg |= CAS_MAC_TX_CONF_ICARR | CAS_MAC_TX_CONF_ICOLLIS; 2227 else if (gigabit != 0) { 2228 rxcfg |= CAS_MAC_RX_CONF_CARR; 2229 txcfg |= CAS_MAC_TX_CONF_CARR; 2230 } 2231 CAS_WRITE_4(sc, CAS_MAC_TX_CONF, 0); 2232 CAS_BARRIER(sc, CAS_MAC_TX_CONF, 4, 2233 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2234 if (!cas_bitwait(sc, CAS_MAC_TX_CONF, CAS_MAC_TX_CONF_EN, 0)) 2235 device_printf(sc->sc_dev, "cannot disable TX MAC\n"); 2236 CAS_WRITE_4(sc, CAS_MAC_TX_CONF, txcfg); 2237 CAS_WRITE_4(sc, CAS_MAC_RX_CONF, 0); 2238 CAS_BARRIER(sc, CAS_MAC_RX_CONF, 4, 2239 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2240 if (!cas_bitwait(sc, CAS_MAC_RX_CONF, CAS_MAC_RX_CONF_EN, 0)) 2241 device_printf(sc->sc_dev, "cannot disable RX MAC\n"); 2242 CAS_WRITE_4(sc, CAS_MAC_RX_CONF, rxcfg); 2243 2244 v = CAS_READ_4(sc, CAS_MAC_CTRL_CONF) & 2245 ~(CAS_MAC_CTRL_CONF_TXP | CAS_MAC_CTRL_CONF_RXP); 2246#ifdef notyet 2247 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & 2248 IFM_ETH_RXPAUSE) != 0) 2249 v |= CAS_MAC_CTRL_CONF_RXP; 2250 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & 2251 IFM_ETH_TXPAUSE) != 0) 2252 v |= CAS_MAC_CTRL_CONF_TXP; 2253#endif 2254 CAS_WRITE_4(sc, CAS_MAC_CTRL_CONF, v); 2255 2256 /* 2257 * All supported chips have a bug causing incorrect checksum 2258 * to be calculated when letting them strip the FCS in half- 2259 * duplex mode. In theory we could disable FCS stripping and 2260 * manually adjust the checksum accordingly. It seems to make 2261 * more sense to optimze for the common case and just disable 2262 * hardware checksumming in half-duplex mode though. 2263 */ 2264 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) == 0) { 2265 ifp->if_capenable &= ~IFCAP_HWCSUM; 2266 ifp->if_hwassist = 0; 2267 } else if ((sc->sc_flags & CAS_NO_CSUM) == 0) { 2268 ifp->if_capenable = ifp->if_capabilities; 2269 ifp->if_hwassist = CAS_CSUM_FEATURES; 2270 } 2271 2272 if (sc->sc_variant == CAS_SATURN) { 2273 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) == 0) 2274 /* silicon bug workaround */ 2275 CAS_WRITE_4(sc, CAS_MAC_PREAMBLE_LEN, 0x41); 2276 else 2277 CAS_WRITE_4(sc, CAS_MAC_PREAMBLE_LEN, 0x7); 2278 } 2279 2280 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) == 0 && 2281 gigabit != 0) 2282 CAS_WRITE_4(sc, CAS_MAC_SLOT_TIME, 2283 CAS_MAC_SLOT_TIME_CARR); 2284 else 2285 CAS_WRITE_4(sc, CAS_MAC_SLOT_TIME, 2286 CAS_MAC_SLOT_TIME_NORM); 2287 2288 /* XIF Configuration */ 2289 v = CAS_MAC_XIF_CONF_TX_OE | CAS_MAC_XIF_CONF_LNKLED; 2290 if ((sc->sc_flags & CAS_SERDES) == 0) { 2291 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) == 0) 2292 v |= CAS_MAC_XIF_CONF_NOECHO; 2293 v |= CAS_MAC_XIF_CONF_BUF_OE; 2294 } 2295 if (gigabit != 0) 2296 v |= CAS_MAC_XIF_CONF_GMII; 2297 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0) 2298 v |= CAS_MAC_XIF_CONF_FDXLED; 2299 CAS_WRITE_4(sc, CAS_MAC_XIF_CONF, v); 2300 2301 if ((sc->sc_ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 2302 (sc->sc_flags & CAS_LINK) != 0) { 2303 CAS_WRITE_4(sc, CAS_MAC_TX_CONF, 2304 txcfg | CAS_MAC_TX_CONF_EN); 2305 CAS_WRITE_4(sc, CAS_MAC_RX_CONF, 2306 rxcfg | CAS_MAC_RX_CONF_EN); 2307 } 2308} 2309 2310static int 2311cas_mediachange(struct ifnet *ifp) 2312{ 2313 struct cas_softc *sc = ifp->if_softc; 2314 int error; 2315 2316 /* XXX add support for serial media. */ 2317 2318 CAS_LOCK(sc); 2319 error = mii_mediachg(sc->sc_mii); 2320 CAS_UNLOCK(sc); 2321 return (error); 2322} 2323 2324static void 2325cas_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2326{ 2327 struct cas_softc *sc = ifp->if_softc; 2328 2329 CAS_LOCK(sc); 2330 if ((ifp->if_flags & IFF_UP) == 0) { 2331 CAS_UNLOCK(sc); 2332 return; 2333 } 2334 2335 mii_pollstat(sc->sc_mii); 2336 ifmr->ifm_active = sc->sc_mii->mii_media_active; 2337 ifmr->ifm_status = sc->sc_mii->mii_media_status; 2338 CAS_UNLOCK(sc); 2339} 2340 2341static int 2342cas_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2343{ 2344 struct cas_softc *sc = ifp->if_softc; 2345 struct ifreq *ifr = (struct ifreq *)data; 2346 int error; 2347 2348 error = 0; 2349 switch (cmd) { 2350 case SIOCSIFFLAGS: 2351 CAS_LOCK(sc); 2352 if ((ifp->if_flags & IFF_UP) != 0) { 2353 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 2354 ((ifp->if_flags ^ sc->sc_ifflags) & 2355 (IFF_ALLMULTI | IFF_PROMISC)) != 0) 2356 cas_setladrf(sc); 2357 else 2358 cas_init_locked(sc); 2359 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2360 cas_stop(ifp); 2361 sc->sc_ifflags = ifp->if_flags; 2362 CAS_UNLOCK(sc); 2363 break; 2364 case SIOCSIFCAP: 2365 CAS_LOCK(sc); 2366 if ((sc->sc_flags & CAS_NO_CSUM) != 0) { 2367 error = EINVAL; 2368 CAS_UNLOCK(sc); 2369 break; 2370 } 2371 ifp->if_capenable = ifr->ifr_reqcap; 2372 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 2373 ifp->if_hwassist = CAS_CSUM_FEATURES; 2374 else 2375 ifp->if_hwassist = 0; 2376 CAS_UNLOCK(sc); 2377 break; 2378 case SIOCADDMULTI: 2379 case SIOCDELMULTI: 2380 CAS_LOCK(sc); 2381 cas_setladrf(sc); 2382 CAS_UNLOCK(sc); 2383 break; 2384 case SIOCSIFMTU: 2385 if ((ifr->ifr_mtu < ETHERMIN) || 2386 (ifr->ifr_mtu > ETHERMTU_JUMBO)) 2387 error = EINVAL; 2388 else 2389 ifp->if_mtu = ifr->ifr_mtu; 2390 break; 2391 case SIOCGIFMEDIA: 2392 case SIOCSIFMEDIA: 2393 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii->mii_media, cmd); 2394 break; 2395 default: 2396 error = ether_ioctl(ifp, cmd, data); 2397 break; 2398 } 2399 2400 return (error); 2401} 2402 2403static void 2404cas_setladrf(struct cas_softc *sc) 2405{ 2406 struct ifnet *ifp = sc->sc_ifp; 2407 struct ifmultiaddr *inm; 2408 int i; 2409 uint32_t hash[16]; 2410 uint32_t crc, v; 2411 2412 CAS_LOCK_ASSERT(sc, MA_OWNED); 2413 2414 /* Get the current RX configuration. */ 2415 v = CAS_READ_4(sc, CAS_MAC_RX_CONF); 2416 2417 /* 2418 * Turn off promiscuous mode, promiscuous group mode (all multicast), 2419 * and hash filter. Depending on the case, the right bit will be 2420 * enabled. 2421 */ 2422 v &= ~(CAS_MAC_RX_CONF_PROMISC | CAS_MAC_RX_CONF_HFILTER | 2423 CAS_MAC_RX_CONF_PGRP); 2424 2425 CAS_WRITE_4(sc, CAS_MAC_RX_CONF, v); 2426 CAS_BARRIER(sc, CAS_MAC_RX_CONF, 4, 2427 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2428 if (!cas_bitwait(sc, CAS_MAC_RX_CONF, CAS_MAC_RX_CONF_HFILTER, 0)) 2429 device_printf(sc->sc_dev, "cannot disable RX hash filter\n"); 2430 2431 if ((ifp->if_flags & IFF_PROMISC) != 0) { 2432 v |= CAS_MAC_RX_CONF_PROMISC; 2433 goto chipit; 2434 } 2435 if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 2436 v |= CAS_MAC_RX_CONF_PGRP; 2437 goto chipit; 2438 } 2439 2440 /* 2441 * Set up multicast address filter by passing all multicast 2442 * addresses through a crc generator, and then using the high 2443 * order 8 bits as an index into the 256 bit logical address 2444 * filter. The high order 4 bits selects the word, while the 2445 * other 4 bits select the bit within the word (where bit 0 2446 * is the MSB). 2447 */ 2448 2449 /* Clear the hash table. */ 2450 memset(hash, 0, sizeof(hash)); 2451 2452 IF_ADDR_LOCK(ifp); 2453 TAILQ_FOREACH(inm, &ifp->if_multiaddrs, ifma_link) { 2454 if (inm->ifma_addr->sa_family != AF_LINK) 2455 continue; 2456 crc = ether_crc32_le(LLADDR((struct sockaddr_dl *) 2457 inm->ifma_addr), ETHER_ADDR_LEN); 2458 2459 /* We just want the 8 most significant bits. */ 2460 crc >>= 24; 2461 2462 /* Set the corresponding bit in the filter. */ 2463 hash[crc >> 4] |= 1 << (15 - (crc & 15)); 2464 } 2465 IF_ADDR_UNLOCK(ifp); 2466 2467 v |= CAS_MAC_RX_CONF_HFILTER; 2468 2469 /* Now load the hash table into the chip (if we are using it). */ 2470 for (i = 0; i < 16; i++) 2471 CAS_WRITE_4(sc, 2472 CAS_MAC_HASH0 + i * (CAS_MAC_HASH1 - CAS_MAC_HASH0), 2473 hash[i]); 2474 2475 chipit: 2476 CAS_WRITE_4(sc, CAS_MAC_RX_CONF, v); 2477} 2478 2479static int cas_pci_attach(device_t dev); 2480static int cas_pci_detach(device_t dev); 2481static int cas_pci_probe(device_t dev); 2482static int cas_pci_resume(device_t dev); 2483static int cas_pci_suspend(device_t dev); 2484 2485static device_method_t cas_pci_methods[] = { 2486 /* Device interface */ 2487 DEVMETHOD(device_probe, cas_pci_probe), 2488 DEVMETHOD(device_attach, cas_pci_attach), 2489 DEVMETHOD(device_detach, cas_pci_detach), 2490 DEVMETHOD(device_suspend, cas_pci_suspend), 2491 DEVMETHOD(device_resume, cas_pci_resume), 2492 /* Use the suspend handler here, it is all that is required. */ 2493 DEVMETHOD(device_shutdown, cas_pci_suspend), 2494 2495 /* bus interface */ 2496 DEVMETHOD(bus_print_child, bus_generic_print_child), 2497 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 2498 2499 /* MII interface */ 2500 DEVMETHOD(miibus_readreg, cas_mii_readreg), 2501 DEVMETHOD(miibus_writereg, cas_mii_writereg), 2502 DEVMETHOD(miibus_statchg, cas_mii_statchg), 2503 2504 KOBJMETHOD_END 2505}; 2506 2507static driver_t cas_pci_driver = { 2508 "cas", 2509 cas_pci_methods, 2510 sizeof(struct cas_softc) 2511}; 2512 2513DRIVER_MODULE(cas, pci, cas_pci_driver, cas_devclass, 0, 0); 2514DRIVER_MODULE(miibus, cas, miibus_driver, miibus_devclass, 0, 0); 2515MODULE_DEPEND(cas, pci, 1, 1, 1); 2516 2517static const struct cas_pci_dev { 2518 uint32_t cpd_devid; 2519 uint8_t cpd_revid; 2520 int cpd_variant; 2521 const char *cpd_desc; 2522} const cas_pci_devlist[] = { 2523 { 0x0035100b, 0x0, CAS_SATURN, "NS DP83065 Saturn Gigabit Ethernet" }, 2524 { 0xabba108e, 0x10, CAS_CASPLUS, "Sun Cassini+ Gigabit Ethernet" }, 2525 { 0xabba108e, 0x0, CAS_CAS, "Sun Cassini Gigabit Ethernet" }, 2526 { 0, 0, 0, NULL } 2527}; 2528 2529static int 2530cas_pci_probe(device_t dev) 2531{ 2532 int i; 2533 2534 for (i = 0; cas_pci_devlist[i].cpd_desc != NULL; i++) { 2535 if (pci_get_devid(dev) == cas_pci_devlist[i].cpd_devid && 2536 pci_get_revid(dev) >= cas_pci_devlist[i].cpd_revid) { 2537 device_set_desc(dev, cas_pci_devlist[i].cpd_desc); 2538 return (BUS_PROBE_DEFAULT); 2539 } 2540 } 2541 2542 return (ENXIO); 2543} 2544 2545static struct resource_spec cas_pci_res_spec[] = { 2546 { SYS_RES_IRQ, 0, RF_SHAREABLE | RF_ACTIVE }, /* CAS_RES_INTR */ 2547 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, /* CAS_RES_MEM */ 2548 { -1, 0 } 2549}; 2550 2551static int 2552cas_pci_attach(device_t dev) 2553{ 2554 struct cas_softc *sc; 2555 int i; 2556#if !(defined(__powerpc__) || defined(__sparc64__)) 2557 u_char enaddr[4][ETHER_ADDR_LEN]; 2558 char lma[sizeof("local-mac-address")]; 2559 int found, j; 2560#endif 2561 2562 sc = device_get_softc(dev); 2563 sc->sc_variant = CAS_UNKNOWN; 2564 for (i = 0; cas_pci_devlist[i].cpd_desc != NULL; i++) { 2565 if (pci_get_devid(dev) == cas_pci_devlist[i].cpd_devid && 2566 pci_get_revid(dev) >= cas_pci_devlist[i].cpd_revid) { 2567 sc->sc_variant = cas_pci_devlist[i].cpd_variant; 2568 break; 2569 } 2570 } 2571 if (sc->sc_variant == CAS_UNKNOWN) { 2572 device_printf(dev, "unknown adaptor\n"); 2573 return (ENXIO); 2574 } 2575 2576 pci_enable_busmaster(dev); 2577 2578 sc->sc_dev = dev; 2579 if (sc->sc_variant == CAS_CAS && pci_get_devid(dev) < 0x02) 2580 /* Hardware checksumming may hang TX. */ 2581 sc->sc_flags |= CAS_NO_CSUM; 2582 if (sc->sc_variant == CAS_CASPLUS || sc->sc_variant == CAS_SATURN) 2583 sc->sc_flags |= CAS_REG_PLUS; 2584 if (sc->sc_variant == CAS_CAS || 2585 (sc->sc_variant == CAS_CASPLUS && pci_get_revid(dev) < 0x11)) 2586 sc->sc_flags |= CAS_TABORT; 2587 if (bootverbose) 2588 device_printf(dev, "flags=0x%x\n", sc->sc_flags); 2589 2590 if (bus_alloc_resources(dev, cas_pci_res_spec, sc->sc_res)) { 2591 device_printf(dev, "failed to allocate resources\n"); 2592 bus_release_resources(dev, cas_pci_res_spec, sc->sc_res); 2593 return (ENXIO); 2594 } 2595 2596 CAS_LOCK_INIT(sc, device_get_nameunit(dev)); 2597 2598#if defined(__powerpc__) || defined(__sparc64__) 2599 OF_getetheraddr(dev, sc->sc_enaddr); 2600#else 2601 /* 2602 * Dig out VPD (vital product data) and read the MAX address. 2603 * The VPD resides in the PCI Expansion ROM (PCI FCode) and 2604 * can't be accessed via the PCI capability pointer. 2605 * SUNW,pci-ce and SUNW,pci-qge use the Enhanced VPD format 2606 * described in US Patent 7149820. 2607 */ 2608 2609#define PCI_ROMHDR_SIZE 0x1c 2610#define PCI_ROMHDR_SIG 0x00 2611#define PCI_ROMHDR_SIG_MAGIC 0xaa55 /* little endian */ 2612#define PCI_ROMHDR_PTR_DATA 0x18 2613#define PCI_ROM_SIZE 0x18 2614#define PCI_ROM_SIG 0x00 2615#define PCI_ROM_SIG_MAGIC 0x52494350 /* "PCIR", endian */ 2616 /* reversed */ 2617#define PCI_ROM_VENDOR 0x04 2618#define PCI_ROM_DEVICE 0x06 2619#define PCI_ROM_PTR_VPD 0x08 2620#define PCI_VPDRES_BYTE0 0x00 2621#define PCI_VPDRES_ISLARGE(x) ((x) & 0x80) 2622#define PCI_VPDRES_LARGE_NAME(x) ((x) & 0x7f) 2623#define PCI_VPDRES_LARGE_LEN_LSB 0x01 2624#define PCI_VPDRES_LARGE_LEN_MSB 0x02 2625#define PCI_VPDRES_LARGE_SIZE 0x03 2626#define PCI_VPDRES_TYPE_ID_STRING 0x02 /* large */ 2627#define PCI_VPDRES_TYPE_VPD 0x10 /* large */ 2628#define PCI_VPD_KEY0 0x00 2629#define PCI_VPD_KEY1 0x01 2630#define PCI_VPD_LEN 0x02 2631#define PCI_VPD_SIZE 0x03 2632 2633#define CAS_ROM_READ_1(sc, offs) \ 2634 CAS_READ_1((sc), CAS_PCI_ROM_OFFSET + (offs)) 2635#define CAS_ROM_READ_2(sc, offs) \ 2636 CAS_READ_2((sc), CAS_PCI_ROM_OFFSET + (offs)) 2637#define CAS_ROM_READ_4(sc, offs) \ 2638 CAS_READ_4((sc), CAS_PCI_ROM_OFFSET + (offs)) 2639 2640 found = 0; 2641 /* Enable PCI Expansion ROM access. */ 2642 CAS_WRITE_4(sc, CAS_BIM_LDEV_OEN, 2643 CAS_BIM_LDEV_OEN_PAD | CAS_BIM_LDEV_OEN_PROM); 2644 2645 /* Read PCI Expansion ROM header. */ 2646 if (CAS_ROM_READ_2(sc, PCI_ROMHDR_SIG) != PCI_ROMHDR_SIG_MAGIC || 2647 (i = CAS_ROM_READ_2(sc, PCI_ROMHDR_PTR_DATA)) < 2648 PCI_ROMHDR_SIZE) { 2649 device_printf(dev, "unexpected PCI Expansion ROM header\n"); 2650 goto fail_prom; 2651 } 2652 2653 /* Read PCI Expansion ROM data. */ 2654 if (CAS_ROM_READ_4(sc, i + PCI_ROM_SIG) != PCI_ROM_SIG_MAGIC || 2655 CAS_ROM_READ_2(sc, i + PCI_ROM_VENDOR) != pci_get_vendor(dev) || 2656 CAS_ROM_READ_2(sc, i + PCI_ROM_DEVICE) != pci_get_device(dev) || 2657 (j = CAS_ROM_READ_2(sc, i + PCI_ROM_PTR_VPD)) < 2658 i + PCI_ROM_SIZE) { 2659 device_printf(dev, "unexpected PCI Expansion ROM data\n"); 2660 goto fail_prom; 2661 } 2662 2663 /* Read PCI VPD. */ 2664 next: 2665 if (PCI_VPDRES_ISLARGE(CAS_ROM_READ_1(sc, 2666 j + PCI_VPDRES_BYTE0)) == 0) { 2667 device_printf(dev, "no large PCI VPD\n"); 2668 goto fail_prom; 2669 } 2670 2671 i = (CAS_ROM_READ_1(sc, j + PCI_VPDRES_LARGE_LEN_MSB) << 8) | 2672 CAS_ROM_READ_1(sc, j + PCI_VPDRES_LARGE_LEN_LSB); 2673 switch (PCI_VPDRES_LARGE_NAME(CAS_ROM_READ_1(sc, 2674 j + PCI_VPDRES_BYTE0))) { 2675 case PCI_VPDRES_TYPE_ID_STRING: 2676 /* Skip identifier string. */ 2677 j += PCI_VPDRES_LARGE_SIZE + i; 2678 goto next; 2679 case PCI_VPDRES_TYPE_VPD: 2680 for (j += PCI_VPDRES_LARGE_SIZE; i > 0; 2681 i -= PCI_VPD_SIZE + CAS_ROM_READ_1(sc, j + PCI_VPD_LEN), 2682 j += PCI_VPD_SIZE + CAS_ROM_READ_1(sc, j + PCI_VPD_LEN)) { 2683 if (CAS_ROM_READ_1(sc, j + PCI_VPD_KEY0) != 'Z') 2684 /* no Enhanced VPD */ 2685 continue; 2686 if (CAS_ROM_READ_1(sc, j + PCI_VPD_SIZE) != 'I') 2687 /* no instance property */ 2688 continue; 2689 if (CAS_ROM_READ_1(sc, j + PCI_VPD_SIZE + 3) != 'B') 2690 /* no byte array */ 2691 continue; 2692 if (CAS_ROM_READ_1(sc, j + PCI_VPD_SIZE + 4) != 2693 ETHER_ADDR_LEN) 2694 continue; 2695 bus_read_region_1(sc->sc_res[CAS_RES_MEM], 2696 CAS_PCI_ROM_OFFSET + j + PCI_VPD_SIZE + 5, 2697 lma, sizeof(lma)); 2698 if (strcmp(lma, "local-mac-address") != 0) 2699 continue; 2700 bus_read_region_1(sc->sc_res[CAS_RES_MEM], 2701 CAS_PCI_ROM_OFFSET + j + PCI_VPD_SIZE + 5 + 2702 sizeof(lma), enaddr[found], 2703 sizeof(enaddr[found])); 2704 if (found++ == 4) 2705 break; 2706 } 2707 break; 2708 default: 2709 device_printf(dev, "unexpected PCI VPD\n"); 2710 goto fail_prom; 2711 } 2712 2713 fail_prom: 2714 CAS_WRITE_4(sc, CAS_BIM_LDEV_OEN, 0); 2715 2716 if (found == 0) { 2717 device_printf(dev, "could not determine Ethernet address\n"); 2718 goto fail; 2719 } 2720 i = 0; 2721 if (found > 1 && pci_get_slot(dev) < sizeof(enaddr) / sizeof(*enaddr)) 2722 i = pci_get_slot(dev); 2723 memcpy(sc->sc_enaddr, enaddr[i], ETHER_ADDR_LEN); 2724#endif 2725 2726 if (cas_attach(sc) != 0) { 2727 device_printf(dev, "could not be attached\n"); 2728 goto fail; 2729 } 2730 2731 if (bus_setup_intr(dev, sc->sc_res[CAS_RES_INTR], INTR_TYPE_NET | 2732 INTR_MPSAFE, NULL, cas_intr, sc, &sc->sc_ih) != 0) { 2733 device_printf(dev, "failed to set up interrupt\n"); 2734 cas_detach(sc); 2735 goto fail; 2736 } 2737 return (0); 2738 2739 fail: 2740 CAS_LOCK_DESTROY(sc); 2741 bus_release_resources(dev, cas_pci_res_spec, sc->sc_res); 2742 return (ENXIO); 2743} 2744 2745static int 2746cas_pci_detach(device_t dev) 2747{ 2748 struct cas_softc *sc; 2749 2750 sc = device_get_softc(dev); 2751 bus_teardown_intr(dev, sc->sc_res[CAS_RES_INTR], sc->sc_ih); 2752 cas_detach(sc); 2753 CAS_LOCK_DESTROY(sc); 2754 bus_release_resources(dev, cas_pci_res_spec, sc->sc_res); 2755 return (0); 2756} 2757 2758static int 2759cas_pci_suspend(device_t dev) 2760{ 2761 2762 cas_suspend(device_get_softc(dev)); 2763 return (0); 2764} 2765 2766static int 2767cas_pci_resume(device_t dev) 2768{ 2769 2770 cas_resume(device_get_softc(dev)); 2771 return (0); 2772} 2773