ecore_hsi.h revision 260415
1/*- 2 * Copyright (c) 2007-2013 Broadcom Corporation. All rights reserved. 3 * 4 * Eric Davis <edavis@broadcom.com> 5 * David Christensen <davidch@broadcom.com> 6 * Gary Zambrano <zambrano@broadcom.com> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. Neither the name of Broadcom Corporation nor the name of its contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written consent. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34#include <sys/cdefs.h> 35__FBSDID("$FreeBSD: head/sys/dev/bxe/ecore_hsi.h 260415 2014-01-07 22:26:20Z edavis $"); 36 37#ifndef ECORE_HSI_H 38#define ECORE_HSI_H 39 40#define FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e 41 42struct license_key { 43 uint32_t reserved[6]; 44 45 uint32_t max_iscsi_conn; 46#define LICENSE_MAX_ISCSI_TRGT_CONN_MASK 0xFFFF 47#define LICENSE_MAX_ISCSI_TRGT_CONN_SHIFT 0 48#define LICENSE_MAX_ISCSI_INIT_CONN_MASK 0xFFFF0000 49#define LICENSE_MAX_ISCSI_INIT_CONN_SHIFT 16 50 51 uint32_t reserved_a; 52 53 uint32_t max_fcoe_conn; 54#define LICENSE_MAX_FCOE_TRGT_CONN_MASK 0xFFFF 55#define LICENSE_MAX_FCOE_TRGT_CONN_SHIFT 0 56#define LICENSE_MAX_FCOE_INIT_CONN_MASK 0xFFFF0000 57#define LICENSE_MAX_FCOE_INIT_CONN_SHIFT 16 58 59 uint32_t reserved_b[4]; 60}; 61 62typedef struct license_key license_key_t; 63 64 65/**************************************************************************** 66 * Shared HW configuration * 67 ****************************************************************************/ 68#define PIN_CFG_NA 0x00000000 69#define PIN_CFG_GPIO0_P0 0x00000001 70#define PIN_CFG_GPIO1_P0 0x00000002 71#define PIN_CFG_GPIO2_P0 0x00000003 72#define PIN_CFG_GPIO3_P0 0x00000004 73#define PIN_CFG_GPIO0_P1 0x00000005 74#define PIN_CFG_GPIO1_P1 0x00000006 75#define PIN_CFG_GPIO2_P1 0x00000007 76#define PIN_CFG_GPIO3_P1 0x00000008 77#define PIN_CFG_EPIO0 0x00000009 78#define PIN_CFG_EPIO1 0x0000000a 79#define PIN_CFG_EPIO2 0x0000000b 80#define PIN_CFG_EPIO3 0x0000000c 81#define PIN_CFG_EPIO4 0x0000000d 82#define PIN_CFG_EPIO5 0x0000000e 83#define PIN_CFG_EPIO6 0x0000000f 84#define PIN_CFG_EPIO7 0x00000010 85#define PIN_CFG_EPIO8 0x00000011 86#define PIN_CFG_EPIO9 0x00000012 87#define PIN_CFG_EPIO10 0x00000013 88#define PIN_CFG_EPIO11 0x00000014 89#define PIN_CFG_EPIO12 0x00000015 90#define PIN_CFG_EPIO13 0x00000016 91#define PIN_CFG_EPIO14 0x00000017 92#define PIN_CFG_EPIO15 0x00000018 93#define PIN_CFG_EPIO16 0x00000019 94#define PIN_CFG_EPIO17 0x0000001a 95#define PIN_CFG_EPIO18 0x0000001b 96#define PIN_CFG_EPIO19 0x0000001c 97#define PIN_CFG_EPIO20 0x0000001d 98#define PIN_CFG_EPIO21 0x0000001e 99#define PIN_CFG_EPIO22 0x0000001f 100#define PIN_CFG_EPIO23 0x00000020 101#define PIN_CFG_EPIO24 0x00000021 102#define PIN_CFG_EPIO25 0x00000022 103#define PIN_CFG_EPIO26 0x00000023 104#define PIN_CFG_EPIO27 0x00000024 105#define PIN_CFG_EPIO28 0x00000025 106#define PIN_CFG_EPIO29 0x00000026 107#define PIN_CFG_EPIO30 0x00000027 108#define PIN_CFG_EPIO31 0x00000028 109 110/* EPIO definition */ 111#define EPIO_CFG_NA 0x00000000 112#define EPIO_CFG_EPIO0 0x00000001 113#define EPIO_CFG_EPIO1 0x00000002 114#define EPIO_CFG_EPIO2 0x00000003 115#define EPIO_CFG_EPIO3 0x00000004 116#define EPIO_CFG_EPIO4 0x00000005 117#define EPIO_CFG_EPIO5 0x00000006 118#define EPIO_CFG_EPIO6 0x00000007 119#define EPIO_CFG_EPIO7 0x00000008 120#define EPIO_CFG_EPIO8 0x00000009 121#define EPIO_CFG_EPIO9 0x0000000a 122#define EPIO_CFG_EPIO10 0x0000000b 123#define EPIO_CFG_EPIO11 0x0000000c 124#define EPIO_CFG_EPIO12 0x0000000d 125#define EPIO_CFG_EPIO13 0x0000000e 126#define EPIO_CFG_EPIO14 0x0000000f 127#define EPIO_CFG_EPIO15 0x00000010 128#define EPIO_CFG_EPIO16 0x00000011 129#define EPIO_CFG_EPIO17 0x00000012 130#define EPIO_CFG_EPIO18 0x00000013 131#define EPIO_CFG_EPIO19 0x00000014 132#define EPIO_CFG_EPIO20 0x00000015 133#define EPIO_CFG_EPIO21 0x00000016 134#define EPIO_CFG_EPIO22 0x00000017 135#define EPIO_CFG_EPIO23 0x00000018 136#define EPIO_CFG_EPIO24 0x00000019 137#define EPIO_CFG_EPIO25 0x0000001a 138#define EPIO_CFG_EPIO26 0x0000001b 139#define EPIO_CFG_EPIO27 0x0000001c 140#define EPIO_CFG_EPIO28 0x0000001d 141#define EPIO_CFG_EPIO29 0x0000001e 142#define EPIO_CFG_EPIO30 0x0000001f 143#define EPIO_CFG_EPIO31 0x00000020 144 145struct mac_addr { 146 uint32_t upper; 147 uint32_t lower; 148}; 149 150 151struct shared_hw_cfg { /* NVRAM Offset */ 152 /* Up to 16 bytes of NULL-terminated string */ 153 uint8_t part_num[16]; /* 0x104 */ 154 155 uint32_t config; /* 0x114 */ 156 #define SHARED_HW_CFG_MDIO_VOLTAGE_MASK 0x00000001 157 #define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT 0 158 #define SHARED_HW_CFG_MDIO_VOLTAGE_1_2V 0x00000000 159 #define SHARED_HW_CFG_MDIO_VOLTAGE_2_5V 0x00000001 160 161 #define SHARED_HW_CFG_PORT_SWAP 0x00000004 162 163 #define SHARED_HW_CFG_BEACON_WOL_EN 0x00000008 164 165 #define SHARED_HW_CFG_PCIE_GEN3_DISABLED 0x00000000 166 #define SHARED_HW_CFG_PCIE_GEN3_ENABLED 0x00000010 167 168 #define SHARED_HW_CFG_MFW_SELECT_MASK 0x00000700 169 #define SHARED_HW_CFG_MFW_SELECT_SHIFT 8 170 /* Whatever MFW found in NVM 171 (if multiple found, priority order is: NC-SI, UMP, IPMI) */ 172 #define SHARED_HW_CFG_MFW_SELECT_DEFAULT 0x00000000 173 #define SHARED_HW_CFG_MFW_SELECT_NC_SI 0x00000100 174 #define SHARED_HW_CFG_MFW_SELECT_UMP 0x00000200 175 #define SHARED_HW_CFG_MFW_SELECT_IPMI 0x00000300 176 /* Use SPIO4 as an arbiter between: 0-NC_SI, 1-IPMI 177 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */ 178 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI 0x00000400 179 /* Use SPIO4 as an arbiter between: 0-UMP, 1-IPMI 180 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */ 181 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI 0x00000500 182 /* Use SPIO4 as an arbiter between: 0-NC-SI, 1-UMP 183 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */ 184 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP 0x00000600 185 186 /* Adjust the PCIe G2 Tx amplitude driver for all Tx lanes. For 187 backwards compatibility, value of 0 is disabling this feature. 188 That means that though 0 is a valid value, it cannot be 189 configured. */ 190 #define SHARED_HW_CFG_G2_TX_DRIVE_MASK 0x0000F000 191 #define SHARED_HW_CFG_G2_TX_DRIVE_SHIFT 12 192 193 #define SHARED_HW_CFG_LED_MODE_MASK 0x000F0000 194 #define SHARED_HW_CFG_LED_MODE_SHIFT 16 195 #define SHARED_HW_CFG_LED_MAC1 0x00000000 196 #define SHARED_HW_CFG_LED_PHY1 0x00010000 197 #define SHARED_HW_CFG_LED_PHY2 0x00020000 198 #define SHARED_HW_CFG_LED_PHY3 0x00030000 199 #define SHARED_HW_CFG_LED_MAC2 0x00040000 200 #define SHARED_HW_CFG_LED_PHY4 0x00050000 201 #define SHARED_HW_CFG_LED_PHY5 0x00060000 202 #define SHARED_HW_CFG_LED_PHY6 0x00070000 203 #define SHARED_HW_CFG_LED_MAC3 0x00080000 204 #define SHARED_HW_CFG_LED_PHY7 0x00090000 205 #define SHARED_HW_CFG_LED_PHY9 0x000a0000 206 #define SHARED_HW_CFG_LED_PHY11 0x000b0000 207 #define SHARED_HW_CFG_LED_MAC4 0x000c0000 208 #define SHARED_HW_CFG_LED_PHY8 0x000d0000 209 #define SHARED_HW_CFG_LED_EXTPHY1 0x000e0000 210 #define SHARED_HW_CFG_LED_EXTPHY2 0x000f0000 211 212 #define SHARED_HW_CFG_SRIOV_MASK 0x40000000 213 #define SHARED_HW_CFG_SRIOV_DISABLED 0x00000000 214 #define SHARED_HW_CFG_SRIOV_ENABLED 0x40000000 215 216 #define SHARED_HW_CFG_ATC_MASK 0x80000000 217 #define SHARED_HW_CFG_ATC_DISABLED 0x00000000 218 #define SHARED_HW_CFG_ATC_ENABLED 0x80000000 219 220 uint32_t config2; /* 0x118 */ 221 222 #define SHARED_HW_CFG_PCIE_GEN2_MASK 0x00000100 223 #define SHARED_HW_CFG_PCIE_GEN2_SHIFT 8 224 #define SHARED_HW_CFG_PCIE_GEN2_DISABLED 0x00000000 225 #define SHARED_HW_CFG_PCIE_GEN2_ENABLED 0x00000100 226 227 #define SHARED_HW_CFG_SMBUS_TIMING_MASK 0x00001000 228 #define SHARED_HW_CFG_SMBUS_TIMING_100KHZ 0x00000000 229 #define SHARED_HW_CFG_SMBUS_TIMING_400KHZ 0x00001000 230 231 #define SHARED_HW_CFG_HIDE_PORT1 0x00002000 232 233 234 /* Output low when PERST is asserted */ 235 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_MASK 0x00008000 236 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_DISABLED 0x00000000 237 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_ENABLED 0x00008000 238 239 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_MASK 0x00070000 240 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_SHIFT 16 241 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_HW 0x00000000 242 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_0DB 0x00010000 243 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_3_5DB 0x00020000 244 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_6_0DB 0x00030000 245 246 /* The fan failure mechanism is usually related to the PHY type 247 since the power consumption of the board is determined by the PHY. 248 Currently, fan is required for most designs with SFX7101, BCM8727 249 and BCM8481. If a fan is not required for a board which uses one 250 of those PHYs, this field should be set to "Disabled". If a fan is 251 required for a different PHY type, this option should be set to 252 "Enabled". The fan failure indication is expected on SPIO5 */ 253 #define SHARED_HW_CFG_FAN_FAILURE_MASK 0x00180000 254 #define SHARED_HW_CFG_FAN_FAILURE_SHIFT 19 255 #define SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE 0x00000000 256 #define SHARED_HW_CFG_FAN_FAILURE_DISABLED 0x00080000 257 #define SHARED_HW_CFG_FAN_FAILURE_ENABLED 0x00100000 258 259 /* ASPM Power Management support */ 260 #define SHARED_HW_CFG_ASPM_SUPPORT_MASK 0x00600000 261 #define SHARED_HW_CFG_ASPM_SUPPORT_SHIFT 21 262 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_ENABLED 0x00000000 263 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_DISABLED 0x00200000 264 #define SHARED_HW_CFG_ASPM_SUPPORT_L1_DISABLED 0x00400000 265 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_DISABLED 0x00600000 266 267 /* The value of PM_TL_IGNORE_REQS (bit0) in PCI register 268 tl_control_0 (register 0x2800) */ 269 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_MASK 0x00800000 270 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_DISABLED 0x00000000 271 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_ENABLED 0x00800000 272 273 274 /* Set the MDC/MDIO access for the first external phy */ 275 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK 0x1C000000 276 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT 26 277 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE 0x00000000 278 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0 0x04000000 279 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1 0x08000000 280 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH 0x0c000000 281 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED 0x10000000 282 283 /* Set the MDC/MDIO access for the second external phy */ 284 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK 0xE0000000 285 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT 29 286 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_PHY_TYPE 0x00000000 287 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC0 0x20000000 288 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC1 0x40000000 289 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_BOTH 0x60000000 290 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SWAPPED 0x80000000 291 292 /* Max number of PF MSIX vectors */ 293 uint32_t config_3; /* 0x11C */ 294 #define SHARED_HW_CFG_PF_MSIX_MAX_NUM_MASK 0x0000007F 295 #define SHARED_HW_CFG_PF_MSIX_MAX_NUM_SHIFT 0 296 297 uint32_t ump_nc_si_config; /* 0x120 */ 298 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK 0x00000003 299 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT 0 300 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC 0x00000000 301 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY 0x00000001 302 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII 0x00000000 303 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII 0x00000002 304 305 /* Reserved bits: 226-230 */ 306 307 /* The output pin template BSC_SEL which selects the I2C for this 308 port in the I2C Mux */ 309 uint32_t board; /* 0x124 */ 310 #define SHARED_HW_CFG_E3_I2C_MUX0_MASK 0x0000003F 311 #define SHARED_HW_CFG_E3_I2C_MUX0_SHIFT 0 312 313 #define SHARED_HW_CFG_E3_I2C_MUX1_MASK 0x00000FC0 314 #define SHARED_HW_CFG_E3_I2C_MUX1_SHIFT 6 315 /* Use the PIN_CFG_XXX defines on top */ 316 #define SHARED_HW_CFG_BOARD_REV_MASK 0x00FF0000 317 #define SHARED_HW_CFG_BOARD_REV_SHIFT 16 318 319 #define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK 0x0F000000 320 #define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT 24 321 322 #define SHARED_HW_CFG_BOARD_MINOR_VER_MASK 0xF0000000 323 #define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT 28 324 325 uint32_t wc_lane_config; /* 0x128 */ 326 #define SHARED_HW_CFG_LANE_SWAP_CFG_MASK 0x0000FFFF 327 #define SHARED_HW_CFG_LANE_SWAP_CFG_SHIFT 0 328 #define SHARED_HW_CFG_LANE_SWAP_CFG_32103210 0x00001b1b 329 #define SHARED_HW_CFG_LANE_SWAP_CFG_32100123 0x00001be4 330 #define SHARED_HW_CFG_LANE_SWAP_CFG_31200213 0x000027d8 331 #define SHARED_HW_CFG_LANE_SWAP_CFG_02133120 0x0000d827 332 #define SHARED_HW_CFG_LANE_SWAP_CFG_01233210 0x0000e41b 333 #define SHARED_HW_CFG_LANE_SWAP_CFG_01230123 0x0000e4e4 334 #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000FF 335 #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0 336 #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000FF00 337 #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8 338 339 /* TX lane Polarity swap */ 340 #define SHARED_HW_CFG_TX_LANE0_POL_FLIP_ENABLED 0x00010000 341 #define SHARED_HW_CFG_TX_LANE1_POL_FLIP_ENABLED 0x00020000 342 #define SHARED_HW_CFG_TX_LANE2_POL_FLIP_ENABLED 0x00040000 343 #define SHARED_HW_CFG_TX_LANE3_POL_FLIP_ENABLED 0x00080000 344 /* TX lane Polarity swap */ 345 #define SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED 0x00100000 346 #define SHARED_HW_CFG_RX_LANE1_POL_FLIP_ENABLED 0x00200000 347 #define SHARED_HW_CFG_RX_LANE2_POL_FLIP_ENABLED 0x00400000 348 #define SHARED_HW_CFG_RX_LANE3_POL_FLIP_ENABLED 0x00800000 349 350 /* Selects the port layout of the board */ 351 #define SHARED_HW_CFG_E3_PORT_LAYOUT_MASK 0x0F000000 352 #define SHARED_HW_CFG_E3_PORT_LAYOUT_SHIFT 24 353 #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_01 0x00000000 354 #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_10 0x01000000 355 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_0123 0x02000000 356 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_1032 0x03000000 357 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_2301 0x04000000 358 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_3210 0x05000000 359}; 360 361 362/**************************************************************************** 363 * Port HW configuration * 364 ****************************************************************************/ 365struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */ 366 367 uint32_t pci_id; 368 #define PORT_HW_CFG_PCI_DEVICE_ID_MASK 0x0000FFFF 369 #define PORT_HW_CFG_PCI_DEVICE_ID_SHIFT 0 370 371 #define PORT_HW_CFG_PCI_VENDOR_ID_MASK 0xFFFF0000 372 #define PORT_HW_CFG_PCI_VENDOR_ID_SHIFT 16 373 374 uint32_t pci_sub_id; 375 #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK 0x0000FFFF 376 #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_SHIFT 0 377 378 #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK 0xFFFF0000 379 #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_SHIFT 16 380 381 uint32_t power_dissipated; 382 #define PORT_HW_CFG_POWER_DIS_D0_MASK 0x000000FF 383 #define PORT_HW_CFG_POWER_DIS_D0_SHIFT 0 384 #define PORT_HW_CFG_POWER_DIS_D1_MASK 0x0000FF00 385 #define PORT_HW_CFG_POWER_DIS_D1_SHIFT 8 386 #define PORT_HW_CFG_POWER_DIS_D2_MASK 0x00FF0000 387 #define PORT_HW_CFG_POWER_DIS_D2_SHIFT 16 388 #define PORT_HW_CFG_POWER_DIS_D3_MASK 0xFF000000 389 #define PORT_HW_CFG_POWER_DIS_D3_SHIFT 24 390 391 uint32_t power_consumed; 392 #define PORT_HW_CFG_POWER_CONS_D0_MASK 0x000000FF 393 #define PORT_HW_CFG_POWER_CONS_D0_SHIFT 0 394 #define PORT_HW_CFG_POWER_CONS_D1_MASK 0x0000FF00 395 #define PORT_HW_CFG_POWER_CONS_D1_SHIFT 8 396 #define PORT_HW_CFG_POWER_CONS_D2_MASK 0x00FF0000 397 #define PORT_HW_CFG_POWER_CONS_D2_SHIFT 16 398 #define PORT_HW_CFG_POWER_CONS_D3_MASK 0xFF000000 399 #define PORT_HW_CFG_POWER_CONS_D3_SHIFT 24 400 401 uint32_t mac_upper; 402 uint32_t mac_lower; /* 0x140 */ 403 #define PORT_HW_CFG_UPPERMAC_MASK 0x0000FFFF 404 #define PORT_HW_CFG_UPPERMAC_SHIFT 0 405 406 407 uint32_t iscsi_mac_upper; /* Upper 16 bits are always zeroes */ 408 uint32_t iscsi_mac_lower; 409 410 uint32_t rdma_mac_upper; /* Upper 16 bits are always zeroes */ 411 uint32_t rdma_mac_lower; 412 413 uint32_t serdes_config; 414 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0x0000FFFF 415 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT 0 416 417 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK 0xFFFF0000 418 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT 16 419 420 421 /* Default values: 2P-64, 4P-32 */ 422 uint32_t reserved; 423 424 uint32_t vf_config; /* 0x15C */ 425 #define PORT_HW_CFG_VF_PCI_DEVICE_ID_MASK 0xFFFF0000 426 #define PORT_HW_CFG_VF_PCI_DEVICE_ID_SHIFT 16 427 428 uint32_t mf_pci_id; /* 0x160 */ 429 #define PORT_HW_CFG_MF_PCI_DEVICE_ID_MASK 0x0000FFFF 430 #define PORT_HW_CFG_MF_PCI_DEVICE_ID_SHIFT 0 431 432 /* Controls the TX laser of the SFP+ module */ 433 uint32_t sfp_ctrl; /* 0x164 */ 434 #define PORT_HW_CFG_TX_LASER_MASK 0x000000FF 435 #define PORT_HW_CFG_TX_LASER_SHIFT 0 436 #define PORT_HW_CFG_TX_LASER_MDIO 0x00000000 437 #define PORT_HW_CFG_TX_LASER_GPIO0 0x00000001 438 #define PORT_HW_CFG_TX_LASER_GPIO1 0x00000002 439 #define PORT_HW_CFG_TX_LASER_GPIO2 0x00000003 440 #define PORT_HW_CFG_TX_LASER_GPIO3 0x00000004 441 442 /* Controls the fault module LED of the SFP+ */ 443 #define PORT_HW_CFG_FAULT_MODULE_LED_MASK 0x0000FF00 444 #define PORT_HW_CFG_FAULT_MODULE_LED_SHIFT 8 445 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO0 0x00000000 446 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO1 0x00000100 447 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO2 0x00000200 448 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO3 0x00000300 449 #define PORT_HW_CFG_FAULT_MODULE_LED_DISABLED 0x00000400 450 451 /* The output pin TX_DIS that controls the TX laser of the SFP+ 452 module. Use the PIN_CFG_XXX defines on top */ 453 uint32_t e3_sfp_ctrl; /* 0x168 */ 454 #define PORT_HW_CFG_E3_TX_LASER_MASK 0x000000FF 455 #define PORT_HW_CFG_E3_TX_LASER_SHIFT 0 456 457 /* The output pin for SFPP_TYPE which turns on the Fault module LED */ 458 #define PORT_HW_CFG_E3_FAULT_MDL_LED_MASK 0x0000FF00 459 #define PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT 8 460 461 /* The input pin MOD_ABS that indicates whether SFP+ module is 462 present or not. Use the PIN_CFG_XXX defines on top */ 463 #define PORT_HW_CFG_E3_MOD_ABS_MASK 0x00FF0000 464 #define PORT_HW_CFG_E3_MOD_ABS_SHIFT 16 465 466 /* The output pin PWRDIS_SFP_X which disable the power of the SFP+ 467 module. Use the PIN_CFG_XXX defines on top */ 468 #define PORT_HW_CFG_E3_PWR_DIS_MASK 0xFF000000 469 #define PORT_HW_CFG_E3_PWR_DIS_SHIFT 24 470 471 /* 472 * The input pin which signals module transmit fault. Use the 473 * PIN_CFG_XXX defines on top 474 */ 475 uint32_t e3_cmn_pin_cfg; /* 0x16C */ 476 #define PORT_HW_CFG_E3_TX_FAULT_MASK 0x000000FF 477 #define PORT_HW_CFG_E3_TX_FAULT_SHIFT 0 478 479 /* The output pin which reset the PHY. Use the PIN_CFG_XXX defines on 480 top */ 481 #define PORT_HW_CFG_E3_PHY_RESET_MASK 0x0000FF00 482 #define PORT_HW_CFG_E3_PHY_RESET_SHIFT 8 483 484 /* 485 * The output pin which powers down the PHY. Use the PIN_CFG_XXX 486 * defines on top 487 */ 488 #define PORT_HW_CFG_E3_PWR_DOWN_MASK 0x00FF0000 489 #define PORT_HW_CFG_E3_PWR_DOWN_SHIFT 16 490 491 /* The output pin values BSC_SEL which selects the I2C for this port 492 in the I2C Mux */ 493 #define PORT_HW_CFG_E3_I2C_MUX0_MASK 0x01000000 494 #define PORT_HW_CFG_E3_I2C_MUX1_MASK 0x02000000 495 496 497 /* 498 * The input pin I_FAULT which indicate over-current has occurred. 499 * Use the PIN_CFG_XXX defines on top 500 */ 501 uint32_t e3_cmn_pin_cfg1; /* 0x170 */ 502 #define PORT_HW_CFG_E3_OVER_CURRENT_MASK 0x000000FF 503 #define PORT_HW_CFG_E3_OVER_CURRENT_SHIFT 0 504 505 /* pause on host ring */ 506 uint32_t generic_features; /* 0x174 */ 507 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_MASK 0x00000001 508 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_SHIFT 0 509 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_DISABLED 0x00000000 510 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED 0x00000001 511 512 /* SFP+ Tx Equalization: NIC recommended and tested value is 0xBEB2 513 * LOM recommended and tested value is 0xBEB2. Using a different 514 * value means using a value not tested by BRCM 515 */ 516 uint32_t sfi_tap_values; /* 0x178 */ 517 #define PORT_HW_CFG_TX_EQUALIZATION_MASK 0x0000FFFF 518 #define PORT_HW_CFG_TX_EQUALIZATION_SHIFT 0 519 520 /* SFP+ Tx driver broadcast IDRIVER: NIC recommended and tested 521 * value is 0x2. LOM recommended and tested value is 0x2. Using a 522 * different value means using a value not tested by BRCM 523 */ 524 #define PORT_HW_CFG_TX_DRV_BROADCAST_MASK 0x000F0000 525 #define PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT 16 526 527 uint32_t reserved0[5]; /* 0x17c */ 528 529 uint32_t aeu_int_mask; /* 0x190 */ 530 531 uint32_t media_type; /* 0x194 */ 532 #define PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK 0x000000FF 533 #define PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT 0 534 535 #define PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK 0x0000FF00 536 #define PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT 8 537 538 #define PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK 0x00FF0000 539 #define PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT 16 540 541 /* 4 times 16 bits for all 4 lanes. In case external PHY is present 542 (not direct mode), those values will not take effect on the 4 XGXS 543 lanes. For some external PHYs (such as 8706 and 8726) the values 544 will be used to configure the external PHY in those cases, not 545 all 4 values are needed. */ 546 uint16_t xgxs_config_rx[4]; /* 0x198 */ 547 uint16_t xgxs_config_tx[4]; /* 0x1A0 */ 548 549 550 /* For storing FCOE mac on shared memory */ 551 uint32_t fcoe_fip_mac_upper; 552 #define PORT_HW_CFG_FCOE_UPPERMAC_MASK 0x0000ffff 553 #define PORT_HW_CFG_FCOE_UPPERMAC_SHIFT 0 554 uint32_t fcoe_fip_mac_lower; 555 556 uint32_t fcoe_wwn_port_name_upper; 557 uint32_t fcoe_wwn_port_name_lower; 558 559 uint32_t fcoe_wwn_node_name_upper; 560 uint32_t fcoe_wwn_node_name_lower; 561 562 /* wwpn for npiv enabled */ 563 uint32_t wwpn_for_npiv_config; /* 0x1C0 */ 564 #define PORT_HW_CFG_WWPN_FOR_NPIV_ENABLED_MASK 0x00000001 565 #define PORT_HW_CFG_WWPN_FOR_NPIV_ENABLED_SHIFT 0 566 #define PORT_HW_CFG_WWPN_FOR_NPIV_ENABLED_DISABLED 0x00000000 567 #define PORT_HW_CFG_WWPN_FOR_NPIV_ENABLED_ENABLED 0x00000001 568 569 /* wwpn for npiv valid addresses */ 570 uint32_t wwpn_for_npiv_valid_addresses; /* 0x1C4 */ 571 #define PORT_HW_CFG_WWPN_FOR_NPIV_ADDRESS_BITMAP_MASK 0x0000FFFF 572 #define PORT_HW_CFG_WWPN_FOR_NPIV_ADDRESS_BITMAP_SHIFT 0 573 574 struct mac_addr wwpn_for_niv_macs[16]; 575 576 /* Reserved bits: 2272-2336 For storing FCOE mac on shared memory */ 577 uint32_t Reserved1[14]; 578 579 uint32_t pf_allocation; /* 0x280 */ 580 /* number of vfs per PF, if 0 - sriov disabled */ 581 #define PORT_HW_CFG_NUMBER_OF_VFS_MASK 0x000000FF 582 #define PORT_HW_CFG_NUMBER_OF_VFS_SHIFT 0 583 584 /* Enable RJ45 magjack pair swapping on 10GBase-T PHY (0=default), 585 84833 only */ 586 uint32_t xgbt_phy_cfg; /* 0x284 */ 587 #define PORT_HW_CFG_RJ45_PAIR_SWAP_MASK 0x000000FF 588 #define PORT_HW_CFG_RJ45_PAIR_SWAP_SHIFT 0 589 590 uint32_t default_cfg; /* 0x288 */ 591 #define PORT_HW_CFG_GPIO0_CONFIG_MASK 0x00000003 592 #define PORT_HW_CFG_GPIO0_CONFIG_SHIFT 0 593 #define PORT_HW_CFG_GPIO0_CONFIG_NA 0x00000000 594 #define PORT_HW_CFG_GPIO0_CONFIG_LOW 0x00000001 595 #define PORT_HW_CFG_GPIO0_CONFIG_HIGH 0x00000002 596 #define PORT_HW_CFG_GPIO0_CONFIG_INPUT 0x00000003 597 598 #define PORT_HW_CFG_GPIO1_CONFIG_MASK 0x0000000C 599 #define PORT_HW_CFG_GPIO1_CONFIG_SHIFT 2 600 #define PORT_HW_CFG_GPIO1_CONFIG_NA 0x00000000 601 #define PORT_HW_CFG_GPIO1_CONFIG_LOW 0x00000004 602 #define PORT_HW_CFG_GPIO1_CONFIG_HIGH 0x00000008 603 #define PORT_HW_CFG_GPIO1_CONFIG_INPUT 0x0000000c 604 605 #define PORT_HW_CFG_GPIO2_CONFIG_MASK 0x00000030 606 #define PORT_HW_CFG_GPIO2_CONFIG_SHIFT 4 607 #define PORT_HW_CFG_GPIO2_CONFIG_NA 0x00000000 608 #define PORT_HW_CFG_GPIO2_CONFIG_LOW 0x00000010 609 #define PORT_HW_CFG_GPIO2_CONFIG_HIGH 0x00000020 610 #define PORT_HW_CFG_GPIO2_CONFIG_INPUT 0x00000030 611 612 #define PORT_HW_CFG_GPIO3_CONFIG_MASK 0x000000C0 613 #define PORT_HW_CFG_GPIO3_CONFIG_SHIFT 6 614 #define PORT_HW_CFG_GPIO3_CONFIG_NA 0x00000000 615 #define PORT_HW_CFG_GPIO3_CONFIG_LOW 0x00000040 616 #define PORT_HW_CFG_GPIO3_CONFIG_HIGH 0x00000080 617 #define PORT_HW_CFG_GPIO3_CONFIG_INPUT 0x000000c0 618 619 /* When KR link is required to be set to force which is not 620 KR-compliant, this parameter determine what is the trigger for it. 621 When GPIO is selected, low input will force the speed. Currently 622 default speed is 1G. In the future, it may be widen to select the 623 forced speed in with another parameter. Note when force-1G is 624 enabled, it override option 56: Link Speed option. */ 625 #define PORT_HW_CFG_FORCE_KR_ENABLER_MASK 0x00000F00 626 #define PORT_HW_CFG_FORCE_KR_ENABLER_SHIFT 8 627 #define PORT_HW_CFG_FORCE_KR_ENABLER_NOT_FORCED 0x00000000 628 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P0 0x00000100 629 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P0 0x00000200 630 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P0 0x00000300 631 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P0 0x00000400 632 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P1 0x00000500 633 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P1 0x00000600 634 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P1 0x00000700 635 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P1 0x00000800 636 #define PORT_HW_CFG_FORCE_KR_ENABLER_FORCED 0x00000900 637 /* Enable to determine with which GPIO to reset the external phy */ 638 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK 0x000F0000 639 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT 16 640 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_PHY_TYPE 0x00000000 641 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0 0x00010000 642 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0 0x00020000 643 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0 0x00030000 644 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0 0x00040000 645 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1 0x00050000 646 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1 0x00060000 647 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1 0x00070000 648 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1 0x00080000 649 650 /* Enable BAM on KR */ 651 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_MASK 0x00100000 652 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_SHIFT 20 653 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_DISABLED 0x00000000 654 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED 0x00100000 655 656 /* Enable Common Mode Sense */ 657 #define PORT_HW_CFG_ENABLE_CMS_MASK 0x00200000 658 #define PORT_HW_CFG_ENABLE_CMS_SHIFT 21 659 #define PORT_HW_CFG_ENABLE_CMS_DISABLED 0x00000000 660 #define PORT_HW_CFG_ENABLE_CMS_ENABLED 0x00200000 661 662 /* Determine the Serdes electrical interface */ 663 #define PORT_HW_CFG_NET_SERDES_IF_MASK 0x0F000000 664 #define PORT_HW_CFG_NET_SERDES_IF_SHIFT 24 665 #define PORT_HW_CFG_NET_SERDES_IF_SGMII 0x00000000 666 #define PORT_HW_CFG_NET_SERDES_IF_XFI 0x01000000 667 #define PORT_HW_CFG_NET_SERDES_IF_SFI 0x02000000 668 #define PORT_HW_CFG_NET_SERDES_IF_KR 0x03000000 669 #define PORT_HW_CFG_NET_SERDES_IF_DXGXS 0x04000000 670 #define PORT_HW_CFG_NET_SERDES_IF_KR2 0x05000000 671 672 /* SFP+ main TAP and post TAP volumes */ 673 #define PORT_HW_CFG_TAP_LEVELS_MASK 0x70000000 674 #define PORT_HW_CFG_TAP_LEVELS_SHIFT 28 675 #define PORT_HW_CFG_TAP_LEVELS_POST_15_MAIN_43 0x00000000 676 #define PORT_HW_CFG_TAP_LEVELS_POST_14_MAIN_44 0x10000000 677 #define PORT_HW_CFG_TAP_LEVELS_POST_13_MAIN_45 0x20000000 678 #define PORT_HW_CFG_TAP_LEVELS_POST_12_MAIN_46 0x30000000 679 #define PORT_HW_CFG_TAP_LEVELS_POST_11_MAIN_47 0x40000000 680 #define PORT_HW_CFG_TAP_LEVELS_POST_10_MAIN_48 0x50000000 681 682 uint32_t speed_capability_mask2; /* 0x28C */ 683 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_MASK 0x0000FFFF 684 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_SHIFT 0 685 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_FULL 0x00000001 686 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_HALF 0x00000002 687 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_HALF 0x00000004 688 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_FULL 0x00000008 689 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_1G 0x00000010 690 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_2_5G 0x00000020 691 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10G 0x00000040 692 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_20G 0x00000080 693 694 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_MASK 0xFFFF0000 695 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_SHIFT 16 696 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_FULL 0x00010000 697 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_HALF 0x00020000 698 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_HALF 0x00040000 699 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_FULL 0x00080000 700 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_1G 0x00100000 701 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_2_5G 0x00200000 702 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10G 0x00400000 703 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_20G 0x00800000 704 705 706 /* In the case where two media types (e.g. copper and fiber) are 707 present and electrically active at the same time, PHY Selection 708 will determine which of the two PHYs will be designated as the 709 Active PHY and used for a connection to the network. */ 710 uint32_t multi_phy_config; /* 0x290 */ 711 #define PORT_HW_CFG_PHY_SELECTION_MASK 0x00000007 712 #define PORT_HW_CFG_PHY_SELECTION_SHIFT 0 713 #define PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT 0x00000000 714 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY 0x00000001 715 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY 0x00000002 716 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY 0x00000003 717 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY 0x00000004 718 719 /* When enabled, all second phy nvram parameters will be swapped 720 with the first phy parameters */ 721 #define PORT_HW_CFG_PHY_SWAPPED_MASK 0x00000008 722 #define PORT_HW_CFG_PHY_SWAPPED_SHIFT 3 723 #define PORT_HW_CFG_PHY_SWAPPED_DISABLED 0x00000000 724 #define PORT_HW_CFG_PHY_SWAPPED_ENABLED 0x00000008 725 726 727 /* Address of the second external phy */ 728 uint32_t external_phy_config2; /* 0x294 */ 729 #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_MASK 0x000000FF 730 #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_SHIFT 0 731 732 /* The second XGXS external PHY type */ 733 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_MASK 0x0000FF00 734 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SHIFT 8 735 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_DIRECT 0x00000000 736 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8071 0x00000100 737 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8072 0x00000200 738 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8073 0x00000300 739 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8705 0x00000400 740 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8706 0x00000500 741 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8726 0x00000600 742 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8481 0x00000700 743 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SFX7101 0x00000800 744 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727 0x00000900 745 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727_NOC 0x00000a00 746 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84823 0x00000b00 747 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54640 0x00000c00 748 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84833 0x00000d00 749 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54618SE 0x00000e00 750 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8722 0x00000f00 751 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54616 0x00001000 752 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84834 0x00001100 753 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_FAILURE 0x0000fd00 754 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_NOT_CONN 0x0000ff00 755 756 757 /* 4 times 16 bits for all 4 lanes. For some external PHYs (such as 758 8706, 8726 and 8727) not all 4 values are needed. */ 759 uint16_t xgxs_config2_rx[4]; /* 0x296 */ 760 uint16_t xgxs_config2_tx[4]; /* 0x2A0 */ 761 762 uint32_t lane_config; 763 #define PORT_HW_CFG_LANE_SWAP_CFG_MASK 0x0000FFFF 764 #define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT 0 765 /* AN and forced */ 766 #define PORT_HW_CFG_LANE_SWAP_CFG_01230123 0x00001b1b 767 /* forced only */ 768 #define PORT_HW_CFG_LANE_SWAP_CFG_01233210 0x00001be4 769 /* forced only */ 770 #define PORT_HW_CFG_LANE_SWAP_CFG_31203120 0x0000d8d8 771 /* forced only */ 772 #define PORT_HW_CFG_LANE_SWAP_CFG_32103210 0x0000e4e4 773 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000FF 774 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0 775 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000FF00 776 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8 777 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK 0x0000C000 778 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT 14 779 780 /* Indicate whether to swap the external phy polarity */ 781 #define PORT_HW_CFG_SWAP_PHY_POLARITY_MASK 0x00010000 782 #define PORT_HW_CFG_SWAP_PHY_POLARITY_DISABLED 0x00000000 783 #define PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED 0x00010000 784 785 786 uint32_t external_phy_config; 787 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK 0x000000FF 788 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT 0 789 790 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK 0x0000FF00 791 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT 8 792 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT 0x00000000 793 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8071 0x00000100 794 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072 0x00000200 795 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073 0x00000300 796 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705 0x00000400 797 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706 0x00000500 798 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726 0x00000600 799 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481 0x00000700 800 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101 0x00000800 801 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727 0x00000900 802 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC 0x00000a00 803 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823 0x00000b00 804 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54640 0x00000c00 805 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833 0x00000d00 806 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE 0x00000e00 807 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722 0x00000f00 808 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616 0x00001000 809 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834 0x00001100 810 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT_WC 0x0000fc00 811 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00 812 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00 813 814 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK 0x00FF0000 815 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT 16 816 817 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK 0xFF000000 818 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT 24 819 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT 0x00000000 820 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482 0x01000000 821 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD 0x02000000 822 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN 0xff000000 823 824 uint32_t speed_capability_mask; 825 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK 0x0000FFFF 826 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT 0 827 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL 0x00000001 828 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF 0x00000002 829 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF 0x00000004 830 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL 0x00000008 831 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_1G 0x00000010 832 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G 0x00000020 833 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10G 0x00000040 834 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_20G 0x00000080 835 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED 0x0000f000 836 837 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK 0xFFFF0000 838 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT 16 839 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL 0x00010000 840 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF 0x00020000 841 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF 0x00040000 842 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL 0x00080000 843 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_1G 0x00100000 844 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G 0x00200000 845 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10G 0x00400000 846 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_20G 0x00800000 847 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED 0xf0000000 848 849 /* A place to hold the original MAC address as a backup */ 850 uint32_t backup_mac_upper; /* 0x2B4 */ 851 uint32_t backup_mac_lower; /* 0x2B8 */ 852 853}; 854 855 856/**************************************************************************** 857 * Shared Feature configuration * 858 ****************************************************************************/ 859struct shared_feat_cfg { /* NVRAM Offset */ 860 861 uint32_t config; /* 0x450 */ 862 #define SHARED_FEATURE_BMC_ECHO_MODE_EN 0x00000001 863 864 /* Use NVRAM values instead of HW default values */ 865 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_MASK \ 866 0x00000002 867 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_DISABLED \ 868 0x00000000 869 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED \ 870 0x00000002 871 872 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_MASK 0x00000008 873 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_SPIO 0x00000000 874 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_NVRAM 0x00000008 875 876 #define SHARED_FEAT_CFG_NCSI_ID_MASK 0x00000030 877 #define SHARED_FEAT_CFG_NCSI_ID_SHIFT 4 878 879 /* Override the OTP back to single function mode. When using GPIO, 880 high means only SF, 0 is according to CLP configuration */ 881 #define SHARED_FEAT_CFG_FORCE_SF_MODE_MASK 0x00000700 882 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SHIFT 8 883 #define SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED 0x00000000 884 #define SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF 0x00000100 885 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4 0x00000200 886 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT 0x00000300 887 #define SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE 0x00000400 888 889 /* Act as if the FCoE license is invalid */ 890 #define SHARED_FEAT_CFG_PREVENT_FCOE 0x00001000 891 892 /* Force FLR capability to all ports */ 893 #define SHARED_FEAT_CFG_FORCE_FLR_CAPABILITY 0x00002000 894 895 /* Act as if the iSCSI license is invalid */ 896 #define SHARED_FEAT_CFG_PREVENT_ISCSI_MASK 0x00004000 897 #define SHARED_FEAT_CFG_PREVENT_ISCSI_SHIFT 14 898 #define SHARED_FEAT_CFG_PREVENT_ISCSI_DISABLED 0x00000000 899 #define SHARED_FEAT_CFG_PREVENT_ISCSI_ENABLED 0x00004000 900 901 /* The interval in seconds between sending LLDP packets. Set to zero 902 to disable the feature */ 903 #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_MASK 0x00FF0000 904 #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_SHIFT 16 905 906 /* The assigned device type ID for LLDP usage */ 907 #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_MASK 0xFF000000 908 #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_SHIFT 24 909 910}; 911 912 913/**************************************************************************** 914 * Port Feature configuration * 915 ****************************************************************************/ 916struct port_feat_cfg { /* port 0: 0x454 port 1: 0x4c8 */ 917 918 uint32_t config; 919 #define PORT_FEAT_CFG_BAR1_SIZE_MASK 0x0000000F 920 #define PORT_FEAT_CFG_BAR1_SIZE_SHIFT 0 921 #define PORT_FEAT_CFG_BAR1_SIZE_DISABLED 0x00000000 922 #define PORT_FEAT_CFG_BAR1_SIZE_64K 0x00000001 923 #define PORT_FEAT_CFG_BAR1_SIZE_128K 0x00000002 924 #define PORT_FEAT_CFG_BAR1_SIZE_256K 0x00000003 925 #define PORT_FEAT_CFG_BAR1_SIZE_512K 0x00000004 926 #define PORT_FEAT_CFG_BAR1_SIZE_1M 0x00000005 927 #define PORT_FEAT_CFG_BAR1_SIZE_2M 0x00000006 928 #define PORT_FEAT_CFG_BAR1_SIZE_4M 0x00000007 929 #define PORT_FEAT_CFG_BAR1_SIZE_8M 0x00000008 930 #define PORT_FEAT_CFG_BAR1_SIZE_16M 0x00000009 931 #define PORT_FEAT_CFG_BAR1_SIZE_32M 0x0000000a 932 #define PORT_FEAT_CFG_BAR1_SIZE_64M 0x0000000b 933 #define PORT_FEAT_CFG_BAR1_SIZE_128M 0x0000000c 934 #define PORT_FEAT_CFG_BAR1_SIZE_256M 0x0000000d 935 #define PORT_FEAT_CFG_BAR1_SIZE_512M 0x0000000e 936 #define PORT_FEAT_CFG_BAR1_SIZE_1G 0x0000000f 937 #define PORT_FEAT_CFG_BAR2_SIZE_MASK 0x000000F0 938 #define PORT_FEAT_CFG_BAR2_SIZE_SHIFT 4 939 #define PORT_FEAT_CFG_BAR2_SIZE_DISABLED 0x00000000 940 #define PORT_FEAT_CFG_BAR2_SIZE_64K 0x00000010 941 #define PORT_FEAT_CFG_BAR2_SIZE_128K 0x00000020 942 #define PORT_FEAT_CFG_BAR2_SIZE_256K 0x00000030 943 #define PORT_FEAT_CFG_BAR2_SIZE_512K 0x00000040 944 #define PORT_FEAT_CFG_BAR2_SIZE_1M 0x00000050 945 #define PORT_FEAT_CFG_BAR2_SIZE_2M 0x00000060 946 #define PORT_FEAT_CFG_BAR2_SIZE_4M 0x00000070 947 #define PORT_FEAT_CFG_BAR2_SIZE_8M 0x00000080 948 #define PORT_FEAT_CFG_BAR2_SIZE_16M 0x00000090 949 #define PORT_FEAT_CFG_BAR2_SIZE_32M 0x000000a0 950 #define PORT_FEAT_CFG_BAR2_SIZE_64M 0x000000b0 951 #define PORT_FEAT_CFG_BAR2_SIZE_128M 0x000000c0 952 #define PORT_FEAT_CFG_BAR2_SIZE_256M 0x000000d0 953 #define PORT_FEAT_CFG_BAR2_SIZE_512M 0x000000e0 954 #define PORT_FEAT_CFG_BAR2_SIZE_1G 0x000000f0 955 956 #define PORT_FEAT_CFG_DCBX_MASK 0x00000100 957 #define PORT_FEAT_CFG_DCBX_DISABLED 0x00000000 958 #define PORT_FEAT_CFG_DCBX_ENABLED 0x00000100 959 960 #define PORT_FEAT_CFG_AUTOGREEEN_MASK 0x00000200 961 #define PORT_FEAT_CFG_AUTOGREEEN_SHIFT 9 962 #define PORT_FEAT_CFG_AUTOGREEEN_DISABLED 0x00000000 963 #define PORT_FEAT_CFG_AUTOGREEEN_ENABLED 0x00000200 964 965 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK 0x00000C00 966 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_SHIFT 10 967 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_DEFAULT 0x00000000 968 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE 0x00000400 969 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI 0x00000800 970 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_BOTH 0x00000c00 971 972 #define PORT_FEATURE_EN_SIZE_MASK 0x0f000000 973 #define PORT_FEATURE_EN_SIZE_SHIFT 24 974 #define PORT_FEATURE_WOL_ENABLED 0x01000000 975 #define PORT_FEATURE_MBA_ENABLED 0x02000000 976 #define PORT_FEATURE_MFW_ENABLED 0x04000000 977 978 /* Advertise expansion ROM even if MBA is disabled */ 979 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_MASK 0x08000000 980 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_DISABLED 0x00000000 981 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_ENABLED 0x08000000 982 983 /* Check the optic vendor via i2c against a list of approved modules 984 in a separate nvram image */ 985 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK 0xE0000000 986 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_SHIFT 29 987 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT \ 988 0x00000000 989 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER \ 990 0x20000000 991 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG 0x40000000 992 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN 0x60000000 993 994 uint32_t wol_config; 995 /* Default is used when driver sets to "auto" mode */ 996 #define PORT_FEATURE_WOL_ACPI_UPON_MGMT 0x00000010 997 998 uint32_t mba_config; 999 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x00000007 1000 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT 0 1001 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0x00000000 1002 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 0x00000001 1003 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 0x00000002 1004 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB 0x00000003 1005 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT 0x00000004 1006 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE 0x00000007 1007 1008 #define PORT_FEATURE_MBA_BOOT_RETRY_MASK 0x00000038 1009 #define PORT_FEATURE_MBA_BOOT_RETRY_SHIFT 3 1010 1011 #define PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x00000400 1012 #define PORT_FEATURE_MBA_HOTKEY_MASK 0x00000800 1013 #define PORT_FEATURE_MBA_HOTKEY_CTRL_S 0x00000000 1014 #define PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x00000800 1015 1016 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0x000FF000 1017 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT 12 1018 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0x00000000 1019 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x00001000 1020 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x00002000 1021 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x00003000 1022 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x00004000 1023 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x00005000 1024 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x00006000 1025 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x00007000 1026 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x00008000 1027 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0x00009000 1028 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0x0000a000 1029 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0x0000b000 1030 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0x0000c000 1031 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0x0000d000 1032 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0x0000e000 1033 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32M 0x0000f000 1034 #define PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0x00F00000 1035 #define PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT 20 1036 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x03000000 1037 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT 24 1038 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0x00000000 1039 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x01000000 1040 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x02000000 1041 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x03000000 1042 #define PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3C000000 1043 #define PORT_FEATURE_MBA_LINK_SPEED_SHIFT 26 1044 #define PORT_FEATURE_MBA_LINK_SPEED_AUTO 0x00000000 1045 #define PORT_FEATURE_MBA_LINK_SPEED_10M_HALF 0x04000000 1046 #define PORT_FEATURE_MBA_LINK_SPEED_10M_FULL 0x08000000 1047 #define PORT_FEATURE_MBA_LINK_SPEED_100M_HALF 0x0c000000 1048 #define PORT_FEATURE_MBA_LINK_SPEED_100M_FULL 0x10000000 1049 #define PORT_FEATURE_MBA_LINK_SPEED_1G 0x14000000 1050 #define PORT_FEATURE_MBA_LINK_SPEED_2_5G 0x18000000 1051 #define PORT_FEATURE_MBA_LINK_SPEED_10G 0x1c000000 1052 #define PORT_FEATURE_MBA_LINK_SPEED_20G 0x20000000 1053 1054 uint32_t Reserved0; /* 0x460 */ 1055 1056 uint32_t mba_vlan_cfg; 1057 #define PORT_FEATURE_MBA_VLAN_TAG_MASK 0x0000FFFF 1058 #define PORT_FEATURE_MBA_VLAN_TAG_SHIFT 0 1059 #define PORT_FEATURE_MBA_VLAN_EN 0x00010000 1060 #define PORT_FEATUTE_BOFM_CFGD_EN 0x00020000 1061 #define PORT_FEATURE_BOFM_CFGD_FTGT 0x00040000 1062 #define PORT_FEATURE_BOFM_CFGD_VEN 0x00080000 1063 1064 uint32_t Reserved1; 1065 uint32_t smbus_config; 1066 #define PORT_FEATURE_SMBUS_ADDR_MASK 0x000000fe 1067 #define PORT_FEATURE_SMBUS_ADDR_SHIFT 1 1068 1069 uint32_t vf_config; 1070 #define PORT_FEAT_CFG_VF_BAR2_SIZE_MASK 0x0000000F 1071 #define PORT_FEAT_CFG_VF_BAR2_SIZE_SHIFT 0 1072 #define PORT_FEAT_CFG_VF_BAR2_SIZE_DISABLED 0x00000000 1073 #define PORT_FEAT_CFG_VF_BAR2_SIZE_4K 0x00000001 1074 #define PORT_FEAT_CFG_VF_BAR2_SIZE_8K 0x00000002 1075 #define PORT_FEAT_CFG_VF_BAR2_SIZE_16K 0x00000003 1076 #define PORT_FEAT_CFG_VF_BAR2_SIZE_32K 0x00000004 1077 #define PORT_FEAT_CFG_VF_BAR2_SIZE_64K 0x00000005 1078 #define PORT_FEAT_CFG_VF_BAR2_SIZE_128K 0x00000006 1079 #define PORT_FEAT_CFG_VF_BAR2_SIZE_256K 0x00000007 1080 #define PORT_FEAT_CFG_VF_BAR2_SIZE_512K 0x00000008 1081 #define PORT_FEAT_CFG_VF_BAR2_SIZE_1M 0x00000009 1082 #define PORT_FEAT_CFG_VF_BAR2_SIZE_2M 0x0000000a 1083 #define PORT_FEAT_CFG_VF_BAR2_SIZE_4M 0x0000000b 1084 #define PORT_FEAT_CFG_VF_BAR2_SIZE_8M 0x0000000c 1085 #define PORT_FEAT_CFG_VF_BAR2_SIZE_16M 0x0000000d 1086 #define PORT_FEAT_CFG_VF_BAR2_SIZE_32M 0x0000000e 1087 #define PORT_FEAT_CFG_VF_BAR2_SIZE_64M 0x0000000f 1088 1089 uint32_t link_config; /* Used as HW defaults for the driver */ 1090 1091 #define PORT_FEATURE_FLOW_CONTROL_MASK 0x00000700 1092 #define PORT_FEATURE_FLOW_CONTROL_SHIFT 8 1093 #define PORT_FEATURE_FLOW_CONTROL_AUTO 0x00000000 1094 #define PORT_FEATURE_FLOW_CONTROL_TX 0x00000100 1095 #define PORT_FEATURE_FLOW_CONTROL_RX 0x00000200 1096 #define PORT_FEATURE_FLOW_CONTROL_BOTH 0x00000300 1097 #define PORT_FEATURE_FLOW_CONTROL_NONE 0x00000400 1098 #define PORT_FEATURE_FLOW_CONTROL_SAFC_RX 0x00000500 1099 #define PORT_FEATURE_FLOW_CONTROL_SAFC_TX 0x00000600 1100 #define PORT_FEATURE_FLOW_CONTROL_SAFC_BOTH 0x00000700 1101 1102 #define PORT_FEATURE_LINK_SPEED_MASK 0x000F0000 1103 #define PORT_FEATURE_LINK_SPEED_SHIFT 16 1104 #define PORT_FEATURE_LINK_SPEED_AUTO 0x00000000 1105 #define PORT_FEATURE_LINK_SPEED_10M_HALF 0x00010000 1106 #define PORT_FEATURE_LINK_SPEED_10M_FULL 0x00020000 1107 #define PORT_FEATURE_LINK_SPEED_100M_HALF 0x00030000 1108 #define PORT_FEATURE_LINK_SPEED_100M_FULL 0x00040000 1109 #define PORT_FEATURE_LINK_SPEED_1G 0x00050000 1110 #define PORT_FEATURE_LINK_SPEED_2_5G 0x00060000 1111 #define PORT_FEATURE_LINK_SPEED_10G_CX4 0x00070000 1112 #define PORT_FEATURE_LINK_SPEED_20G 0x00080000 1113 1114 #define PORT_FEATURE_CONNECTED_SWITCH_MASK 0x03000000 1115 #define PORT_FEATURE_CONNECTED_SWITCH_SHIFT 24 1116 /* (forced) low speed switch (< 10G) */ 1117 #define PORT_FEATURE_CON_SWITCH_1G_SWITCH 0x00000000 1118 /* (forced) high speed switch (>= 10G) */ 1119 #define PORT_FEATURE_CON_SWITCH_10G_SWITCH 0x01000000 1120 #define PORT_FEATURE_CON_SWITCH_AUTO_DETECT 0x02000000 1121 #define PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT 0x03000000 1122 1123 1124 /* The default for MCP link configuration, 1125 uses the same defines as link_config */ 1126 uint32_t mfw_wol_link_cfg; 1127 1128 /* The default for the driver of the second external phy, 1129 uses the same defines as link_config */ 1130 uint32_t link_config2; /* 0x47C */ 1131 1132 /* The default for MCP of the second external phy, 1133 uses the same defines as link_config */ 1134 uint32_t mfw_wol_link_cfg2; /* 0x480 */ 1135 1136 1137 /* EEE power saving mode */ 1138 uint32_t eee_power_mode; /* 0x484 */ 1139 #define PORT_FEAT_CFG_EEE_POWER_MODE_MASK 0x000000FF 1140 #define PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT 0 1141 #define PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED 0x00000000 1142 #define PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED 0x00000001 1143 #define PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE 0x00000002 1144 #define PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY 0x00000003 1145 1146 1147 uint32_t Reserved2[16]; /* 0x488 */ 1148}; 1149 1150/**************************************************************************** 1151 * Device Information * 1152 ****************************************************************************/ 1153struct shm_dev_info { /* size */ 1154 1155 uint32_t bc_rev; /* 8 bits each: major, minor, build */ /* 4 */ 1156 1157 struct shared_hw_cfg shared_hw_config; /* 40 */ 1158 1159 struct port_hw_cfg port_hw_config[PORT_MAX]; /* 400*2=800 */ 1160 1161 struct shared_feat_cfg shared_feature_config; /* 4 */ 1162 1163 struct port_feat_cfg port_feature_config[PORT_MAX];/* 116*2=232 */ 1164 1165}; 1166 1167struct extended_dev_info_shared_cfg { /* NVRAM OFFSET */ 1168 1169 /* Threshold in celcius to start using the fan */ 1170 uint32_t temperature_monitor1; /* 0x4000 */ 1171 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_THRESH_MASK 0x0000007F 1172 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_THRESH_SHIFT 0 1173 1174 /* Threshold in celcius to shut down the board */ 1175 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_THRESH_MASK 0x00007F00 1176 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_THRESH_SHIFT 8 1177 1178 /* EPIO of fan temperature status */ 1179 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_MASK 0x00FF0000 1180 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_SHIFT 16 1181 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_NA 0x00000000 1182 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO0 0x00010000 1183 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO1 0x00020000 1184 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO2 0x00030000 1185 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO3 0x00040000 1186 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO4 0x00050000 1187 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO5 0x00060000 1188 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO6 0x00070000 1189 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO7 0x00080000 1190 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO8 0x00090000 1191 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO9 0x000a0000 1192 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO10 0x000b0000 1193 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO11 0x000c0000 1194 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO12 0x000d0000 1195 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO13 0x000e0000 1196 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO14 0x000f0000 1197 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO15 0x00100000 1198 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO16 0x00110000 1199 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO17 0x00120000 1200 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO18 0x00130000 1201 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO19 0x00140000 1202 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO20 0x00150000 1203 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO21 0x00160000 1204 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO22 0x00170000 1205 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO23 0x00180000 1206 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO24 0x00190000 1207 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO25 0x001a0000 1208 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO26 0x001b0000 1209 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO27 0x001c0000 1210 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO28 0x001d0000 1211 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO29 0x001e0000 1212 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO30 0x001f0000 1213 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO31 0x00200000 1214 1215 /* EPIO of shut down temperature status */ 1216 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_MASK 0xFF000000 1217 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_SHIFT 24 1218 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_NA 0x00000000 1219 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO0 0x01000000 1220 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO1 0x02000000 1221 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO2 0x03000000 1222 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO3 0x04000000 1223 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO4 0x05000000 1224 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO5 0x06000000 1225 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO6 0x07000000 1226 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO7 0x08000000 1227 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO8 0x09000000 1228 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO9 0x0a000000 1229 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO10 0x0b000000 1230 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO11 0x0c000000 1231 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO12 0x0d000000 1232 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO13 0x0e000000 1233 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO14 0x0f000000 1234 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO15 0x10000000 1235 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO16 0x11000000 1236 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO17 0x12000000 1237 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO18 0x13000000 1238 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO19 0x14000000 1239 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO20 0x15000000 1240 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO21 0x16000000 1241 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO22 0x17000000 1242 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO23 0x18000000 1243 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO24 0x19000000 1244 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO25 0x1a000000 1245 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO26 0x1b000000 1246 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO27 0x1c000000 1247 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO28 0x1d000000 1248 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO29 0x1e000000 1249 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO30 0x1f000000 1250 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO31 0x20000000 1251 1252 1253 /* EPIO of shut down temperature status */ 1254 uint32_t temperature_monitor2; /* 0x4004 */ 1255 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_PERIOD_MASK 0x0000FFFF 1256 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_PERIOD_SHIFT 0 1257 1258 1259 /* MFW flavor to be used */ 1260 uint32_t mfw_cfg; /* 0x4008 */ 1261 #define EXTENDED_DEV_INFO_SHARED_CFG_MFW_FLAVOR_MASK 0x000000FF 1262 #define EXTENDED_DEV_INFO_SHARED_CFG_MFW_FLAVOR_SHIFT 0 1263 #define EXTENDED_DEV_INFO_SHARED_CFG_MFW_FLAVOR_NA 0x00000000 1264 #define EXTENDED_DEV_INFO_SHARED_CFG_MFW_FLAVOR_A 0x00000001 1265 1266 /* Should NIC data query remain enabled upon last drv unload */ 1267 #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_EN_LAST_DRV_MASK 0x00000100 1268 #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_EN_LAST_DRV_SHIFT 8 1269 #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_EN_LAST_DRV_DISABLED 0x00000000 1270 #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_EN_LAST_DRV_ENABLED 0x00000100 1271 1272 /* Hide DCBX feature in CCM/BACS menus */ 1273 #define EXTENDED_DEV_INFO_SHARED_CFG_HIDE_DCBX_FEAT_MASK 0x00010000 1274 #define EXTENDED_DEV_INFO_SHARED_CFG_HIDE_DCBX_FEAT_SHIFT 16 1275 #define EXTENDED_DEV_INFO_SHARED_CFG_HIDE_DCBX_FEAT_DISABLED 0x00000000 1276 #define EXTENDED_DEV_INFO_SHARED_CFG_HIDE_DCBX_FEAT_ENABLED 0x00010000 1277 1278 uint32_t smbus_config; /* 0x400C */ 1279 #define EXTENDED_DEV_INFO_SHARED_CFG_SMBUS_ADDR_MASK 0x000000FF 1280 #define EXTENDED_DEV_INFO_SHARED_CFG_SMBUS_ADDR_SHIFT 0 1281 1282 /* Switching regulator loop gain */ 1283 uint32_t board_cfg; /* 0x4010 */ 1284 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_MASK 0x0000000F 1285 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_SHIFT 0 1286 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_HW_DEFAULT 0x00000000 1287 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X2 0x00000008 1288 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X4 0x00000009 1289 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X8 0x0000000a 1290 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X16 0x0000000b 1291 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_DIV8 0x0000000c 1292 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_DIV4 0x0000000d 1293 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_DIV2 0x0000000e 1294 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X1 0x0000000f 1295 1296 /* whether shadow swim feature is supported */ 1297 #define EXTENDED_DEV_INFO_SHARED_CFG_SHADOW_SWIM_MASK 0x00000100 1298 #define EXTENDED_DEV_INFO_SHARED_CFG_SHADOW_SWIM_SHIFT 8 1299 #define EXTENDED_DEV_INFO_SHARED_CFG_SHADOW_SWIM_DISABLED 0x00000000 1300 #define EXTENDED_DEV_INFO_SHARED_CFG_SHADOW_SWIM_ENABLED 0x00000100 1301 1302 /* whether to show/hide SRIOV menu in CCM */ 1303 #define EXTENDED_DEV_INFO_SHARED_CFG_SRIOV_SHOW_MENU_MASK 0x00000200 1304 #define EXTENDED_DEV_INFO_SHARED_CFG_SRIOV_SHOW_MENU_SHIFT 9 1305 #define EXTENDED_DEV_INFO_SHARED_CFG_SRIOV_SHOW_MENU 0x00000000 1306 #define EXTENDED_DEV_INFO_SHARED_CFG_SRIOV_HIDE_MENU 0x00000200 1307 1308 /* Overide PCIE revision ID when enabled the, 1309 revision ID will set to B1=='0x11' */ 1310 #define EXTENDED_DEV_INFO_SHARED_CFG_OVR_REV_ID_MASK 0x00000400 1311 #define EXTENDED_DEV_INFO_SHARED_CFG_OVR_REV_ID_SHIFT 10 1312 #define EXTENDED_DEV_INFO_SHARED_CFG_OVR_REV_ID_DISABLED 0x00000000 1313 #define EXTENDED_DEV_INFO_SHARED_CFG_OVR_REV_ID_ENABLED 0x00000400 1314 1315 /* Threshold in celcius for max continuous operation */ 1316 uint32_t temperature_report; /* 0x4014 */ 1317 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_MCOT_MASK 0x0000007F 1318 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_MCOT_SHIFT 0 1319 1320 /* Threshold in celcius for sensor caution */ 1321 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SCT_MASK 0x00007F00 1322 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SCT_SHIFT 8 1323 1324 /* wwn node prefix to be used (unless value is 0) */ 1325 uint32_t wwn_prefix; /* 0x4018 */ 1326 #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_NODE_PREFIX0_MASK 0x000000FF 1327 #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_NODE_PREFIX0_SHIFT 0 1328 1329 #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_NODE_PREFIX1_MASK 0x0000FF00 1330 #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_NODE_PREFIX1_SHIFT 8 1331 1332 /* wwn port prefix to be used (unless value is 0) */ 1333 #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_PORT_PREFIX0_MASK 0x00FF0000 1334 #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_PORT_PREFIX0_SHIFT 16 1335 1336 /* wwn port prefix to be used (unless value is 0) */ 1337 #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_PORT_PREFIX1_MASK 0xFF000000 1338 #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_PORT_PREFIX1_SHIFT 24 1339 1340 /* General debug nvm cfg */ 1341 uint32_t dbg_cfg_flags; /* 0x401C */ 1342 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_MASK 0x000FFFFF 1343 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SHIFT 0 1344 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_ENABLE 0x00000001 1345 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_EN_SIGDET_FILTER 0x00000002 1346 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_LP_TX_PRESET7 0x00000004 1347 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_TX_ANA_DEFAULT 0x00000008 1348 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_PLL_ANA_DEFAULT 0x00000010 1349 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_FORCE_G1PLL_RETUNE 0x00000020 1350 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_RX_ANA_DEFAULT 0x00000040 1351 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_FORCE_SERDES_RX_CLK 0x00000080 1352 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_DIS_RX_LP_EIEOS 0x00000100 1353 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_FINALIZE_UCODE 0x00000200 1354 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_HOLDOFF_REQ 0x00000400 1355 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_RX_SIGDET_OVERRIDE 0x00000800 1356 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_GP_PORG_UC_RESET 0x00001000 1357 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SUPPRESS_COMPEN_EVT 0x00002000 1358 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_ADJ_TXEQ_P0_P1 0x00004000 1359 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_G3_PLL_RETUNE 0x00008000 1360 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_MAC_PHY_CTL8 0x00010000 1361 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_DIS_MAC_G3_FRM_ERR 0x00020000 1362 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_INFERRED_EI 0x00040000 1363 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_GEN3_COMPLI_ENA 0x00080000 1364 1365 /* Debug signet rx threshold */ 1366 uint32_t dbg_rx_sigdet_threshold; /* 0x4020 */ 1367 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_RX_SIGDET_MASK 0x00000007 1368 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_RX_SIGDET_SHIFT 0 1369 1370 /* Enable IFFE feature */ 1371 uint32_t iffe_features; /* 0x4024 */ 1372 #define EXTENDED_DEV_INFO_SHARED_CFG_ENABLE_IFFE_MASK 0x00000001 1373 #define EXTENDED_DEV_INFO_SHARED_CFG_ENABLE_IFFE_SHIFT 0 1374 #define EXTENDED_DEV_INFO_SHARED_CFG_ENABLE_IFFE_DISABLED 0x00000000 1375 #define EXTENDED_DEV_INFO_SHARED_CFG_ENABLE_IFFE_ENABLED 0x00000001 1376 1377 /* Allowable port enablement (bitmask for ports 3-1) */ 1378 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_PORT_MASK 0x0000000E 1379 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_PORT_SHIFT 1 1380 1381 /* Allow iSCSI offload override */ 1382 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_ISCSI_MASK 0x00000010 1383 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_ISCSI_SHIFT 4 1384 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_ISCSI_DISABLED 0x00000000 1385 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_ISCSI_ENABLED 0x00000010 1386 1387 /* Allow FCoE offload override */ 1388 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_FCOE_MASK 0x00000020 1389 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_FCOE_SHIFT 5 1390 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_FCOE_DISABLED 0x00000000 1391 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_FCOE_ENABLED 0x00000020 1392 1393 /* Tie to adaptor */ 1394 #define EXTENDED_DEV_INFO_SHARED_CFG_TIE_ADAPTOR_MASK 0x00008000 1395 #define EXTENDED_DEV_INFO_SHARED_CFG_TIE_ADAPTOR_SHIFT 15 1396 #define EXTENDED_DEV_INFO_SHARED_CFG_TIE_ADAPTOR_DISABLED 0x00000000 1397 #define EXTENDED_DEV_INFO_SHARED_CFG_TIE_ADAPTOR_ENABLED 0x00008000 1398 1399 /* Currently enabled port(s) (bitmask for ports 3-1) */ 1400 uint32_t current_iffe_mask; /* 0x4028 */ 1401 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_CFG_MASK 0x0000000E 1402 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_CFG_SHIFT 1 1403 1404 /* Current iSCSI offload */ 1405 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_ISCSI_MASK 0x00000010 1406 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_ISCSI_SHIFT 4 1407 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_ISCSI_DISABLED 0x00000000 1408 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_ISCSI_ENABLED 0x00000010 1409 1410 /* Current FCoE offload */ 1411 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_FCOE_MASK 0x00000020 1412 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_FCOE_SHIFT 5 1413 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_FCOE_DISABLED 0x00000000 1414 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_FCOE_ENABLED 0x00000020 1415 1416 /* FW set this pin to "0" (assert) these signal if either of its MAC 1417 * or PHY specific threshold values is exceeded. 1418 * Values are standard GPIO/EPIO pins. 1419 */ 1420 uint32_t threshold_pin; /* 0x402C */ 1421 #define EXTENDED_DEV_INFO_SHARED_CFG_TCONTROL_PIN_MASK 0x000000FF 1422 #define EXTENDED_DEV_INFO_SHARED_CFG_TCONTROL_PIN_SHIFT 0 1423 #define EXTENDED_DEV_INFO_SHARED_CFG_TWARNING_PIN_MASK 0x0000FF00 1424 #define EXTENDED_DEV_INFO_SHARED_CFG_TWARNING_PIN_SHIFT 8 1425 #define EXTENDED_DEV_INFO_SHARED_CFG_TCRITICAL_PIN_MASK 0x00FF0000 1426 #define EXTENDED_DEV_INFO_SHARED_CFG_TCRITICAL_PIN_SHIFT 16 1427 1428 /* MAC die temperature threshold in Celsius. */ 1429 uint32_t mac_threshold_val; /* 0x4030 */ 1430 #define EXTENDED_DEV_INFO_SHARED_CFG_CONTROL_MAC_THRESH_MASK 0x000000FF 1431 #define EXTENDED_DEV_INFO_SHARED_CFG_CONTROL_MAC_THRESH_SHIFT 0 1432 #define EXTENDED_DEV_INFO_SHARED_CFG_WARNING_MAC_THRESH_MASK 0x0000FF00 1433 #define EXTENDED_DEV_INFO_SHARED_CFG_WARNING_MAC_THRESH_SHIFT 8 1434 #define EXTENDED_DEV_INFO_SHARED_CFG_CRITICAL_MAC_THRESH_MASK 0x00FF0000 1435 #define EXTENDED_DEV_INFO_SHARED_CFG_CRITICAL_MAC_THRESH_SHIFT 16 1436 1437 /* PHY die temperature threshold in Celsius. */ 1438 uint32_t phy_threshold_val; /* 0x4034 */ 1439 #define EXTENDED_DEV_INFO_SHARED_CFG_CONTROL_PHY_THRESH_MASK 0x000000FF 1440 #define EXTENDED_DEV_INFO_SHARED_CFG_CONTROL_PHY_THRESH_SHIFT 0 1441 #define EXTENDED_DEV_INFO_SHARED_CFG_WARNING_PHY_THRESH_MASK 0x0000FF00 1442 #define EXTENDED_DEV_INFO_SHARED_CFG_WARNING_PHY_THRESH_SHIFT 8 1443 #define EXTENDED_DEV_INFO_SHARED_CFG_CRITICAL_PHY_THRESH_MASK 0x00FF0000 1444 #define EXTENDED_DEV_INFO_SHARED_CFG_CRITICAL_PHY_THRESH_SHIFT 16 1445 1446 /* External pins to communicate with host. 1447 * Values are standard GPIO/EPIO pins. 1448 */ 1449 uint32_t host_pin; /* 0x4038 */ 1450 #define EXTENDED_DEV_INFO_SHARED_CFG_I2C_ISOLATE_MASK 0x000000FF 1451 #define EXTENDED_DEV_INFO_SHARED_CFG_I2C_ISOLATE_SHIFT 0 1452 #define EXTENDED_DEV_INFO_SHARED_CFG_MEZZ_FAULT_MASK 0x0000FF00 1453 #define EXTENDED_DEV_INFO_SHARED_CFG_MEZZ_FAULT_SHIFT 8 1454 #define EXTENDED_DEV_INFO_SHARED_CFG_MEZZ_VPD_UPDATE_MASK 0x00FF0000 1455 #define EXTENDED_DEV_INFO_SHARED_CFG_MEZZ_VPD_UPDATE_SHIFT 16 1456 #define EXTENDED_DEV_INFO_SHARED_CFG_VPD_CACHE_COMP_MASK 0xFF000000 1457 #define EXTENDED_DEV_INFO_SHARED_CFG_VPD_CACHE_COMP_SHIFT 24 1458}; 1459 1460 1461#if !defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN) 1462 #error "Missing either LITTLE_ENDIAN or BIG_ENDIAN definition." 1463#endif 1464 1465#define FUNC_0 0 1466#define FUNC_1 1 1467#define FUNC_2 2 1468#define FUNC_3 3 1469#define FUNC_4 4 1470#define FUNC_5 5 1471#define FUNC_6 6 1472#define FUNC_7 7 1473#define E1_FUNC_MAX 2 1474#define E1H_FUNC_MAX 8 1475#define E2_FUNC_MAX 4 /* per path */ 1476 1477#define VN_0 0 1478#define VN_1 1 1479#define VN_2 2 1480#define VN_3 3 1481#define E1VN_MAX 1 1482#define E1HVN_MAX 4 1483 1484#define E2_VF_MAX 64 /* HC_REG_VF_CONFIGURATION_SIZE */ 1485/* This value (in milliseconds) determines the frequency of the driver 1486 * issuing the PULSE message code. The firmware monitors this periodic 1487 * pulse to determine when to switch to an OS-absent mode. */ 1488#define DRV_PULSE_PERIOD_MS 250 1489 1490/* This value (in milliseconds) determines how long the driver should 1491 * wait for an acknowledgement from the firmware before timing out. Once 1492 * the firmware has timed out, the driver will assume there is no firmware 1493 * running and there won't be any firmware-driver synchronization during a 1494 * driver reset. */ 1495#define FW_ACK_TIME_OUT_MS 5000 1496 1497#define FW_ACK_POLL_TIME_MS 1 1498 1499#define FW_ACK_NUM_OF_POLL (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS) 1500 1501#define MFW_TRACE_SIGNATURE 0x54524342 1502 1503/**************************************************************************** 1504 * Driver <-> FW Mailbox * 1505 ****************************************************************************/ 1506struct drv_port_mb { 1507 1508 uint32_t link_status; 1509 /* Driver should update this field on any link change event */ 1510 1511 #define LINK_STATUS_NONE (0<<0) 1512 #define LINK_STATUS_LINK_FLAG_MASK 0x00000001 1513 #define LINK_STATUS_LINK_UP 0x00000001 1514 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001E 1515 #define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE (0<<1) 1516 #define LINK_STATUS_SPEED_AND_DUPLEX_10THD (1<<1) 1517 #define LINK_STATUS_SPEED_AND_DUPLEX_10TFD (2<<1) 1518 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD (3<<1) 1519 #define LINK_STATUS_SPEED_AND_DUPLEX_100T4 (4<<1) 1520 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD (5<<1) 1521 #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (6<<1) 1522 #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (7<<1) 1523 #define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD (7<<1) 1524 #define LINK_STATUS_SPEED_AND_DUPLEX_2500THD (8<<1) 1525 #define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD (9<<1) 1526 #define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD (9<<1) 1527 #define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD (10<<1) 1528 #define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD (10<<1) 1529 #define LINK_STATUS_SPEED_AND_DUPLEX_20GTFD (11<<1) 1530 #define LINK_STATUS_SPEED_AND_DUPLEX_20GXFD (11<<1) 1531 1532 #define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK 0x00000020 1533 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020 1534 1535 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040 1536 #define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK 0x00000080 1537 #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080 1538 1539 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200 1540 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400 1541 #define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE 0x00000800 1542 #define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE 0x00001000 1543 #define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE 0x00002000 1544 #define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE 0x00004000 1545 #define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE 0x00008000 1546 1547 #define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK 0x00010000 1548 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00010000 1549 1550 #define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK 0x00020000 1551 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00020000 1552 1553 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000 1554 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0<<18) 1555 #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1<<18) 1556 #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2<<18) 1557 #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3<<18) 1558 1559 #define LINK_STATUS_SERDES_LINK 0x00100000 1560 1561 #define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE 0x00200000 1562 #define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE 0x00400000 1563 #define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE 0x00800000 1564 #define LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE 0x10000000 1565 1566 #define LINK_STATUS_PFC_ENABLED 0x20000000 1567 1568 #define LINK_STATUS_PHYSICAL_LINK_FLAG 0x40000000 1569 #define LINK_STATUS_SFP_TX_FAULT 0x80000000 1570 1571 uint32_t port_stx; 1572 1573 uint32_t stat_nig_timer; 1574 1575 /* MCP firmware does not use this field */ 1576 uint32_t ext_phy_fw_version; 1577 1578}; 1579 1580 1581struct drv_func_mb { 1582 1583 uint32_t drv_mb_header; 1584 #define DRV_MSG_CODE_MASK 0xffff0000 1585 #define DRV_MSG_CODE_LOAD_REQ 0x10000000 1586 #define DRV_MSG_CODE_LOAD_DONE 0x11000000 1587 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN 0x20000000 1588 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS 0x20010000 1589 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP 0x20020000 1590 #define DRV_MSG_CODE_UNLOAD_DONE 0x21000000 1591 #define DRV_MSG_CODE_DCC_OK 0x30000000 1592 #define DRV_MSG_CODE_DCC_FAILURE 0x31000000 1593 #define DRV_MSG_CODE_DIAG_ENTER_REQ 0x50000000 1594 #define DRV_MSG_CODE_DIAG_EXIT_REQ 0x60000000 1595 #define DRV_MSG_CODE_VALIDATE_KEY 0x70000000 1596 #define DRV_MSG_CODE_GET_CURR_KEY 0x80000000 1597 #define DRV_MSG_CODE_GET_UPGRADE_KEY 0x81000000 1598 #define DRV_MSG_CODE_GET_MANUF_KEY 0x82000000 1599 #define DRV_MSG_CODE_LOAD_L2B_PRAM 0x90000000 1600 1601 /* 1602 * The optic module verification command requires bootcode 1603 * v5.0.6 or later, te specific optic module verification command 1604 * requires bootcode v5.2.12 or later 1605 */ 1606 #define DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL 0xa0000000 1607 #define REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL 0x00050006 1608 #define DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL 0xa1000000 1609 #define REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL 0x00050234 1610 #define DRV_MSG_CODE_VRFY_AFEX_SUPPORTED 0xa2000000 1611 #define REQ_BC_VER_4_VRFY_AFEX_SUPPORTED 0x00070002 1612 #define REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED 0x00070014 1613 #define REQ_BC_VER_4_MT_SUPPORTED 0x00070201 1614 #define REQ_BC_VER_4_PFC_STATS_SUPPORTED 0x00070201 1615 #define REQ_BC_VER_4_FCOE_FEATURES 0x00070209 1616 1617 #define DRV_MSG_CODE_DCBX_ADMIN_PMF_MSG 0xb0000000 1618 #define DRV_MSG_CODE_DCBX_PMF_DRV_OK 0xb2000000 1619 #define REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF 0x00070401 1620 1621 #define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000 1622 1623 #define DRV_MSG_CODE_AFEX_DRIVER_SETMAC 0xd0000000 1624 #define DRV_MSG_CODE_AFEX_LISTGET_ACK 0xd1000000 1625 #define DRV_MSG_CODE_AFEX_LISTSET_ACK 0xd2000000 1626 #define DRV_MSG_CODE_AFEX_STATSGET_ACK 0xd3000000 1627 #define DRV_MSG_CODE_AFEX_VIFSET_ACK 0xd4000000 1628 1629 #define DRV_MSG_CODE_DRV_INFO_ACK 0xd8000000 1630 #define DRV_MSG_CODE_DRV_INFO_NACK 0xd9000000 1631 1632 #define DRV_MSG_CODE_EEE_RESULTS_ACK 0xda000000 1633 1634 #define DRV_MSG_CODE_RMMOD 0xdb000000 1635 #define REQ_BC_VER_4_RMMOD_CMD 0x0007080f 1636 1637 #define DRV_MSG_CODE_SET_MF_BW 0xe0000000 1638 #define REQ_BC_VER_4_SET_MF_BW 0x00060202 1639 #define DRV_MSG_CODE_SET_MF_BW_ACK 0xe1000000 1640 1641 #define DRV_MSG_CODE_LINK_STATUS_CHANGED 0x01000000 1642 1643 #define DRV_MSG_CODE_INITIATE_FLR 0x02000000 1644 #define REQ_BC_VER_4_INITIATE_FLR 0x00070213 1645 1646 #define BIOS_MSG_CODE_LIC_CHALLENGE 0xff010000 1647 #define BIOS_MSG_CODE_LIC_RESPONSE 0xff020000 1648 #define BIOS_MSG_CODE_VIRT_MAC_PRIM 0xff030000 1649 #define BIOS_MSG_CODE_VIRT_MAC_ISCSI 0xff040000 1650 1651 #define DRV_MSG_CODE_IMG_OFFSET_REQ 0xe2000000 1652 #define DRV_MSG_CODE_IMG_SIZE_REQ 0xe3000000 1653 1654 #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff 1655 1656 uint32_t drv_mb_param; 1657 #define DRV_MSG_CODE_SET_MF_BW_MIN_MASK 0x00ff0000 1658 #define DRV_MSG_CODE_SET_MF_BW_MAX_MASK 0xff000000 1659 1660 #define DRV_MSG_CODE_UNLOAD_NON_D3_POWER 0x00000001 1661 #define DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET 0x00000002 1662 1663 #define DRV_MSG_CODE_LOAD_REQ_WITH_LFA 0x0000100a 1664 #define DRV_MSG_CODE_LOAD_REQ_FORCE_LFA 0x00002000 1665 1666 #define DRV_MSG_CODE_USR_BLK_IMAGE_REQ 0x00000001 1667 #define DRV_MSG_CODE_ISCSI_PERS_IMAGE_REQ 0x00000002 1668 1669 uint32_t fw_mb_header; 1670 #define FW_MSG_CODE_MASK 0xffff0000 1671 #define FW_MSG_CODE_DRV_LOAD_COMMON 0x10100000 1672 #define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000 1673 #define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000 1674 /* Load common chip is supported from bc 6.0.0 */ 1675 #define REQ_BC_VER_4_DRV_LOAD_COMMON_CHIP 0x00060000 1676 #define FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 0x10130000 1677 1678 #define FW_MSG_CODE_DRV_LOAD_REFUSED 0x10200000 1679 #define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000 1680 #define FW_MSG_CODE_DRV_UNLOAD_COMMON 0x20100000 1681 #define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20110000 1682 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20120000 1683 #define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000 1684 #define FW_MSG_CODE_DCC_DONE 0x30100000 1685 #define FW_MSG_CODE_LLDP_DONE 0x40100000 1686 #define FW_MSG_CODE_DIAG_ENTER_DONE 0x50100000 1687 #define FW_MSG_CODE_DIAG_REFUSE 0x50200000 1688 #define FW_MSG_CODE_DIAG_EXIT_DONE 0x60100000 1689 #define FW_MSG_CODE_VALIDATE_KEY_SUCCESS 0x70100000 1690 #define FW_MSG_CODE_VALIDATE_KEY_FAILURE 0x70200000 1691 #define FW_MSG_CODE_GET_KEY_DONE 0x80100000 1692 #define FW_MSG_CODE_NO_KEY 0x80f00000 1693 #define FW_MSG_CODE_LIC_INFO_NOT_READY 0x80f80000 1694 #define FW_MSG_CODE_L2B_PRAM_LOADED 0x90100000 1695 #define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE 0x90210000 1696 #define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE 0x90220000 1697 #define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE 0x90230000 1698 #define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE 0x90240000 1699 #define FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS 0xa0100000 1700 #define FW_MSG_CODE_VRFY_OPT_MDL_INVLD_IMG 0xa0200000 1701 #define FW_MSG_CODE_VRFY_OPT_MDL_UNAPPROVED 0xa0300000 1702 #define FW_MSG_CODE_VF_DISABLED_DONE 0xb0000000 1703 #define FW_MSG_CODE_HW_SET_INVALID_IMAGE 0xb0100000 1704 1705 #define FW_MSG_CODE_AFEX_DRIVER_SETMAC_DONE 0xd0100000 1706 #define FW_MSG_CODE_AFEX_LISTGET_ACK 0xd1100000 1707 #define FW_MSG_CODE_AFEX_LISTSET_ACK 0xd2100000 1708 #define FW_MSG_CODE_AFEX_STATSGET_ACK 0xd3100000 1709 #define FW_MSG_CODE_AFEX_VIFSET_ACK 0xd4100000 1710 1711 #define FW_MSG_CODE_DRV_INFO_ACK 0xd8100000 1712 #define FW_MSG_CODE_DRV_INFO_NACK 0xd9100000 1713 1714 #define FW_MSG_CODE_EEE_RESULS_ACK 0xda100000 1715 1716 #define FW_MSG_CODE_RMMOD_ACK 0xdb100000 1717 1718 #define FW_MSG_CODE_SET_MF_BW_SENT 0xe0000000 1719 #define FW_MSG_CODE_SET_MF_BW_DONE 0xe1000000 1720 1721 #define FW_MSG_CODE_LINK_CHANGED_ACK 0x01100000 1722 1723 #define FW_MSG_CODE_FLR_ACK 0x02000000 1724 #define FW_MSG_CODE_FLR_NACK 0x02100000 1725 1726 #define FW_MSG_CODE_LIC_CHALLENGE 0xff010000 1727 #define FW_MSG_CODE_LIC_RESPONSE 0xff020000 1728 #define FW_MSG_CODE_VIRT_MAC_PRIM 0xff030000 1729 #define FW_MSG_CODE_VIRT_MAC_ISCSI 0xff040000 1730 1731 #define FW_MSG_CODE_IMG_OFFSET_RESPONSE 0xe2100000 1732 #define FW_MSG_CODE_IMG_SIZE_RESPONSE 0xe3100000 1733 1734 #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff 1735 1736 uint32_t fw_mb_param; 1737 1738 #define FW_PARAM_INVALID_IMG 0xffffffff 1739 1740 uint32_t drv_pulse_mb; 1741 #define DRV_PULSE_SEQ_MASK 0x00007fff 1742 #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000 1743 /* 1744 * The system time is in the format of 1745 * (year-2001)*12*32 + month*32 + day. 1746 */ 1747 #define DRV_PULSE_ALWAYS_ALIVE 0x00008000 1748 /* 1749 * Indicate to the firmware not to go into the 1750 * OS-absent when it is not getting driver pulse. 1751 * This is used for debugging as well for PXE(MBA). 1752 */ 1753 1754 uint32_t mcp_pulse_mb; 1755 #define MCP_PULSE_SEQ_MASK 0x00007fff 1756 #define MCP_PULSE_ALWAYS_ALIVE 0x00008000 1757 /* Indicates to the driver not to assert due to lack 1758 * of MCP response */ 1759 #define MCP_EVENT_MASK 0xffff0000 1760 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000 1761 1762 uint32_t iscsi_boot_signature; 1763 uint32_t iscsi_boot_block_offset; 1764 1765 uint32_t drv_status; 1766 #define DRV_STATUS_PMF 0x00000001 1767 #define DRV_STATUS_VF_DISABLED 0x00000002 1768 #define DRV_STATUS_SET_MF_BW 0x00000004 1769 #define DRV_STATUS_LINK_EVENT 0x00000008 1770 1771 #define DRV_STATUS_DCC_EVENT_MASK 0x0000ff00 1772 #define DRV_STATUS_DCC_DISABLE_ENABLE_PF 0x00000100 1773 #define DRV_STATUS_DCC_BANDWIDTH_ALLOCATION 0x00000200 1774 #define DRV_STATUS_DCC_CHANGE_MAC_ADDRESS 0x00000400 1775 #define DRV_STATUS_DCC_RESERVED1 0x00000800 1776 #define DRV_STATUS_DCC_SET_PROTOCOL 0x00001000 1777 #define DRV_STATUS_DCC_SET_PRIORITY 0x00002000 1778 1779 #define DRV_STATUS_DCBX_EVENT_MASK 0x000f0000 1780 #define DRV_STATUS_DCBX_NEGOTIATION_RESULTS 0x00010000 1781 #define DRV_STATUS_AFEX_EVENT_MASK 0x03f00000 1782 #define DRV_STATUS_AFEX_LISTGET_REQ 0x00100000 1783 #define DRV_STATUS_AFEX_LISTSET_REQ 0x00200000 1784 #define DRV_STATUS_AFEX_STATSGET_REQ 0x00400000 1785 #define DRV_STATUS_AFEX_VIFSET_REQ 0x00800000 1786 1787 #define DRV_STATUS_DRV_INFO_REQ 0x04000000 1788 1789 #define DRV_STATUS_EEE_NEGOTIATION_RESULTS 0x08000000 1790 1791 uint32_t virt_mac_upper; 1792 #define VIRT_MAC_SIGN_MASK 0xffff0000 1793 #define VIRT_MAC_SIGNATURE 0x564d0000 1794 uint32_t virt_mac_lower; 1795 1796}; 1797 1798 1799/**************************************************************************** 1800 * Management firmware state * 1801 ****************************************************************************/ 1802/* Allocate 440 bytes for management firmware */ 1803#define MGMTFW_STATE_WORD_SIZE 110 1804 1805struct mgmtfw_state { 1806 uint32_t opaque[MGMTFW_STATE_WORD_SIZE]; 1807}; 1808 1809 1810/**************************************************************************** 1811 * Multi-Function configuration * 1812 ****************************************************************************/ 1813struct shared_mf_cfg { 1814 1815 uint32_t clp_mb; 1816 #define SHARED_MF_CLP_SET_DEFAULT 0x00000000 1817 /* set by CLP */ 1818 #define SHARED_MF_CLP_EXIT 0x00000001 1819 /* set by MCP */ 1820 #define SHARED_MF_CLP_EXIT_DONE 0x00010000 1821 1822}; 1823 1824struct port_mf_cfg { 1825 1826 uint32_t dynamic_cfg; /* device control channel */ 1827 #define PORT_MF_CFG_E1HOV_TAG_MASK 0x0000ffff 1828 #define PORT_MF_CFG_E1HOV_TAG_SHIFT 0 1829 #define PORT_MF_CFG_E1HOV_TAG_DEFAULT PORT_MF_CFG_E1HOV_TAG_MASK 1830 1831 uint32_t reserved[1]; 1832 1833}; 1834 1835struct func_mf_cfg { 1836 1837 uint32_t config; 1838 /* E/R/I/D */ 1839 /* function 0 of each port cannot be hidden */ 1840 #define FUNC_MF_CFG_FUNC_HIDE 0x00000001 1841 1842 #define FUNC_MF_CFG_PROTOCOL_MASK 0x00000006 1843 #define FUNC_MF_CFG_PROTOCOL_FCOE 0x00000000 1844 #define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000002 1845 #define FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 0x00000004 1846 #define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000006 1847 #define FUNC_MF_CFG_PROTOCOL_DEFAULT \ 1848 FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 1849 1850 #define FUNC_MF_CFG_FUNC_DISABLED 0x00000008 1851 #define FUNC_MF_CFG_FUNC_DELETED 0x00000010 1852 1853 #define FUNC_MF_CFG_FUNC_BOOT_MASK 0x00000060 1854 #define FUNC_MF_CFG_FUNC_BOOT_BIOS_CTRL 0x00000000 1855 #define FUNC_MF_CFG_FUNC_BOOT_VCM_DISABLED 0x00000020 1856 #define FUNC_MF_CFG_FUNC_BOOT_VCM_ENABLED 0x00000040 1857 1858 /* PRI */ 1859 /* 0 - low priority, 3 - high priority */ 1860 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK 0x00000300 1861 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT 8 1862 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT 0x00000000 1863 1864 /* MINBW, MAXBW */ 1865 /* value range - 0..100, increments in 100Mbps */ 1866 #define FUNC_MF_CFG_MIN_BW_MASK 0x00ff0000 1867 #define FUNC_MF_CFG_MIN_BW_SHIFT 16 1868 #define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000 1869 #define FUNC_MF_CFG_MAX_BW_MASK 0xff000000 1870 #define FUNC_MF_CFG_MAX_BW_SHIFT 24 1871 #define FUNC_MF_CFG_MAX_BW_DEFAULT 0x64000000 1872 1873 uint32_t mac_upper; /* MAC */ 1874 #define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff 1875 #define FUNC_MF_CFG_UPPERMAC_SHIFT 0 1876 #define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK 1877 uint32_t mac_lower; 1878 #define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff 1879 1880 uint32_t e1hov_tag; /* VNI */ 1881 #define FUNC_MF_CFG_E1HOV_TAG_MASK 0x0000ffff 1882 #define FUNC_MF_CFG_E1HOV_TAG_SHIFT 0 1883 #define FUNC_MF_CFG_E1HOV_TAG_DEFAULT FUNC_MF_CFG_E1HOV_TAG_MASK 1884 1885 /* afex default VLAN ID - 12 bits */ 1886 #define FUNC_MF_CFG_AFEX_VLAN_MASK 0x0fff0000 1887 #define FUNC_MF_CFG_AFEX_VLAN_SHIFT 16 1888 1889 uint32_t afex_config; 1890 #define FUNC_MF_CFG_AFEX_COS_FILTER_MASK 0x000000ff 1891 #define FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT 0 1892 #define FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK 0x0000ff00 1893 #define FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT 8 1894 #define FUNC_MF_CFG_AFEX_MBA_ENABLED_VAL 0x00000100 1895 #define FUNC_MF_CFG_AFEX_VLAN_MODE_MASK 0x000f0000 1896 #define FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT 16 1897 1898 uint32_t pf_allocation; 1899 /* number of vfs in function, if 0 - sriov disabled */ 1900 #define FUNC_MF_CFG_NUMBER_OF_VFS_MASK 0x000000FF 1901 #define FUNC_MF_CFG_NUMBER_OF_VFS_SHIFT 0 1902}; 1903 1904enum mf_cfg_afex_vlan_mode { 1905 FUNC_MF_CFG_AFEX_VLAN_TRUNK_MODE = 0, 1906 FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE, 1907 FUNC_MF_CFG_AFEX_VLAN_TRUNK_TAG_NATIVE_MODE 1908}; 1909 1910/* This structure is not applicable and should not be accessed on 57711 */ 1911struct func_ext_cfg { 1912 uint32_t func_cfg; 1913 #define MACP_FUNC_CFG_FLAGS_MASK 0x0000007F 1914 #define MACP_FUNC_CFG_FLAGS_SHIFT 0 1915 #define MACP_FUNC_CFG_FLAGS_ENABLED 0x00000001 1916 #define MACP_FUNC_CFG_FLAGS_ETHERNET 0x00000002 1917 #define MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD 0x00000004 1918 #define MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD 0x00000008 1919 #define MACP_FUNC_CFG_PAUSE_ON_HOST_RING 0x00000080 1920 1921 uint32_t iscsi_mac_addr_upper; 1922 uint32_t iscsi_mac_addr_lower; 1923 1924 uint32_t fcoe_mac_addr_upper; 1925 uint32_t fcoe_mac_addr_lower; 1926 1927 uint32_t fcoe_wwn_port_name_upper; 1928 uint32_t fcoe_wwn_port_name_lower; 1929 1930 uint32_t fcoe_wwn_node_name_upper; 1931 uint32_t fcoe_wwn_node_name_lower; 1932 1933 uint32_t preserve_data; 1934 #define MF_FUNC_CFG_PRESERVE_L2_MAC (1<<0) 1935 #define MF_FUNC_CFG_PRESERVE_ISCSI_MAC (1<<1) 1936 #define MF_FUNC_CFG_PRESERVE_FCOE_MAC (1<<2) 1937 #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_P (1<<3) 1938 #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_N (1<<4) 1939 #define MF_FUNC_CFG_PRESERVE_TX_BW (1<<5) 1940}; 1941 1942struct mf_cfg { 1943 1944 struct shared_mf_cfg shared_mf_config; /* 0x4 */ 1945 struct port_mf_cfg port_mf_config[NVM_PATH_MAX][PORT_MAX]; 1946 /* 0x10*2=0x20 */ 1947 /* for all chips, there are 8 mf functions */ 1948 struct func_mf_cfg func_mf_config[E1H_FUNC_MAX]; /* 0x18 * 8 = 0xc0 */ 1949 /* 1950 * Extended configuration per function - this array does not exist and 1951 * should not be accessed on 57711 1952 */ 1953 struct func_ext_cfg func_ext_config[E1H_FUNC_MAX]; /* 0x28 * 8 = 0x140*/ 1954}; /* 0x224 */ 1955 1956/**************************************************************************** 1957 * Shared Memory Region * 1958 ****************************************************************************/ 1959struct shmem_region { /* SharedMem Offset (size) */ 1960 1961 uint32_t validity_map[PORT_MAX]; /* 0x0 (4*2 = 0x8) */ 1962 #define SHR_MEM_FORMAT_REV_MASK 0xff000000 1963 #define SHR_MEM_FORMAT_REV_ID ('A'<<24) 1964 /* validity bits */ 1965 #define SHR_MEM_VALIDITY_PCI_CFG 0x00100000 1966 #define SHR_MEM_VALIDITY_MB 0x00200000 1967 #define SHR_MEM_VALIDITY_DEV_INFO 0x00400000 1968 #define SHR_MEM_VALIDITY_RESERVED 0x00000007 1969 /* One licensing bit should be set */ 1970 #define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038 1971 #define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008 1972 #define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010 1973 #define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020 1974 /* Active MFW */ 1975 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN 0x00000000 1976 #define SHR_MEM_VALIDITY_ACTIVE_MFW_MASK 0x000001c0 1977 #define SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI 0x00000040 1978 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UMP 0x00000080 1979 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI 0x000000c0 1980 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NONE 0x000001c0 1981 1982 struct shm_dev_info dev_info; /* 0x8 (0x438) */ 1983 1984 license_key_t drv_lic_key[PORT_MAX]; /* 0x440 (52*2=0x68) */ 1985 1986 /* FW information (for internal FW use) */ 1987 uint32_t fw_info_fio_offset; /* 0x4a8 (0x4) */ 1988 struct mgmtfw_state mgmtfw_state; /* 0x4ac (0x1b8) */ 1989 1990 struct drv_port_mb port_mb[PORT_MAX]; /* 0x664 (16*2=0x20) */ 1991 1992 1993#ifdef BMAPI 1994 /* This is a variable length array */ 1995 /* the number of function depends on the chip type */ 1996 struct drv_func_mb func_mb[1]; /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */ 1997#else 1998 /* the number of function depends on the chip type */ 1999 struct drv_func_mb func_mb[]; /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */ 2000#endif /* BMAPI */ 2001 2002}; /* 57710 = 0x6dc | 57711 = 0x7E4 | 57712 = 0x734 */ 2003 2004/**************************************************************************** 2005 * Shared Memory 2 Region * 2006 ****************************************************************************/ 2007/* The fw_flr_ack is actually built in the following way: */ 2008/* 8 bit: PF ack */ 2009/* 64 bit: VF ack */ 2010/* 8 bit: ios_dis_ack */ 2011/* In order to maintain endianity in the mailbox hsi, we want to keep using */ 2012/* uint32_t. The fw must have the VF right after the PF since this is how it */ 2013/* access arrays(it expects always the VF to reside after the PF, and that */ 2014/* makes the calculation much easier for it. ) */ 2015/* In order to answer both limitations, and keep the struct small, the code */ 2016/* will abuse the structure defined here to achieve the actual partition */ 2017/* above */ 2018/****************************************************************************/ 2019struct fw_flr_ack { 2020 uint32_t pf_ack; 2021 uint32_t vf_ack[1]; 2022 uint32_t iov_dis_ack; 2023}; 2024 2025struct fw_flr_mb { 2026 uint32_t aggint; 2027 uint32_t opgen_addr; 2028 struct fw_flr_ack ack; 2029}; 2030 2031struct eee_remote_vals { 2032 uint32_t tx_tw; 2033 uint32_t rx_tw; 2034}; 2035 2036/**** SUPPORT FOR SHMEM ARRRAYS *** 2037 * The SHMEM HSI is aligned on 32 bit boundaries which makes it difficult to 2038 * define arrays with storage types smaller then unsigned dwords. 2039 * The macros below add generic support for SHMEM arrays with numeric elements 2040 * that can span 2,4,8 or 16 bits. The array underlying type is a 32 bit dword 2041 * array with individual bit-filed elements accessed using shifts and masks. 2042 * 2043 */ 2044 2045/* eb is the bitwidth of a single element */ 2046#define SHMEM_ARRAY_MASK(eb) ((1<<(eb))-1) 2047#define SHMEM_ARRAY_ENTRY(i, eb) ((i)/(32/(eb))) 2048 2049/* the bit-position macro allows the used to flip the order of the arrays 2050 * elements on a per byte or word boundary. 2051 * 2052 * example: an array with 8 entries each 4 bit wide. This array will fit into 2053 * a single dword. The diagrmas below show the array order of the nibbles. 2054 * 2055 * SHMEM_ARRAY_BITPOS(i, 4, 4) defines the stadard ordering: 2056 * 2057 * | | | | 2058 * 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 2059 * | | | | 2060 * 2061 * SHMEM_ARRAY_BITPOS(i, 4, 8) defines a flip ordering per byte: 2062 * 2063 * | | | | 2064 * 1 | 0 | 3 | 2 | 5 | 4 | 7 | 6 | 2065 * | | | | 2066 * 2067 * SHMEM_ARRAY_BITPOS(i, 4, 16) defines a flip ordering per word: 2068 * 2069 * | | | | 2070 * 3 | 2 | 1 | 0 | 7 | 6 | 5 | 4 | 2071 * | | | | 2072 */ 2073#define SHMEM_ARRAY_BITPOS(i, eb, fb) \ 2074 ((((32/(fb)) - 1 - ((i)/((fb)/(eb))) % (32/(fb))) * (fb)) + \ 2075 (((i)%((fb)/(eb))) * (eb))) 2076 2077#define SHMEM_ARRAY_GET(a, i, eb, fb) \ 2078 ((a[SHMEM_ARRAY_ENTRY(i, eb)] >> SHMEM_ARRAY_BITPOS(i, eb, fb)) & \ 2079 SHMEM_ARRAY_MASK(eb)) 2080 2081#define SHMEM_ARRAY_SET(a, i, eb, fb, val) \ 2082do { \ 2083 a[SHMEM_ARRAY_ENTRY(i, eb)] &= ~(SHMEM_ARRAY_MASK(eb) << \ 2084 SHMEM_ARRAY_BITPOS(i, eb, fb)); \ 2085 a[SHMEM_ARRAY_ENTRY(i, eb)] |= (((val) & SHMEM_ARRAY_MASK(eb)) << \ 2086 SHMEM_ARRAY_BITPOS(i, eb, fb)); \ 2087} while (0) 2088 2089 2090/****START OF DCBX STRUCTURES DECLARATIONS****/ 2091#define DCBX_MAX_NUM_PRI_PG_ENTRIES 8 2092#define DCBX_PRI_PG_BITWIDTH 4 2093#define DCBX_PRI_PG_FBITS 8 2094#define DCBX_PRI_PG_GET(a, i) \ 2095 SHMEM_ARRAY_GET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS) 2096#define DCBX_PRI_PG_SET(a, i, val) \ 2097 SHMEM_ARRAY_SET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS, val) 2098#define DCBX_MAX_NUM_PG_BW_ENTRIES 8 2099#define DCBX_BW_PG_BITWIDTH 8 2100#define DCBX_PG_BW_GET(a, i) \ 2101 SHMEM_ARRAY_GET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH) 2102#define DCBX_PG_BW_SET(a, i, val) \ 2103 SHMEM_ARRAY_SET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH, val) 2104#define DCBX_STRICT_PRI_PG 15 2105#define DCBX_MAX_APP_PROTOCOL 16 2106#define DCBX_MAX_APP_LOCAL 32 2107#define FCOE_APP_IDX 0 2108#define ISCSI_APP_IDX 1 2109#define PREDEFINED_APP_IDX_MAX 2 2110 2111 2112/* Big/Little endian have the same representation. */ 2113struct dcbx_ets_feature { 2114 /* 2115 * For Admin MIB - is this feature supported by the 2116 * driver | For Local MIB - should this feature be enabled. 2117 */ 2118 uint32_t enabled; 2119 uint32_t pg_bw_tbl[2]; 2120 uint32_t pri_pg_tbl[1]; 2121}; 2122 2123/* Driver structure in LE */ 2124struct dcbx_pfc_feature { 2125#ifdef __BIG_ENDIAN 2126 uint8_t pri_en_bitmap; 2127 #define DCBX_PFC_PRI_0 0x01 2128 #define DCBX_PFC_PRI_1 0x02 2129 #define DCBX_PFC_PRI_2 0x04 2130 #define DCBX_PFC_PRI_3 0x08 2131 #define DCBX_PFC_PRI_4 0x10 2132 #define DCBX_PFC_PRI_5 0x20 2133 #define DCBX_PFC_PRI_6 0x40 2134 #define DCBX_PFC_PRI_7 0x80 2135 uint8_t pfc_caps; 2136 uint8_t reserved; 2137 uint8_t enabled; 2138#elif defined(__LITTLE_ENDIAN) 2139 uint8_t enabled; 2140 uint8_t reserved; 2141 uint8_t pfc_caps; 2142 uint8_t pri_en_bitmap; 2143 #define DCBX_PFC_PRI_0 0x01 2144 #define DCBX_PFC_PRI_1 0x02 2145 #define DCBX_PFC_PRI_2 0x04 2146 #define DCBX_PFC_PRI_3 0x08 2147 #define DCBX_PFC_PRI_4 0x10 2148 #define DCBX_PFC_PRI_5 0x20 2149 #define DCBX_PFC_PRI_6 0x40 2150 #define DCBX_PFC_PRI_7 0x80 2151#endif 2152}; 2153 2154struct dcbx_app_priority_entry { 2155#ifdef __BIG_ENDIAN 2156 uint16_t app_id; 2157 uint8_t pri_bitmap; 2158 uint8_t appBitfield; 2159 #define DCBX_APP_ENTRY_VALID 0x01 2160 #define DCBX_APP_ENTRY_SF_MASK 0x30 2161 #define DCBX_APP_ENTRY_SF_SHIFT 4 2162 #define DCBX_APP_SF_ETH_TYPE 0x10 2163 #define DCBX_APP_SF_PORT 0x20 2164#elif defined(__LITTLE_ENDIAN) 2165 uint8_t appBitfield; 2166 #define DCBX_APP_ENTRY_VALID 0x01 2167 #define DCBX_APP_ENTRY_SF_MASK 0x30 2168 #define DCBX_APP_ENTRY_SF_SHIFT 4 2169 #define DCBX_APP_SF_ETH_TYPE 0x10 2170 #define DCBX_APP_SF_PORT 0x20 2171 uint8_t pri_bitmap; 2172 uint16_t app_id; 2173#endif 2174}; 2175 2176 2177/* FW structure in BE */ 2178struct dcbx_app_priority_feature { 2179#ifdef __BIG_ENDIAN 2180 uint8_t reserved; 2181 uint8_t default_pri; 2182 uint8_t tc_supported; 2183 uint8_t enabled; 2184#elif defined(__LITTLE_ENDIAN) 2185 uint8_t enabled; 2186 uint8_t tc_supported; 2187 uint8_t default_pri; 2188 uint8_t reserved; 2189#endif 2190 struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL]; 2191}; 2192 2193/* FW structure in BE */ 2194struct dcbx_features { 2195 /* PG feature */ 2196 struct dcbx_ets_feature ets; 2197 /* PFC feature */ 2198 struct dcbx_pfc_feature pfc; 2199 /* APP feature */ 2200 struct dcbx_app_priority_feature app; 2201}; 2202 2203/* LLDP protocol parameters */ 2204/* FW structure in BE */ 2205struct lldp_params { 2206#ifdef __BIG_ENDIAN 2207 uint8_t msg_fast_tx_interval; 2208 uint8_t msg_tx_hold; 2209 uint8_t msg_tx_interval; 2210 uint8_t admin_status; 2211 #define LLDP_TX_ONLY 0x01 2212 #define LLDP_RX_ONLY 0x02 2213 #define LLDP_TX_RX 0x03 2214 #define LLDP_DISABLED 0x04 2215 uint8_t reserved1; 2216 uint8_t tx_fast; 2217 uint8_t tx_crd_max; 2218 uint8_t tx_crd; 2219#elif defined(__LITTLE_ENDIAN) 2220 uint8_t admin_status; 2221 #define LLDP_TX_ONLY 0x01 2222 #define LLDP_RX_ONLY 0x02 2223 #define LLDP_TX_RX 0x03 2224 #define LLDP_DISABLED 0x04 2225 uint8_t msg_tx_interval; 2226 uint8_t msg_tx_hold; 2227 uint8_t msg_fast_tx_interval; 2228 uint8_t tx_crd; 2229 uint8_t tx_crd_max; 2230 uint8_t tx_fast; 2231 uint8_t reserved1; 2232#endif 2233 #define REM_CHASSIS_ID_STAT_LEN 4 2234 #define REM_PORT_ID_STAT_LEN 4 2235 /* Holds remote Chassis ID TLV header, subtype and 9B of payload. */ 2236 uint32_t peer_chassis_id[REM_CHASSIS_ID_STAT_LEN]; 2237 /* Holds remote Port ID TLV header, subtype and 9B of payload. */ 2238 uint32_t peer_port_id[REM_PORT_ID_STAT_LEN]; 2239}; 2240 2241struct lldp_dcbx_stat { 2242 #define LOCAL_CHASSIS_ID_STAT_LEN 2 2243 #define LOCAL_PORT_ID_STAT_LEN 2 2244 /* Holds local Chassis ID 8B payload of constant subtype 4. */ 2245 uint32_t local_chassis_id[LOCAL_CHASSIS_ID_STAT_LEN]; 2246 /* Holds local Port ID 8B payload of constant subtype 3. */ 2247 uint32_t local_port_id[LOCAL_PORT_ID_STAT_LEN]; 2248 /* Number of DCBX frames transmitted. */ 2249 uint32_t num_tx_dcbx_pkts; 2250 /* Number of DCBX frames received. */ 2251 uint32_t num_rx_dcbx_pkts; 2252}; 2253 2254/* ADMIN MIB - DCBX local machine default configuration. */ 2255struct lldp_admin_mib { 2256 uint32_t ver_cfg_flags; 2257 #define DCBX_ETS_CONFIG_TX_ENABLED 0x00000001 2258 #define DCBX_PFC_CONFIG_TX_ENABLED 0x00000002 2259 #define DCBX_APP_CONFIG_TX_ENABLED 0x00000004 2260 #define DCBX_ETS_RECO_TX_ENABLED 0x00000008 2261 #define DCBX_ETS_RECO_VALID 0x00000010 2262 #define DCBX_ETS_WILLING 0x00000020 2263 #define DCBX_PFC_WILLING 0x00000040 2264 #define DCBX_APP_WILLING 0x00000080 2265 #define DCBX_VERSION_CEE 0x00000100 2266 #define DCBX_VERSION_IEEE 0x00000200 2267 #define DCBX_DCBX_ENABLED 0x00000400 2268 #define DCBX_CEE_VERSION_MASK 0x0000f000 2269 #define DCBX_CEE_VERSION_SHIFT 12 2270 #define DCBX_CEE_MAX_VERSION_MASK 0x000f0000 2271 #define DCBX_CEE_MAX_VERSION_SHIFT 16 2272 struct dcbx_features features; 2273}; 2274 2275/* REMOTE MIB - remote machine DCBX configuration. */ 2276struct lldp_remote_mib { 2277 uint32_t prefix_seq_num; 2278 uint32_t flags; 2279 #define DCBX_ETS_TLV_RX 0x00000001 2280 #define DCBX_PFC_TLV_RX 0x00000002 2281 #define DCBX_APP_TLV_RX 0x00000004 2282 #define DCBX_ETS_RX_ERROR 0x00000010 2283 #define DCBX_PFC_RX_ERROR 0x00000020 2284 #define DCBX_APP_RX_ERROR 0x00000040 2285 #define DCBX_ETS_REM_WILLING 0x00000100 2286 #define DCBX_PFC_REM_WILLING 0x00000200 2287 #define DCBX_APP_REM_WILLING 0x00000400 2288 #define DCBX_REMOTE_ETS_RECO_VALID 0x00001000 2289 #define DCBX_REMOTE_MIB_VALID 0x00002000 2290 struct dcbx_features features; 2291 uint32_t suffix_seq_num; 2292}; 2293 2294/* LOCAL MIB - operational DCBX configuration - transmitted on Tx LLDPDU. */ 2295struct lldp_local_mib { 2296 uint32_t prefix_seq_num; 2297 /* Indicates if there is mismatch with negotiation results. */ 2298 uint32_t error; 2299 #define DCBX_LOCAL_ETS_ERROR 0x00000001 2300 #define DCBX_LOCAL_PFC_ERROR 0x00000002 2301 #define DCBX_LOCAL_APP_ERROR 0x00000004 2302 #define DCBX_LOCAL_PFC_MISMATCH 0x00000010 2303 #define DCBX_LOCAL_APP_MISMATCH 0x00000020 2304 #define DCBX_REMOTE_MIB_ERROR 0x00000040 2305 #define DCBX_REMOTE_ETS_TLV_NOT_FOUND 0x00000080 2306 #define DCBX_REMOTE_PFC_TLV_NOT_FOUND 0x00000100 2307 #define DCBX_REMOTE_APP_TLV_NOT_FOUND 0x00000200 2308 struct dcbx_features features; 2309 uint32_t suffix_seq_num; 2310}; 2311 2312struct lldp_local_mib_ext { 2313 uint32_t prefix_seq_num; 2314 /* APP TLV extension - 16 more entries for negotiation results*/ 2315 struct dcbx_app_priority_entry app_pri_tbl_ext[DCBX_MAX_APP_PROTOCOL]; 2316 uint32_t suffix_seq_num; 2317}; 2318/***END OF DCBX STRUCTURES DECLARATIONS***/ 2319 2320/***********************************************************/ 2321/* Elink section */ 2322/***********************************************************/ 2323#define SHMEM_LINK_CONFIG_SIZE 2 2324struct shmem_lfa { 2325 uint32_t req_duplex; 2326 #define REQ_DUPLEX_PHY0_MASK 0x0000ffff 2327 #define REQ_DUPLEX_PHY0_SHIFT 0 2328 #define REQ_DUPLEX_PHY1_MASK 0xffff0000 2329 #define REQ_DUPLEX_PHY1_SHIFT 16 2330 uint32_t req_flow_ctrl; 2331 #define REQ_FLOW_CTRL_PHY0_MASK 0x0000ffff 2332 #define REQ_FLOW_CTRL_PHY0_SHIFT 0 2333 #define REQ_FLOW_CTRL_PHY1_MASK 0xffff0000 2334 #define REQ_FLOW_CTRL_PHY1_SHIFT 16 2335 uint32_t req_line_speed; /* Also determine AutoNeg */ 2336 #define REQ_LINE_SPD_PHY0_MASK 0x0000ffff 2337 #define REQ_LINE_SPD_PHY0_SHIFT 0 2338 #define REQ_LINE_SPD_PHY1_MASK 0xffff0000 2339 #define REQ_LINE_SPD_PHY1_SHIFT 16 2340 uint32_t speed_cap_mask[SHMEM_LINK_CONFIG_SIZE]; 2341 uint32_t additional_config; 2342 #define REQ_FC_AUTO_ADV_MASK 0x0000ffff 2343 #define REQ_FC_AUTO_ADV0_SHIFT 0 2344 #define NO_LFA_DUE_TO_DCC_MASK 0x00010000 2345 uint32_t lfa_sts; 2346 #define LFA_LINK_FLAP_REASON_OFFSET 0 2347 #define LFA_LINK_FLAP_REASON_MASK 0x000000ff 2348 #define LFA_LINK_DOWN 0x1 2349 #define LFA_LOOPBACK_ENABLED 0x2 2350 #define LFA_DUPLEX_MISMATCH 0x3 2351 #define LFA_MFW_IS_TOO_OLD 0x4 2352 #define LFA_LINK_SPEED_MISMATCH 0x5 2353 #define LFA_FLOW_CTRL_MISMATCH 0x6 2354 #define LFA_SPEED_CAP_MISMATCH 0x7 2355 #define LFA_DCC_LFA_DISABLED 0x8 2356 #define LFA_EEE_MISMATCH 0x9 2357 2358 #define LINK_FLAP_AVOIDANCE_COUNT_OFFSET 8 2359 #define LINK_FLAP_AVOIDANCE_COUNT_MASK 0x0000ff00 2360 2361 #define LINK_FLAP_COUNT_OFFSET 16 2362 #define LINK_FLAP_COUNT_MASK 0x00ff0000 2363 2364 #define LFA_FLAGS_MASK 0xff000000 2365 #define SHMEM_LFA_DONT_CLEAR_STAT (1<<24) 2366 2367}; 2368 2369struct shmem2_region { 2370 2371 uint32_t size; /* 0x0000 */ 2372 2373 uint32_t dcc_support; /* 0x0004 */ 2374 #define SHMEM_DCC_SUPPORT_NONE 0x00000000 2375 #define SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV 0x00000001 2376 #define SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV 0x00000004 2377 #define SHMEM_DCC_SUPPORT_CHANGE_MAC_ADDRESS_TLV 0x00000008 2378 #define SHMEM_DCC_SUPPORT_SET_PROTOCOL_TLV 0x00000040 2379 #define SHMEM_DCC_SUPPORT_SET_PRIORITY_TLV 0x00000080 2380 2381 uint32_t ext_phy_fw_version2[PORT_MAX]; /* 0x0008 */ 2382 /* 2383 * For backwards compatibility, if the mf_cfg_addr does not exist 2384 * (the size filed is smaller than 0xc) the mf_cfg resides at the 2385 * end of struct shmem_region 2386 */ 2387 uint32_t mf_cfg_addr; /* 0x0010 */ 2388 #define SHMEM_MF_CFG_ADDR_NONE 0x00000000 2389 2390 struct fw_flr_mb flr_mb; /* 0x0014 */ 2391 uint32_t dcbx_lldp_params_offset; /* 0x0028 */ 2392 #define SHMEM_LLDP_DCBX_PARAMS_NONE 0x00000000 2393 uint32_t dcbx_neg_res_offset; /* 0x002c */ 2394 #define SHMEM_DCBX_NEG_RES_NONE 0x00000000 2395 uint32_t dcbx_remote_mib_offset; /* 0x0030 */ 2396 #define SHMEM_DCBX_REMOTE_MIB_NONE 0x00000000 2397 /* 2398 * The other shmemX_base_addr holds the other path's shmem address 2399 * required for example in case of common phy init, or for path1 to know 2400 * the address of mcp debug trace which is located in offset from shmem 2401 * of path0 2402 */ 2403 uint32_t other_shmem_base_addr; /* 0x0034 */ 2404 uint32_t other_shmem2_base_addr; /* 0x0038 */ 2405 /* 2406 * mcp_vf_disabled is set by the MCP to indicate the driver about VFs 2407 * which were disabled/flred 2408 */ 2409 uint32_t mcp_vf_disabled[E2_VF_MAX / 32]; /* 0x003c */ 2410 2411 /* 2412 * drv_ack_vf_disabled is set by the PF driver to ack handled disabled 2413 * VFs 2414 */ 2415 uint32_t drv_ack_vf_disabled[E2_FUNC_MAX][E2_VF_MAX / 32]; /* 0x0044 */ 2416 2417 uint32_t dcbx_lldp_dcbx_stat_offset; /* 0x0064 */ 2418 #define SHMEM_LLDP_DCBX_STAT_NONE 0x00000000 2419 2420 /* 2421 * edebug_driver_if field is used to transfer messages between edebug 2422 * app to the driver through shmem2. 2423 * 2424 * message format: 2425 * bits 0-2 - function number / instance of driver to perform request 2426 * bits 3-5 - op code / is_ack? 2427 * bits 6-63 - data 2428 */ 2429 uint32_t edebug_driver_if[2]; /* 0x0068 */ 2430 #define EDEBUG_DRIVER_IF_OP_CODE_GET_PHYS_ADDR 1 2431 #define EDEBUG_DRIVER_IF_OP_CODE_GET_BUS_ADDR 2 2432 #define EDEBUG_DRIVER_IF_OP_CODE_DISABLE_STAT 3 2433 2434 uint32_t nvm_retain_bitmap_addr; /* 0x0070 */ 2435 2436 /* afex support of that driver */ 2437 uint32_t afex_driver_support; /* 0x0074 */ 2438 #define SHMEM_AFEX_VERSION_MASK 0x100f 2439 #define SHMEM_AFEX_SUPPORTED_VERSION_ONE 0x1001 2440 #define SHMEM_AFEX_REDUCED_DRV_LOADED 0x8000 2441 2442 /* driver receives addr in scratchpad to which it should respond */ 2443 uint32_t afex_scratchpad_addr_to_write[E2_FUNC_MAX]; 2444 2445 /* 2446 * generic params from MCP to driver (value depends on the msg sent 2447 * to driver 2448 */ 2449 uint32_t afex_param1_to_driver[E2_FUNC_MAX]; /* 0x0088 */ 2450 uint32_t afex_param2_to_driver[E2_FUNC_MAX]; /* 0x0098 */ 2451 2452 uint32_t swim_base_addr; /* 0x0108 */ 2453 uint32_t swim_funcs; 2454 uint32_t swim_main_cb; 2455 2456 /* 2457 * bitmap notifying which VIF profiles stored in nvram are enabled by 2458 * switch 2459 */ 2460 uint32_t afex_profiles_enabled[2]; 2461 2462 /* generic flags controlled by the driver */ 2463 uint32_t drv_flags; 2464 #define DRV_FLAGS_DCB_CONFIGURED 0x0 2465 #define DRV_FLAGS_DCB_CONFIGURATION_ABORTED 0x1 2466 #define DRV_FLAGS_DCB_MFW_CONFIGURED 0x2 2467 2468 #define DRV_FLAGS_PORT_MASK ((1 << DRV_FLAGS_DCB_CONFIGURED) | \ 2469 (1 << DRV_FLAGS_DCB_CONFIGURATION_ABORTED) | \ 2470 (1 << DRV_FLAGS_DCB_MFW_CONFIGURED)) 2471 /* Port offset*/ 2472 #define DRV_FLAGS_P0_OFFSET 0 2473 #define DRV_FLAGS_P1_OFFSET 16 2474 #define DRV_FLAGS_GET_PORT_OFFSET(_port) ((0 == _port) ? \ 2475 DRV_FLAGS_P0_OFFSET : \ 2476 DRV_FLAGS_P1_OFFSET) 2477 2478 #define DRV_FLAGS_GET_PORT_MASK(_port) (DRV_FLAGS_PORT_MASK << \ 2479 DRV_FLAGS_GET_PORT_OFFSET(_port)) 2480 2481 #define DRV_FLAGS_FILED_BY_PORT(_field_bit, _port) (1 << ( \ 2482 (_field_bit) + DRV_FLAGS_GET_PORT_OFFSET(_port))) 2483 2484 /* pointer to extended dev_info shared data copied from nvm image */ 2485 uint32_t extended_dev_info_shared_addr; 2486 uint32_t ncsi_oem_data_addr; 2487 2488 uint32_t sensor_data_addr; 2489 uint32_t buffer_block_addr; 2490 uint32_t sensor_data_req_update_interval; 2491 uint32_t temperature_in_half_celsius; 2492 uint32_t glob_struct_in_host; 2493 2494 uint32_t dcbx_neg_res_ext_offset; 2495 #define SHMEM_DCBX_NEG_RES_EXT_NONE 0x00000000 2496 2497 uint32_t drv_capabilities_flag[E2_FUNC_MAX]; 2498 #define DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED 0x00000001 2499 #define DRV_FLAGS_CAPABILITIES_LOADED_L2 0x00000002 2500 #define DRV_FLAGS_CAPABILITIES_LOADED_FCOE 0x00000004 2501 #define DRV_FLAGS_CAPABILITIES_LOADED_ISCSI 0x00000008 2502 2503 uint32_t extended_dev_info_shared_cfg_size; 2504 2505 uint32_t dcbx_en[PORT_MAX]; 2506 2507 /* The offset points to the multi threaded meta structure */ 2508 uint32_t multi_thread_data_offset; 2509 2510 /* address of DMAable host address holding values from the drivers */ 2511 uint32_t drv_info_host_addr_lo; 2512 uint32_t drv_info_host_addr_hi; 2513 2514 /* general values written by the MFW (such as current version) */ 2515 uint32_t drv_info_control; 2516 #define DRV_INFO_CONTROL_VER_MASK 0x000000ff 2517 #define DRV_INFO_CONTROL_VER_SHIFT 0 2518 #define DRV_INFO_CONTROL_OP_CODE_MASK 0x0000ff00 2519 #define DRV_INFO_CONTROL_OP_CODE_SHIFT 8 2520 uint32_t ibft_host_addr; /* initialized by option ROM */ 2521 2522 struct eee_remote_vals eee_remote_vals[PORT_MAX]; 2523 uint32_t pf_allocation[E2_FUNC_MAX]; 2524 #define PF_ALLOACTION_MSIX_VECTORS_MASK 0x000000ff /* real value, as PCI config space can show only maximum of 64 vectors */ 2525 #define PF_ALLOACTION_MSIX_VECTORS_SHIFT 0 2526 2527 /* the status of EEE auto-negotiation 2528 * bits 15:0 the configured tx-lpi entry timer value. Depends on bit 31. 2529 * bits 19:16 the supported modes for EEE. 2530 * bits 23:20 the speeds advertised for EEE. 2531 * bits 27:24 the speeds the Link partner advertised for EEE. 2532 * The supported/adv. modes in bits 27:19 originate from the 2533 * SHMEM_EEE_XXX_ADV definitions (where XXX is replaced by speed). 2534 * bit 28 when 1'b1 EEE was requested. 2535 * bit 29 when 1'b1 tx lpi was requested. 2536 * bit 30 when 1'b1 EEE was negotiated. Tx lpi will be asserted iff 2537 * 30:29 are 2'b11. 2538 * bit 31 when 1'b0 bits 15:0 contain a PORT_FEAT_CFG_EEE_ define as 2539 * value. When 1'b1 those bits contains a value times 16 microseconds. 2540 */ 2541 uint32_t eee_status[PORT_MAX]; 2542 #define SHMEM_EEE_TIMER_MASK 0x0000ffff 2543 #define SHMEM_EEE_SUPPORTED_MASK 0x000f0000 2544 #define SHMEM_EEE_SUPPORTED_SHIFT 16 2545 #define SHMEM_EEE_ADV_STATUS_MASK 0x00f00000 2546 #define SHMEM_EEE_100M_ADV (1<<0) 2547 #define SHMEM_EEE_1G_ADV (1<<1) 2548 #define SHMEM_EEE_10G_ADV (1<<2) 2549 #define SHMEM_EEE_ADV_STATUS_SHIFT 20 2550 #define SHMEM_EEE_LP_ADV_STATUS_MASK 0x0f000000 2551 #define SHMEM_EEE_LP_ADV_STATUS_SHIFT 24 2552 #define SHMEM_EEE_REQUESTED_BIT 0x10000000 2553 #define SHMEM_EEE_LPI_REQUESTED_BIT 0x20000000 2554 #define SHMEM_EEE_ACTIVE_BIT 0x40000000 2555 #define SHMEM_EEE_TIME_OUTPUT_BIT 0x80000000 2556 2557 uint32_t sizeof_port_stats; 2558 2559 /* Link Flap Avoidance */ 2560 uint32_t lfa_host_addr[PORT_MAX]; 2561 2562 /* External PHY temperature in deg C. */ 2563 uint32_t extphy_temps_in_celsius; 2564 #define EXTPHY1_TEMP_MASK 0x0000ffff 2565 #define EXTPHY1_TEMP_SHIFT 0 2566 2567 uint32_t ocdata_info_addr; /* Offset 0x148 */ 2568 uint32_t drv_func_info_addr; /* Offset 0x14C */ 2569 uint32_t drv_func_info_size; /* Offset 0x150 */ 2570 uint32_t link_attr_sync[PORT_MAX]; /* Offset 0x154 */ 2571 #define LINK_ATTR_SYNC_KR2_ENABLE (1<<0) 2572 2573 uint32_t ibft_host_addr_hi; /* Initialize by uEFI ROM */ 2574}; 2575 2576 2577struct emac_stats { 2578 uint32_t rx_stat_ifhcinoctets; 2579 uint32_t rx_stat_ifhcinbadoctets; 2580 uint32_t rx_stat_etherstatsfragments; 2581 uint32_t rx_stat_ifhcinucastpkts; 2582 uint32_t rx_stat_ifhcinmulticastpkts; 2583 uint32_t rx_stat_ifhcinbroadcastpkts; 2584 uint32_t rx_stat_dot3statsfcserrors; 2585 uint32_t rx_stat_dot3statsalignmenterrors; 2586 uint32_t rx_stat_dot3statscarriersenseerrors; 2587 uint32_t rx_stat_xonpauseframesreceived; 2588 uint32_t rx_stat_xoffpauseframesreceived; 2589 uint32_t rx_stat_maccontrolframesreceived; 2590 uint32_t rx_stat_xoffstateentered; 2591 uint32_t rx_stat_dot3statsframestoolong; 2592 uint32_t rx_stat_etherstatsjabbers; 2593 uint32_t rx_stat_etherstatsundersizepkts; 2594 uint32_t rx_stat_etherstatspkts64octets; 2595 uint32_t rx_stat_etherstatspkts65octetsto127octets; 2596 uint32_t rx_stat_etherstatspkts128octetsto255octets; 2597 uint32_t rx_stat_etherstatspkts256octetsto511octets; 2598 uint32_t rx_stat_etherstatspkts512octetsto1023octets; 2599 uint32_t rx_stat_etherstatspkts1024octetsto1522octets; 2600 uint32_t rx_stat_etherstatspktsover1522octets; 2601 2602 uint32_t rx_stat_falsecarriererrors; 2603 2604 uint32_t tx_stat_ifhcoutoctets; 2605 uint32_t tx_stat_ifhcoutbadoctets; 2606 uint32_t tx_stat_etherstatscollisions; 2607 uint32_t tx_stat_outxonsent; 2608 uint32_t tx_stat_outxoffsent; 2609 uint32_t tx_stat_flowcontroldone; 2610 uint32_t tx_stat_dot3statssinglecollisionframes; 2611 uint32_t tx_stat_dot3statsmultiplecollisionframes; 2612 uint32_t tx_stat_dot3statsdeferredtransmissions; 2613 uint32_t tx_stat_dot3statsexcessivecollisions; 2614 uint32_t tx_stat_dot3statslatecollisions; 2615 uint32_t tx_stat_ifhcoutucastpkts; 2616 uint32_t tx_stat_ifhcoutmulticastpkts; 2617 uint32_t tx_stat_ifhcoutbroadcastpkts; 2618 uint32_t tx_stat_etherstatspkts64octets; 2619 uint32_t tx_stat_etherstatspkts65octetsto127octets; 2620 uint32_t tx_stat_etherstatspkts128octetsto255octets; 2621 uint32_t tx_stat_etherstatspkts256octetsto511octets; 2622 uint32_t tx_stat_etherstatspkts512octetsto1023octets; 2623 uint32_t tx_stat_etherstatspkts1024octetsto1522octets; 2624 uint32_t tx_stat_etherstatspktsover1522octets; 2625 uint32_t tx_stat_dot3statsinternalmactransmiterrors; 2626}; 2627 2628 2629struct bmac1_stats { 2630 uint32_t tx_stat_gtpkt_lo; 2631 uint32_t tx_stat_gtpkt_hi; 2632 uint32_t tx_stat_gtxpf_lo; 2633 uint32_t tx_stat_gtxpf_hi; 2634 uint32_t tx_stat_gtfcs_lo; 2635 uint32_t tx_stat_gtfcs_hi; 2636 uint32_t tx_stat_gtmca_lo; 2637 uint32_t tx_stat_gtmca_hi; 2638 uint32_t tx_stat_gtbca_lo; 2639 uint32_t tx_stat_gtbca_hi; 2640 uint32_t tx_stat_gtfrg_lo; 2641 uint32_t tx_stat_gtfrg_hi; 2642 uint32_t tx_stat_gtovr_lo; 2643 uint32_t tx_stat_gtovr_hi; 2644 uint32_t tx_stat_gt64_lo; 2645 uint32_t tx_stat_gt64_hi; 2646 uint32_t tx_stat_gt127_lo; 2647 uint32_t tx_stat_gt127_hi; 2648 uint32_t tx_stat_gt255_lo; 2649 uint32_t tx_stat_gt255_hi; 2650 uint32_t tx_stat_gt511_lo; 2651 uint32_t tx_stat_gt511_hi; 2652 uint32_t tx_stat_gt1023_lo; 2653 uint32_t tx_stat_gt1023_hi; 2654 uint32_t tx_stat_gt1518_lo; 2655 uint32_t tx_stat_gt1518_hi; 2656 uint32_t tx_stat_gt2047_lo; 2657 uint32_t tx_stat_gt2047_hi; 2658 uint32_t tx_stat_gt4095_lo; 2659 uint32_t tx_stat_gt4095_hi; 2660 uint32_t tx_stat_gt9216_lo; 2661 uint32_t tx_stat_gt9216_hi; 2662 uint32_t tx_stat_gt16383_lo; 2663 uint32_t tx_stat_gt16383_hi; 2664 uint32_t tx_stat_gtmax_lo; 2665 uint32_t tx_stat_gtmax_hi; 2666 uint32_t tx_stat_gtufl_lo; 2667 uint32_t tx_stat_gtufl_hi; 2668 uint32_t tx_stat_gterr_lo; 2669 uint32_t tx_stat_gterr_hi; 2670 uint32_t tx_stat_gtbyt_lo; 2671 uint32_t tx_stat_gtbyt_hi; 2672 2673 uint32_t rx_stat_gr64_lo; 2674 uint32_t rx_stat_gr64_hi; 2675 uint32_t rx_stat_gr127_lo; 2676 uint32_t rx_stat_gr127_hi; 2677 uint32_t rx_stat_gr255_lo; 2678 uint32_t rx_stat_gr255_hi; 2679 uint32_t rx_stat_gr511_lo; 2680 uint32_t rx_stat_gr511_hi; 2681 uint32_t rx_stat_gr1023_lo; 2682 uint32_t rx_stat_gr1023_hi; 2683 uint32_t rx_stat_gr1518_lo; 2684 uint32_t rx_stat_gr1518_hi; 2685 uint32_t rx_stat_gr2047_lo; 2686 uint32_t rx_stat_gr2047_hi; 2687 uint32_t rx_stat_gr4095_lo; 2688 uint32_t rx_stat_gr4095_hi; 2689 uint32_t rx_stat_gr9216_lo; 2690 uint32_t rx_stat_gr9216_hi; 2691 uint32_t rx_stat_gr16383_lo; 2692 uint32_t rx_stat_gr16383_hi; 2693 uint32_t rx_stat_grmax_lo; 2694 uint32_t rx_stat_grmax_hi; 2695 uint32_t rx_stat_grpkt_lo; 2696 uint32_t rx_stat_grpkt_hi; 2697 uint32_t rx_stat_grfcs_lo; 2698 uint32_t rx_stat_grfcs_hi; 2699 uint32_t rx_stat_grmca_lo; 2700 uint32_t rx_stat_grmca_hi; 2701 uint32_t rx_stat_grbca_lo; 2702 uint32_t rx_stat_grbca_hi; 2703 uint32_t rx_stat_grxcf_lo; 2704 uint32_t rx_stat_grxcf_hi; 2705 uint32_t rx_stat_grxpf_lo; 2706 uint32_t rx_stat_grxpf_hi; 2707 uint32_t rx_stat_grxuo_lo; 2708 uint32_t rx_stat_grxuo_hi; 2709 uint32_t rx_stat_grjbr_lo; 2710 uint32_t rx_stat_grjbr_hi; 2711 uint32_t rx_stat_grovr_lo; 2712 uint32_t rx_stat_grovr_hi; 2713 uint32_t rx_stat_grflr_lo; 2714 uint32_t rx_stat_grflr_hi; 2715 uint32_t rx_stat_grmeg_lo; 2716 uint32_t rx_stat_grmeg_hi; 2717 uint32_t rx_stat_grmeb_lo; 2718 uint32_t rx_stat_grmeb_hi; 2719 uint32_t rx_stat_grbyt_lo; 2720 uint32_t rx_stat_grbyt_hi; 2721 uint32_t rx_stat_grund_lo; 2722 uint32_t rx_stat_grund_hi; 2723 uint32_t rx_stat_grfrg_lo; 2724 uint32_t rx_stat_grfrg_hi; 2725 uint32_t rx_stat_grerb_lo; 2726 uint32_t rx_stat_grerb_hi; 2727 uint32_t rx_stat_grfre_lo; 2728 uint32_t rx_stat_grfre_hi; 2729 uint32_t rx_stat_gripj_lo; 2730 uint32_t rx_stat_gripj_hi; 2731}; 2732 2733struct bmac2_stats { 2734 uint32_t tx_stat_gtpk_lo; /* gtpok */ 2735 uint32_t tx_stat_gtpk_hi; /* gtpok */ 2736 uint32_t tx_stat_gtxpf_lo; /* gtpf */ 2737 uint32_t tx_stat_gtxpf_hi; /* gtpf */ 2738 uint32_t tx_stat_gtpp_lo; /* NEW BMAC2 */ 2739 uint32_t tx_stat_gtpp_hi; /* NEW BMAC2 */ 2740 uint32_t tx_stat_gtfcs_lo; 2741 uint32_t tx_stat_gtfcs_hi; 2742 uint32_t tx_stat_gtuca_lo; /* NEW BMAC2 */ 2743 uint32_t tx_stat_gtuca_hi; /* NEW BMAC2 */ 2744 uint32_t tx_stat_gtmca_lo; 2745 uint32_t tx_stat_gtmca_hi; 2746 uint32_t tx_stat_gtbca_lo; 2747 uint32_t tx_stat_gtbca_hi; 2748 uint32_t tx_stat_gtovr_lo; 2749 uint32_t tx_stat_gtovr_hi; 2750 uint32_t tx_stat_gtfrg_lo; 2751 uint32_t tx_stat_gtfrg_hi; 2752 uint32_t tx_stat_gtpkt1_lo; /* gtpkt */ 2753 uint32_t tx_stat_gtpkt1_hi; /* gtpkt */ 2754 uint32_t tx_stat_gt64_lo; 2755 uint32_t tx_stat_gt64_hi; 2756 uint32_t tx_stat_gt127_lo; 2757 uint32_t tx_stat_gt127_hi; 2758 uint32_t tx_stat_gt255_lo; 2759 uint32_t tx_stat_gt255_hi; 2760 uint32_t tx_stat_gt511_lo; 2761 uint32_t tx_stat_gt511_hi; 2762 uint32_t tx_stat_gt1023_lo; 2763 uint32_t tx_stat_gt1023_hi; 2764 uint32_t tx_stat_gt1518_lo; 2765 uint32_t tx_stat_gt1518_hi; 2766 uint32_t tx_stat_gt2047_lo; 2767 uint32_t tx_stat_gt2047_hi; 2768 uint32_t tx_stat_gt4095_lo; 2769 uint32_t tx_stat_gt4095_hi; 2770 uint32_t tx_stat_gt9216_lo; 2771 uint32_t tx_stat_gt9216_hi; 2772 uint32_t tx_stat_gt16383_lo; 2773 uint32_t tx_stat_gt16383_hi; 2774 uint32_t tx_stat_gtmax_lo; 2775 uint32_t tx_stat_gtmax_hi; 2776 uint32_t tx_stat_gtufl_lo; 2777 uint32_t tx_stat_gtufl_hi; 2778 uint32_t tx_stat_gterr_lo; 2779 uint32_t tx_stat_gterr_hi; 2780 uint32_t tx_stat_gtbyt_lo; 2781 uint32_t tx_stat_gtbyt_hi; 2782 2783 uint32_t rx_stat_gr64_lo; 2784 uint32_t rx_stat_gr64_hi; 2785 uint32_t rx_stat_gr127_lo; 2786 uint32_t rx_stat_gr127_hi; 2787 uint32_t rx_stat_gr255_lo; 2788 uint32_t rx_stat_gr255_hi; 2789 uint32_t rx_stat_gr511_lo; 2790 uint32_t rx_stat_gr511_hi; 2791 uint32_t rx_stat_gr1023_lo; 2792 uint32_t rx_stat_gr1023_hi; 2793 uint32_t rx_stat_gr1518_lo; 2794 uint32_t rx_stat_gr1518_hi; 2795 uint32_t rx_stat_gr2047_lo; 2796 uint32_t rx_stat_gr2047_hi; 2797 uint32_t rx_stat_gr4095_lo; 2798 uint32_t rx_stat_gr4095_hi; 2799 uint32_t rx_stat_gr9216_lo; 2800 uint32_t rx_stat_gr9216_hi; 2801 uint32_t rx_stat_gr16383_lo; 2802 uint32_t rx_stat_gr16383_hi; 2803 uint32_t rx_stat_grmax_lo; 2804 uint32_t rx_stat_grmax_hi; 2805 uint32_t rx_stat_grpkt_lo; 2806 uint32_t rx_stat_grpkt_hi; 2807 uint32_t rx_stat_grfcs_lo; 2808 uint32_t rx_stat_grfcs_hi; 2809 uint32_t rx_stat_gruca_lo; 2810 uint32_t rx_stat_gruca_hi; 2811 uint32_t rx_stat_grmca_lo; 2812 uint32_t rx_stat_grmca_hi; 2813 uint32_t rx_stat_grbca_lo; 2814 uint32_t rx_stat_grbca_hi; 2815 uint32_t rx_stat_grxpf_lo; /* grpf */ 2816 uint32_t rx_stat_grxpf_hi; /* grpf */ 2817 uint32_t rx_stat_grpp_lo; 2818 uint32_t rx_stat_grpp_hi; 2819 uint32_t rx_stat_grxuo_lo; /* gruo */ 2820 uint32_t rx_stat_grxuo_hi; /* gruo */ 2821 uint32_t rx_stat_grjbr_lo; 2822 uint32_t rx_stat_grjbr_hi; 2823 uint32_t rx_stat_grovr_lo; 2824 uint32_t rx_stat_grovr_hi; 2825 uint32_t rx_stat_grxcf_lo; /* grcf */ 2826 uint32_t rx_stat_grxcf_hi; /* grcf */ 2827 uint32_t rx_stat_grflr_lo; 2828 uint32_t rx_stat_grflr_hi; 2829 uint32_t rx_stat_grpok_lo; 2830 uint32_t rx_stat_grpok_hi; 2831 uint32_t rx_stat_grmeg_lo; 2832 uint32_t rx_stat_grmeg_hi; 2833 uint32_t rx_stat_grmeb_lo; 2834 uint32_t rx_stat_grmeb_hi; 2835 uint32_t rx_stat_grbyt_lo; 2836 uint32_t rx_stat_grbyt_hi; 2837 uint32_t rx_stat_grund_lo; 2838 uint32_t rx_stat_grund_hi; 2839 uint32_t rx_stat_grfrg_lo; 2840 uint32_t rx_stat_grfrg_hi; 2841 uint32_t rx_stat_grerb_lo; /* grerrbyt */ 2842 uint32_t rx_stat_grerb_hi; /* grerrbyt */ 2843 uint32_t rx_stat_grfre_lo; /* grfrerr */ 2844 uint32_t rx_stat_grfre_hi; /* grfrerr */ 2845 uint32_t rx_stat_gripj_lo; 2846 uint32_t rx_stat_gripj_hi; 2847}; 2848 2849struct mstat_stats { 2850 struct { 2851 /* OTE MSTAT on E3 has a bug where this register's contents are 2852 * actually tx_gtxpok + tx_gtxpf + (possibly)tx_gtxpp 2853 */ 2854 uint32_t tx_gtxpok_lo; 2855 uint32_t tx_gtxpok_hi; 2856 uint32_t tx_gtxpf_lo; 2857 uint32_t tx_gtxpf_hi; 2858 uint32_t tx_gtxpp_lo; 2859 uint32_t tx_gtxpp_hi; 2860 uint32_t tx_gtfcs_lo; 2861 uint32_t tx_gtfcs_hi; 2862 uint32_t tx_gtuca_lo; 2863 uint32_t tx_gtuca_hi; 2864 uint32_t tx_gtmca_lo; 2865 uint32_t tx_gtmca_hi; 2866 uint32_t tx_gtgca_lo; 2867 uint32_t tx_gtgca_hi; 2868 uint32_t tx_gtpkt_lo; 2869 uint32_t tx_gtpkt_hi; 2870 uint32_t tx_gt64_lo; 2871 uint32_t tx_gt64_hi; 2872 uint32_t tx_gt127_lo; 2873 uint32_t tx_gt127_hi; 2874 uint32_t tx_gt255_lo; 2875 uint32_t tx_gt255_hi; 2876 uint32_t tx_gt511_lo; 2877 uint32_t tx_gt511_hi; 2878 uint32_t tx_gt1023_lo; 2879 uint32_t tx_gt1023_hi; 2880 uint32_t tx_gt1518_lo; 2881 uint32_t tx_gt1518_hi; 2882 uint32_t tx_gt2047_lo; 2883 uint32_t tx_gt2047_hi; 2884 uint32_t tx_gt4095_lo; 2885 uint32_t tx_gt4095_hi; 2886 uint32_t tx_gt9216_lo; 2887 uint32_t tx_gt9216_hi; 2888 uint32_t tx_gt16383_lo; 2889 uint32_t tx_gt16383_hi; 2890 uint32_t tx_gtufl_lo; 2891 uint32_t tx_gtufl_hi; 2892 uint32_t tx_gterr_lo; 2893 uint32_t tx_gterr_hi; 2894 uint32_t tx_gtbyt_lo; 2895 uint32_t tx_gtbyt_hi; 2896 uint32_t tx_collisions_lo; 2897 uint32_t tx_collisions_hi; 2898 uint32_t tx_singlecollision_lo; 2899 uint32_t tx_singlecollision_hi; 2900 uint32_t tx_multiplecollisions_lo; 2901 uint32_t tx_multiplecollisions_hi; 2902 uint32_t tx_deferred_lo; 2903 uint32_t tx_deferred_hi; 2904 uint32_t tx_excessivecollisions_lo; 2905 uint32_t tx_excessivecollisions_hi; 2906 uint32_t tx_latecollisions_lo; 2907 uint32_t tx_latecollisions_hi; 2908 } stats_tx; 2909 2910 struct { 2911 uint32_t rx_gr64_lo; 2912 uint32_t rx_gr64_hi; 2913 uint32_t rx_gr127_lo; 2914 uint32_t rx_gr127_hi; 2915 uint32_t rx_gr255_lo; 2916 uint32_t rx_gr255_hi; 2917 uint32_t rx_gr511_lo; 2918 uint32_t rx_gr511_hi; 2919 uint32_t rx_gr1023_lo; 2920 uint32_t rx_gr1023_hi; 2921 uint32_t rx_gr1518_lo; 2922 uint32_t rx_gr1518_hi; 2923 uint32_t rx_gr2047_lo; 2924 uint32_t rx_gr2047_hi; 2925 uint32_t rx_gr4095_lo; 2926 uint32_t rx_gr4095_hi; 2927 uint32_t rx_gr9216_lo; 2928 uint32_t rx_gr9216_hi; 2929 uint32_t rx_gr16383_lo; 2930 uint32_t rx_gr16383_hi; 2931 uint32_t rx_grpkt_lo; 2932 uint32_t rx_grpkt_hi; 2933 uint32_t rx_grfcs_lo; 2934 uint32_t rx_grfcs_hi; 2935 uint32_t rx_gruca_lo; 2936 uint32_t rx_gruca_hi; 2937 uint32_t rx_grmca_lo; 2938 uint32_t rx_grmca_hi; 2939 uint32_t rx_grbca_lo; 2940 uint32_t rx_grbca_hi; 2941 uint32_t rx_grxpf_lo; 2942 uint32_t rx_grxpf_hi; 2943 uint32_t rx_grxpp_lo; 2944 uint32_t rx_grxpp_hi; 2945 uint32_t rx_grxuo_lo; 2946 uint32_t rx_grxuo_hi; 2947 uint32_t rx_grovr_lo; 2948 uint32_t rx_grovr_hi; 2949 uint32_t rx_grxcf_lo; 2950 uint32_t rx_grxcf_hi; 2951 uint32_t rx_grflr_lo; 2952 uint32_t rx_grflr_hi; 2953 uint32_t rx_grpok_lo; 2954 uint32_t rx_grpok_hi; 2955 uint32_t rx_grbyt_lo; 2956 uint32_t rx_grbyt_hi; 2957 uint32_t rx_grund_lo; 2958 uint32_t rx_grund_hi; 2959 uint32_t rx_grfrg_lo; 2960 uint32_t rx_grfrg_hi; 2961 uint32_t rx_grerb_lo; 2962 uint32_t rx_grerb_hi; 2963 uint32_t rx_grfre_lo; 2964 uint32_t rx_grfre_hi; 2965 2966 uint32_t rx_alignmenterrors_lo; 2967 uint32_t rx_alignmenterrors_hi; 2968 uint32_t rx_falsecarrier_lo; 2969 uint32_t rx_falsecarrier_hi; 2970 uint32_t rx_llfcmsgcnt_lo; 2971 uint32_t rx_llfcmsgcnt_hi; 2972 } stats_rx; 2973}; 2974 2975union mac_stats { 2976 struct emac_stats emac_stats; 2977 struct bmac1_stats bmac1_stats; 2978 struct bmac2_stats bmac2_stats; 2979 struct mstat_stats mstat_stats; 2980}; 2981 2982 2983struct mac_stx { 2984 /* in_bad_octets */ 2985 uint32_t rx_stat_ifhcinbadoctets_hi; 2986 uint32_t rx_stat_ifhcinbadoctets_lo; 2987 2988 /* out_bad_octets */ 2989 uint32_t tx_stat_ifhcoutbadoctets_hi; 2990 uint32_t tx_stat_ifhcoutbadoctets_lo; 2991 2992 /* crc_receive_errors */ 2993 uint32_t rx_stat_dot3statsfcserrors_hi; 2994 uint32_t rx_stat_dot3statsfcserrors_lo; 2995 /* alignment_errors */ 2996 uint32_t rx_stat_dot3statsalignmenterrors_hi; 2997 uint32_t rx_stat_dot3statsalignmenterrors_lo; 2998 /* carrier_sense_errors */ 2999 uint32_t rx_stat_dot3statscarriersenseerrors_hi; 3000 uint32_t rx_stat_dot3statscarriersenseerrors_lo; 3001 /* false_carrier_detections */ 3002 uint32_t rx_stat_falsecarriererrors_hi; 3003 uint32_t rx_stat_falsecarriererrors_lo; 3004 3005 /* runt_packets_received */ 3006 uint32_t rx_stat_etherstatsundersizepkts_hi; 3007 uint32_t rx_stat_etherstatsundersizepkts_lo; 3008 /* jabber_packets_received */ 3009 uint32_t rx_stat_dot3statsframestoolong_hi; 3010 uint32_t rx_stat_dot3statsframestoolong_lo; 3011 3012 /* error_runt_packets_received */ 3013 uint32_t rx_stat_etherstatsfragments_hi; 3014 uint32_t rx_stat_etherstatsfragments_lo; 3015 /* error_jabber_packets_received */ 3016 uint32_t rx_stat_etherstatsjabbers_hi; 3017 uint32_t rx_stat_etherstatsjabbers_lo; 3018 3019 /* control_frames_received */ 3020 uint32_t rx_stat_maccontrolframesreceived_hi; 3021 uint32_t rx_stat_maccontrolframesreceived_lo; 3022 uint32_t rx_stat_mac_xpf_hi; 3023 uint32_t rx_stat_mac_xpf_lo; 3024 uint32_t rx_stat_mac_xcf_hi; 3025 uint32_t rx_stat_mac_xcf_lo; 3026 3027 /* xoff_state_entered */ 3028 uint32_t rx_stat_xoffstateentered_hi; 3029 uint32_t rx_stat_xoffstateentered_lo; 3030 /* pause_xon_frames_received */ 3031 uint32_t rx_stat_xonpauseframesreceived_hi; 3032 uint32_t rx_stat_xonpauseframesreceived_lo; 3033 /* pause_xoff_frames_received */ 3034 uint32_t rx_stat_xoffpauseframesreceived_hi; 3035 uint32_t rx_stat_xoffpauseframesreceived_lo; 3036 /* pause_xon_frames_transmitted */ 3037 uint32_t tx_stat_outxonsent_hi; 3038 uint32_t tx_stat_outxonsent_lo; 3039 /* pause_xoff_frames_transmitted */ 3040 uint32_t tx_stat_outxoffsent_hi; 3041 uint32_t tx_stat_outxoffsent_lo; 3042 /* flow_control_done */ 3043 uint32_t tx_stat_flowcontroldone_hi; 3044 uint32_t tx_stat_flowcontroldone_lo; 3045 3046 /* ether_stats_collisions */ 3047 uint32_t tx_stat_etherstatscollisions_hi; 3048 uint32_t tx_stat_etherstatscollisions_lo; 3049 /* single_collision_transmit_frames */ 3050 uint32_t tx_stat_dot3statssinglecollisionframes_hi; 3051 uint32_t tx_stat_dot3statssinglecollisionframes_lo; 3052 /* multiple_collision_transmit_frames */ 3053 uint32_t tx_stat_dot3statsmultiplecollisionframes_hi; 3054 uint32_t tx_stat_dot3statsmultiplecollisionframes_lo; 3055 /* deferred_transmissions */ 3056 uint32_t tx_stat_dot3statsdeferredtransmissions_hi; 3057 uint32_t tx_stat_dot3statsdeferredtransmissions_lo; 3058 /* excessive_collision_frames */ 3059 uint32_t tx_stat_dot3statsexcessivecollisions_hi; 3060 uint32_t tx_stat_dot3statsexcessivecollisions_lo; 3061 /* late_collision_frames */ 3062 uint32_t tx_stat_dot3statslatecollisions_hi; 3063 uint32_t tx_stat_dot3statslatecollisions_lo; 3064 3065 /* frames_transmitted_64_bytes */ 3066 uint32_t tx_stat_etherstatspkts64octets_hi; 3067 uint32_t tx_stat_etherstatspkts64octets_lo; 3068 /* frames_transmitted_65_127_bytes */ 3069 uint32_t tx_stat_etherstatspkts65octetsto127octets_hi; 3070 uint32_t tx_stat_etherstatspkts65octetsto127octets_lo; 3071 /* frames_transmitted_128_255_bytes */ 3072 uint32_t tx_stat_etherstatspkts128octetsto255octets_hi; 3073 uint32_t tx_stat_etherstatspkts128octetsto255octets_lo; 3074 /* frames_transmitted_256_511_bytes */ 3075 uint32_t tx_stat_etherstatspkts256octetsto511octets_hi; 3076 uint32_t tx_stat_etherstatspkts256octetsto511octets_lo; 3077 /* frames_transmitted_512_1023_bytes */ 3078 uint32_t tx_stat_etherstatspkts512octetsto1023octets_hi; 3079 uint32_t tx_stat_etherstatspkts512octetsto1023octets_lo; 3080 /* frames_transmitted_1024_1522_bytes */ 3081 uint32_t tx_stat_etherstatspkts1024octetsto1522octets_hi; 3082 uint32_t tx_stat_etherstatspkts1024octetsto1522octets_lo; 3083 /* frames_transmitted_1523_9022_bytes */ 3084 uint32_t tx_stat_etherstatspktsover1522octets_hi; 3085 uint32_t tx_stat_etherstatspktsover1522octets_lo; 3086 uint32_t tx_stat_mac_2047_hi; 3087 uint32_t tx_stat_mac_2047_lo; 3088 uint32_t tx_stat_mac_4095_hi; 3089 uint32_t tx_stat_mac_4095_lo; 3090 uint32_t tx_stat_mac_9216_hi; 3091 uint32_t tx_stat_mac_9216_lo; 3092 uint32_t tx_stat_mac_16383_hi; 3093 uint32_t tx_stat_mac_16383_lo; 3094 3095 /* internal_mac_transmit_errors */ 3096 uint32_t tx_stat_dot3statsinternalmactransmiterrors_hi; 3097 uint32_t tx_stat_dot3statsinternalmactransmiterrors_lo; 3098 3099 /* if_out_discards */ 3100 uint32_t tx_stat_mac_ufl_hi; 3101 uint32_t tx_stat_mac_ufl_lo; 3102}; 3103 3104 3105#define MAC_STX_IDX_MAX 2 3106 3107struct host_port_stats { 3108 uint32_t host_port_stats_counter; 3109 3110 struct mac_stx mac_stx[MAC_STX_IDX_MAX]; 3111 3112 uint32_t brb_drop_hi; 3113 uint32_t brb_drop_lo; 3114 3115 uint32_t not_used; /* obsolete as of MFW 7.2.1 */ 3116 3117 uint32_t pfc_frames_tx_hi; 3118 uint32_t pfc_frames_tx_lo; 3119 uint32_t pfc_frames_rx_hi; 3120 uint32_t pfc_frames_rx_lo; 3121 3122 uint32_t eee_lpi_count_hi; 3123 uint32_t eee_lpi_count_lo; 3124}; 3125 3126 3127struct host_func_stats { 3128 uint32_t host_func_stats_start; 3129 3130 uint32_t total_bytes_received_hi; 3131 uint32_t total_bytes_received_lo; 3132 3133 uint32_t total_bytes_transmitted_hi; 3134 uint32_t total_bytes_transmitted_lo; 3135 3136 uint32_t total_unicast_packets_received_hi; 3137 uint32_t total_unicast_packets_received_lo; 3138 3139 uint32_t total_multicast_packets_received_hi; 3140 uint32_t total_multicast_packets_received_lo; 3141 3142 uint32_t total_broadcast_packets_received_hi; 3143 uint32_t total_broadcast_packets_received_lo; 3144 3145 uint32_t total_unicast_packets_transmitted_hi; 3146 uint32_t total_unicast_packets_transmitted_lo; 3147 3148 uint32_t total_multicast_packets_transmitted_hi; 3149 uint32_t total_multicast_packets_transmitted_lo; 3150 3151 uint32_t total_broadcast_packets_transmitted_hi; 3152 uint32_t total_broadcast_packets_transmitted_lo; 3153 3154 uint32_t valid_bytes_received_hi; 3155 uint32_t valid_bytes_received_lo; 3156 3157 uint32_t host_func_stats_end; 3158}; 3159 3160/* VIC definitions */ 3161#define VICSTATST_UIF_INDEX 2 3162 3163/* 3164 * stats collected for afex. 3165 * NOTE: structure is exactly as expected to be received by the switch. 3166 * order must remain exactly as is unless protocol changes ! 3167 */ 3168struct afex_stats { 3169 uint32_t tx_unicast_frames_hi; 3170 uint32_t tx_unicast_frames_lo; 3171 uint32_t tx_unicast_bytes_hi; 3172 uint32_t tx_unicast_bytes_lo; 3173 uint32_t tx_multicast_frames_hi; 3174 uint32_t tx_multicast_frames_lo; 3175 uint32_t tx_multicast_bytes_hi; 3176 uint32_t tx_multicast_bytes_lo; 3177 uint32_t tx_broadcast_frames_hi; 3178 uint32_t tx_broadcast_frames_lo; 3179 uint32_t tx_broadcast_bytes_hi; 3180 uint32_t tx_broadcast_bytes_lo; 3181 uint32_t tx_frames_discarded_hi; 3182 uint32_t tx_frames_discarded_lo; 3183 uint32_t tx_frames_dropped_hi; 3184 uint32_t tx_frames_dropped_lo; 3185 3186 uint32_t rx_unicast_frames_hi; 3187 uint32_t rx_unicast_frames_lo; 3188 uint32_t rx_unicast_bytes_hi; 3189 uint32_t rx_unicast_bytes_lo; 3190 uint32_t rx_multicast_frames_hi; 3191 uint32_t rx_multicast_frames_lo; 3192 uint32_t rx_multicast_bytes_hi; 3193 uint32_t rx_multicast_bytes_lo; 3194 uint32_t rx_broadcast_frames_hi; 3195 uint32_t rx_broadcast_frames_lo; 3196 uint32_t rx_broadcast_bytes_hi; 3197 uint32_t rx_broadcast_bytes_lo; 3198 uint32_t rx_frames_discarded_hi; 3199 uint32_t rx_frames_discarded_lo; 3200 uint32_t rx_frames_dropped_hi; 3201 uint32_t rx_frames_dropped_lo; 3202}; 3203 3204/* To maintain backward compatibility between FW and drivers, new elements */ 3205/* should be added to the end of the structure. */ 3206 3207/* Per Port Statistics */ 3208struct port_info { 3209 uint32_t size; /* size of this structure (i.e. sizeof(port_info)) */ 3210 uint32_t enabled; /* 0 =Disabled, 1= Enabled */ 3211 uint32_t link_speed; /* multiplier of 100Mb */ 3212 uint32_t wol_support; /* WoL Support (i.e. Non-Zero if WOL supported ) */ 3213 uint32_t flow_control; /* 802.3X Flow Ctrl. 0=off 1=RX 2=TX 3=RX&TX.*/ 3214 uint32_t flex10; /* Flex10 mode enabled. non zero = yes */ 3215 uint32_t rx_drops; /* RX Discards. Counters roll over, never reset */ 3216 uint32_t rx_errors; /* RX Errors. Physical Port Stats L95, All PFs and NC-SI. 3217 This is flagged by Consumer as an error. */ 3218 uint32_t rx_uncast_lo; /* RX Unicast Packets. Free running counters: */ 3219 uint32_t rx_uncast_hi; /* RX Unicast Packets. Free running counters: */ 3220 uint32_t rx_mcast_lo; /* RX Multicast Packets */ 3221 uint32_t rx_mcast_hi; /* RX Multicast Packets */ 3222 uint32_t rx_bcast_lo; /* RX Broadcast Packets */ 3223 uint32_t rx_bcast_hi; /* RX Broadcast Packets */ 3224 uint32_t tx_uncast_lo; /* TX Unicast Packets */ 3225 uint32_t tx_uncast_hi; /* TX Unicast Packets */ 3226 uint32_t tx_mcast_lo; /* TX Multicast Packets */ 3227 uint32_t tx_mcast_hi; /* TX Multicast Packets */ 3228 uint32_t tx_bcast_lo; /* TX Broadcast Packets */ 3229 uint32_t tx_bcast_hi; /* TX Broadcast Packets */ 3230 uint32_t tx_errors; /* TX Errors */ 3231 uint32_t tx_discards; /* TX Discards */ 3232 uint32_t rx_frames_lo; /* RX Frames received */ 3233 uint32_t rx_frames_hi; /* RX Frames received */ 3234 uint32_t rx_bytes_lo; /* RX Bytes received */ 3235 uint32_t rx_bytes_hi; /* RX Bytes received */ 3236 uint32_t tx_frames_lo; /* TX Frames sent */ 3237 uint32_t tx_frames_hi; /* TX Frames sent */ 3238 uint32_t tx_bytes_lo; /* TX Bytes sent */ 3239 uint32_t tx_bytes_hi; /* TX Bytes sent */ 3240 uint32_t link_status; /* Port P Link Status. 1:0 bit for port enabled. 3241 1:1 bit for link good, 3242 2:1 Set if link changed between last poll. */ 3243 uint32_t tx_pfc_frames_lo; /* PFC Frames sent. */ 3244 uint32_t tx_pfc_frames_hi; /* PFC Frames sent. */ 3245 uint32_t rx_pfc_frames_lo; /* PFC Frames Received. */ 3246 uint32_t rx_pfc_frames_hi; /* PFC Frames Received. */ 3247}; 3248 3249 3250#define BCM_5710_FW_MAJOR_VERSION 7 3251#define BCM_5710_FW_MINOR_VERSION 8 3252#define BCM_5710_FW_REVISION_VERSION 51 3253#define BCM_5710_FW_ENGINEERING_VERSION 0 3254#define BCM_5710_FW_COMPILE_FLAGS 1 3255 3256 3257/* 3258 * attention bits $$KEEP_ENDIANNESS$$ 3259 */ 3260struct atten_sp_status_block 3261{ 3262 uint32_t attn_bits /* 16 bit of attention signal lines */; 3263 uint32_t attn_bits_ack /* 16 bit of attention signal ack */; 3264 uint8_t status_block_id /* status block id */; 3265 uint8_t reserved0 /* resreved for padding */; 3266 uint16_t attn_bits_index /* attention bits running index */; 3267 uint32_t reserved1 /* resreved for padding */; 3268}; 3269 3270 3271/* 3272 * The eth aggregative context of Cstorm 3273 */ 3274struct cstorm_eth_ag_context 3275{ 3276 uint32_t __reserved0[10]; 3277}; 3278 3279 3280/* 3281 * dmae command structure 3282 */ 3283struct dmae_command 3284{ 3285 uint32_t opcode; 3286#define DMAE_COMMAND_SRC (0x1<<0) /* BitField opcode Whether the source is the PCIe or the GRC. 0- The source is the PCIe 1- The source is the GRC. */ 3287#define DMAE_COMMAND_SRC_SHIFT 0 3288#define DMAE_COMMAND_DST (0x3<<1) /* BitField opcode The destination of the DMA can be: 0-None 1-PCIe 2-GRC 3-None */ 3289#define DMAE_COMMAND_DST_SHIFT 1 3290#define DMAE_COMMAND_C_DST (0x1<<3) /* BitField opcode The destination of the completion: 0-PCIe 1-GRC */ 3291#define DMAE_COMMAND_C_DST_SHIFT 3 3292#define DMAE_COMMAND_C_TYPE_ENABLE (0x1<<4) /* BitField opcode Whether to write a completion word to the completion destination: 0-Do not write a completion word 1-Write the completion word */ 3293#define DMAE_COMMAND_C_TYPE_ENABLE_SHIFT 4 3294#define DMAE_COMMAND_C_TYPE_CRC_ENABLE (0x1<<5) /* BitField opcode Whether to write a CRC word to the completion destination 0-Do not write a CRC word 1-Write a CRC word */ 3295#define DMAE_COMMAND_C_TYPE_CRC_ENABLE_SHIFT 5 3296#define DMAE_COMMAND_C_TYPE_CRC_OFFSET (0x7<<6) /* BitField opcode The CRC word should be taken from the DMAE GRC space from address 9+X, where X is the value in these bits. */ 3297#define DMAE_COMMAND_C_TYPE_CRC_OFFSET_SHIFT 6 3298#define DMAE_COMMAND_ENDIANITY (0x3<<9) /* BitField opcode swapping mode. */ 3299#define DMAE_COMMAND_ENDIANITY_SHIFT 9 3300#define DMAE_COMMAND_PORT (0x1<<11) /* BitField opcode Which network port ID to present to the PCI request interface */ 3301#define DMAE_COMMAND_PORT_SHIFT 11 3302#define DMAE_COMMAND_CRC_RESET (0x1<<12) /* BitField opcode reset crc result */ 3303#define DMAE_COMMAND_CRC_RESET_SHIFT 12 3304#define DMAE_COMMAND_SRC_RESET (0x1<<13) /* BitField opcode reset source address in next go */ 3305#define DMAE_COMMAND_SRC_RESET_SHIFT 13 3306#define DMAE_COMMAND_DST_RESET (0x1<<14) /* BitField opcode reset dest address in next go */ 3307#define DMAE_COMMAND_DST_RESET_SHIFT 14 3308#define DMAE_COMMAND_E1HVN (0x3<<15) /* BitField opcode vnic number E2 and onwards source vnic */ 3309#define DMAE_COMMAND_E1HVN_SHIFT 15 3310#define DMAE_COMMAND_DST_VN (0x3<<17) /* BitField opcode E2 and onwards dest vnic */ 3311#define DMAE_COMMAND_DST_VN_SHIFT 17 3312#define DMAE_COMMAND_C_FUNC (0x1<<19) /* BitField opcode E2 and onwards which function gets the completion src_vn(e1hvn)-0 dst_vn-1 */ 3313#define DMAE_COMMAND_C_FUNC_SHIFT 19 3314#define DMAE_COMMAND_ERR_POLICY (0x3<<20) /* BitField opcode E2 and onwards what to do when theres a completion and a PCI error regular-0 error indication-1 no completion-2 */ 3315#define DMAE_COMMAND_ERR_POLICY_SHIFT 20 3316#define DMAE_COMMAND_RESERVED0 (0x3FF<<22) /* BitField opcode */ 3317#define DMAE_COMMAND_RESERVED0_SHIFT 22 3318 uint32_t src_addr_lo /* source address low/grc address */; 3319 uint32_t src_addr_hi /* source address hi */; 3320 uint32_t dst_addr_lo /* dest address low/grc address */; 3321 uint32_t dst_addr_hi /* dest address hi */; 3322#if defined(__BIG_ENDIAN) 3323 uint16_t opcode_iov; 3324#define DMAE_COMMAND_SRC_VFID (0x3F<<0) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility source VF id */ 3325#define DMAE_COMMAND_SRC_VFID_SHIFT 0 3326#define DMAE_COMMAND_SRC_VFPF (0x1<<6) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility selects the source function PF-0, VF-1 */ 3327#define DMAE_COMMAND_SRC_VFPF_SHIFT 6 3328#define DMAE_COMMAND_RESERVED1 (0x1<<7) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility */ 3329#define DMAE_COMMAND_RESERVED1_SHIFT 7 3330#define DMAE_COMMAND_DST_VFID (0x3F<<8) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility destination VF id */ 3331#define DMAE_COMMAND_DST_VFID_SHIFT 8 3332#define DMAE_COMMAND_DST_VFPF (0x1<<14) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility selects the destination function PF-0, VF-1 */ 3333#define DMAE_COMMAND_DST_VFPF_SHIFT 14 3334#define DMAE_COMMAND_RESERVED2 (0x1<<15) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility */ 3335#define DMAE_COMMAND_RESERVED2_SHIFT 15 3336 uint16_t len /* copy length */; 3337#elif defined(__LITTLE_ENDIAN) 3338 uint16_t len /* copy length */; 3339 uint16_t opcode_iov; 3340#define DMAE_COMMAND_SRC_VFID (0x3F<<0) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility source VF id */ 3341#define DMAE_COMMAND_SRC_VFID_SHIFT 0 3342#define DMAE_COMMAND_SRC_VFPF (0x1<<6) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility selects the source function PF-0, VF-1 */ 3343#define DMAE_COMMAND_SRC_VFPF_SHIFT 6 3344#define DMAE_COMMAND_RESERVED1 (0x1<<7) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility */ 3345#define DMAE_COMMAND_RESERVED1_SHIFT 7 3346#define DMAE_COMMAND_DST_VFID (0x3F<<8) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility destination VF id */ 3347#define DMAE_COMMAND_DST_VFID_SHIFT 8 3348#define DMAE_COMMAND_DST_VFPF (0x1<<14) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility selects the destination function PF-0, VF-1 */ 3349#define DMAE_COMMAND_DST_VFPF_SHIFT 14 3350#define DMAE_COMMAND_RESERVED2 (0x1<<15) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility */ 3351#define DMAE_COMMAND_RESERVED2_SHIFT 15 3352#endif 3353 uint32_t comp_addr_lo /* completion address low/grc address */; 3354 uint32_t comp_addr_hi /* completion address hi */; 3355 uint32_t comp_val /* value to write to completion address */; 3356 uint32_t crc32 /* crc32 result */; 3357 uint32_t crc32_c /* crc32_c result */; 3358#if defined(__BIG_ENDIAN) 3359 uint16_t crc16_c /* crc16_c result */; 3360 uint16_t crc16 /* crc16 result */; 3361#elif defined(__LITTLE_ENDIAN) 3362 uint16_t crc16 /* crc16 result */; 3363 uint16_t crc16_c /* crc16_c result */; 3364#endif 3365#if defined(__BIG_ENDIAN) 3366 uint16_t reserved3; 3367 uint16_t crc_t10 /* crc_t10 result */; 3368#elif defined(__LITTLE_ENDIAN) 3369 uint16_t crc_t10 /* crc_t10 result */; 3370 uint16_t reserved3; 3371#endif 3372#if defined(__BIG_ENDIAN) 3373 uint16_t xsum8 /* checksum8 result */; 3374 uint16_t xsum16 /* checksum16 result */; 3375#elif defined(__LITTLE_ENDIAN) 3376 uint16_t xsum16 /* checksum16 result */; 3377 uint16_t xsum8 /* checksum8 result */; 3378#endif 3379}; 3380 3381 3382/* 3383 * common data for all protocols 3384 */ 3385struct doorbell_hdr 3386{ 3387 uint8_t header; 3388#define DOORBELL_HDR_RX (0x1<<0) /* BitField header 1 for rx doorbell, 0 for tx doorbell */ 3389#define DOORBELL_HDR_RX_SHIFT 0 3390#define DOORBELL_HDR_DB_TYPE (0x1<<1) /* BitField header 0 for normal doorbell, 1 for advertise wnd doorbell */ 3391#define DOORBELL_HDR_DB_TYPE_SHIFT 1 3392#define DOORBELL_HDR_DPM_SIZE (0x3<<2) /* BitField header rdma tx only: DPM transaction size specifier (64/128/256/512 bytes) */ 3393#define DOORBELL_HDR_DPM_SIZE_SHIFT 2 3394#define DOORBELL_HDR_CONN_TYPE (0xF<<4) /* BitField header connection type */ 3395#define DOORBELL_HDR_CONN_TYPE_SHIFT 4 3396}; 3397 3398/* 3399 * Ethernet doorbell 3400 */ 3401struct eth_tx_doorbell 3402{ 3403#if defined(__BIG_ENDIAN) 3404 uint16_t npackets /* number of data bytes that were added in the doorbell */; 3405 uint8_t params; 3406#define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0) /* BitField params number of buffer descriptors that were added in the doorbell */ 3407#define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0 3408#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6) /* BitField params tx fin command flag */ 3409#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6 3410#define ETH_TX_DOORBELL_SPARE (0x1<<7) /* BitField params doorbell queue spare flag */ 3411#define ETH_TX_DOORBELL_SPARE_SHIFT 7 3412 struct doorbell_hdr hdr; 3413#elif defined(__LITTLE_ENDIAN) 3414 struct doorbell_hdr hdr; 3415 uint8_t params; 3416#define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0) /* BitField params number of buffer descriptors that were added in the doorbell */ 3417#define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0 3418#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6) /* BitField params tx fin command flag */ 3419#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6 3420#define ETH_TX_DOORBELL_SPARE (0x1<<7) /* BitField params doorbell queue spare flag */ 3421#define ETH_TX_DOORBELL_SPARE_SHIFT 7 3422 uint16_t npackets /* number of data bytes that were added in the doorbell */; 3423#endif 3424}; 3425 3426 3427/* 3428 * 3 lines. status block $$KEEP_ENDIANNESS$$ 3429 */ 3430struct hc_status_block_e1x 3431{ 3432 uint16_t index_values[HC_SB_MAX_INDICES_E1X] /* indices reported by cstorm */; 3433 uint16_t running_index[HC_SB_MAX_SM] /* Status Block running indices */; 3434 uint32_t rsrv[11]; 3435}; 3436 3437/* 3438 * host status block 3439 */ 3440struct host_hc_status_block_e1x 3441{ 3442 struct hc_status_block_e1x sb /* fast path indices */; 3443}; 3444 3445 3446/* 3447 * 3 lines. status block $$KEEP_ENDIANNESS$$ 3448 */ 3449struct hc_status_block_e2 3450{ 3451 uint16_t index_values[HC_SB_MAX_INDICES_E2] /* indices reported by cstorm */; 3452 uint16_t running_index[HC_SB_MAX_SM] /* Status Block running indices */; 3453 uint32_t reserved[11]; 3454}; 3455 3456/* 3457 * host status block 3458 */ 3459struct host_hc_status_block_e2 3460{ 3461 struct hc_status_block_e2 sb /* fast path indices */; 3462}; 3463 3464 3465/* 3466 * 5 lines. slow-path status block $$KEEP_ENDIANNESS$$ 3467 */ 3468struct hc_sp_status_block 3469{ 3470 uint16_t index_values[HC_SP_SB_MAX_INDICES] /* indices reported by cstorm */; 3471 uint16_t running_index /* Status Block running index */; 3472 uint16_t rsrv; 3473 uint32_t rsrv1; 3474}; 3475 3476/* 3477 * host status block 3478 */ 3479struct host_sp_status_block 3480{ 3481 struct atten_sp_status_block atten_status_block /* attention bits section */; 3482 struct hc_sp_status_block sp_sb /* slow path indices */; 3483}; 3484 3485 3486/* 3487 * IGU driver acknowledgment register 3488 */ 3489struct igu_ack_register 3490{ 3491#if defined(__BIG_ENDIAN) 3492 uint16_t sb_id_and_flags; 3493#define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0) /* BitField sb_id_and_flags 0-15: non default status blocks, 16: default status block */ 3494#define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0 3495#define IGU_ACK_REGISTER_STORM_ID (0x7<<5) /* BitField sb_id_and_flags 0-3:storm id, 4: attn status block (valid in default sb only) */ 3496#define IGU_ACK_REGISTER_STORM_ID_SHIFT 5 3497#define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8) /* BitField sb_id_and_flags if set, acknowledges status block index */ 3498#define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8 3499#define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9) /* BitField sb_id_and_flags interrupt enable/disable/nop: use IGU_INT_xxx constants */ 3500#define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9 3501#define IGU_ACK_REGISTER_RESERVED (0x1F<<11) /* BitField sb_id_and_flags */ 3502#define IGU_ACK_REGISTER_RESERVED_SHIFT 11 3503 uint16_t status_block_index /* status block index acknowledgement */; 3504#elif defined(__LITTLE_ENDIAN) 3505 uint16_t status_block_index /* status block index acknowledgement */; 3506 uint16_t sb_id_and_flags; 3507#define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0) /* BitField sb_id_and_flags 0-15: non default status blocks, 16: default status block */ 3508#define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0 3509#define IGU_ACK_REGISTER_STORM_ID (0x7<<5) /* BitField sb_id_and_flags 0-3:storm id, 4: attn status block (valid in default sb only) */ 3510#define IGU_ACK_REGISTER_STORM_ID_SHIFT 5 3511#define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8) /* BitField sb_id_and_flags if set, acknowledges status block index */ 3512#define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8 3513#define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9) /* BitField sb_id_and_flags interrupt enable/disable/nop: use IGU_INT_xxx constants */ 3514#define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9 3515#define IGU_ACK_REGISTER_RESERVED (0x1F<<11) /* BitField sb_id_and_flags */ 3516#define IGU_ACK_REGISTER_RESERVED_SHIFT 11 3517#endif 3518}; 3519 3520 3521/* 3522 * IGU driver acknowledgement register 3523 */ 3524struct igu_backward_compatible 3525{ 3526 uint32_t sb_id_and_flags; 3527#define IGU_BACKWARD_COMPATIBLE_SB_INDEX (0xFFFF<<0) /* BitField sb_id_and_flags */ 3528#define IGU_BACKWARD_COMPATIBLE_SB_INDEX_SHIFT 0 3529#define IGU_BACKWARD_COMPATIBLE_SB_SELECT (0x1F<<16) /* BitField sb_id_and_flags */ 3530#define IGU_BACKWARD_COMPATIBLE_SB_SELECT_SHIFT 16 3531#define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS (0x7<<21) /* BitField sb_id_and_flags 0-3:storm id, 4: attn status block (valid in default sb only) */ 3532#define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS_SHIFT 21 3533#define IGU_BACKWARD_COMPATIBLE_BUPDATE (0x1<<24) /* BitField sb_id_and_flags if set, acknowledges status block index */ 3534#define IGU_BACKWARD_COMPATIBLE_BUPDATE_SHIFT 24 3535#define IGU_BACKWARD_COMPATIBLE_ENABLE_INT (0x3<<25) /* BitField sb_id_and_flags interrupt enable/disable/nop: use IGU_INT_xxx constants */ 3536#define IGU_BACKWARD_COMPATIBLE_ENABLE_INT_SHIFT 25 3537#define IGU_BACKWARD_COMPATIBLE_RESERVED_0 (0x1F<<27) /* BitField sb_id_and_flags */ 3538#define IGU_BACKWARD_COMPATIBLE_RESERVED_0_SHIFT 27 3539 uint32_t reserved_2; 3540}; 3541 3542 3543/* 3544 * IGU driver acknowledgement register 3545 */ 3546struct igu_regular 3547{ 3548 uint32_t sb_id_and_flags; 3549#define IGU_REGULAR_SB_INDEX (0xFFFFF<<0) /* BitField sb_id_and_flags */ 3550#define IGU_REGULAR_SB_INDEX_SHIFT 0 3551#define IGU_REGULAR_RESERVED0 (0x1<<20) /* BitField sb_id_and_flags */ 3552#define IGU_REGULAR_RESERVED0_SHIFT 20 3553#define IGU_REGULAR_SEGMENT_ACCESS (0x7<<21) /* BitField sb_id_and_flags 21-23 (use enum igu_seg_access) */ 3554#define IGU_REGULAR_SEGMENT_ACCESS_SHIFT 21 3555#define IGU_REGULAR_BUPDATE (0x1<<24) /* BitField sb_id_and_flags */ 3556#define IGU_REGULAR_BUPDATE_SHIFT 24 3557#define IGU_REGULAR_ENABLE_INT (0x3<<25) /* BitField sb_id_and_flags interrupt enable/disable/nop (use enum igu_int_cmd) */ 3558#define IGU_REGULAR_ENABLE_INT_SHIFT 25 3559#define IGU_REGULAR_RESERVED_1 (0x1<<27) /* BitField sb_id_and_flags */ 3560#define IGU_REGULAR_RESERVED_1_SHIFT 27 3561#define IGU_REGULAR_CLEANUP_TYPE (0x3<<28) /* BitField sb_id_and_flags */ 3562#define IGU_REGULAR_CLEANUP_TYPE_SHIFT 28 3563#define IGU_REGULAR_CLEANUP_SET (0x1<<30) /* BitField sb_id_and_flags */ 3564#define IGU_REGULAR_CLEANUP_SET_SHIFT 30 3565#define IGU_REGULAR_BCLEANUP (0x1<<31) /* BitField sb_id_and_flags */ 3566#define IGU_REGULAR_BCLEANUP_SHIFT 31 3567 uint32_t reserved_2; 3568}; 3569 3570/* 3571 * IGU driver acknowledgement register 3572 */ 3573union igu_consprod_reg 3574{ 3575 struct igu_regular regular; 3576 struct igu_backward_compatible backward_compatible; 3577}; 3578 3579 3580/* 3581 * Igu control commands 3582 */ 3583enum igu_ctrl_cmd 3584{ 3585 IGU_CTRL_CMD_TYPE_RD, 3586 IGU_CTRL_CMD_TYPE_WR, 3587 MAX_IGU_CTRL_CMD}; 3588 3589 3590/* 3591 * Control register for the IGU command register 3592 */ 3593struct igu_ctrl_reg 3594{ 3595 uint32_t ctrl_data; 3596#define IGU_CTRL_REG_ADDRESS (0xFFF<<0) /* BitField ctrl_data */ 3597#define IGU_CTRL_REG_ADDRESS_SHIFT 0 3598#define IGU_CTRL_REG_FID (0x7F<<12) /* BitField ctrl_data */ 3599#define IGU_CTRL_REG_FID_SHIFT 12 3600#define IGU_CTRL_REG_RESERVED (0x1<<19) /* BitField ctrl_data */ 3601#define IGU_CTRL_REG_RESERVED_SHIFT 19 3602#define IGU_CTRL_REG_TYPE (0x1<<20) /* BitField ctrl_data (use enum igu_ctrl_cmd) */ 3603#define IGU_CTRL_REG_TYPE_SHIFT 20 3604#define IGU_CTRL_REG_UNUSED (0x7FF<<21) /* BitField ctrl_data */ 3605#define IGU_CTRL_REG_UNUSED_SHIFT 21 3606}; 3607 3608 3609/* 3610 * Igu interrupt command 3611 */ 3612enum igu_int_cmd 3613{ 3614 IGU_INT_ENABLE, 3615 IGU_INT_DISABLE, 3616 IGU_INT_NOP, 3617 IGU_INT_NOP2, 3618 MAX_IGU_INT_CMD}; 3619 3620 3621/* 3622 * Igu segments 3623 */ 3624enum igu_seg_access 3625{ 3626 IGU_SEG_ACCESS_NORM, 3627 IGU_SEG_ACCESS_DEF, 3628 IGU_SEG_ACCESS_ATTN, 3629 MAX_IGU_SEG_ACCESS}; 3630 3631 3632/* 3633 * Parser parsing flags field 3634 */ 3635struct parsing_flags 3636{ 3637 uint16_t flags; 3638#define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0) /* BitField flagscontext flags 0=non-unicast, 1=unicast (use enum prs_flags_eth_addr_type) */ 3639#define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0 3640#define PARSING_FLAGS_VLAN (0x1<<1) /* BitField flagscontext flags 0 or 1 */ 3641#define PARSING_FLAGS_VLAN_SHIFT 1 3642#define PARSING_FLAGS_EXTRA_VLAN (0x1<<2) /* BitField flagscontext flags 0 or 1 */ 3643#define PARSING_FLAGS_EXTRA_VLAN_SHIFT 2 3644#define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3) /* BitField flagscontext flags 0=un-known, 1=Ipv4, 2=Ipv6,3=LLC SNAP un-known. LLC SNAP here refers only to LLC/SNAP packets that do not have Ipv4 or Ipv6 above them. Ipv4 and Ipv6 indications are even if they are over LLC/SNAP and not directly over Ethernet (use enum prs_flags_over_eth) */ 3645#define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3 3646#define PARSING_FLAGS_IP_OPTIONS (0x1<<5) /* BitField flagscontext flags 0=no IP options / extension headers. 1=IP options / extension header exist */ 3647#define PARSING_FLAGS_IP_OPTIONS_SHIFT 5 3648#define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1<<6) /* BitField flagscontext flags 0=non-fragmented, 1=fragmented */ 3649#define PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT 6 3650#define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3<<7) /* BitField flagscontext flags 0=un-known, 1=TCP, 2=UDP (use enum prs_flags_over_ip) */ 3651#define PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT 7 3652#define PARSING_FLAGS_PURE_ACK_INDICATION (0x1<<9) /* BitField flagscontext flags 0=packet with data, 1=pure-ACK (use enum prs_flags_ack_type) */ 3653#define PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT 9 3654#define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1<<10) /* BitField flagscontext flags 0=no TCP options. 1=TCP options */ 3655#define PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT 10 3656#define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1<<11) /* BitField flagscontext flags According to the TCP header options parsing */ 3657#define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT 11 3658#define PARSING_FLAGS_CONNECTION_MATCH (0x1<<12) /* BitField flagscontext flags connection match in searcher indication */ 3659#define PARSING_FLAGS_CONNECTION_MATCH_SHIFT 12 3660#define PARSING_FLAGS_LLC_SNAP (0x1<<13) /* BitField flagscontext flags LLC SNAP indication */ 3661#define PARSING_FLAGS_LLC_SNAP_SHIFT 13 3662#define PARSING_FLAGS_RESERVED0 (0x3<<14) /* BitField flagscontext flags */ 3663#define PARSING_FLAGS_RESERVED0_SHIFT 14 3664}; 3665 3666 3667/* 3668 * Parsing flags for TCP ACK type 3669 */ 3670enum prs_flags_ack_type 3671{ 3672 PRS_FLAG_PUREACK_PIGGY, 3673 PRS_FLAG_PUREACK_PURE, 3674 MAX_PRS_FLAGS_ACK_TYPE}; 3675 3676 3677/* 3678 * Parsing flags for Ethernet address type 3679 */ 3680enum prs_flags_eth_addr_type 3681{ 3682 PRS_FLAG_ETHTYPE_NON_UNICAST, 3683 PRS_FLAG_ETHTYPE_UNICAST, 3684 MAX_PRS_FLAGS_ETH_ADDR_TYPE}; 3685 3686 3687/* 3688 * Parsing flags for over-ethernet protocol 3689 */ 3690enum prs_flags_over_eth 3691{ 3692 PRS_FLAG_OVERETH_UNKNOWN, 3693 PRS_FLAG_OVERETH_IPV4, 3694 PRS_FLAG_OVERETH_IPV6, 3695 PRS_FLAG_OVERETH_LLCSNAP_UNKNOWN, 3696 MAX_PRS_FLAGS_OVER_ETH}; 3697 3698 3699/* 3700 * Parsing flags for over-IP protocol 3701 */ 3702enum prs_flags_over_ip 3703{ 3704 PRS_FLAG_OVERIP_UNKNOWN, 3705 PRS_FLAG_OVERIP_TCP, 3706 PRS_FLAG_OVERIP_UDP, 3707 MAX_PRS_FLAGS_OVER_IP}; 3708 3709 3710/* 3711 * SDM operation gen command (generate aggregative interrupt) 3712 */ 3713struct sdm_op_gen 3714{ 3715 uint32_t command; 3716#define SDM_OP_GEN_COMP_PARAM (0x1F<<0) /* BitField commandcomp_param and comp_type thread ID/aggr interrupt number/counter depending on the completion type */ 3717#define SDM_OP_GEN_COMP_PARAM_SHIFT 0 3718#define SDM_OP_GEN_COMP_TYPE (0x7<<5) /* BitField commandcomp_param and comp_type Direct messages to CM / PCI switch are not supported in operation_gen completion */ 3719#define SDM_OP_GEN_COMP_TYPE_SHIFT 5 3720#define SDM_OP_GEN_AGG_VECT_IDX (0xFF<<8) /* BitField commandcomp_param and comp_type bit index in aggregated interrupt vector */ 3721#define SDM_OP_GEN_AGG_VECT_IDX_SHIFT 8 3722#define SDM_OP_GEN_AGG_VECT_IDX_VALID (0x1<<16) /* BitField commandcomp_param and comp_type */ 3723#define SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT 16 3724#define SDM_OP_GEN_RESERVED (0x7FFF<<17) /* BitField commandcomp_param and comp_type */ 3725#define SDM_OP_GEN_RESERVED_SHIFT 17 3726}; 3727 3728 3729/* 3730 * Timers connection context 3731 */ 3732struct timers_block_context 3733{ 3734 uint32_t __reserved_0 /* data of client 0 of the timers block*/; 3735 uint32_t __reserved_1 /* data of client 1 of the timers block*/; 3736 uint32_t __reserved_2 /* data of client 2 of the timers block*/; 3737 uint32_t flags; 3738#define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3<<0) /* BitField flagscontext flags number of active timers running */ 3739#define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 0 3740#define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1<<2) /* BitField flagscontext flags flag: is connection valid (should be set by driver to 1 in toe/iscsi connections) */ 3741#define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG_SHIFT 2 3742#define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF<<3) /* BitField flagscontext flags */ 3743#define __TIMERS_BLOCK_CONTEXT_RESERVED0_SHIFT 3 3744}; 3745 3746 3747/* 3748 * The eth aggregative context of Tstorm 3749 */ 3750struct tstorm_eth_ag_context 3751{ 3752 uint32_t __reserved0[14]; 3753}; 3754 3755 3756/* 3757 * The eth aggregative context of Ustorm 3758 */ 3759struct ustorm_eth_ag_context 3760{ 3761 uint32_t __reserved0; 3762#if defined(__BIG_ENDIAN) 3763 uint8_t cdu_usage /* Will be used by the CDU for validation of the CID/connection type on doorbells. */; 3764 uint8_t __reserved2; 3765 uint16_t __reserved1; 3766#elif defined(__LITTLE_ENDIAN) 3767 uint16_t __reserved1; 3768 uint8_t __reserved2; 3769 uint8_t cdu_usage /* Will be used by the CDU for validation of the CID/connection type on doorbells. */; 3770#endif 3771 uint32_t __reserved3[6]; 3772}; 3773 3774 3775/* 3776 * The eth aggregative context of Xstorm 3777 */ 3778struct xstorm_eth_ag_context 3779{ 3780 uint32_t reserved0; 3781#if defined(__BIG_ENDIAN) 3782 uint8_t cdu_reserved /* Used by the CDU for validation and debugging */; 3783 uint8_t reserved2; 3784 uint16_t reserved1; 3785#elif defined(__LITTLE_ENDIAN) 3786 uint16_t reserved1; 3787 uint8_t reserved2; 3788 uint8_t cdu_reserved /* Used by the CDU for validation and debugging */; 3789#endif 3790 uint32_t reserved3[30]; 3791}; 3792 3793 3794/* 3795 * doorbell message sent to the chip 3796 */ 3797struct doorbell 3798{ 3799#if defined(__BIG_ENDIAN) 3800 uint16_t zero_fill2 /* driver must zero this field! */; 3801 uint8_t zero_fill1 /* driver must zero this field! */; 3802 struct doorbell_hdr header; 3803#elif defined(__LITTLE_ENDIAN) 3804 struct doorbell_hdr header; 3805 uint8_t zero_fill1 /* driver must zero this field! */; 3806 uint16_t zero_fill2 /* driver must zero this field! */; 3807#endif 3808}; 3809 3810 3811/* 3812 * doorbell message sent to the chip 3813 */ 3814struct doorbell_set_prod 3815{ 3816#if defined(__BIG_ENDIAN) 3817 uint16_t prod /* Producer index to be set */; 3818 uint8_t zero_fill1 /* driver must zero this field! */; 3819 struct doorbell_hdr header; 3820#elif defined(__LITTLE_ENDIAN) 3821 struct doorbell_hdr header; 3822 uint8_t zero_fill1 /* driver must zero this field! */; 3823 uint16_t prod /* Producer index to be set */; 3824#endif 3825}; 3826 3827 3828struct regpair 3829{ 3830 uint32_t lo /* low word for reg-pair */; 3831 uint32_t hi /* high word for reg-pair */; 3832}; 3833 3834 3835struct regpair_native 3836{ 3837 uint32_t lo /* low word for reg-pair */; 3838 uint32_t hi /* high word for reg-pair */; 3839}; 3840 3841 3842/* 3843 * Classify rule opcodes in E2/E3 3844 */ 3845enum classify_rule 3846{ 3847 CLASSIFY_RULE_OPCODE_MAC /* Add/remove a MAC address */, 3848 CLASSIFY_RULE_OPCODE_VLAN /* Add/remove a VLAN */, 3849 CLASSIFY_RULE_OPCODE_PAIR /* Add/remove a MAC-VLAN pair */, 3850 MAX_CLASSIFY_RULE}; 3851 3852 3853/* 3854 * Classify rule types in E2/E3 3855 */ 3856enum classify_rule_action_type 3857{ 3858 CLASSIFY_RULE_REMOVE, 3859 CLASSIFY_RULE_ADD, 3860 MAX_CLASSIFY_RULE_ACTION_TYPE}; 3861 3862 3863/* 3864 * client init ramrod data $$KEEP_ENDIANNESS$$ 3865 */ 3866struct client_init_general_data 3867{ 3868 uint8_t client_id /* client_id */; 3869 uint8_t statistics_counter_id /* statistics counter id */; 3870 uint8_t statistics_en_flg /* statistics en flg */; 3871 uint8_t is_fcoe_flg /* is this an fcoe connection. (1 bit is used) */; 3872 uint8_t activate_flg /* if 0 - the client is deactivate else the client is activate client (1 bit is used) */; 3873 uint8_t sp_client_id /* the slow path rings client Id. */; 3874 uint16_t mtu /* Host MTU from client config */; 3875 uint8_t statistics_zero_flg /* if set FW will reset the statistic counter of this client */; 3876 uint8_t func_id /* PCI function ID (0-71) */; 3877 uint8_t cos /* The connection cos, if applicable */; 3878 uint8_t traffic_type; 3879 uint32_t reserved0; 3880}; 3881 3882 3883/* 3884 * client init rx data $$KEEP_ENDIANNESS$$ 3885 */ 3886struct client_init_rx_data 3887{ 3888 uint8_t tpa_en; 3889#define CLIENT_INIT_RX_DATA_TPA_EN_IPV4 (0x1<<0) /* BitField tpa_entpa_enable tpa enable flg ipv4 */ 3890#define CLIENT_INIT_RX_DATA_TPA_EN_IPV4_SHIFT 0 3891#define CLIENT_INIT_RX_DATA_TPA_EN_IPV6 (0x1<<1) /* BitField tpa_entpa_enable tpa enable flg ipv6 */ 3892#define CLIENT_INIT_RX_DATA_TPA_EN_IPV6_SHIFT 1 3893#define CLIENT_INIT_RX_DATA_TPA_MODE (0x1<<2) /* BitField tpa_entpa_enable tpa mode (LRO or GRO) (use enum tpa_mode) */ 3894#define CLIENT_INIT_RX_DATA_TPA_MODE_SHIFT 2 3895#define CLIENT_INIT_RX_DATA_RESERVED5 (0x1F<<3) /* BitField tpa_entpa_enable */ 3896#define CLIENT_INIT_RX_DATA_RESERVED5_SHIFT 3 3897 uint8_t vmqueue_mode_en_flg /* If set, working in VMQueue mode (always consume one sge) */; 3898 uint8_t extra_data_over_sgl_en_flg /* if set, put over sgl data from end of input message */; 3899 uint8_t cache_line_alignment_log_size /* The log size of cache line alignment in bytes. Must be a power of 2. */; 3900 uint8_t enable_dynamic_hc /* If set, dynamic HC is enabled */; 3901 uint8_t max_sges_for_packet /* The maximal number of SGEs that can be used for one packet. depends on MTU and SGE size. must be 0 if SGEs are disabled */; 3902 uint8_t client_qzone_id /* used in E2 only, to specify the HW queue zone ID used for this client rx producers */; 3903 uint8_t drop_ip_cs_err_flg /* If set, this client drops packets with IP checksum error */; 3904 uint8_t drop_tcp_cs_err_flg /* If set, this client drops packets with TCP checksum error */; 3905 uint8_t drop_ttl0_flg /* If set, this client drops packets with TTL=0 */; 3906 uint8_t drop_udp_cs_err_flg /* If set, this client drops packets with UDP checksum error */; 3907 uint8_t inner_vlan_removal_enable_flg /* If set, inner VLAN removal is enabled for this client */; 3908 uint8_t outer_vlan_removal_enable_flg /* If set, outer VLAN removal is enabled for this client */; 3909 uint8_t status_block_id /* rx status block id */; 3910 uint8_t rx_sb_index_number /* status block indices */; 3911 uint8_t dont_verify_rings_pause_thr_flg /* If set, the rings pause thresholds will not be verified by firmware. */; 3912 uint8_t max_tpa_queues /* maximal TPA queues allowed for this client */; 3913 uint8_t silent_vlan_removal_flg /* if set, and the vlan is equal to requested vlan according to mask, the vlan will be remove without notifying the driver */; 3914 uint16_t max_bytes_on_bd /* Maximum bytes that can be placed on a BD. The BD allocated size should include 2 more bytes (ip alignment) and alignment size (in case the address is not aligned) */; 3915 uint16_t sge_buff_size /* Size of the buffers pointed by SGEs */; 3916 uint8_t approx_mcast_engine_id /* In Everest2, if is_approx_mcast is set, this field specified which approximate multicast engine is associate with this client */; 3917 uint8_t rss_engine_id /* In Everest2, if rss_mode is set, this field specified which RSS engine is associate with this client */; 3918 struct regpair bd_page_base /* BD page base address at the host */; 3919 struct regpair sge_page_base /* SGE page base address at the host */; 3920 struct regpair cqe_page_base /* Completion queue base address */; 3921 uint8_t is_leading_rss; 3922 uint8_t is_approx_mcast; 3923 uint16_t max_agg_size /* maximal size for the aggregated TPA packets, reprted by the host */; 3924 uint16_t state; 3925#define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL (0x1<<0) /* BitField staterx filters state drop all unicast packets */ 3926#define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL_SHIFT 0 3927#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL (0x1<<1) /* BitField staterx filters state accept all unicast packets (subject to vlan) */ 3928#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL_SHIFT 1 3929#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED (0x1<<2) /* BitField staterx filters state accept all unmatched unicast packets (subject to vlan) */ 3930#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED_SHIFT 2 3931#define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL (0x1<<3) /* BitField staterx filters state drop all multicast packets */ 3932#define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL_SHIFT 3 3933#define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL (0x1<<4) /* BitField staterx filters state accept all multicast packets (subject to vlan) */ 3934#define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL_SHIFT 4 3935#define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL (0x1<<5) /* BitField staterx filters state accept all broadcast packets (subject to vlan) */ 3936#define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL_SHIFT 5 3937#define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN (0x1<<6) /* BitField staterx filters state accept packets matched only by MAC (without checking vlan) */ 3938#define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN_SHIFT 6 3939#define CLIENT_INIT_RX_DATA_RESERVED2 (0x1FF<<7) /* BitField staterx filters state */ 3940#define CLIENT_INIT_RX_DATA_RESERVED2_SHIFT 7 3941 uint16_t cqe_pause_thr_low /* number of remaining cqes under which, we send pause message */; 3942 uint16_t cqe_pause_thr_high /* number of remaining cqes above which, we send un-pause message */; 3943 uint16_t bd_pause_thr_low /* number of remaining bds under which, we send pause message */; 3944 uint16_t bd_pause_thr_high /* number of remaining bds above which, we send un-pause message */; 3945 uint16_t sge_pause_thr_low /* number of remaining sges under which, we send pause message */; 3946 uint16_t sge_pause_thr_high /* number of remaining sges above which, we send un-pause message */; 3947 uint16_t rx_cos_mask /* the bits that will be set on pfc/ safc paket whith will be genratet when this ring is full. for regular flow control set this to 1 */; 3948 uint16_t silent_vlan_value /* The vlan to compare, in case, silent vlan is set */; 3949 uint16_t silent_vlan_mask /* The vlan mask, in case, silent vlan is set */; 3950 uint32_t reserved6[2]; 3951}; 3952 3953/* 3954 * client init tx data $$KEEP_ENDIANNESS$$ 3955 */ 3956struct client_init_tx_data 3957{ 3958 uint8_t enforce_security_flg /* if set, security checks will be made for this connection */; 3959 uint8_t tx_status_block_id /* the number of status block to update */; 3960 uint8_t tx_sb_index_number /* the index to use inside the status block */; 3961 uint8_t tss_leading_client_id /* client ID of the leading TSS client, for TX classification source knock out */; 3962 uint8_t tx_switching_flg /* if set, tx switching will be done to packets on this connection */; 3963 uint8_t anti_spoofing_flg /* if set, anti spoofing check will be done to packets on this connection */; 3964 uint16_t default_vlan /* default vlan tag (id+pri). (valid if default_vlan_flg is set) */; 3965 struct regpair tx_bd_page_base /* BD page base address at the host for TxBdCons */; 3966 uint16_t state; 3967#define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL (0x1<<0) /* BitField statetx filters state accept all unicast packets (subject to vlan) */ 3968#define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL_SHIFT 0 3969#define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL (0x1<<1) /* BitField statetx filters state accept all multicast packets (subject to vlan) */ 3970#define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL_SHIFT 1 3971#define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL (0x1<<2) /* BitField statetx filters state accept all broadcast packets (subject to vlan) */ 3972#define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL_SHIFT 2 3973#define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN (0x1<<3) /* BitField statetx filters state accept packets matched only by MAC (without checking vlan) */ 3974#define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN_SHIFT 3 3975#define CLIENT_INIT_TX_DATA_RESERVED0 (0xFFF<<4) /* BitField statetx filters state */ 3976#define CLIENT_INIT_TX_DATA_RESERVED0_SHIFT 4 3977 uint8_t default_vlan_flg /* is default vlan valid for this client. */; 3978 uint8_t force_default_pri_flg /* if set, force default priority */; 3979 uint8_t tunnel_lso_inc_ip_id /* In case of LSO over IPv4 tunnel, whether to increment IP ID on external IP header or internal IP header */; 3980 uint8_t refuse_outband_vlan_flg /* if set, the FW will not add outband vlan on packet (even if will exist on BD). */; 3981 uint8_t tunnel_non_lso_pcsum_location /* In case of non-Lso encapsulated packets with L4 checksum offload, the pseudo checksum location - on packet or on BD. */; 3982 uint8_t tunnel_non_lso_outer_ip_csum_location /* In case of non-Lso encapsulated packets with outer L3 ip checksum offload, the pseudo checksum location - on packet or on BD. */; 3983}; 3984 3985/* 3986 * client init ramrod data $$KEEP_ENDIANNESS$$ 3987 */ 3988struct client_init_ramrod_data 3989{ 3990 struct client_init_general_data general /* client init general data */; 3991 struct client_init_rx_data rx /* client init rx data */; 3992 struct client_init_tx_data tx /* client init tx data */; 3993}; 3994 3995 3996/* 3997 * client update ramrod data $$KEEP_ENDIANNESS$$ 3998 */ 3999struct client_update_ramrod_data 4000{ 4001 uint8_t client_id /* the client to update */; 4002 uint8_t func_id /* PCI function ID this client belongs to (0-71) */; 4003 uint8_t inner_vlan_removal_enable_flg /* If set, inner VLAN removal is enabled for this client, will be change according to change flag */; 4004 uint8_t inner_vlan_removal_change_flg /* If set, inner VLAN removal flag will be set according to the enable flag */; 4005 uint8_t outer_vlan_removal_enable_flg /* If set, outer VLAN removal is enabled for this client, will be change according to change flag */; 4006 uint8_t outer_vlan_removal_change_flg /* If set, outer VLAN removal flag will be set according to the enable flag */; 4007 uint8_t anti_spoofing_enable_flg /* If set, anti spoofing is enabled for this client, will be change according to change flag */; 4008 uint8_t anti_spoofing_change_flg /* If set, anti spoofing flag will be set according to anti spoofing flag */; 4009 uint8_t activate_flg /* if 0 - the client is deactivate else the client is activate client (1 bit is used) */; 4010 uint8_t activate_change_flg /* If set, activate_flg will be checked */; 4011 uint16_t default_vlan /* default vlan tag (id+pri). (valid if default_vlan_flg is set) */; 4012 uint8_t default_vlan_enable_flg; 4013 uint8_t default_vlan_change_flg; 4014 uint16_t silent_vlan_value /* The vlan to compare, in case, silent vlan is set */; 4015 uint16_t silent_vlan_mask /* The vlan mask, in case, silent vlan is set */; 4016 uint8_t silent_vlan_removal_flg /* if set, and the vlan is equal to requested vlan according to mask, the vlan will be remove without notifying the driver */; 4017 uint8_t silent_vlan_change_flg; 4018 uint8_t refuse_outband_vlan_flg /* If set, the FW will not add outband vlan on packet (even if will exist on BD). */; 4019 uint8_t refuse_outband_vlan_change_flg /* If set, refuse_outband_vlan_flg will be updated. */; 4020 uint8_t tx_switching_flg /* If set, tx switching will be done to packets on this connection. */; 4021 uint8_t tx_switching_change_flg /* If set, tx_switching_flg will be updated. */; 4022 uint32_t reserved1; 4023 uint32_t echo /* echo value to be sent to driver on event ring */; 4024}; 4025 4026 4027/* 4028 * The eth storm context of Cstorm 4029 */ 4030struct cstorm_eth_st_context 4031{ 4032 uint32_t __reserved0[4]; 4033}; 4034 4035 4036struct double_regpair 4037{ 4038 uint32_t regpair0_lo /* low word for reg-pair0 */; 4039 uint32_t regpair0_hi /* high word for reg-pair0 */; 4040 uint32_t regpair1_lo /* low word for reg-pair1 */; 4041 uint32_t regpair1_hi /* high word for reg-pair1 */; 4042}; 4043 4044 4045/* 4046 * Ethernet address typesm used in ethernet tx BDs 4047 */ 4048enum eth_addr_type 4049{ 4050 UNKNOWN_ADDRESS, 4051 UNICAST_ADDRESS, 4052 MULTICAST_ADDRESS, 4053 BROADCAST_ADDRESS, 4054 MAX_ETH_ADDR_TYPE}; 4055 4056 4057/* 4058 * $$KEEP_ENDIANNESS$$ 4059 */ 4060struct eth_classify_cmd_header 4061{ 4062 uint8_t cmd_general_data; 4063#define ETH_CLASSIFY_CMD_HEADER_RX_CMD (0x1<<0) /* BitField cmd_general_data should this cmd be applied for Rx */ 4064#define ETH_CLASSIFY_CMD_HEADER_RX_CMD_SHIFT 0 4065#define ETH_CLASSIFY_CMD_HEADER_TX_CMD (0x1<<1) /* BitField cmd_general_data should this cmd be applied for Tx */ 4066#define ETH_CLASSIFY_CMD_HEADER_TX_CMD_SHIFT 1 4067#define ETH_CLASSIFY_CMD_HEADER_OPCODE (0x3<<2) /* BitField cmd_general_data command opcode for MAC/VLAN/PAIR (use enum classify_rule) */ 4068#define ETH_CLASSIFY_CMD_HEADER_OPCODE_SHIFT 2 4069#define ETH_CLASSIFY_CMD_HEADER_IS_ADD (0x1<<4) /* BitField cmd_general_data (use enum classify_rule_action_type) */ 4070#define ETH_CLASSIFY_CMD_HEADER_IS_ADD_SHIFT 4 4071#define ETH_CLASSIFY_CMD_HEADER_RESERVED0 (0x7<<5) /* BitField cmd_general_data */ 4072#define ETH_CLASSIFY_CMD_HEADER_RESERVED0_SHIFT 5 4073 uint8_t func_id /* the function id */; 4074 uint8_t client_id; 4075 uint8_t reserved1; 4076}; 4077 4078 4079/* 4080 * header for eth classification config ramrod $$KEEP_ENDIANNESS$$ 4081 */ 4082struct eth_classify_header 4083{ 4084 uint8_t rule_cnt /* number of rules in classification config ramrod */; 4085 uint8_t reserved0; 4086 uint16_t reserved1; 4087 uint32_t echo /* echo value to be sent to driver on event ring */; 4088}; 4089 4090 4091/* 4092 * Command for adding/removing a MAC classification rule $$KEEP_ENDIANNESS$$ 4093 */ 4094struct eth_classify_mac_cmd 4095{ 4096 struct eth_classify_cmd_header header; 4097 uint16_t reserved0; 4098 uint16_t inner_mac; 4099 uint16_t mac_lsb; 4100 uint16_t mac_mid; 4101 uint16_t mac_msb; 4102 uint16_t reserved1; 4103}; 4104 4105 4106/* 4107 * Command for adding/removing a MAC-VLAN pair classification rule $$KEEP_ENDIANNESS$$ 4108 */ 4109struct eth_classify_pair_cmd 4110{ 4111 struct eth_classify_cmd_header header; 4112 uint16_t reserved0; 4113 uint16_t inner_mac; 4114 uint16_t mac_lsb; 4115 uint16_t mac_mid; 4116 uint16_t mac_msb; 4117 uint16_t vlan; 4118}; 4119 4120 4121/* 4122 * Command for adding/removing a VLAN classification rule $$KEEP_ENDIANNESS$$ 4123 */ 4124struct eth_classify_vlan_cmd 4125{ 4126 struct eth_classify_cmd_header header; 4127 uint32_t reserved0; 4128 uint32_t reserved1; 4129 uint16_t reserved2; 4130 uint16_t vlan; 4131}; 4132 4133/* 4134 * union for eth classification rule $$KEEP_ENDIANNESS$$ 4135 */ 4136union eth_classify_rule_cmd 4137{ 4138 struct eth_classify_mac_cmd mac; 4139 struct eth_classify_vlan_cmd vlan; 4140 struct eth_classify_pair_cmd pair; 4141}; 4142 4143/* 4144 * parameters for eth classification configuration ramrod $$KEEP_ENDIANNESS$$ 4145 */ 4146struct eth_classify_rules_ramrod_data 4147{ 4148 struct eth_classify_header header; 4149 union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT]; 4150}; 4151 4152 4153/* 4154 * The data contain client ID need to the ramrod $$KEEP_ENDIANNESS$$ 4155 */ 4156struct eth_common_ramrod_data 4157{ 4158 uint32_t client_id /* id of this client. (5 bits are used) */; 4159 uint32_t reserved1; 4160}; 4161 4162 4163/* 4164 * The eth storm context of Ustorm 4165 */ 4166struct ustorm_eth_st_context 4167{ 4168 uint32_t reserved0[52]; 4169}; 4170 4171/* 4172 * The eth storm context of Tstorm 4173 */ 4174struct tstorm_eth_st_context 4175{ 4176 uint32_t __reserved0[28]; 4177}; 4178 4179/* 4180 * The eth storm context of Xstorm 4181 */ 4182struct xstorm_eth_st_context 4183{ 4184 uint32_t reserved0[60]; 4185}; 4186 4187/* 4188 * Ethernet connection context 4189 */ 4190struct eth_context 4191{ 4192 struct ustorm_eth_st_context ustorm_st_context /* Ustorm storm context */; 4193 struct tstorm_eth_st_context tstorm_st_context /* Tstorm storm context */; 4194 struct xstorm_eth_ag_context xstorm_ag_context /* Xstorm aggregative context */; 4195 struct tstorm_eth_ag_context tstorm_ag_context /* Tstorm aggregative context */; 4196 struct cstorm_eth_ag_context cstorm_ag_context /* Cstorm aggregative context */; 4197 struct ustorm_eth_ag_context ustorm_ag_context /* Ustorm aggregative context */; 4198 struct timers_block_context timers_context /* Timers block context */; 4199 struct xstorm_eth_st_context xstorm_st_context /* Xstorm storm context */; 4200 struct cstorm_eth_st_context cstorm_st_context /* Cstorm storm context */; 4201}; 4202 4203 4204/* 4205 * union for sgl and raw data. 4206 */ 4207union eth_sgl_or_raw_data 4208{ 4209 uint16_t sgl[8] /* Scatter-gather list of SGEs used by this packet. This list includes the indices of the SGEs. */; 4210 uint32_t raw_data[4] /* raw data from Tstorm to the driver. */; 4211}; 4212 4213/* 4214 * eth FP end aggregation CQE parameters struct $$KEEP_ENDIANNESS$$ 4215 */ 4216struct eth_end_agg_rx_cqe 4217{ 4218 uint8_t type_error_flags; 4219#define ETH_END_AGG_RX_CQE_TYPE (0x3<<0) /* BitField type_error_flags (use enum eth_rx_cqe_type) */ 4220#define ETH_END_AGG_RX_CQE_TYPE_SHIFT 0 4221#define ETH_END_AGG_RX_CQE_SGL_RAW_SEL (0x1<<2) /* BitField type_error_flags (use enum eth_rx_fp_sel) */ 4222#define ETH_END_AGG_RX_CQE_SGL_RAW_SEL_SHIFT 2 4223#define ETH_END_AGG_RX_CQE_RESERVED0 (0x1F<<3) /* BitField type_error_flags */ 4224#define ETH_END_AGG_RX_CQE_RESERVED0_SHIFT 3 4225 uint8_t reserved1; 4226 uint8_t queue_index /* The aggregation queue index of this packet */; 4227 uint8_t reserved2; 4228 uint32_t timestamp_delta /* timestamp delta between first packet to last packet in aggregation */; 4229 uint16_t num_of_coalesced_segs /* Num of coalesced segments. */; 4230 uint16_t pkt_len /* Packet length */; 4231 uint8_t pure_ack_count /* Number of pure acks coalesced. */; 4232 uint8_t reserved3; 4233 uint16_t reserved4; 4234 union eth_sgl_or_raw_data sgl_or_raw_data /* union for sgl and raw data. */; 4235 uint32_t reserved5[8]; 4236}; 4237 4238 4239/* 4240 * regular eth FP CQE parameters struct $$KEEP_ENDIANNESS$$ 4241 */ 4242struct eth_fast_path_rx_cqe 4243{ 4244 uint8_t type_error_flags; 4245#define ETH_FAST_PATH_RX_CQE_TYPE (0x3<<0) /* BitField type_error_flags (use enum eth_rx_cqe_type) */ 4246#define ETH_FAST_PATH_RX_CQE_TYPE_SHIFT 0 4247#define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL (0x1<<2) /* BitField type_error_flags (use enum eth_rx_fp_sel) */ 4248#define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL_SHIFT 2 4249#define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<3) /* BitField type_error_flags Physical layer errors */ 4250#define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 3 4251#define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<4) /* BitField type_error_flags IP checksum error */ 4252#define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 4 4253#define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<5) /* BitField type_error_flags TCP/UDP checksum error */ 4254#define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 5 4255#define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x3<<6) /* BitField type_error_flags */ 4256#define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 6 4257 uint8_t status_flags; 4258#define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0) /* BitField status_flags (use enum eth_rss_hash_type) */ 4259#define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0 4260#define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3) /* BitField status_flags RSS hashing on/off */ 4261#define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3 4262#define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4) /* BitField status_flags if set to 1, this is a broadcast packet */ 4263#define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4 4264#define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5) /* BitField status_flags if set to 1, the MAC address was matched in the tstorm CAM search */ 4265#define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5 4266#define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6) /* BitField status_flags IP checksum validation was not performed (if packet is not IPv4) */ 4267#define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6 4268#define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7) /* BitField status_flags TCP/UDP checksum validation was not performed (if packet is not TCP/UDP or IPv6 extheaders exist) */ 4269#define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7 4270 uint8_t queue_index /* The aggregation queue index of this packet */; 4271 uint8_t placement_offset /* Placement offset from the start of the BD, in bytes */; 4272 uint32_t rss_hash_result /* RSS toeplitz hash result */; 4273 uint16_t vlan_tag /* Ethernet VLAN tag field */; 4274 uint16_t pkt_len_or_gro_seg_len /* Packet length (for non-TPA CQE) or GRO Segment Length (for TPA in GRO Mode) otherwise 0 */; 4275 uint16_t len_on_bd /* Number of bytes placed on the BD */; 4276 struct parsing_flags pars_flags; 4277 union eth_sgl_or_raw_data sgl_or_raw_data /* union for sgl and raw data. */; 4278 uint32_t reserved1[8]; 4279}; 4280 4281 4282/* 4283 * Command for setting classification flags for a client $$KEEP_ENDIANNESS$$ 4284 */ 4285struct eth_filter_rules_cmd 4286{ 4287 uint8_t cmd_general_data; 4288#define ETH_FILTER_RULES_CMD_RX_CMD (0x1<<0) /* BitField cmd_general_data should this cmd be applied for Rx */ 4289#define ETH_FILTER_RULES_CMD_RX_CMD_SHIFT 0 4290#define ETH_FILTER_RULES_CMD_TX_CMD (0x1<<1) /* BitField cmd_general_data should this cmd be applied for Tx */ 4291#define ETH_FILTER_RULES_CMD_TX_CMD_SHIFT 1 4292#define ETH_FILTER_RULES_CMD_RESERVED0 (0x3F<<2) /* BitField cmd_general_data */ 4293#define ETH_FILTER_RULES_CMD_RESERVED0_SHIFT 2 4294 uint8_t func_id /* the function id */; 4295 uint8_t client_id /* the client id */; 4296 uint8_t reserved1; 4297 uint16_t state; 4298#define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL (0x1<<0) /* BitField state drop all unicast packets */ 4299#define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL_SHIFT 0 4300#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL (0x1<<1) /* BitField state accept all unicast packets (subject to vlan) */ 4301#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL_SHIFT 1 4302#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED (0x1<<2) /* BitField state accept all unmatched unicast packets */ 4303#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED_SHIFT 2 4304#define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL (0x1<<3) /* BitField state drop all multicast packets */ 4305#define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL_SHIFT 3 4306#define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL (0x1<<4) /* BitField state accept all multicast packets (subject to vlan) */ 4307#define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL_SHIFT 4 4308#define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL (0x1<<5) /* BitField state accept all broadcast packets (subject to vlan) */ 4309#define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL_SHIFT 5 4310#define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN (0x1<<6) /* BitField state accept packets matched only by MAC (without checking vlan) */ 4311#define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN_SHIFT 6 4312#define ETH_FILTER_RULES_CMD_RESERVED2 (0x1FF<<7) /* BitField state */ 4313#define ETH_FILTER_RULES_CMD_RESERVED2_SHIFT 7 4314 uint16_t reserved3; 4315 struct regpair reserved4; 4316}; 4317 4318 4319/* 4320 * parameters for eth classification filters ramrod $$KEEP_ENDIANNESS$$ 4321 */ 4322struct eth_filter_rules_ramrod_data 4323{ 4324 struct eth_classify_header header; 4325 struct eth_filter_rules_cmd rules[FILTER_RULES_COUNT]; 4326}; 4327 4328 4329/* 4330 * parameters for eth classification configuration ramrod $$KEEP_ENDIANNESS$$ 4331 */ 4332struct eth_general_rules_ramrod_data 4333{ 4334 struct eth_classify_header header; 4335 union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT]; 4336}; 4337 4338 4339/* 4340 * The data for Halt ramrod 4341 */ 4342struct eth_halt_ramrod_data 4343{ 4344 uint32_t client_id /* id of this client. (5 bits are used) */; 4345 uint32_t reserved0; 4346}; 4347 4348 4349/* 4350 * destination and source mac address. 4351 */ 4352struct eth_mac_addresses 4353{ 4354#if defined(__BIG_ENDIAN) 4355 uint16_t dst_mid /* destination mac address 16 middle bits */; 4356 uint16_t dst_lo /* destination mac address 16 low bits */; 4357#elif defined(__LITTLE_ENDIAN) 4358 uint16_t dst_lo /* destination mac address 16 low bits */; 4359 uint16_t dst_mid /* destination mac address 16 middle bits */; 4360#endif 4361#if defined(__BIG_ENDIAN) 4362 uint16_t src_lo /* source mac address 16 low bits */; 4363 uint16_t dst_hi /* destination mac address 16 high bits */; 4364#elif defined(__LITTLE_ENDIAN) 4365 uint16_t dst_hi /* destination mac address 16 high bits */; 4366 uint16_t src_lo /* source mac address 16 low bits */; 4367#endif 4368#if defined(__BIG_ENDIAN) 4369 uint16_t src_hi /* source mac address 16 high bits */; 4370 uint16_t src_mid /* source mac address 16 middle bits */; 4371#elif defined(__LITTLE_ENDIAN) 4372 uint16_t src_mid /* source mac address 16 middle bits */; 4373 uint16_t src_hi /* source mac address 16 high bits */; 4374#endif 4375}; 4376 4377 4378/* 4379 * tunneling related data. 4380 */ 4381struct eth_tunnel_data 4382{ 4383#if defined(__BIG_ENDIAN) 4384 uint16_t dst_mid /* destination mac address 16 middle bits */; 4385 uint16_t dst_lo /* destination mac address 16 low bits */; 4386#elif defined(__LITTLE_ENDIAN) 4387 uint16_t dst_lo /* destination mac address 16 low bits */; 4388 uint16_t dst_mid /* destination mac address 16 middle bits */; 4389#endif 4390#if defined(__BIG_ENDIAN) 4391 uint16_t fw_ip_hdr_csum /* Fw Ip header checksum (with ALL ip header fields) for the outer IP header */; 4392 uint16_t dst_hi /* destination mac address 16 high bits */; 4393#elif defined(__LITTLE_ENDIAN) 4394 uint16_t dst_hi /* destination mac address 16 high bits */; 4395 uint16_t fw_ip_hdr_csum /* Fw Ip header checksum (with ALL ip header fields) for the outer IP header */; 4396#endif 4397#if defined(__BIG_ENDIAN) 4398 uint8_t flags; 4399#define ETH_TUNNEL_DATA_IP_HDR_TYPE_OUTER (0x1<<0) /* BitField flags Set in case outer IP header is ipV6 */ 4400#define ETH_TUNNEL_DATA_IP_HDR_TYPE_OUTER_SHIFT 0 4401#define ETH_TUNNEL_DATA_RESERVED (0x7F<<1) /* BitField flags Should be set with 0 */ 4402#define ETH_TUNNEL_DATA_RESERVED_SHIFT 1 4403 uint8_t ip_hdr_start_inner_w /* Inner IP header offset in WORDs (16-bit) from start of packet */; 4404 uint16_t pseudo_csum /* Pseudo checksum with length field=0 */; 4405#elif defined(__LITTLE_ENDIAN) 4406 uint16_t pseudo_csum /* Pseudo checksum with length field=0 */; 4407 uint8_t ip_hdr_start_inner_w /* Inner IP header offset in WORDs (16-bit) from start of packet */; 4408 uint8_t flags; 4409#define ETH_TUNNEL_DATA_IP_HDR_TYPE_OUTER (0x1<<0) /* BitField flags Set in case outer IP header is ipV6 */ 4410#define ETH_TUNNEL_DATA_IP_HDR_TYPE_OUTER_SHIFT 0 4411#define ETH_TUNNEL_DATA_RESERVED (0x7F<<1) /* BitField flags Should be set with 0 */ 4412#define ETH_TUNNEL_DATA_RESERVED_SHIFT 1 4413#endif 4414}; 4415 4416/* 4417 * union for mac addresses and for tunneling data. considered as tunneling data only if (tunnel_exist == 1). 4418 */ 4419union eth_mac_addr_or_tunnel_data 4420{ 4421 struct eth_mac_addresses mac_addr /* destination and source mac addresses. */; 4422 struct eth_tunnel_data tunnel_data /* tunneling related data. */; 4423}; 4424 4425 4426/* 4427 * Command for setting multicast classification for a client $$KEEP_ENDIANNESS$$ 4428 */ 4429struct eth_multicast_rules_cmd 4430{ 4431 uint8_t cmd_general_data; 4432#define ETH_MULTICAST_RULES_CMD_RX_CMD (0x1<<0) /* BitField cmd_general_data should this cmd be applied for Rx */ 4433#define ETH_MULTICAST_RULES_CMD_RX_CMD_SHIFT 0 4434#define ETH_MULTICAST_RULES_CMD_TX_CMD (0x1<<1) /* BitField cmd_general_data should this cmd be applied for Tx */ 4435#define ETH_MULTICAST_RULES_CMD_TX_CMD_SHIFT 1 4436#define ETH_MULTICAST_RULES_CMD_IS_ADD (0x1<<2) /* BitField cmd_general_data 1 for add rule, 0 for remove rule */ 4437#define ETH_MULTICAST_RULES_CMD_IS_ADD_SHIFT 2 4438#define ETH_MULTICAST_RULES_CMD_RESERVED0 (0x1F<<3) /* BitField cmd_general_data */ 4439#define ETH_MULTICAST_RULES_CMD_RESERVED0_SHIFT 3 4440 uint8_t func_id /* the function id */; 4441 uint8_t bin_id /* the bin to add this function to (0-255) */; 4442 uint8_t engine_id /* the approximate multicast engine id */; 4443 uint32_t reserved2; 4444 struct regpair reserved3; 4445}; 4446 4447 4448/* 4449 * parameters for multicast classification ramrod $$KEEP_ENDIANNESS$$ 4450 */ 4451struct eth_multicast_rules_ramrod_data 4452{ 4453 struct eth_classify_header header; 4454 struct eth_multicast_rules_cmd rules[MULTICAST_RULES_COUNT]; 4455}; 4456 4457 4458/* 4459 * Place holder for ramrods protocol specific data 4460 */ 4461struct ramrod_data 4462{ 4463 uint32_t data_lo; 4464 uint32_t data_hi; 4465}; 4466 4467/* 4468 * union for ramrod data for Ethernet protocol (CQE) (force size of 16 bits) 4469 */ 4470union eth_ramrod_data 4471{ 4472 struct ramrod_data general; 4473}; 4474 4475 4476/* 4477 * RSS toeplitz hash type, as reported in CQE 4478 */ 4479enum eth_rss_hash_type 4480{ 4481 DEFAULT_HASH_TYPE, 4482 IPV4_HASH_TYPE, 4483 TCP_IPV4_HASH_TYPE, 4484 IPV6_HASH_TYPE, 4485 TCP_IPV6_HASH_TYPE, 4486 VLAN_PRI_HASH_TYPE, 4487 E1HOV_PRI_HASH_TYPE, 4488 DSCP_HASH_TYPE, 4489 MAX_ETH_RSS_HASH_TYPE}; 4490 4491 4492/* 4493 * Ethernet RSS mode 4494 */ 4495enum eth_rss_mode 4496{ 4497 ETH_RSS_MODE_DISABLED, 4498 ETH_RSS_MODE_ESX51 /* RSS mode for Vmware ESX 5.1 (Only do RSS if packet is UDP with dst port that matches the UDP 4-tuble Destination Port mask and value) */, 4499 ETH_RSS_MODE_REGULAR /* Regular (ndis-like) RSS */, 4500 ETH_RSS_MODE_VLAN_PRI /* RSS based on inner-vlan priority field */, 4501 ETH_RSS_MODE_E1HOV_PRI /* RSS based on outer-vlan priority field */, 4502 ETH_RSS_MODE_IP_DSCP /* RSS based on IPv4 DSCP field */, 4503 MAX_ETH_RSS_MODE}; 4504 4505 4506/* 4507 * parameters for RSS update ramrod (E2) $$KEEP_ENDIANNESS$$ 4508 */ 4509struct eth_rss_update_ramrod_data 4510{ 4511 uint8_t rss_engine_id; 4512 uint8_t capabilities; 4513#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY (0x1<<0) /* BitField capabilitiesFunction RSS capabilities configuration of the IpV4 2-tupple capability */ 4514#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY_SHIFT 0 4515#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY (0x1<<1) /* BitField capabilitiesFunction RSS capabilities configuration of the IpV4 4-tupple capability for TCP */ 4516#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY_SHIFT 1 4517#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY (0x1<<2) /* BitField capabilitiesFunction RSS capabilities configuration of the IpV4 4-tupple capability for UDP */ 4518#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY_SHIFT 2 4519#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY (0x1<<3) /* BitField capabilitiesFunction RSS capabilities configuration of the IpV6 2-tupple capability */ 4520#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY_SHIFT 3 4521#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY (0x1<<4) /* BitField capabilitiesFunction RSS capabilities configuration of the IpV6 4-tupple capability for TCP */ 4522#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY_SHIFT 4 4523#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY (0x1<<5) /* BitField capabilitiesFunction RSS capabilities configuration of the IpV6 4-tupple capability for UDP */ 4524#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY_SHIFT 5 4525#define ETH_RSS_UPDATE_RAMROD_DATA_EN_5_TUPLE_CAPABILITY (0x1<<6) /* BitField capabilitiesFunction RSS capabilities configuration of the 5-tupple capability */ 4526#define ETH_RSS_UPDATE_RAMROD_DATA_EN_5_TUPLE_CAPABILITY_SHIFT 6 4527#define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY (0x1<<7) /* BitField capabilitiesFunction RSS capabilities if set update the rss keys */ 4528#define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY_SHIFT 7 4529 uint8_t rss_result_mask /* The mask for the lower byte of RSS result - defines which section of the indirection table will be used. To enable all table put here 0x7F */; 4530 uint8_t rss_mode /* The RSS mode for this function */; 4531 uint16_t udp_4tuple_dst_port_mask /* If UDP 4-tuple enabled, packets that match the mask and value are 4-tupled, the rest are 2-tupled. (Set to 0 to match all) */; 4532 uint16_t udp_4tuple_dst_port_value /* If UDP 4-tuple enabled, packets that match the mask and value are 4-tupled, the rest are 2-tupled. (Set to 0 to match all) */; 4533 uint8_t indirection_table[T_ETH_INDIRECTION_TABLE_SIZE] /* RSS indirection table */; 4534 uint32_t rss_key[T_ETH_RSS_KEY] /* RSS key supplied as by OS */; 4535 uint32_t echo; 4536 uint32_t reserved3; 4537}; 4538 4539 4540/* 4541 * The eth Rx Buffer Descriptor 4542 */ 4543struct eth_rx_bd 4544{ 4545 uint32_t addr_lo /* Single continuous buffer low pointer */; 4546 uint32_t addr_hi /* Single continuous buffer high pointer */; 4547}; 4548 4549 4550/* 4551 * Eth Rx Cqe structure- general structure for ramrods $$KEEP_ENDIANNESS$$ 4552 */ 4553struct common_ramrod_eth_rx_cqe 4554{ 4555 uint8_t ramrod_type; 4556#define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x3<<0) /* BitField ramrod_type (use enum eth_rx_cqe_type) */ 4557#define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0 4558#define COMMON_RAMROD_ETH_RX_CQE_ERROR (0x1<<2) /* BitField ramrod_type */ 4559#define COMMON_RAMROD_ETH_RX_CQE_ERROR_SHIFT 2 4560#define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x1F<<3) /* BitField ramrod_type */ 4561#define COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 3 4562 uint8_t conn_type /* only 3 bits are used */; 4563 uint16_t reserved1 /* protocol specific data */; 4564 uint32_t conn_and_cmd_data; 4565#define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0) /* BitField conn_and_cmd_data */ 4566#define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0 4567#define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24) /* BitField conn_and_cmd_data command id of the ramrod- use RamrodCommandIdEnum */ 4568#define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24 4569 struct ramrod_data protocol_data /* protocol specific data */; 4570 uint32_t echo; 4571 uint32_t reserved2[11]; 4572}; 4573 4574/* 4575 * Rx Last CQE in page (in ETH) 4576 */ 4577struct eth_rx_cqe_next_page 4578{ 4579 uint32_t addr_lo /* Next page low pointer */; 4580 uint32_t addr_hi /* Next page high pointer */; 4581 uint32_t reserved[14]; 4582}; 4583 4584/* 4585 * union for all eth rx cqe types (fix their sizes) 4586 */ 4587union eth_rx_cqe 4588{ 4589 struct eth_fast_path_rx_cqe fast_path_cqe; 4590 struct common_ramrod_eth_rx_cqe ramrod_cqe; 4591 struct eth_rx_cqe_next_page next_page_cqe; 4592 struct eth_end_agg_rx_cqe end_agg_cqe; 4593}; 4594 4595 4596/* 4597 * Values for RX ETH CQE type field 4598 */ 4599enum eth_rx_cqe_type 4600{ 4601 RX_ETH_CQE_TYPE_ETH_FASTPATH /* Fast path CQE */, 4602 RX_ETH_CQE_TYPE_ETH_RAMROD /* Slow path CQE */, 4603 RX_ETH_CQE_TYPE_ETH_START_AGG /* Fast path CQE */, 4604 RX_ETH_CQE_TYPE_ETH_STOP_AGG /* Slow path CQE */, 4605 MAX_ETH_RX_CQE_TYPE}; 4606 4607 4608/* 4609 * Type of SGL/Raw field in ETH RX fast path CQE 4610 */ 4611enum eth_rx_fp_sel 4612{ 4613 ETH_FP_CQE_REGULAR /* Regular CQE- no extra data */, 4614 ETH_FP_CQE_RAW /* Extra data is raw data- iscsi OOO */, 4615 MAX_ETH_RX_FP_SEL}; 4616 4617 4618/* 4619 * The eth Rx SGE Descriptor 4620 */ 4621struct eth_rx_sge 4622{ 4623 uint32_t addr_lo /* Single continuous buffer low pointer */; 4624 uint32_t addr_hi /* Single continuous buffer high pointer */; 4625}; 4626 4627 4628/* 4629 * common data for all protocols $$KEEP_ENDIANNESS$$ 4630 */ 4631struct spe_hdr 4632{ 4633 uint32_t conn_and_cmd_data; 4634#define SPE_HDR_CID (0xFFFFFF<<0) /* BitField conn_and_cmd_data */ 4635#define SPE_HDR_CID_SHIFT 0 4636#define SPE_HDR_CMD_ID (0xFF<<24) /* BitField conn_and_cmd_data command id of the ramrod- use enum common_spqe_cmd_id/eth_spqe_cmd_id/toe_spqe_cmd_id */ 4637#define SPE_HDR_CMD_ID_SHIFT 24 4638 uint16_t type; 4639#define SPE_HDR_CONN_TYPE (0xFF<<0) /* BitField type connection type. (3 bits are used) (use enum connection_type) */ 4640#define SPE_HDR_CONN_TYPE_SHIFT 0 4641#define SPE_HDR_FUNCTION_ID (0xFF<<8) /* BitField type */ 4642#define SPE_HDR_FUNCTION_ID_SHIFT 8 4643 uint16_t reserved1; 4644}; 4645 4646/* 4647 * specific data for ethernet slow path element 4648 */ 4649union eth_specific_data 4650{ 4651 uint8_t protocol_data[8] /* to fix this structure size to 8 bytes */; 4652 struct regpair client_update_ramrod_data /* The address of the data for client update ramrod */; 4653 struct regpair client_init_ramrod_init_data /* The data for client setup ramrod */; 4654 struct eth_halt_ramrod_data halt_ramrod_data /* Includes the client id to be deleted */; 4655 struct regpair update_data_addr /* physical address of the eth_rss_update_ramrod_data struct, as allocated by the driver */; 4656 struct eth_common_ramrod_data common_ramrod_data /* The data contain client ID need to the ramrod */; 4657 struct regpair classify_cfg_addr /* physical address of the eth_classify_rules_ramrod_data struct, as allocated by the driver */; 4658 struct regpair filter_cfg_addr /* physical address of the eth_filter_cfg_ramrod_data struct, as allocated by the driver */; 4659 struct regpair mcast_cfg_addr /* physical address of the eth_mcast_cfg_ramrod_data struct, as allocated by the driver */; 4660}; 4661 4662/* 4663 * Ethernet slow path element 4664 */ 4665struct eth_spe 4666{ 4667 struct spe_hdr hdr /* common data for all protocols */; 4668 union eth_specific_data data /* data specific to ethernet protocol */; 4669}; 4670 4671 4672/* 4673 * Ethernet command ID for slow path elements 4674 */ 4675enum eth_spqe_cmd_id 4676{ 4677 RAMROD_CMD_ID_ETH_UNUSED, 4678 RAMROD_CMD_ID_ETH_CLIENT_SETUP /* Setup a new L2 client */, 4679 RAMROD_CMD_ID_ETH_HALT /* Halt an L2 client */, 4680 RAMROD_CMD_ID_ETH_FORWARD_SETUP /* Setup a new FW channel */, 4681 RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP /* Setup a new Tx only queue */, 4682 RAMROD_CMD_ID_ETH_CLIENT_UPDATE /* Update an L2 client configuration */, 4683 RAMROD_CMD_ID_ETH_EMPTY /* Empty ramrod - used to synchronize iSCSI OOO */, 4684 RAMROD_CMD_ID_ETH_TERMINATE /* Terminate an L2 client */, 4685 RAMROD_CMD_ID_ETH_TPA_UPDATE /* update the tpa roles in L2 client */, 4686 RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES /* Add/remove classification filters for L2 client (in E2/E3 only) */, 4687 RAMROD_CMD_ID_ETH_FILTER_RULES /* Add/remove classification filters for L2 client (in E2/E3 only) */, 4688 RAMROD_CMD_ID_ETH_MULTICAST_RULES /* Add/remove multicast classification bin (in E2/E3 only) */, 4689 RAMROD_CMD_ID_ETH_RSS_UPDATE /* Update RSS configuration */, 4690 RAMROD_CMD_ID_ETH_SET_MAC /* Update RSS configuration */, 4691 MAX_ETH_SPQE_CMD_ID}; 4692 4693 4694/* 4695 * eth tpa update command 4696 */ 4697enum eth_tpa_update_command 4698{ 4699 TPA_UPDATE_NONE_COMMAND /* nop command */, 4700 TPA_UPDATE_ENABLE_COMMAND /* enable command */, 4701 TPA_UPDATE_DISABLE_COMMAND /* disable command */, 4702 MAX_ETH_TPA_UPDATE_COMMAND}; 4703 4704 4705/* 4706 * In case of LSO over IPv4 tunnel, whether to increment IP ID on external IP header or internal IP header 4707 */ 4708enum eth_tunnel_lso_inc_ip_id 4709{ 4710 EXT_HEADER /* Increment IP ID of external header (HW works on external, FW works on internal */, 4711 INT_HEADER /* Increment IP ID of internal header (HW works on internal, FW works on external */, 4712 MAX_ETH_TUNNEL_LSO_INC_IP_ID}; 4713 4714 4715/* 4716 * In case tunnel exist and L4 checksum offload (or outer ip header checksum), the pseudo checksum location, on packet or on BD. 4717 */ 4718enum eth_tunnel_non_lso_csum_location 4719{ 4720 CSUM_ON_PKT /* checksum is on the packet. */, 4721 CSUM_ON_BD /* checksum is on the BD. */, 4722 MAX_ETH_TUNNEL_NON_LSO_CSUM_LOCATION}; 4723 4724 4725/* 4726 * Tx regular BD structure $$KEEP_ENDIANNESS$$ 4727 */ 4728struct eth_tx_bd 4729{ 4730 uint32_t addr_lo /* Single continuous buffer low pointer */; 4731 uint32_t addr_hi /* Single continuous buffer high pointer */; 4732 uint16_t total_pkt_bytes /* Size of the entire packet, valid for non-LSO packets */; 4733 uint16_t nbytes /* Size of the data represented by the BD */; 4734 uint8_t reserved[4] /* keeps same size as other eth tx bd types */; 4735}; 4736 4737 4738/* 4739 * structure for easy accessibility to assembler 4740 */ 4741struct eth_tx_bd_flags 4742{ 4743 uint8_t as_bitfield; 4744#define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<0) /* BitField as_bitfield IP CKSUM flag,Relevant in START */ 4745#define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 0 4746#define ETH_TX_BD_FLAGS_L4_CSUM (0x1<<1) /* BitField as_bitfield L4 CKSUM flag,Relevant in START */ 4747#define ETH_TX_BD_FLAGS_L4_CSUM_SHIFT 1 4748#define ETH_TX_BD_FLAGS_VLAN_MODE (0x3<<2) /* BitField as_bitfield 00 - no vlan; 01 - inband Vlan; 10 outband Vlan (use enum eth_tx_vlan_type) */ 4749#define ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT 2 4750#define ETH_TX_BD_FLAGS_START_BD (0x1<<4) /* BitField as_bitfield Start of packet BD */ 4751#define ETH_TX_BD_FLAGS_START_BD_SHIFT 4 4752#define ETH_TX_BD_FLAGS_IS_UDP (0x1<<5) /* BitField as_bitfield flag that indicates that the current packet is a udp packet */ 4753#define ETH_TX_BD_FLAGS_IS_UDP_SHIFT 5 4754#define ETH_TX_BD_FLAGS_SW_LSO (0x1<<6) /* BitField as_bitfield LSO flag, Relevant in START */ 4755#define ETH_TX_BD_FLAGS_SW_LSO_SHIFT 6 4756#define ETH_TX_BD_FLAGS_IPV6 (0x1<<7) /* BitField as_bitfield set in case ipV6 packet, Relevant in START */ 4757#define ETH_TX_BD_FLAGS_IPV6_SHIFT 7 4758}; 4759 4760/* 4761 * The eth Tx Buffer Descriptor $$KEEP_ENDIANNESS$$ 4762 */ 4763struct eth_tx_start_bd 4764{ 4765 uint32_t addr_lo /* Single continuous buffer low pointer */; 4766 uint32_t addr_hi /* Single continuous buffer high pointer */; 4767 uint16_t nbd /* Num of BDs in packet: include parsInfoBD, Relevant in START(only in Everest) */; 4768 uint16_t nbytes /* Size of the data represented by the BD */; 4769 uint16_t vlan_or_ethertype /* Vlan structure: vlan_id is in lsb, then cfi and then priority vlan_id 12 bits (lsb), cfi 1 bit, priority 3 bits. In E2, this field should be set with etherType for VFs with no vlan */; 4770 struct eth_tx_bd_flags bd_flags; 4771 uint8_t general_data; 4772#define ETH_TX_START_BD_HDR_NBDS (0xF<<0) /* BitField general_data contains the number of BDs that contain Ethernet/IP/TCP headers, for full/partial LSO modes */ 4773#define ETH_TX_START_BD_HDR_NBDS_SHIFT 0 4774#define ETH_TX_START_BD_FORCE_VLAN_MODE (0x1<<4) /* BitField general_data force vlan mode according to bds (vlan mode can change accroding to global configuration) */ 4775#define ETH_TX_START_BD_FORCE_VLAN_MODE_SHIFT 4 4776#define ETH_TX_START_BD_PARSE_NBDS (0x3<<5) /* BitField general_data Determines the number of parsing BDs in packet. Number of parsing BDs in packet is (parse_nbds+1). */ 4777#define ETH_TX_START_BD_PARSE_NBDS_SHIFT 5 4778#define ETH_TX_START_BD_TUNNEL_EXIST (0x1<<7) /* BitField general_data set in case of tunneling encapsulated packet */ 4779#define ETH_TX_START_BD_TUNNEL_EXIST_SHIFT 7 4780}; 4781 4782/* 4783 * Tx parsing BD structure for ETH E1/E1h $$KEEP_ENDIANNESS$$ 4784 */ 4785struct eth_tx_parse_bd_e1x 4786{ 4787 uint16_t global_data; 4788#define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W (0xF<<0) /* BitField global_data IP header Offset in WORDs from start of packet */ 4789#define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W_SHIFT 0 4790#define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE (0x3<<4) /* BitField global_data marks ethernet address type (use enum eth_addr_type) */ 4791#define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE_SHIFT 4 4792#define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN (0x1<<6) /* BitField global_data */ 4793#define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN_SHIFT 6 4794#define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN (0x1<<7) /* BitField global_data */ 4795#define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN_SHIFT 7 4796#define ETH_TX_PARSE_BD_E1X_NS_FLG (0x1<<8) /* BitField global_data an optional addition to ECN that protects against accidental or malicious concealment of marked packets from the TCP sender. */ 4797#define ETH_TX_PARSE_BD_E1X_NS_FLG_SHIFT 8 4798#define ETH_TX_PARSE_BD_E1X_RESERVED0 (0x7F<<9) /* BitField global_data reserved bit, should be set with 0 */ 4799#define ETH_TX_PARSE_BD_E1X_RESERVED0_SHIFT 9 4800 uint8_t tcp_flags; 4801#define ETH_TX_PARSE_BD_E1X_FIN_FLG (0x1<<0) /* BitField tcp_flagsState flags End of data flag */ 4802#define ETH_TX_PARSE_BD_E1X_FIN_FLG_SHIFT 0 4803#define ETH_TX_PARSE_BD_E1X_SYN_FLG (0x1<<1) /* BitField tcp_flagsState flags Synchronize sequence numbers flag */ 4804#define ETH_TX_PARSE_BD_E1X_SYN_FLG_SHIFT 1 4805#define ETH_TX_PARSE_BD_E1X_RST_FLG (0x1<<2) /* BitField tcp_flagsState flags Reset connection flag */ 4806#define ETH_TX_PARSE_BD_E1X_RST_FLG_SHIFT 2 4807#define ETH_TX_PARSE_BD_E1X_PSH_FLG (0x1<<3) /* BitField tcp_flagsState flags Push flag */ 4808#define ETH_TX_PARSE_BD_E1X_PSH_FLG_SHIFT 3 4809#define ETH_TX_PARSE_BD_E1X_ACK_FLG (0x1<<4) /* BitField tcp_flagsState flags Acknowledgment number valid flag */ 4810#define ETH_TX_PARSE_BD_E1X_ACK_FLG_SHIFT 4 4811#define ETH_TX_PARSE_BD_E1X_URG_FLG (0x1<<5) /* BitField tcp_flagsState flags Urgent pointer valid flag */ 4812#define ETH_TX_PARSE_BD_E1X_URG_FLG_SHIFT 5 4813#define ETH_TX_PARSE_BD_E1X_ECE_FLG (0x1<<6) /* BitField tcp_flagsState flags ECN-Echo */ 4814#define ETH_TX_PARSE_BD_E1X_ECE_FLG_SHIFT 6 4815#define ETH_TX_PARSE_BD_E1X_CWR_FLG (0x1<<7) /* BitField tcp_flagsState flags Congestion Window Reduced */ 4816#define ETH_TX_PARSE_BD_E1X_CWR_FLG_SHIFT 7 4817 uint8_t ip_hlen_w /* IP header length in WORDs */; 4818 uint16_t total_hlen_w /* IP+TCP+ETH */; 4819 uint16_t tcp_pseudo_csum /* Checksum of pseudo header with length field=0 */; 4820 uint16_t lso_mss /* for LSO mode */; 4821 uint16_t ip_id /* for LSO mode */; 4822 uint32_t tcp_send_seq /* for LSO mode */; 4823}; 4824 4825/* 4826 * Tx parsing BD structure for ETH E2 $$KEEP_ENDIANNESS$$ 4827 */ 4828struct eth_tx_parse_bd_e2 4829{ 4830 union eth_mac_addr_or_tunnel_data data /* union for mac addresses and for tunneling data. considered as tunneling data only if (tunnel_exist == 1). */; 4831 uint32_t parsing_data; 4832#define ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W (0x7FF<<0) /* BitField parsing_data TCP/UDP header Offset in WORDs from start of packet */ 4833#define ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W_SHIFT 0 4834#define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW (0xF<<11) /* BitField parsing_data TCP header size in DOUBLE WORDS */ 4835#define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT 11 4836#define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR (0x1<<15) /* BitField parsing_data a flag to indicate an ipv6 packet with extension headers. If set on LSO packet, pseudo CS should be placed in TCP CS field without length field */ 4837#define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR_SHIFT 15 4838#define ETH_TX_PARSE_BD_E2_LSO_MSS (0x3FFF<<16) /* BitField parsing_data for LSO mode */ 4839#define ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT 16 4840#define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE (0x3<<30) /* BitField parsing_data marks ethernet address type (use enum eth_addr_type) */ 4841#define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT 30 4842}; 4843 4844/* 4845 * Tx 2nd parsing BD structure for ETH packet $$KEEP_ENDIANNESS$$ 4846 */ 4847struct eth_tx_parse_2nd_bd 4848{ 4849 uint16_t global_data; 4850#define ETH_TX_PARSE_2ND_BD_IP_HDR_START_OUTER_W (0xF<<0) /* BitField global_data Outer IP header offset in WORDs (16-bit) from start of packet */ 4851#define ETH_TX_PARSE_2ND_BD_IP_HDR_START_OUTER_W_SHIFT 0 4852#define ETH_TX_PARSE_2ND_BD_RESERVED0 (0x1<<4) /* BitField global_data should be set with 0 */ 4853#define ETH_TX_PARSE_2ND_BD_RESERVED0_SHIFT 4 4854#define ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN (0x1<<5) /* BitField global_data */ 4855#define ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN_SHIFT 5 4856#define ETH_TX_PARSE_2ND_BD_NS_FLG (0x1<<6) /* BitField global_data an optional addition to ECN that protects against accidental or malicious concealment of marked packets from the TCP sender. */ 4857#define ETH_TX_PARSE_2ND_BD_NS_FLG_SHIFT 6 4858#define ETH_TX_PARSE_2ND_BD_TUNNEL_UDP_EXIST (0x1<<7) /* BitField global_data Set in case UDP header exists in tunnel outer hedears. */ 4859#define ETH_TX_PARSE_2ND_BD_TUNNEL_UDP_EXIST_SHIFT 7 4860#define ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W (0x1F<<8) /* BitField global_data Outer IP header length in WORDs (16-bit). Valid only for IpV4. */ 4861#define ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W_SHIFT 8 4862#define ETH_TX_PARSE_2ND_BD_RESERVED1 (0x7<<13) /* BitField global_data should be set with 0 */ 4863#define ETH_TX_PARSE_2ND_BD_RESERVED1_SHIFT 13 4864 uint16_t reserved2; 4865 uint8_t tcp_flags; 4866#define ETH_TX_PARSE_2ND_BD_FIN_FLG (0x1<<0) /* BitField tcp_flagsState flags End of data flag */ 4867#define ETH_TX_PARSE_2ND_BD_FIN_FLG_SHIFT 0 4868#define ETH_TX_PARSE_2ND_BD_SYN_FLG (0x1<<1) /* BitField tcp_flagsState flags Synchronize sequence numbers flag */ 4869#define ETH_TX_PARSE_2ND_BD_SYN_FLG_SHIFT 1 4870#define ETH_TX_PARSE_2ND_BD_RST_FLG (0x1<<2) /* BitField tcp_flagsState flags Reset connection flag */ 4871#define ETH_TX_PARSE_2ND_BD_RST_FLG_SHIFT 2 4872#define ETH_TX_PARSE_2ND_BD_PSH_FLG (0x1<<3) /* BitField tcp_flagsState flags Push flag */ 4873#define ETH_TX_PARSE_2ND_BD_PSH_FLG_SHIFT 3 4874#define ETH_TX_PARSE_2ND_BD_ACK_FLG (0x1<<4) /* BitField tcp_flagsState flags Acknowledgment number valid flag */ 4875#define ETH_TX_PARSE_2ND_BD_ACK_FLG_SHIFT 4 4876#define ETH_TX_PARSE_2ND_BD_URG_FLG (0x1<<5) /* BitField tcp_flagsState flags Urgent pointer valid flag */ 4877#define ETH_TX_PARSE_2ND_BD_URG_FLG_SHIFT 5 4878#define ETH_TX_PARSE_2ND_BD_ECE_FLG (0x1<<6) /* BitField tcp_flagsState flags ECN-Echo */ 4879#define ETH_TX_PARSE_2ND_BD_ECE_FLG_SHIFT 6 4880#define ETH_TX_PARSE_2ND_BD_CWR_FLG (0x1<<7) /* BitField tcp_flagsState flags Congestion Window Reduced */ 4881#define ETH_TX_PARSE_2ND_BD_CWR_FLG_SHIFT 7 4882 uint8_t reserved3; 4883 uint8_t tunnel_udp_hdr_start_w /* Offset (in WORDs) from start of packet to tunnel UDP header. (if exist) */; 4884 uint8_t fw_ip_hdr_to_payload_w /* In IpV4, the length (in WORDs) from the FW IpV4 header start to the payload start. In IpV6, the length (in WORDs) from the FW IpV6 header end to the payload start. However, if extension headers are included, their length is counted here as well. */; 4885 uint16_t fw_ip_csum_wo_len_flags_frag /* For the IP header which is set by the FW, the IP checksum without length, flags and fragment offset. */; 4886 uint16_t hw_ip_id /* The IP ID to be set by HW for LSO packets in tunnel mode. */; 4887 uint32_t tcp_send_seq /* The TCP sequence number for LSO packets. */; 4888}; 4889 4890/* 4891 * The last BD in the BD memory will hold a pointer to the next BD memory 4892 */ 4893struct eth_tx_next_bd 4894{ 4895 uint32_t addr_lo /* Single continuous buffer low pointer */; 4896 uint32_t addr_hi /* Single continuous buffer high pointer */; 4897 uint8_t reserved[8] /* keeps same size as other eth tx bd types */; 4898}; 4899 4900/* 4901 * union for 4 Bd types 4902 */ 4903union eth_tx_bd_types 4904{ 4905 struct eth_tx_start_bd start_bd /* the first bd in a packets */; 4906 struct eth_tx_bd reg_bd /* the common bd */; 4907 struct eth_tx_parse_bd_e1x parse_bd_e1x /* parsing info BD for e1/e1h */; 4908 struct eth_tx_parse_bd_e2 parse_bd_e2 /* parsing info BD for e2 */; 4909 struct eth_tx_parse_2nd_bd parse_2nd_bd /* 2nd parsing info BD */; 4910 struct eth_tx_next_bd next_bd /* Bd that contains the address of the next page */; 4911}; 4912 4913/* 4914 * array of 13 bds as appears in the eth xstorm context 4915 */ 4916struct eth_tx_bds_array 4917{ 4918 union eth_tx_bd_types bds[13]; 4919}; 4920 4921 4922/* 4923 * VLAN mode on TX BDs 4924 */ 4925enum eth_tx_vlan_type 4926{ 4927 X_ETH_NO_VLAN, 4928 X_ETH_OUTBAND_VLAN, 4929 X_ETH_INBAND_VLAN, 4930 X_ETH_FW_ADDED_VLAN /* Driver should not use this! */, 4931 MAX_ETH_TX_VLAN_TYPE}; 4932 4933 4934/* 4935 * Ethernet VLAN filtering mode in E1x 4936 */ 4937enum eth_vlan_filter_mode 4938{ 4939 ETH_VLAN_FILTER_ANY_VLAN /* Dont filter by vlan */, 4940 ETH_VLAN_FILTER_SPECIFIC_VLAN /* Only the vlan_id is allowed */, 4941 ETH_VLAN_FILTER_CLASSIFY /* Vlan will be added to CAM for classification */, 4942 MAX_ETH_VLAN_FILTER_MODE}; 4943 4944 4945/* 4946 * MAC filtering configuration command header $$KEEP_ENDIANNESS$$ 4947 */ 4948struct mac_configuration_hdr 4949{ 4950 uint8_t length /* number of entries valid in this command (6 bits) */; 4951 uint8_t offset /* offset of the first entry in the list */; 4952 uint16_t client_id /* the client id which this ramrod is sent on. 5b is used. */; 4953 uint32_t echo /* echo value to be sent to driver on event ring */; 4954}; 4955 4956/* 4957 * MAC address in list for ramrod $$KEEP_ENDIANNESS$$ 4958 */ 4959struct mac_configuration_entry 4960{ 4961 uint16_t lsb_mac_addr /* 2 LSB of MAC address (should be given in big endien - driver should do hton to this number!!!) */; 4962 uint16_t middle_mac_addr /* 2 middle bytes of MAC address (should be given in big endien - driver should do hton to this number!!!) */; 4963 uint16_t msb_mac_addr /* 2 MSB of MAC address (should be given in big endien - driver should do hton to this number!!!) */; 4964 uint16_t vlan_id /* The inner vlan id (12b). Used either in vlan_in_cam for mac_valn pair or for vlan filtering */; 4965 uint8_t pf_id /* The pf id, for multi function mode */; 4966 uint8_t flags; 4967#define MAC_CONFIGURATION_ENTRY_ACTION_TYPE (0x1<<0) /* BitField flags configures the action to be done in cam (used only is slow path handlers) (use enum set_mac_action_type) */ 4968#define MAC_CONFIGURATION_ENTRY_ACTION_TYPE_SHIFT 0 4969#define MAC_CONFIGURATION_ENTRY_RDMA_MAC (0x1<<1) /* BitField flags If set, this MAC also belongs to RDMA client */ 4970#define MAC_CONFIGURATION_ENTRY_RDMA_MAC_SHIFT 1 4971#define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE (0x3<<2) /* BitField flags (use enum eth_vlan_filter_mode) */ 4972#define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE_SHIFT 2 4973#define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1<<4) /* BitField flags BitField flags 0 - cant remove vlan 1 - can remove vlan. relevant only to everest1 */ 4974#define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 4 4975#define MAC_CONFIGURATION_ENTRY_BROADCAST (0x1<<5) /* BitField flags BitField flags 0 - not broadcast 1 - broadcast. relevant only to everest1 */ 4976#define MAC_CONFIGURATION_ENTRY_BROADCAST_SHIFT 5 4977#define MAC_CONFIGURATION_ENTRY_RESERVED1 (0x3<<6) /* BitField flags */ 4978#define MAC_CONFIGURATION_ENTRY_RESERVED1_SHIFT 6 4979 uint16_t reserved0; 4980 uint32_t clients_bit_vector /* Bit vector for the clients which should receive this MAC. */; 4981}; 4982 4983/* 4984 * MAC filtering configuration command 4985 */ 4986struct mac_configuration_cmd 4987{ 4988 struct mac_configuration_hdr hdr /* header */; 4989 struct mac_configuration_entry config_table[64] /* table of 64 MAC configuration entries: addresses and target table entries */; 4990}; 4991 4992 4993/* 4994 * Set-MAC command type (in E1x) 4995 */ 4996enum set_mac_action_type 4997{ 4998 T_ETH_MAC_COMMAND_INVALIDATE, 4999 T_ETH_MAC_COMMAND_SET, 5000 MAX_SET_MAC_ACTION_TYPE}; 5001 5002 5003/* 5004 * Ethernet TPA Modes 5005 */ 5006enum tpa_mode 5007{ 5008 TPA_LRO /* LRO mode TPA */, 5009 TPA_GRO /* GRO mode TPA */, 5010 MAX_TPA_MODE}; 5011 5012 5013/* 5014 * tpa update ramrod data $$KEEP_ENDIANNESS$$ 5015 */ 5016struct tpa_update_ramrod_data 5017{ 5018 uint8_t update_ipv4 /* none, enable or disable */; 5019 uint8_t update_ipv6 /* none, enable or disable */; 5020 uint8_t client_id /* client init flow control data */; 5021 uint8_t max_tpa_queues /* maximal TPA queues allowed for this client */; 5022 uint8_t max_sges_for_packet /* The maximal number of SGEs that can be used for one packet. depends on MTU and SGE size. must be 0 if SGEs are disabled */; 5023 uint8_t complete_on_both_clients /* If set and the client has different sp_client, completion will be sent to both rings */; 5024 uint8_t dont_verify_rings_pause_thr_flg /* If set, the rings pause thresholds will not be verified by firmware. */; 5025 uint8_t tpa_mode /* TPA mode to use (LRO or GRO) */; 5026 uint16_t sge_buff_size /* Size of the buffers pointed by SGEs */; 5027 uint16_t max_agg_size /* maximal size for the aggregated TPA packets, reprted by the host */; 5028 uint32_t sge_page_base_lo /* The address to fetch the next sges from (low) */; 5029 uint32_t sge_page_base_hi /* The address to fetch the next sges from (high) */; 5030 uint16_t sge_pause_thr_low /* number of remaining sges under which, we send pause message */; 5031 uint16_t sge_pause_thr_high /* number of remaining sges above which, we send un-pause message */; 5032}; 5033 5034 5035/* 5036 * approximate-match multicast filtering for E1H per function in Tstorm 5037 */ 5038struct tstorm_eth_approximate_match_multicast_filtering 5039{ 5040 uint32_t mcast_add_hash_bit_array[8] /* Bit array for multicast hash filtering.Each bit supports a hash function result if to accept this multicast dst address. */; 5041}; 5042 5043 5044/* 5045 * Common configuration parameters per function in Tstorm $$KEEP_ENDIANNESS$$ 5046 */ 5047struct tstorm_eth_function_common_config 5048{ 5049 uint16_t config_flags; 5050#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0) /* BitField config_flagsGeneral configuration flags configuration of the port RSS IpV4 2-tupple capability */ 5051#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0 5052#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1) /* BitField config_flagsGeneral configuration flags configuration of the port RSS IpV4 4-tupple capability */ 5053#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1 5054#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2) /* BitField config_flagsGeneral configuration flags configuration of the port RSS IpV4 2-tupple capability */ 5055#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2 5056#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3) /* BitField config_flagsGeneral configuration flags configuration of the port RSS IpV6 4-tupple capability */ 5057#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3 5058#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4) /* BitField config_flagsGeneral configuration flags RSS mode of operation (use enum eth_rss_mode) */ 5059#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4 5060#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE (0x1<<7) /* BitField config_flagsGeneral configuration flags 0 - Dont filter by vlan, 1 - Filter according to the vlans specificied in mac_filter_config */ 5061#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE_SHIFT 7 5062#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0xFF<<8) /* BitField config_flagsGeneral configuration flags */ 5063#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 8 5064 uint8_t rss_result_mask /* The mask for the lower byte of RSS result - defines which section of the indirection table will be used. To enable all table put here 0x7F */; 5065 uint8_t reserved1; 5066 uint16_t vlan_id[2] /* VLANs of this function. VLAN filtering is determine according to vlan_filtering_enable. */; 5067}; 5068 5069 5070/* 5071 * MAC filtering configuration parameters per port in Tstorm $$KEEP_ENDIANNESS$$ 5072 */ 5073struct tstorm_eth_mac_filter_config 5074{ 5075 uint32_t ucast_drop_all /* bit vector in which the clients which drop all unicast packets are set */; 5076 uint32_t ucast_accept_all /* bit vector in which clients that accept all unicast packets are set */; 5077 uint32_t mcast_drop_all /* bit vector in which the clients which drop all multicast packets are set */; 5078 uint32_t mcast_accept_all /* bit vector in which clients that accept all multicast packets are set */; 5079 uint32_t bcast_accept_all /* bit vector in which clients that accept all broadcast packets are set */; 5080 uint32_t vlan_filter[2] /* bit vector for VLAN filtering. Clients which enforce filtering of vlan[x] should be marked in vlan_filter[x]. In E1 only vlan_filter[1] is checked. The primary vlan is taken from the CAM target table. */; 5081 uint32_t unmatched_unicast /* bit vector in which clients that accept unmatched unicast packets are set */; 5082}; 5083 5084 5085/* 5086 * tx only queue init ramrod data $$KEEP_ENDIANNESS$$ 5087 */ 5088struct tx_queue_init_ramrod_data 5089{ 5090 struct client_init_general_data general /* client init general data */; 5091 struct client_init_tx_data tx /* client init tx data */; 5092}; 5093 5094 5095/* 5096 * Three RX producers for ETH 5097 */ 5098struct ustorm_eth_rx_producers 5099{ 5100#if defined(__BIG_ENDIAN) 5101 uint16_t bd_prod /* Producer of the RX BD ring */; 5102 uint16_t cqe_prod /* Producer of the RX CQE ring */; 5103#elif defined(__LITTLE_ENDIAN) 5104 uint16_t cqe_prod /* Producer of the RX CQE ring */; 5105 uint16_t bd_prod /* Producer of the RX BD ring */; 5106#endif 5107#if defined(__BIG_ENDIAN) 5108 uint16_t reserved; 5109 uint16_t sge_prod /* Producer of the RX SGE ring */; 5110#elif defined(__LITTLE_ENDIAN) 5111 uint16_t sge_prod /* Producer of the RX SGE ring */; 5112 uint16_t reserved; 5113#endif 5114}; 5115 5116 5117/* 5118 * The data afex vif list ramrod need $$KEEP_ENDIANNESS$$ 5119 */ 5120struct afex_vif_list_ramrod_data 5121{ 5122 uint8_t afex_vif_list_command /* set get, clear all a VIF list id defined by enum vif_list_rule_kind */; 5123 uint8_t func_bit_map /* the function bit map to set */; 5124 uint16_t vif_list_index /* the VIF list, in a per pf vector to add this function to */; 5125 uint8_t func_to_clear /* the func id to clear in case of clear func mode */; 5126 uint8_t echo; 5127 uint16_t reserved1; 5128}; 5129 5130 5131/* 5132 * cfc delete event data $$KEEP_ENDIANNESS$$ 5133 */ 5134struct cfc_del_event_data 5135{ 5136 uint32_t cid /* cid of deleted connection */; 5137 uint32_t reserved0; 5138 uint32_t reserved1; 5139}; 5140 5141 5142/* 5143 * per-port SAFC demo variables 5144 */ 5145struct cmng_flags_per_port 5146{ 5147 uint32_t cmng_enables; 5148#define CMNG_FLAGS_PER_PORT_FAIRNESS_VN (0x1<<0) /* BitField cmng_enablesenables flag for fairness and rate shaping between protocols, vnics and COSes if set, enable fairness between vnics */ 5149#define CMNG_FLAGS_PER_PORT_FAIRNESS_VN_SHIFT 0 5150#define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN (0x1<<1) /* BitField cmng_enablesenables flag for fairness and rate shaping between protocols, vnics and COSes if set, enable rate shaping between vnics */ 5151#define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN_SHIFT 1 5152#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS (0x1<<2) /* BitField cmng_enablesenables flag for fairness and rate shaping between protocols, vnics and COSes if set, enable fairness between COSes */ 5153#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_SHIFT 2 5154#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE (0x1<<3) /* BitField cmng_enablesenables flag for fairness and rate shaping between protocols, vnics and COSes (use enum fairness_mode) */ 5155#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE_SHIFT 3 5156#define __CMNG_FLAGS_PER_PORT_RESERVED0 (0xFFFFFFF<<4) /* BitField cmng_enablesenables flag for fairness and rate shaping between protocols, vnics and COSes reserved */ 5157#define __CMNG_FLAGS_PER_PORT_RESERVED0_SHIFT 4 5158 uint32_t __reserved1; 5159}; 5160 5161 5162/* 5163 * per-port rate shaping variables 5164 */ 5165struct rate_shaping_vars_per_port 5166{ 5167 uint32_t rs_periodic_timeout /* timeout of periodic timer */; 5168 uint32_t rs_threshold /* threshold, below which we start to stop queues */; 5169}; 5170 5171/* 5172 * per-port fairness variables 5173 */ 5174struct fairness_vars_per_port 5175{ 5176 uint32_t upper_bound /* Quota for a protocol/vnic */; 5177 uint32_t fair_threshold /* almost-empty threshold */; 5178 uint32_t fairness_timeout /* timeout of fairness timer */; 5179 uint32_t reserved0; 5180}; 5181 5182/* 5183 * per-port SAFC variables 5184 */ 5185struct safc_struct_per_port 5186{ 5187#if defined(__BIG_ENDIAN) 5188 uint16_t __reserved1; 5189 uint8_t __reserved0; 5190 uint8_t safc_timeout_usec /* timeout to stop queues on SAFC pause command */; 5191#elif defined(__LITTLE_ENDIAN) 5192 uint8_t safc_timeout_usec /* timeout to stop queues on SAFC pause command */; 5193 uint8_t __reserved0; 5194 uint16_t __reserved1; 5195#endif 5196 uint8_t cos_to_traffic_types[MAX_COS_NUMBER] /* translate cos to service traffics types */; 5197 uint16_t cos_to_pause_mask[NUM_OF_SAFC_BITS] /* QM pause mask for each class of service in the SAFC frame */; 5198}; 5199 5200/* 5201 * Per-port congestion management variables 5202 */ 5203struct cmng_struct_per_port 5204{ 5205 struct rate_shaping_vars_per_port rs_vars; 5206 struct fairness_vars_per_port fair_vars; 5207 struct safc_struct_per_port safc_vars; 5208 struct cmng_flags_per_port flags; 5209}; 5210 5211/* 5212 * a single rate shaping counter. can be used as protocol or vnic counter 5213 */ 5214struct rate_shaping_counter 5215{ 5216 uint32_t quota /* Quota for a protocol/vnic */; 5217#if defined(__BIG_ENDIAN) 5218 uint16_t __reserved0; 5219 uint16_t rate /* Vnic/Protocol rate in units of Mega-bits/sec */; 5220#elif defined(__LITTLE_ENDIAN) 5221 uint16_t rate /* Vnic/Protocol rate in units of Mega-bits/sec */; 5222 uint16_t __reserved0; 5223#endif 5224}; 5225 5226/* 5227 * per-vnic rate shaping variables 5228 */ 5229struct rate_shaping_vars_per_vn 5230{ 5231 struct rate_shaping_counter vn_counter /* per-vnic counter */; 5232}; 5233 5234/* 5235 * per-vnic fairness variables 5236 */ 5237struct fairness_vars_per_vn 5238{ 5239 uint32_t cos_credit_delta[MAX_COS_NUMBER] /* used for incrementing the credit */; 5240 uint32_t vn_credit_delta /* used for incrementing the credit */; 5241 uint32_t __reserved0; 5242}; 5243 5244/* 5245 * cmng port init state 5246 */ 5247struct cmng_vnic 5248{ 5249 struct rate_shaping_vars_per_vn vnic_max_rate[4]; 5250 struct fairness_vars_per_vn vnic_min_rate[4]; 5251}; 5252 5253/* 5254 * cmng port init state 5255 */ 5256struct cmng_init 5257{ 5258 struct cmng_struct_per_port port; 5259 struct cmng_vnic vnic; 5260}; 5261 5262 5263/* 5264 * driver parameters for congestion management init, all rates are in Mbps 5265 */ 5266struct cmng_init_input 5267{ 5268 uint32_t port_rate; 5269 uint16_t vnic_min_rate[4] /* rates are in Mbps */; 5270 uint16_t vnic_max_rate[4] /* rates are in Mbps */; 5271 uint16_t cos_min_rate[MAX_COS_NUMBER] /* rates are in Mbps */; 5272 uint16_t cos_to_pause_mask[MAX_COS_NUMBER]; 5273 struct cmng_flags_per_port flags; 5274}; 5275 5276 5277/* 5278 * Protocol-common command ID for slow path elements 5279 */ 5280enum common_spqe_cmd_id 5281{ 5282 RAMROD_CMD_ID_COMMON_UNUSED, 5283 RAMROD_CMD_ID_COMMON_FUNCTION_START /* Start a function (for PFs only) */, 5284 RAMROD_CMD_ID_COMMON_FUNCTION_STOP /* Stop a function (for PFs only) */, 5285 RAMROD_CMD_ID_COMMON_FUNCTION_UPDATE /* niv update function */, 5286 RAMROD_CMD_ID_COMMON_CFC_DEL /* Delete a connection from CFC */, 5287 RAMROD_CMD_ID_COMMON_CFC_DEL_WB /* Delete a connection from CFC (with write back) */, 5288 RAMROD_CMD_ID_COMMON_STAT_QUERY /* Collect statistics counters */, 5289 RAMROD_CMD_ID_COMMON_STOP_TRAFFIC /* Stop Tx traffic (before DCB updates) */, 5290 RAMROD_CMD_ID_COMMON_START_TRAFFIC /* Start Tx traffic (after DCB updates) */, 5291 RAMROD_CMD_ID_COMMON_AFEX_VIF_LISTS /* niv vif lists */, 5292 RAMROD_CMD_ID_COMMON_SET_TIMESYNC /* Set Timesync Parameters (E3 Only) */, 5293 MAX_COMMON_SPQE_CMD_ID}; 5294 5295 5296/* 5297 * Per-protocol connection types 5298 */ 5299enum connection_type 5300{ 5301 ETH_CONNECTION_TYPE /* Ethernet */, 5302 TOE_CONNECTION_TYPE /* TOE */, 5303 RDMA_CONNECTION_TYPE /* RDMA */, 5304 ISCSI_CONNECTION_TYPE /* iSCSI */, 5305 FCOE_CONNECTION_TYPE /* FCoE */, 5306 RESERVED_CONNECTION_TYPE_0, 5307 RESERVED_CONNECTION_TYPE_1, 5308 RESERVED_CONNECTION_TYPE_2, 5309 NONE_CONNECTION_TYPE /* General- used for common slow path */, 5310 MAX_CONNECTION_TYPE}; 5311 5312 5313/* 5314 * Cos modes 5315 */ 5316enum cos_mode 5317{ 5318 OVERRIDE_COS /* Firmware deduce cos according to DCB */, 5319 STATIC_COS /* Firmware has constant queues per CoS */, 5320 FW_WRR /* Firmware keep fairness between different CoSes */, 5321 MAX_COS_MODE}; 5322 5323 5324/* 5325 * Dynamic HC counters set by the driver 5326 */ 5327struct hc_dynamic_drv_counter 5328{ 5329 uint32_t val[HC_SB_MAX_DYNAMIC_INDICES] /* 4 bytes * 4 indices = 2 lines */; 5330}; 5331 5332/* 5333 * zone A per-queue data 5334 */ 5335struct cstorm_queue_zone_data 5336{ 5337 struct hc_dynamic_drv_counter hc_dyn_drv_cnt /* 4 bytes * 4 indices = 2 lines */; 5338 struct regpair reserved[2]; 5339}; 5340 5341 5342/* 5343 * Vf-PF channel data in cstorm ram (non-triggered zone) 5344 */ 5345struct vf_pf_channel_zone_data 5346{ 5347 uint32_t msg_addr_lo /* the message address on VF memory */; 5348 uint32_t msg_addr_hi /* the message address on VF memory */; 5349}; 5350 5351/* 5352 * zone for VF non-triggered data 5353 */ 5354struct non_trigger_vf_zone 5355{ 5356 struct vf_pf_channel_zone_data vf_pf_channel /* vf-pf channel zone data */; 5357}; 5358 5359/* 5360 * Vf-PF channel trigger zone in cstorm ram 5361 */ 5362struct vf_pf_channel_zone_trigger 5363{ 5364 uint8_t addr_valid /* indicates that a vf-pf message is pending. MUST be set AFTER the message address. */; 5365}; 5366 5367/* 5368 * zone that triggers the in-bound interrupt 5369 */ 5370struct trigger_vf_zone 5371{ 5372#if defined(__BIG_ENDIAN) 5373 uint16_t reserved1; 5374 uint8_t reserved0; 5375 struct vf_pf_channel_zone_trigger vf_pf_channel; 5376#elif defined(__LITTLE_ENDIAN) 5377 struct vf_pf_channel_zone_trigger vf_pf_channel; 5378 uint8_t reserved0; 5379 uint16_t reserved1; 5380#endif 5381 uint32_t reserved2; 5382}; 5383 5384/* 5385 * zone B per-VF data 5386 */ 5387struct cstorm_vf_zone_data 5388{ 5389 struct non_trigger_vf_zone non_trigger /* zone for VF non-triggered data */; 5390 struct trigger_vf_zone trigger /* zone that triggers the in-bound interrupt */; 5391}; 5392 5393 5394/* 5395 * Dynamic host coalescing init parameters, per state machine 5396 */ 5397struct dynamic_hc_sm_config 5398{ 5399 uint32_t threshold[3] /* thresholds of number of outstanding bytes */; 5400 uint8_t shift_per_protocol[HC_SB_MAX_DYNAMIC_INDICES] /* bytes difference of each protocol is shifted right by this value */; 5401 uint8_t hc_timeout0[HC_SB_MAX_DYNAMIC_INDICES] /* timeout for level 0 for each protocol, in units of usec */; 5402 uint8_t hc_timeout1[HC_SB_MAX_DYNAMIC_INDICES] /* timeout for level 1 for each protocol, in units of usec */; 5403 uint8_t hc_timeout2[HC_SB_MAX_DYNAMIC_INDICES] /* timeout for level 2 for each protocol, in units of usec */; 5404 uint8_t hc_timeout3[HC_SB_MAX_DYNAMIC_INDICES] /* timeout for level 3 for each protocol, in units of usec */; 5405}; 5406 5407/* 5408 * Dynamic host coalescing init parameters 5409 */ 5410struct dynamic_hc_config 5411{ 5412 struct dynamic_hc_sm_config sm_config[HC_SB_MAX_SM] /* Configuration per state machine */; 5413}; 5414 5415 5416struct e2_integ_data 5417{ 5418#if defined(__BIG_ENDIAN) 5419 uint8_t flags; 5420#define E2_INTEG_DATA_TESTING_EN (0x1<<0) /* BitField flags integration testing enabled */ 5421#define E2_INTEG_DATA_TESTING_EN_SHIFT 0 5422#define E2_INTEG_DATA_LB_TX (0x1<<1) /* BitField flags flag indicating this connection will transmit on loopback */ 5423#define E2_INTEG_DATA_LB_TX_SHIFT 1 5424#define E2_INTEG_DATA_COS_TX (0x1<<2) /* BitField flags flag indicating this connection will transmit according to cos field */ 5425#define E2_INTEG_DATA_COS_TX_SHIFT 2 5426#define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3) /* BitField flags flag indicating this connection will activate the opportunistic QM credit flow */ 5427#define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3 5428#define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4) /* BitField flags flag indicating this connection will release the door bell queue (DQ) */ 5429#define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4 5430#define E2_INTEG_DATA_RESERVED (0x7<<5) /* BitField flags */ 5431#define E2_INTEG_DATA_RESERVED_SHIFT 5 5432 uint8_t cos /* cos of the connection (relevant only in cos transmitting connections, when cosTx is set */; 5433 uint8_t voq /* voq to return credit on. Normally equal to port (i.e. always 0 in E2 operational connections). in cos tests equal to cos. in loopback tests equal to LB_PORT (=4) */; 5434 uint8_t pbf_queue /* pbf queue to transmit on. Normally equal to port (i.e. always 0 in E2 operational connections). in cos tests equal to cos. in loopback tests equal to LB_PORT (=4) */; 5435#elif defined(__LITTLE_ENDIAN) 5436 uint8_t pbf_queue /* pbf queue to transmit on. Normally equal to port (i.e. always 0 in E2 operational connections). in cos tests equal to cos. in loopback tests equal to LB_PORT (=4) */; 5437 uint8_t voq /* voq to return credit on. Normally equal to port (i.e. always 0 in E2 operational connections). in cos tests equal to cos. in loopback tests equal to LB_PORT (=4) */; 5438 uint8_t cos /* cos of the connection (relevant only in cos transmitting connections, when cosTx is set */; 5439 uint8_t flags; 5440#define E2_INTEG_DATA_TESTING_EN (0x1<<0) /* BitField flags integration testing enabled */ 5441#define E2_INTEG_DATA_TESTING_EN_SHIFT 0 5442#define E2_INTEG_DATA_LB_TX (0x1<<1) /* BitField flags flag indicating this connection will transmit on loopback */ 5443#define E2_INTEG_DATA_LB_TX_SHIFT 1 5444#define E2_INTEG_DATA_COS_TX (0x1<<2) /* BitField flags flag indicating this connection will transmit according to cos field */ 5445#define E2_INTEG_DATA_COS_TX_SHIFT 2 5446#define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3) /* BitField flags flag indicating this connection will activate the opportunistic QM credit flow */ 5447#define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3 5448#define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4) /* BitField flags flag indicating this connection will release the door bell queue (DQ) */ 5449#define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4 5450#define E2_INTEG_DATA_RESERVED (0x7<<5) /* BitField flags */ 5451#define E2_INTEG_DATA_RESERVED_SHIFT 5 5452#endif 5453#if defined(__BIG_ENDIAN) 5454 uint16_t reserved3; 5455 uint8_t reserved2; 5456 uint8_t ramEn /* context area reserved for reading enable bit from ram */; 5457#elif defined(__LITTLE_ENDIAN) 5458 uint8_t ramEn /* context area reserved for reading enable bit from ram */; 5459 uint8_t reserved2; 5460 uint16_t reserved3; 5461#endif 5462}; 5463 5464 5465/* 5466 * set mac event data $$KEEP_ENDIANNESS$$ 5467 */ 5468struct eth_event_data 5469{ 5470 uint32_t echo /* set mac echo data to return to driver */; 5471 uint32_t reserved0; 5472 uint32_t reserved1; 5473}; 5474 5475 5476/* 5477 * pf-vf event data $$KEEP_ENDIANNESS$$ 5478 */ 5479struct vf_pf_event_data 5480{ 5481 uint8_t vf_id /* VF ID (0-63) */; 5482 uint8_t reserved0; 5483 uint16_t reserved1; 5484 uint32_t msg_addr_lo /* message address on Vf (low 32 bits) */; 5485 uint32_t msg_addr_hi /* message address on Vf (high 32 bits) */; 5486}; 5487 5488/* 5489 * VF FLR event data $$KEEP_ENDIANNESS$$ 5490 */ 5491struct vf_flr_event_data 5492{ 5493 uint8_t vf_id /* VF ID (0-63) */; 5494 uint8_t reserved0; 5495 uint16_t reserved1; 5496 uint32_t reserved2; 5497 uint32_t reserved3; 5498}; 5499 5500/* 5501 * malicious VF event data $$KEEP_ENDIANNESS$$ 5502 */ 5503struct malicious_vf_event_data 5504{ 5505 uint8_t vf_id /* VF ID (0-63) */; 5506 uint8_t err_id /* reason for malicious notification */; 5507 uint16_t reserved1; 5508 uint32_t reserved2; 5509 uint32_t reserved3; 5510}; 5511 5512/* 5513 * vif list event data $$KEEP_ENDIANNESS$$ 5514 */ 5515struct vif_list_event_data 5516{ 5517 uint8_t func_bit_map /* bit map of pf indice */; 5518 uint8_t echo; 5519 uint16_t reserved0; 5520 uint32_t reserved1; 5521 uint32_t reserved2; 5522}; 5523 5524/* 5525 * function update event data $$KEEP_ENDIANNESS$$ 5526 */ 5527struct function_update_event_data 5528{ 5529 uint8_t echo; 5530 uint8_t reserved; 5531 uint16_t reserved0; 5532 uint32_t reserved1; 5533 uint32_t reserved2; 5534}; 5535 5536/* 5537 * union for all event ring message types 5538 */ 5539union event_data 5540{ 5541 struct vf_pf_event_data vf_pf_event /* vf-pf event data */; 5542 struct eth_event_data eth_event /* set mac event data */; 5543 struct cfc_del_event_data cfc_del_event /* cfc delete event data */; 5544 struct vf_flr_event_data vf_flr_event /* vf flr event data */; 5545 struct malicious_vf_event_data malicious_vf_event /* malicious vf event data */; 5546 struct vif_list_event_data vif_list_event /* vif list event data */; 5547 struct function_update_event_data function_update_event /* function update event data */; 5548}; 5549 5550 5551/* 5552 * per PF event ring data 5553 */ 5554struct event_ring_data 5555{ 5556 struct regpair_native base_addr /* ring base address */; 5557#if defined(__BIG_ENDIAN) 5558 uint8_t index_id /* index ID within the status block */; 5559 uint8_t sb_id /* status block ID */; 5560 uint16_t producer /* event ring producer */; 5561#elif defined(__LITTLE_ENDIAN) 5562 uint16_t producer /* event ring producer */; 5563 uint8_t sb_id /* status block ID */; 5564 uint8_t index_id /* index ID within the status block */; 5565#endif 5566 uint32_t reserved0; 5567}; 5568 5569 5570/* 5571 * event ring message element (each element is 128 bits) $$KEEP_ENDIANNESS$$ 5572 */ 5573struct event_ring_msg 5574{ 5575 uint8_t opcode; 5576 uint8_t error /* error on the mesasage */; 5577 uint16_t reserved1; 5578 union event_data data /* message data (96 bits data) */; 5579}; 5580 5581/* 5582 * event ring next page element (128 bits) 5583 */ 5584struct event_ring_next 5585{ 5586 struct regpair addr /* Address of the next page of the ring */; 5587 uint32_t reserved[2]; 5588}; 5589 5590/* 5591 * union for event ring element types (each element is 128 bits) 5592 */ 5593union event_ring_elem 5594{ 5595 struct event_ring_msg message /* event ring message */; 5596 struct event_ring_next next_page /* event ring next page */; 5597}; 5598 5599 5600/* 5601 * Common event ring opcodes 5602 */ 5603enum event_ring_opcode 5604{ 5605 EVENT_RING_OPCODE_VF_PF_CHANNEL, 5606 EVENT_RING_OPCODE_FUNCTION_START /* Start a function (for PFs only) */, 5607 EVENT_RING_OPCODE_FUNCTION_STOP /* Stop a function (for PFs only) */, 5608 EVENT_RING_OPCODE_CFC_DEL /* Delete a connection from CFC */, 5609 EVENT_RING_OPCODE_CFC_DEL_WB /* Delete a connection from CFC (with write back) */, 5610 EVENT_RING_OPCODE_STAT_QUERY /* Collect statistics counters */, 5611 EVENT_RING_OPCODE_STOP_TRAFFIC /* Stop Tx traffic (before DCB updates) */, 5612 EVENT_RING_OPCODE_START_TRAFFIC /* Start Tx traffic (after DCB updates) */, 5613 EVENT_RING_OPCODE_VF_FLR /* VF FLR indication for PF */, 5614 EVENT_RING_OPCODE_MALICIOUS_VF /* Malicious VF operation detected */, 5615 EVENT_RING_OPCODE_FORWARD_SETUP /* Initialize forward channel */, 5616 EVENT_RING_OPCODE_RSS_UPDATE_RULES /* Update RSS configuration */, 5617 EVENT_RING_OPCODE_FUNCTION_UPDATE /* function update */, 5618 EVENT_RING_OPCODE_AFEX_VIF_LISTS /* event ring opcode niv vif lists */, 5619 EVENT_RING_OPCODE_SET_MAC /* Add/remove MAC (in E1x only) */, 5620 EVENT_RING_OPCODE_CLASSIFICATION_RULES /* Add/remove MAC or VLAN (in E2/E3 only) */, 5621 EVENT_RING_OPCODE_FILTERS_RULES /* Add/remove classification filters for L2 client (in E2/E3 only) */, 5622 EVENT_RING_OPCODE_MULTICAST_RULES /* Add/remove multicast classification bin (in E2/E3 only) */, 5623 EVENT_RING_OPCODE_SET_TIMESYNC /* Set Timesync Parameters (E3 Only) */, 5624 MAX_EVENT_RING_OPCODE}; 5625 5626 5627/* 5628 * Modes for fairness algorithm 5629 */ 5630enum fairness_mode 5631{ 5632 FAIRNESS_COS_WRR_MODE /* Weighted round robin mode (used in Google) */, 5633 FAIRNESS_COS_ETS_MODE /* ETS mode (used in FCoE) */, 5634 MAX_FAIRNESS_MODE}; 5635 5636 5637/* 5638 * Priority and cos $$KEEP_ENDIANNESS$$ 5639 */ 5640struct priority_cos 5641{ 5642 uint8_t priority /* Priority */; 5643 uint8_t cos /* Cos */; 5644 uint16_t reserved1; 5645}; 5646 5647/* 5648 * The data for flow control configuration $$KEEP_ENDIANNESS$$ 5649 */ 5650struct flow_control_configuration 5651{ 5652 struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES] /* traffic_type to priority cos */; 5653 uint8_t dcb_enabled /* If DCB mode is enabled then traffic class to priority array is fully initialized and there must be inner VLAN */; 5654 uint8_t dcb_version /* DCB version Increase by one on each DCB update */; 5655 uint8_t dont_add_pri_0 /* In case, the priority is 0, and the packet has no vlan, the firmware wont add vlan */; 5656 uint8_t reserved1; 5657 uint32_t reserved2; 5658}; 5659 5660 5661/* 5662 * $$KEEP_ENDIANNESS$$ 5663 */ 5664struct function_start_data 5665{ 5666 uint8_t function_mode /* the function mode */; 5667 uint8_t allow_npar_tx_switching /* If set, inter-pf tx switching is allowed in Switch Independant function mode. (E2/E3 Only) */; 5668 uint16_t sd_vlan_tag /* value of Vlan in case of switch depended multi-function mode */; 5669 uint16_t vif_id /* value of VIF id in case of NIV multi-function mode */; 5670 uint8_t path_id; 5671 uint8_t network_cos_mode /* The cos mode for network traffic. */; 5672 uint8_t dmae_cmd_id /* The DMAE command id to use for FW DMAE transactions */; 5673 uint8_t gre_tunnel_mode /* GRE Tunnel Mode to enable on the Function (E2/E3 Only) */; 5674 uint8_t gre_tunnel_rss /* Type of RSS to perform on GRE Tunneled packets */; 5675 uint8_t nvgre_clss_en /* If set, NVGRE tunneled packets are classified according to their inner MAC (gre_mode must be NVGRE_TUNNEL) */; 5676 uint16_t reserved1[2]; 5677}; 5678 5679 5680/* 5681 * $$KEEP_ENDIANNESS$$ 5682 */ 5683struct function_update_data 5684{ 5685 uint8_t vif_id_change_flg /* If set, vif_id will be checked */; 5686 uint8_t afex_default_vlan_change_flg /* If set, afex_default_vlan will be checked */; 5687 uint8_t allowed_priorities_change_flg /* If set, allowed_priorities will be checked */; 5688 uint8_t network_cos_mode_change_flg /* If set, network_cos_mode will be checked */; 5689 uint16_t vif_id /* value of VIF id in case of NIV multi-function mode */; 5690 uint16_t afex_default_vlan /* value of default Vlan in case of NIV mf */; 5691 uint8_t allowed_priorities /* bit vector of allowed Vlan priorities for this VIF */; 5692 uint8_t network_cos_mode /* The cos mode for network traffic. */; 5693 uint8_t lb_mode_en_change_flg /* If set, lb_mode_en will be checked */; 5694 uint8_t lb_mode_en /* If set, niv loopback mode will be enabled */; 5695 uint8_t tx_switch_suspend_change_flg /* If set, tx_switch_suspend will be checked */; 5696 uint8_t tx_switch_suspend /* If set, TX switching TO this function will be disabled and packets will be dropped */; 5697 uint8_t echo; 5698 uint8_t reserved1; 5699 uint8_t update_gre_cfg_flg /* If set, GRE config for the function will be updated according to the gre_tunnel_rss and nvgre_clss_en fields */; 5700 uint8_t gre_tunnel_mode /* GRE Tunnel Mode to enable on the Function (E2/E3 Only) */; 5701 uint8_t gre_tunnel_rss /* Type of RSS to perform on GRE Tunneled packets */; 5702 uint8_t nvgre_clss_en /* If set, NVGRE tunneled packets are classified according to their inner MAC (gre_mode must be NVGRE_TUNNEL) */; 5703 uint32_t reserved3; 5704}; 5705 5706 5707/* 5708 * FW version stored in the Xstorm RAM 5709 */ 5710struct fw_version 5711{ 5712#if defined(__BIG_ENDIAN) 5713 uint8_t engineering /* firmware current engineering version */; 5714 uint8_t revision /* firmware current revision version */; 5715 uint8_t minor /* firmware current minor version */; 5716 uint8_t major /* firmware current major version */; 5717#elif defined(__LITTLE_ENDIAN) 5718 uint8_t major /* firmware current major version */; 5719 uint8_t minor /* firmware current minor version */; 5720 uint8_t revision /* firmware current revision version */; 5721 uint8_t engineering /* firmware current engineering version */; 5722#endif 5723 uint32_t flags; 5724#define FW_VERSION_OPTIMIZED (0x1<<0) /* BitField flags if set, this is optimized ASM */ 5725#define FW_VERSION_OPTIMIZED_SHIFT 0 5726#define FW_VERSION_BIG_ENDIEN (0x1<<1) /* BitField flags if set, this is big-endien ASM */ 5727#define FW_VERSION_BIG_ENDIEN_SHIFT 1 5728#define FW_VERSION_CHIP_VERSION (0x3<<2) /* BitField flags 0 - E1, 1 - E1H */ 5729#define FW_VERSION_CHIP_VERSION_SHIFT 2 5730#define __FW_VERSION_RESERVED (0xFFFFFFF<<4) /* BitField flags */ 5731#define __FW_VERSION_RESERVED_SHIFT 4 5732}; 5733 5734 5735/* 5736 * GRE RSS Mode 5737 */ 5738enum gre_rss_mode 5739{ 5740 GRE_OUTER_HEADERS_RSS /* RSS for GRE Packets is performed on the outer headers */, 5741 GRE_INNER_HEADERS_RSS /* RSS for GRE Packets is performed on the inner headers */, 5742 NVGRE_KEY_ENTROPY_RSS /* RSS for NVGRE Packets is done based on a hash containing the entropy bits from the GRE Key Field (gre_tunnel must be NVGRE_TUNNEL) */, 5743 MAX_GRE_RSS_MODE}; 5744 5745 5746/* 5747 * GRE Tunnel Mode 5748 */ 5749enum gre_tunnel_type 5750{ 5751 NO_GRE_TUNNEL, 5752 NVGRE_TUNNEL /* NV-GRE Tunneling Microsoft L2 over GRE. GRE header contains mandatory Key Field. */, 5753 L2GRE_TUNNEL /* L2-GRE Tunneling General L2 over GRE. GRE can contain Key field with Tenant ID and Sequence Field */, 5754 IPGRE_TUNNEL /* IP-GRE Tunneling IP over GRE. GRE may contain Key field with Tenant ID, Sequence Field and/or Checksum Field */, 5755 MAX_GRE_TUNNEL_TYPE}; 5756 5757 5758/* 5759 * Dynamic Host-Coalescing - Driver(host) counters 5760 */ 5761struct hc_dynamic_sb_drv_counters 5762{ 5763 uint32_t dynamic_hc_drv_counter[HC_SB_MAX_DYNAMIC_INDICES] /* Dynamic HC counters written by drivers */; 5764}; 5765 5766 5767/* 5768 * 2 bytes. configuration/state parameters for a single protocol index 5769 */ 5770struct hc_index_data 5771{ 5772#if defined(__BIG_ENDIAN) 5773 uint8_t flags; 5774#define HC_INDEX_DATA_SM_ID (0x1<<0) /* BitField flags Index to a state machine. Can be 0 or 1 */ 5775#define HC_INDEX_DATA_SM_ID_SHIFT 0 5776#define HC_INDEX_DATA_HC_ENABLED (0x1<<1) /* BitField flags if set, host coalescing would be done for this index */ 5777#define HC_INDEX_DATA_HC_ENABLED_SHIFT 1 5778#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2) /* BitField flags if set, dynamic HC will be done for this index */ 5779#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2 5780#define HC_INDEX_DATA_RESERVE (0x1F<<3) /* BitField flags */ 5781#define HC_INDEX_DATA_RESERVE_SHIFT 3 5782 uint8_t timeout /* the timeout values for this index. Units are 4 usec */; 5783#elif defined(__LITTLE_ENDIAN) 5784 uint8_t timeout /* the timeout values for this index. Units are 4 usec */; 5785 uint8_t flags; 5786#define HC_INDEX_DATA_SM_ID (0x1<<0) /* BitField flags Index to a state machine. Can be 0 or 1 */ 5787#define HC_INDEX_DATA_SM_ID_SHIFT 0 5788#define HC_INDEX_DATA_HC_ENABLED (0x1<<1) /* BitField flags if set, host coalescing would be done for this index */ 5789#define HC_INDEX_DATA_HC_ENABLED_SHIFT 1 5790#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2) /* BitField flags if set, dynamic HC will be done for this index */ 5791#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2 5792#define HC_INDEX_DATA_RESERVE (0x1F<<3) /* BitField flags */ 5793#define HC_INDEX_DATA_RESERVE_SHIFT 3 5794#endif 5795}; 5796 5797 5798/* 5799 * HC state-machine 5800 */ 5801struct hc_status_block_sm 5802{ 5803#if defined(__BIG_ENDIAN) 5804 uint8_t igu_seg_id; 5805 uint8_t igu_sb_id /* sb_id within the IGU */; 5806 uint8_t timer_value /* Determines the time_to_expire */; 5807 uint8_t __flags; 5808#elif defined(__LITTLE_ENDIAN) 5809 uint8_t __flags; 5810 uint8_t timer_value /* Determines the time_to_expire */; 5811 uint8_t igu_sb_id /* sb_id within the IGU */; 5812 uint8_t igu_seg_id; 5813#endif 5814 uint32_t time_to_expire /* The time in which it expects to wake up */; 5815}; 5816 5817/* 5818 * hold PCI identification variables- used in various places in firmware 5819 */ 5820struct pci_entity 5821{ 5822#if defined(__BIG_ENDIAN) 5823 uint8_t vf_valid /* If set, this is a VF, otherwise it is PF */; 5824 uint8_t vf_id /* VF ID (0-63). Value of 0xFF means VF not valid */; 5825 uint8_t vnic_id /* Virtual NIC ID (0-3) */; 5826 uint8_t pf_id /* PCI physical function number (0-7). The LSB of this field is the port ID */; 5827#elif defined(__LITTLE_ENDIAN) 5828 uint8_t pf_id /* PCI physical function number (0-7). The LSB of this field is the port ID */; 5829 uint8_t vnic_id /* Virtual NIC ID (0-3) */; 5830 uint8_t vf_id /* VF ID (0-63). Value of 0xFF means VF not valid */; 5831 uint8_t vf_valid /* If set, this is a VF, otherwise it is PF */; 5832#endif 5833}; 5834 5835/* 5836 * The fast-path status block meta-data, common to all chips 5837 */ 5838struct hc_sb_data 5839{ 5840 struct regpair_native host_sb_addr /* Host status block address */; 5841 struct hc_status_block_sm state_machine[HC_SB_MAX_SM] /* Holds the state machines of the status block */; 5842 struct pci_entity p_func /* vnic / port of the status block to be set by the driver */; 5843#if defined(__BIG_ENDIAN) 5844 uint8_t rsrv0; 5845 uint8_t state; 5846 uint8_t dhc_qzone_id /* used in E2 only, to specify the HW queue zone ID used for this status block dynamic HC counters */; 5847 uint8_t same_igu_sb_1b /* Indicate that both state-machines acts like single sm */; 5848#elif defined(__LITTLE_ENDIAN) 5849 uint8_t same_igu_sb_1b /* Indicate that both state-machines acts like single sm */; 5850 uint8_t dhc_qzone_id /* used in E2 only, to specify the HW queue zone ID used for this status block dynamic HC counters */; 5851 uint8_t state; 5852 uint8_t rsrv0; 5853#endif 5854 struct regpair_native rsrv1[2]; 5855}; 5856 5857 5858/* 5859 * Segment types for host coaslescing 5860 */ 5861enum hc_segment 5862{ 5863 HC_REGULAR_SEGMENT, 5864 HC_DEFAULT_SEGMENT, 5865 MAX_HC_SEGMENT}; 5866 5867 5868/* 5869 * The fast-path status block meta-data 5870 */ 5871struct hc_sp_status_block_data 5872{ 5873 struct regpair_native host_sb_addr /* Host status block address */; 5874#if defined(__BIG_ENDIAN) 5875 uint8_t rsrv1; 5876 uint8_t state; 5877 uint8_t igu_seg_id /* segment id of the IGU */; 5878 uint8_t igu_sb_id /* sb_id within the IGU */; 5879#elif defined(__LITTLE_ENDIAN) 5880 uint8_t igu_sb_id /* sb_id within the IGU */; 5881 uint8_t igu_seg_id /* segment id of the IGU */; 5882 uint8_t state; 5883 uint8_t rsrv1; 5884#endif 5885 struct pci_entity p_func /* vnic / port of the status block to be set by the driver */; 5886}; 5887 5888 5889/* 5890 * The fast-path status block meta-data 5891 */ 5892struct hc_status_block_data_e1x 5893{ 5894 struct hc_index_data index_data[HC_SB_MAX_INDICES_E1X] /* configuration/state parameters for a single protocol index */; 5895 struct hc_sb_data common /* The fast-path status block meta-data, common to all chips */; 5896}; 5897 5898 5899/* 5900 * The fast-path status block meta-data 5901 */ 5902struct hc_status_block_data_e2 5903{ 5904 struct hc_index_data index_data[HC_SB_MAX_INDICES_E2] /* configuration/state parameters for a single protocol index */; 5905 struct hc_sb_data common /* The fast-path status block meta-data, common to all chips */; 5906}; 5907 5908 5909/* 5910 * IGU block operartion modes (in Everest2) 5911 */ 5912enum igu_mode 5913{ 5914 HC_IGU_BC_MODE /* Backward compatible mode */, 5915 HC_IGU_NBC_MODE /* Non-backward compatible mode */, 5916 MAX_IGU_MODE}; 5917 5918 5919/* 5920 * IP versions 5921 */ 5922enum ip_ver 5923{ 5924 IP_V4, 5925 IP_V6, 5926 MAX_IP_VER}; 5927 5928 5929/* 5930 * Malicious VF error ID 5931 */ 5932enum malicious_vf_error_id 5933{ 5934 VF_PF_CHANNEL_NOT_READY /* Writing to VF/PF channel when it is not ready */, 5935 ETH_ILLEGAL_BD_LENGTHS /* TX BD lengths error was detected */, 5936 ETH_PACKET_TOO_SHORT /* TX packet is shorter then reported on BDs */, 5937 ETH_PAYLOAD_TOO_BIG /* TX packet is greater then MTU */, 5938 ETH_ILLEGAL_ETH_TYPE /* TX packet reported without VLAN but eth type is 0x8100 */, 5939 ETH_ILLEGAL_LSO_HDR_LEN /* LSO header length on BDs and on hdr_nbd do not match */, 5940 ETH_TOO_MANY_BDS /* Tx packet has too many BDs */, 5941 ETH_ZERO_HDR_NBDS /* hdr_nbds field is zero */, 5942 ETH_START_BD_NOT_SET /* start_bd should be set on first TX BD in packet */, 5943 ETH_ILLEGAL_PARSE_NBDS /* Tx packet with parse_nbds field which is not legal */, 5944 ETH_IPV6_AND_CHECKSUM /* Tx packet with IP checksum on IPv6 */, 5945 ETH_VLAN_FLG_INCORRECT /* Tx packet with incorrect VLAN flag */, 5946 ETH_ILLEGAL_LSO_MSS /* Tx LSO packet with illegal MSS value */, 5947 ETH_TUNNEL_NOT_SUPPORTED /* Tunneling packets are not supported in current connection */, 5948 MAX_MALICIOUS_VF_ERROR_ID}; 5949 5950 5951/* 5952 * Multi-function modes 5953 */ 5954enum mf_mode 5955{ 5956 SINGLE_FUNCTION, 5957 MULTI_FUNCTION_SD /* Switch dependent (vlan based) */, 5958 MULTI_FUNCTION_SI /* Switch independent (mac based) */, 5959 MULTI_FUNCTION_AFEX /* Switch dependent (niv based) */, 5960 MAX_MF_MODE}; 5961 5962 5963/* 5964 * Protocol-common statistics collected by the Tstorm (per pf) $$KEEP_ENDIANNESS$$ 5965 */ 5966struct tstorm_per_pf_stats 5967{ 5968 struct regpair rcv_error_bytes /* number of bytes received with errors */; 5969}; 5970 5971/* 5972 * $$KEEP_ENDIANNESS$$ 5973 */ 5974struct per_pf_stats 5975{ 5976 struct tstorm_per_pf_stats tstorm_pf_statistics; 5977}; 5978 5979 5980/* 5981 * Protocol-common statistics collected by the Tstorm (per port) $$KEEP_ENDIANNESS$$ 5982 */ 5983struct tstorm_per_port_stats 5984{ 5985 uint32_t mac_discard /* number of packets with mac errors */; 5986 uint32_t mac_filter_discard /* the number of good frames dropped because of no perfect match to MAC/VLAN address */; 5987 uint32_t brb_truncate_discard /* the number of packtes that were dropped because they were truncated in BRB */; 5988 uint32_t mf_tag_discard /* the number of good frames dropped because of no match to the outer vlan/VNtag */; 5989 uint32_t packet_drop /* general packet drop conter- incremented for every packet drop */; 5990 uint32_t reserved; 5991}; 5992 5993/* 5994 * $$KEEP_ENDIANNESS$$ 5995 */ 5996struct per_port_stats 5997{ 5998 struct tstorm_per_port_stats tstorm_port_statistics; 5999}; 6000 6001 6002/* 6003 * Protocol-common statistics collected by the Tstorm (per client) $$KEEP_ENDIANNESS$$ 6004 */ 6005struct tstorm_per_queue_stats 6006{ 6007 struct regpair rcv_ucast_bytes /* number of bytes in unicast packets received without errors and pass the filter */; 6008 uint32_t rcv_ucast_pkts /* number of unicast packets received without errors and pass the filter */; 6009 uint32_t checksum_discard /* number of total packets received with checksum error */; 6010 struct regpair rcv_bcast_bytes /* number of bytes in broadcast packets received without errors and pass the filter */; 6011 uint32_t rcv_bcast_pkts /* number of packets in broadcast packets received without errors and pass the filter */; 6012 uint32_t pkts_too_big_discard /* number of too long packets received */; 6013 struct regpair rcv_mcast_bytes /* number of bytes in multicast packets received without errors and pass the filter */; 6014 uint32_t rcv_mcast_pkts /* number of packets in multicast packets received without errors and pass the filter */; 6015 uint32_t ttl0_discard /* the number of good frames dropped because of TTL=0 */; 6016 uint16_t no_buff_discard; 6017 uint16_t reserved0; 6018 uint32_t reserved1; 6019}; 6020 6021/* 6022 * Protocol-common statistics collected by the Ustorm (per client) $$KEEP_ENDIANNESS$$ 6023 */ 6024struct ustorm_per_queue_stats 6025{ 6026 struct regpair ucast_no_buff_bytes /* the number of unicast bytes received from network dropped because of no buffer at host */; 6027 struct regpair mcast_no_buff_bytes /* the number of multicast bytes received from network dropped because of no buffer at host */; 6028 struct regpair bcast_no_buff_bytes /* the number of broadcast bytes received from network dropped because of no buffer at host */; 6029 uint32_t ucast_no_buff_pkts /* the number of unicast frames received from network dropped because of no buffer at host */; 6030 uint32_t mcast_no_buff_pkts /* the number of unicast frames received from network dropped because of no buffer at host */; 6031 uint32_t bcast_no_buff_pkts /* the number of unicast frames received from network dropped because of no buffer at host */; 6032 uint32_t coalesced_pkts /* the number of packets coalesced in all aggregations */; 6033 struct regpair coalesced_bytes /* the number of bytes coalesced in all aggregations */; 6034 uint32_t coalesced_events /* the number of aggregations */; 6035 uint32_t coalesced_aborts /* the number of exception which avoid aggregation */; 6036}; 6037 6038/* 6039 * Protocol-common statistics collected by the Xstorm (per client) $$KEEP_ENDIANNESS$$ 6040 */ 6041struct xstorm_per_queue_stats 6042{ 6043 struct regpair ucast_bytes_sent /* number of total bytes sent without errors */; 6044 struct regpair mcast_bytes_sent /* number of total bytes sent without errors */; 6045 struct regpair bcast_bytes_sent /* number of total bytes sent without errors */; 6046 uint32_t ucast_pkts_sent /* number of total packets sent without errors */; 6047 uint32_t mcast_pkts_sent /* number of total packets sent without errors */; 6048 uint32_t bcast_pkts_sent /* number of total packets sent without errors */; 6049 uint32_t error_drop_pkts /* number of total packets drooped due to errors */; 6050}; 6051 6052/* 6053 * $$KEEP_ENDIANNESS$$ 6054 */ 6055struct per_queue_stats 6056{ 6057 struct tstorm_per_queue_stats tstorm_queue_statistics; 6058 struct ustorm_per_queue_stats ustorm_queue_statistics; 6059 struct xstorm_per_queue_stats xstorm_queue_statistics; 6060}; 6061 6062 6063/* 6064 * FW version stored in first line of pram $$KEEP_ENDIANNESS$$ 6065 */ 6066struct pram_fw_version 6067{ 6068 uint8_t major /* firmware current major version */; 6069 uint8_t minor /* firmware current minor version */; 6070 uint8_t revision /* firmware current revision version */; 6071 uint8_t engineering /* firmware current engineering version */; 6072 uint8_t flags; 6073#define PRAM_FW_VERSION_OPTIMIZED (0x1<<0) /* BitField flags if set, this is optimized ASM */ 6074#define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0 6075#define PRAM_FW_VERSION_STORM_ID (0x3<<1) /* BitField flags storm_id identification */ 6076#define PRAM_FW_VERSION_STORM_ID_SHIFT 1 6077#define PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3) /* BitField flags if set, this is big-endien ASM */ 6078#define PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 3 6079#define PRAM_FW_VERSION_CHIP_VERSION (0x3<<4) /* BitField flags 0 - E1, 1 - E1H */ 6080#define PRAM_FW_VERSION_CHIP_VERSION_SHIFT 4 6081#define __PRAM_FW_VERSION_RESERVED0 (0x3<<6) /* BitField flags */ 6082#define __PRAM_FW_VERSION_RESERVED0_SHIFT 6 6083}; 6084 6085 6086/* 6087 * Ethernet slow path element 6088 */ 6089union protocol_common_specific_data 6090{ 6091 uint8_t protocol_data[8] /* to fix this structure size to 8 bytes */; 6092 struct regpair phy_address /* SPE physical address */; 6093 struct regpair mac_config_addr /* physical address of the MAC configuration command, as allocated by the driver */; 6094 struct afex_vif_list_ramrod_data afex_vif_list_data /* The data afex vif list ramrod need */; 6095}; 6096 6097/* 6098 * The send queue element 6099 */ 6100struct protocol_common_spe 6101{ 6102 struct spe_hdr hdr /* SPE header */; 6103 union protocol_common_specific_data data /* data specific to common protocol */; 6104}; 6105 6106 6107/* 6108 * The data for the Set Timesync Ramrod $$KEEP_ENDIANNESS$$ 6109 */ 6110struct set_timesync_ramrod_data 6111{ 6112 uint8_t drift_adjust_cmd /* Timesync Drift Adjust Command */; 6113 uint8_t offset_cmd /* Timesync Offset Command */; 6114 uint8_t add_sub_drift_adjust_value /* Whether to add(1)/subtract(0) Drift Adjust Value from the Offset */; 6115 uint8_t drift_adjust_value /* Drift Adjust Value (in ns) */; 6116 uint32_t drift_adjust_period /* Drift Adjust Period (in us) */; 6117 struct regpair offset_delta /* Timesync Offset Delta (in ns) */; 6118}; 6119 6120 6121/* 6122 * The send queue element 6123 */ 6124struct slow_path_element 6125{ 6126 struct spe_hdr hdr /* common data for all protocols */; 6127 struct regpair protocol_data /* additional data specific to the protocol */; 6128}; 6129 6130 6131/* 6132 * Protocol-common statistics counter $$KEEP_ENDIANNESS$$ 6133 */ 6134struct stats_counter 6135{ 6136 uint16_t xstats_counter /* xstorm statistics counter */; 6137 uint16_t reserved0; 6138 uint32_t reserved1; 6139 uint16_t tstats_counter /* tstorm statistics counter */; 6140 uint16_t reserved2; 6141 uint32_t reserved3; 6142 uint16_t ustats_counter /* ustorm statistics counter */; 6143 uint16_t reserved4; 6144 uint32_t reserved5; 6145 uint16_t cstats_counter /* ustorm statistics counter */; 6146 uint16_t reserved6; 6147 uint32_t reserved7; 6148}; 6149 6150 6151/* 6152 * $$KEEP_ENDIANNESS$$ 6153 */ 6154struct stats_query_entry 6155{ 6156 uint8_t kind; 6157 uint8_t index /* queue index */; 6158 uint16_t funcID /* the func the statistic will send to */; 6159 uint32_t reserved; 6160 struct regpair address /* pxp address */; 6161}; 6162 6163/* 6164 * statistic command $$KEEP_ENDIANNESS$$ 6165 */ 6166struct stats_query_cmd_group 6167{ 6168 struct stats_query_entry query[STATS_QUERY_CMD_COUNT]; 6169}; 6170 6171 6172/* 6173 * statistic command header $$KEEP_ENDIANNESS$$ 6174 */ 6175struct stats_query_header 6176{ 6177 uint8_t cmd_num /* command number */; 6178 uint8_t reserved0; 6179 uint16_t drv_stats_counter; 6180 uint32_t reserved1; 6181 struct regpair stats_counters_addrs /* stats counter */; 6182}; 6183 6184 6185/* 6186 * Types of statistcis query entry 6187 */ 6188enum stats_query_type 6189{ 6190 STATS_TYPE_QUEUE, 6191 STATS_TYPE_PORT, 6192 STATS_TYPE_PF, 6193 STATS_TYPE_TOE, 6194 STATS_TYPE_FCOE, 6195 MAX_STATS_QUERY_TYPE}; 6196 6197 6198/* 6199 * Indicate of the function status block state 6200 */ 6201enum status_block_state 6202{ 6203 SB_DISABLED, 6204 SB_ENABLED, 6205 SB_CLEANED, 6206 MAX_STATUS_BLOCK_STATE}; 6207 6208 6209/* 6210 * Storm IDs (including attentions for IGU related enums) 6211 */ 6212enum storm_id 6213{ 6214 USTORM_ID, 6215 CSTORM_ID, 6216 XSTORM_ID, 6217 TSTORM_ID, 6218 ATTENTION_ID, 6219 MAX_STORM_ID}; 6220 6221 6222/* 6223 * Taffic types used in ETS and flow control algorithms 6224 */ 6225enum traffic_type 6226{ 6227 LLFC_TRAFFIC_TYPE_NW /* Networking */, 6228 LLFC_TRAFFIC_TYPE_FCOE /* FCoE */, 6229 LLFC_TRAFFIC_TYPE_ISCSI /* iSCSI */, 6230 MAX_TRAFFIC_TYPE}; 6231 6232 6233/* 6234 * zone A per-queue data 6235 */ 6236struct tstorm_queue_zone_data 6237{ 6238 struct regpair reserved[4]; 6239}; 6240 6241 6242/* 6243 * zone B per-VF data 6244 */ 6245struct tstorm_vf_zone_data 6246{ 6247 struct regpair reserved; 6248}; 6249 6250 6251/* 6252 * Add or Subtract Value for Set Timesync Ramrod 6253 */ 6254enum ts_add_sub_value 6255{ 6256 TS_SUB_VALUE /* Subtract Value */, 6257 TS_ADD_VALUE /* Add Value */, 6258 MAX_TS_ADD_SUB_VALUE}; 6259 6260 6261/* 6262 * Drift-Adjust Commands for Set Timesync Ramrod 6263 */ 6264enum ts_drift_adjust_cmd 6265{ 6266 TS_DRIFT_ADJUST_KEEP /* Keep Drift-Adjust at current values */, 6267 TS_DRIFT_ADJUST_SET /* Set Drift-Adjust */, 6268 TS_DRIFT_ADJUST_RESET /* Reset Drift-Adjust */, 6269 MAX_TS_DRIFT_ADJUST_CMD}; 6270 6271 6272/* 6273 * Offset Commands for Set Timesync Ramrod 6274 */ 6275enum ts_offset_cmd 6276{ 6277 TS_OFFSET_KEEP /* Keep Offset at current values */, 6278 TS_OFFSET_INC /* Increase Offset by Offset Delta */, 6279 TS_OFFSET_DEC /* Decrease Offset by Offset Delta */, 6280 MAX_TS_OFFSET_CMD}; 6281 6282 6283/* 6284 * zone A per-queue data 6285 */ 6286struct ustorm_queue_zone_data 6287{ 6288 struct ustorm_eth_rx_producers eth_rx_producers /* ETH RX rings producers */; 6289 struct regpair reserved[3]; 6290}; 6291 6292 6293/* 6294 * zone B per-VF data 6295 */ 6296struct ustorm_vf_zone_data 6297{ 6298 struct regpair reserved; 6299}; 6300 6301 6302/* 6303 * data per VF-PF channel 6304 */ 6305struct vf_pf_channel_data 6306{ 6307#if defined(__BIG_ENDIAN) 6308 uint16_t reserved0; 6309 uint8_t valid /* flag for channel validity. (cleared when identify a VF as malicious) */; 6310 uint8_t state /* channel state (ready / waiting for ack) */; 6311#elif defined(__LITTLE_ENDIAN) 6312 uint8_t state /* channel state (ready / waiting for ack) */; 6313 uint8_t valid /* flag for channel validity. (cleared when identify a VF as malicious) */; 6314 uint16_t reserved0; 6315#endif 6316 uint32_t reserved1; 6317}; 6318 6319 6320/* 6321 * State of VF-PF channel 6322 */ 6323enum vf_pf_channel_state 6324{ 6325 VF_PF_CHANNEL_STATE_READY /* Channel is ready to accept a message from VF */, 6326 VF_PF_CHANNEL_STATE_WAITING_FOR_ACK /* Channel waits for an ACK from PF */, 6327 MAX_VF_PF_CHANNEL_STATE}; 6328 6329 6330/* 6331 * vif_list_rule_kind 6332 */ 6333enum vif_list_rule_kind 6334{ 6335 VIF_LIST_RULE_SET, 6336 VIF_LIST_RULE_GET, 6337 VIF_LIST_RULE_CLEAR_ALL, 6338 VIF_LIST_RULE_CLEAR_FUNC, 6339 MAX_VIF_LIST_RULE_KIND}; 6340 6341 6342/* 6343 * zone A per-queue data 6344 */ 6345struct xstorm_queue_zone_data 6346{ 6347 struct regpair reserved[4]; 6348}; 6349 6350 6351/* 6352 * zone B per-VF data 6353 */ 6354struct xstorm_vf_zone_data 6355{ 6356 struct regpair reserved; 6357}; 6358 6359 6360#endif /* ECORE_HSI_H */ 6361 6362