ecore_fw_defs.h revision 255736
1/*- 2 * Copyright (c) 2007-2013 Broadcom Corporation. All rights reserved. 3 * 4 * Eric Davis <edavis@broadcom.com> 5 * David Christensen <davidch@broadcom.com> 6 * Gary Zambrano <zambrano@broadcom.com> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. Neither the name of Broadcom Corporation nor the name of its contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written consent. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34#include <sys/cdefs.h> 35__FBSDID("$FreeBSD: head/sys/dev/bxe/ecore_fw_defs.h 255736 2013-09-20 20:18:49Z davidch $"); 36 37#ifndef ECORE_FW_DEFS_H 38#define ECORE_FW_DEFS_H 39 40 41#define CSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[148].base) 42#define CSTORM_ASSERT_LIST_OFFSET(assertListEntry) \ 43 (IRO[147].base + ((assertListEntry) * IRO[147].m1)) 44#define CSTORM_EVENT_RING_DATA_OFFSET(pfId) \ 45 (IRO[153].base + (((pfId)>>1) * IRO[153].m1) + (((pfId)&1) * \ 46 IRO[153].m2)) 47#define CSTORM_EVENT_RING_PROD_OFFSET(pfId) \ 48 (IRO[154].base + (((pfId)>>1) * IRO[154].m1) + (((pfId)&1) * \ 49 IRO[154].m2)) 50#define CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(funcId) \ 51 (IRO[159].base + ((funcId) * IRO[159].m1)) 52#define CSTORM_FUNC_EN_OFFSET(funcId) \ 53 (IRO[149].base + ((funcId) * IRO[149].m1)) 54#define CSTORM_HC_SYNC_LINE_INDEX_E1X_OFFSET(hcIndex, sbId) \ 55 (IRO[139].base + ((hcIndex) * IRO[139].m1) + ((sbId) * IRO[139].m2)) 56#define CSTORM_HC_SYNC_LINE_INDEX_E2_OFFSET(hcIndex, sbId) \ 57 (IRO[138].base + (((hcIndex)>>2) * IRO[138].m1) + (((hcIndex)&3) \ 58 * IRO[138].m2) + ((sbId) * IRO[138].m3)) 59#define CSTORM_IGU_MODE_OFFSET (IRO[157].base) 60#define CSTORM_ISCSI_CQ_SIZE_OFFSET(pfId) \ 61 (IRO[317].base + ((pfId) * IRO[317].m1)) 62#define CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfId) \ 63 (IRO[318].base + ((pfId) * IRO[318].m1)) 64#define CSTORM_ISCSI_EQ_CONS_OFFSET(pfId, iscsiEqId) \ 65 (IRO[310].base + ((pfId) * IRO[310].m1) + ((iscsiEqId) * IRO[310].m2)) 66#define CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfId, iscsiEqId) \ 67 (IRO[312].base + ((pfId) * IRO[312].m1) + ((iscsiEqId) * IRO[312].m2)) 68#define CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfId, iscsiEqId) \ 69 (IRO[311].base + ((pfId) * IRO[311].m1) + ((iscsiEqId) * IRO[311].m2)) 70#define CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(pfId, iscsiEqId) \ 71 (IRO[313].base + ((pfId) * IRO[313].m1) + ((iscsiEqId) * IRO[313].m2)) 72#define CSTORM_ISCSI_EQ_PROD_OFFSET(pfId, iscsiEqId) \ 73 (IRO[309].base + ((pfId) * IRO[309].m1) + ((iscsiEqId) * IRO[309].m2)) 74#define CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(pfId, iscsiEqId) \ 75 (IRO[315].base + ((pfId) * IRO[315].m1) + ((iscsiEqId) * IRO[315].m2)) 76#define CSTORM_ISCSI_EQ_SB_NUM_OFFSET(pfId, iscsiEqId) \ 77 (IRO[314].base + ((pfId) * IRO[314].m1) + ((iscsiEqId) * IRO[314].m2)) 78#define CSTORM_ISCSI_HQ_SIZE_OFFSET(pfId) \ 79 (IRO[316].base + ((pfId) * IRO[316].m1)) 80#define CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \ 81 (IRO[308].base + ((pfId) * IRO[308].m1)) 82#define CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \ 83 (IRO[307].base + ((pfId) * IRO[307].m1)) 84#define CSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \ 85 (IRO[306].base + ((pfId) * IRO[306].m1)) 86#define CSTORM_RECORD_SLOW_PATH_OFFSET(funcId) \ 87 (IRO[151].base + ((funcId) * IRO[151].m1)) 88#define CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(pfId) \ 89 (IRO[142].base + ((pfId) * IRO[142].m1)) 90#define CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(pfId) \ 91 (IRO[143].base + ((pfId) * IRO[143].m1)) 92#define CSTORM_SP_STATUS_BLOCK_OFFSET(pfId) \ 93 (IRO[141].base + ((pfId) * IRO[141].m1)) 94#define CSTORM_SP_STATUS_BLOCK_SIZE (IRO[141].size) 95#define CSTORM_SP_SYNC_BLOCK_OFFSET(pfId) \ 96 (IRO[144].base + ((pfId) * IRO[144].m1)) 97#define CSTORM_SP_SYNC_BLOCK_SIZE (IRO[144].size) 98#define CSTORM_STATUS_BLOCK_DATA_FLAGS_OFFSET(sbId, hcIndex) \ 99 (IRO[136].base + ((sbId) * IRO[136].m1) + ((hcIndex) * IRO[136].m2)) 100#define CSTORM_STATUS_BLOCK_DATA_OFFSET(sbId) \ 101 (IRO[133].base + ((sbId) * IRO[133].m1)) 102#define CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(sbId) \ 103 (IRO[134].base + ((sbId) * IRO[134].m1)) 104#define CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(sbId, hcIndex) \ 105 (IRO[135].base + ((sbId) * IRO[135].m1) + ((hcIndex) * IRO[135].m2)) 106#define CSTORM_STATUS_BLOCK_OFFSET(sbId) \ 107 (IRO[132].base + ((sbId) * IRO[132].m1)) 108#define CSTORM_STATUS_BLOCK_SIZE (IRO[132].size) 109#define CSTORM_SYNC_BLOCK_OFFSET(sbId) \ 110 (IRO[137].base + ((sbId) * IRO[137].m1)) 111#define CSTORM_SYNC_BLOCK_SIZE (IRO[137].size) 112#define CSTORM_VF_TO_PF_OFFSET(funcId) \ 113 (IRO[150].base + ((funcId) * IRO[150].m1)) 114#define TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET (IRO[204].base) 115#define TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(pfId) \ 116 (IRO[203].base + ((pfId) * IRO[203].m1)) 117#define TSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[102].base) 118#define TSTORM_ASSERT_LIST_OFFSET(assertListEntry) \ 119 (IRO[101].base + ((assertListEntry) * IRO[101].m1)) 120#define TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(pfId) \ 121 (IRO[201].base + ((pfId) * IRO[201].m1)) 122#define TSTORM_FUNC_EN_OFFSET(funcId) \ 123 (IRO[103].base + ((funcId) * IRO[103].m1)) 124#define TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfId) \ 125 (IRO[272].base + ((pfId) * IRO[272].m1)) 126#define TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \ 127 (IRO[271].base + ((pfId) * IRO[271].m1)) 128#define TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \ 129 (IRO[270].base + ((pfId) * IRO[270].m1)) 130#define TSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \ 131 (IRO[269].base + ((pfId) * IRO[269].m1)) 132#define TSTORM_ISCSI_RQ_SIZE_OFFSET(pfId) \ 133 (IRO[268].base + ((pfId) * IRO[268].m1)) 134#define TSTORM_ISCSI_TCP_LOCAL_ADV_WND_OFFSET(pfId) \ 135 (IRO[278].base + ((pfId) * IRO[278].m1)) 136#define TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(pfId) \ 137 (IRO[264].base + ((pfId) * IRO[264].m1)) 138#define TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfId) \ 139 (IRO[265].base + ((pfId) * IRO[265].m1)) 140#define TSTORM_ISCSI_TCP_VARS_MID_LOCAL_MAC_ADDR_OFFSET(pfId) \ 141 (IRO[266].base + ((pfId) * IRO[266].m1)) 142#define TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfId) \ 143 (IRO[267].base + ((pfId) * IRO[267].m1)) 144#define TSTORM_MAC_FILTER_CONFIG_OFFSET(pfId) \ 145 (IRO[202].base + ((pfId) * IRO[202].m1)) 146#define TSTORM_RECORD_SLOW_PATH_OFFSET(funcId) \ 147 (IRO[105].base + ((funcId) * IRO[105].m1)) 148#define TSTORM_TCP_MAX_CWND_OFFSET(pfId) \ 149 (IRO[217].base + ((pfId) * IRO[217].m1)) 150#define TSTORM_VF_TO_PF_OFFSET(funcId) \ 151 (IRO[104].base + ((funcId) * IRO[104].m1)) 152#define USTORM_AGG_DATA_OFFSET (IRO[206].base) 153#define USTORM_AGG_DATA_SIZE (IRO[206].size) 154#define USTORM_ASSERT_LIST_INDEX_OFFSET (IRO[177].base) 155#define USTORM_ASSERT_LIST_OFFSET(assertListEntry) \ 156 (IRO[176].base + ((assertListEntry) * IRO[176].m1)) 157#define USTORM_ETH_PAUSE_ENABLED_OFFSET(portId) \ 158 (IRO[183].base + ((portId) * IRO[183].m1)) 159#define USTORM_FCOE_EQ_PROD_OFFSET(pfId) \ 160 (IRO[319].base + ((pfId) * IRO[319].m1)) 161#define USTORM_FUNC_EN_OFFSET(funcId) \ 162 (IRO[178].base + ((funcId) * IRO[178].m1)) 163#define USTORM_ISCSI_CQ_SIZE_OFFSET(pfId) \ 164 (IRO[283].base + ((pfId) * IRO[283].m1)) 165#define USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfId) \ 166 (IRO[284].base + ((pfId) * IRO[284].m1)) 167#define USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfId) \ 168 (IRO[288].base + ((pfId) * IRO[288].m1)) 169#define USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfId) \ 170 (IRO[285].base + ((pfId) * IRO[285].m1)) 171#define USTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \ 172 (IRO[281].base + ((pfId) * IRO[281].m1)) 173#define USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \ 174 (IRO[280].base + ((pfId) * IRO[280].m1)) 175#define USTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \ 176 (IRO[279].base + ((pfId) * IRO[279].m1)) 177#define USTORM_ISCSI_R2TQ_SIZE_OFFSET(pfId) \ 178 (IRO[282].base + ((pfId) * IRO[282].m1)) 179#define USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(pfId) \ 180 (IRO[286].base + ((pfId) * IRO[286].m1)) 181#define USTORM_ISCSI_RQ_SIZE_OFFSET(pfId) \ 182 (IRO[287].base + ((pfId) * IRO[287].m1)) 183#define USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(pfId) \ 184 (IRO[182].base + ((pfId) * IRO[182].m1)) 185#define USTORM_RECORD_SLOW_PATH_OFFSET(funcId) \ 186 (IRO[180].base + ((funcId) * IRO[180].m1)) 187#define USTORM_RX_PRODS_E1X_OFFSET(portId, clientId) \ 188 (IRO[209].base + ((portId) * IRO[209].m1) + ((clientId) * \ 189 IRO[209].m2)) 190#define USTORM_RX_PRODS_E2_OFFSET(qzoneId) \ 191 (IRO[210].base + ((qzoneId) * IRO[210].m1)) 192#define USTORM_TPA_BTR_OFFSET (IRO[207].base) 193#define USTORM_TPA_BTR_SIZE (IRO[207].size) 194#define USTORM_VF_TO_PF_OFFSET(funcId) \ 195 (IRO[179].base + ((funcId) * IRO[179].m1)) 196#define XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE (IRO[67].base) 197#define XSTORM_AGG_INT_FINAL_CLEANUP_INDEX (IRO[66].base) 198#define XSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[51].base) 199#define XSTORM_ASSERT_LIST_OFFSET(assertListEntry) \ 200 (IRO[50].base + ((assertListEntry) * IRO[50].m1)) 201#define XSTORM_CMNG_PER_PORT_VARS_OFFSET(portId) \ 202 (IRO[43].base + ((portId) * IRO[43].m1)) 203#define XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(pfId) \ 204 (IRO[45].base + ((pfId) * IRO[45].m1)) 205#define XSTORM_FUNC_EN_OFFSET(funcId) \ 206 (IRO[47].base + ((funcId) * IRO[47].m1)) 207#define XSTORM_ISCSI_HQ_SIZE_OFFSET(pfId) \ 208 (IRO[296].base + ((pfId) * IRO[296].m1)) 209#define XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(pfId) \ 210 (IRO[299].base + ((pfId) * IRO[299].m1)) 211#define XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(pfId) \ 212 (IRO[300].base + ((pfId) * IRO[300].m1)) 213#define XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(pfId) \ 214 (IRO[301].base + ((pfId) * IRO[301].m1)) 215#define XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(pfId) \ 216 (IRO[302].base + ((pfId) * IRO[302].m1)) 217#define XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(pfId) \ 218 (IRO[303].base + ((pfId) * IRO[303].m1)) 219#define XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(pfId) \ 220 (IRO[304].base + ((pfId) * IRO[304].m1)) 221#define XSTORM_ISCSI_LOCAL_VLAN_OFFSET(pfId) \ 222 (IRO[305].base + ((pfId) * IRO[305].m1)) 223#define XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \ 224 (IRO[295].base + ((pfId) * IRO[295].m1)) 225#define XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \ 226 (IRO[294].base + ((pfId) * IRO[294].m1)) 227#define XSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \ 228 (IRO[293].base + ((pfId) * IRO[293].m1)) 229#define XSTORM_ISCSI_R2TQ_SIZE_OFFSET(pfId) \ 230 (IRO[298].base + ((pfId) * IRO[298].m1)) 231#define XSTORM_ISCSI_SQ_SIZE_OFFSET(pfId) \ 232 (IRO[297].base + ((pfId) * IRO[297].m1)) 233#define XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(pfId) \ 234 (IRO[292].base + ((pfId) * IRO[292].m1)) 235#define XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(pfId) \ 236 (IRO[291].base + ((pfId) * IRO[291].m1)) 237#define XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(pfId) \ 238 (IRO[290].base + ((pfId) * IRO[290].m1)) 239#define XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(pfId) \ 240 (IRO[289].base + ((pfId) * IRO[289].m1)) 241#define XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(pfId) \ 242 (IRO[44].base + ((pfId) * IRO[44].m1)) 243#define XSTORM_RECORD_SLOW_PATH_OFFSET(funcId) \ 244 (IRO[49].base + ((funcId) * IRO[49].m1)) 245#define XSTORM_SPQ_DATA_OFFSET(funcId) \ 246 (IRO[32].base + ((funcId) * IRO[32].m1)) 247#define XSTORM_SPQ_DATA_SIZE (IRO[32].size) 248#define XSTORM_SPQ_PAGE_BASE_OFFSET(funcId) \ 249 (IRO[30].base + ((funcId) * IRO[30].m1)) 250#define XSTORM_SPQ_PROD_OFFSET(funcId) \ 251 (IRO[31].base + ((funcId) * IRO[31].m1)) 252#define XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(portId) \ 253 (IRO[211].base + ((portId) * IRO[211].m1)) 254#define XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(portId) \ 255 (IRO[212].base + ((portId) * IRO[212].m1)) 256#define XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(pfId) \ 257 (IRO[214].base + (((pfId)>>1) * IRO[214].m1) + (((pfId)&1) * \ 258 IRO[214].m2)) 259#define XSTORM_VF_TO_PF_OFFSET(funcId) \ 260 (IRO[48].base + ((funcId) * IRO[48].m1)) 261#define COMMON_ASM_INVALID_ASSERT_OPCODE (IRO[7].base) 262 263 264/* Ethernet Ring parameters */ 265#define X_ETH_LOCAL_RING_SIZE 13 266#define FIRST_BD_IN_PKT 0 267#define PARSE_BD_INDEX 1 268#define NUM_OF_ETH_BDS_IN_PAGE ((PAGE_SIZE)/(STRUCT_SIZE(eth_tx_bd)/8)) 269#define U_ETH_NUM_OF_SGES_TO_FETCH 8 270#define U_ETH_MAX_SGES_FOR_PACKET 3 271 272/* Rx ring params */ 273#define U_ETH_LOCAL_BD_RING_SIZE 8 274#define U_ETH_LOCAL_SGE_RING_SIZE 10 275#define U_ETH_SGL_SIZE 8 276 /* The fw will padd the buffer with this value, so the IP header \ 277 will be align to 4 Byte */ 278#define IP_HEADER_ALIGNMENT_PADDING 2 279 280#define U_ETH_SGES_PER_PAGE_INVERSE_MASK \ 281 (0xFFFF - ((PAGE_SIZE/((STRUCT_SIZE(eth_rx_sge))/8))-1)) 282 283#define TU_ETH_CQES_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_cqe)/8)) 284#define U_ETH_BDS_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_bd)/8)) 285#define U_ETH_SGES_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_sge)/8)) 286 287#define U_ETH_BDS_PER_PAGE_MASK (U_ETH_BDS_PER_PAGE-1) 288#define U_ETH_CQE_PER_PAGE_MASK (TU_ETH_CQES_PER_PAGE-1) 289#define U_ETH_SGES_PER_PAGE_MASK (U_ETH_SGES_PER_PAGE-1) 290 291#define U_ETH_UNDEFINED_Q 0xFF 292 293#define T_ETH_INDIRECTION_TABLE_SIZE 128 294#define T_ETH_RSS_KEY 10 295#define ETH_NUM_OF_RSS_ENGINES_E2 72 296 297#define FILTER_RULES_COUNT 16 298#define MULTICAST_RULES_COUNT 16 299#define CLASSIFY_RULES_COUNT 16 300 301/*The CRC32 seed, that is used for the hash(reduction) multicast address */ 302#define ETH_CRC32_HASH_SEED 0x00000000 303 304#define ETH_CRC32_HASH_BIT_SIZE (8) 305#define ETH_CRC32_HASH_MASK EVAL((1<<ETH_CRC32_HASH_BIT_SIZE)-1) 306 307/* Maximal L2 clients supported */ 308#define ETH_MAX_RX_CLIENTS_E1 18 309#define ETH_MAX_RX_CLIENTS_E1H 28 310#define ETH_MAX_RX_CLIENTS_E2 152 311 312/* Maximal statistics client Ids */ 313#define MAX_STAT_COUNTER_ID_E1 36 314#define MAX_STAT_COUNTER_ID_E1H 56 315#define MAX_STAT_COUNTER_ID_E2 140 316 317#define MAX_MAC_CREDIT_E1 192 /* Per Chip */ 318#define MAX_MAC_CREDIT_E1H 256 /* Per Chip */ 319#define MAX_MAC_CREDIT_E2 272 /* Per Path */ 320#define MAX_VLAN_CREDIT_E1 0 /* Per Chip */ 321#define MAX_VLAN_CREDIT_E1H 0 /* Per Chip */ 322#define MAX_VLAN_CREDIT_E2 272 /* Per Path */ 323 324 325/* Maximal aggregation queues supported */ 326#define ETH_MAX_AGGREGATION_QUEUES_E1 32 327#define ETH_MAX_AGGREGATION_QUEUES_E1H_E2 64 328 329 330#define ETH_NUM_OF_MCAST_BINS 256 331#define ETH_NUM_OF_MCAST_ENGINES_E2 72 332 333#define ETH_MIN_RX_CQES_WITHOUT_TPA (MAX_RAMRODS_PER_PORT + 3) 334#define ETH_MIN_RX_CQES_WITH_TPA_E1 \ 335 (ETH_MAX_AGGREGATION_QUEUES_E1 + ETH_MIN_RX_CQES_WITHOUT_TPA) 336#define ETH_MIN_RX_CQES_WITH_TPA_E1H_E2 \ 337 (ETH_MAX_AGGREGATION_QUEUES_E1H_E2 + ETH_MIN_RX_CQES_WITHOUT_TPA) 338 339#define DISABLE_STATISTIC_COUNTER_ID_VALUE 0 340 341 342/* This file defines HSI constants common to all microcode flows */ 343 344/* offset in bits of protocol in the state context parameter */ 345#define PROTOCOL_STATE_BIT_OFFSET 6 346 347#define ETH_STATE (ETH_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET) 348#define TOE_STATE (TOE_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET) 349#define RDMA_STATE (RDMA_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET) 350 351/* microcode fixed page page size 4K (chains and ring segments) */ 352#define MC_PAGE_SIZE 4096 353 354/* Number of indices per slow-path SB */ 355#define HC_SP_SB_MAX_INDICES 16 /* The Maximum of all */ 356 357/* Number of indices per SB */ 358#define HC_SB_MAX_INDICES_E1X 8 /* Multiple of 4 */ 359#define HC_SB_MAX_INDICES_E2 8 /* Multiple of 4 */ 360 361/* Number of SB */ 362#define HC_SB_MAX_SB_E1X 32 363#define HC_SB_MAX_SB_E2 136 /* include PF */ 364 365/* ID of slow path status block */ 366#define HC_SP_SB_ID 0xde 367 368/* Num of State machines */ 369#define HC_SB_MAX_SM 2 /* Fixed */ 370 371/* Num of dynamic indices */ 372#define HC_SB_MAX_DYNAMIC_INDICES 4 /* 0..3 fixed */ 373 374/* max number of slow path commands per port */ 375#define MAX_RAMRODS_PER_PORT 8 376 377 378/**** DEFINES FOR TIMERS/CLOCKS RESOLUTIONS ****/ 379 380/* chip timers frequency constants */ 381#define TIMERS_TICK_SIZE_CHIP (1e-3) 382 383/* used in toe: TsRecentAge, MaxRt, and temporarily RTT */ 384#define TSEMI_CLK1_RESUL_CHIP (1e-3) 385 386/* temporarily used for RTT */ 387#define XSEMI_CLK1_RESUL_CHIP (1e-3) 388 389/* used for Host Coallescing */ 390#define SDM_TIMER_TICK_RESUL_CHIP (4 * (1e-6)) 391 392/**** END DEFINES FOR TIMERS/CLOCKS RESOLUTIONS ****/ 393 394#define XSTORM_IP_ID_ROLL_HALF 0x8000 395#define XSTORM_IP_ID_ROLL_ALL 0 396 397/* assert list: number of entries */ 398#define FW_LOG_LIST_SIZE 50 399 400#define NUM_OF_SAFC_BITS 16 401#define MAX_COS_NUMBER 4 402#define MAX_TRAFFIC_TYPES 8 403#define MAX_PFC_PRIORITIES 8 404 405 /* used by array traffic_type_to_priority[] to mark traffic type \ 406 that is not mapped to priority*/ 407#define LLFC_TRAFFIC_TYPE_TO_PRIORITY_UNMAPPED 0xFF 408 409/* Event Ring definitions */ 410#define C_ERES_PER_PAGE \ 411 (PAGE_SIZE / BITS_TO_BYTES(STRUCT_SIZE(event_ring_elem))) 412#define C_ERE_PER_PAGE_MASK (C_ERES_PER_PAGE - 1) 413 414/* number of statistic command */ 415#define STATS_QUERY_CMD_COUNT 16 416 417/* niv list table size */ 418#define AFEX_LIST_TABLE_SIZE 4096 419 420/* invalid VNIC Id. used in VNIC classification */ 421#define INVALID_VNIC_ID 0xFF 422 423/* used for indicating an undefined RAM offset in the IRO arrays */ 424#define UNDEF_IRO 0x80000000 425 426/* used for defining the amount of FCoE tasks supported for PF */ 427#define MAX_FCOE_FUNCS_PER_ENGINE 2 428#define MAX_NUM_FCOE_TASKS_PER_ENGINE \ 429 4096 /*Each port can have at max 1 function*/ 430 431 432#endif /* ECORE_FW_DEFS_H */ 433 434