bxe.c revision 289199
1/*-
2 * Copyright (c) 2007-2014 QLogic Corporation. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
18 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
19 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
20 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
21 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
22 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
23 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
24 * THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
28__FBSDID("$FreeBSD: head/sys/dev/bxe/bxe.c 289199 2015-10-12 20:21:17Z davidcs $");
29
30#define BXE_DRIVER_VERSION "1.78.79"
31
32#include "bxe.h"
33#include "ecore_sp.h"
34#include "ecore_init.h"
35#include "ecore_init_ops.h"
36
37#include "57710_int_offsets.h"
38#include "57711_int_offsets.h"
39#include "57712_int_offsets.h"
40
41/*
42 * CTLTYPE_U64 and sysctl_handle_64 were added in r217616. Define these
43 * explicitly here for older kernels that don't include this changeset.
44 */
45#ifndef CTLTYPE_U64
46#define CTLTYPE_U64      CTLTYPE_QUAD
47#define sysctl_handle_64 sysctl_handle_quad
48#endif
49
50/*
51 * CSUM_TCP_IPV6 and CSUM_UDP_IPV6 were added in r236170. Define these
52 * here as zero(0) for older kernels that don't include this changeset
53 * thereby masking the functionality.
54 */
55#ifndef CSUM_TCP_IPV6
56#define CSUM_TCP_IPV6 0
57#define CSUM_UDP_IPV6 0
58#endif
59
60/*
61 * pci_find_cap was added in r219865. Re-define this at pci_find_extcap
62 * for older kernels that don't include this changeset.
63 */
64#if __FreeBSD_version < 900035
65#define pci_find_cap pci_find_extcap
66#endif
67
68#define BXE_DEF_SB_ATT_IDX 0x0001
69#define BXE_DEF_SB_IDX     0x0002
70
71/*
72 * FLR Support - bxe_pf_flr_clnup() is called during nic_load in the per
73 * function HW initialization.
74 */
75#define FLR_WAIT_USEC     10000 /* 10 msecs */
76#define FLR_WAIT_INTERVAL 50    /* usecs */
77#define FLR_POLL_CNT      (FLR_WAIT_USEC / FLR_WAIT_INTERVAL) /* 200 */
78
79struct pbf_pN_buf_regs {
80    int pN;
81    uint32_t init_crd;
82    uint32_t crd;
83    uint32_t crd_freed;
84};
85
86struct pbf_pN_cmd_regs {
87    int pN;
88    uint32_t lines_occup;
89    uint32_t lines_freed;
90};
91
92/*
93 * PCI Device ID Table used by bxe_probe().
94 */
95#define BXE_DEVDESC_MAX 64
96static struct bxe_device_type bxe_devs[] = {
97    {
98        BRCM_VENDORID,
99        CHIP_NUM_57710,
100        PCI_ANY_ID, PCI_ANY_ID,
101        "QLogic NetXtreme II BCM57710 10GbE"
102    },
103    {
104        BRCM_VENDORID,
105        CHIP_NUM_57711,
106        PCI_ANY_ID, PCI_ANY_ID,
107        "QLogic NetXtreme II BCM57711 10GbE"
108    },
109    {
110        BRCM_VENDORID,
111        CHIP_NUM_57711E,
112        PCI_ANY_ID, PCI_ANY_ID,
113        "QLogic NetXtreme II BCM57711E 10GbE"
114    },
115    {
116        BRCM_VENDORID,
117        CHIP_NUM_57712,
118        PCI_ANY_ID, PCI_ANY_ID,
119        "QLogic NetXtreme II BCM57712 10GbE"
120    },
121    {
122        BRCM_VENDORID,
123        CHIP_NUM_57712_MF,
124        PCI_ANY_ID, PCI_ANY_ID,
125        "QLogic NetXtreme II BCM57712 MF 10GbE"
126    },
127#if 0
128    {
129        BRCM_VENDORID,
130        CHIP_NUM_57712_VF,
131        PCI_ANY_ID, PCI_ANY_ID,
132        "QLogic NetXtreme II BCM57712 VF 10GbE"
133    },
134#endif
135    {
136        BRCM_VENDORID,
137        CHIP_NUM_57800,
138        PCI_ANY_ID, PCI_ANY_ID,
139        "QLogic NetXtreme II BCM57800 10GbE"
140    },
141    {
142        BRCM_VENDORID,
143        CHIP_NUM_57800_MF,
144        PCI_ANY_ID, PCI_ANY_ID,
145        "QLogic NetXtreme II BCM57800 MF 10GbE"
146    },
147#if 0
148    {
149        BRCM_VENDORID,
150        CHIP_NUM_57800_VF,
151        PCI_ANY_ID, PCI_ANY_ID,
152        "QLogic NetXtreme II BCM57800 VF 10GbE"
153    },
154#endif
155    {
156        BRCM_VENDORID,
157        CHIP_NUM_57810,
158        PCI_ANY_ID, PCI_ANY_ID,
159        "QLogic NetXtreme II BCM57810 10GbE"
160    },
161    {
162        BRCM_VENDORID,
163        CHIP_NUM_57810_MF,
164        PCI_ANY_ID, PCI_ANY_ID,
165        "QLogic NetXtreme II BCM57810 MF 10GbE"
166    },
167#if 0
168    {
169        BRCM_VENDORID,
170        CHIP_NUM_57810_VF,
171        PCI_ANY_ID, PCI_ANY_ID,
172        "QLogic NetXtreme II BCM57810 VF 10GbE"
173    },
174#endif
175    {
176        BRCM_VENDORID,
177        CHIP_NUM_57811,
178        PCI_ANY_ID, PCI_ANY_ID,
179        "QLogic NetXtreme II BCM57811 10GbE"
180    },
181    {
182        BRCM_VENDORID,
183        CHIP_NUM_57811_MF,
184        PCI_ANY_ID, PCI_ANY_ID,
185        "QLogic NetXtreme II BCM57811 MF 10GbE"
186    },
187#if 0
188    {
189        BRCM_VENDORID,
190        CHIP_NUM_57811_VF,
191        PCI_ANY_ID, PCI_ANY_ID,
192        "QLogic NetXtreme II BCM57811 VF 10GbE"
193    },
194#endif
195    {
196        BRCM_VENDORID,
197        CHIP_NUM_57840_4_10,
198        PCI_ANY_ID, PCI_ANY_ID,
199        "QLogic NetXtreme II BCM57840 4x10GbE"
200    },
201#if 0
202    {
203        BRCM_VENDORID,
204        CHIP_NUM_57840_2_20,
205        PCI_ANY_ID, PCI_ANY_ID,
206        "QLogic NetXtreme II BCM57840 2x20GbE"
207    },
208#endif
209    {
210        BRCM_VENDORID,
211        CHIP_NUM_57840_MF,
212        PCI_ANY_ID, PCI_ANY_ID,
213        "QLogic NetXtreme II BCM57840 MF 10GbE"
214    },
215#if 0
216    {
217        BRCM_VENDORID,
218        CHIP_NUM_57840_VF,
219        PCI_ANY_ID, PCI_ANY_ID,
220        "QLogic NetXtreme II BCM57840 VF 10GbE"
221    },
222#endif
223    {
224        0, 0, 0, 0, NULL
225    }
226};
227
228MALLOC_DECLARE(M_BXE_ILT);
229MALLOC_DEFINE(M_BXE_ILT, "bxe_ilt", "bxe ILT pointer");
230
231/*
232 * FreeBSD device entry points.
233 */
234static int bxe_probe(device_t);
235static int bxe_attach(device_t);
236static int bxe_detach(device_t);
237static int bxe_shutdown(device_t);
238
239/*
240 * FreeBSD KLD module/device interface event handler method.
241 */
242static device_method_t bxe_methods[] = {
243    /* Device interface (device_if.h) */
244    DEVMETHOD(device_probe,     bxe_probe),
245    DEVMETHOD(device_attach,    bxe_attach),
246    DEVMETHOD(device_detach,    bxe_detach),
247    DEVMETHOD(device_shutdown,  bxe_shutdown),
248#if 0
249    DEVMETHOD(device_suspend,   bxe_suspend),
250    DEVMETHOD(device_resume,    bxe_resume),
251#endif
252    /* Bus interface (bus_if.h) */
253    DEVMETHOD(bus_print_child,  bus_generic_print_child),
254    DEVMETHOD(bus_driver_added, bus_generic_driver_added),
255    KOBJMETHOD_END
256};
257
258/*
259 * FreeBSD KLD Module data declaration
260 */
261static driver_t bxe_driver = {
262    "bxe",                   /* module name */
263    bxe_methods,             /* event handler */
264    sizeof(struct bxe_softc) /* extra data */
265};
266
267/*
268 * FreeBSD dev class is needed to manage dev instances and
269 * to associate with a bus type
270 */
271static devclass_t bxe_devclass;
272
273MODULE_DEPEND(bxe, pci, 1, 1, 1);
274MODULE_DEPEND(bxe, ether, 1, 1, 1);
275DRIVER_MODULE(bxe, pci, bxe_driver, bxe_devclass, 0, 0);
276
277/* resources needed for unloading a previously loaded device */
278
279#define BXE_PREV_WAIT_NEEDED 1
280struct mtx bxe_prev_mtx;
281MTX_SYSINIT(bxe_prev_mtx, &bxe_prev_mtx, "bxe_prev_lock", MTX_DEF);
282struct bxe_prev_list_node {
283    LIST_ENTRY(bxe_prev_list_node) node;
284    uint8_t bus;
285    uint8_t slot;
286    uint8_t path;
287    uint8_t aer; /* XXX automatic error recovery */
288    uint8_t undi;
289};
290static LIST_HEAD(, bxe_prev_list_node) bxe_prev_list = LIST_HEAD_INITIALIZER(bxe_prev_list);
291
292static int load_count[2][3] = { {0} }; /* per-path: 0-common, 1-port0, 2-port1 */
293
294/* Tunable device values... */
295
296SYSCTL_NODE(_hw, OID_AUTO, bxe, CTLFLAG_RD, 0, "bxe driver parameters");
297
298/* Debug */
299unsigned long bxe_debug = 0;
300SYSCTL_ULONG(_hw_bxe, OID_AUTO, debug, CTLFLAG_RDTUN,
301             &bxe_debug, 0, "Debug logging mode");
302
303/* Interrupt Mode: 0 (IRQ), 1 (MSI/IRQ), and 2 (MSI-X/MSI/IRQ) */
304static int bxe_interrupt_mode = INTR_MODE_MSIX;
305SYSCTL_INT(_hw_bxe, OID_AUTO, interrupt_mode, CTLFLAG_RDTUN,
306           &bxe_interrupt_mode, 0, "Interrupt (MSI-X/MSI/INTx) mode");
307
308/* Number of Queues: 0 (Auto) or 1 to 16 (fixed queue number) */
309static int bxe_queue_count = 4;
310SYSCTL_INT(_hw_bxe, OID_AUTO, queue_count, CTLFLAG_RDTUN,
311           &bxe_queue_count, 0, "Multi-Queue queue count");
312
313/* max number of buffers per queue (default RX_BD_USABLE) */
314static int bxe_max_rx_bufs = 0;
315SYSCTL_INT(_hw_bxe, OID_AUTO, max_rx_bufs, CTLFLAG_RDTUN,
316           &bxe_max_rx_bufs, 0, "Maximum Number of Rx Buffers Per Queue");
317
318/* Host interrupt coalescing RX tick timer (usecs) */
319static int bxe_hc_rx_ticks = 25;
320SYSCTL_INT(_hw_bxe, OID_AUTO, hc_rx_ticks, CTLFLAG_RDTUN,
321           &bxe_hc_rx_ticks, 0, "Host Coalescing Rx ticks");
322
323/* Host interrupt coalescing TX tick timer (usecs) */
324static int bxe_hc_tx_ticks = 50;
325SYSCTL_INT(_hw_bxe, OID_AUTO, hc_tx_ticks, CTLFLAG_RDTUN,
326           &bxe_hc_tx_ticks, 0, "Host Coalescing Tx ticks");
327
328/* Maximum number of Rx packets to process at a time */
329static int bxe_rx_budget = 0xffffffff;
330SYSCTL_INT(_hw_bxe, OID_AUTO, rx_budget, CTLFLAG_TUN,
331           &bxe_rx_budget, 0, "Rx processing budget");
332
333/* Maximum LRO aggregation size */
334static int bxe_max_aggregation_size = 0;
335SYSCTL_INT(_hw_bxe, OID_AUTO, max_aggregation_size, CTLFLAG_TUN,
336           &bxe_max_aggregation_size, 0, "max aggregation size");
337
338/* PCI MRRS: -1 (Auto), 0 (128B), 1 (256B), 2 (512B), 3 (1KB) */
339static int bxe_mrrs = -1;
340SYSCTL_INT(_hw_bxe, OID_AUTO, mrrs, CTLFLAG_RDTUN,
341           &bxe_mrrs, 0, "PCIe maximum read request size");
342
343/* AutoGrEEEn: 0 (hardware default), 1 (force on), 2 (force off) */
344static int bxe_autogreeen = 0;
345SYSCTL_INT(_hw_bxe, OID_AUTO, autogreeen, CTLFLAG_RDTUN,
346           &bxe_autogreeen, 0, "AutoGrEEEn support");
347
348/* 4-tuple RSS support for UDP: 0 (disabled), 1 (enabled) */
349static int bxe_udp_rss = 0;
350SYSCTL_INT(_hw_bxe, OID_AUTO, udp_rss, CTLFLAG_RDTUN,
351           &bxe_udp_rss, 0, "UDP RSS support");
352
353
354#define STAT_NAME_LEN 32 /* no stat names below can be longer than this */
355
356#define STATS_OFFSET32(stat_name)                   \
357    (offsetof(struct bxe_eth_stats, stat_name) / 4)
358
359#define Q_STATS_OFFSET32(stat_name)                   \
360    (offsetof(struct bxe_eth_q_stats, stat_name) / 4)
361
362static const struct {
363    uint32_t offset;
364    uint32_t size;
365    uint32_t flags;
366#define STATS_FLAGS_PORT  1
367#define STATS_FLAGS_FUNC  2 /* MF only cares about function stats */
368#define STATS_FLAGS_BOTH  (STATS_FLAGS_FUNC | STATS_FLAGS_PORT)
369    char string[STAT_NAME_LEN];
370} bxe_eth_stats_arr[] = {
371    { STATS_OFFSET32(total_bytes_received_hi),
372                8, STATS_FLAGS_BOTH, "rx_bytes" },
373    { STATS_OFFSET32(error_bytes_received_hi),
374                8, STATS_FLAGS_BOTH, "rx_error_bytes" },
375    { STATS_OFFSET32(total_unicast_packets_received_hi),
376                8, STATS_FLAGS_BOTH, "rx_ucast_packets" },
377    { STATS_OFFSET32(total_multicast_packets_received_hi),
378                8, STATS_FLAGS_BOTH, "rx_mcast_packets" },
379    { STATS_OFFSET32(total_broadcast_packets_received_hi),
380                8, STATS_FLAGS_BOTH, "rx_bcast_packets" },
381    { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
382                8, STATS_FLAGS_PORT, "rx_crc_errors" },
383    { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
384                8, STATS_FLAGS_PORT, "rx_align_errors" },
385    { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
386                8, STATS_FLAGS_PORT, "rx_undersize_packets" },
387    { STATS_OFFSET32(etherstatsoverrsizepkts_hi),
388                8, STATS_FLAGS_PORT, "rx_oversize_packets" },
389    { STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
390                8, STATS_FLAGS_PORT, "rx_fragments" },
391    { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
392                8, STATS_FLAGS_PORT, "rx_jabbers" },
393    { STATS_OFFSET32(no_buff_discard_hi),
394                8, STATS_FLAGS_BOTH, "rx_discards" },
395    { STATS_OFFSET32(mac_filter_discard),
396                4, STATS_FLAGS_PORT, "rx_filtered_packets" },
397    { STATS_OFFSET32(mf_tag_discard),
398                4, STATS_FLAGS_PORT, "rx_mf_tag_discard" },
399    { STATS_OFFSET32(pfc_frames_received_hi),
400                8, STATS_FLAGS_PORT, "pfc_frames_received" },
401    { STATS_OFFSET32(pfc_frames_sent_hi),
402                8, STATS_FLAGS_PORT, "pfc_frames_sent" },
403    { STATS_OFFSET32(brb_drop_hi),
404                8, STATS_FLAGS_PORT, "rx_brb_discard" },
405    { STATS_OFFSET32(brb_truncate_hi),
406                8, STATS_FLAGS_PORT, "rx_brb_truncate" },
407    { STATS_OFFSET32(pause_frames_received_hi),
408                8, STATS_FLAGS_PORT, "rx_pause_frames" },
409    { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
410                8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" },
411    { STATS_OFFSET32(nig_timer_max),
412                4, STATS_FLAGS_PORT, "rx_constant_pause_events" },
413    { STATS_OFFSET32(total_bytes_transmitted_hi),
414                8, STATS_FLAGS_BOTH, "tx_bytes" },
415    { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
416                8, STATS_FLAGS_PORT, "tx_error_bytes" },
417    { STATS_OFFSET32(total_unicast_packets_transmitted_hi),
418                8, STATS_FLAGS_BOTH, "tx_ucast_packets" },
419    { STATS_OFFSET32(total_multicast_packets_transmitted_hi),
420                8, STATS_FLAGS_BOTH, "tx_mcast_packets" },
421    { STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
422                8, STATS_FLAGS_BOTH, "tx_bcast_packets" },
423    { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
424                8, STATS_FLAGS_PORT, "tx_mac_errors" },
425    { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
426                8, STATS_FLAGS_PORT, "tx_carrier_errors" },
427    { STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
428                8, STATS_FLAGS_PORT, "tx_single_collisions" },
429    { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
430                8, STATS_FLAGS_PORT, "tx_multi_collisions" },
431    { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
432                8, STATS_FLAGS_PORT, "tx_deferred" },
433    { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
434                8, STATS_FLAGS_PORT, "tx_excess_collisions" },
435    { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
436                8, STATS_FLAGS_PORT, "tx_late_collisions" },
437    { STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
438                8, STATS_FLAGS_PORT, "tx_total_collisions" },
439    { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
440                8, STATS_FLAGS_PORT, "tx_64_byte_packets" },
441    { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
442                8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" },
443    { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
444                8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" },
445    { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
446                8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" },
447    { STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
448                8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" },
449    { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
450                8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" },
451    { STATS_OFFSET32(etherstatspktsover1522octets_hi),
452                8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" },
453    { STATS_OFFSET32(pause_frames_sent_hi),
454                8, STATS_FLAGS_PORT, "tx_pause_frames" },
455    { STATS_OFFSET32(total_tpa_aggregations_hi),
456                8, STATS_FLAGS_FUNC, "tpa_aggregations" },
457    { STATS_OFFSET32(total_tpa_aggregated_frames_hi),
458                8, STATS_FLAGS_FUNC, "tpa_aggregated_frames"},
459    { STATS_OFFSET32(total_tpa_bytes_hi),
460                8, STATS_FLAGS_FUNC, "tpa_bytes"},
461#if 0
462    { STATS_OFFSET32(recoverable_error),
463                4, STATS_FLAGS_FUNC, "recoverable_errors" },
464    { STATS_OFFSET32(unrecoverable_error),
465                4, STATS_FLAGS_FUNC, "unrecoverable_errors" },
466#endif
467    { STATS_OFFSET32(eee_tx_lpi),
468                4, STATS_FLAGS_PORT, "eee_tx_lpi"},
469    { STATS_OFFSET32(rx_calls),
470                4, STATS_FLAGS_FUNC, "rx_calls"},
471    { STATS_OFFSET32(rx_pkts),
472                4, STATS_FLAGS_FUNC, "rx_pkts"},
473    { STATS_OFFSET32(rx_tpa_pkts),
474                4, STATS_FLAGS_FUNC, "rx_tpa_pkts"},
475    { STATS_OFFSET32(rx_jumbo_sge_pkts),
476                4, STATS_FLAGS_FUNC, "rx_jumbo_sge_pkts"},
477    { STATS_OFFSET32(rx_soft_errors),
478                4, STATS_FLAGS_FUNC, "rx_soft_errors"},
479    { STATS_OFFSET32(rx_hw_csum_errors),
480                4, STATS_FLAGS_FUNC, "rx_hw_csum_errors"},
481    { STATS_OFFSET32(rx_ofld_frames_csum_ip),
482                4, STATS_FLAGS_FUNC, "rx_ofld_frames_csum_ip"},
483    { STATS_OFFSET32(rx_ofld_frames_csum_tcp_udp),
484                4, STATS_FLAGS_FUNC, "rx_ofld_frames_csum_tcp_udp"},
485    { STATS_OFFSET32(rx_budget_reached),
486                4, STATS_FLAGS_FUNC, "rx_budget_reached"},
487    { STATS_OFFSET32(tx_pkts),
488                4, STATS_FLAGS_FUNC, "tx_pkts"},
489    { STATS_OFFSET32(tx_soft_errors),
490                4, STATS_FLAGS_FUNC, "tx_soft_errors"},
491    { STATS_OFFSET32(tx_ofld_frames_csum_ip),
492                4, STATS_FLAGS_FUNC, "tx_ofld_frames_csum_ip"},
493    { STATS_OFFSET32(tx_ofld_frames_csum_tcp),
494                4, STATS_FLAGS_FUNC, "tx_ofld_frames_csum_tcp"},
495    { STATS_OFFSET32(tx_ofld_frames_csum_udp),
496                4, STATS_FLAGS_FUNC, "tx_ofld_frames_csum_udp"},
497    { STATS_OFFSET32(tx_ofld_frames_lso),
498                4, STATS_FLAGS_FUNC, "tx_ofld_frames_lso"},
499    { STATS_OFFSET32(tx_ofld_frames_lso_hdr_splits),
500                4, STATS_FLAGS_FUNC, "tx_ofld_frames_lso_hdr_splits"},
501    { STATS_OFFSET32(tx_encap_failures),
502                4, STATS_FLAGS_FUNC, "tx_encap_failures"},
503    { STATS_OFFSET32(tx_hw_queue_full),
504                4, STATS_FLAGS_FUNC, "tx_hw_queue_full"},
505    { STATS_OFFSET32(tx_hw_max_queue_depth),
506                4, STATS_FLAGS_FUNC, "tx_hw_max_queue_depth"},
507    { STATS_OFFSET32(tx_dma_mapping_failure),
508                4, STATS_FLAGS_FUNC, "tx_dma_mapping_failure"},
509    { STATS_OFFSET32(tx_max_drbr_queue_depth),
510                4, STATS_FLAGS_FUNC, "tx_max_drbr_queue_depth"},
511    { STATS_OFFSET32(tx_window_violation_std),
512                4, STATS_FLAGS_FUNC, "tx_window_violation_std"},
513    { STATS_OFFSET32(tx_window_violation_tso),
514                4, STATS_FLAGS_FUNC, "tx_window_violation_tso"},
515#if 0
516    { STATS_OFFSET32(tx_unsupported_tso_request_ipv6),
517                4, STATS_FLAGS_FUNC, "tx_unsupported_tso_request_ipv6"},
518    { STATS_OFFSET32(tx_unsupported_tso_request_not_tcp),
519                4, STATS_FLAGS_FUNC, "tx_unsupported_tso_request_not_tcp"},
520#endif
521    { STATS_OFFSET32(tx_chain_lost_mbuf),
522                4, STATS_FLAGS_FUNC, "tx_chain_lost_mbuf"},
523    { STATS_OFFSET32(tx_frames_deferred),
524                4, STATS_FLAGS_FUNC, "tx_frames_deferred"},
525    { STATS_OFFSET32(tx_queue_xoff),
526                4, STATS_FLAGS_FUNC, "tx_queue_xoff"},
527    { STATS_OFFSET32(mbuf_defrag_attempts),
528                4, STATS_FLAGS_FUNC, "mbuf_defrag_attempts"},
529    { STATS_OFFSET32(mbuf_defrag_failures),
530                4, STATS_FLAGS_FUNC, "mbuf_defrag_failures"},
531    { STATS_OFFSET32(mbuf_rx_bd_alloc_failed),
532                4, STATS_FLAGS_FUNC, "mbuf_rx_bd_alloc_failed"},
533    { STATS_OFFSET32(mbuf_rx_bd_mapping_failed),
534                4, STATS_FLAGS_FUNC, "mbuf_rx_bd_mapping_failed"},
535    { STATS_OFFSET32(mbuf_rx_tpa_alloc_failed),
536                4, STATS_FLAGS_FUNC, "mbuf_rx_tpa_alloc_failed"},
537    { STATS_OFFSET32(mbuf_rx_tpa_mapping_failed),
538                4, STATS_FLAGS_FUNC, "mbuf_rx_tpa_mapping_failed"},
539    { STATS_OFFSET32(mbuf_rx_sge_alloc_failed),
540                4, STATS_FLAGS_FUNC, "mbuf_rx_sge_alloc_failed"},
541    { STATS_OFFSET32(mbuf_rx_sge_mapping_failed),
542                4, STATS_FLAGS_FUNC, "mbuf_rx_sge_mapping_failed"},
543    { STATS_OFFSET32(mbuf_alloc_tx),
544                4, STATS_FLAGS_FUNC, "mbuf_alloc_tx"},
545    { STATS_OFFSET32(mbuf_alloc_rx),
546                4, STATS_FLAGS_FUNC, "mbuf_alloc_rx"},
547    { STATS_OFFSET32(mbuf_alloc_sge),
548                4, STATS_FLAGS_FUNC, "mbuf_alloc_sge"},
549    { STATS_OFFSET32(mbuf_alloc_tpa),
550                4, STATS_FLAGS_FUNC, "mbuf_alloc_tpa"}
551};
552
553static const struct {
554    uint32_t offset;
555    uint32_t size;
556    char string[STAT_NAME_LEN];
557} bxe_eth_q_stats_arr[] = {
558    { Q_STATS_OFFSET32(total_bytes_received_hi),
559                8, "rx_bytes" },
560    { Q_STATS_OFFSET32(total_unicast_packets_received_hi),
561                8, "rx_ucast_packets" },
562    { Q_STATS_OFFSET32(total_multicast_packets_received_hi),
563                8, "rx_mcast_packets" },
564    { Q_STATS_OFFSET32(total_broadcast_packets_received_hi),
565                8, "rx_bcast_packets" },
566    { Q_STATS_OFFSET32(no_buff_discard_hi),
567                8, "rx_discards" },
568    { Q_STATS_OFFSET32(total_bytes_transmitted_hi),
569                8, "tx_bytes" },
570    { Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi),
571                8, "tx_ucast_packets" },
572    { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi),
573                8, "tx_mcast_packets" },
574    { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
575                8, "tx_bcast_packets" },
576    { Q_STATS_OFFSET32(total_tpa_aggregations_hi),
577                8, "tpa_aggregations" },
578    { Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi),
579                8, "tpa_aggregated_frames"},
580    { Q_STATS_OFFSET32(total_tpa_bytes_hi),
581                8, "tpa_bytes"},
582    { Q_STATS_OFFSET32(rx_calls),
583                4, "rx_calls"},
584    { Q_STATS_OFFSET32(rx_pkts),
585                4, "rx_pkts"},
586    { Q_STATS_OFFSET32(rx_tpa_pkts),
587                4, "rx_tpa_pkts"},
588    { Q_STATS_OFFSET32(rx_jumbo_sge_pkts),
589                4, "rx_jumbo_sge_pkts"},
590    { Q_STATS_OFFSET32(rx_soft_errors),
591                4, "rx_soft_errors"},
592    { Q_STATS_OFFSET32(rx_hw_csum_errors),
593                4, "rx_hw_csum_errors"},
594    { Q_STATS_OFFSET32(rx_ofld_frames_csum_ip),
595                4, "rx_ofld_frames_csum_ip"},
596    { Q_STATS_OFFSET32(rx_ofld_frames_csum_tcp_udp),
597                4, "rx_ofld_frames_csum_tcp_udp"},
598    { Q_STATS_OFFSET32(rx_budget_reached),
599                4, "rx_budget_reached"},
600    { Q_STATS_OFFSET32(tx_pkts),
601                4, "tx_pkts"},
602    { Q_STATS_OFFSET32(tx_soft_errors),
603                4, "tx_soft_errors"},
604    { Q_STATS_OFFSET32(tx_ofld_frames_csum_ip),
605                4, "tx_ofld_frames_csum_ip"},
606    { Q_STATS_OFFSET32(tx_ofld_frames_csum_tcp),
607                4, "tx_ofld_frames_csum_tcp"},
608    { Q_STATS_OFFSET32(tx_ofld_frames_csum_udp),
609                4, "tx_ofld_frames_csum_udp"},
610    { Q_STATS_OFFSET32(tx_ofld_frames_lso),
611                4, "tx_ofld_frames_lso"},
612    { Q_STATS_OFFSET32(tx_ofld_frames_lso_hdr_splits),
613                4, "tx_ofld_frames_lso_hdr_splits"},
614    { Q_STATS_OFFSET32(tx_encap_failures),
615                4, "tx_encap_failures"},
616    { Q_STATS_OFFSET32(tx_hw_queue_full),
617                4, "tx_hw_queue_full"},
618    { Q_STATS_OFFSET32(tx_hw_max_queue_depth),
619                4, "tx_hw_max_queue_depth"},
620    { Q_STATS_OFFSET32(tx_dma_mapping_failure),
621                4, "tx_dma_mapping_failure"},
622    { Q_STATS_OFFSET32(tx_max_drbr_queue_depth),
623                4, "tx_max_drbr_queue_depth"},
624    { Q_STATS_OFFSET32(tx_window_violation_std),
625                4, "tx_window_violation_std"},
626    { Q_STATS_OFFSET32(tx_window_violation_tso),
627                4, "tx_window_violation_tso"},
628#if 0
629    { Q_STATS_OFFSET32(tx_unsupported_tso_request_ipv6),
630                4, "tx_unsupported_tso_request_ipv6"},
631    { Q_STATS_OFFSET32(tx_unsupported_tso_request_not_tcp),
632                4, "tx_unsupported_tso_request_not_tcp"},
633#endif
634    { Q_STATS_OFFSET32(tx_chain_lost_mbuf),
635                4, "tx_chain_lost_mbuf"},
636    { Q_STATS_OFFSET32(tx_frames_deferred),
637                4, "tx_frames_deferred"},
638    { Q_STATS_OFFSET32(tx_queue_xoff),
639                4, "tx_queue_xoff"},
640    { Q_STATS_OFFSET32(mbuf_defrag_attempts),
641                4, "mbuf_defrag_attempts"},
642    { Q_STATS_OFFSET32(mbuf_defrag_failures),
643                4, "mbuf_defrag_failures"},
644    { Q_STATS_OFFSET32(mbuf_rx_bd_alloc_failed),
645                4, "mbuf_rx_bd_alloc_failed"},
646    { Q_STATS_OFFSET32(mbuf_rx_bd_mapping_failed),
647                4, "mbuf_rx_bd_mapping_failed"},
648    { Q_STATS_OFFSET32(mbuf_rx_tpa_alloc_failed),
649                4, "mbuf_rx_tpa_alloc_failed"},
650    { Q_STATS_OFFSET32(mbuf_rx_tpa_mapping_failed),
651                4, "mbuf_rx_tpa_mapping_failed"},
652    { Q_STATS_OFFSET32(mbuf_rx_sge_alloc_failed),
653                4, "mbuf_rx_sge_alloc_failed"},
654    { Q_STATS_OFFSET32(mbuf_rx_sge_mapping_failed),
655                4, "mbuf_rx_sge_mapping_failed"},
656    { Q_STATS_OFFSET32(mbuf_alloc_tx),
657                4, "mbuf_alloc_tx"},
658    { Q_STATS_OFFSET32(mbuf_alloc_rx),
659                4, "mbuf_alloc_rx"},
660    { Q_STATS_OFFSET32(mbuf_alloc_sge),
661                4, "mbuf_alloc_sge"},
662    { Q_STATS_OFFSET32(mbuf_alloc_tpa),
663                4, "mbuf_alloc_tpa"}
664};
665
666#define BXE_NUM_ETH_STATS   ARRAY_SIZE(bxe_eth_stats_arr)
667#define BXE_NUM_ETH_Q_STATS ARRAY_SIZE(bxe_eth_q_stats_arr)
668
669
670static void    bxe_cmng_fns_init(struct bxe_softc *sc,
671                                 uint8_t          read_cfg,
672                                 uint8_t          cmng_type);
673static int     bxe_get_cmng_fns_mode(struct bxe_softc *sc);
674static void    storm_memset_cmng(struct bxe_softc *sc,
675                                 struct cmng_init *cmng,
676                                 uint8_t          port);
677static void    bxe_set_reset_global(struct bxe_softc *sc);
678static void    bxe_set_reset_in_progress(struct bxe_softc *sc);
679static uint8_t bxe_reset_is_done(struct bxe_softc *sc,
680                                 int              engine);
681static uint8_t bxe_clear_pf_load(struct bxe_softc *sc);
682static uint8_t bxe_chk_parity_attn(struct bxe_softc *sc,
683                                   uint8_t          *global,
684                                   uint8_t          print);
685static void    bxe_int_disable(struct bxe_softc *sc);
686static int     bxe_release_leader_lock(struct bxe_softc *sc);
687static void    bxe_pf_disable(struct bxe_softc *sc);
688static void    bxe_free_fp_buffers(struct bxe_softc *sc);
689static inline void bxe_update_rx_prod(struct bxe_softc    *sc,
690                                      struct bxe_fastpath *fp,
691                                      uint16_t            rx_bd_prod,
692                                      uint16_t            rx_cq_prod,
693                                      uint16_t            rx_sge_prod);
694static void    bxe_link_report_locked(struct bxe_softc *sc);
695static void    bxe_link_report(struct bxe_softc *sc);
696static void    bxe_link_status_update(struct bxe_softc *sc);
697static void    bxe_periodic_callout_func(void *xsc);
698static void    bxe_periodic_start(struct bxe_softc *sc);
699static void    bxe_periodic_stop(struct bxe_softc *sc);
700static int     bxe_alloc_rx_bd_mbuf(struct bxe_fastpath *fp,
701                                    uint16_t prev_index,
702                                    uint16_t index);
703static int     bxe_alloc_rx_tpa_mbuf(struct bxe_fastpath *fp,
704                                     int                 queue);
705static int     bxe_alloc_rx_sge_mbuf(struct bxe_fastpath *fp,
706                                     uint16_t            index);
707static uint8_t bxe_txeof(struct bxe_softc *sc,
708                         struct bxe_fastpath *fp);
709static void    bxe_task_fp(struct bxe_fastpath *fp);
710static __noinline void bxe_dump_mbuf(struct bxe_softc *sc,
711                                     struct mbuf      *m,
712                                     uint8_t          contents);
713static int     bxe_alloc_mem(struct bxe_softc *sc);
714static void    bxe_free_mem(struct bxe_softc *sc);
715static int     bxe_alloc_fw_stats_mem(struct bxe_softc *sc);
716static void    bxe_free_fw_stats_mem(struct bxe_softc *sc);
717static int     bxe_interrupt_attach(struct bxe_softc *sc);
718static void    bxe_interrupt_detach(struct bxe_softc *sc);
719static void    bxe_set_rx_mode(struct bxe_softc *sc);
720static int     bxe_init_locked(struct bxe_softc *sc);
721static int     bxe_stop_locked(struct bxe_softc *sc);
722static __noinline int bxe_nic_load(struct bxe_softc *sc,
723                                   int              load_mode);
724static __noinline int bxe_nic_unload(struct bxe_softc *sc,
725                                     uint32_t         unload_mode,
726                                     uint8_t          keep_link);
727
728static void bxe_handle_sp_tq(void *context, int pending);
729static void bxe_handle_fp_tq(void *context, int pending);
730
731
732/* calculate crc32 on a buffer (NOTE: crc32_length MUST be aligned to 8) */
733uint32_t
734calc_crc32(uint8_t  *crc32_packet,
735           uint32_t crc32_length,
736           uint32_t crc32_seed,
737           uint8_t  complement)
738{
739   uint32_t byte         = 0;
740   uint32_t bit          = 0;
741   uint8_t  msb          = 0;
742   uint32_t temp         = 0;
743   uint32_t shft         = 0;
744   uint8_t  current_byte = 0;
745   uint32_t crc32_result = crc32_seed;
746   const uint32_t CRC32_POLY = 0x1edc6f41;
747
748   if ((crc32_packet == NULL) ||
749       (crc32_length == 0) ||
750       ((crc32_length % 8) != 0))
751    {
752        return (crc32_result);
753    }
754
755    for (byte = 0; byte < crc32_length; byte = byte + 1)
756    {
757        current_byte = crc32_packet[byte];
758        for (bit = 0; bit < 8; bit = bit + 1)
759        {
760            /* msb = crc32_result[31]; */
761            msb = (uint8_t)(crc32_result >> 31);
762
763            crc32_result = crc32_result << 1;
764
765            /* it (msb != current_byte[bit]) */
766            if (msb != (0x1 & (current_byte >> bit)))
767            {
768                crc32_result = crc32_result ^ CRC32_POLY;
769                /* crc32_result[0] = 1 */
770                crc32_result |= 1;
771            }
772        }
773    }
774
775    /* Last step is to:
776     * 1. "mirror" every bit
777     * 2. swap the 4 bytes
778     * 3. complement each bit
779     */
780
781    /* Mirror */
782    temp = crc32_result;
783    shft = sizeof(crc32_result) * 8 - 1;
784
785    for (crc32_result >>= 1; crc32_result; crc32_result >>= 1)
786    {
787        temp <<= 1;
788        temp |= crc32_result & 1;
789        shft-- ;
790    }
791
792    /* temp[31-bit] = crc32_result[bit] */
793    temp <<= shft;
794
795    /* Swap */
796    /* crc32_result = {temp[7:0], temp[15:8], temp[23:16], temp[31:24]} */
797    {
798        uint32_t t0, t1, t2, t3;
799        t0 = (0x000000ff & (temp >> 24));
800        t1 = (0x0000ff00 & (temp >> 8));
801        t2 = (0x00ff0000 & (temp << 8));
802        t3 = (0xff000000 & (temp << 24));
803        crc32_result = t0 | t1 | t2 | t3;
804    }
805
806    /* Complement */
807    if (complement)
808    {
809        crc32_result = ~crc32_result;
810    }
811
812    return (crc32_result);
813}
814
815int
816bxe_test_bit(int                    nr,
817             volatile unsigned long *addr)
818{
819    return ((atomic_load_acq_long(addr) & (1 << nr)) != 0);
820}
821
822void
823bxe_set_bit(unsigned int           nr,
824            volatile unsigned long *addr)
825{
826    atomic_set_acq_long(addr, (1 << nr));
827}
828
829void
830bxe_clear_bit(int                    nr,
831              volatile unsigned long *addr)
832{
833    atomic_clear_acq_long(addr, (1 << nr));
834}
835
836int
837bxe_test_and_set_bit(int                    nr,
838                       volatile unsigned long *addr)
839{
840    unsigned long x;
841    nr = (1 << nr);
842    do {
843        x = *addr;
844    } while (atomic_cmpset_acq_long(addr, x, x | nr) == 0);
845    // if (x & nr) bit_was_set; else bit_was_not_set;
846    return (x & nr);
847}
848
849int
850bxe_test_and_clear_bit(int                    nr,
851                       volatile unsigned long *addr)
852{
853    unsigned long x;
854    nr = (1 << nr);
855    do {
856        x = *addr;
857    } while (atomic_cmpset_acq_long(addr, x, x & ~nr) == 0);
858    // if (x & nr) bit_was_set; else bit_was_not_set;
859    return (x & nr);
860}
861
862int
863bxe_cmpxchg(volatile int *addr,
864            int          old,
865            int          new)
866{
867    int x;
868    do {
869        x = *addr;
870    } while (atomic_cmpset_acq_int(addr, old, new) == 0);
871    return (x);
872}
873
874/*
875 * Get DMA memory from the OS.
876 *
877 * Validates that the OS has provided DMA buffers in response to a
878 * bus_dmamap_load call and saves the physical address of those buffers.
879 * When the callback is used the OS will return 0 for the mapping function
880 * (bus_dmamap_load) so we use the value of map_arg->maxsegs to pass any
881 * failures back to the caller.
882 *
883 * Returns:
884 *   Nothing.
885 */
886static void
887bxe_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
888{
889    struct bxe_dma *dma = arg;
890
891    if (error) {
892        dma->paddr = 0;
893        dma->nseg  = 0;
894        BLOGE(dma->sc, "Failed DMA alloc '%s' (%d)!\n", dma->msg, error);
895    } else {
896        dma->paddr = segs->ds_addr;
897        dma->nseg  = nseg;
898#if 0
899        BLOGD(dma->sc, DBG_LOAD,
900              "DMA alloc '%s': vaddr=%p paddr=%p nseg=%d size=%lu\n",
901              dma->msg, dma->vaddr, (void *)dma->paddr,
902              dma->nseg, dma->size);
903#endif
904    }
905}
906
907/*
908 * Allocate a block of memory and map it for DMA. No partial completions
909 * allowed and release any resources acquired if we can't acquire all
910 * resources.
911 *
912 * Returns:
913 *   0 = Success, !0 = Failure
914 */
915int
916bxe_dma_alloc(struct bxe_softc *sc,
917              bus_size_t       size,
918              struct bxe_dma   *dma,
919              const char       *msg)
920{
921    int rc;
922
923    if (dma->size > 0) {
924        BLOGE(sc, "dma block '%s' already has size %lu\n", msg,
925              (unsigned long)dma->size);
926        return (1);
927    }
928
929    memset(dma, 0, sizeof(*dma)); /* sanity */
930    dma->sc   = sc;
931    dma->size = size;
932    snprintf(dma->msg, sizeof(dma->msg), "%s", msg);
933
934    rc = bus_dma_tag_create(sc->parent_dma_tag, /* parent tag */
935                            BCM_PAGE_SIZE,      /* alignment */
936                            0,                  /* boundary limit */
937                            BUS_SPACE_MAXADDR,  /* restricted low */
938                            BUS_SPACE_MAXADDR,  /* restricted hi */
939                            NULL,               /* addr filter() */
940                            NULL,               /* addr filter() arg */
941                            size,               /* max map size */
942                            1,                  /* num discontinuous */
943                            size,               /* max seg size */
944                            BUS_DMA_ALLOCNOW,   /* flags */
945                            NULL,               /* lock() */
946                            NULL,               /* lock() arg */
947                            &dma->tag);         /* returned dma tag */
948    if (rc != 0) {
949        BLOGE(sc, "Failed to create dma tag for '%s' (%d)\n", msg, rc);
950        memset(dma, 0, sizeof(*dma));
951        return (1);
952    }
953
954    rc = bus_dmamem_alloc(dma->tag,
955                          (void **)&dma->vaddr,
956                          (BUS_DMA_NOWAIT | BUS_DMA_ZERO),
957                          &dma->map);
958    if (rc != 0) {
959        BLOGE(sc, "Failed to alloc dma mem for '%s' (%d)\n", msg, rc);
960        bus_dma_tag_destroy(dma->tag);
961        memset(dma, 0, sizeof(*dma));
962        return (1);
963    }
964
965    rc = bus_dmamap_load(dma->tag,
966                         dma->map,
967                         dma->vaddr,
968                         size,
969                         bxe_dma_map_addr, /* BLOGD in here */
970                         dma,
971                         BUS_DMA_NOWAIT);
972    if (rc != 0) {
973        BLOGE(sc, "Failed to load dma map for '%s' (%d)\n", msg, rc);
974        bus_dmamem_free(dma->tag, dma->vaddr, dma->map);
975        bus_dma_tag_destroy(dma->tag);
976        memset(dma, 0, sizeof(*dma));
977        return (1);
978    }
979
980    return (0);
981}
982
983void
984bxe_dma_free(struct bxe_softc *sc,
985             struct bxe_dma   *dma)
986{
987    if (dma->size > 0) {
988#if 0
989        BLOGD(sc, DBG_LOAD,
990              "DMA free '%s': vaddr=%p paddr=%p nseg=%d size=%lu\n",
991              dma->msg, dma->vaddr, (void *)dma->paddr,
992              dma->nseg, dma->size);
993#endif
994
995        DBASSERT(sc, (dma->tag != NULL), ("dma tag is NULL"));
996
997        bus_dmamap_sync(dma->tag, dma->map,
998                        (BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE));
999        bus_dmamap_unload(dma->tag, dma->map);
1000        bus_dmamem_free(dma->tag, dma->vaddr, dma->map);
1001        bus_dma_tag_destroy(dma->tag);
1002    }
1003
1004    memset(dma, 0, sizeof(*dma));
1005}
1006
1007/*
1008 * These indirect read and write routines are only during init.
1009 * The locking is handled by the MCP.
1010 */
1011
1012void
1013bxe_reg_wr_ind(struct bxe_softc *sc,
1014               uint32_t         addr,
1015               uint32_t         val)
1016{
1017    pci_write_config(sc->dev, PCICFG_GRC_ADDRESS, addr, 4);
1018    pci_write_config(sc->dev, PCICFG_GRC_DATA, val, 4);
1019    pci_write_config(sc->dev, PCICFG_GRC_ADDRESS, 0, 4);
1020}
1021
1022uint32_t
1023bxe_reg_rd_ind(struct bxe_softc *sc,
1024               uint32_t         addr)
1025{
1026    uint32_t val;
1027
1028    pci_write_config(sc->dev, PCICFG_GRC_ADDRESS, addr, 4);
1029    val = pci_read_config(sc->dev, PCICFG_GRC_DATA, 4);
1030    pci_write_config(sc->dev, PCICFG_GRC_ADDRESS, 0, 4);
1031
1032    return (val);
1033}
1034
1035#if 0
1036void bxe_dp_dmae(struct bxe_softc *sc, struct dmae_command *dmae, int msglvl)
1037{
1038    uint32_t src_type = dmae->opcode & DMAE_COMMAND_SRC;
1039
1040    switch (dmae->opcode & DMAE_COMMAND_DST) {
1041    case DMAE_CMD_DST_PCI:
1042        if (src_type == DMAE_CMD_SRC_PCI)
1043            DP(msglvl, "DMAE: opcode 0x%08x\n"
1044               "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
1045               "comp_addr [%x:%08x], comp_val 0x%08x\n",
1046               dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
1047               dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
1048               dmae->comp_addr_hi, dmae->comp_addr_lo,
1049               dmae->comp_val);
1050        else
1051            DP(msglvl, "DMAE: opcode 0x%08x\n"
1052               "src [%08x], len [%d*4], dst [%x:%08x]\n"
1053               "comp_addr [%x:%08x], comp_val 0x%08x\n",
1054               dmae->opcode, dmae->src_addr_lo >> 2,
1055               dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
1056               dmae->comp_addr_hi, dmae->comp_addr_lo,
1057               dmae->comp_val);
1058        break;
1059    case DMAE_CMD_DST_GRC:
1060        if (src_type == DMAE_CMD_SRC_PCI)
1061            DP(msglvl, "DMAE: opcode 0x%08x\n"
1062               "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
1063               "comp_addr [%x:%08x], comp_val 0x%08x\n",
1064               dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
1065               dmae->len, dmae->dst_addr_lo >> 2,
1066               dmae->comp_addr_hi, dmae->comp_addr_lo,
1067               dmae->comp_val);
1068        else
1069            DP(msglvl, "DMAE: opcode 0x%08x\n"
1070               "src [%08x], len [%d*4], dst [%08x]\n"
1071               "comp_addr [%x:%08x], comp_val 0x%08x\n",
1072               dmae->opcode, dmae->src_addr_lo >> 2,
1073               dmae->len, dmae->dst_addr_lo >> 2,
1074               dmae->comp_addr_hi, dmae->comp_addr_lo,
1075               dmae->comp_val);
1076        break;
1077    default:
1078        if (src_type == DMAE_CMD_SRC_PCI)
1079            DP(msglvl, "DMAE: opcode 0x%08x\n"
1080               "src_addr [%x:%08x]  len [%d * 4]  dst_addr [none]\n"
1081               "comp_addr [%x:%08x]  comp_val 0x%08x\n",
1082               dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
1083               dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
1084               dmae->comp_val);
1085        else
1086            DP(msglvl, "DMAE: opcode 0x%08x\n"
1087               "src_addr [%08x]  len [%d * 4]  dst_addr [none]\n"
1088               "comp_addr [%x:%08x]  comp_val 0x%08x\n",
1089               dmae->opcode, dmae->src_addr_lo >> 2,
1090               dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
1091               dmae->comp_val);
1092        break;
1093    }
1094
1095}
1096#endif
1097
1098static int
1099bxe_acquire_hw_lock(struct bxe_softc *sc,
1100                    uint32_t         resource)
1101{
1102    uint32_t lock_status;
1103    uint32_t resource_bit = (1 << resource);
1104    int func = SC_FUNC(sc);
1105    uint32_t hw_lock_control_reg;
1106    int cnt;
1107
1108    /* validate the resource is within range */
1109    if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1110        BLOGE(sc, "resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE\n", resource);
1111        return (-1);
1112    }
1113
1114    if (func <= 5) {
1115        hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
1116    } else {
1117        hw_lock_control_reg =
1118                (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
1119    }
1120
1121    /* validate the resource is not already taken */
1122    lock_status = REG_RD(sc, hw_lock_control_reg);
1123    if (lock_status & resource_bit) {
1124        BLOGE(sc, "resource in use (status 0x%x bit 0x%x)\n",
1125              lock_status, resource_bit);
1126        return (-1);
1127    }
1128
1129    /* try every 5ms for 5 seconds */
1130    for (cnt = 0; cnt < 1000; cnt++) {
1131        REG_WR(sc, (hw_lock_control_reg + 4), resource_bit);
1132        lock_status = REG_RD(sc, hw_lock_control_reg);
1133        if (lock_status & resource_bit) {
1134            return (0);
1135        }
1136        DELAY(5000);
1137    }
1138
1139    BLOGE(sc, "Resource lock timeout!\n");
1140    return (-1);
1141}
1142
1143static int
1144bxe_release_hw_lock(struct bxe_softc *sc,
1145                    uint32_t         resource)
1146{
1147    uint32_t lock_status;
1148    uint32_t resource_bit = (1 << resource);
1149    int func = SC_FUNC(sc);
1150    uint32_t hw_lock_control_reg;
1151
1152    /* validate the resource is within range */
1153    if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1154        BLOGE(sc, "resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE\n", resource);
1155        return (-1);
1156    }
1157
1158    if (func <= 5) {
1159        hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
1160    } else {
1161        hw_lock_control_reg =
1162                (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
1163    }
1164
1165    /* validate the resource is currently taken */
1166    lock_status = REG_RD(sc, hw_lock_control_reg);
1167    if (!(lock_status & resource_bit)) {
1168        BLOGE(sc, "resource not in use (status 0x%x bit 0x%x)\n",
1169              lock_status, resource_bit);
1170        return (-1);
1171    }
1172
1173    REG_WR(sc, hw_lock_control_reg, resource_bit);
1174    return (0);
1175}
1176static void bxe_acquire_phy_lock(struct bxe_softc *sc)
1177{
1178	BXE_PHY_LOCK(sc);
1179	bxe_acquire_hw_lock(sc,HW_LOCK_RESOURCE_MDIO);
1180}
1181
1182static void bxe_release_phy_lock(struct bxe_softc *sc)
1183{
1184	bxe_release_hw_lock(sc,HW_LOCK_RESOURCE_MDIO);
1185	BXE_PHY_UNLOCK(sc);
1186}
1187/*
1188 * Per pf misc lock must be acquired before the per port mcp lock. Otherwise,
1189 * had we done things the other way around, if two pfs from the same port
1190 * would attempt to access nvram at the same time, we could run into a
1191 * scenario such as:
1192 * pf A takes the port lock.
1193 * pf B succeeds in taking the same lock since they are from the same port.
1194 * pf A takes the per pf misc lock. Performs eeprom access.
1195 * pf A finishes. Unlocks the per pf misc lock.
1196 * Pf B takes the lock and proceeds to perform it's own access.
1197 * pf A unlocks the per port lock, while pf B is still working (!).
1198 * mcp takes the per port lock and corrupts pf B's access (and/or has it's own
1199 * access corrupted by pf B).*
1200 */
1201static int
1202bxe_acquire_nvram_lock(struct bxe_softc *sc)
1203{
1204    int port = SC_PORT(sc);
1205    int count, i;
1206    uint32_t val = 0;
1207
1208    /* acquire HW lock: protect against other PFs in PF Direct Assignment */
1209    bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_NVRAM);
1210
1211    /* adjust timeout for emulation/FPGA */
1212    count = NVRAM_TIMEOUT_COUNT;
1213    if (CHIP_REV_IS_SLOW(sc)) {
1214        count *= 100;
1215    }
1216
1217    /* request access to nvram interface */
1218    REG_WR(sc, MCP_REG_MCPR_NVM_SW_ARB,
1219           (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
1220
1221    for (i = 0; i < count*10; i++) {
1222        val = REG_RD(sc, MCP_REG_MCPR_NVM_SW_ARB);
1223        if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
1224            break;
1225        }
1226
1227        DELAY(5);
1228    }
1229
1230    if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
1231        BLOGE(sc, "Cannot get access to nvram interface\n");
1232        return (-1);
1233    }
1234
1235    return (0);
1236}
1237
1238static int
1239bxe_release_nvram_lock(struct bxe_softc *sc)
1240{
1241    int port = SC_PORT(sc);
1242    int count, i;
1243    uint32_t val = 0;
1244
1245    /* adjust timeout for emulation/FPGA */
1246    count = NVRAM_TIMEOUT_COUNT;
1247    if (CHIP_REV_IS_SLOW(sc)) {
1248        count *= 100;
1249    }
1250
1251    /* relinquish nvram interface */
1252    REG_WR(sc, MCP_REG_MCPR_NVM_SW_ARB,
1253           (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
1254
1255    for (i = 0; i < count*10; i++) {
1256        val = REG_RD(sc, MCP_REG_MCPR_NVM_SW_ARB);
1257        if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
1258            break;
1259        }
1260
1261        DELAY(5);
1262    }
1263
1264    if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
1265        BLOGE(sc, "Cannot free access to nvram interface\n");
1266        return (-1);
1267    }
1268
1269    /* release HW lock: protect against other PFs in PF Direct Assignment */
1270    bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_NVRAM);
1271
1272    return (0);
1273}
1274
1275static void
1276bxe_enable_nvram_access(struct bxe_softc *sc)
1277{
1278    uint32_t val;
1279
1280    val = REG_RD(sc, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1281
1282    /* enable both bits, even on read */
1283    REG_WR(sc, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1284           (val | MCPR_NVM_ACCESS_ENABLE_EN | MCPR_NVM_ACCESS_ENABLE_WR_EN));
1285}
1286
1287static void
1288bxe_disable_nvram_access(struct bxe_softc *sc)
1289{
1290    uint32_t val;
1291
1292    val = REG_RD(sc, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1293
1294    /* disable both bits, even after read */
1295    REG_WR(sc, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1296           (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
1297                    MCPR_NVM_ACCESS_ENABLE_WR_EN)));
1298}
1299
1300static int
1301bxe_nvram_read_dword(struct bxe_softc *sc,
1302                     uint32_t         offset,
1303                     uint32_t         *ret_val,
1304                     uint32_t         cmd_flags)
1305{
1306    int count, i, rc;
1307    uint32_t val;
1308
1309    /* build the command word */
1310    cmd_flags |= MCPR_NVM_COMMAND_DOIT;
1311
1312    /* need to clear DONE bit separately */
1313    REG_WR(sc, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1314
1315    /* address of the NVRAM to read from */
1316    REG_WR(sc, MCP_REG_MCPR_NVM_ADDR,
1317           (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1318
1319    /* issue a read command */
1320    REG_WR(sc, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1321
1322    /* adjust timeout for emulation/FPGA */
1323    count = NVRAM_TIMEOUT_COUNT;
1324    if (CHIP_REV_IS_SLOW(sc)) {
1325        count *= 100;
1326    }
1327
1328    /* wait for completion */
1329    *ret_val = 0;
1330    rc = -1;
1331    for (i = 0; i < count; i++) {
1332        DELAY(5);
1333        val = REG_RD(sc, MCP_REG_MCPR_NVM_COMMAND);
1334
1335        if (val & MCPR_NVM_COMMAND_DONE) {
1336            val = REG_RD(sc, MCP_REG_MCPR_NVM_READ);
1337            /* we read nvram data in cpu order
1338             * but ethtool sees it as an array of bytes
1339             * converting to big-endian will do the work
1340             */
1341            *ret_val = htobe32(val);
1342            rc = 0;
1343            break;
1344        }
1345    }
1346
1347    if (rc == -1) {
1348        BLOGE(sc, "nvram read timeout expired\n");
1349    }
1350
1351    return (rc);
1352}
1353
1354static int
1355bxe_nvram_read(struct bxe_softc *sc,
1356               uint32_t         offset,
1357               uint8_t          *ret_buf,
1358               int              buf_size)
1359{
1360    uint32_t cmd_flags;
1361    uint32_t val;
1362    int rc;
1363
1364    if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1365        BLOGE(sc, "Invalid parameter, offset 0x%x buf_size 0x%x\n",
1366              offset, buf_size);
1367        return (-1);
1368    }
1369
1370    if ((offset + buf_size) > sc->devinfo.flash_size) {
1371        BLOGE(sc, "Invalid parameter, "
1372                  "offset 0x%x + buf_size 0x%x > flash_size 0x%x\n",
1373              offset, buf_size, sc->devinfo.flash_size);
1374        return (-1);
1375    }
1376
1377    /* request access to nvram interface */
1378    rc = bxe_acquire_nvram_lock(sc);
1379    if (rc) {
1380        return (rc);
1381    }
1382
1383    /* enable access to nvram interface */
1384    bxe_enable_nvram_access(sc);
1385
1386    /* read the first word(s) */
1387    cmd_flags = MCPR_NVM_COMMAND_FIRST;
1388    while ((buf_size > sizeof(uint32_t)) && (rc == 0)) {
1389        rc = bxe_nvram_read_dword(sc, offset, &val, cmd_flags);
1390        memcpy(ret_buf, &val, 4);
1391
1392        /* advance to the next dword */
1393        offset += sizeof(uint32_t);
1394        ret_buf += sizeof(uint32_t);
1395        buf_size -= sizeof(uint32_t);
1396        cmd_flags = 0;
1397    }
1398
1399    if (rc == 0) {
1400        cmd_flags |= MCPR_NVM_COMMAND_LAST;
1401        rc = bxe_nvram_read_dword(sc, offset, &val, cmd_flags);
1402        memcpy(ret_buf, &val, 4);
1403    }
1404
1405    /* disable access to nvram interface */
1406    bxe_disable_nvram_access(sc);
1407    bxe_release_nvram_lock(sc);
1408
1409    return (rc);
1410}
1411
1412static int
1413bxe_nvram_write_dword(struct bxe_softc *sc,
1414                      uint32_t         offset,
1415                      uint32_t         val,
1416                      uint32_t         cmd_flags)
1417{
1418    int count, i, rc;
1419
1420    /* build the command word */
1421    cmd_flags |= (MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR);
1422
1423    /* need to clear DONE bit separately */
1424    REG_WR(sc, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1425
1426    /* write the data */
1427    REG_WR(sc, MCP_REG_MCPR_NVM_WRITE, val);
1428
1429    /* address of the NVRAM to write to */
1430    REG_WR(sc, MCP_REG_MCPR_NVM_ADDR,
1431           (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1432
1433    /* issue the write command */
1434    REG_WR(sc, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1435
1436    /* adjust timeout for emulation/FPGA */
1437    count = NVRAM_TIMEOUT_COUNT;
1438    if (CHIP_REV_IS_SLOW(sc)) {
1439        count *= 100;
1440    }
1441
1442    /* wait for completion */
1443    rc = -1;
1444    for (i = 0; i < count; i++) {
1445        DELAY(5);
1446        val = REG_RD(sc, MCP_REG_MCPR_NVM_COMMAND);
1447        if (val & MCPR_NVM_COMMAND_DONE) {
1448            rc = 0;
1449            break;
1450        }
1451    }
1452
1453    if (rc == -1) {
1454        BLOGE(sc, "nvram write timeout expired\n");
1455    }
1456
1457    return (rc);
1458}
1459
1460#define BYTE_OFFSET(offset) (8 * (offset & 0x03))
1461
1462static int
1463bxe_nvram_write1(struct bxe_softc *sc,
1464                 uint32_t         offset,
1465                 uint8_t          *data_buf,
1466                 int              buf_size)
1467{
1468    uint32_t cmd_flags;
1469    uint32_t align_offset;
1470    uint32_t val;
1471    int rc;
1472
1473    if ((offset + buf_size) > sc->devinfo.flash_size) {
1474        BLOGE(sc, "Invalid parameter, "
1475                  "offset 0x%x + buf_size 0x%x > flash_size 0x%x\n",
1476              offset, buf_size, sc->devinfo.flash_size);
1477        return (-1);
1478    }
1479
1480    /* request access to nvram interface */
1481    rc = bxe_acquire_nvram_lock(sc);
1482    if (rc) {
1483        return (rc);
1484    }
1485
1486    /* enable access to nvram interface */
1487    bxe_enable_nvram_access(sc);
1488
1489    cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
1490    align_offset = (offset & ~0x03);
1491    rc = bxe_nvram_read_dword(sc, align_offset, &val, cmd_flags);
1492
1493    if (rc == 0) {
1494        val &= ~(0xff << BYTE_OFFSET(offset));
1495        val |= (*data_buf << BYTE_OFFSET(offset));
1496
1497        /* nvram data is returned as an array of bytes
1498         * convert it back to cpu order
1499         */
1500        val = be32toh(val);
1501
1502        rc = bxe_nvram_write_dword(sc, align_offset, val, cmd_flags);
1503    }
1504
1505    /* disable access to nvram interface */
1506    bxe_disable_nvram_access(sc);
1507    bxe_release_nvram_lock(sc);
1508
1509    return (rc);
1510}
1511
1512static int
1513bxe_nvram_write(struct bxe_softc *sc,
1514                uint32_t         offset,
1515                uint8_t          *data_buf,
1516                int              buf_size)
1517{
1518    uint32_t cmd_flags;
1519    uint32_t val;
1520    uint32_t written_so_far;
1521    int rc;
1522
1523    if (buf_size == 1) {
1524        return (bxe_nvram_write1(sc, offset, data_buf, buf_size));
1525    }
1526
1527    if ((offset & 0x03) || (buf_size & 0x03) /* || (buf_size == 0) */) {
1528        BLOGE(sc, "Invalid parameter, offset 0x%x buf_size 0x%x\n",
1529              offset, buf_size);
1530        return (-1);
1531    }
1532
1533    if (buf_size == 0) {
1534        return (0); /* nothing to do */
1535    }
1536
1537    if ((offset + buf_size) > sc->devinfo.flash_size) {
1538        BLOGE(sc, "Invalid parameter, "
1539                  "offset 0x%x + buf_size 0x%x > flash_size 0x%x\n",
1540              offset, buf_size, sc->devinfo.flash_size);
1541        return (-1);
1542    }
1543
1544    /* request access to nvram interface */
1545    rc = bxe_acquire_nvram_lock(sc);
1546    if (rc) {
1547        return (rc);
1548    }
1549
1550    /* enable access to nvram interface */
1551    bxe_enable_nvram_access(sc);
1552
1553    written_so_far = 0;
1554    cmd_flags = MCPR_NVM_COMMAND_FIRST;
1555    while ((written_so_far < buf_size) && (rc == 0)) {
1556        if (written_so_far == (buf_size - sizeof(uint32_t))) {
1557            cmd_flags |= MCPR_NVM_COMMAND_LAST;
1558        } else if (((offset + 4) % NVRAM_PAGE_SIZE) == 0) {
1559            cmd_flags |= MCPR_NVM_COMMAND_LAST;
1560        } else if ((offset % NVRAM_PAGE_SIZE) == 0) {
1561            cmd_flags |= MCPR_NVM_COMMAND_FIRST;
1562        }
1563
1564        memcpy(&val, data_buf, 4);
1565
1566        rc = bxe_nvram_write_dword(sc, offset, val, cmd_flags);
1567
1568        /* advance to the next dword */
1569        offset += sizeof(uint32_t);
1570        data_buf += sizeof(uint32_t);
1571        written_so_far += sizeof(uint32_t);
1572        cmd_flags = 0;
1573    }
1574
1575    /* disable access to nvram interface */
1576    bxe_disable_nvram_access(sc);
1577    bxe_release_nvram_lock(sc);
1578
1579    return (rc);
1580}
1581
1582/* copy command into DMAE command memory and set DMAE command Go */
1583void
1584bxe_post_dmae(struct bxe_softc    *sc,
1585              struct dmae_command *dmae,
1586              int                 idx)
1587{
1588    uint32_t cmd_offset;
1589    int i;
1590
1591    cmd_offset = (DMAE_REG_CMD_MEM + (sizeof(struct dmae_command) * idx));
1592    for (i = 0; i < ((sizeof(struct dmae_command) / 4)); i++) {
1593        REG_WR(sc, (cmd_offset + (i * 4)), *(((uint32_t *)dmae) + i));
1594    }
1595
1596    REG_WR(sc, dmae_reg_go_c[idx], 1);
1597}
1598
1599uint32_t
1600bxe_dmae_opcode_add_comp(uint32_t opcode,
1601                         uint8_t  comp_type)
1602{
1603    return (opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
1604                      DMAE_COMMAND_C_TYPE_ENABLE));
1605}
1606
1607uint32_t
1608bxe_dmae_opcode_clr_src_reset(uint32_t opcode)
1609{
1610    return (opcode & ~DMAE_COMMAND_SRC_RESET);
1611}
1612
1613uint32_t
1614bxe_dmae_opcode(struct bxe_softc *sc,
1615                uint8_t          src_type,
1616                uint8_t          dst_type,
1617                uint8_t          with_comp,
1618                uint8_t          comp_type)
1619{
1620    uint32_t opcode = 0;
1621
1622    opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
1623               (dst_type << DMAE_COMMAND_DST_SHIFT));
1624
1625    opcode |= (DMAE_COMMAND_SRC_RESET | DMAE_COMMAND_DST_RESET);
1626
1627    opcode |= (SC_PORT(sc) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
1628
1629    opcode |= ((SC_VN(sc) << DMAE_COMMAND_E1HVN_SHIFT) |
1630               (SC_VN(sc) << DMAE_COMMAND_DST_VN_SHIFT));
1631
1632    opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
1633
1634#ifdef __BIG_ENDIAN
1635    opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
1636#else
1637    opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
1638#endif
1639
1640    if (with_comp) {
1641        opcode = bxe_dmae_opcode_add_comp(opcode, comp_type);
1642    }
1643
1644    return (opcode);
1645}
1646
1647static void
1648bxe_prep_dmae_with_comp(struct bxe_softc    *sc,
1649                        struct dmae_command *dmae,
1650                        uint8_t             src_type,
1651                        uint8_t             dst_type)
1652{
1653    memset(dmae, 0, sizeof(struct dmae_command));
1654
1655    /* set the opcode */
1656    dmae->opcode = bxe_dmae_opcode(sc, src_type, dst_type,
1657                                   TRUE, DMAE_COMP_PCI);
1658
1659    /* fill in the completion parameters */
1660    dmae->comp_addr_lo = U64_LO(BXE_SP_MAPPING(sc, wb_comp));
1661    dmae->comp_addr_hi = U64_HI(BXE_SP_MAPPING(sc, wb_comp));
1662    dmae->comp_val     = DMAE_COMP_VAL;
1663}
1664
1665/* issue a DMAE command over the init channel and wait for completion */
1666static int
1667bxe_issue_dmae_with_comp(struct bxe_softc    *sc,
1668                         struct dmae_command *dmae)
1669{
1670    uint32_t *wb_comp = BXE_SP(sc, wb_comp);
1671    int timeout = CHIP_REV_IS_SLOW(sc) ? 400000 : 4000;
1672
1673    BXE_DMAE_LOCK(sc);
1674
1675    /* reset completion */
1676    *wb_comp = 0;
1677
1678    /* post the command on the channel used for initializations */
1679    bxe_post_dmae(sc, dmae, INIT_DMAE_C(sc));
1680
1681    /* wait for completion */
1682    DELAY(5);
1683
1684    while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
1685        if (!timeout ||
1686            (sc->recovery_state != BXE_RECOVERY_DONE &&
1687             sc->recovery_state != BXE_RECOVERY_NIC_LOADING)) {
1688            BLOGE(sc, "DMAE timeout!\n");
1689            BXE_DMAE_UNLOCK(sc);
1690            return (DMAE_TIMEOUT);
1691        }
1692
1693        timeout--;
1694        DELAY(50);
1695    }
1696
1697    if (*wb_comp & DMAE_PCI_ERR_FLAG) {
1698        BLOGE(sc, "DMAE PCI error!\n");
1699        BXE_DMAE_UNLOCK(sc);
1700        return (DMAE_PCI_ERROR);
1701    }
1702
1703    BXE_DMAE_UNLOCK(sc);
1704    return (0);
1705}
1706
1707void
1708bxe_read_dmae(struct bxe_softc *sc,
1709              uint32_t         src_addr,
1710              uint32_t         len32)
1711{
1712    struct dmae_command dmae;
1713    uint32_t *data;
1714    int i, rc;
1715
1716    DBASSERT(sc, (len32 <= 4), ("DMAE read length is %d", len32));
1717
1718    if (!sc->dmae_ready) {
1719        data = BXE_SP(sc, wb_data[0]);
1720
1721        for (i = 0; i < len32; i++) {
1722            data[i] = (CHIP_IS_E1(sc)) ?
1723                          bxe_reg_rd_ind(sc, (src_addr + (i * 4))) :
1724                          REG_RD(sc, (src_addr + (i * 4)));
1725        }
1726
1727        return;
1728    }
1729
1730    /* set opcode and fixed command fields */
1731    bxe_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
1732
1733    /* fill in addresses and len */
1734    dmae.src_addr_lo = (src_addr >> 2); /* GRC addr has dword resolution */
1735    dmae.src_addr_hi = 0;
1736    dmae.dst_addr_lo = U64_LO(BXE_SP_MAPPING(sc, wb_data));
1737    dmae.dst_addr_hi = U64_HI(BXE_SP_MAPPING(sc, wb_data));
1738    dmae.len         = len32;
1739
1740    /* issue the command and wait for completion */
1741    if ((rc = bxe_issue_dmae_with_comp(sc, &dmae)) != 0) {
1742        bxe_panic(sc, ("DMAE failed (%d)\n", rc));
1743    };
1744}
1745
1746void
1747bxe_write_dmae(struct bxe_softc *sc,
1748               bus_addr_t       dma_addr,
1749               uint32_t         dst_addr,
1750               uint32_t         len32)
1751{
1752    struct dmae_command dmae;
1753    int rc;
1754
1755    if (!sc->dmae_ready) {
1756        DBASSERT(sc, (len32 <= 4), ("DMAE not ready and length is %d", len32));
1757
1758        if (CHIP_IS_E1(sc)) {
1759            ecore_init_ind_wr(sc, dst_addr, BXE_SP(sc, wb_data[0]), len32);
1760        } else {
1761            ecore_init_str_wr(sc, dst_addr, BXE_SP(sc, wb_data[0]), len32);
1762        }
1763
1764        return;
1765    }
1766
1767    /* set opcode and fixed command fields */
1768    bxe_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
1769
1770    /* fill in addresses and len */
1771    dmae.src_addr_lo = U64_LO(dma_addr);
1772    dmae.src_addr_hi = U64_HI(dma_addr);
1773    dmae.dst_addr_lo = (dst_addr >> 2); /* GRC addr has dword resolution */
1774    dmae.dst_addr_hi = 0;
1775    dmae.len         = len32;
1776
1777    /* issue the command and wait for completion */
1778    if ((rc = bxe_issue_dmae_with_comp(sc, &dmae)) != 0) {
1779        bxe_panic(sc, ("DMAE failed (%d)\n", rc));
1780    }
1781}
1782
1783void
1784bxe_write_dmae_phys_len(struct bxe_softc *sc,
1785                        bus_addr_t       phys_addr,
1786                        uint32_t         addr,
1787                        uint32_t         len)
1788{
1789    int dmae_wr_max = DMAE_LEN32_WR_MAX(sc);
1790    int offset = 0;
1791
1792    while (len > dmae_wr_max) {
1793        bxe_write_dmae(sc,
1794                       (phys_addr + offset), /* src DMA address */
1795                       (addr + offset),      /* dst GRC address */
1796                       dmae_wr_max);
1797        offset += (dmae_wr_max * 4);
1798        len -= dmae_wr_max;
1799    }
1800
1801    bxe_write_dmae(sc,
1802                   (phys_addr + offset), /* src DMA address */
1803                   (addr + offset),      /* dst GRC address */
1804                   len);
1805}
1806
1807void
1808bxe_set_ctx_validation(struct bxe_softc   *sc,
1809                       struct eth_context *cxt,
1810                       uint32_t           cid)
1811{
1812    /* ustorm cxt validation */
1813    cxt->ustorm_ag_context.cdu_usage =
1814        CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
1815            CDU_REGION_NUMBER_UCM_AG, ETH_CONNECTION_TYPE);
1816    /* xcontext validation */
1817    cxt->xstorm_ag_context.cdu_reserved =
1818        CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
1819            CDU_REGION_NUMBER_XCM_AG, ETH_CONNECTION_TYPE);
1820}
1821
1822static void
1823bxe_storm_memset_hc_timeout(struct bxe_softc *sc,
1824                            uint8_t          port,
1825                            uint8_t          fw_sb_id,
1826                            uint8_t          sb_index,
1827                            uint8_t          ticks)
1828{
1829    uint32_t addr =
1830        (BAR_CSTRORM_INTMEM +
1831         CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(fw_sb_id, sb_index));
1832
1833    REG_WR8(sc, addr, ticks);
1834
1835    BLOGD(sc, DBG_LOAD,
1836          "port %d fw_sb_id %d sb_index %d ticks %d\n",
1837          port, fw_sb_id, sb_index, ticks);
1838}
1839
1840static void
1841bxe_storm_memset_hc_disable(struct bxe_softc *sc,
1842                            uint8_t          port,
1843                            uint16_t         fw_sb_id,
1844                            uint8_t          sb_index,
1845                            uint8_t          disable)
1846{
1847    uint32_t enable_flag =
1848        (disable) ? 0 : (1 << HC_INDEX_DATA_HC_ENABLED_SHIFT);
1849    uint32_t addr =
1850        (BAR_CSTRORM_INTMEM +
1851         CSTORM_STATUS_BLOCK_DATA_FLAGS_OFFSET(fw_sb_id, sb_index));
1852    uint8_t flags;
1853
1854    /* clear and set */
1855    flags = REG_RD8(sc, addr);
1856    flags &= ~HC_INDEX_DATA_HC_ENABLED;
1857    flags |= enable_flag;
1858    REG_WR8(sc, addr, flags);
1859
1860    BLOGD(sc, DBG_LOAD,
1861          "port %d fw_sb_id %d sb_index %d disable %d\n",
1862          port, fw_sb_id, sb_index, disable);
1863}
1864
1865void
1866bxe_update_coalesce_sb_index(struct bxe_softc *sc,
1867                             uint8_t          fw_sb_id,
1868                             uint8_t          sb_index,
1869                             uint8_t          disable,
1870                             uint16_t         usec)
1871{
1872    int port = SC_PORT(sc);
1873    uint8_t ticks = (usec / 4); /* XXX ??? */
1874
1875    bxe_storm_memset_hc_timeout(sc, port, fw_sb_id, sb_index, ticks);
1876
1877    disable = (disable) ? 1 : ((usec) ? 0 : 1);
1878    bxe_storm_memset_hc_disable(sc, port, fw_sb_id, sb_index, disable);
1879}
1880
1881void
1882elink_cb_udelay(struct bxe_softc *sc,
1883                uint32_t         usecs)
1884{
1885    DELAY(usecs);
1886}
1887
1888uint32_t
1889elink_cb_reg_read(struct bxe_softc *sc,
1890                  uint32_t         reg_addr)
1891{
1892    return (REG_RD(sc, reg_addr));
1893}
1894
1895void
1896elink_cb_reg_write(struct bxe_softc *sc,
1897                   uint32_t         reg_addr,
1898                   uint32_t         val)
1899{
1900    REG_WR(sc, reg_addr, val);
1901}
1902
1903void
1904elink_cb_reg_wb_write(struct bxe_softc *sc,
1905                      uint32_t         offset,
1906                      uint32_t         *wb_write,
1907                      uint16_t         len)
1908{
1909    REG_WR_DMAE(sc, offset, wb_write, len);
1910}
1911
1912void
1913elink_cb_reg_wb_read(struct bxe_softc *sc,
1914                     uint32_t         offset,
1915                     uint32_t         *wb_write,
1916                     uint16_t         len)
1917{
1918    REG_RD_DMAE(sc, offset, wb_write, len);
1919}
1920
1921uint8_t
1922elink_cb_path_id(struct bxe_softc *sc)
1923{
1924    return (SC_PATH(sc));
1925}
1926
1927void
1928elink_cb_event_log(struct bxe_softc     *sc,
1929                   const elink_log_id_t elink_log_id,
1930                   ...)
1931{
1932    /* XXX */
1933#if 0
1934    //va_list ap;
1935    va_start(ap, elink_log_id);
1936    _XXX_(sc, lm_log_id, ap);
1937    va_end(ap);
1938#endif
1939    BLOGI(sc, "ELINK EVENT LOG (%d)\n", elink_log_id);
1940}
1941
1942static int
1943bxe_set_spio(struct bxe_softc *sc,
1944             int              spio,
1945             uint32_t         mode)
1946{
1947    uint32_t spio_reg;
1948
1949    /* Only 2 SPIOs are configurable */
1950    if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
1951        BLOGE(sc, "Invalid SPIO 0x%x\n", spio);
1952        return (-1);
1953    }
1954
1955    bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
1956
1957    /* read SPIO and mask except the float bits */
1958    spio_reg = (REG_RD(sc, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
1959
1960    switch (mode) {
1961    case MISC_SPIO_OUTPUT_LOW:
1962        BLOGD(sc, DBG_LOAD, "Set SPIO 0x%x -> output low\n", spio);
1963        /* clear FLOAT and set CLR */
1964        spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
1965        spio_reg |=  (spio << MISC_SPIO_CLR_POS);
1966        break;
1967
1968    case MISC_SPIO_OUTPUT_HIGH:
1969        BLOGD(sc, DBG_LOAD, "Set SPIO 0x%x -> output high\n", spio);
1970        /* clear FLOAT and set SET */
1971        spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
1972        spio_reg |=  (spio << MISC_SPIO_SET_POS);
1973        break;
1974
1975    case MISC_SPIO_INPUT_HI_Z:
1976        BLOGD(sc, DBG_LOAD, "Set SPIO 0x%x -> input\n", spio);
1977        /* set FLOAT */
1978        spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
1979        break;
1980
1981    default:
1982        break;
1983    }
1984
1985    REG_WR(sc, MISC_REG_SPIO, spio_reg);
1986    bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
1987
1988    return (0);
1989}
1990
1991static int
1992bxe_gpio_read(struct bxe_softc *sc,
1993              int              gpio_num,
1994              uint8_t          port)
1995{
1996    /* The GPIO should be swapped if swap register is set and active */
1997    int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
1998                      REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
1999    int gpio_shift = (gpio_num +
2000                      (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0));
2001    uint32_t gpio_mask = (1 << gpio_shift);
2002    uint32_t gpio_reg;
2003
2004    if (gpio_num > MISC_REGISTERS_GPIO_3) {
2005        BLOGE(sc, "Invalid GPIO %d\n", gpio_num);
2006        return (-1);
2007    }
2008
2009    /* read GPIO value */
2010    gpio_reg = REG_RD(sc, MISC_REG_GPIO);
2011
2012    /* get the requested pin value */
2013    return ((gpio_reg & gpio_mask) == gpio_mask) ? 1 : 0;
2014}
2015
2016static int
2017bxe_gpio_write(struct bxe_softc *sc,
2018               int              gpio_num,
2019               uint32_t         mode,
2020               uint8_t          port)
2021{
2022    /* The GPIO should be swapped if swap register is set and active */
2023    int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
2024                      REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
2025    int gpio_shift = (gpio_num +
2026                      (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0));
2027    uint32_t gpio_mask = (1 << gpio_shift);
2028    uint32_t gpio_reg;
2029
2030    if (gpio_num > MISC_REGISTERS_GPIO_3) {
2031        BLOGE(sc, "Invalid GPIO %d\n", gpio_num);
2032        return (-1);
2033    }
2034
2035    bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
2036
2037    /* read GPIO and mask except the float bits */
2038    gpio_reg = (REG_RD(sc, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
2039
2040    switch (mode) {
2041    case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2042        BLOGD(sc, DBG_PHY,
2043              "Set GPIO %d (shift %d) -> output low\n",
2044              gpio_num, gpio_shift);
2045        /* clear FLOAT and set CLR */
2046        gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2047        gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
2048        break;
2049
2050    case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2051        BLOGD(sc, DBG_PHY,
2052              "Set GPIO %d (shift %d) -> output high\n",
2053              gpio_num, gpio_shift);
2054        /* clear FLOAT and set SET */
2055        gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2056        gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
2057        break;
2058
2059    case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2060        BLOGD(sc, DBG_PHY,
2061              "Set GPIO %d (shift %d) -> input\n",
2062              gpio_num, gpio_shift);
2063        /* set FLOAT */
2064        gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2065        break;
2066
2067    default:
2068        break;
2069    }
2070
2071    REG_WR(sc, MISC_REG_GPIO, gpio_reg);
2072    bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
2073
2074    return (0);
2075}
2076
2077static int
2078bxe_gpio_mult_write(struct bxe_softc *sc,
2079                    uint8_t          pins,
2080                    uint32_t         mode)
2081{
2082    uint32_t gpio_reg;
2083
2084    /* any port swapping should be handled by caller */
2085
2086    bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
2087
2088    /* read GPIO and mask except the float bits */
2089    gpio_reg = REG_RD(sc, MISC_REG_GPIO);
2090    gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2091    gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
2092    gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
2093
2094    switch (mode) {
2095    case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2096        BLOGD(sc, DBG_PHY, "Set GPIO 0x%x -> output low\n", pins);
2097        /* set CLR */
2098        gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2099        break;
2100
2101    case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2102        BLOGD(sc, DBG_PHY, "Set GPIO 0x%x -> output high\n", pins);
2103        /* set SET */
2104        gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2105        break;
2106
2107    case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2108        BLOGD(sc, DBG_PHY, "Set GPIO 0x%x -> input\n", pins);
2109        /* set FLOAT */
2110        gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2111        break;
2112
2113    default:
2114        BLOGE(sc, "Invalid GPIO mode assignment %d\n", mode);
2115        bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
2116        return (-1);
2117    }
2118
2119    REG_WR(sc, MISC_REG_GPIO, gpio_reg);
2120    bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
2121
2122    return (0);
2123}
2124
2125static int
2126bxe_gpio_int_write(struct bxe_softc *sc,
2127                   int              gpio_num,
2128                   uint32_t         mode,
2129                   uint8_t          port)
2130{
2131    /* The GPIO should be swapped if swap register is set and active */
2132    int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
2133                      REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
2134    int gpio_shift = (gpio_num +
2135                      (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0));
2136    uint32_t gpio_mask = (1 << gpio_shift);
2137    uint32_t gpio_reg;
2138
2139    if (gpio_num > MISC_REGISTERS_GPIO_3) {
2140        BLOGE(sc, "Invalid GPIO %d\n", gpio_num);
2141        return (-1);
2142    }
2143
2144    bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
2145
2146    /* read GPIO int */
2147    gpio_reg = REG_RD(sc, MISC_REG_GPIO_INT);
2148
2149    switch (mode) {
2150    case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2151        BLOGD(sc, DBG_PHY,
2152              "Clear GPIO INT %d (shift %d) -> output low\n",
2153              gpio_num, gpio_shift);
2154        /* clear SET and set CLR */
2155        gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2156        gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2157        break;
2158
2159    case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2160        BLOGD(sc, DBG_PHY,
2161              "Set GPIO INT %d (shift %d) -> output high\n",
2162              gpio_num, gpio_shift);
2163        /* clear CLR and set SET */
2164        gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2165        gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2166        break;
2167
2168    default:
2169        break;
2170    }
2171
2172    REG_WR(sc, MISC_REG_GPIO_INT, gpio_reg);
2173    bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
2174
2175    return (0);
2176}
2177
2178uint32_t
2179elink_cb_gpio_read(struct bxe_softc *sc,
2180                   uint16_t         gpio_num,
2181                   uint8_t          port)
2182{
2183    return (bxe_gpio_read(sc, gpio_num, port));
2184}
2185
2186uint8_t
2187elink_cb_gpio_write(struct bxe_softc *sc,
2188                    uint16_t         gpio_num,
2189                    uint8_t          mode, /* 0=low 1=high */
2190                    uint8_t          port)
2191{
2192    return (bxe_gpio_write(sc, gpio_num, mode, port));
2193}
2194
2195uint8_t
2196elink_cb_gpio_mult_write(struct bxe_softc *sc,
2197                         uint8_t          pins,
2198                         uint8_t          mode) /* 0=low 1=high */
2199{
2200    return (bxe_gpio_mult_write(sc, pins, mode));
2201}
2202
2203uint8_t
2204elink_cb_gpio_int_write(struct bxe_softc *sc,
2205                        uint16_t         gpio_num,
2206                        uint8_t          mode, /* 0=low 1=high */
2207                        uint8_t          port)
2208{
2209    return (bxe_gpio_int_write(sc, gpio_num, mode, port));
2210}
2211
2212void
2213elink_cb_notify_link_changed(struct bxe_softc *sc)
2214{
2215    REG_WR(sc, (MISC_REG_AEU_GENERAL_ATTN_12 +
2216                (SC_FUNC(sc) * sizeof(uint32_t))), 1);
2217}
2218
2219/* send the MCP a request, block until there is a reply */
2220uint32_t
2221elink_cb_fw_command(struct bxe_softc *sc,
2222                    uint32_t         command,
2223                    uint32_t         param)
2224{
2225    int mb_idx = SC_FW_MB_IDX(sc);
2226    uint32_t seq;
2227    uint32_t rc = 0;
2228    uint32_t cnt = 1;
2229    uint8_t delay = CHIP_REV_IS_SLOW(sc) ? 100 : 10;
2230
2231    BXE_FWMB_LOCK(sc);
2232
2233    seq = ++sc->fw_seq;
2234    SHMEM_WR(sc, func_mb[mb_idx].drv_mb_param, param);
2235    SHMEM_WR(sc, func_mb[mb_idx].drv_mb_header, (command | seq));
2236
2237    BLOGD(sc, DBG_PHY,
2238          "wrote command 0x%08x to FW MB param 0x%08x\n",
2239          (command | seq), param);
2240
2241    /* Let the FW do it's magic. GIve it up to 5 seconds... */
2242    do {
2243        DELAY(delay * 1000);
2244        rc = SHMEM_RD(sc, func_mb[mb_idx].fw_mb_header);
2245    } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2246
2247    BLOGD(sc, DBG_PHY,
2248          "[after %d ms] read 0x%x seq 0x%x from FW MB\n",
2249          cnt*delay, rc, seq);
2250
2251    /* is this a reply to our command? */
2252    if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) {
2253        rc &= FW_MSG_CODE_MASK;
2254    } else {
2255        /* Ruh-roh! */
2256        BLOGE(sc, "FW failed to respond!\n");
2257        // XXX bxe_fw_dump(sc);
2258        rc = 0;
2259    }
2260
2261    BXE_FWMB_UNLOCK(sc);
2262    return (rc);
2263}
2264
2265static uint32_t
2266bxe_fw_command(struct bxe_softc *sc,
2267               uint32_t         command,
2268               uint32_t         param)
2269{
2270    return (elink_cb_fw_command(sc, command, param));
2271}
2272
2273static void
2274__storm_memset_dma_mapping(struct bxe_softc *sc,
2275                           uint32_t         addr,
2276                           bus_addr_t       mapping)
2277{
2278    REG_WR(sc, addr, U64_LO(mapping));
2279    REG_WR(sc, (addr + 4), U64_HI(mapping));
2280}
2281
2282static void
2283storm_memset_spq_addr(struct bxe_softc *sc,
2284                      bus_addr_t       mapping,
2285                      uint16_t         abs_fid)
2286{
2287    uint32_t addr = (XSEM_REG_FAST_MEMORY +
2288                     XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid));
2289    __storm_memset_dma_mapping(sc, addr, mapping);
2290}
2291
2292static void
2293storm_memset_vf_to_pf(struct bxe_softc *sc,
2294                      uint16_t         abs_fid,
2295                      uint16_t         pf_id)
2296{
2297    REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid)), pf_id);
2298    REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid)), pf_id);
2299    REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid)), pf_id);
2300    REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid)), pf_id);
2301}
2302
2303static void
2304storm_memset_func_en(struct bxe_softc *sc,
2305                     uint16_t         abs_fid,
2306                     uint8_t          enable)
2307{
2308    REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid)), enable);
2309    REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid)), enable);
2310    REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid)), enable);
2311    REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid)), enable);
2312}
2313
2314static void
2315storm_memset_eq_data(struct bxe_softc       *sc,
2316                     struct event_ring_data *eq_data,
2317                     uint16_t               pfid)
2318{
2319    uint32_t addr;
2320    size_t size;
2321
2322    addr = (BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid));
2323    size = sizeof(struct event_ring_data);
2324    ecore_storm_memset_struct(sc, addr, size, (uint32_t *)eq_data);
2325}
2326
2327static void
2328storm_memset_eq_prod(struct bxe_softc *sc,
2329                     uint16_t         eq_prod,
2330                     uint16_t         pfid)
2331{
2332    uint32_t addr = (BAR_CSTRORM_INTMEM +
2333                     CSTORM_EVENT_RING_PROD_OFFSET(pfid));
2334    REG_WR16(sc, addr, eq_prod);
2335}
2336
2337/*
2338 * Post a slowpath command.
2339 *
2340 * A slowpath command is used to propogate a configuration change through
2341 * the controller in a controlled manner, allowing each STORM processor and
2342 * other H/W blocks to phase in the change.  The commands sent on the
2343 * slowpath are referred to as ramrods.  Depending on the ramrod used the
2344 * completion of the ramrod will occur in different ways.  Here's a
2345 * breakdown of ramrods and how they complete:
2346 *
2347 * RAMROD_CMD_ID_ETH_PORT_SETUP
2348 *   Used to setup the leading connection on a port.  Completes on the
2349 *   Receive Completion Queue (RCQ) of that port (typically fp[0]).
2350 *
2351 * RAMROD_CMD_ID_ETH_CLIENT_SETUP
2352 *   Used to setup an additional connection on a port.  Completes on the
2353 *   RCQ of the multi-queue/RSS connection being initialized.
2354 *
2355 * RAMROD_CMD_ID_ETH_STAT_QUERY
2356 *   Used to force the storm processors to update the statistics database
2357 *   in host memory.  This ramrod is send on the leading connection CID and
2358 *   completes as an index increment of the CSTORM on the default status
2359 *   block.
2360 *
2361 * RAMROD_CMD_ID_ETH_UPDATE
2362 *   Used to update the state of the leading connection, usually to udpate
2363 *   the RSS indirection table.  Completes on the RCQ of the leading
2364 *   connection. (Not currently used under FreeBSD until OS support becomes
2365 *   available.)
2366 *
2367 * RAMROD_CMD_ID_ETH_HALT
2368 *   Used when tearing down a connection prior to driver unload.  Completes
2369 *   on the RCQ of the multi-queue/RSS connection being torn down.  Don't
2370 *   use this on the leading connection.
2371 *
2372 * RAMROD_CMD_ID_ETH_SET_MAC
2373 *   Sets the Unicast/Broadcast/Multicast used by the port.  Completes on
2374 *   the RCQ of the leading connection.
2375 *
2376 * RAMROD_CMD_ID_ETH_CFC_DEL
2377 *   Used when tearing down a conneciton prior to driver unload.  Completes
2378 *   on the RCQ of the leading connection (since the current connection
2379 *   has been completely removed from controller memory).
2380 *
2381 * RAMROD_CMD_ID_ETH_PORT_DEL
2382 *   Used to tear down the leading connection prior to driver unload,
2383 *   typically fp[0].  Completes as an index increment of the CSTORM on the
2384 *   default status block.
2385 *
2386 * RAMROD_CMD_ID_ETH_FORWARD_SETUP
2387 *   Used for connection offload.  Completes on the RCQ of the multi-queue
2388 *   RSS connection that is being offloaded.  (Not currently used under
2389 *   FreeBSD.)
2390 *
2391 * There can only be one command pending per function.
2392 *
2393 * Returns:
2394 *   0 = Success, !0 = Failure.
2395 */
2396
2397/* must be called under the spq lock */
2398static inline
2399struct eth_spe *bxe_sp_get_next(struct bxe_softc *sc)
2400{
2401    struct eth_spe *next_spe = sc->spq_prod_bd;
2402
2403    if (sc->spq_prod_bd == sc->spq_last_bd) {
2404        /* wrap back to the first eth_spq */
2405        sc->spq_prod_bd = sc->spq;
2406        sc->spq_prod_idx = 0;
2407    } else {
2408        sc->spq_prod_bd++;
2409        sc->spq_prod_idx++;
2410    }
2411
2412    return (next_spe);
2413}
2414
2415/* must be called under the spq lock */
2416static inline
2417void bxe_sp_prod_update(struct bxe_softc *sc)
2418{
2419    int func = SC_FUNC(sc);
2420
2421    /*
2422     * Make sure that BD data is updated before writing the producer.
2423     * BD data is written to the memory, the producer is read from the
2424     * memory, thus we need a full memory barrier to ensure the ordering.
2425     */
2426    mb();
2427
2428    REG_WR16(sc, (BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func)),
2429             sc->spq_prod_idx);
2430
2431    bus_space_barrier(sc->bar[BAR0].tag, sc->bar[BAR0].handle, 0, 0,
2432                      BUS_SPACE_BARRIER_WRITE);
2433}
2434
2435/**
2436 * bxe_is_contextless_ramrod - check if the current command ends on EQ
2437 *
2438 * @cmd:      command to check
2439 * @cmd_type: command type
2440 */
2441static inline
2442int bxe_is_contextless_ramrod(int cmd,
2443                              int cmd_type)
2444{
2445    if ((cmd_type == NONE_CONNECTION_TYPE) ||
2446        (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
2447        (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
2448        (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
2449        (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
2450        (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
2451        (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) {
2452        return (TRUE);
2453    } else {
2454        return (FALSE);
2455    }
2456}
2457
2458/**
2459 * bxe_sp_post - place a single command on an SP ring
2460 *
2461 * @sc:         driver handle
2462 * @command:    command to place (e.g. SETUP, FILTER_RULES, etc.)
2463 * @cid:        SW CID the command is related to
2464 * @data_hi:    command private data address (high 32 bits)
2465 * @data_lo:    command private data address (low 32 bits)
2466 * @cmd_type:   command type (e.g. NONE, ETH)
2467 *
2468 * SP data is handled as if it's always an address pair, thus data fields are
2469 * not swapped to little endian in upper functions. Instead this function swaps
2470 * data as if it's two uint32 fields.
2471 */
2472int
2473bxe_sp_post(struct bxe_softc *sc,
2474            int              command,
2475            int              cid,
2476            uint32_t         data_hi,
2477            uint32_t         data_lo,
2478            int              cmd_type)
2479{
2480    struct eth_spe *spe;
2481    uint16_t type;
2482    int common;
2483
2484    common = bxe_is_contextless_ramrod(command, cmd_type);
2485
2486    BXE_SP_LOCK(sc);
2487
2488    if (common) {
2489        if (!atomic_load_acq_long(&sc->eq_spq_left)) {
2490            BLOGE(sc, "EQ ring is full!\n");
2491            BXE_SP_UNLOCK(sc);
2492            return (-1);
2493        }
2494    } else {
2495        if (!atomic_load_acq_long(&sc->cq_spq_left)) {
2496            BLOGE(sc, "SPQ ring is full!\n");
2497            BXE_SP_UNLOCK(sc);
2498            return (-1);
2499        }
2500    }
2501
2502    spe = bxe_sp_get_next(sc);
2503
2504    /* CID needs port number to be encoded int it */
2505    spe->hdr.conn_and_cmd_data =
2506        htole32((command << SPE_HDR_CMD_ID_SHIFT) | HW_CID(sc, cid));
2507
2508    type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
2509
2510    /* TBD: Check if it works for VFs */
2511    type |= ((SC_FUNC(sc) << SPE_HDR_FUNCTION_ID_SHIFT) &
2512             SPE_HDR_FUNCTION_ID);
2513
2514    spe->hdr.type = htole16(type);
2515
2516    spe->data.update_data_addr.hi = htole32(data_hi);
2517    spe->data.update_data_addr.lo = htole32(data_lo);
2518
2519    /*
2520     * It's ok if the actual decrement is issued towards the memory
2521     * somewhere between the lock and unlock. Thus no more explict
2522     * memory barrier is needed.
2523     */
2524    if (common) {
2525        atomic_subtract_acq_long(&sc->eq_spq_left, 1);
2526    } else {
2527        atomic_subtract_acq_long(&sc->cq_spq_left, 1);
2528    }
2529
2530    BLOGD(sc, DBG_SP, "SPQE -> %#jx\n", (uintmax_t)sc->spq_dma.paddr);
2531    BLOGD(sc, DBG_SP, "FUNC_RDATA -> %p / %#jx\n",
2532          BXE_SP(sc, func_rdata), (uintmax_t)BXE_SP_MAPPING(sc, func_rdata));
2533    BLOGD(sc, DBG_SP,
2534          "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) type(0x%x) left (CQ, EQ) (%lx,%lx)\n",
2535          sc->spq_prod_idx,
2536          (uint32_t)U64_HI(sc->spq_dma.paddr),
2537          (uint32_t)(U64_LO(sc->spq_dma.paddr) + (uint8_t *)sc->spq_prod_bd - (uint8_t *)sc->spq),
2538          command,
2539          common,
2540          HW_CID(sc, cid),
2541          data_hi,
2542          data_lo,
2543          type,
2544          atomic_load_acq_long(&sc->cq_spq_left),
2545          atomic_load_acq_long(&sc->eq_spq_left));
2546
2547    bxe_sp_prod_update(sc);
2548
2549    BXE_SP_UNLOCK(sc);
2550    return (0);
2551}
2552
2553/**
2554 * bxe_debug_print_ind_table - prints the indirection table configuration.
2555 *
2556 * @sc: driver hanlde
2557 * @p:  pointer to rss configuration
2558 */
2559#if 0
2560static void
2561bxe_debug_print_ind_table(struct bxe_softc               *sc,
2562                          struct ecore_config_rss_params *p)
2563{
2564    int i;
2565
2566    BLOGD(sc, DBG_LOAD, "Setting indirection table to:\n");
2567    BLOGD(sc, DBG_LOAD, "    0x0000: ");
2568    for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) {
2569        BLOGD(sc, DBG_LOAD, "0x%02x ", p->ind_table[i]);
2570
2571        /* Print 4 bytes in a line */
2572        if ((i + 1 < T_ETH_INDIRECTION_TABLE_SIZE) &&
2573            (((i + 1) & 0x3) == 0)) {
2574            BLOGD(sc, DBG_LOAD, "\n");
2575            BLOGD(sc, DBG_LOAD, "0x%04x: ", i + 1);
2576        }
2577    }
2578
2579    BLOGD(sc, DBG_LOAD, "\n");
2580}
2581#endif
2582
2583/*
2584 * FreeBSD Device probe function.
2585 *
2586 * Compares the device found to the driver's list of supported devices and
2587 * reports back to the bsd loader whether this is the right driver for the device.
2588 * This is the driver entry function called from the "kldload" command.
2589 *
2590 * Returns:
2591 *   BUS_PROBE_DEFAULT on success, positive value on failure.
2592 */
2593static int
2594bxe_probe(device_t dev)
2595{
2596    struct bxe_softc *sc;
2597    struct bxe_device_type *t;
2598    char *descbuf;
2599    uint16_t did, sdid, svid, vid;
2600
2601    /* Find our device structure */
2602    sc = device_get_softc(dev);
2603    sc->dev = dev;
2604    t = bxe_devs;
2605
2606    /* Get the data for the device to be probed. */
2607    vid  = pci_get_vendor(dev);
2608    did  = pci_get_device(dev);
2609    svid = pci_get_subvendor(dev);
2610    sdid = pci_get_subdevice(dev);
2611
2612    BLOGD(sc, DBG_LOAD,
2613          "%s(); VID = 0x%04X, DID = 0x%04X, SVID = 0x%04X, "
2614          "SDID = 0x%04X\n", __FUNCTION__, vid, did, svid, sdid);
2615
2616    /* Look through the list of known devices for a match. */
2617    while (t->bxe_name != NULL) {
2618        if ((vid == t->bxe_vid) && (did == t->bxe_did) &&
2619            ((svid == t->bxe_svid) || (t->bxe_svid == PCI_ANY_ID)) &&
2620            ((sdid == t->bxe_sdid) || (t->bxe_sdid == PCI_ANY_ID))) {
2621            descbuf = malloc(BXE_DEVDESC_MAX, M_TEMP, M_NOWAIT);
2622            if (descbuf == NULL)
2623                return (ENOMEM);
2624
2625            /* Print out the device identity. */
2626            snprintf(descbuf, BXE_DEVDESC_MAX,
2627                     "%s (%c%d) BXE v:%s\n", t->bxe_name,
2628                     (((pci_read_config(dev, PCIR_REVID, 4) &
2629                        0xf0) >> 4) + 'A'),
2630                     (pci_read_config(dev, PCIR_REVID, 4) & 0xf),
2631                     BXE_DRIVER_VERSION);
2632
2633            device_set_desc_copy(dev, descbuf);
2634            free(descbuf, M_TEMP);
2635            return (BUS_PROBE_DEFAULT);
2636        }
2637        t++;
2638    }
2639
2640    return (ENXIO);
2641}
2642
2643static void
2644bxe_init_mutexes(struct bxe_softc *sc)
2645{
2646#ifdef BXE_CORE_LOCK_SX
2647    snprintf(sc->core_sx_name, sizeof(sc->core_sx_name),
2648             "bxe%d_core_lock", sc->unit);
2649    sx_init(&sc->core_sx, sc->core_sx_name);
2650#else
2651    snprintf(sc->core_mtx_name, sizeof(sc->core_mtx_name),
2652             "bxe%d_core_lock", sc->unit);
2653    mtx_init(&sc->core_mtx, sc->core_mtx_name, NULL, MTX_DEF);
2654#endif
2655
2656    snprintf(sc->sp_mtx_name, sizeof(sc->sp_mtx_name),
2657             "bxe%d_sp_lock", sc->unit);
2658    mtx_init(&sc->sp_mtx, sc->sp_mtx_name, NULL, MTX_DEF);
2659
2660    snprintf(sc->dmae_mtx_name, sizeof(sc->dmae_mtx_name),
2661             "bxe%d_dmae_lock", sc->unit);
2662    mtx_init(&sc->dmae_mtx, sc->dmae_mtx_name, NULL, MTX_DEF);
2663
2664    snprintf(sc->port.phy_mtx_name, sizeof(sc->port.phy_mtx_name),
2665             "bxe%d_phy_lock", sc->unit);
2666    mtx_init(&sc->port.phy_mtx, sc->port.phy_mtx_name, NULL, MTX_DEF);
2667
2668    snprintf(sc->fwmb_mtx_name, sizeof(sc->fwmb_mtx_name),
2669             "bxe%d_fwmb_lock", sc->unit);
2670    mtx_init(&sc->fwmb_mtx, sc->fwmb_mtx_name, NULL, MTX_DEF);
2671
2672    snprintf(sc->print_mtx_name, sizeof(sc->print_mtx_name),
2673             "bxe%d_print_lock", sc->unit);
2674    mtx_init(&(sc->print_mtx), sc->print_mtx_name, NULL, MTX_DEF);
2675
2676    snprintf(sc->stats_mtx_name, sizeof(sc->stats_mtx_name),
2677             "bxe%d_stats_lock", sc->unit);
2678    mtx_init(&(sc->stats_mtx), sc->stats_mtx_name, NULL, MTX_DEF);
2679
2680    snprintf(sc->mcast_mtx_name, sizeof(sc->mcast_mtx_name),
2681             "bxe%d_mcast_lock", sc->unit);
2682    mtx_init(&(sc->mcast_mtx), sc->mcast_mtx_name, NULL, MTX_DEF);
2683}
2684
2685static void
2686bxe_release_mutexes(struct bxe_softc *sc)
2687{
2688#ifdef BXE_CORE_LOCK_SX
2689    sx_destroy(&sc->core_sx);
2690#else
2691    if (mtx_initialized(&sc->core_mtx)) {
2692        mtx_destroy(&sc->core_mtx);
2693    }
2694#endif
2695
2696    if (mtx_initialized(&sc->sp_mtx)) {
2697        mtx_destroy(&sc->sp_mtx);
2698    }
2699
2700    if (mtx_initialized(&sc->dmae_mtx)) {
2701        mtx_destroy(&sc->dmae_mtx);
2702    }
2703
2704    if (mtx_initialized(&sc->port.phy_mtx)) {
2705        mtx_destroy(&sc->port.phy_mtx);
2706    }
2707
2708    if (mtx_initialized(&sc->fwmb_mtx)) {
2709        mtx_destroy(&sc->fwmb_mtx);
2710    }
2711
2712    if (mtx_initialized(&sc->print_mtx)) {
2713        mtx_destroy(&sc->print_mtx);
2714    }
2715
2716    if (mtx_initialized(&sc->stats_mtx)) {
2717        mtx_destroy(&sc->stats_mtx);
2718    }
2719
2720    if (mtx_initialized(&sc->mcast_mtx)) {
2721        mtx_destroy(&sc->mcast_mtx);
2722    }
2723}
2724
2725static void
2726bxe_tx_disable(struct bxe_softc* sc)
2727{
2728    if_t ifp = sc->ifp;
2729
2730    /* tell the stack the driver is stopped and TX queue is full */
2731    if (ifp !=  NULL) {
2732        if_setdrvflags(ifp, 0);
2733    }
2734}
2735
2736static void
2737bxe_drv_pulse(struct bxe_softc *sc)
2738{
2739    SHMEM_WR(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb,
2740             sc->fw_drv_pulse_wr_seq);
2741}
2742
2743static inline uint16_t
2744bxe_tx_avail(struct bxe_softc *sc,
2745             struct bxe_fastpath *fp)
2746{
2747    int16_t  used;
2748    uint16_t prod;
2749    uint16_t cons;
2750
2751    prod = fp->tx_bd_prod;
2752    cons = fp->tx_bd_cons;
2753
2754    used = SUB_S16(prod, cons);
2755
2756#if 0
2757    KASSERT((used < 0), ("used tx bds < 0"));
2758    KASSERT((used > sc->tx_ring_size), ("used tx bds > tx_ring_size"));
2759    KASSERT(((sc->tx_ring_size - used) > MAX_TX_AVAIL),
2760            ("invalid number of tx bds used"));
2761#endif
2762
2763    return (int16_t)(sc->tx_ring_size) - used;
2764}
2765
2766static inline int
2767bxe_tx_queue_has_work(struct bxe_fastpath *fp)
2768{
2769    uint16_t hw_cons;
2770
2771    mb(); /* status block fields can change */
2772    hw_cons = le16toh(*fp->tx_cons_sb);
2773    return (hw_cons != fp->tx_pkt_cons);
2774}
2775
2776static inline uint8_t
2777bxe_has_tx_work(struct bxe_fastpath *fp)
2778{
2779    /* expand this for multi-cos if ever supported */
2780    return (bxe_tx_queue_has_work(fp)) ? TRUE : FALSE;
2781}
2782
2783static inline int
2784bxe_has_rx_work(struct bxe_fastpath *fp)
2785{
2786    uint16_t rx_cq_cons_sb;
2787
2788    mb(); /* status block fields can change */
2789    rx_cq_cons_sb = le16toh(*fp->rx_cq_cons_sb);
2790    if ((rx_cq_cons_sb & RCQ_MAX) == RCQ_MAX)
2791        rx_cq_cons_sb++;
2792    return (fp->rx_cq_cons != rx_cq_cons_sb);
2793}
2794
2795static void
2796bxe_sp_event(struct bxe_softc    *sc,
2797             struct bxe_fastpath *fp,
2798             union eth_rx_cqe    *rr_cqe)
2799{
2800    int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
2801    int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
2802    enum ecore_queue_cmd drv_cmd = ECORE_Q_CMD_MAX;
2803    struct ecore_queue_sp_obj *q_obj = &BXE_SP_OBJ(sc, fp).q_obj;
2804
2805    BLOGD(sc, DBG_SP, "fp=%d cid=%d got ramrod #%d state is %x type is %d\n",
2806          fp->index, cid, command, sc->state, rr_cqe->ramrod_cqe.ramrod_type);
2807
2808#if 0
2809    /*
2810     * If cid is within VF range, replace the slowpath object with the
2811     * one corresponding to this VF
2812     */
2813    if ((cid >= BXE_FIRST_VF_CID) && (cid < BXE_FIRST_VF_CID + BXE_VF_CIDS)) {
2814        bxe_iov_set_queue_sp_obj(sc, cid, &q_obj);
2815    }
2816#endif
2817
2818    switch (command) {
2819    case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
2820        BLOGD(sc, DBG_SP, "got UPDATE ramrod. CID %d\n", cid);
2821        drv_cmd = ECORE_Q_CMD_UPDATE;
2822        break;
2823
2824    case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
2825        BLOGD(sc, DBG_SP, "got MULTI[%d] setup ramrod\n", cid);
2826        drv_cmd = ECORE_Q_CMD_SETUP;
2827        break;
2828
2829    case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
2830        BLOGD(sc, DBG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
2831        drv_cmd = ECORE_Q_CMD_SETUP_TX_ONLY;
2832        break;
2833
2834    case (RAMROD_CMD_ID_ETH_HALT):
2835        BLOGD(sc, DBG_SP, "got MULTI[%d] halt ramrod\n", cid);
2836        drv_cmd = ECORE_Q_CMD_HALT;
2837        break;
2838
2839    case (RAMROD_CMD_ID_ETH_TERMINATE):
2840        BLOGD(sc, DBG_SP, "got MULTI[%d] teminate ramrod\n", cid);
2841        drv_cmd = ECORE_Q_CMD_TERMINATE;
2842        break;
2843
2844    case (RAMROD_CMD_ID_ETH_EMPTY):
2845        BLOGD(sc, DBG_SP, "got MULTI[%d] empty ramrod\n", cid);
2846        drv_cmd = ECORE_Q_CMD_EMPTY;
2847        break;
2848
2849    default:
2850        BLOGD(sc, DBG_SP, "ERROR: unexpected MC reply (%d) on fp[%d]\n",
2851              command, fp->index);
2852        return;
2853    }
2854
2855    if ((drv_cmd != ECORE_Q_CMD_MAX) &&
2856        q_obj->complete_cmd(sc, q_obj, drv_cmd)) {
2857        /*
2858         * q_obj->complete_cmd() failure means that this was
2859         * an unexpected completion.
2860         *
2861         * In this case we don't want to increase the sc->spq_left
2862         * because apparently we haven't sent this command the first
2863         * place.
2864         */
2865        // bxe_panic(sc, ("Unexpected SP completion\n"));
2866        return;
2867    }
2868
2869#if 0
2870    /* SRIOV: reschedule any 'in_progress' operations */
2871    bxe_iov_sp_event(sc, cid, TRUE);
2872#endif
2873
2874    atomic_add_acq_long(&sc->cq_spq_left, 1);
2875
2876    BLOGD(sc, DBG_SP, "sc->cq_spq_left 0x%lx\n",
2877          atomic_load_acq_long(&sc->cq_spq_left));
2878
2879#if 0
2880    if ((drv_cmd == ECORE_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) &&
2881        (!!bxe_test_bit(ECORE_AFEX_FCOE_Q_UPDATE_PENDING, &sc->sp_state))) {
2882        /*
2883         * If Queue update ramrod is completed for last Queue in AFEX VIF set
2884         * flow, then ACK MCP at the end. Mark pending ACK to MCP bit to
2885         * prevent case that both bits are cleared. At the end of load/unload
2886         * driver checks that sp_state is cleared and this order prevents
2887         * races.
2888         */
2889        bxe_set_bit(ECORE_AFEX_PENDING_VIFSET_MCP_ACK, &sc->sp_state);
2890        wmb();
2891        bxe_clear_bit(ECORE_AFEX_FCOE_Q_UPDATE_PENDING, &sc->sp_state);
2892
2893        /* schedule the sp task as MCP ack is required */
2894        bxe_schedule_sp_task(sc);
2895    }
2896#endif
2897}
2898
2899/*
2900 * The current mbuf is part of an aggregation. Move the mbuf into the TPA
2901 * aggregation queue, put an empty mbuf back onto the receive chain, and mark
2902 * the current aggregation queue as in-progress.
2903 */
2904static void
2905bxe_tpa_start(struct bxe_softc            *sc,
2906              struct bxe_fastpath         *fp,
2907              uint16_t                    queue,
2908              uint16_t                    cons,
2909              uint16_t                    prod,
2910              struct eth_fast_path_rx_cqe *cqe)
2911{
2912    struct bxe_sw_rx_bd tmp_bd;
2913    struct bxe_sw_rx_bd *rx_buf;
2914    struct eth_rx_bd *rx_bd;
2915    int max_agg_queues;
2916    struct bxe_sw_tpa_info *tpa_info = &fp->rx_tpa_info[queue];
2917    uint16_t index;
2918
2919    BLOGD(sc, DBG_LRO, "fp[%02d].tpa[%02d] TPA START "
2920                       "cons=%d prod=%d\n",
2921          fp->index, queue, cons, prod);
2922
2923    max_agg_queues = MAX_AGG_QS(sc);
2924
2925    KASSERT((queue < max_agg_queues),
2926            ("fp[%02d] invalid aggr queue (%d >= %d)!",
2927             fp->index, queue, max_agg_queues));
2928
2929    KASSERT((tpa_info->state == BXE_TPA_STATE_STOP),
2930            ("fp[%02d].tpa[%02d] starting aggr on queue not stopped!",
2931             fp->index, queue));
2932
2933    /* copy the existing mbuf and mapping from the TPA pool */
2934    tmp_bd = tpa_info->bd;
2935
2936    if (tmp_bd.m == NULL) {
2937        BLOGE(sc, "fp[%02d].tpa[%02d] mbuf not allocated!\n",
2938              fp->index, queue);
2939        /* XXX Error handling? */
2940        return;
2941    }
2942
2943    /* change the TPA queue to the start state */
2944    tpa_info->state            = BXE_TPA_STATE_START;
2945    tpa_info->placement_offset = cqe->placement_offset;
2946    tpa_info->parsing_flags    = le16toh(cqe->pars_flags.flags);
2947    tpa_info->vlan_tag         = le16toh(cqe->vlan_tag);
2948    tpa_info->len_on_bd        = le16toh(cqe->len_on_bd);
2949
2950    fp->rx_tpa_queue_used |= (1 << queue);
2951
2952    /*
2953     * If all the buffer descriptors are filled with mbufs then fill in
2954     * the current consumer index with a new BD. Else if a maximum Rx
2955     * buffer limit is imposed then fill in the next producer index.
2956     */
2957    index = (sc->max_rx_bufs != RX_BD_USABLE) ?
2958                prod : cons;
2959
2960    /* move the received mbuf and mapping to TPA pool */
2961    tpa_info->bd = fp->rx_mbuf_chain[cons];
2962
2963    /* release any existing RX BD mbuf mappings */
2964    if (cons != index) {
2965        rx_buf = &fp->rx_mbuf_chain[cons];
2966
2967        if (rx_buf->m_map != NULL) {
2968            bus_dmamap_sync(fp->rx_mbuf_tag, rx_buf->m_map,
2969                            BUS_DMASYNC_POSTREAD);
2970            bus_dmamap_unload(fp->rx_mbuf_tag, rx_buf->m_map);
2971        }
2972
2973        /*
2974         * We get here when the maximum number of rx buffers is less than
2975         * RX_BD_USABLE. The mbuf is already saved above so it's OK to NULL
2976         * it out here without concern of a memory leak.
2977         */
2978        fp->rx_mbuf_chain[cons].m = NULL;
2979    }
2980
2981    /* update the Rx SW BD with the mbuf info from the TPA pool */
2982    fp->rx_mbuf_chain[index] = tmp_bd;
2983
2984    /* update the Rx BD with the empty mbuf phys address from the TPA pool */
2985    rx_bd = &fp->rx_chain[index];
2986    rx_bd->addr_hi = htole32(U64_HI(tpa_info->seg.ds_addr));
2987    rx_bd->addr_lo = htole32(U64_LO(tpa_info->seg.ds_addr));
2988}
2989
2990/*
2991 * When a TPA aggregation is completed, loop through the individual mbufs
2992 * of the aggregation, combining them into a single mbuf which will be sent
2993 * up the stack. Refill all freed SGEs with mbufs as we go along.
2994 */
2995static int
2996bxe_fill_frag_mbuf(struct bxe_softc          *sc,
2997                   struct bxe_fastpath       *fp,
2998                   struct bxe_sw_tpa_info    *tpa_info,
2999                   uint16_t                  queue,
3000                   uint16_t                  pages,
3001                   struct mbuf               *m,
3002			       struct eth_end_agg_rx_cqe *cqe,
3003                   uint16_t                  cqe_idx)
3004{
3005    struct mbuf *m_frag;
3006    uint32_t frag_len, frag_size, i;
3007    uint16_t sge_idx;
3008    int rc = 0;
3009    int j;
3010
3011    frag_size = le16toh(cqe->pkt_len) - tpa_info->len_on_bd;
3012
3013    BLOGD(sc, DBG_LRO,
3014          "fp[%02d].tpa[%02d] TPA fill len_on_bd=%d frag_size=%d pages=%d\n",
3015          fp->index, queue, tpa_info->len_on_bd, frag_size, pages);
3016
3017    /* make sure the aggregated frame is not too big to handle */
3018    if (pages > 8 * PAGES_PER_SGE) {
3019        BLOGE(sc, "fp[%02d].sge[0x%04x] has too many pages (%d)! "
3020                  "pkt_len=%d len_on_bd=%d frag_size=%d\n",
3021              fp->index, cqe_idx, pages, le16toh(cqe->pkt_len),
3022              tpa_info->len_on_bd, frag_size);
3023        bxe_panic(sc, ("sge page count error\n"));
3024        return (EINVAL);
3025    }
3026
3027    /*
3028     * Scan through the scatter gather list pulling individual mbufs into a
3029     * single mbuf for the host stack.
3030     */
3031    for (i = 0, j = 0; i < pages; i += PAGES_PER_SGE, j++) {
3032        sge_idx = RX_SGE(le16toh(cqe->sgl_or_raw_data.sgl[j]));
3033
3034        /*
3035         * Firmware gives the indices of the SGE as if the ring is an array
3036         * (meaning that the "next" element will consume 2 indices).
3037         */
3038        frag_len = min(frag_size, (uint32_t)(SGE_PAGES));
3039
3040        BLOGD(sc, DBG_LRO, "fp[%02d].tpa[%02d] TPA fill i=%d j=%d "
3041                           "sge_idx=%d frag_size=%d frag_len=%d\n",
3042              fp->index, queue, i, j, sge_idx, frag_size, frag_len);
3043
3044        m_frag = fp->rx_sge_mbuf_chain[sge_idx].m;
3045
3046        /* allocate a new mbuf for the SGE */
3047        rc = bxe_alloc_rx_sge_mbuf(fp, sge_idx);
3048        if (rc) {
3049            /* Leave all remaining SGEs in the ring! */
3050            return (rc);
3051        }
3052
3053        /* update the fragment length */
3054        m_frag->m_len = frag_len;
3055
3056        /* concatenate the fragment to the head mbuf */
3057        m_cat(m, m_frag);
3058        fp->eth_q_stats.mbuf_alloc_sge--;
3059
3060        /* update the TPA mbuf size and remaining fragment size */
3061        m->m_pkthdr.len += frag_len;
3062        frag_size -= frag_len;
3063    }
3064
3065    BLOGD(sc, DBG_LRO,
3066          "fp[%02d].tpa[%02d] TPA fill done frag_size=%d\n",
3067          fp->index, queue, frag_size);
3068
3069    return (rc);
3070}
3071
3072static inline void
3073bxe_clear_sge_mask_next_elems(struct bxe_fastpath *fp)
3074{
3075    int i, j;
3076
3077    for (i = 1; i <= RX_SGE_NUM_PAGES; i++) {
3078        int idx = RX_SGE_TOTAL_PER_PAGE * i - 1;
3079
3080        for (j = 0; j < 2; j++) {
3081            BIT_VEC64_CLEAR_BIT(fp->sge_mask, idx);
3082            idx--;
3083        }
3084    }
3085}
3086
3087static inline void
3088bxe_init_sge_ring_bit_mask(struct bxe_fastpath *fp)
3089{
3090    /* set the mask to all 1's, it's faster to compare to 0 than to 0xf's */
3091    memset(fp->sge_mask, 0xff, sizeof(fp->sge_mask));
3092
3093    /*
3094     * Clear the two last indices in the page to 1. These are the indices that
3095     * correspond to the "next" element, hence will never be indicated and
3096     * should be removed from the calculations.
3097     */
3098    bxe_clear_sge_mask_next_elems(fp);
3099}
3100
3101static inline void
3102bxe_update_last_max_sge(struct bxe_fastpath *fp,
3103                        uint16_t            idx)
3104{
3105    uint16_t last_max = fp->last_max_sge;
3106
3107    if (SUB_S16(idx, last_max) > 0) {
3108        fp->last_max_sge = idx;
3109    }
3110}
3111
3112static inline void
3113bxe_update_sge_prod(struct bxe_softc          *sc,
3114                    struct bxe_fastpath       *fp,
3115                    uint16_t                  sge_len,
3116                    union eth_sgl_or_raw_data *cqe)
3117{
3118    uint16_t last_max, last_elem, first_elem;
3119    uint16_t delta = 0;
3120    uint16_t i;
3121
3122    if (!sge_len) {
3123        return;
3124    }
3125
3126    /* first mark all used pages */
3127    for (i = 0; i < sge_len; i++) {
3128        BIT_VEC64_CLEAR_BIT(fp->sge_mask,
3129                            RX_SGE(le16toh(cqe->sgl[i])));
3130    }
3131
3132    BLOGD(sc, DBG_LRO,
3133          "fp[%02d] fp_cqe->sgl[%d] = %d\n",
3134          fp->index, sge_len - 1,
3135          le16toh(cqe->sgl[sge_len - 1]));
3136
3137    /* assume that the last SGE index is the biggest */
3138    bxe_update_last_max_sge(fp,
3139                            le16toh(cqe->sgl[sge_len - 1]));
3140
3141    last_max = RX_SGE(fp->last_max_sge);
3142    last_elem = last_max >> BIT_VEC64_ELEM_SHIFT;
3143    first_elem = RX_SGE(fp->rx_sge_prod) >> BIT_VEC64_ELEM_SHIFT;
3144
3145    /* if ring is not full */
3146    if (last_elem + 1 != first_elem) {
3147        last_elem++;
3148    }
3149
3150    /* now update the prod */
3151    for (i = first_elem; i != last_elem; i = RX_SGE_NEXT_MASK_ELEM(i)) {
3152        if (__predict_true(fp->sge_mask[i])) {
3153            break;
3154        }
3155
3156        fp->sge_mask[i] = BIT_VEC64_ELEM_ONE_MASK;
3157        delta += BIT_VEC64_ELEM_SZ;
3158    }
3159
3160    if (delta > 0) {
3161        fp->rx_sge_prod += delta;
3162        /* clear page-end entries */
3163        bxe_clear_sge_mask_next_elems(fp);
3164    }
3165
3166    BLOGD(sc, DBG_LRO,
3167          "fp[%02d] fp->last_max_sge=%d fp->rx_sge_prod=%d\n",
3168          fp->index, fp->last_max_sge, fp->rx_sge_prod);
3169}
3170
3171/*
3172 * The aggregation on the current TPA queue has completed. Pull the individual
3173 * mbuf fragments together into a single mbuf, perform all necessary checksum
3174 * calculations, and send the resuting mbuf to the stack.
3175 */
3176static void
3177bxe_tpa_stop(struct bxe_softc          *sc,
3178             struct bxe_fastpath       *fp,
3179             struct bxe_sw_tpa_info    *tpa_info,
3180             uint16_t                  queue,
3181             uint16_t                  pages,
3182			 struct eth_end_agg_rx_cqe *cqe,
3183             uint16_t                  cqe_idx)
3184{
3185    if_t ifp = sc->ifp;
3186    struct mbuf *m;
3187    int rc = 0;
3188
3189    BLOGD(sc, DBG_LRO,
3190          "fp[%02d].tpa[%02d] pad=%d pkt_len=%d pages=%d vlan=%d\n",
3191          fp->index, queue, tpa_info->placement_offset,
3192          le16toh(cqe->pkt_len), pages, tpa_info->vlan_tag);
3193
3194    m = tpa_info->bd.m;
3195
3196    /* allocate a replacement before modifying existing mbuf */
3197    rc = bxe_alloc_rx_tpa_mbuf(fp, queue);
3198    if (rc) {
3199        /* drop the frame and log an error */
3200        fp->eth_q_stats.rx_soft_errors++;
3201        goto bxe_tpa_stop_exit;
3202    }
3203
3204    /* we have a replacement, fixup the current mbuf */
3205    m_adj(m, tpa_info->placement_offset);
3206    m->m_pkthdr.len = m->m_len = tpa_info->len_on_bd;
3207
3208    /* mark the checksums valid (taken care of by the firmware) */
3209    fp->eth_q_stats.rx_ofld_frames_csum_ip++;
3210    fp->eth_q_stats.rx_ofld_frames_csum_tcp_udp++;
3211    m->m_pkthdr.csum_data = 0xffff;
3212    m->m_pkthdr.csum_flags |= (CSUM_IP_CHECKED |
3213                               CSUM_IP_VALID   |
3214                               CSUM_DATA_VALID |
3215                               CSUM_PSEUDO_HDR);
3216
3217    /* aggregate all of the SGEs into a single mbuf */
3218    rc = bxe_fill_frag_mbuf(sc, fp, tpa_info, queue, pages, m, cqe, cqe_idx);
3219    if (rc) {
3220        /* drop the packet and log an error */
3221        fp->eth_q_stats.rx_soft_errors++;
3222        m_freem(m);
3223    } else {
3224        if (tpa_info->parsing_flags & PARSING_FLAGS_VLAN) {
3225            m->m_pkthdr.ether_vtag = tpa_info->vlan_tag;
3226            m->m_flags |= M_VLANTAG;
3227        }
3228
3229        /* assign packet to this interface interface */
3230        if_setrcvif(m, ifp);
3231
3232#if __FreeBSD_version >= 800000
3233        /* specify what RSS queue was used for this flow */
3234        m->m_pkthdr.flowid = fp->index;
3235        M_HASHTYPE_SET(m, M_HASHTYPE_OPAQUE);
3236#endif
3237
3238        if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
3239        fp->eth_q_stats.rx_tpa_pkts++;
3240
3241        /* pass the frame to the stack */
3242        if_input(ifp, m);
3243    }
3244
3245    /* we passed an mbuf up the stack or dropped the frame */
3246    fp->eth_q_stats.mbuf_alloc_tpa--;
3247
3248bxe_tpa_stop_exit:
3249
3250    fp->rx_tpa_info[queue].state = BXE_TPA_STATE_STOP;
3251    fp->rx_tpa_queue_used &= ~(1 << queue);
3252}
3253
3254static uint8_t
3255bxe_service_rxsgl(
3256                 struct bxe_fastpath *fp,
3257                 uint16_t len,
3258                 uint16_t lenonbd,
3259                 struct mbuf *m,
3260                 struct eth_fast_path_rx_cqe *cqe_fp)
3261{
3262    struct mbuf *m_frag;
3263    uint16_t frags, frag_len;
3264    uint16_t sge_idx = 0;
3265    uint16_t j;
3266    uint8_t i, rc = 0;
3267    uint32_t frag_size;
3268
3269    /* adjust the mbuf */
3270    m->m_len = lenonbd;
3271
3272    frag_size =  len - lenonbd;
3273    frags = SGE_PAGE_ALIGN(frag_size) >> SGE_PAGE_SHIFT;
3274
3275    for (i = 0, j = 0; i < frags; i += PAGES_PER_SGE, j++) {
3276        sge_idx = RX_SGE(le16toh(cqe_fp->sgl_or_raw_data.sgl[j]));
3277
3278        m_frag = fp->rx_sge_mbuf_chain[sge_idx].m;
3279        frag_len = min(frag_size, (uint32_t)(SGE_PAGE_SIZE));
3280        m_frag->m_len = frag_len;
3281
3282       /* allocate a new mbuf for the SGE */
3283        rc = bxe_alloc_rx_sge_mbuf(fp, sge_idx);
3284        if (rc) {
3285            /* Leave all remaining SGEs in the ring! */
3286            return (rc);
3287        }
3288        fp->eth_q_stats.mbuf_alloc_sge--;
3289
3290        /* concatenate the fragment to the head mbuf */
3291        m_cat(m, m_frag);
3292
3293        frag_size -= frag_len;
3294    }
3295
3296    bxe_update_sge_prod(fp->sc, fp, frags, &cqe_fp->sgl_or_raw_data);
3297
3298    return rc;
3299}
3300
3301static uint8_t
3302bxe_rxeof(struct bxe_softc    *sc,
3303          struct bxe_fastpath *fp)
3304{
3305    if_t ifp = sc->ifp;
3306    uint16_t bd_cons, bd_prod, bd_prod_fw, comp_ring_cons;
3307    uint16_t hw_cq_cons, sw_cq_cons, sw_cq_prod;
3308    int rx_pkts = 0;
3309    int rc = 0;
3310
3311    BXE_FP_RX_LOCK(fp);
3312
3313    /* CQ "next element" is of the size of the regular element */
3314    hw_cq_cons = le16toh(*fp->rx_cq_cons_sb);
3315    if ((hw_cq_cons & RCQ_USABLE_PER_PAGE) == RCQ_USABLE_PER_PAGE) {
3316        hw_cq_cons++;
3317    }
3318
3319    bd_cons = fp->rx_bd_cons;
3320    bd_prod = fp->rx_bd_prod;
3321    bd_prod_fw = bd_prod;
3322    sw_cq_cons = fp->rx_cq_cons;
3323    sw_cq_prod = fp->rx_cq_prod;
3324
3325    /*
3326     * Memory barrier necessary as speculative reads of the rx
3327     * buffer can be ahead of the index in the status block
3328     */
3329    rmb();
3330
3331    BLOGD(sc, DBG_RX,
3332          "fp[%02d] Rx START hw_cq_cons=%u sw_cq_cons=%u\n",
3333          fp->index, hw_cq_cons, sw_cq_cons);
3334
3335    while (sw_cq_cons != hw_cq_cons) {
3336        struct bxe_sw_rx_bd *rx_buf = NULL;
3337        union eth_rx_cqe *cqe;
3338        struct eth_fast_path_rx_cqe *cqe_fp;
3339        uint8_t cqe_fp_flags;
3340        enum eth_rx_cqe_type cqe_fp_type;
3341        uint16_t len, lenonbd,  pad;
3342        struct mbuf *m = NULL;
3343
3344        comp_ring_cons = RCQ(sw_cq_cons);
3345        bd_prod = RX_BD(bd_prod);
3346        bd_cons = RX_BD(bd_cons);
3347
3348        cqe          = &fp->rcq_chain[comp_ring_cons];
3349        cqe_fp       = &cqe->fast_path_cqe;
3350        cqe_fp_flags = cqe_fp->type_error_flags;
3351        cqe_fp_type  = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
3352
3353        BLOGD(sc, DBG_RX,
3354              "fp[%02d] Rx hw_cq_cons=%d hw_sw_cons=%d "
3355              "BD prod=%d cons=%d CQE type=0x%x err=0x%x "
3356              "status=0x%x rss_hash=0x%x vlan=0x%x len=%u lenonbd=%u\n",
3357              fp->index,
3358              hw_cq_cons,
3359              sw_cq_cons,
3360              bd_prod,
3361              bd_cons,
3362              CQE_TYPE(cqe_fp_flags),
3363              cqe_fp_flags,
3364              cqe_fp->status_flags,
3365              le32toh(cqe_fp->rss_hash_result),
3366              le16toh(cqe_fp->vlan_tag),
3367              le16toh(cqe_fp->pkt_len_or_gro_seg_len),
3368              le16toh(cqe_fp->len_on_bd));
3369
3370        /* is this a slowpath msg? */
3371        if (__predict_false(CQE_TYPE_SLOW(cqe_fp_type))) {
3372            bxe_sp_event(sc, fp, cqe);
3373            goto next_cqe;
3374        }
3375
3376        rx_buf = &fp->rx_mbuf_chain[bd_cons];
3377
3378        if (!CQE_TYPE_FAST(cqe_fp_type)) {
3379            struct bxe_sw_tpa_info *tpa_info;
3380            uint16_t frag_size, pages;
3381            uint8_t queue;
3382
3383#if 0
3384            /* sanity check */
3385            if (!fp->tpa_enable &&
3386                (CQE_TYPE_START(cqe_fp_type) || CQE_TYPE_STOP(cqe_fp_type))) {
3387                BLOGE(sc, "START/STOP packet while !tpa_enable type (0x%x)\n",
3388                      CQE_TYPE(cqe_fp_type));
3389            }
3390#endif
3391
3392            if (CQE_TYPE_START(cqe_fp_type)) {
3393                bxe_tpa_start(sc, fp, cqe_fp->queue_index,
3394                              bd_cons, bd_prod, cqe_fp);
3395                m = NULL; /* packet not ready yet */
3396                goto next_rx;
3397            }
3398
3399            KASSERT(CQE_TYPE_STOP(cqe_fp_type),
3400                    ("CQE type is not STOP! (0x%x)\n", cqe_fp_type));
3401
3402            queue = cqe->end_agg_cqe.queue_index;
3403            tpa_info = &fp->rx_tpa_info[queue];
3404
3405            BLOGD(sc, DBG_LRO, "fp[%02d].tpa[%02d] TPA STOP\n",
3406                  fp->index, queue);
3407
3408            frag_size = (le16toh(cqe->end_agg_cqe.pkt_len) -
3409                         tpa_info->len_on_bd);
3410            pages = SGE_PAGE_ALIGN(frag_size) >> SGE_PAGE_SHIFT;
3411
3412            bxe_tpa_stop(sc, fp, tpa_info, queue, pages,
3413                         &cqe->end_agg_cqe, comp_ring_cons);
3414
3415            bxe_update_sge_prod(sc, fp, pages, &cqe->end_agg_cqe.sgl_or_raw_data);
3416
3417            goto next_cqe;
3418        }
3419
3420        /* non TPA */
3421
3422        /* is this an error packet? */
3423        if (__predict_false(cqe_fp_flags &
3424                            ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG)) {
3425            BLOGE(sc, "flags 0x%x rx packet %u\n", cqe_fp_flags, sw_cq_cons);
3426            fp->eth_q_stats.rx_soft_errors++;
3427            goto next_rx;
3428        }
3429
3430        len = le16toh(cqe_fp->pkt_len_or_gro_seg_len);
3431        lenonbd = le16toh(cqe_fp->len_on_bd);
3432        pad = cqe_fp->placement_offset;
3433
3434        m = rx_buf->m;
3435
3436        if (__predict_false(m == NULL)) {
3437            BLOGE(sc, "No mbuf in rx chain descriptor %d for fp[%02d]\n",
3438                  bd_cons, fp->index);
3439            goto next_rx;
3440        }
3441
3442        /* XXX double copy if packet length under a threshold */
3443
3444        /*
3445         * If all the buffer descriptors are filled with mbufs then fill in
3446         * the current consumer index with a new BD. Else if a maximum Rx
3447         * buffer limit is imposed then fill in the next producer index.
3448         */
3449        rc = bxe_alloc_rx_bd_mbuf(fp, bd_cons,
3450                                  (sc->max_rx_bufs != RX_BD_USABLE) ?
3451                                      bd_prod : bd_cons);
3452        if (rc != 0) {
3453
3454            /* we simply reuse the received mbuf and don't post it to the stack */
3455            m = NULL;
3456
3457            BLOGE(sc, "mbuf alloc fail for fp[%02d] rx chain (%d)\n",
3458                  fp->index, rc);
3459            fp->eth_q_stats.rx_soft_errors++;
3460
3461            if (sc->max_rx_bufs != RX_BD_USABLE) {
3462                /* copy this consumer index to the producer index */
3463                memcpy(&fp->rx_mbuf_chain[bd_prod], rx_buf,
3464                       sizeof(struct bxe_sw_rx_bd));
3465                memset(rx_buf, 0, sizeof(struct bxe_sw_rx_bd));
3466            }
3467
3468            goto next_rx;
3469        }
3470
3471        /* current mbuf was detached from the bd */
3472        fp->eth_q_stats.mbuf_alloc_rx--;
3473
3474        /* we allocated a replacement mbuf, fixup the current one */
3475        m_adj(m, pad);
3476        m->m_pkthdr.len = m->m_len = len;
3477
3478        if (len != lenonbd){
3479            rc = bxe_service_rxsgl(fp, len, lenonbd, m, cqe_fp);
3480            if (rc)
3481                break;
3482            fp->eth_q_stats.rx_jumbo_sge_pkts++;
3483        }
3484
3485        /* assign packet to this interface interface */
3486	if_setrcvif(m, ifp);
3487
3488        /* assume no hardware checksum has complated */
3489        m->m_pkthdr.csum_flags = 0;
3490
3491        /* validate checksum if offload enabled */
3492        if (if_getcapenable(ifp) & IFCAP_RXCSUM) {
3493            /* check for a valid IP frame */
3494            if (!(cqe->fast_path_cqe.status_flags &
3495                  ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG)) {
3496                m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
3497                if (__predict_false(cqe_fp_flags &
3498                                    ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG)) {
3499                    fp->eth_q_stats.rx_hw_csum_errors++;
3500                } else {
3501                    fp->eth_q_stats.rx_ofld_frames_csum_ip++;
3502                    m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
3503                }
3504            }
3505
3506            /* check for a valid TCP/UDP frame */
3507            if (!(cqe->fast_path_cqe.status_flags &
3508                  ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG)) {
3509                if (__predict_false(cqe_fp_flags &
3510                                    ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG)) {
3511                    fp->eth_q_stats.rx_hw_csum_errors++;
3512                } else {
3513                    fp->eth_q_stats.rx_ofld_frames_csum_tcp_udp++;
3514                    m->m_pkthdr.csum_data = 0xFFFF;
3515                    m->m_pkthdr.csum_flags |= (CSUM_DATA_VALID |
3516                                               CSUM_PSEUDO_HDR);
3517                }
3518            }
3519        }
3520
3521        /* if there is a VLAN tag then flag that info */
3522        if (cqe->fast_path_cqe.pars_flags.flags & PARSING_FLAGS_VLAN) {
3523            m->m_pkthdr.ether_vtag = cqe->fast_path_cqe.vlan_tag;
3524            m->m_flags |= M_VLANTAG;
3525        }
3526
3527#if __FreeBSD_version >= 800000
3528        /* specify what RSS queue was used for this flow */
3529        m->m_pkthdr.flowid = fp->index;
3530        M_HASHTYPE_SET(m, M_HASHTYPE_OPAQUE);
3531#endif
3532
3533next_rx:
3534
3535        bd_cons    = RX_BD_NEXT(bd_cons);
3536        bd_prod    = RX_BD_NEXT(bd_prod);
3537        bd_prod_fw = RX_BD_NEXT(bd_prod_fw);
3538
3539        /* pass the frame to the stack */
3540        if (__predict_true(m != NULL)) {
3541            if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
3542            rx_pkts++;
3543            if_input(ifp, m);
3544        }
3545
3546next_cqe:
3547
3548        sw_cq_prod = RCQ_NEXT(sw_cq_prod);
3549        sw_cq_cons = RCQ_NEXT(sw_cq_cons);
3550
3551        /* limit spinning on the queue */
3552        if (rc != 0)
3553            break;
3554
3555        if (rx_pkts == sc->rx_budget) {
3556            fp->eth_q_stats.rx_budget_reached++;
3557            break;
3558        }
3559    } /* while work to do */
3560
3561    fp->rx_bd_cons = bd_cons;
3562    fp->rx_bd_prod = bd_prod_fw;
3563    fp->rx_cq_cons = sw_cq_cons;
3564    fp->rx_cq_prod = sw_cq_prod;
3565
3566    /* Update producers */
3567    bxe_update_rx_prod(sc, fp, bd_prod_fw, sw_cq_prod, fp->rx_sge_prod);
3568
3569    fp->eth_q_stats.rx_pkts += rx_pkts;
3570    fp->eth_q_stats.rx_calls++;
3571
3572    BXE_FP_RX_UNLOCK(fp);
3573
3574    return (sw_cq_cons != hw_cq_cons);
3575}
3576
3577static uint16_t
3578bxe_free_tx_pkt(struct bxe_softc    *sc,
3579                struct bxe_fastpath *fp,
3580                uint16_t            idx)
3581{
3582    struct bxe_sw_tx_bd *tx_buf = &fp->tx_mbuf_chain[idx];
3583    struct eth_tx_start_bd *tx_start_bd;
3584    uint16_t bd_idx = TX_BD(tx_buf->first_bd);
3585    uint16_t new_cons;
3586    int nbd;
3587
3588    /* unmap the mbuf from non-paged memory */
3589    bus_dmamap_unload(fp->tx_mbuf_tag, tx_buf->m_map);
3590
3591    tx_start_bd = &fp->tx_chain[bd_idx].start_bd;
3592    nbd = le16toh(tx_start_bd->nbd) - 1;
3593
3594#if 0
3595    if ((nbd - 1) > (MAX_MBUF_FRAGS + 2)) {
3596        bxe_panic(sc, ("BAD nbd!\n"));
3597    }
3598#endif
3599
3600    new_cons = (tx_buf->first_bd + nbd);
3601
3602#if 0
3603    struct eth_tx_bd *tx_data_bd;
3604
3605    /*
3606     * The following code doesn't do anything but is left here
3607     * for clarity on what the new value of new_cons skipped.
3608     */
3609
3610    /* get the next bd */
3611    bd_idx = TX_BD(TX_BD_NEXT(bd_idx));
3612
3613    /* skip the parse bd */
3614    --nbd;
3615    bd_idx = TX_BD(TX_BD_NEXT(bd_idx));
3616
3617    /* skip the TSO split header bd since they have no mapping */
3618    if (tx_buf->flags & BXE_TSO_SPLIT_BD) {
3619        --nbd;
3620        bd_idx = TX_BD(TX_BD_NEXT(bd_idx));
3621    }
3622
3623    /* now free frags */
3624    while (nbd > 0) {
3625        tx_data_bd = &fp->tx_chain[bd_idx].reg_bd;
3626        if (--nbd) {
3627            bd_idx = TX_BD(TX_BD_NEXT(bd_idx));
3628        }
3629    }
3630#endif
3631
3632    /* free the mbuf */
3633    if (__predict_true(tx_buf->m != NULL)) {
3634        m_freem(tx_buf->m);
3635        fp->eth_q_stats.mbuf_alloc_tx--;
3636    } else {
3637        fp->eth_q_stats.tx_chain_lost_mbuf++;
3638    }
3639
3640    tx_buf->m = NULL;
3641    tx_buf->first_bd = 0;
3642
3643    return (new_cons);
3644}
3645
3646/* transmit timeout watchdog */
3647static int
3648bxe_watchdog(struct bxe_softc    *sc,
3649             struct bxe_fastpath *fp)
3650{
3651    BXE_FP_TX_LOCK(fp);
3652
3653    if ((fp->watchdog_timer == 0) || (--fp->watchdog_timer)) {
3654        BXE_FP_TX_UNLOCK(fp);
3655        return (0);
3656    }
3657
3658    BLOGE(sc, "TX watchdog timeout on fp[%02d], resetting!\n", fp->index);
3659
3660    BXE_FP_TX_UNLOCK(fp);
3661
3662    atomic_store_rel_long(&sc->chip_tq_flags, CHIP_TQ_REINIT);
3663    taskqueue_enqueue(sc->chip_tq, &sc->chip_tq_task);
3664
3665    return (-1);
3666}
3667
3668/* processes transmit completions */
3669static uint8_t
3670bxe_txeof(struct bxe_softc    *sc,
3671          struct bxe_fastpath *fp)
3672{
3673    if_t ifp = sc->ifp;
3674    uint16_t bd_cons, hw_cons, sw_cons, pkt_cons;
3675    uint16_t tx_bd_avail;
3676
3677    BXE_FP_TX_LOCK_ASSERT(fp);
3678
3679    bd_cons = fp->tx_bd_cons;
3680    hw_cons = le16toh(*fp->tx_cons_sb);
3681    sw_cons = fp->tx_pkt_cons;
3682
3683    while (sw_cons != hw_cons) {
3684        pkt_cons = TX_BD(sw_cons);
3685
3686        BLOGD(sc, DBG_TX,
3687              "TX: fp[%d]: hw_cons=%u sw_cons=%u pkt_cons=%u\n",
3688              fp->index, hw_cons, sw_cons, pkt_cons);
3689
3690        bd_cons = bxe_free_tx_pkt(sc, fp, pkt_cons);
3691
3692        sw_cons++;
3693    }
3694
3695    fp->tx_pkt_cons = sw_cons;
3696    fp->tx_bd_cons  = bd_cons;
3697
3698    BLOGD(sc, DBG_TX,
3699          "TX done: fp[%d]: hw_cons=%u sw_cons=%u sw_prod=%u\n",
3700          fp->index, hw_cons, fp->tx_pkt_cons, fp->tx_pkt_prod);
3701
3702    mb();
3703
3704    tx_bd_avail = bxe_tx_avail(sc, fp);
3705
3706    if (tx_bd_avail < BXE_TX_CLEANUP_THRESHOLD) {
3707        if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
3708    } else {
3709        if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
3710    }
3711
3712    if (fp->tx_pkt_prod != fp->tx_pkt_cons) {
3713        /* reset the watchdog timer if there are pending transmits */
3714        fp->watchdog_timer = BXE_TX_TIMEOUT;
3715        return (TRUE);
3716    } else {
3717        /* clear watchdog when there are no pending transmits */
3718        fp->watchdog_timer = 0;
3719        return (FALSE);
3720    }
3721}
3722
3723static void
3724bxe_drain_tx_queues(struct bxe_softc *sc)
3725{
3726    struct bxe_fastpath *fp;
3727    int i, count;
3728
3729    /* wait until all TX fastpath tasks have completed */
3730    for (i = 0; i < sc->num_queues; i++) {
3731        fp = &sc->fp[i];
3732
3733        count = 1000;
3734
3735        while (bxe_has_tx_work(fp)) {
3736
3737            BXE_FP_TX_LOCK(fp);
3738            bxe_txeof(sc, fp);
3739            BXE_FP_TX_UNLOCK(fp);
3740
3741            if (count == 0) {
3742                BLOGE(sc, "Timeout waiting for fp[%d] "
3743                          "transmits to complete!\n", i);
3744                bxe_panic(sc, ("tx drain failure\n"));
3745                return;
3746            }
3747
3748            count--;
3749            DELAY(1000);
3750            rmb();
3751        }
3752    }
3753
3754    return;
3755}
3756
3757static int
3758bxe_del_all_macs(struct bxe_softc          *sc,
3759                 struct ecore_vlan_mac_obj *mac_obj,
3760                 int                       mac_type,
3761                 uint8_t                   wait_for_comp)
3762{
3763    unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
3764    int rc;
3765
3766    /* wait for completion of requested */
3767    if (wait_for_comp) {
3768        bxe_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
3769    }
3770
3771    /* Set the mac type of addresses we want to clear */
3772    bxe_set_bit(mac_type, &vlan_mac_flags);
3773
3774    rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);
3775    if (rc < 0) {
3776        BLOGE(sc, "Failed to delete MACs (%d)\n", rc);
3777    }
3778
3779    return (rc);
3780}
3781
3782static int
3783bxe_fill_accept_flags(struct bxe_softc *sc,
3784                      uint32_t         rx_mode,
3785                      unsigned long    *rx_accept_flags,
3786                      unsigned long    *tx_accept_flags)
3787{
3788    /* Clear the flags first */
3789    *rx_accept_flags = 0;
3790    *tx_accept_flags = 0;
3791
3792    switch (rx_mode) {
3793    case BXE_RX_MODE_NONE:
3794        /*
3795         * 'drop all' supersedes any accept flags that may have been
3796         * passed to the function.
3797         */
3798        break;
3799
3800    case BXE_RX_MODE_NORMAL:
3801        bxe_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
3802        bxe_set_bit(ECORE_ACCEPT_MULTICAST, rx_accept_flags);
3803        bxe_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
3804
3805        /* internal switching mode */
3806        bxe_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
3807        bxe_set_bit(ECORE_ACCEPT_MULTICAST, tx_accept_flags);
3808        bxe_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
3809
3810        break;
3811
3812    case BXE_RX_MODE_ALLMULTI:
3813        bxe_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
3814        bxe_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);
3815        bxe_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
3816
3817        /* internal switching mode */
3818        bxe_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
3819        bxe_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);
3820        bxe_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
3821
3822        break;
3823
3824    case BXE_RX_MODE_PROMISC:
3825        /*
3826         * According to deffinition of SI mode, iface in promisc mode
3827         * should receive matched and unmatched (in resolution of port)
3828         * unicast packets.
3829         */
3830        bxe_set_bit(ECORE_ACCEPT_UNMATCHED, rx_accept_flags);
3831        bxe_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
3832        bxe_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);
3833        bxe_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
3834
3835        /* internal switching mode */
3836        bxe_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);
3837        bxe_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
3838
3839        if (IS_MF_SI(sc)) {
3840            bxe_set_bit(ECORE_ACCEPT_ALL_UNICAST, tx_accept_flags);
3841        } else {
3842            bxe_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
3843        }
3844
3845        break;
3846
3847    default:
3848        BLOGE(sc, "Unknown rx_mode (%d)\n", rx_mode);
3849        return (-1);
3850    }
3851
3852    /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
3853    if (rx_mode != BXE_RX_MODE_NONE) {
3854        bxe_set_bit(ECORE_ACCEPT_ANY_VLAN, rx_accept_flags);
3855        bxe_set_bit(ECORE_ACCEPT_ANY_VLAN, tx_accept_flags);
3856    }
3857
3858    return (0);
3859}
3860
3861static int
3862bxe_set_q_rx_mode(struct bxe_softc *sc,
3863                  uint8_t          cl_id,
3864                  unsigned long    rx_mode_flags,
3865                  unsigned long    rx_accept_flags,
3866                  unsigned long    tx_accept_flags,
3867                  unsigned long    ramrod_flags)
3868{
3869    struct ecore_rx_mode_ramrod_params ramrod_param;
3870    int rc;
3871
3872    memset(&ramrod_param, 0, sizeof(ramrod_param));
3873
3874    /* Prepare ramrod parameters */
3875    ramrod_param.cid = 0;
3876    ramrod_param.cl_id = cl_id;
3877    ramrod_param.rx_mode_obj = &sc->rx_mode_obj;
3878    ramrod_param.func_id = SC_FUNC(sc);
3879
3880    ramrod_param.pstate = &sc->sp_state;
3881    ramrod_param.state = ECORE_FILTER_RX_MODE_PENDING;
3882
3883    ramrod_param.rdata = BXE_SP(sc, rx_mode_rdata);
3884    ramrod_param.rdata_mapping = BXE_SP_MAPPING(sc, rx_mode_rdata);
3885
3886    bxe_set_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
3887
3888    ramrod_param.ramrod_flags = ramrod_flags;
3889    ramrod_param.rx_mode_flags = rx_mode_flags;
3890
3891    ramrod_param.rx_accept_flags = rx_accept_flags;
3892    ramrod_param.tx_accept_flags = tx_accept_flags;
3893
3894    rc = ecore_config_rx_mode(sc, &ramrod_param);
3895    if (rc < 0) {
3896        BLOGE(sc, "Set rx_mode %d failed\n", sc->rx_mode);
3897        return (rc);
3898    }
3899
3900    return (0);
3901}
3902
3903static int
3904bxe_set_storm_rx_mode(struct bxe_softc *sc)
3905{
3906    unsigned long rx_mode_flags = 0, ramrod_flags = 0;
3907    unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
3908    int rc;
3909
3910    rc = bxe_fill_accept_flags(sc, sc->rx_mode, &rx_accept_flags,
3911                               &tx_accept_flags);
3912    if (rc) {
3913        return (rc);
3914    }
3915
3916    bxe_set_bit(RAMROD_RX, &ramrod_flags);
3917    bxe_set_bit(RAMROD_TX, &ramrod_flags);
3918
3919    /* XXX ensure all fastpath have same cl_id and/or move it to bxe_softc */
3920    return (bxe_set_q_rx_mode(sc, sc->fp[0].cl_id, rx_mode_flags,
3921                              rx_accept_flags, tx_accept_flags,
3922                              ramrod_flags));
3923}
3924
3925/* returns the "mcp load_code" according to global load_count array */
3926static int
3927bxe_nic_load_no_mcp(struct bxe_softc *sc)
3928{
3929    int path = SC_PATH(sc);
3930    int port = SC_PORT(sc);
3931
3932    BLOGI(sc, "NO MCP - load counts[%d]      %d, %d, %d\n",
3933          path, load_count[path][0], load_count[path][1],
3934          load_count[path][2]);
3935    load_count[path][0]++;
3936    load_count[path][1 + port]++;
3937    BLOGI(sc, "NO MCP - new load counts[%d]  %d, %d, %d\n",
3938          path, load_count[path][0], load_count[path][1],
3939          load_count[path][2]);
3940    if (load_count[path][0] == 1) {
3941        return (FW_MSG_CODE_DRV_LOAD_COMMON);
3942    } else if (load_count[path][1 + port] == 1) {
3943        return (FW_MSG_CODE_DRV_LOAD_PORT);
3944    } else {
3945        return (FW_MSG_CODE_DRV_LOAD_FUNCTION);
3946    }
3947}
3948
3949/* returns the "mcp load_code" according to global load_count array */
3950static int
3951bxe_nic_unload_no_mcp(struct bxe_softc *sc)
3952{
3953    int port = SC_PORT(sc);
3954    int path = SC_PATH(sc);
3955
3956    BLOGI(sc, "NO MCP - load counts[%d]      %d, %d, %d\n",
3957          path, load_count[path][0], load_count[path][1],
3958          load_count[path][2]);
3959    load_count[path][0]--;
3960    load_count[path][1 + port]--;
3961    BLOGI(sc, "NO MCP - new load counts[%d]  %d, %d, %d\n",
3962          path, load_count[path][0], load_count[path][1],
3963          load_count[path][2]);
3964    if (load_count[path][0] == 0) {
3965        return (FW_MSG_CODE_DRV_UNLOAD_COMMON);
3966    } else if (load_count[path][1 + port] == 0) {
3967        return (FW_MSG_CODE_DRV_UNLOAD_PORT);
3968    } else {
3969        return (FW_MSG_CODE_DRV_UNLOAD_FUNCTION);
3970    }
3971}
3972
3973/* request unload mode from the MCP: COMMON, PORT or FUNCTION */
3974static uint32_t
3975bxe_send_unload_req(struct bxe_softc *sc,
3976                    int              unload_mode)
3977{
3978    uint32_t reset_code = 0;
3979#if 0
3980    int port = SC_PORT(sc);
3981    int path = SC_PATH(sc);
3982#endif
3983
3984    /* Select the UNLOAD request mode */
3985    if (unload_mode == UNLOAD_NORMAL) {
3986        reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
3987    }
3988#if 0
3989    else if (sc->flags & BXE_NO_WOL_FLAG) {
3990        reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
3991    } else if (sc->wol) {
3992        uint32_t emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
3993        uint8_t *mac_addr = sc->dev->dev_addr;
3994        uint32_t val;
3995        uint16_t pmc;
3996
3997        /*
3998         * The mac address is written to entries 1-4 to
3999         * preserve entry 0 which is used by the PMF
4000         */
4001        uint8_t entry = (SC_VN(sc) + 1)*8;
4002
4003        val = (mac_addr[0] << 8) | mac_addr[1];
4004        EMAC_WR(sc, EMAC_REG_EMAC_MAC_MATCH + entry, val);
4005
4006        val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
4007              (mac_addr[4] << 8) | mac_addr[5];
4008        EMAC_WR(sc, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
4009
4010        /* Enable the PME and clear the status */
4011        pmc = pci_read_config(sc->dev,
4012                              (sc->devinfo.pcie_pm_cap_reg +
4013                               PCIR_POWER_STATUS),
4014                              2);
4015        pmc |= PCIM_PSTAT_PMEENABLE | PCIM_PSTAT_PME;
4016        pci_write_config(sc->dev,
4017                         (sc->devinfo.pcie_pm_cap_reg +
4018                          PCIR_POWER_STATUS),
4019                         pmc, 4);
4020
4021        reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
4022    }
4023#endif
4024    else {
4025        reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
4026    }
4027
4028    /* Send the request to the MCP */
4029    if (!BXE_NOMCP(sc)) {
4030        reset_code = bxe_fw_command(sc, reset_code, 0);
4031    } else {
4032        reset_code = bxe_nic_unload_no_mcp(sc);
4033    }
4034
4035    return (reset_code);
4036}
4037
4038/* send UNLOAD_DONE command to the MCP */
4039static void
4040bxe_send_unload_done(struct bxe_softc *sc,
4041                     uint8_t          keep_link)
4042{
4043    uint32_t reset_param =
4044        keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
4045
4046    /* Report UNLOAD_DONE to MCP */
4047    if (!BXE_NOMCP(sc)) {
4048        bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
4049    }
4050}
4051
4052static int
4053bxe_func_wait_started(struct bxe_softc *sc)
4054{
4055    int tout = 50;
4056
4057    if (!sc->port.pmf) {
4058        return (0);
4059    }
4060
4061    /*
4062     * (assumption: No Attention from MCP at this stage)
4063     * PMF probably in the middle of TX disable/enable transaction
4064     * 1. Sync IRS for default SB
4065     * 2. Sync SP queue - this guarantees us that attention handling started
4066     * 3. Wait, that TX disable/enable transaction completes
4067     *
4068     * 1+2 guarantee that if DCBX attention was scheduled it already changed
4069     * pending bit of transaction from STARTED-->TX_STOPPED, if we already
4070     * received completion for the transaction the state is TX_STOPPED.
4071     * State will return to STARTED after completion of TX_STOPPED-->STARTED
4072     * transaction.
4073     */
4074
4075    /* XXX make sure default SB ISR is done */
4076    /* need a way to synchronize an irq (intr_mtx?) */
4077
4078    /* XXX flush any work queues */
4079
4080    while (ecore_func_get_state(sc, &sc->func_obj) !=
4081           ECORE_F_STATE_STARTED && tout--) {
4082        DELAY(20000);
4083    }
4084
4085    if (ecore_func_get_state(sc, &sc->func_obj) != ECORE_F_STATE_STARTED) {
4086        /*
4087         * Failed to complete the transaction in a "good way"
4088         * Force both transactions with CLR bit.
4089         */
4090        struct ecore_func_state_params func_params = { NULL };
4091
4092        BLOGE(sc, "Unexpected function state! "
4093                  "Forcing STARTED-->TX_STOPPED-->STARTED\n");
4094
4095        func_params.f_obj = &sc->func_obj;
4096        bxe_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
4097
4098        /* STARTED-->TX_STOPPED */
4099        func_params.cmd = ECORE_F_CMD_TX_STOP;
4100        ecore_func_state_change(sc, &func_params);
4101
4102        /* TX_STOPPED-->STARTED */
4103        func_params.cmd = ECORE_F_CMD_TX_START;
4104        return (ecore_func_state_change(sc, &func_params));
4105    }
4106
4107    return (0);
4108}
4109
4110static int
4111bxe_stop_queue(struct bxe_softc *sc,
4112               int              index)
4113{
4114    struct bxe_fastpath *fp = &sc->fp[index];
4115    struct ecore_queue_state_params q_params = { NULL };
4116    int rc;
4117
4118    BLOGD(sc, DBG_LOAD, "stopping queue %d cid %d\n", index, fp->index);
4119
4120    q_params.q_obj = &sc->sp_objs[fp->index].q_obj;
4121    /* We want to wait for completion in this context */
4122    bxe_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
4123
4124    /* Stop the primary connection: */
4125
4126    /* ...halt the connection */
4127    q_params.cmd = ECORE_Q_CMD_HALT;
4128    rc = ecore_queue_state_change(sc, &q_params);
4129    if (rc) {
4130        return (rc);
4131    }
4132
4133    /* ...terminate the connection */
4134    q_params.cmd = ECORE_Q_CMD_TERMINATE;
4135    memset(&q_params.params.terminate, 0, sizeof(q_params.params.terminate));
4136    q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
4137    rc = ecore_queue_state_change(sc, &q_params);
4138    if (rc) {
4139        return (rc);
4140    }
4141
4142    /* ...delete cfc entry */
4143    q_params.cmd = ECORE_Q_CMD_CFC_DEL;
4144    memset(&q_params.params.cfc_del, 0, sizeof(q_params.params.cfc_del));
4145    q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
4146    return (ecore_queue_state_change(sc, &q_params));
4147}
4148
4149/* wait for the outstanding SP commands */
4150static inline uint8_t
4151bxe_wait_sp_comp(struct bxe_softc *sc,
4152                 unsigned long    mask)
4153{
4154    unsigned long tmp;
4155    int tout = 5000; /* wait for 5 secs tops */
4156
4157    while (tout--) {
4158        mb();
4159        if (!(atomic_load_acq_long(&sc->sp_state) & mask)) {
4160            return (TRUE);
4161        }
4162
4163        DELAY(1000);
4164    }
4165
4166    mb();
4167
4168    tmp = atomic_load_acq_long(&sc->sp_state);
4169    if (tmp & mask) {
4170        BLOGE(sc, "Filtering completion timed out: "
4171                  "sp_state 0x%lx, mask 0x%lx\n",
4172              tmp, mask);
4173        return (FALSE);
4174    }
4175
4176    return (FALSE);
4177}
4178
4179static int
4180bxe_func_stop(struct bxe_softc *sc)
4181{
4182    struct ecore_func_state_params func_params = { NULL };
4183    int rc;
4184
4185    /* prepare parameters for function state transitions */
4186    bxe_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
4187    func_params.f_obj = &sc->func_obj;
4188    func_params.cmd = ECORE_F_CMD_STOP;
4189
4190    /*
4191     * Try to stop the function the 'good way'. If it fails (in case
4192     * of a parity error during bxe_chip_cleanup()) and we are
4193     * not in a debug mode, perform a state transaction in order to
4194     * enable further HW_RESET transaction.
4195     */
4196    rc = ecore_func_state_change(sc, &func_params);
4197    if (rc) {
4198        BLOGE(sc, "FUNC_STOP ramrod failed. "
4199                  "Running a dry transaction\n");
4200        bxe_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
4201        return (ecore_func_state_change(sc, &func_params));
4202    }
4203
4204    return (0);
4205}
4206
4207static int
4208bxe_reset_hw(struct bxe_softc *sc,
4209             uint32_t         load_code)
4210{
4211    struct ecore_func_state_params func_params = { NULL };
4212
4213    /* Prepare parameters for function state transitions */
4214    bxe_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
4215
4216    func_params.f_obj = &sc->func_obj;
4217    func_params.cmd = ECORE_F_CMD_HW_RESET;
4218
4219    func_params.params.hw_init.load_phase = load_code;
4220
4221    return (ecore_func_state_change(sc, &func_params));
4222}
4223
4224static void
4225bxe_int_disable_sync(struct bxe_softc *sc,
4226                     int              disable_hw)
4227{
4228    if (disable_hw) {
4229        /* prevent the HW from sending interrupts */
4230        bxe_int_disable(sc);
4231    }
4232
4233    /* XXX need a way to synchronize ALL irqs (intr_mtx?) */
4234    /* make sure all ISRs are done */
4235
4236    /* XXX make sure sp_task is not running */
4237    /* cancel and flush work queues */
4238}
4239
4240static void
4241bxe_chip_cleanup(struct bxe_softc *sc,
4242                 uint32_t         unload_mode,
4243                 uint8_t          keep_link)
4244{
4245    int port = SC_PORT(sc);
4246    struct ecore_mcast_ramrod_params rparam = { NULL };
4247    uint32_t reset_code;
4248    int i, rc = 0;
4249
4250    bxe_drain_tx_queues(sc);
4251
4252    /* give HW time to discard old tx messages */
4253    DELAY(1000);
4254
4255    /* Clean all ETH MACs */
4256    rc = bxe_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_ETH_MAC, FALSE);
4257    if (rc < 0) {
4258        BLOGE(sc, "Failed to delete all ETH MACs (%d)\n", rc);
4259    }
4260
4261    /* Clean up UC list  */
4262    rc = bxe_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_UC_LIST_MAC, TRUE);
4263    if (rc < 0) {
4264        BLOGE(sc, "Failed to delete UC MACs list (%d)\n", rc);
4265    }
4266
4267    /* Disable LLH */
4268    if (!CHIP_IS_E1(sc)) {
4269        REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port*8, 0);
4270    }
4271
4272    /* Set "drop all" to stop Rx */
4273
4274    /*
4275     * We need to take the BXE_MCAST_LOCK() here in order to prevent
4276     * a race between the completion code and this code.
4277     */
4278    BXE_MCAST_LOCK(sc);
4279
4280    if (bxe_test_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state)) {
4281        bxe_set_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state);
4282    } else {
4283        bxe_set_storm_rx_mode(sc);
4284    }
4285
4286    /* Clean up multicast configuration */
4287    rparam.mcast_obj = &sc->mcast_obj;
4288    rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
4289    if (rc < 0) {
4290        BLOGE(sc, "Failed to send DEL MCAST command (%d)\n", rc);
4291    }
4292
4293    BXE_MCAST_UNLOCK(sc);
4294
4295    // XXX bxe_iov_chip_cleanup(sc);
4296
4297    /*
4298     * Send the UNLOAD_REQUEST to the MCP. This will return if
4299     * this function should perform FUNCTION, PORT, or COMMON HW
4300     * reset.
4301     */
4302    reset_code = bxe_send_unload_req(sc, unload_mode);
4303
4304    /*
4305     * (assumption: No Attention from MCP at this stage)
4306     * PMF probably in the middle of TX disable/enable transaction
4307     */
4308    rc = bxe_func_wait_started(sc);
4309    if (rc) {
4310        BLOGE(sc, "bxe_func_wait_started failed\n");
4311    }
4312
4313    /*
4314     * Close multi and leading connections
4315     * Completions for ramrods are collected in a synchronous way
4316     */
4317    for (i = 0; i < sc->num_queues; i++) {
4318        if (bxe_stop_queue(sc, i)) {
4319            goto unload_error;
4320        }
4321    }
4322
4323    /*
4324     * If SP settings didn't get completed so far - something
4325     * very wrong has happen.
4326     */
4327    if (!bxe_wait_sp_comp(sc, ~0x0UL)) {
4328        BLOGE(sc, "Common slow path ramrods got stuck!\n");
4329    }
4330
4331unload_error:
4332
4333    rc = bxe_func_stop(sc);
4334    if (rc) {
4335        BLOGE(sc, "Function stop failed!\n");
4336    }
4337
4338    /* disable HW interrupts */
4339    bxe_int_disable_sync(sc, TRUE);
4340
4341    /* detach interrupts */
4342    bxe_interrupt_detach(sc);
4343
4344    /* Reset the chip */
4345    rc = bxe_reset_hw(sc, reset_code);
4346    if (rc) {
4347        BLOGE(sc, "Hardware reset failed\n");
4348    }
4349
4350    /* Report UNLOAD_DONE to MCP */
4351    bxe_send_unload_done(sc, keep_link);
4352}
4353
4354static void
4355bxe_disable_close_the_gate(struct bxe_softc *sc)
4356{
4357    uint32_t val;
4358    int port = SC_PORT(sc);
4359
4360    BLOGD(sc, DBG_LOAD,
4361          "Disabling 'close the gates'\n");
4362
4363    if (CHIP_IS_E1(sc)) {
4364        uint32_t addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4365                               MISC_REG_AEU_MASK_ATTN_FUNC_0;
4366        val = REG_RD(sc, addr);
4367        val &= ~(0x300);
4368        REG_WR(sc, addr, val);
4369    } else {
4370        val = REG_RD(sc, MISC_REG_AEU_GENERAL_MASK);
4371        val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
4372                 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
4373        REG_WR(sc, MISC_REG_AEU_GENERAL_MASK, val);
4374    }
4375}
4376
4377/*
4378 * Cleans the object that have internal lists without sending
4379 * ramrods. Should be run when interrutps are disabled.
4380 */
4381static void
4382bxe_squeeze_objects(struct bxe_softc *sc)
4383{
4384    unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
4385    struct ecore_mcast_ramrod_params rparam = { NULL };
4386    struct ecore_vlan_mac_obj *mac_obj = &sc->sp_objs->mac_obj;
4387    int rc;
4388
4389    /* Cleanup MACs' object first... */
4390
4391    /* Wait for completion of requested */
4392    bxe_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
4393    /* Perform a dry cleanup */
4394    bxe_set_bit(RAMROD_DRV_CLR_ONLY, &ramrod_flags);
4395
4396    /* Clean ETH primary MAC */
4397    bxe_set_bit(ECORE_ETH_MAC, &vlan_mac_flags);
4398    rc = mac_obj->delete_all(sc, &sc->sp_objs->mac_obj, &vlan_mac_flags,
4399                             &ramrod_flags);
4400    if (rc != 0) {
4401        BLOGE(sc, "Failed to clean ETH MACs (%d)\n", rc);
4402    }
4403
4404    /* Cleanup UC list */
4405    vlan_mac_flags = 0;
4406    bxe_set_bit(ECORE_UC_LIST_MAC, &vlan_mac_flags);
4407    rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags,
4408                             &ramrod_flags);
4409    if (rc != 0) {
4410        BLOGE(sc, "Failed to clean UC list MACs (%d)\n", rc);
4411    }
4412
4413    /* Now clean mcast object... */
4414
4415    rparam.mcast_obj = &sc->mcast_obj;
4416    bxe_set_bit(RAMROD_DRV_CLR_ONLY, &rparam.ramrod_flags);
4417
4418    /* Add a DEL command... */
4419    rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
4420    if (rc < 0) {
4421        BLOGE(sc, "Failed to send DEL MCAST command (%d)\n", rc);
4422    }
4423
4424    /* now wait until all pending commands are cleared */
4425
4426    rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
4427    while (rc != 0) {
4428        if (rc < 0) {
4429            BLOGE(sc, "Failed to clean MCAST object (%d)\n", rc);
4430            return;
4431        }
4432
4433        rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
4434    }
4435}
4436
4437/* stop the controller */
4438static __noinline int
4439bxe_nic_unload(struct bxe_softc *sc,
4440               uint32_t         unload_mode,
4441               uint8_t          keep_link)
4442{
4443    uint8_t global = FALSE;
4444    uint32_t val;
4445
4446    BXE_CORE_LOCK_ASSERT(sc);
4447
4448    BLOGD(sc, DBG_LOAD, "Starting NIC unload...\n");
4449
4450    /* mark driver as unloaded in shmem2 */
4451    if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
4452        val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
4453        SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
4454                  val & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
4455    }
4456
4457    if (IS_PF(sc) && sc->recovery_state != BXE_RECOVERY_DONE &&
4458        (sc->state == BXE_STATE_CLOSED || sc->state == BXE_STATE_ERROR)) {
4459        /*
4460         * We can get here if the driver has been unloaded
4461         * during parity error recovery and is either waiting for a
4462         * leader to complete or for other functions to unload and
4463         * then ifconfig down has been issued. In this case we want to
4464         * unload and let other functions to complete a recovery
4465         * process.
4466         */
4467        sc->recovery_state = BXE_RECOVERY_DONE;
4468        sc->is_leader = 0;
4469        bxe_release_leader_lock(sc);
4470        mb();
4471
4472        BLOGD(sc, DBG_LOAD, "Releasing a leadership...\n");
4473        BLOGE(sc, "Can't unload in closed or error state\n");
4474        return (-1);
4475    }
4476
4477    /*
4478     * Nothing to do during unload if previous bxe_nic_load()
4479     * did not completed succesfully - all resourses are released.
4480     */
4481    if ((sc->state == BXE_STATE_CLOSED) ||
4482        (sc->state == BXE_STATE_ERROR)) {
4483        return (0);
4484    }
4485
4486    sc->state = BXE_STATE_CLOSING_WAITING_HALT;
4487    mb();
4488
4489    /* stop tx */
4490    bxe_tx_disable(sc);
4491
4492    sc->rx_mode = BXE_RX_MODE_NONE;
4493    /* XXX set rx mode ??? */
4494
4495    if (IS_PF(sc)) {
4496        /* set ALWAYS_ALIVE bit in shmem */
4497        sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
4498
4499        bxe_drv_pulse(sc);
4500
4501        bxe_stats_handle(sc, STATS_EVENT_STOP);
4502        bxe_save_statistics(sc);
4503    }
4504
4505    /* wait till consumers catch up with producers in all queues */
4506    bxe_drain_tx_queues(sc);
4507
4508    /* if VF indicate to PF this function is going down (PF will delete sp
4509     * elements and clear initializations
4510     */
4511    if (IS_VF(sc)) {
4512        ; /* bxe_vfpf_close_vf(sc); */
4513    } else if (unload_mode != UNLOAD_RECOVERY) {
4514        /* if this is a normal/close unload need to clean up chip */
4515        bxe_chip_cleanup(sc, unload_mode, keep_link);
4516    } else {
4517        /* Send the UNLOAD_REQUEST to the MCP */
4518        bxe_send_unload_req(sc, unload_mode);
4519
4520        /*
4521         * Prevent transactions to host from the functions on the
4522         * engine that doesn't reset global blocks in case of global
4523         * attention once gloabl blocks are reset and gates are opened
4524         * (the engine which leader will perform the recovery
4525         * last).
4526         */
4527        if (!CHIP_IS_E1x(sc)) {
4528            bxe_pf_disable(sc);
4529        }
4530
4531        /* disable HW interrupts */
4532        bxe_int_disable_sync(sc, TRUE);
4533
4534        /* detach interrupts */
4535        bxe_interrupt_detach(sc);
4536
4537        /* Report UNLOAD_DONE to MCP */
4538        bxe_send_unload_done(sc, FALSE);
4539    }
4540
4541    /*
4542     * At this stage no more interrupts will arrive so we may safely clean
4543     * the queue'able objects here in case they failed to get cleaned so far.
4544     */
4545    if (IS_PF(sc)) {
4546        bxe_squeeze_objects(sc);
4547    }
4548
4549    /* There should be no more pending SP commands at this stage */
4550    sc->sp_state = 0;
4551
4552    sc->port.pmf = 0;
4553
4554    bxe_free_fp_buffers(sc);
4555
4556    if (IS_PF(sc)) {
4557        bxe_free_mem(sc);
4558    }
4559
4560    bxe_free_fw_stats_mem(sc);
4561
4562    sc->state = BXE_STATE_CLOSED;
4563
4564    /*
4565     * Check if there are pending parity attentions. If there are - set
4566     * RECOVERY_IN_PROGRESS.
4567     */
4568    if (IS_PF(sc) && bxe_chk_parity_attn(sc, &global, FALSE)) {
4569        bxe_set_reset_in_progress(sc);
4570
4571        /* Set RESET_IS_GLOBAL if needed */
4572        if (global) {
4573            bxe_set_reset_global(sc);
4574        }
4575    }
4576
4577    /*
4578     * The last driver must disable a "close the gate" if there is no
4579     * parity attention or "process kill" pending.
4580     */
4581    if (IS_PF(sc) && !bxe_clear_pf_load(sc) &&
4582        bxe_reset_is_done(sc, SC_PATH(sc))) {
4583        bxe_disable_close_the_gate(sc);
4584    }
4585
4586    BLOGD(sc, DBG_LOAD, "Ended NIC unload\n");
4587
4588    return (0);
4589}
4590
4591/*
4592 * Called by the OS to set various media options (i.e. link, speed, etc.) when
4593 * the user runs "ifconfig bxe media ..." or "ifconfig bxe mediaopt ...".
4594 */
4595static int
4596bxe_ifmedia_update(struct ifnet  *ifp)
4597{
4598    struct bxe_softc *sc = (struct bxe_softc *)if_getsoftc(ifp);
4599    struct ifmedia *ifm;
4600
4601    ifm = &sc->ifmedia;
4602
4603    /* We only support Ethernet media type. */
4604    if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) {
4605        return (EINVAL);
4606    }
4607
4608    switch (IFM_SUBTYPE(ifm->ifm_media)) {
4609    case IFM_AUTO:
4610         break;
4611    case IFM_10G_CX4:
4612    case IFM_10G_SR:
4613    case IFM_10G_T:
4614    case IFM_10G_TWINAX:
4615    default:
4616        /* We don't support changing the media type. */
4617        BLOGD(sc, DBG_LOAD, "Invalid media type (%d)\n",
4618              IFM_SUBTYPE(ifm->ifm_media));
4619        return (EINVAL);
4620    }
4621
4622    return (0);
4623}
4624
4625/*
4626 * Called by the OS to get the current media status (i.e. link, speed, etc.).
4627 */
4628static void
4629bxe_ifmedia_status(struct ifnet *ifp, struct ifmediareq *ifmr)
4630{
4631    struct bxe_softc *sc = if_getsoftc(ifp);
4632
4633    /* Report link down if the driver isn't running. */
4634    if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) {
4635        ifmr->ifm_active |= IFM_NONE;
4636        return;
4637    }
4638
4639    /* Setup the default interface info. */
4640    ifmr->ifm_status = IFM_AVALID;
4641    ifmr->ifm_active = IFM_ETHER;
4642
4643    if (sc->link_vars.link_up) {
4644        ifmr->ifm_status |= IFM_ACTIVE;
4645    } else {
4646        ifmr->ifm_active |= IFM_NONE;
4647        return;
4648    }
4649
4650    ifmr->ifm_active |= sc->media;
4651
4652    if (sc->link_vars.duplex == DUPLEX_FULL) {
4653        ifmr->ifm_active |= IFM_FDX;
4654    } else {
4655        ifmr->ifm_active |= IFM_HDX;
4656    }
4657}
4658
4659static int
4660bxe_ioctl_nvram(struct bxe_softc *sc,
4661                uint32_t         priv_op,
4662                struct ifreq     *ifr)
4663{
4664    struct bxe_nvram_data nvdata_base;
4665    struct bxe_nvram_data *nvdata;
4666    int len;
4667    int error = 0;
4668
4669    copyin(ifr->ifr_data, &nvdata_base, sizeof(nvdata_base));
4670
4671    len = (sizeof(struct bxe_nvram_data) +
4672           nvdata_base.len -
4673           sizeof(uint32_t));
4674
4675    if (len > sizeof(struct bxe_nvram_data)) {
4676        if ((nvdata = (struct bxe_nvram_data *)
4677                 malloc(len, M_DEVBUF,
4678                        (M_NOWAIT | M_ZERO))) == NULL) {
4679            BLOGE(sc, "BXE_IOC_RD_NVRAM malloc failed\n");
4680            return (1);
4681        }
4682        memcpy(nvdata, &nvdata_base, sizeof(struct bxe_nvram_data));
4683    } else {
4684        nvdata = &nvdata_base;
4685    }
4686
4687    if (priv_op == BXE_IOC_RD_NVRAM) {
4688        BLOGD(sc, DBG_IOCTL, "IOC_RD_NVRAM 0x%x %d\n",
4689              nvdata->offset, nvdata->len);
4690        error = bxe_nvram_read(sc,
4691                               nvdata->offset,
4692                               (uint8_t *)nvdata->value,
4693                               nvdata->len);
4694        copyout(nvdata, ifr->ifr_data, len);
4695    } else { /* BXE_IOC_WR_NVRAM */
4696        BLOGD(sc, DBG_IOCTL, "IOC_WR_NVRAM 0x%x %d\n",
4697              nvdata->offset, nvdata->len);
4698        copyin(ifr->ifr_data, nvdata, len);
4699        error = bxe_nvram_write(sc,
4700                                nvdata->offset,
4701                                (uint8_t *)nvdata->value,
4702                                nvdata->len);
4703    }
4704
4705    if (len > sizeof(struct bxe_nvram_data)) {
4706        free(nvdata, M_DEVBUF);
4707    }
4708
4709    return (error);
4710}
4711
4712static int
4713bxe_ioctl_stats_show(struct bxe_softc *sc,
4714                     uint32_t         priv_op,
4715                     struct ifreq     *ifr)
4716{
4717    const size_t str_size   = (BXE_NUM_ETH_STATS * STAT_NAME_LEN);
4718    const size_t stats_size = (BXE_NUM_ETH_STATS * sizeof(uint64_t));
4719    caddr_t p_tmp;
4720    uint32_t *offset;
4721    int i;
4722
4723    switch (priv_op)
4724    {
4725    case BXE_IOC_STATS_SHOW_NUM:
4726        memset(ifr->ifr_data, 0, sizeof(union bxe_stats_show_data));
4727        ((union bxe_stats_show_data *)ifr->ifr_data)->desc.num =
4728            BXE_NUM_ETH_STATS;
4729        ((union bxe_stats_show_data *)ifr->ifr_data)->desc.len =
4730            STAT_NAME_LEN;
4731        return (0);
4732
4733    case BXE_IOC_STATS_SHOW_STR:
4734        memset(ifr->ifr_data, 0, str_size);
4735        p_tmp = ifr->ifr_data;
4736        for (i = 0; i < BXE_NUM_ETH_STATS; i++) {
4737            strcpy(p_tmp, bxe_eth_stats_arr[i].string);
4738            p_tmp += STAT_NAME_LEN;
4739        }
4740        return (0);
4741
4742    case BXE_IOC_STATS_SHOW_CNT:
4743        memset(ifr->ifr_data, 0, stats_size);
4744        p_tmp = ifr->ifr_data;
4745        for (i = 0; i < BXE_NUM_ETH_STATS; i++) {
4746            offset = ((uint32_t *)&sc->eth_stats +
4747                      bxe_eth_stats_arr[i].offset);
4748            switch (bxe_eth_stats_arr[i].size) {
4749            case 4:
4750                *((uint64_t *)p_tmp) = (uint64_t)*offset;
4751                break;
4752            case 8:
4753                *((uint64_t *)p_tmp) = HILO_U64(*offset, *(offset + 1));
4754                break;
4755            default:
4756                *((uint64_t *)p_tmp) = 0;
4757            }
4758            p_tmp += sizeof(uint64_t);
4759        }
4760        return (0);
4761
4762    default:
4763        return (-1);
4764    }
4765}
4766
4767static void
4768bxe_handle_chip_tq(void *context,
4769                   int  pending)
4770{
4771    struct bxe_softc *sc = (struct bxe_softc *)context;
4772    long work = atomic_load_acq_long(&sc->chip_tq_flags);
4773
4774    switch (work)
4775    {
4776
4777    case CHIP_TQ_REINIT:
4778        if (if_getdrvflags(sc->ifp) & IFF_DRV_RUNNING) {
4779            /* restart the interface */
4780            BLOGD(sc, DBG_LOAD, "Restarting the interface...\n");
4781            bxe_periodic_stop(sc);
4782            BXE_CORE_LOCK(sc);
4783            bxe_stop_locked(sc);
4784            bxe_init_locked(sc);
4785            BXE_CORE_UNLOCK(sc);
4786        }
4787        break;
4788
4789    default:
4790        break;
4791    }
4792}
4793
4794/*
4795 * Handles any IOCTL calls from the operating system.
4796 *
4797 * Returns:
4798 *   0 = Success, >0 Failure
4799 */
4800static int
4801bxe_ioctl(if_t ifp,
4802          u_long       command,
4803          caddr_t      data)
4804{
4805    struct bxe_softc *sc = if_getsoftc(ifp);
4806    struct ifreq *ifr = (struct ifreq *)data;
4807    struct bxe_nvram_data *nvdata;
4808    uint32_t priv_op;
4809    int mask = 0;
4810    int reinit = 0;
4811    int error = 0;
4812
4813    int mtu_min = (ETH_MIN_PACKET_SIZE - ETH_HLEN);
4814    int mtu_max = (MJUM9BYTES - ETH_OVERHEAD - IP_HEADER_ALIGNMENT_PADDING);
4815
4816    switch (command)
4817    {
4818    case SIOCSIFMTU:
4819        BLOGD(sc, DBG_IOCTL, "Received SIOCSIFMTU ioctl (mtu=%d)\n",
4820              ifr->ifr_mtu);
4821
4822        if (sc->mtu == ifr->ifr_mtu) {
4823            /* nothing to change */
4824            break;
4825        }
4826
4827        if ((ifr->ifr_mtu < mtu_min) || (ifr->ifr_mtu > mtu_max)) {
4828            BLOGE(sc, "Unsupported MTU size %d (range is %d-%d)\n",
4829                  ifr->ifr_mtu, mtu_min, mtu_max);
4830            error = EINVAL;
4831            break;
4832        }
4833
4834        atomic_store_rel_int((volatile unsigned int *)&sc->mtu,
4835                             (unsigned long)ifr->ifr_mtu);
4836	/*
4837        atomic_store_rel_long((volatile unsigned long *)&if_getmtu(ifp),
4838                              (unsigned long)ifr->ifr_mtu);
4839	XXX - Not sure why it needs to be atomic
4840	*/
4841	if_setmtu(ifp, ifr->ifr_mtu);
4842        reinit = 1;
4843        break;
4844
4845    case SIOCSIFFLAGS:
4846        /* toggle the interface state up or down */
4847        BLOGD(sc, DBG_IOCTL, "Received SIOCSIFFLAGS ioctl\n");
4848
4849	BXE_CORE_LOCK(sc);
4850        /* check if the interface is up */
4851        if (if_getflags(ifp) & IFF_UP) {
4852            if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4853                /* set the receive mode flags */
4854                bxe_set_rx_mode(sc);
4855            } else {
4856		bxe_init_locked(sc);
4857            }
4858        } else {
4859            if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4860		bxe_periodic_stop(sc);
4861		bxe_stop_locked(sc);
4862            }
4863        }
4864	BXE_CORE_UNLOCK(sc);
4865
4866        break;
4867
4868    case SIOCADDMULTI:
4869    case SIOCDELMULTI:
4870        /* add/delete multicast addresses */
4871        BLOGD(sc, DBG_IOCTL, "Received SIOCADDMULTI/SIOCDELMULTI ioctl\n");
4872
4873        /* check if the interface is up */
4874        if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4875            /* set the receive mode flags */
4876	    BXE_CORE_LOCK(sc);
4877            bxe_set_rx_mode(sc);
4878	    BXE_CORE_UNLOCK(sc);
4879        }
4880
4881        break;
4882
4883    case SIOCSIFCAP:
4884        /* find out which capabilities have changed */
4885        mask = (ifr->ifr_reqcap ^ if_getcapenable(ifp));
4886
4887        BLOGD(sc, DBG_IOCTL, "Received SIOCSIFCAP ioctl (mask=0x%08x)\n",
4888              mask);
4889
4890        /* toggle the LRO capabilites enable flag */
4891        if (mask & IFCAP_LRO) {
4892	    if_togglecapenable(ifp, IFCAP_LRO);
4893            BLOGD(sc, DBG_IOCTL, "Turning LRO %s\n",
4894                  (if_getcapenable(ifp) & IFCAP_LRO) ? "ON" : "OFF");
4895            reinit = 1;
4896        }
4897
4898        /* toggle the TXCSUM checksum capabilites enable flag */
4899        if (mask & IFCAP_TXCSUM) {
4900	    if_togglecapenable(ifp, IFCAP_TXCSUM);
4901            BLOGD(sc, DBG_IOCTL, "Turning TXCSUM %s\n",
4902                  (if_getcapenable(ifp) & IFCAP_TXCSUM) ? "ON" : "OFF");
4903            if (if_getcapenable(ifp) & IFCAP_TXCSUM) {
4904                if_sethwassistbits(ifp, (CSUM_IP      |
4905                                    CSUM_TCP      |
4906                                    CSUM_UDP      |
4907                                    CSUM_TSO      |
4908                                    CSUM_TCP_IPV6 |
4909                                    CSUM_UDP_IPV6), 0);
4910            } else {
4911		if_clearhwassist(ifp); /* XXX */
4912            }
4913        }
4914
4915        /* toggle the RXCSUM checksum capabilities enable flag */
4916        if (mask & IFCAP_RXCSUM) {
4917	    if_togglecapenable(ifp, IFCAP_RXCSUM);
4918            BLOGD(sc, DBG_IOCTL, "Turning RXCSUM %s\n",
4919                  (if_getcapenable(ifp) & IFCAP_RXCSUM) ? "ON" : "OFF");
4920            if (if_getcapenable(ifp) & IFCAP_RXCSUM) {
4921                if_sethwassistbits(ifp, (CSUM_IP      |
4922                                    CSUM_TCP      |
4923                                    CSUM_UDP      |
4924                                    CSUM_TSO      |
4925                                    CSUM_TCP_IPV6 |
4926                                    CSUM_UDP_IPV6), 0);
4927            } else {
4928		if_clearhwassist(ifp); /* XXX */
4929            }
4930        }
4931
4932        /* toggle TSO4 capabilities enabled flag */
4933        if (mask & IFCAP_TSO4) {
4934            if_togglecapenable(ifp, IFCAP_TSO4);
4935            BLOGD(sc, DBG_IOCTL, "Turning TSO4 %s\n",
4936                  (if_getcapenable(ifp) & IFCAP_TSO4) ? "ON" : "OFF");
4937        }
4938
4939        /* toggle TSO6 capabilities enabled flag */
4940        if (mask & IFCAP_TSO6) {
4941	    if_togglecapenable(ifp, IFCAP_TSO6);
4942            BLOGD(sc, DBG_IOCTL, "Turning TSO6 %s\n",
4943                  (if_getcapenable(ifp) & IFCAP_TSO6) ? "ON" : "OFF");
4944        }
4945
4946        /* toggle VLAN_HWTSO capabilities enabled flag */
4947        if (mask & IFCAP_VLAN_HWTSO) {
4948
4949	    if_togglecapenable(ifp, IFCAP_VLAN_HWTSO);
4950            BLOGD(sc, DBG_IOCTL, "Turning VLAN_HWTSO %s\n",
4951                  (if_getcapenable(ifp) & IFCAP_VLAN_HWTSO) ? "ON" : "OFF");
4952        }
4953
4954        /* toggle VLAN_HWCSUM capabilities enabled flag */
4955        if (mask & IFCAP_VLAN_HWCSUM) {
4956            /* XXX investigate this... */
4957            BLOGE(sc, "Changing VLAN_HWCSUM is not supported!\n");
4958            error = EINVAL;
4959        }
4960
4961        /* toggle VLAN_MTU capabilities enable flag */
4962        if (mask & IFCAP_VLAN_MTU) {
4963            /* XXX investigate this... */
4964            BLOGE(sc, "Changing VLAN_MTU is not supported!\n");
4965            error = EINVAL;
4966        }
4967
4968        /* toggle VLAN_HWTAGGING capabilities enabled flag */
4969        if (mask & IFCAP_VLAN_HWTAGGING) {
4970            /* XXX investigate this... */
4971            BLOGE(sc, "Changing VLAN_HWTAGGING is not supported!\n");
4972            error = EINVAL;
4973        }
4974
4975        /* toggle VLAN_HWFILTER capabilities enabled flag */
4976        if (mask & IFCAP_VLAN_HWFILTER) {
4977            /* XXX investigate this... */
4978            BLOGE(sc, "Changing VLAN_HWFILTER is not supported!\n");
4979            error = EINVAL;
4980        }
4981
4982        /* XXX not yet...
4983         * IFCAP_WOL_MAGIC
4984         */
4985
4986        break;
4987
4988    case SIOCSIFMEDIA:
4989    case SIOCGIFMEDIA:
4990        /* set/get interface media */
4991        BLOGD(sc, DBG_IOCTL,
4992              "Received SIOCSIFMEDIA/SIOCGIFMEDIA ioctl (cmd=%lu)\n",
4993              (command & 0xff));
4994        error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
4995        break;
4996
4997    case SIOCGPRIVATE_0:
4998        copyin(ifr->ifr_data, &priv_op, sizeof(priv_op));
4999
5000        switch (priv_op)
5001        {
5002        case BXE_IOC_RD_NVRAM:
5003        case BXE_IOC_WR_NVRAM:
5004            nvdata = (struct bxe_nvram_data *)ifr->ifr_data;
5005            BLOGD(sc, DBG_IOCTL,
5006                  "Received Private NVRAM ioctl addr=0x%x size=%u\n",
5007                  nvdata->offset, nvdata->len);
5008            error = bxe_ioctl_nvram(sc, priv_op, ifr);
5009            break;
5010
5011        case BXE_IOC_STATS_SHOW_NUM:
5012        case BXE_IOC_STATS_SHOW_STR:
5013        case BXE_IOC_STATS_SHOW_CNT:
5014            BLOGD(sc, DBG_IOCTL, "Received Private Stats ioctl (%d)\n",
5015                  priv_op);
5016            error = bxe_ioctl_stats_show(sc, priv_op, ifr);
5017            break;
5018
5019        default:
5020            BLOGW(sc, "Received Private Unknown ioctl (%d)\n", priv_op);
5021            error = EINVAL;
5022            break;
5023        }
5024
5025        break;
5026
5027    default:
5028        BLOGD(sc, DBG_IOCTL, "Received Unknown Ioctl (cmd=%lu)\n",
5029              (command & 0xff));
5030        error = ether_ioctl(ifp, command, data);
5031        break;
5032    }
5033
5034    if (reinit && (if_getdrvflags(sc->ifp) & IFF_DRV_RUNNING)) {
5035        BLOGD(sc, DBG_LOAD | DBG_IOCTL,
5036              "Re-initializing hardware from IOCTL change\n");
5037	bxe_periodic_stop(sc);
5038	BXE_CORE_LOCK(sc);
5039	bxe_stop_locked(sc);
5040	bxe_init_locked(sc);
5041	BXE_CORE_UNLOCK(sc);
5042    }
5043
5044    return (error);
5045}
5046
5047static __noinline void
5048bxe_dump_mbuf(struct bxe_softc *sc,
5049              struct mbuf      *m,
5050              uint8_t          contents)
5051{
5052    char * type;
5053    int i = 0;
5054
5055    if (!(sc->debug & DBG_MBUF)) {
5056        return;
5057    }
5058
5059    if (m == NULL) {
5060        BLOGD(sc, DBG_MBUF, "mbuf: null pointer\n");
5061        return;
5062    }
5063
5064    while (m) {
5065        BLOGD(sc, DBG_MBUF,
5066              "%02d: mbuf=%p m_len=%d m_flags=0x%b m_data=%p\n",
5067              i, m, m->m_len, m->m_flags, M_FLAG_BITS, m->m_data);
5068
5069        if (m->m_flags & M_PKTHDR) {
5070             BLOGD(sc, DBG_MBUF,
5071                   "%02d: - m_pkthdr: tot_len=%d flags=0x%b csum_flags=%b\n",
5072                   i, m->m_pkthdr.len, m->m_flags, M_FLAG_BITS,
5073                   (int)m->m_pkthdr.csum_flags, CSUM_BITS);
5074        }
5075
5076        if (m->m_flags & M_EXT) {
5077            switch (m->m_ext.ext_type) {
5078            case EXT_CLUSTER:    type = "EXT_CLUSTER";    break;
5079            case EXT_SFBUF:      type = "EXT_SFBUF";      break;
5080            case EXT_JUMBOP:     type = "EXT_JUMBOP";     break;
5081            case EXT_JUMBO9:     type = "EXT_JUMBO9";     break;
5082            case EXT_JUMBO16:    type = "EXT_JUMBO16";    break;
5083            case EXT_PACKET:     type = "EXT_PACKET";     break;
5084            case EXT_MBUF:       type = "EXT_MBUF";       break;
5085            case EXT_NET_DRV:    type = "EXT_NET_DRV";    break;
5086            case EXT_MOD_TYPE:   type = "EXT_MOD_TYPE";   break;
5087            case EXT_DISPOSABLE: type = "EXT_DISPOSABLE"; break;
5088            case EXT_EXTREF:     type = "EXT_EXTREF";     break;
5089            default:             type = "UNKNOWN";        break;
5090            }
5091
5092            BLOGD(sc, DBG_MBUF,
5093                  "%02d: - m_ext: %p ext_size=%d type=%s\n",
5094                  i, m->m_ext.ext_buf, m->m_ext.ext_size, type);
5095        }
5096
5097        if (contents) {
5098            bxe_dump_mbuf_data(sc, "mbuf data", m, TRUE);
5099        }
5100
5101        m = m->m_next;
5102        i++;
5103    }
5104}
5105
5106/*
5107 * Checks to ensure the 13 bd sliding window is >= MSS for TSO.
5108 * Check that (13 total bds - 3 bds) = 10 bd window >= MSS.
5109 * The window: 3 bds are = 1 for headers BD + 2 for parse BD and last BD
5110 * The headers comes in a seperate bd in FreeBSD so 13-3=10.
5111 * Returns: 0 if OK to send, 1 if packet needs further defragmentation
5112 */
5113static int
5114bxe_chktso_window(struct bxe_softc  *sc,
5115                  int               nsegs,
5116                  bus_dma_segment_t *segs,
5117                  struct mbuf       *m)
5118{
5119    uint32_t num_wnds, wnd_size, wnd_sum;
5120    int32_t frag_idx, wnd_idx;
5121    unsigned short lso_mss;
5122    int defrag;
5123
5124    defrag = 0;
5125    wnd_sum = 0;
5126    wnd_size = 10;
5127    num_wnds = nsegs - wnd_size;
5128    lso_mss = htole16(m->m_pkthdr.tso_segsz);
5129
5130    /*
5131     * Total header lengths Eth+IP+TCP in first FreeBSD mbuf so calculate the
5132     * first window sum of data while skipping the first assuming it is the
5133     * header in FreeBSD.
5134     */
5135    for (frag_idx = 1; (frag_idx <= wnd_size); frag_idx++) {
5136        wnd_sum += htole16(segs[frag_idx].ds_len);
5137    }
5138
5139    /* check the first 10 bd window size */
5140    if (wnd_sum < lso_mss) {
5141        return (1);
5142    }
5143
5144    /* run through the windows */
5145    for (wnd_idx = 0; wnd_idx < num_wnds; wnd_idx++, frag_idx++) {
5146        /* subtract the first mbuf->m_len of the last wndw(-header) */
5147        wnd_sum -= htole16(segs[wnd_idx+1].ds_len);
5148        /* add the next mbuf len to the len of our new window */
5149        wnd_sum += htole16(segs[frag_idx].ds_len);
5150        if (wnd_sum < lso_mss) {
5151            return (1);
5152        }
5153    }
5154
5155    return (0);
5156}
5157
5158static uint8_t
5159bxe_set_pbd_csum_e2(struct bxe_fastpath *fp,
5160                    struct mbuf         *m,
5161                    uint32_t            *parsing_data)
5162{
5163    struct ether_vlan_header *eh = NULL;
5164    struct ip *ip4 = NULL;
5165    struct ip6_hdr *ip6 = NULL;
5166    caddr_t ip = NULL;
5167    struct tcphdr *th = NULL;
5168    int e_hlen, ip_hlen, l4_off;
5169    uint16_t proto;
5170
5171    if (m->m_pkthdr.csum_flags == CSUM_IP) {
5172        /* no L4 checksum offload needed */
5173        return (0);
5174    }
5175
5176    /* get the Ethernet header */
5177    eh = mtod(m, struct ether_vlan_header *);
5178
5179    /* handle VLAN encapsulation if present */
5180    if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
5181        e_hlen = (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN);
5182        proto  = ntohs(eh->evl_proto);
5183    } else {
5184        e_hlen = ETHER_HDR_LEN;
5185        proto  = ntohs(eh->evl_encap_proto);
5186    }
5187
5188    switch (proto) {
5189    case ETHERTYPE_IP:
5190        /* get the IP header, if mbuf len < 20 then header in next mbuf */
5191        ip4 = (m->m_len < sizeof(struct ip)) ?
5192                  (struct ip *)m->m_next->m_data :
5193                  (struct ip *)(m->m_data + e_hlen);
5194        /* ip_hl is number of 32-bit words */
5195        ip_hlen = (ip4->ip_hl << 2);
5196        ip = (caddr_t)ip4;
5197        break;
5198    case ETHERTYPE_IPV6:
5199        /* get the IPv6 header, if mbuf len < 40 then header in next mbuf */
5200        ip6 = (m->m_len < sizeof(struct ip6_hdr)) ?
5201                  (struct ip6_hdr *)m->m_next->m_data :
5202                  (struct ip6_hdr *)(m->m_data + e_hlen);
5203        /* XXX cannot support offload with IPv6 extensions */
5204        ip_hlen = sizeof(struct ip6_hdr);
5205        ip = (caddr_t)ip6;
5206        break;
5207    default:
5208        /* We can't offload in this case... */
5209        /* XXX error stat ??? */
5210        return (0);
5211    }
5212
5213    /* XXX assuming L4 header is contiguous to IPv4/IPv6 in the same mbuf */
5214    l4_off = (e_hlen + ip_hlen);
5215
5216    *parsing_data |=
5217        (((l4_off >> 1) << ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W_SHIFT) &
5218         ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W);
5219
5220    if (m->m_pkthdr.csum_flags & (CSUM_TCP |
5221                                  CSUM_TSO |
5222                                  CSUM_TCP_IPV6)) {
5223        fp->eth_q_stats.tx_ofld_frames_csum_tcp++;
5224        th = (struct tcphdr *)(ip + ip_hlen);
5225        /* th_off is number of 32-bit words */
5226        *parsing_data |= ((th->th_off <<
5227                           ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT) &
5228                          ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW);
5229        return (l4_off + (th->th_off << 2)); /* entire header length */
5230    } else if (m->m_pkthdr.csum_flags & (CSUM_UDP |
5231                                         CSUM_UDP_IPV6)) {
5232        fp->eth_q_stats.tx_ofld_frames_csum_udp++;
5233        return (l4_off + sizeof(struct udphdr)); /* entire header length */
5234    } else {
5235        /* XXX error stat ??? */
5236        return (0);
5237    }
5238}
5239
5240static uint8_t
5241bxe_set_pbd_csum(struct bxe_fastpath        *fp,
5242                 struct mbuf                *m,
5243                 struct eth_tx_parse_bd_e1x *pbd)
5244{
5245    struct ether_vlan_header *eh = NULL;
5246    struct ip *ip4 = NULL;
5247    struct ip6_hdr *ip6 = NULL;
5248    caddr_t ip = NULL;
5249    struct tcphdr *th = NULL;
5250    struct udphdr *uh = NULL;
5251    int e_hlen, ip_hlen;
5252    uint16_t proto;
5253    uint8_t hlen;
5254    uint16_t tmp_csum;
5255    uint32_t *tmp_uh;
5256
5257    /* get the Ethernet header */
5258    eh = mtod(m, struct ether_vlan_header *);
5259
5260    /* handle VLAN encapsulation if present */
5261    if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
5262        e_hlen = (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN);
5263        proto  = ntohs(eh->evl_proto);
5264    } else {
5265        e_hlen = ETHER_HDR_LEN;
5266        proto  = ntohs(eh->evl_encap_proto);
5267    }
5268
5269    switch (proto) {
5270    case ETHERTYPE_IP:
5271        /* get the IP header, if mbuf len < 20 then header in next mbuf */
5272        ip4 = (m->m_len < sizeof(struct ip)) ?
5273                  (struct ip *)m->m_next->m_data :
5274                  (struct ip *)(m->m_data + e_hlen);
5275        /* ip_hl is number of 32-bit words */
5276        ip_hlen = (ip4->ip_hl << 1);
5277        ip = (caddr_t)ip4;
5278        break;
5279    case ETHERTYPE_IPV6:
5280        /* get the IPv6 header, if mbuf len < 40 then header in next mbuf */
5281        ip6 = (m->m_len < sizeof(struct ip6_hdr)) ?
5282                  (struct ip6_hdr *)m->m_next->m_data :
5283                  (struct ip6_hdr *)(m->m_data + e_hlen);
5284        /* XXX cannot support offload with IPv6 extensions */
5285        ip_hlen = (sizeof(struct ip6_hdr) >> 1);
5286        ip = (caddr_t)ip6;
5287        break;
5288    default:
5289        /* We can't offload in this case... */
5290        /* XXX error stat ??? */
5291        return (0);
5292    }
5293
5294    hlen = (e_hlen >> 1);
5295
5296    /* note that rest of global_data is indirectly zeroed here */
5297    if (m->m_flags & M_VLANTAG) {
5298        pbd->global_data =
5299            htole16(hlen | (1 << ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN_SHIFT));
5300    } else {
5301        pbd->global_data = htole16(hlen);
5302    }
5303
5304    pbd->ip_hlen_w = ip_hlen;
5305
5306    hlen += pbd->ip_hlen_w;
5307
5308    /* XXX assuming L4 header is contiguous to IPv4/IPv6 in the same mbuf */
5309
5310    if (m->m_pkthdr.csum_flags & (CSUM_TCP |
5311                                  CSUM_TSO |
5312                                  CSUM_TCP_IPV6)) {
5313        th = (struct tcphdr *)(ip + (ip_hlen << 1));
5314        /* th_off is number of 32-bit words */
5315        hlen += (uint16_t)(th->th_off << 1);
5316    } else if (m->m_pkthdr.csum_flags & (CSUM_UDP |
5317                                         CSUM_UDP_IPV6)) {
5318        uh = (struct udphdr *)(ip + (ip_hlen << 1));
5319        hlen += (sizeof(struct udphdr) / 2);
5320    } else {
5321        /* valid case as only CSUM_IP was set */
5322        return (0);
5323    }
5324
5325    pbd->total_hlen_w = htole16(hlen);
5326
5327    if (m->m_pkthdr.csum_flags & (CSUM_TCP |
5328                                  CSUM_TSO |
5329                                  CSUM_TCP_IPV6)) {
5330        fp->eth_q_stats.tx_ofld_frames_csum_tcp++;
5331        pbd->tcp_pseudo_csum = ntohs(th->th_sum);
5332    } else if (m->m_pkthdr.csum_flags & (CSUM_UDP |
5333                                         CSUM_UDP_IPV6)) {
5334        fp->eth_q_stats.tx_ofld_frames_csum_udp++;
5335
5336        /*
5337         * Everest1 (i.e. 57710, 57711, 57711E) does not natively support UDP
5338         * checksums and does not know anything about the UDP header and where
5339         * the checksum field is located. It only knows about TCP. Therefore
5340         * we "lie" to the hardware for outgoing UDP packets w/ checksum
5341         * offload. Since the checksum field offset for TCP is 16 bytes and
5342         * for UDP it is 6 bytes we pass a pointer to the hardware that is 10
5343         * bytes less than the start of the UDP header. This allows the
5344         * hardware to write the checksum in the correct spot. But the
5345         * hardware will compute a checksum which includes the last 10 bytes
5346         * of the IP header. To correct this we tweak the stack computed
5347         * pseudo checksum by folding in the calculation of the inverse
5348         * checksum for those final 10 bytes of the IP header. This allows
5349         * the correct checksum to be computed by the hardware.
5350         */
5351
5352        /* set pointer 10 bytes before UDP header */
5353        tmp_uh = (uint32_t *)((uint8_t *)uh - 10);
5354
5355        /* calculate a pseudo header checksum over the first 10 bytes */
5356        tmp_csum = in_pseudo(*tmp_uh,
5357                             *(tmp_uh + 1),
5358                             *(uint16_t *)(tmp_uh + 2));
5359
5360        pbd->tcp_pseudo_csum = ntohs(in_addword(uh->uh_sum, ~tmp_csum));
5361    }
5362
5363    return (hlen * 2); /* entire header length, number of bytes */
5364}
5365
5366static void
5367bxe_set_pbd_lso_e2(struct mbuf *m,
5368                   uint32_t    *parsing_data)
5369{
5370    *parsing_data |= ((m->m_pkthdr.tso_segsz <<
5371                       ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT) &
5372                      ETH_TX_PARSE_BD_E2_LSO_MSS);
5373
5374    /* XXX test for IPv6 with extension header... */
5375#if 0
5376    struct ip6_hdr *ip6;
5377    if (ip6 && ip6->ip6_nxt == 'some ipv6 extension header')
5378        *parsing_data |= ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR;
5379#endif
5380}
5381
5382static void
5383bxe_set_pbd_lso(struct mbuf                *m,
5384                struct eth_tx_parse_bd_e1x *pbd)
5385{
5386    struct ether_vlan_header *eh = NULL;
5387    struct ip *ip = NULL;
5388    struct tcphdr *th = NULL;
5389    int e_hlen;
5390
5391    /* get the Ethernet header */
5392    eh = mtod(m, struct ether_vlan_header *);
5393
5394    /* handle VLAN encapsulation if present */
5395    e_hlen = (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) ?
5396                 (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN) : ETHER_HDR_LEN;
5397
5398    /* get the IP and TCP header, with LSO entire header in first mbuf */
5399    /* XXX assuming IPv4 */
5400    ip = (struct ip *)(m->m_data + e_hlen);
5401    th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
5402
5403    pbd->lso_mss = htole16(m->m_pkthdr.tso_segsz);
5404    pbd->tcp_send_seq = ntohl(th->th_seq);
5405    pbd->tcp_flags = ((ntohl(((uint32_t *)th)[3]) >> 16) & 0xff);
5406
5407#if 1
5408        /* XXX IPv4 */
5409        pbd->ip_id = ntohs(ip->ip_id);
5410        pbd->tcp_pseudo_csum =
5411            ntohs(in_pseudo(ip->ip_src.s_addr,
5412                            ip->ip_dst.s_addr,
5413                            htons(IPPROTO_TCP)));
5414#else
5415        /* XXX IPv6 */
5416        pbd->tcp_pseudo_csum =
5417            ntohs(in_pseudo(&ip6->ip6_src,
5418                            &ip6->ip6_dst,
5419                            htons(IPPROTO_TCP)));
5420#endif
5421
5422    pbd->global_data |=
5423        htole16(ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN);
5424}
5425
5426/*
5427 * Encapsulte an mbuf cluster into the tx bd chain and makes the memory
5428 * visible to the controller.
5429 *
5430 * If an mbuf is submitted to this routine and cannot be given to the
5431 * controller (e.g. it has too many fragments) then the function may free
5432 * the mbuf and return to the caller.
5433 *
5434 * Returns:
5435 *   0 = Success, !0 = Failure
5436 *   Note the side effect that an mbuf may be freed if it causes a problem.
5437 */
5438static int
5439bxe_tx_encap(struct bxe_fastpath *fp, struct mbuf **m_head)
5440{
5441    bus_dma_segment_t segs[32];
5442    struct mbuf *m0;
5443    struct bxe_sw_tx_bd *tx_buf;
5444    struct eth_tx_parse_bd_e1x *pbd_e1x = NULL;
5445    struct eth_tx_parse_bd_e2 *pbd_e2 = NULL;
5446    /* struct eth_tx_parse_2nd_bd *pbd2 = NULL; */
5447    struct eth_tx_bd *tx_data_bd;
5448    struct eth_tx_bd *tx_total_pkt_size_bd;
5449    struct eth_tx_start_bd *tx_start_bd;
5450    uint16_t bd_prod, pkt_prod, total_pkt_size;
5451    uint8_t mac_type;
5452    int defragged, error, nsegs, rc, nbds, vlan_off, ovlan;
5453    struct bxe_softc *sc;
5454    uint16_t tx_bd_avail;
5455    struct ether_vlan_header *eh;
5456    uint32_t pbd_e2_parsing_data = 0;
5457    uint8_t hlen = 0;
5458    int tmp_bd;
5459    int i;
5460
5461    sc = fp->sc;
5462
5463    M_ASSERTPKTHDR(*m_head);
5464
5465    m0 = *m_head;
5466    rc = defragged = nbds = ovlan = vlan_off = total_pkt_size = 0;
5467    tx_start_bd = NULL;
5468    tx_data_bd = NULL;
5469    tx_total_pkt_size_bd = NULL;
5470
5471    /* get the H/W pointer for packets and BDs */
5472    pkt_prod = fp->tx_pkt_prod;
5473    bd_prod = fp->tx_bd_prod;
5474
5475    mac_type = UNICAST_ADDRESS;
5476
5477    /* map the mbuf into the next open DMAable memory */
5478    tx_buf = &fp->tx_mbuf_chain[TX_BD(pkt_prod)];
5479    error = bus_dmamap_load_mbuf_sg(fp->tx_mbuf_tag,
5480                                    tx_buf->m_map, m0,
5481                                    segs, &nsegs, BUS_DMA_NOWAIT);
5482
5483    /* mapping errors */
5484    if(__predict_false(error != 0)) {
5485        fp->eth_q_stats.tx_dma_mapping_failure++;
5486        if (error == ENOMEM) {
5487            /* resource issue, try again later */
5488            rc = ENOMEM;
5489        } else if (error == EFBIG) {
5490            /* possibly recoverable with defragmentation */
5491            fp->eth_q_stats.mbuf_defrag_attempts++;
5492            m0 = m_defrag(*m_head, M_NOWAIT);
5493            if (m0 == NULL) {
5494                fp->eth_q_stats.mbuf_defrag_failures++;
5495                rc = ENOBUFS;
5496            } else {
5497                /* defrag successful, try mapping again */
5498                *m_head = m0;
5499                error = bus_dmamap_load_mbuf_sg(fp->tx_mbuf_tag,
5500                                                tx_buf->m_map, m0,
5501                                                segs, &nsegs, BUS_DMA_NOWAIT);
5502                if (error) {
5503                    fp->eth_q_stats.tx_dma_mapping_failure++;
5504                    rc = error;
5505                }
5506            }
5507        } else {
5508            /* unknown, unrecoverable mapping error */
5509            BLOGE(sc, "Unknown TX mapping error rc=%d\n", error);
5510            bxe_dump_mbuf(sc, m0, FALSE);
5511            rc = error;
5512        }
5513
5514        goto bxe_tx_encap_continue;
5515    }
5516
5517    tx_bd_avail = bxe_tx_avail(sc, fp);
5518
5519    /* make sure there is enough room in the send queue */
5520    if (__predict_false(tx_bd_avail < (nsegs + 2))) {
5521        /* Recoverable, try again later. */
5522        fp->eth_q_stats.tx_hw_queue_full++;
5523        bus_dmamap_unload(fp->tx_mbuf_tag, tx_buf->m_map);
5524        rc = ENOMEM;
5525        goto bxe_tx_encap_continue;
5526    }
5527
5528    /* capture the current H/W TX chain high watermark */
5529    if (__predict_false(fp->eth_q_stats.tx_hw_max_queue_depth <
5530                        (TX_BD_USABLE - tx_bd_avail))) {
5531        fp->eth_q_stats.tx_hw_max_queue_depth = (TX_BD_USABLE - tx_bd_avail);
5532    }
5533
5534    /* make sure it fits in the packet window */
5535    if (__predict_false(nsegs > BXE_MAX_SEGMENTS)) {
5536        /*
5537         * The mbuf may be to big for the controller to handle. If the frame
5538         * is a TSO frame we'll need to do an additional check.
5539         */
5540        if (m0->m_pkthdr.csum_flags & CSUM_TSO) {
5541            if (bxe_chktso_window(sc, nsegs, segs, m0) == 0) {
5542                goto bxe_tx_encap_continue; /* OK to send */
5543            } else {
5544                fp->eth_q_stats.tx_window_violation_tso++;
5545            }
5546        } else {
5547            fp->eth_q_stats.tx_window_violation_std++;
5548        }
5549
5550        /* lets try to defragment this mbuf and remap it */
5551        fp->eth_q_stats.mbuf_defrag_attempts++;
5552        bus_dmamap_unload(fp->tx_mbuf_tag, tx_buf->m_map);
5553
5554        m0 = m_defrag(*m_head, M_NOWAIT);
5555        if (m0 == NULL) {
5556            fp->eth_q_stats.mbuf_defrag_failures++;
5557            /* Ugh, just drop the frame... :( */
5558            rc = ENOBUFS;
5559        } else {
5560            /* defrag successful, try mapping again */
5561            *m_head = m0;
5562            error = bus_dmamap_load_mbuf_sg(fp->tx_mbuf_tag,
5563                                            tx_buf->m_map, m0,
5564                                            segs, &nsegs, BUS_DMA_NOWAIT);
5565            if (error) {
5566                fp->eth_q_stats.tx_dma_mapping_failure++;
5567                /* No sense in trying to defrag/copy chain, drop it. :( */
5568                rc = error;
5569            }
5570            else {
5571                /* if the chain is still too long then drop it */
5572                if (__predict_false(nsegs > BXE_MAX_SEGMENTS)) {
5573                    bus_dmamap_unload(fp->tx_mbuf_tag, tx_buf->m_map);
5574                    rc = ENODEV;
5575                }
5576            }
5577        }
5578    }
5579
5580bxe_tx_encap_continue:
5581
5582    /* Check for errors */
5583    if (rc) {
5584        if (rc == ENOMEM) {
5585            /* recoverable try again later  */
5586        } else {
5587            fp->eth_q_stats.tx_soft_errors++;
5588            fp->eth_q_stats.mbuf_alloc_tx--;
5589            m_freem(*m_head);
5590            *m_head = NULL;
5591        }
5592
5593        return (rc);
5594    }
5595
5596    /* set flag according to packet type (UNICAST_ADDRESS is default) */
5597    if (m0->m_flags & M_BCAST) {
5598        mac_type = BROADCAST_ADDRESS;
5599    } else if (m0->m_flags & M_MCAST) {
5600        mac_type = MULTICAST_ADDRESS;
5601    }
5602
5603    /* store the mbuf into the mbuf ring */
5604    tx_buf->m        = m0;
5605    tx_buf->first_bd = fp->tx_bd_prod;
5606    tx_buf->flags    = 0;
5607
5608    /* prepare the first transmit (start) BD for the mbuf */
5609    tx_start_bd = &fp->tx_chain[TX_BD(bd_prod)].start_bd;
5610
5611    BLOGD(sc, DBG_TX,
5612          "sending pkt_prod=%u tx_buf=%p next_idx=%u bd=%u tx_start_bd=%p\n",
5613          pkt_prod, tx_buf, fp->tx_pkt_prod, bd_prod, tx_start_bd);
5614
5615    tx_start_bd->addr_lo = htole32(U64_LO(segs[0].ds_addr));
5616    tx_start_bd->addr_hi = htole32(U64_HI(segs[0].ds_addr));
5617    tx_start_bd->nbytes  = htole16(segs[0].ds_len);
5618    total_pkt_size += tx_start_bd->nbytes;
5619    tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
5620
5621    tx_start_bd->general_data = (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
5622
5623    /* all frames have at least Start BD + Parsing BD */
5624    nbds = nsegs + 1;
5625    tx_start_bd->nbd = htole16(nbds);
5626
5627    if (m0->m_flags & M_VLANTAG) {
5628        tx_start_bd->vlan_or_ethertype = htole16(m0->m_pkthdr.ether_vtag);
5629        tx_start_bd->bd_flags.as_bitfield |=
5630            (X_ETH_OUTBAND_VLAN << ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT);
5631    } else {
5632        /* vf tx, start bd must hold the ethertype for fw to enforce it */
5633        if (IS_VF(sc)) {
5634            /* map ethernet header to find type and header length */
5635            eh = mtod(m0, struct ether_vlan_header *);
5636            tx_start_bd->vlan_or_ethertype = eh->evl_encap_proto;
5637        } else {
5638            /* used by FW for packet accounting */
5639            tx_start_bd->vlan_or_ethertype = htole16(fp->tx_pkt_prod);
5640#if 0
5641            /*
5642             * If NPAR-SD is active then FW should do the tagging regardless
5643             * of value of priority. Otherwise, if priority indicates this is
5644             * a control packet we need to indicate to FW to avoid tagging.
5645             */
5646            if (!IS_MF_AFEX(sc) && (mbuf priority == PRIO_CONTROL)) {
5647                SET_FLAG(tx_start_bd->general_data,
5648                         ETH_TX_START_BD_FORCE_VLAN_MODE, 1);
5649            }
5650#endif
5651        }
5652    }
5653
5654    /*
5655     * add a parsing BD from the chain. The parsing BD is always added
5656     * though it is only used for TSO and chksum
5657     */
5658    bd_prod = TX_BD_NEXT(bd_prod);
5659
5660    if (m0->m_pkthdr.csum_flags) {
5661        if (m0->m_pkthdr.csum_flags & CSUM_IP) {
5662            fp->eth_q_stats.tx_ofld_frames_csum_ip++;
5663            tx_start_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_IP_CSUM;
5664        }
5665
5666        if (m0->m_pkthdr.csum_flags & CSUM_TCP_IPV6) {
5667            tx_start_bd->bd_flags.as_bitfield |= (ETH_TX_BD_FLAGS_IPV6 |
5668                                                  ETH_TX_BD_FLAGS_L4_CSUM);
5669        } else if (m0->m_pkthdr.csum_flags & CSUM_UDP_IPV6) {
5670            tx_start_bd->bd_flags.as_bitfield |= (ETH_TX_BD_FLAGS_IPV6   |
5671                                                  ETH_TX_BD_FLAGS_IS_UDP |
5672                                                  ETH_TX_BD_FLAGS_L4_CSUM);
5673        } else if ((m0->m_pkthdr.csum_flags & CSUM_TCP) ||
5674                   (m0->m_pkthdr.csum_flags & CSUM_TSO)) {
5675            tx_start_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_L4_CSUM;
5676        } else if (m0->m_pkthdr.csum_flags & CSUM_UDP) {
5677            tx_start_bd->bd_flags.as_bitfield |= (ETH_TX_BD_FLAGS_L4_CSUM |
5678                                                  ETH_TX_BD_FLAGS_IS_UDP);
5679        }
5680    }
5681
5682    if (!CHIP_IS_E1x(sc)) {
5683        pbd_e2 = &fp->tx_chain[TX_BD(bd_prod)].parse_bd_e2;
5684        memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
5685
5686        if (m0->m_pkthdr.csum_flags) {
5687            hlen = bxe_set_pbd_csum_e2(fp, m0, &pbd_e2_parsing_data);
5688        }
5689
5690#if 0
5691        /*
5692         * Add the MACs to the parsing BD if the module param was
5693         * explicitly set, if this is a vf, or in switch independent
5694         * mode.
5695         */
5696        if (sc->flags & BXE_TX_SWITCHING || IS_VF(sc) || IS_MF_SI(sc)) {
5697            eh = mtod(m0, struct ether_vlan_header *);
5698            bxe_set_fw_mac_addr(&pbd_e2->data.mac_addr.src_hi,
5699                                &pbd_e2->data.mac_addr.src_mid,
5700                                &pbd_e2->data.mac_addr.src_lo,
5701                                eh->evl_shost);
5702            bxe_set_fw_mac_addr(&pbd_e2->data.mac_addr.dst_hi,
5703                                &pbd_e2->data.mac_addr.dst_mid,
5704                                &pbd_e2->data.mac_addr.dst_lo,
5705                                eh->evl_dhost);
5706        }
5707#endif
5708
5709        SET_FLAG(pbd_e2_parsing_data, ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE,
5710                 mac_type);
5711    } else {
5712        uint16_t global_data = 0;
5713
5714        pbd_e1x = &fp->tx_chain[TX_BD(bd_prod)].parse_bd_e1x;
5715        memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
5716
5717        if (m0->m_pkthdr.csum_flags) {
5718            hlen = bxe_set_pbd_csum(fp, m0, pbd_e1x);
5719        }
5720
5721        SET_FLAG(global_data,
5722                 ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE, mac_type);
5723        pbd_e1x->global_data |= htole16(global_data);
5724    }
5725
5726    /* setup the parsing BD with TSO specific info */
5727    if (m0->m_pkthdr.csum_flags & CSUM_TSO) {
5728        fp->eth_q_stats.tx_ofld_frames_lso++;
5729        tx_start_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_SW_LSO;
5730
5731        if (__predict_false(tx_start_bd->nbytes > hlen)) {
5732            fp->eth_q_stats.tx_ofld_frames_lso_hdr_splits++;
5733
5734            /* split the first BD into header/data making the fw job easy */
5735            nbds++;
5736            tx_start_bd->nbd = htole16(nbds);
5737            tx_start_bd->nbytes = htole16(hlen);
5738
5739            bd_prod = TX_BD_NEXT(bd_prod);
5740
5741            /* new transmit BD after the tx_parse_bd */
5742            tx_data_bd = &fp->tx_chain[TX_BD(bd_prod)].reg_bd;
5743            tx_data_bd->addr_hi = htole32(U64_HI(segs[0].ds_addr + hlen));
5744            tx_data_bd->addr_lo = htole32(U64_LO(segs[0].ds_addr + hlen));
5745            tx_data_bd->nbytes  = htole16(segs[0].ds_len - hlen);
5746            if (tx_total_pkt_size_bd == NULL) {
5747                tx_total_pkt_size_bd = tx_data_bd;
5748            }
5749
5750            BLOGD(sc, DBG_TX,
5751                  "TSO split header size is %d (%x:%x) nbds %d\n",
5752                  le16toh(tx_start_bd->nbytes),
5753                  le32toh(tx_start_bd->addr_hi),
5754                  le32toh(tx_start_bd->addr_lo),
5755                  nbds);
5756        }
5757
5758        if (!CHIP_IS_E1x(sc)) {
5759            bxe_set_pbd_lso_e2(m0, &pbd_e2_parsing_data);
5760        } else {
5761            bxe_set_pbd_lso(m0, pbd_e1x);
5762        }
5763    }
5764
5765    if (pbd_e2_parsing_data) {
5766        pbd_e2->parsing_data = htole32(pbd_e2_parsing_data);
5767    }
5768
5769    /* prepare remaining BDs, start tx bd contains first seg/frag */
5770    for (i = 1; i < nsegs ; i++) {
5771        bd_prod = TX_BD_NEXT(bd_prod);
5772        tx_data_bd = &fp->tx_chain[TX_BD(bd_prod)].reg_bd;
5773        tx_data_bd->addr_lo = htole32(U64_LO(segs[i].ds_addr));
5774        tx_data_bd->addr_hi = htole32(U64_HI(segs[i].ds_addr));
5775        tx_data_bd->nbytes  = htole16(segs[i].ds_len);
5776        if (tx_total_pkt_size_bd == NULL) {
5777            tx_total_pkt_size_bd = tx_data_bd;
5778        }
5779        total_pkt_size += tx_data_bd->nbytes;
5780    }
5781
5782    BLOGD(sc, DBG_TX, "last bd %p\n", tx_data_bd);
5783
5784    if (tx_total_pkt_size_bd != NULL) {
5785        tx_total_pkt_size_bd->total_pkt_bytes = total_pkt_size;
5786    }
5787
5788    if (__predict_false(sc->debug & DBG_TX)) {
5789        tmp_bd = tx_buf->first_bd;
5790        for (i = 0; i < nbds; i++)
5791        {
5792            if (i == 0) {
5793                BLOGD(sc, DBG_TX,
5794                      "TX Strt: %p bd=%d nbd=%d vlan=0x%x "
5795                      "bd_flags=0x%x hdr_nbds=%d\n",
5796                      tx_start_bd,
5797                      tmp_bd,
5798                      le16toh(tx_start_bd->nbd),
5799                      le16toh(tx_start_bd->vlan_or_ethertype),
5800                      tx_start_bd->bd_flags.as_bitfield,
5801                      (tx_start_bd->general_data & ETH_TX_START_BD_HDR_NBDS));
5802            } else if (i == 1) {
5803                if (pbd_e1x) {
5804                    BLOGD(sc, DBG_TX,
5805                          "-> Prse: %p bd=%d global=0x%x ip_hlen_w=%u "
5806                          "ip_id=%u lso_mss=%u tcp_flags=0x%x csum=0x%x "
5807                          "tcp_seq=%u total_hlen_w=%u\n",
5808                          pbd_e1x,
5809                          tmp_bd,
5810                          pbd_e1x->global_data,
5811                          pbd_e1x->ip_hlen_w,
5812                          pbd_e1x->ip_id,
5813                          pbd_e1x->lso_mss,
5814                          pbd_e1x->tcp_flags,
5815                          pbd_e1x->tcp_pseudo_csum,
5816                          pbd_e1x->tcp_send_seq,
5817                          le16toh(pbd_e1x->total_hlen_w));
5818                } else { /* if (pbd_e2) */
5819                    BLOGD(sc, DBG_TX,
5820                          "-> Parse: %p bd=%d dst=%02x:%02x:%02x "
5821                          "src=%02x:%02x:%02x parsing_data=0x%x\n",
5822                          pbd_e2,
5823                          tmp_bd,
5824                          pbd_e2->data.mac_addr.dst_hi,
5825                          pbd_e2->data.mac_addr.dst_mid,
5826                          pbd_e2->data.mac_addr.dst_lo,
5827                          pbd_e2->data.mac_addr.src_hi,
5828                          pbd_e2->data.mac_addr.src_mid,
5829                          pbd_e2->data.mac_addr.src_lo,
5830                          pbd_e2->parsing_data);
5831                }
5832            }
5833
5834            if (i != 1) { /* skip parse db as it doesn't hold data */
5835                tx_data_bd = &fp->tx_chain[TX_BD(tmp_bd)].reg_bd;
5836                BLOGD(sc, DBG_TX,
5837                      "-> Frag: %p bd=%d nbytes=%d hi=0x%x lo: 0x%x\n",
5838                      tx_data_bd,
5839                      tmp_bd,
5840                      le16toh(tx_data_bd->nbytes),
5841                      le32toh(tx_data_bd->addr_hi),
5842                      le32toh(tx_data_bd->addr_lo));
5843            }
5844
5845            tmp_bd = TX_BD_NEXT(tmp_bd);
5846        }
5847    }
5848
5849    BLOGD(sc, DBG_TX, "doorbell: nbds=%d bd=%u\n", nbds, bd_prod);
5850
5851    /* update TX BD producer index value for next TX */
5852    bd_prod = TX_BD_NEXT(bd_prod);
5853
5854    /*
5855     * If the chain of tx_bd's describing this frame is adjacent to or spans
5856     * an eth_tx_next_bd element then we need to increment the nbds value.
5857     */
5858    if (TX_BD_IDX(bd_prod) < nbds) {
5859        nbds++;
5860    }
5861
5862    /* don't allow reordering of writes for nbd and packets */
5863    mb();
5864
5865    fp->tx_db.data.prod += nbds;
5866
5867    /* producer points to the next free tx_bd at this point */
5868    fp->tx_pkt_prod++;
5869    fp->tx_bd_prod = bd_prod;
5870
5871    DOORBELL(sc, fp->index, fp->tx_db.raw);
5872
5873    fp->eth_q_stats.tx_pkts++;
5874
5875    /* Prevent speculative reads from getting ahead of the status block. */
5876    bus_space_barrier(sc->bar[BAR0].tag, sc->bar[BAR0].handle,
5877                      0, 0, BUS_SPACE_BARRIER_READ);
5878
5879    /* Prevent speculative reads from getting ahead of the doorbell. */
5880    bus_space_barrier(sc->bar[BAR2].tag, sc->bar[BAR2].handle,
5881                      0, 0, BUS_SPACE_BARRIER_READ);
5882
5883    return (0);
5884}
5885
5886static void
5887bxe_tx_start_locked(struct bxe_softc *sc,
5888                    if_t ifp,
5889                    struct bxe_fastpath *fp)
5890{
5891    struct mbuf *m = NULL;
5892    int tx_count = 0;
5893    uint16_t tx_bd_avail;
5894
5895    BXE_FP_TX_LOCK_ASSERT(fp);
5896
5897    /* keep adding entries while there are frames to send */
5898    while (!if_sendq_empty(ifp)) {
5899
5900        /*
5901         * check for any frames to send
5902         * dequeue can still be NULL even if queue is not empty
5903         */
5904        m = if_dequeue(ifp);
5905        if (__predict_false(m == NULL)) {
5906            break;
5907        }
5908
5909        /* the mbuf now belongs to us */
5910        fp->eth_q_stats.mbuf_alloc_tx++;
5911
5912        /*
5913         * Put the frame into the transmit ring. If we don't have room,
5914         * place the mbuf back at the head of the TX queue, set the
5915         * OACTIVE flag, and wait for the NIC to drain the chain.
5916         */
5917        if (__predict_false(bxe_tx_encap(fp, &m))) {
5918            fp->eth_q_stats.tx_encap_failures++;
5919            if (m != NULL) {
5920                /* mark the TX queue as full and return the frame */
5921                if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
5922		if_sendq_prepend(ifp, m);
5923                fp->eth_q_stats.mbuf_alloc_tx--;
5924                fp->eth_q_stats.tx_queue_xoff++;
5925            }
5926
5927            /* stop looking for more work */
5928            break;
5929        }
5930
5931        /* the frame was enqueued successfully */
5932        tx_count++;
5933
5934        /* send a copy of the frame to any BPF listeners. */
5935        if_etherbpfmtap(ifp, m);
5936
5937        tx_bd_avail = bxe_tx_avail(sc, fp);
5938
5939        /* handle any completions if we're running low */
5940        if (tx_bd_avail < BXE_TX_CLEANUP_THRESHOLD) {
5941            /* bxe_txeof will set IFF_DRV_OACTIVE appropriately */
5942            bxe_txeof(sc, fp);
5943            if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE) {
5944                break;
5945            }
5946        }
5947    }
5948
5949    /* all TX packets were dequeued and/or the tx ring is full */
5950    if (tx_count > 0) {
5951        /* reset the TX watchdog timeout timer */
5952        fp->watchdog_timer = BXE_TX_TIMEOUT;
5953    }
5954}
5955
5956/* Legacy (non-RSS) dispatch routine */
5957static void
5958bxe_tx_start(if_t ifp)
5959{
5960    struct bxe_softc *sc;
5961    struct bxe_fastpath *fp;
5962
5963    sc = if_getsoftc(ifp);
5964
5965    if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) {
5966        BLOGW(sc, "Interface not running, ignoring transmit request\n");
5967        return;
5968    }
5969
5970    if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE) {
5971        BLOGW(sc, "Interface TX queue is full, ignoring transmit request\n");
5972        return;
5973    }
5974
5975    if (!sc->link_vars.link_up) {
5976        BLOGW(sc, "Interface link is down, ignoring transmit request\n");
5977        return;
5978    }
5979
5980    fp = &sc->fp[0];
5981
5982    BXE_FP_TX_LOCK(fp);
5983    bxe_tx_start_locked(sc, ifp, fp);
5984    BXE_FP_TX_UNLOCK(fp);
5985}
5986
5987#if __FreeBSD_version >= 800000
5988
5989static int
5990bxe_tx_mq_start_locked(struct bxe_softc    *sc,
5991                       if_t                ifp,
5992                       struct bxe_fastpath *fp,
5993                       struct mbuf         *m)
5994{
5995    struct buf_ring *tx_br = fp->tx_br;
5996    struct mbuf *next;
5997    int depth, rc, tx_count;
5998    uint16_t tx_bd_avail;
5999
6000    rc = tx_count = 0;
6001
6002    BXE_FP_TX_LOCK_ASSERT(fp);
6003
6004    if (!tx_br) {
6005        BLOGE(sc, "Multiqueue TX and no buf_ring!\n");
6006        return (EINVAL);
6007    }
6008
6009    if (!sc->link_vars.link_up ||
6010        (ifp->if_drv_flags &
6011        (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != IFF_DRV_RUNNING) {
6012        rc = drbr_enqueue_drv(ifp, tx_br, m);
6013        goto bxe_tx_mq_start_locked_exit;
6014    }
6015
6016    /* fetch the depth of the driver queue */
6017    depth = drbr_inuse_drv(ifp, tx_br);
6018    if (depth > fp->eth_q_stats.tx_max_drbr_queue_depth) {
6019        fp->eth_q_stats.tx_max_drbr_queue_depth = depth;
6020    }
6021
6022    if (m == NULL) {
6023        /* no new work, check for pending frames */
6024        next = drbr_dequeue_drv(ifp, tx_br);
6025    } else if (drbr_needs_enqueue_drv(ifp, tx_br)) {
6026        /* have both new and pending work, maintain packet order */
6027        rc = drbr_enqueue_drv(ifp, tx_br, m);
6028        if (rc != 0) {
6029            fp->eth_q_stats.tx_soft_errors++;
6030            goto bxe_tx_mq_start_locked_exit;
6031        }
6032        next = drbr_dequeue_drv(ifp, tx_br);
6033    } else {
6034        /* new work only and nothing pending */
6035        next = m;
6036    }
6037
6038    /* keep adding entries while there are frames to send */
6039    while (next != NULL) {
6040
6041        /* the mbuf now belongs to us */
6042        fp->eth_q_stats.mbuf_alloc_tx++;
6043
6044        /*
6045         * Put the frame into the transmit ring. If we don't have room,
6046         * place the mbuf back at the head of the TX queue, set the
6047         * OACTIVE flag, and wait for the NIC to drain the chain.
6048         */
6049        rc = bxe_tx_encap(fp, &next);
6050        if (__predict_false(rc != 0)) {
6051            fp->eth_q_stats.tx_encap_failures++;
6052            if (next != NULL) {
6053                /* mark the TX queue as full and save the frame */
6054                if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
6055                /* XXX this may reorder the frame */
6056                rc = drbr_enqueue_drv(ifp, tx_br, next);
6057                fp->eth_q_stats.mbuf_alloc_tx--;
6058                fp->eth_q_stats.tx_frames_deferred++;
6059            }
6060
6061            /* stop looking for more work */
6062            break;
6063        }
6064
6065        /* the transmit frame was enqueued successfully */
6066        tx_count++;
6067
6068        /* send a copy of the frame to any BPF listeners */
6069	if_etherbpfmtap(ifp, next);
6070
6071        tx_bd_avail = bxe_tx_avail(sc, fp);
6072
6073        /* handle any completions if we're running low */
6074        if (tx_bd_avail < BXE_TX_CLEANUP_THRESHOLD) {
6075            /* bxe_txeof will set IFF_DRV_OACTIVE appropriately */
6076            bxe_txeof(sc, fp);
6077            if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE) {
6078                break;
6079            }
6080        }
6081
6082        next = drbr_dequeue_drv(ifp, tx_br);
6083    }
6084
6085    /* all TX packets were dequeued and/or the tx ring is full */
6086    if (tx_count > 0) {
6087        /* reset the TX watchdog timeout timer */
6088        fp->watchdog_timer = BXE_TX_TIMEOUT;
6089    }
6090
6091bxe_tx_mq_start_locked_exit:
6092
6093    return (rc);
6094}
6095
6096/* Multiqueue (TSS) dispatch routine. */
6097static int
6098bxe_tx_mq_start(struct ifnet *ifp,
6099                struct mbuf  *m)
6100{
6101    struct bxe_softc *sc = if_getsoftc(ifp);
6102    struct bxe_fastpath *fp;
6103    int fp_index, rc;
6104
6105    fp_index = 0; /* default is the first queue */
6106
6107    /* check if flowid is set */
6108    if (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE)
6109        fp_index = (m->m_pkthdr.flowid % sc->num_queues);
6110
6111    fp = &sc->fp[fp_index];
6112
6113    if (BXE_FP_TX_TRYLOCK(fp)) {
6114        rc = bxe_tx_mq_start_locked(sc, ifp, fp, m);
6115        BXE_FP_TX_UNLOCK(fp);
6116    } else
6117        rc = drbr_enqueue_drv(ifp, fp->tx_br, m);
6118
6119    return (rc);
6120}
6121
6122static void
6123bxe_mq_flush(struct ifnet *ifp)
6124{
6125    struct bxe_softc *sc = if_getsoftc(ifp);
6126    struct bxe_fastpath *fp;
6127    struct mbuf *m;
6128    int i;
6129
6130    for (i = 0; i < sc->num_queues; i++) {
6131        fp = &sc->fp[i];
6132
6133        if (fp->state != BXE_FP_STATE_OPEN) {
6134            BLOGD(sc, DBG_LOAD, "Not clearing fp[%02d] buf_ring (state=%d)\n",
6135                  fp->index, fp->state);
6136            continue;
6137        }
6138
6139        if (fp->tx_br != NULL) {
6140            BLOGD(sc, DBG_LOAD, "Clearing fp[%02d] buf_ring\n", fp->index);
6141            BXE_FP_TX_LOCK(fp);
6142            while ((m = buf_ring_dequeue_sc(fp->tx_br)) != NULL) {
6143                m_freem(m);
6144            }
6145            BXE_FP_TX_UNLOCK(fp);
6146        }
6147    }
6148
6149    if_qflush(ifp);
6150}
6151
6152#endif /* FreeBSD_version >= 800000 */
6153
6154static uint16_t
6155bxe_cid_ilt_lines(struct bxe_softc *sc)
6156{
6157    if (IS_SRIOV(sc)) {
6158        return ((BXE_FIRST_VF_CID + BXE_VF_CIDS) / ILT_PAGE_CIDS);
6159    }
6160    return (L2_ILT_LINES(sc));
6161}
6162
6163static void
6164bxe_ilt_set_info(struct bxe_softc *sc)
6165{
6166    struct ilt_client_info *ilt_client;
6167    struct ecore_ilt *ilt = sc->ilt;
6168    uint16_t line = 0;
6169
6170    ilt->start_line = FUNC_ILT_BASE(SC_FUNC(sc));
6171    BLOGD(sc, DBG_LOAD, "ilt starts at line %d\n", ilt->start_line);
6172
6173    /* CDU */
6174    ilt_client = &ilt->clients[ILT_CLIENT_CDU];
6175    ilt_client->client_num = ILT_CLIENT_CDU;
6176    ilt_client->page_size = CDU_ILT_PAGE_SZ;
6177    ilt_client->flags = ILT_CLIENT_SKIP_MEM;
6178    ilt_client->start = line;
6179    line += bxe_cid_ilt_lines(sc);
6180
6181    if (CNIC_SUPPORT(sc)) {
6182        line += CNIC_ILT_LINES;
6183    }
6184
6185    ilt_client->end = (line - 1);
6186
6187    BLOGD(sc, DBG_LOAD,
6188          "ilt client[CDU]: start %d, end %d, "
6189          "psz 0x%x, flags 0x%x, hw psz %d\n",
6190          ilt_client->start, ilt_client->end,
6191          ilt_client->page_size,
6192          ilt_client->flags,
6193          ilog2(ilt_client->page_size >> 12));
6194
6195    /* QM */
6196    if (QM_INIT(sc->qm_cid_count)) {
6197        ilt_client = &ilt->clients[ILT_CLIENT_QM];
6198        ilt_client->client_num = ILT_CLIENT_QM;
6199        ilt_client->page_size = QM_ILT_PAGE_SZ;
6200        ilt_client->flags = 0;
6201        ilt_client->start = line;
6202
6203        /* 4 bytes for each cid */
6204        line += DIV_ROUND_UP(sc->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
6205                             QM_ILT_PAGE_SZ);
6206
6207        ilt_client->end = (line - 1);
6208
6209        BLOGD(sc, DBG_LOAD,
6210              "ilt client[QM]: start %d, end %d, "
6211              "psz 0x%x, flags 0x%x, hw psz %d\n",
6212              ilt_client->start, ilt_client->end,
6213              ilt_client->page_size, ilt_client->flags,
6214              ilog2(ilt_client->page_size >> 12));
6215    }
6216
6217    if (CNIC_SUPPORT(sc)) {
6218        /* SRC */
6219        ilt_client = &ilt->clients[ILT_CLIENT_SRC];
6220        ilt_client->client_num = ILT_CLIENT_SRC;
6221        ilt_client->page_size = SRC_ILT_PAGE_SZ;
6222        ilt_client->flags = 0;
6223        ilt_client->start = line;
6224        line += SRC_ILT_LINES;
6225        ilt_client->end = (line - 1);
6226
6227        BLOGD(sc, DBG_LOAD,
6228              "ilt client[SRC]: start %d, end %d, "
6229              "psz 0x%x, flags 0x%x, hw psz %d\n",
6230              ilt_client->start, ilt_client->end,
6231              ilt_client->page_size, ilt_client->flags,
6232              ilog2(ilt_client->page_size >> 12));
6233
6234        /* TM */
6235        ilt_client = &ilt->clients[ILT_CLIENT_TM];
6236        ilt_client->client_num = ILT_CLIENT_TM;
6237        ilt_client->page_size = TM_ILT_PAGE_SZ;
6238        ilt_client->flags = 0;
6239        ilt_client->start = line;
6240        line += TM_ILT_LINES;
6241        ilt_client->end = (line - 1);
6242
6243        BLOGD(sc, DBG_LOAD,
6244              "ilt client[TM]: start %d, end %d, "
6245              "psz 0x%x, flags 0x%x, hw psz %d\n",
6246              ilt_client->start, ilt_client->end,
6247              ilt_client->page_size, ilt_client->flags,
6248              ilog2(ilt_client->page_size >> 12));
6249    }
6250
6251    KASSERT((line <= ILT_MAX_LINES), ("Invalid number of ILT lines!"));
6252}
6253
6254static void
6255bxe_set_fp_rx_buf_size(struct bxe_softc *sc)
6256{
6257    int i;
6258    uint32_t rx_buf_size;
6259
6260    rx_buf_size = (IP_HEADER_ALIGNMENT_PADDING + ETH_OVERHEAD + sc->mtu);
6261
6262    for (i = 0; i < sc->num_queues; i++) {
6263        if(rx_buf_size <= MCLBYTES){
6264            sc->fp[i].rx_buf_size = rx_buf_size;
6265            sc->fp[i].mbuf_alloc_size = MCLBYTES;
6266        }else if (rx_buf_size <= MJUMPAGESIZE){
6267            sc->fp[i].rx_buf_size = rx_buf_size;
6268            sc->fp[i].mbuf_alloc_size = MJUMPAGESIZE;
6269        }else if (rx_buf_size <= (MJUMPAGESIZE + MCLBYTES)){
6270            sc->fp[i].rx_buf_size = MCLBYTES;
6271            sc->fp[i].mbuf_alloc_size = MCLBYTES;
6272        }else if (rx_buf_size <= (2 * MJUMPAGESIZE)){
6273            sc->fp[i].rx_buf_size = MJUMPAGESIZE;
6274            sc->fp[i].mbuf_alloc_size = MJUMPAGESIZE;
6275        }else {
6276            sc->fp[i].rx_buf_size = MCLBYTES;
6277            sc->fp[i].mbuf_alloc_size = MCLBYTES;
6278        }
6279    }
6280}
6281
6282static int
6283bxe_alloc_ilt_mem(struct bxe_softc *sc)
6284{
6285    int rc = 0;
6286
6287    if ((sc->ilt =
6288         (struct ecore_ilt *)malloc(sizeof(struct ecore_ilt),
6289                                    M_BXE_ILT,
6290                                    (M_NOWAIT | M_ZERO))) == NULL) {
6291        rc = 1;
6292    }
6293
6294    return (rc);
6295}
6296
6297static int
6298bxe_alloc_ilt_lines_mem(struct bxe_softc *sc)
6299{
6300    int rc = 0;
6301
6302    if ((sc->ilt->lines =
6303         (struct ilt_line *)malloc((sizeof(struct ilt_line) * ILT_MAX_LINES),
6304                                    M_BXE_ILT,
6305                                    (M_NOWAIT | M_ZERO))) == NULL) {
6306        rc = 1;
6307    }
6308
6309    return (rc);
6310}
6311
6312static void
6313bxe_free_ilt_mem(struct bxe_softc *sc)
6314{
6315    if (sc->ilt != NULL) {
6316        free(sc->ilt, M_BXE_ILT);
6317        sc->ilt = NULL;
6318    }
6319}
6320
6321static void
6322bxe_free_ilt_lines_mem(struct bxe_softc *sc)
6323{
6324    if (sc->ilt->lines != NULL) {
6325        free(sc->ilt->lines, M_BXE_ILT);
6326        sc->ilt->lines = NULL;
6327    }
6328}
6329
6330static void
6331bxe_free_mem(struct bxe_softc *sc)
6332{
6333    int i;
6334
6335#if 0
6336    if (!CONFIGURE_NIC_MODE(sc)) {
6337        /* free searcher T2 table */
6338        bxe_dma_free(sc, &sc->t2);
6339    }
6340#endif
6341
6342    for (i = 0; i < L2_ILT_LINES(sc); i++) {
6343        bxe_dma_free(sc, &sc->context[i].vcxt_dma);
6344        sc->context[i].vcxt = NULL;
6345        sc->context[i].size = 0;
6346    }
6347
6348    ecore_ilt_mem_op(sc, ILT_MEMOP_FREE);
6349
6350    bxe_free_ilt_lines_mem(sc);
6351
6352#if 0
6353    bxe_iov_free_mem(sc);
6354#endif
6355}
6356
6357static int
6358bxe_alloc_mem(struct bxe_softc *sc)
6359{
6360    int context_size;
6361    int allocated;
6362    int i;
6363
6364#if 0
6365    if (!CONFIGURE_NIC_MODE(sc)) {
6366        /* allocate searcher T2 table */
6367        if (bxe_dma_alloc(sc, SRC_T2_SZ,
6368                          &sc->t2, "searcher t2 table") != 0) {
6369            return (-1);
6370        }
6371    }
6372#endif
6373
6374    /*
6375     * Allocate memory for CDU context:
6376     * This memory is allocated separately and not in the generic ILT
6377     * functions because CDU differs in few aspects:
6378     * 1. There can be multiple entities allocating memory for context -
6379     * regular L2, CNIC, and SRIOV drivers. Each separately controls
6380     * its own ILT lines.
6381     * 2. Since CDU page-size is not a single 4KB page (which is the case
6382     * for the other ILT clients), to be efficient we want to support
6383     * allocation of sub-page-size in the last entry.
6384     * 3. Context pointers are used by the driver to pass to FW / update
6385     * the context (for the other ILT clients the pointers are used just to
6386     * free the memory during unload).
6387     */
6388    context_size = (sizeof(union cdu_context) * BXE_L2_CID_COUNT(sc));
6389    for (i = 0, allocated = 0; allocated < context_size; i++) {
6390        sc->context[i].size = min(CDU_ILT_PAGE_SZ,
6391                                  (context_size - allocated));
6392
6393        if (bxe_dma_alloc(sc, sc->context[i].size,
6394                          &sc->context[i].vcxt_dma,
6395                          "cdu context") != 0) {
6396            bxe_free_mem(sc);
6397            return (-1);
6398        }
6399
6400        sc->context[i].vcxt =
6401            (union cdu_context *)sc->context[i].vcxt_dma.vaddr;
6402
6403        allocated += sc->context[i].size;
6404    }
6405
6406    bxe_alloc_ilt_lines_mem(sc);
6407
6408    BLOGD(sc, DBG_LOAD, "ilt=%p start_line=%u lines=%p\n",
6409          sc->ilt, sc->ilt->start_line, sc->ilt->lines);
6410    {
6411        for (i = 0; i < 4; i++) {
6412            BLOGD(sc, DBG_LOAD,
6413                  "c%d page_size=%u start=%u end=%u num=%u flags=0x%x\n",
6414                  i,
6415                  sc->ilt->clients[i].page_size,
6416                  sc->ilt->clients[i].start,
6417                  sc->ilt->clients[i].end,
6418                  sc->ilt->clients[i].client_num,
6419                  sc->ilt->clients[i].flags);
6420        }
6421    }
6422    if (ecore_ilt_mem_op(sc, ILT_MEMOP_ALLOC)) {
6423        BLOGE(sc, "ecore_ilt_mem_op ILT_MEMOP_ALLOC failed\n");
6424        bxe_free_mem(sc);
6425        return (-1);
6426    }
6427
6428#if 0
6429    if (bxe_iov_alloc_mem(sc)) {
6430        BLOGE(sc, "Failed to allocate memory for SRIOV\n");
6431        bxe_free_mem(sc);
6432        return (-1);
6433    }
6434#endif
6435
6436    return (0);
6437}
6438
6439static void
6440bxe_free_rx_bd_chain(struct bxe_fastpath *fp)
6441{
6442    struct bxe_softc *sc;
6443    int i;
6444
6445    sc = fp->sc;
6446
6447    if (fp->rx_mbuf_tag == NULL) {
6448        return;
6449    }
6450
6451    /* free all mbufs and unload all maps */
6452    for (i = 0; i < RX_BD_TOTAL; i++) {
6453        if (fp->rx_mbuf_chain[i].m_map != NULL) {
6454            bus_dmamap_sync(fp->rx_mbuf_tag,
6455                            fp->rx_mbuf_chain[i].m_map,
6456                            BUS_DMASYNC_POSTREAD);
6457            bus_dmamap_unload(fp->rx_mbuf_tag,
6458                              fp->rx_mbuf_chain[i].m_map);
6459        }
6460
6461        if (fp->rx_mbuf_chain[i].m != NULL) {
6462            m_freem(fp->rx_mbuf_chain[i].m);
6463            fp->rx_mbuf_chain[i].m = NULL;
6464            fp->eth_q_stats.mbuf_alloc_rx--;
6465        }
6466    }
6467}
6468
6469static void
6470bxe_free_tpa_pool(struct bxe_fastpath *fp)
6471{
6472    struct bxe_softc *sc;
6473    int i, max_agg_queues;
6474
6475    sc = fp->sc;
6476
6477    if (fp->rx_mbuf_tag == NULL) {
6478        return;
6479    }
6480
6481    max_agg_queues = MAX_AGG_QS(sc);
6482
6483    /* release all mbufs and unload all DMA maps in the TPA pool */
6484    for (i = 0; i < max_agg_queues; i++) {
6485        if (fp->rx_tpa_info[i].bd.m_map != NULL) {
6486            bus_dmamap_sync(fp->rx_mbuf_tag,
6487                            fp->rx_tpa_info[i].bd.m_map,
6488                            BUS_DMASYNC_POSTREAD);
6489            bus_dmamap_unload(fp->rx_mbuf_tag,
6490                              fp->rx_tpa_info[i].bd.m_map);
6491        }
6492
6493        if (fp->rx_tpa_info[i].bd.m != NULL) {
6494            m_freem(fp->rx_tpa_info[i].bd.m);
6495            fp->rx_tpa_info[i].bd.m = NULL;
6496            fp->eth_q_stats.mbuf_alloc_tpa--;
6497        }
6498    }
6499}
6500
6501static void
6502bxe_free_sge_chain(struct bxe_fastpath *fp)
6503{
6504    struct bxe_softc *sc;
6505    int i;
6506
6507    sc = fp->sc;
6508
6509    if (fp->rx_sge_mbuf_tag == NULL) {
6510        return;
6511    }
6512
6513    /* rree all mbufs and unload all maps */
6514    for (i = 0; i < RX_SGE_TOTAL; i++) {
6515        if (fp->rx_sge_mbuf_chain[i].m_map != NULL) {
6516            bus_dmamap_sync(fp->rx_sge_mbuf_tag,
6517                            fp->rx_sge_mbuf_chain[i].m_map,
6518                            BUS_DMASYNC_POSTREAD);
6519            bus_dmamap_unload(fp->rx_sge_mbuf_tag,
6520                              fp->rx_sge_mbuf_chain[i].m_map);
6521        }
6522
6523        if (fp->rx_sge_mbuf_chain[i].m != NULL) {
6524            m_freem(fp->rx_sge_mbuf_chain[i].m);
6525            fp->rx_sge_mbuf_chain[i].m = NULL;
6526            fp->eth_q_stats.mbuf_alloc_sge--;
6527        }
6528    }
6529}
6530
6531static void
6532bxe_free_fp_buffers(struct bxe_softc *sc)
6533{
6534    struct bxe_fastpath *fp;
6535    int i;
6536
6537    for (i = 0; i < sc->num_queues; i++) {
6538        fp = &sc->fp[i];
6539
6540#if __FreeBSD_version >= 800000
6541        if (fp->tx_br != NULL) {
6542            /* just in case bxe_mq_flush() wasn't called */
6543            if (mtx_initialized(&fp->tx_mtx)) {
6544                struct mbuf *m;
6545
6546                BXE_FP_TX_LOCK(fp);
6547                while ((m = buf_ring_dequeue_sc(fp->tx_br)) != NULL)
6548                    m_freem(m);
6549                BXE_FP_TX_UNLOCK(fp);
6550            }
6551            buf_ring_free(fp->tx_br, M_DEVBUF);
6552            fp->tx_br = NULL;
6553        }
6554#endif
6555
6556        /* free all RX buffers */
6557        bxe_free_rx_bd_chain(fp);
6558        bxe_free_tpa_pool(fp);
6559        bxe_free_sge_chain(fp);
6560
6561        if (fp->eth_q_stats.mbuf_alloc_rx != 0) {
6562            BLOGE(sc, "failed to claim all rx mbufs (%d left)\n",
6563                  fp->eth_q_stats.mbuf_alloc_rx);
6564        }
6565
6566        if (fp->eth_q_stats.mbuf_alloc_sge != 0) {
6567            BLOGE(sc, "failed to claim all sge mbufs (%d left)\n",
6568                  fp->eth_q_stats.mbuf_alloc_sge);
6569        }
6570
6571        if (fp->eth_q_stats.mbuf_alloc_tpa != 0) {
6572            BLOGE(sc, "failed to claim all sge mbufs (%d left)\n",
6573                  fp->eth_q_stats.mbuf_alloc_tpa);
6574        }
6575
6576        if (fp->eth_q_stats.mbuf_alloc_tx != 0) {
6577            BLOGE(sc, "failed to release tx mbufs (%d left)\n",
6578                  fp->eth_q_stats.mbuf_alloc_tx);
6579        }
6580
6581        /* XXX verify all mbufs were reclaimed */
6582
6583        if (mtx_initialized(&fp->tx_mtx)) {
6584            mtx_destroy(&fp->tx_mtx);
6585        }
6586
6587        if (mtx_initialized(&fp->rx_mtx)) {
6588            mtx_destroy(&fp->rx_mtx);
6589        }
6590    }
6591}
6592
6593static int
6594bxe_alloc_rx_bd_mbuf(struct bxe_fastpath *fp,
6595                     uint16_t            prev_index,
6596                     uint16_t            index)
6597{
6598    struct bxe_sw_rx_bd *rx_buf;
6599    struct eth_rx_bd *rx_bd;
6600    bus_dma_segment_t segs[1];
6601    bus_dmamap_t map;
6602    struct mbuf *m;
6603    int nsegs, rc;
6604
6605    rc = 0;
6606
6607    /* allocate the new RX BD mbuf */
6608    m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, fp->mbuf_alloc_size);
6609    if (__predict_false(m == NULL)) {
6610        fp->eth_q_stats.mbuf_rx_bd_alloc_failed++;
6611        return (ENOBUFS);
6612    }
6613
6614    fp->eth_q_stats.mbuf_alloc_rx++;
6615
6616    /* initialize the mbuf buffer length */
6617    m->m_pkthdr.len = m->m_len = fp->rx_buf_size;
6618
6619    /* map the mbuf into non-paged pool */
6620    rc = bus_dmamap_load_mbuf_sg(fp->rx_mbuf_tag,
6621                                 fp->rx_mbuf_spare_map,
6622                                 m, segs, &nsegs, BUS_DMA_NOWAIT);
6623    if (__predict_false(rc != 0)) {
6624        fp->eth_q_stats.mbuf_rx_bd_mapping_failed++;
6625        m_freem(m);
6626        fp->eth_q_stats.mbuf_alloc_rx--;
6627        return (rc);
6628    }
6629
6630    /* all mbufs must map to a single segment */
6631    KASSERT((nsegs == 1), ("Too many segments, %d returned!", nsegs));
6632
6633    /* release any existing RX BD mbuf mappings */
6634
6635    if (prev_index != index) {
6636        rx_buf = &fp->rx_mbuf_chain[prev_index];
6637
6638        if (rx_buf->m_map != NULL) {
6639            bus_dmamap_sync(fp->rx_mbuf_tag, rx_buf->m_map,
6640                            BUS_DMASYNC_POSTREAD);
6641            bus_dmamap_unload(fp->rx_mbuf_tag, rx_buf->m_map);
6642        }
6643
6644        /*
6645         * We only get here from bxe_rxeof() when the maximum number
6646         * of rx buffers is less than RX_BD_USABLE. bxe_rxeof() already
6647         * holds the mbuf in the prev_index so it's OK to NULL it out
6648         * here without concern of a memory leak.
6649         */
6650        fp->rx_mbuf_chain[prev_index].m = NULL;
6651    }
6652
6653    rx_buf = &fp->rx_mbuf_chain[index];
6654
6655    if (rx_buf->m_map != NULL) {
6656        bus_dmamap_sync(fp->rx_mbuf_tag, rx_buf->m_map,
6657                        BUS_DMASYNC_POSTREAD);
6658        bus_dmamap_unload(fp->rx_mbuf_tag, rx_buf->m_map);
6659    }
6660
6661    /* save the mbuf and mapping info for a future packet */
6662    map = (prev_index != index) ?
6663              fp->rx_mbuf_chain[prev_index].m_map : rx_buf->m_map;
6664    rx_buf->m_map = fp->rx_mbuf_spare_map;
6665    fp->rx_mbuf_spare_map = map;
6666    bus_dmamap_sync(fp->rx_mbuf_tag, rx_buf->m_map,
6667                    BUS_DMASYNC_PREREAD);
6668    rx_buf->m = m;
6669
6670    rx_bd = &fp->rx_chain[index];
6671    rx_bd->addr_hi = htole32(U64_HI(segs[0].ds_addr));
6672    rx_bd->addr_lo = htole32(U64_LO(segs[0].ds_addr));
6673
6674    return (rc);
6675}
6676
6677static int
6678bxe_alloc_rx_tpa_mbuf(struct bxe_fastpath *fp,
6679                      int                 queue)
6680{
6681    struct bxe_sw_tpa_info *tpa_info = &fp->rx_tpa_info[queue];
6682    bus_dma_segment_t segs[1];
6683    bus_dmamap_t map;
6684    struct mbuf *m;
6685    int nsegs;
6686    int rc = 0;
6687
6688    /* allocate the new TPA mbuf */
6689    m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, fp->mbuf_alloc_size);
6690    if (__predict_false(m == NULL)) {
6691        fp->eth_q_stats.mbuf_rx_tpa_alloc_failed++;
6692        return (ENOBUFS);
6693    }
6694
6695    fp->eth_q_stats.mbuf_alloc_tpa++;
6696
6697    /* initialize the mbuf buffer length */
6698    m->m_pkthdr.len = m->m_len = fp->rx_buf_size;
6699
6700    /* map the mbuf into non-paged pool */
6701    rc = bus_dmamap_load_mbuf_sg(fp->rx_mbuf_tag,
6702                                 fp->rx_tpa_info_mbuf_spare_map,
6703                                 m, segs, &nsegs, BUS_DMA_NOWAIT);
6704    if (__predict_false(rc != 0)) {
6705        fp->eth_q_stats.mbuf_rx_tpa_mapping_failed++;
6706        m_free(m);
6707        fp->eth_q_stats.mbuf_alloc_tpa--;
6708        return (rc);
6709    }
6710
6711    /* all mbufs must map to a single segment */
6712    KASSERT((nsegs == 1), ("Too many segments, %d returned!", nsegs));
6713
6714    /* release any existing TPA mbuf mapping */
6715    if (tpa_info->bd.m_map != NULL) {
6716        bus_dmamap_sync(fp->rx_mbuf_tag, tpa_info->bd.m_map,
6717                        BUS_DMASYNC_POSTREAD);
6718        bus_dmamap_unload(fp->rx_mbuf_tag, tpa_info->bd.m_map);
6719    }
6720
6721    /* save the mbuf and mapping info for the TPA mbuf */
6722    map = tpa_info->bd.m_map;
6723    tpa_info->bd.m_map = fp->rx_tpa_info_mbuf_spare_map;
6724    fp->rx_tpa_info_mbuf_spare_map = map;
6725    bus_dmamap_sync(fp->rx_mbuf_tag, tpa_info->bd.m_map,
6726                    BUS_DMASYNC_PREREAD);
6727    tpa_info->bd.m = m;
6728    tpa_info->seg = segs[0];
6729
6730    return (rc);
6731}
6732
6733/*
6734 * Allocate an mbuf and assign it to the receive scatter gather chain. The
6735 * caller must take care to save a copy of the existing mbuf in the SG mbuf
6736 * chain.
6737 */
6738static int
6739bxe_alloc_rx_sge_mbuf(struct bxe_fastpath *fp,
6740                      uint16_t            index)
6741{
6742    struct bxe_sw_rx_bd *sge_buf;
6743    struct eth_rx_sge *sge;
6744    bus_dma_segment_t segs[1];
6745    bus_dmamap_t map;
6746    struct mbuf *m;
6747    int nsegs;
6748    int rc = 0;
6749
6750    /* allocate a new SGE mbuf */
6751    m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, SGE_PAGE_SIZE);
6752    if (__predict_false(m == NULL)) {
6753        fp->eth_q_stats.mbuf_rx_sge_alloc_failed++;
6754        return (ENOMEM);
6755    }
6756
6757    fp->eth_q_stats.mbuf_alloc_sge++;
6758
6759    /* initialize the mbuf buffer length */
6760    m->m_pkthdr.len = m->m_len = SGE_PAGE_SIZE;
6761
6762    /* map the SGE mbuf into non-paged pool */
6763    rc = bus_dmamap_load_mbuf_sg(fp->rx_sge_mbuf_tag,
6764                                 fp->rx_sge_mbuf_spare_map,
6765                                 m, segs, &nsegs, BUS_DMA_NOWAIT);
6766    if (__predict_false(rc != 0)) {
6767        fp->eth_q_stats.mbuf_rx_sge_mapping_failed++;
6768        m_freem(m);
6769        fp->eth_q_stats.mbuf_alloc_sge--;
6770        return (rc);
6771    }
6772
6773    /* all mbufs must map to a single segment */
6774    KASSERT((nsegs == 1), ("Too many segments, %d returned!", nsegs));
6775
6776    sge_buf = &fp->rx_sge_mbuf_chain[index];
6777
6778    /* release any existing SGE mbuf mapping */
6779    if (sge_buf->m_map != NULL) {
6780        bus_dmamap_sync(fp->rx_sge_mbuf_tag, sge_buf->m_map,
6781                        BUS_DMASYNC_POSTREAD);
6782        bus_dmamap_unload(fp->rx_sge_mbuf_tag, sge_buf->m_map);
6783    }
6784
6785    /* save the mbuf and mapping info for a future packet */
6786    map = sge_buf->m_map;
6787    sge_buf->m_map = fp->rx_sge_mbuf_spare_map;
6788    fp->rx_sge_mbuf_spare_map = map;
6789    bus_dmamap_sync(fp->rx_sge_mbuf_tag, sge_buf->m_map,
6790                    BUS_DMASYNC_PREREAD);
6791    sge_buf->m = m;
6792
6793    sge = &fp->rx_sge_chain[index];
6794    sge->addr_hi = htole32(U64_HI(segs[0].ds_addr));
6795    sge->addr_lo = htole32(U64_LO(segs[0].ds_addr));
6796
6797    return (rc);
6798}
6799
6800static __noinline int
6801bxe_alloc_fp_buffers(struct bxe_softc *sc)
6802{
6803    struct bxe_fastpath *fp;
6804    int i, j, rc = 0;
6805    int ring_prod, cqe_ring_prod;
6806    int max_agg_queues;
6807
6808    for (i = 0; i < sc->num_queues; i++) {
6809        fp = &sc->fp[i];
6810
6811#if __FreeBSD_version >= 800000
6812        fp->tx_br = buf_ring_alloc(BXE_BR_SIZE, M_DEVBUF,
6813                                   M_NOWAIT, &fp->tx_mtx);
6814        if (fp->tx_br == NULL) {
6815            BLOGE(sc, "buf_ring alloc fail for fp[%02d]\n", i);
6816            goto bxe_alloc_fp_buffers_error;
6817        }
6818#endif
6819
6820        ring_prod = cqe_ring_prod = 0;
6821        fp->rx_bd_cons = 0;
6822        fp->rx_cq_cons = 0;
6823
6824        /* allocate buffers for the RX BDs in RX BD chain */
6825        for (j = 0; j < sc->max_rx_bufs; j++) {
6826            rc = bxe_alloc_rx_bd_mbuf(fp, ring_prod, ring_prod);
6827            if (rc != 0) {
6828                BLOGE(sc, "mbuf alloc fail for fp[%02d] rx chain (%d)\n",
6829                      i, rc);
6830                goto bxe_alloc_fp_buffers_error;
6831            }
6832
6833            ring_prod     = RX_BD_NEXT(ring_prod);
6834            cqe_ring_prod = RCQ_NEXT(cqe_ring_prod);
6835        }
6836
6837        fp->rx_bd_prod = ring_prod;
6838        fp->rx_cq_prod = cqe_ring_prod;
6839        fp->eth_q_stats.rx_calls = fp->eth_q_stats.rx_pkts = 0;
6840
6841        max_agg_queues = MAX_AGG_QS(sc);
6842
6843        fp->tpa_enable = TRUE;
6844
6845        /* fill the TPA pool */
6846        for (j = 0; j < max_agg_queues; j++) {
6847            rc = bxe_alloc_rx_tpa_mbuf(fp, j);
6848            if (rc != 0) {
6849                BLOGE(sc, "mbuf alloc fail for fp[%02d] TPA queue %d\n",
6850                          i, j);
6851                fp->tpa_enable = FALSE;
6852                goto bxe_alloc_fp_buffers_error;
6853            }
6854
6855            fp->rx_tpa_info[j].state = BXE_TPA_STATE_STOP;
6856        }
6857
6858        if (fp->tpa_enable) {
6859            /* fill the RX SGE chain */
6860            ring_prod = 0;
6861            for (j = 0; j < RX_SGE_USABLE; j++) {
6862                rc = bxe_alloc_rx_sge_mbuf(fp, ring_prod);
6863                if (rc != 0) {
6864                    BLOGE(sc, "mbuf alloc fail for fp[%02d] SGE %d\n",
6865                              i, ring_prod);
6866                    fp->tpa_enable = FALSE;
6867                    ring_prod = 0;
6868                    goto bxe_alloc_fp_buffers_error;
6869                }
6870
6871                ring_prod = RX_SGE_NEXT(ring_prod);
6872            }
6873
6874            fp->rx_sge_prod = ring_prod;
6875        }
6876    }
6877
6878    return (0);
6879
6880bxe_alloc_fp_buffers_error:
6881
6882    /* unwind what was already allocated */
6883    bxe_free_rx_bd_chain(fp);
6884    bxe_free_tpa_pool(fp);
6885    bxe_free_sge_chain(fp);
6886
6887    return (ENOBUFS);
6888}
6889
6890static void
6891bxe_free_fw_stats_mem(struct bxe_softc *sc)
6892{
6893    bxe_dma_free(sc, &sc->fw_stats_dma);
6894
6895    sc->fw_stats_num = 0;
6896
6897    sc->fw_stats_req_size = 0;
6898    sc->fw_stats_req = NULL;
6899    sc->fw_stats_req_mapping = 0;
6900
6901    sc->fw_stats_data_size = 0;
6902    sc->fw_stats_data = NULL;
6903    sc->fw_stats_data_mapping = 0;
6904}
6905
6906static int
6907bxe_alloc_fw_stats_mem(struct bxe_softc *sc)
6908{
6909    uint8_t num_queue_stats;
6910    int num_groups;
6911
6912    /* number of queues for statistics is number of eth queues */
6913    num_queue_stats = BXE_NUM_ETH_QUEUES(sc);
6914
6915    /*
6916     * Total number of FW statistics requests =
6917     *   1 for port stats + 1 for PF stats + num of queues
6918     */
6919    sc->fw_stats_num = (2 + num_queue_stats);
6920
6921    /*
6922     * Request is built from stats_query_header and an array of
6923     * stats_query_cmd_group each of which contains STATS_QUERY_CMD_COUNT
6924     * rules. The real number or requests is configured in the
6925     * stats_query_header.
6926     */
6927    num_groups =
6928        ((sc->fw_stats_num / STATS_QUERY_CMD_COUNT) +
6929         ((sc->fw_stats_num % STATS_QUERY_CMD_COUNT) ? 1 : 0));
6930
6931    BLOGD(sc, DBG_LOAD, "stats fw_stats_num %d num_groups %d\n",
6932          sc->fw_stats_num, num_groups);
6933
6934    sc->fw_stats_req_size =
6935        (sizeof(struct stats_query_header) +
6936         (num_groups * sizeof(struct stats_query_cmd_group)));
6937
6938    /*
6939     * Data for statistics requests + stats_counter.
6940     * stats_counter holds per-STORM counters that are incremented when
6941     * STORM has finished with the current request. Memory for FCoE
6942     * offloaded statistics are counted anyway, even if they will not be sent.
6943     * VF stats are not accounted for here as the data of VF stats is stored
6944     * in memory allocated by the VF, not here.
6945     */
6946    sc->fw_stats_data_size =
6947        (sizeof(struct stats_counter) +
6948         sizeof(struct per_port_stats) +
6949         sizeof(struct per_pf_stats) +
6950         /* sizeof(struct fcoe_statistics_params) + */
6951         (sizeof(struct per_queue_stats) * num_queue_stats));
6952
6953    if (bxe_dma_alloc(sc, (sc->fw_stats_req_size + sc->fw_stats_data_size),
6954                      &sc->fw_stats_dma, "fw stats") != 0) {
6955        bxe_free_fw_stats_mem(sc);
6956        return (-1);
6957    }
6958
6959    /* set up the shortcuts */
6960
6961    sc->fw_stats_req =
6962        (struct bxe_fw_stats_req *)sc->fw_stats_dma.vaddr;
6963    sc->fw_stats_req_mapping = sc->fw_stats_dma.paddr;
6964
6965    sc->fw_stats_data =
6966        (struct bxe_fw_stats_data *)((uint8_t *)sc->fw_stats_dma.vaddr +
6967                                     sc->fw_stats_req_size);
6968    sc->fw_stats_data_mapping = (sc->fw_stats_dma.paddr +
6969                                 sc->fw_stats_req_size);
6970
6971    BLOGD(sc, DBG_LOAD, "statistics request base address set to %#jx\n",
6972          (uintmax_t)sc->fw_stats_req_mapping);
6973
6974    BLOGD(sc, DBG_LOAD, "statistics data base address set to %#jx\n",
6975          (uintmax_t)sc->fw_stats_data_mapping);
6976
6977    return (0);
6978}
6979
6980/*
6981 * Bits map:
6982 * 0-7  - Engine0 load counter.
6983 * 8-15 - Engine1 load counter.
6984 * 16   - Engine0 RESET_IN_PROGRESS bit.
6985 * 17   - Engine1 RESET_IN_PROGRESS bit.
6986 * 18   - Engine0 ONE_IS_LOADED. Set when there is at least one active
6987 *        function on the engine
6988 * 19   - Engine1 ONE_IS_LOADED.
6989 * 20   - Chip reset flow bit. When set none-leader must wait for both engines
6990 *        leader to complete (check for both RESET_IN_PROGRESS bits and not
6991 *        for just the one belonging to its engine).
6992 */
6993#define BXE_RECOVERY_GLOB_REG     MISC_REG_GENERIC_POR_1
6994#define BXE_PATH0_LOAD_CNT_MASK   0x000000ff
6995#define BXE_PATH0_LOAD_CNT_SHIFT  0
6996#define BXE_PATH1_LOAD_CNT_MASK   0x0000ff00
6997#define BXE_PATH1_LOAD_CNT_SHIFT  8
6998#define BXE_PATH0_RST_IN_PROG_BIT 0x00010000
6999#define BXE_PATH1_RST_IN_PROG_BIT 0x00020000
7000#define BXE_GLOBAL_RESET_BIT      0x00040000
7001
7002/* set the GLOBAL_RESET bit, should be run under rtnl lock */
7003static void
7004bxe_set_reset_global(struct bxe_softc *sc)
7005{
7006    uint32_t val;
7007    bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
7008    val = REG_RD(sc, BXE_RECOVERY_GLOB_REG);
7009    REG_WR(sc, BXE_RECOVERY_GLOB_REG, val | BXE_GLOBAL_RESET_BIT);
7010    bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
7011}
7012
7013/* clear the GLOBAL_RESET bit, should be run under rtnl lock */
7014static void
7015bxe_clear_reset_global(struct bxe_softc *sc)
7016{
7017    uint32_t val;
7018    bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
7019    val = REG_RD(sc, BXE_RECOVERY_GLOB_REG);
7020    REG_WR(sc, BXE_RECOVERY_GLOB_REG, val & (~BXE_GLOBAL_RESET_BIT));
7021    bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
7022}
7023
7024/* checks the GLOBAL_RESET bit, should be run under rtnl lock */
7025static uint8_t
7026bxe_reset_is_global(struct bxe_softc *sc)
7027{
7028    uint32_t val = REG_RD(sc, BXE_RECOVERY_GLOB_REG);
7029    BLOGD(sc, DBG_LOAD, "GLOB_REG=0x%08x\n", val);
7030    return (val & BXE_GLOBAL_RESET_BIT) ? TRUE : FALSE;
7031}
7032
7033/* clear RESET_IN_PROGRESS bit for the engine, should be run under rtnl lock */
7034static void
7035bxe_set_reset_done(struct bxe_softc *sc)
7036{
7037    uint32_t val;
7038    uint32_t bit = SC_PATH(sc) ? BXE_PATH1_RST_IN_PROG_BIT :
7039                                 BXE_PATH0_RST_IN_PROG_BIT;
7040
7041    bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
7042
7043    val = REG_RD(sc, BXE_RECOVERY_GLOB_REG);
7044    /* Clear the bit */
7045    val &= ~bit;
7046    REG_WR(sc, BXE_RECOVERY_GLOB_REG, val);
7047
7048    bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
7049}
7050
7051/* set RESET_IN_PROGRESS for the engine, should be run under rtnl lock */
7052static void
7053bxe_set_reset_in_progress(struct bxe_softc *sc)
7054{
7055    uint32_t val;
7056    uint32_t bit = SC_PATH(sc) ? BXE_PATH1_RST_IN_PROG_BIT :
7057                                 BXE_PATH0_RST_IN_PROG_BIT;
7058
7059    bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
7060
7061    val = REG_RD(sc, BXE_RECOVERY_GLOB_REG);
7062    /* Set the bit */
7063    val |= bit;
7064    REG_WR(sc, BXE_RECOVERY_GLOB_REG, val);
7065
7066    bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
7067}
7068
7069/* check RESET_IN_PROGRESS bit for an engine, should be run under rtnl lock */
7070static uint8_t
7071bxe_reset_is_done(struct bxe_softc *sc,
7072                  int              engine)
7073{
7074    uint32_t val = REG_RD(sc, BXE_RECOVERY_GLOB_REG);
7075    uint32_t bit = engine ? BXE_PATH1_RST_IN_PROG_BIT :
7076                            BXE_PATH0_RST_IN_PROG_BIT;
7077
7078    /* return false if bit is set */
7079    return (val & bit) ? FALSE : TRUE;
7080}
7081
7082/* get the load status for an engine, should be run under rtnl lock */
7083static uint8_t
7084bxe_get_load_status(struct bxe_softc *sc,
7085                    int              engine)
7086{
7087    uint32_t mask = engine ? BXE_PATH1_LOAD_CNT_MASK :
7088                             BXE_PATH0_LOAD_CNT_MASK;
7089    uint32_t shift = engine ? BXE_PATH1_LOAD_CNT_SHIFT :
7090                              BXE_PATH0_LOAD_CNT_SHIFT;
7091    uint32_t val = REG_RD(sc, BXE_RECOVERY_GLOB_REG);
7092
7093    BLOGD(sc, DBG_LOAD, "Old value for GLOB_REG=0x%08x\n", val);
7094
7095    val = ((val & mask) >> shift);
7096
7097    BLOGD(sc, DBG_LOAD, "Load mask engine %d = 0x%08x\n", engine, val);
7098
7099    return (val != 0);
7100}
7101
7102/* set pf load mark */
7103/* XXX needs to be under rtnl lock */
7104static void
7105bxe_set_pf_load(struct bxe_softc *sc)
7106{
7107    uint32_t val;
7108    uint32_t val1;
7109    uint32_t mask = SC_PATH(sc) ? BXE_PATH1_LOAD_CNT_MASK :
7110                                  BXE_PATH0_LOAD_CNT_MASK;
7111    uint32_t shift = SC_PATH(sc) ? BXE_PATH1_LOAD_CNT_SHIFT :
7112                                   BXE_PATH0_LOAD_CNT_SHIFT;
7113
7114    bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
7115
7116    val = REG_RD(sc, BXE_RECOVERY_GLOB_REG);
7117    BLOGD(sc, DBG_LOAD, "Old value for GLOB_REG=0x%08x\n", val);
7118
7119    /* get the current counter value */
7120    val1 = ((val & mask) >> shift);
7121
7122    /* set bit of this PF */
7123    val1 |= (1 << SC_ABS_FUNC(sc));
7124
7125    /* clear the old value */
7126    val &= ~mask;
7127
7128    /* set the new one */
7129    val |= ((val1 << shift) & mask);
7130
7131    REG_WR(sc, BXE_RECOVERY_GLOB_REG, val);
7132
7133    bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
7134}
7135
7136/* clear pf load mark */
7137/* XXX needs to be under rtnl lock */
7138static uint8_t
7139bxe_clear_pf_load(struct bxe_softc *sc)
7140{
7141    uint32_t val1, val;
7142    uint32_t mask = SC_PATH(sc) ? BXE_PATH1_LOAD_CNT_MASK :
7143                                  BXE_PATH0_LOAD_CNT_MASK;
7144    uint32_t shift = SC_PATH(sc) ? BXE_PATH1_LOAD_CNT_SHIFT :
7145                                   BXE_PATH0_LOAD_CNT_SHIFT;
7146
7147    bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
7148    val = REG_RD(sc, BXE_RECOVERY_GLOB_REG);
7149    BLOGD(sc, DBG_LOAD, "Old GEN_REG_VAL=0x%08x\n", val);
7150
7151    /* get the current counter value */
7152    val1 = (val & mask) >> shift;
7153
7154    /* clear bit of that PF */
7155    val1 &= ~(1 << SC_ABS_FUNC(sc));
7156
7157    /* clear the old value */
7158    val &= ~mask;
7159
7160    /* set the new one */
7161    val |= ((val1 << shift) & mask);
7162
7163    REG_WR(sc, BXE_RECOVERY_GLOB_REG, val);
7164    bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
7165    return (val1 != 0);
7166}
7167
7168/* send load requrest to mcp and analyze response */
7169static int
7170bxe_nic_load_request(struct bxe_softc *sc,
7171                     uint32_t         *load_code)
7172{
7173    /* init fw_seq */
7174    sc->fw_seq =
7175        (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
7176         DRV_MSG_SEQ_NUMBER_MASK);
7177
7178    BLOGD(sc, DBG_LOAD, "initial fw_seq 0x%04x\n", sc->fw_seq);
7179
7180    /* get the current FW pulse sequence */
7181    sc->fw_drv_pulse_wr_seq =
7182        (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb) &
7183         DRV_PULSE_SEQ_MASK);
7184
7185    BLOGD(sc, DBG_LOAD, "initial drv_pulse 0x%04x\n",
7186          sc->fw_drv_pulse_wr_seq);
7187
7188    /* load request */
7189    (*load_code) = bxe_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
7190                                  DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
7191
7192    /* if the MCP fails to respond we must abort */
7193    if (!(*load_code)) {
7194        BLOGE(sc, "MCP response failure!\n");
7195        return (-1);
7196    }
7197
7198    /* if MCP refused then must abort */
7199    if ((*load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED) {
7200        BLOGE(sc, "MCP refused load request\n");
7201        return (-1);
7202    }
7203
7204    return (0);
7205}
7206
7207/*
7208 * Check whether another PF has already loaded FW to chip. In virtualized
7209 * environments a pf from anoth VM may have already initialized the device
7210 * including loading FW.
7211 */
7212static int
7213bxe_nic_load_analyze_req(struct bxe_softc *sc,
7214                         uint32_t         load_code)
7215{
7216    uint32_t my_fw, loaded_fw;
7217
7218    /* is another pf loaded on this engine? */
7219    if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
7220        (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
7221        /* build my FW version dword */
7222        my_fw = (BCM_5710_FW_MAJOR_VERSION +
7223                 (BCM_5710_FW_MINOR_VERSION << 8 ) +
7224                 (BCM_5710_FW_REVISION_VERSION << 16) +
7225                 (BCM_5710_FW_ENGINEERING_VERSION << 24));
7226
7227        /* read loaded FW from chip */
7228        loaded_fw = REG_RD(sc, XSEM_REG_PRAM);
7229        BLOGD(sc, DBG_LOAD, "loaded FW 0x%08x / my FW 0x%08x\n",
7230              loaded_fw, my_fw);
7231
7232        /* abort nic load if version mismatch */
7233        if (my_fw != loaded_fw) {
7234            BLOGE(sc, "FW 0x%08x already loaded (mine is 0x%08x)",
7235                  loaded_fw, my_fw);
7236            return (-1);
7237        }
7238    }
7239
7240    return (0);
7241}
7242
7243/* mark PMF if applicable */
7244static void
7245bxe_nic_load_pmf(struct bxe_softc *sc,
7246                 uint32_t         load_code)
7247{
7248    uint32_t ncsi_oem_data_addr;
7249
7250    if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) ||
7251        (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) ||
7252        (load_code == FW_MSG_CODE_DRV_LOAD_PORT)) {
7253        /*
7254         * Barrier here for ordering between the writing to sc->port.pmf here
7255         * and reading it from the periodic task.
7256         */
7257        sc->port.pmf = 1;
7258        mb();
7259    } else {
7260        sc->port.pmf = 0;
7261    }
7262
7263    BLOGD(sc, DBG_LOAD, "pmf %d\n", sc->port.pmf);
7264
7265    /* XXX needed? */
7266    if (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) {
7267        if (SHMEM2_HAS(sc, ncsi_oem_data_addr)) {
7268            ncsi_oem_data_addr = SHMEM2_RD(sc, ncsi_oem_data_addr);
7269            if (ncsi_oem_data_addr) {
7270                REG_WR(sc,
7271                       (ncsi_oem_data_addr +
7272                        offsetof(struct glob_ncsi_oem_data, driver_version)),
7273                       0);
7274            }
7275        }
7276    }
7277}
7278
7279static void
7280bxe_read_mf_cfg(struct bxe_softc *sc)
7281{
7282    int n = (CHIP_IS_MODE_4_PORT(sc) ? 2 : 1);
7283    int abs_func;
7284    int vn;
7285
7286    if (BXE_NOMCP(sc)) {
7287        return; /* what should be the default bvalue in this case */
7288    }
7289
7290    /*
7291     * The formula for computing the absolute function number is...
7292     * For 2 port configuration (4 functions per port):
7293     *   abs_func = 2 * vn + SC_PORT + SC_PATH
7294     * For 4 port configuration (2 functions per port):
7295     *   abs_func = 4 * vn + 2 * SC_PORT + SC_PATH
7296     */
7297    for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
7298        abs_func = (n * (2 * vn + SC_PORT(sc)) + SC_PATH(sc));
7299        if (abs_func >= E1H_FUNC_MAX) {
7300            break;
7301        }
7302        sc->devinfo.mf_info.mf_config[vn] =
7303            MFCFG_RD(sc, func_mf_config[abs_func].config);
7304    }
7305
7306    if (sc->devinfo.mf_info.mf_config[SC_VN(sc)] &
7307        FUNC_MF_CFG_FUNC_DISABLED) {
7308        BLOGD(sc, DBG_LOAD, "mf_cfg function disabled\n");
7309        sc->flags |= BXE_MF_FUNC_DIS;
7310    } else {
7311        BLOGD(sc, DBG_LOAD, "mf_cfg function enabled\n");
7312        sc->flags &= ~BXE_MF_FUNC_DIS;
7313    }
7314}
7315
7316/* acquire split MCP access lock register */
7317static int bxe_acquire_alr(struct bxe_softc *sc)
7318{
7319    uint32_t j, val;
7320
7321    for (j = 0; j < 1000; j++) {
7322        val = (1UL << 31);
7323        REG_WR(sc, GRCBASE_MCP + 0x9c, val);
7324        val = REG_RD(sc, GRCBASE_MCP + 0x9c);
7325        if (val & (1L << 31))
7326            break;
7327
7328        DELAY(5000);
7329    }
7330
7331    if (!(val & (1L << 31))) {
7332        BLOGE(sc, "Cannot acquire MCP access lock register\n");
7333        return (-1);
7334    }
7335
7336    return (0);
7337}
7338
7339/* release split MCP access lock register */
7340static void bxe_release_alr(struct bxe_softc *sc)
7341{
7342    REG_WR(sc, GRCBASE_MCP + 0x9c, 0);
7343}
7344
7345static void
7346bxe_fan_failure(struct bxe_softc *sc)
7347{
7348    int port = SC_PORT(sc);
7349    uint32_t ext_phy_config;
7350
7351    /* mark the failure */
7352    ext_phy_config =
7353        SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
7354
7355    ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
7356    ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
7357    SHMEM_WR(sc, dev_info.port_hw_config[port].external_phy_config,
7358             ext_phy_config);
7359
7360    /* log the failure */
7361    BLOGW(sc, "Fan Failure has caused the driver to shutdown "
7362              "the card to prevent permanent damage. "
7363              "Please contact OEM Support for assistance\n");
7364
7365    /* XXX */
7366#if 1
7367    bxe_panic(sc, ("Schedule task to handle fan failure\n"));
7368#else
7369    /*
7370     * Schedule device reset (unload)
7371     * This is due to some boards consuming sufficient power when driver is
7372     * up to overheat if fan fails.
7373     */
7374    bxe_set_bit(BXE_SP_RTNL_FAN_FAILURE, &sc->sp_rtnl_state);
7375    schedule_delayed_work(&sc->sp_rtnl_task, 0);
7376#endif
7377}
7378
7379/* this function is called upon a link interrupt */
7380static void
7381bxe_link_attn(struct bxe_softc *sc)
7382{
7383    uint32_t pause_enabled = 0;
7384    struct host_port_stats *pstats;
7385    int cmng_fns;
7386
7387    /* Make sure that we are synced with the current statistics */
7388    bxe_stats_handle(sc, STATS_EVENT_STOP);
7389
7390    elink_link_update(&sc->link_params, &sc->link_vars);
7391
7392    if (sc->link_vars.link_up) {
7393
7394        /* dropless flow control */
7395        if (!CHIP_IS_E1(sc) && sc->dropless_fc) {
7396            pause_enabled = 0;
7397
7398            if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
7399                pause_enabled = 1;
7400            }
7401
7402            REG_WR(sc,
7403                   (BAR_USTRORM_INTMEM +
7404                    USTORM_ETH_PAUSE_ENABLED_OFFSET(SC_PORT(sc))),
7405                   pause_enabled);
7406        }
7407
7408        if (sc->link_vars.mac_type != ELINK_MAC_TYPE_EMAC) {
7409            pstats = BXE_SP(sc, port_stats);
7410            /* reset old mac stats */
7411            memset(&(pstats->mac_stx[0]), 0, sizeof(struct mac_stx));
7412        }
7413
7414        if (sc->state == BXE_STATE_OPEN) {
7415            bxe_stats_handle(sc, STATS_EVENT_LINK_UP);
7416        }
7417    }
7418
7419    if (sc->link_vars.link_up && sc->link_vars.line_speed) {
7420        cmng_fns = bxe_get_cmng_fns_mode(sc);
7421
7422        if (cmng_fns != CMNG_FNS_NONE) {
7423            bxe_cmng_fns_init(sc, FALSE, cmng_fns);
7424            storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
7425        } else {
7426            /* rate shaping and fairness are disabled */
7427            BLOGD(sc, DBG_LOAD, "single function mode without fairness\n");
7428        }
7429    }
7430
7431    bxe_link_report_locked(sc);
7432
7433    if (IS_MF(sc)) {
7434        ; // XXX bxe_link_sync_notify(sc);
7435    }
7436}
7437
7438static void
7439bxe_attn_int_asserted(struct bxe_softc *sc,
7440                      uint32_t         asserted)
7441{
7442    int port = SC_PORT(sc);
7443    uint32_t aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
7444                               MISC_REG_AEU_MASK_ATTN_FUNC_0;
7445    uint32_t nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
7446                                        NIG_REG_MASK_INTERRUPT_PORT0;
7447    uint32_t aeu_mask;
7448    uint32_t nig_mask = 0;
7449    uint32_t reg_addr;
7450    uint32_t igu_acked;
7451    uint32_t cnt;
7452
7453    if (sc->attn_state & asserted) {
7454        BLOGE(sc, "IGU ERROR attn=0x%08x\n", asserted);
7455    }
7456
7457    bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
7458
7459    aeu_mask = REG_RD(sc, aeu_addr);
7460
7461    BLOGD(sc, DBG_INTR, "aeu_mask 0x%08x newly asserted 0x%08x\n",
7462          aeu_mask, asserted);
7463
7464    aeu_mask &= ~(asserted & 0x3ff);
7465
7466    BLOGD(sc, DBG_INTR, "new mask 0x%08x\n", aeu_mask);
7467
7468    REG_WR(sc, aeu_addr, aeu_mask);
7469
7470    bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
7471
7472    BLOGD(sc, DBG_INTR, "attn_state 0x%08x\n", sc->attn_state);
7473    sc->attn_state |= asserted;
7474    BLOGD(sc, DBG_INTR, "new state 0x%08x\n", sc->attn_state);
7475
7476    if (asserted & ATTN_HARD_WIRED_MASK) {
7477        if (asserted & ATTN_NIG_FOR_FUNC) {
7478
7479	    bxe_acquire_phy_lock(sc);
7480            /* save nig interrupt mask */
7481            nig_mask = REG_RD(sc, nig_int_mask_addr);
7482
7483            /* If nig_mask is not set, no need to call the update function */
7484            if (nig_mask) {
7485                REG_WR(sc, nig_int_mask_addr, 0);
7486
7487                bxe_link_attn(sc);
7488            }
7489
7490            /* handle unicore attn? */
7491        }
7492
7493        if (asserted & ATTN_SW_TIMER_4_FUNC) {
7494            BLOGD(sc, DBG_INTR, "ATTN_SW_TIMER_4_FUNC!\n");
7495        }
7496
7497        if (asserted & GPIO_2_FUNC) {
7498            BLOGD(sc, DBG_INTR, "GPIO_2_FUNC!\n");
7499        }
7500
7501        if (asserted & GPIO_3_FUNC) {
7502            BLOGD(sc, DBG_INTR, "GPIO_3_FUNC!\n");
7503        }
7504
7505        if (asserted & GPIO_4_FUNC) {
7506            BLOGD(sc, DBG_INTR, "GPIO_4_FUNC!\n");
7507        }
7508
7509        if (port == 0) {
7510            if (asserted & ATTN_GENERAL_ATTN_1) {
7511                BLOGD(sc, DBG_INTR, "ATTN_GENERAL_ATTN_1!\n");
7512                REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
7513            }
7514            if (asserted & ATTN_GENERAL_ATTN_2) {
7515                BLOGD(sc, DBG_INTR, "ATTN_GENERAL_ATTN_2!\n");
7516                REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
7517            }
7518            if (asserted & ATTN_GENERAL_ATTN_3) {
7519                BLOGD(sc, DBG_INTR, "ATTN_GENERAL_ATTN_3!\n");
7520                REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
7521            }
7522        } else {
7523            if (asserted & ATTN_GENERAL_ATTN_4) {
7524                BLOGD(sc, DBG_INTR, "ATTN_GENERAL_ATTN_4!\n");
7525                REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
7526            }
7527            if (asserted & ATTN_GENERAL_ATTN_5) {
7528                BLOGD(sc, DBG_INTR, "ATTN_GENERAL_ATTN_5!\n");
7529                REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
7530            }
7531            if (asserted & ATTN_GENERAL_ATTN_6) {
7532                BLOGD(sc, DBG_INTR, "ATTN_GENERAL_ATTN_6!\n");
7533                REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
7534            }
7535        }
7536    } /* hardwired */
7537
7538    if (sc->devinfo.int_block == INT_BLOCK_HC) {
7539        reg_addr = (HC_REG_COMMAND_REG + port*32 + COMMAND_REG_ATTN_BITS_SET);
7540    } else {
7541        reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
7542    }
7543
7544    BLOGD(sc, DBG_INTR, "about to mask 0x%08x at %s addr 0x%08x\n",
7545          asserted,
7546          (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
7547    REG_WR(sc, reg_addr, asserted);
7548
7549    /* now set back the mask */
7550    if (asserted & ATTN_NIG_FOR_FUNC) {
7551        /*
7552         * Verify that IGU ack through BAR was written before restoring
7553         * NIG mask. This loop should exit after 2-3 iterations max.
7554         */
7555        if (sc->devinfo.int_block != INT_BLOCK_HC) {
7556            cnt = 0;
7557
7558            do {
7559                igu_acked = REG_RD(sc, IGU_REG_ATTENTION_ACK_BITS);
7560            } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) &&
7561                     (++cnt < MAX_IGU_ATTN_ACK_TO));
7562
7563            if (!igu_acked) {
7564                BLOGE(sc, "Failed to verify IGU ack on time\n");
7565            }
7566
7567            mb();
7568        }
7569
7570        REG_WR(sc, nig_int_mask_addr, nig_mask);
7571
7572	bxe_release_phy_lock(sc);
7573    }
7574}
7575
7576static void
7577bxe_print_next_block(struct bxe_softc *sc,
7578                     int              idx,
7579                     const char       *blk)
7580{
7581    BLOGI(sc, "%s%s", idx ? ", " : "", blk);
7582}
7583
7584static int
7585bxe_check_blocks_with_parity0(struct bxe_softc *sc,
7586                              uint32_t         sig,
7587                              int              par_num,
7588                              uint8_t          print)
7589{
7590    uint32_t cur_bit = 0;
7591    int i = 0;
7592
7593    for (i = 0; sig; i++) {
7594        cur_bit = ((uint32_t)0x1 << i);
7595        if (sig & cur_bit) {
7596            switch (cur_bit) {
7597            case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
7598                if (print)
7599                    bxe_print_next_block(sc, par_num++, "BRB");
7600                break;
7601            case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
7602                if (print)
7603                    bxe_print_next_block(sc, par_num++, "PARSER");
7604                break;
7605            case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
7606                if (print)
7607                    bxe_print_next_block(sc, par_num++, "TSDM");
7608                break;
7609            case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
7610                if (print)
7611                    bxe_print_next_block(sc, par_num++, "SEARCHER");
7612                break;
7613            case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
7614                if (print)
7615                    bxe_print_next_block(sc, par_num++, "TCM");
7616                break;
7617            case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
7618                if (print)
7619                    bxe_print_next_block(sc, par_num++, "TSEMI");
7620                break;
7621            case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
7622                if (print)
7623                    bxe_print_next_block(sc, par_num++, "XPB");
7624                break;
7625            }
7626
7627            /* Clear the bit */
7628            sig &= ~cur_bit;
7629        }
7630    }
7631
7632    return (par_num);
7633}
7634
7635static int
7636bxe_check_blocks_with_parity1(struct bxe_softc *sc,
7637                              uint32_t         sig,
7638                              int              par_num,
7639                              uint8_t          *global,
7640                              uint8_t          print)
7641{
7642    int i = 0;
7643    uint32_t cur_bit = 0;
7644    for (i = 0; sig; i++) {
7645        cur_bit = ((uint32_t)0x1 << i);
7646        if (sig & cur_bit) {
7647            switch (cur_bit) {
7648            case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
7649                if (print)
7650                    bxe_print_next_block(sc, par_num++, "PBF");
7651                break;
7652            case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
7653                if (print)
7654                    bxe_print_next_block(sc, par_num++, "QM");
7655                break;
7656            case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
7657                if (print)
7658                    bxe_print_next_block(sc, par_num++, "TM");
7659                break;
7660            case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
7661                if (print)
7662                    bxe_print_next_block(sc, par_num++, "XSDM");
7663                break;
7664            case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
7665                if (print)
7666                    bxe_print_next_block(sc, par_num++, "XCM");
7667                break;
7668            case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
7669                if (print)
7670                    bxe_print_next_block(sc, par_num++, "XSEMI");
7671                break;
7672            case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
7673                if (print)
7674                    bxe_print_next_block(sc, par_num++, "DOORBELLQ");
7675                break;
7676            case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
7677                if (print)
7678                    bxe_print_next_block(sc, par_num++, "NIG");
7679                break;
7680            case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
7681                if (print)
7682                    bxe_print_next_block(sc, par_num++, "VAUX PCI CORE");
7683                *global = TRUE;
7684                break;
7685            case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
7686                if (print)
7687                    bxe_print_next_block(sc, par_num++, "DEBUG");
7688                break;
7689            case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
7690                if (print)
7691                    bxe_print_next_block(sc, par_num++, "USDM");
7692                break;
7693            case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
7694                if (print)
7695                    bxe_print_next_block(sc, par_num++, "UCM");
7696                break;
7697            case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
7698                if (print)
7699                    bxe_print_next_block(sc, par_num++, "USEMI");
7700                break;
7701            case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
7702                if (print)
7703                    bxe_print_next_block(sc, par_num++, "UPB");
7704                break;
7705            case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
7706                if (print)
7707                    bxe_print_next_block(sc, par_num++, "CSDM");
7708                break;
7709            case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
7710                if (print)
7711                    bxe_print_next_block(sc, par_num++, "CCM");
7712                break;
7713            }
7714
7715            /* Clear the bit */
7716            sig &= ~cur_bit;
7717        }
7718    }
7719
7720    return (par_num);
7721}
7722
7723static int
7724bxe_check_blocks_with_parity2(struct bxe_softc *sc,
7725                              uint32_t         sig,
7726                              int              par_num,
7727                              uint8_t          print)
7728{
7729    uint32_t cur_bit = 0;
7730    int i = 0;
7731
7732    for (i = 0; sig; i++) {
7733        cur_bit = ((uint32_t)0x1 << i);
7734        if (sig & cur_bit) {
7735            switch (cur_bit) {
7736            case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
7737                if (print)
7738                    bxe_print_next_block(sc, par_num++, "CSEMI");
7739                break;
7740            case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
7741                if (print)
7742                    bxe_print_next_block(sc, par_num++, "PXP");
7743                break;
7744            case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
7745                if (print)
7746                    bxe_print_next_block(sc, par_num++, "PXPPCICLOCKCLIENT");
7747                break;
7748            case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
7749                if (print)
7750                    bxe_print_next_block(sc, par_num++, "CFC");
7751                break;
7752            case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
7753                if (print)
7754                    bxe_print_next_block(sc, par_num++, "CDU");
7755                break;
7756            case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
7757                if (print)
7758                    bxe_print_next_block(sc, par_num++, "DMAE");
7759                break;
7760            case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
7761                if (print)
7762                    bxe_print_next_block(sc, par_num++, "IGU");
7763                break;
7764            case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
7765                if (print)
7766                    bxe_print_next_block(sc, par_num++, "MISC");
7767                break;
7768            }
7769
7770            /* Clear the bit */
7771            sig &= ~cur_bit;
7772        }
7773    }
7774
7775    return (par_num);
7776}
7777
7778static int
7779bxe_check_blocks_with_parity3(struct bxe_softc *sc,
7780                              uint32_t         sig,
7781                              int              par_num,
7782                              uint8_t          *global,
7783                              uint8_t          print)
7784{
7785    uint32_t cur_bit = 0;
7786    int i = 0;
7787
7788    for (i = 0; sig; i++) {
7789        cur_bit = ((uint32_t)0x1 << i);
7790        if (sig & cur_bit) {
7791            switch (cur_bit) {
7792            case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
7793                if (print)
7794                    bxe_print_next_block(sc, par_num++, "MCP ROM");
7795                *global = TRUE;
7796                break;
7797            case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
7798                if (print)
7799                    bxe_print_next_block(sc, par_num++,
7800                              "MCP UMP RX");
7801                *global = TRUE;
7802                break;
7803            case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
7804                if (print)
7805                    bxe_print_next_block(sc, par_num++,
7806                              "MCP UMP TX");
7807                *global = TRUE;
7808                break;
7809            case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
7810                if (print)
7811                    bxe_print_next_block(sc, par_num++,
7812                              "MCP SCPAD");
7813                *global = TRUE;
7814                break;
7815            }
7816
7817            /* Clear the bit */
7818            sig &= ~cur_bit;
7819        }
7820    }
7821
7822    return (par_num);
7823}
7824
7825static int
7826bxe_check_blocks_with_parity4(struct bxe_softc *sc,
7827                              uint32_t         sig,
7828                              int              par_num,
7829                              uint8_t          print)
7830{
7831    uint32_t cur_bit = 0;
7832    int i = 0;
7833
7834    for (i = 0; sig; i++) {
7835        cur_bit = ((uint32_t)0x1 << i);
7836        if (sig & cur_bit) {
7837            switch (cur_bit) {
7838            case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
7839                if (print)
7840                    bxe_print_next_block(sc, par_num++, "PGLUE_B");
7841                break;
7842            case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
7843                if (print)
7844                    bxe_print_next_block(sc, par_num++, "ATC");
7845                break;
7846            }
7847
7848            /* Clear the bit */
7849            sig &= ~cur_bit;
7850        }
7851    }
7852
7853    return (par_num);
7854}
7855
7856static uint8_t
7857bxe_parity_attn(struct bxe_softc *sc,
7858                uint8_t          *global,
7859                uint8_t          print,
7860                uint32_t         *sig)
7861{
7862    int par_num = 0;
7863
7864    if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
7865        (sig[1] & HW_PRTY_ASSERT_SET_1) ||
7866        (sig[2] & HW_PRTY_ASSERT_SET_2) ||
7867        (sig[3] & HW_PRTY_ASSERT_SET_3) ||
7868        (sig[4] & HW_PRTY_ASSERT_SET_4)) {
7869        BLOGE(sc, "Parity error: HW block parity attention:\n"
7870                  "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
7871              (uint32_t)(sig[0] & HW_PRTY_ASSERT_SET_0),
7872              (uint32_t)(sig[1] & HW_PRTY_ASSERT_SET_1),
7873              (uint32_t)(sig[2] & HW_PRTY_ASSERT_SET_2),
7874              (uint32_t)(sig[3] & HW_PRTY_ASSERT_SET_3),
7875              (uint32_t)(sig[4] & HW_PRTY_ASSERT_SET_4));
7876
7877        if (print)
7878            BLOGI(sc, "Parity errors detected in blocks: ");
7879
7880        par_num =
7881            bxe_check_blocks_with_parity0(sc, sig[0] &
7882                                          HW_PRTY_ASSERT_SET_0,
7883                                          par_num, print);
7884        par_num =
7885            bxe_check_blocks_with_parity1(sc, sig[1] &
7886                                          HW_PRTY_ASSERT_SET_1,
7887                                          par_num, global, print);
7888        par_num =
7889            bxe_check_blocks_with_parity2(sc, sig[2] &
7890                                          HW_PRTY_ASSERT_SET_2,
7891                                          par_num, print);
7892        par_num =
7893            bxe_check_blocks_with_parity3(sc, sig[3] &
7894                                          HW_PRTY_ASSERT_SET_3,
7895                                          par_num, global, print);
7896        par_num =
7897            bxe_check_blocks_with_parity4(sc, sig[4] &
7898                                          HW_PRTY_ASSERT_SET_4,
7899                                          par_num, print);
7900
7901        if (print)
7902            BLOGI(sc, "\n");
7903
7904        return (TRUE);
7905    }
7906
7907    return (FALSE);
7908}
7909
7910static uint8_t
7911bxe_chk_parity_attn(struct bxe_softc *sc,
7912                    uint8_t          *global,
7913                    uint8_t          print)
7914{
7915    struct attn_route attn = { {0} };
7916    int port = SC_PORT(sc);
7917
7918    attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
7919    attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
7920    attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
7921    attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
7922
7923    if (!CHIP_IS_E1x(sc))
7924        attn.sig[4] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
7925
7926    return (bxe_parity_attn(sc, global, print, attn.sig));
7927}
7928
7929static void
7930bxe_attn_int_deasserted4(struct bxe_softc *sc,
7931                         uint32_t         attn)
7932{
7933    uint32_t val;
7934
7935    if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
7936        val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
7937        BLOGE(sc, "PGLUE hw attention 0x%08x\n", val);
7938        if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
7939            BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
7940        if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
7941            BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
7942        if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
7943            BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
7944        if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
7945            BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
7946        if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
7947            BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
7948        if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
7949            BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
7950        if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
7951            BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
7952        if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
7953            BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
7954        if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
7955            BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
7956    }
7957
7958    if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
7959        val = REG_RD(sc, ATC_REG_ATC_INT_STS_CLR);
7960        BLOGE(sc, "ATC hw attention 0x%08x\n", val);
7961        if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
7962            BLOGE(sc, "ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
7963        if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
7964            BLOGE(sc, "ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
7965        if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
7966            BLOGE(sc, "ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
7967        if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
7968            BLOGE(sc, "ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
7969        if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
7970            BLOGE(sc, "ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
7971        if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
7972            BLOGE(sc, "ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
7973    }
7974
7975    if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
7976                AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
7977        BLOGE(sc, "FATAL parity attention set4 0x%08x\n",
7978              (uint32_t)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
7979                                 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
7980    }
7981}
7982
7983static void
7984bxe_e1h_disable(struct bxe_softc *sc)
7985{
7986    int port = SC_PORT(sc);
7987
7988    bxe_tx_disable(sc);
7989
7990    REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port*8, 0);
7991}
7992
7993static void
7994bxe_e1h_enable(struct bxe_softc *sc)
7995{
7996    int port = SC_PORT(sc);
7997
7998    REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port*8, 1);
7999
8000    // XXX bxe_tx_enable(sc);
8001}
8002
8003/*
8004 * called due to MCP event (on pmf):
8005 *   reread new bandwidth configuration
8006 *   configure FW
8007 *   notify others function about the change
8008 */
8009static void
8010bxe_config_mf_bw(struct bxe_softc *sc)
8011{
8012    if (sc->link_vars.link_up) {
8013        bxe_cmng_fns_init(sc, TRUE, CMNG_FNS_MINMAX);
8014        // XXX bxe_link_sync_notify(sc);
8015    }
8016
8017    storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
8018}
8019
8020static void
8021bxe_set_mf_bw(struct bxe_softc *sc)
8022{
8023    bxe_config_mf_bw(sc);
8024    bxe_fw_command(sc, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
8025}
8026
8027static void
8028bxe_handle_eee_event(struct bxe_softc *sc)
8029{
8030    BLOGD(sc, DBG_INTR, "EEE - LLDP event\n");
8031    bxe_fw_command(sc, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
8032}
8033
8034#define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
8035
8036static void
8037bxe_drv_info_ether_stat(struct bxe_softc *sc)
8038{
8039    struct eth_stats_info *ether_stat =
8040        &sc->sp->drv_info_to_mcp.ether_stat;
8041
8042    strlcpy(ether_stat->version, BXE_DRIVER_VERSION,
8043            ETH_STAT_INFO_VERSION_LEN);
8044
8045    /* XXX (+ MAC_PAD) taken from other driver... verify this is right */
8046    sc->sp_objs[0].mac_obj.get_n_elements(sc, &sc->sp_objs[0].mac_obj,
8047                                          DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
8048                                          ether_stat->mac_local + MAC_PAD,
8049                                          MAC_PAD, ETH_ALEN);
8050
8051    ether_stat->mtu_size = sc->mtu;
8052
8053    ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
8054    if (if_getcapenable(sc->ifp) & (IFCAP_TSO4 | IFCAP_TSO6)) {
8055        ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
8056    }
8057
8058    // XXX ether_stat->feature_flags |= ???;
8059
8060    ether_stat->promiscuous_mode = 0; // (flags & PROMISC) ? 1 : 0;
8061
8062    ether_stat->txq_size = sc->tx_ring_size;
8063    ether_stat->rxq_size = sc->rx_ring_size;
8064}
8065
8066static void
8067bxe_handle_drv_info_req(struct bxe_softc *sc)
8068{
8069    enum drv_info_opcode op_code;
8070    uint32_t drv_info_ctl = SHMEM2_RD(sc, drv_info_control);
8071
8072    /* if drv_info version supported by MFW doesn't match - send NACK */
8073    if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
8074        bxe_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
8075        return;
8076    }
8077
8078    op_code = ((drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
8079               DRV_INFO_CONTROL_OP_CODE_SHIFT);
8080
8081    memset(&sc->sp->drv_info_to_mcp, 0, sizeof(union drv_info_to_mcp));
8082
8083    switch (op_code) {
8084    case ETH_STATS_OPCODE:
8085        bxe_drv_info_ether_stat(sc);
8086        break;
8087    case FCOE_STATS_OPCODE:
8088    case ISCSI_STATS_OPCODE:
8089    default:
8090        /* if op code isn't supported - send NACK */
8091        bxe_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
8092        return;
8093    }
8094
8095    /*
8096     * If we got drv_info attn from MFW then these fields are defined in
8097     * shmem2 for sure
8098     */
8099    SHMEM2_WR(sc, drv_info_host_addr_lo,
8100              U64_LO(BXE_SP_MAPPING(sc, drv_info_to_mcp)));
8101    SHMEM2_WR(sc, drv_info_host_addr_hi,
8102              U64_HI(BXE_SP_MAPPING(sc, drv_info_to_mcp)));
8103
8104    bxe_fw_command(sc, DRV_MSG_CODE_DRV_INFO_ACK, 0);
8105}
8106
8107static void
8108bxe_dcc_event(struct bxe_softc *sc,
8109              uint32_t         dcc_event)
8110{
8111    BLOGD(sc, DBG_INTR, "dcc_event 0x%08x\n", dcc_event);
8112
8113    if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
8114        /*
8115         * This is the only place besides the function initialization
8116         * where the sc->flags can change so it is done without any
8117         * locks
8118         */
8119        if (sc->devinfo.mf_info.mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_DISABLED) {
8120            BLOGD(sc, DBG_INTR, "mf_cfg function disabled\n");
8121            sc->flags |= BXE_MF_FUNC_DIS;
8122            bxe_e1h_disable(sc);
8123        } else {
8124            BLOGD(sc, DBG_INTR, "mf_cfg function enabled\n");
8125            sc->flags &= ~BXE_MF_FUNC_DIS;
8126            bxe_e1h_enable(sc);
8127        }
8128        dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
8129    }
8130
8131    if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
8132        bxe_config_mf_bw(sc);
8133        dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
8134    }
8135
8136    /* Report results to MCP */
8137    if (dcc_event)
8138        bxe_fw_command(sc, DRV_MSG_CODE_DCC_FAILURE, 0);
8139    else
8140        bxe_fw_command(sc, DRV_MSG_CODE_DCC_OK, 0);
8141}
8142
8143static void
8144bxe_pmf_update(struct bxe_softc *sc)
8145{
8146    int port = SC_PORT(sc);
8147    uint32_t val;
8148
8149    sc->port.pmf = 1;
8150    BLOGD(sc, DBG_INTR, "pmf %d\n", sc->port.pmf);
8151
8152    /*
8153     * We need the mb() to ensure the ordering between the writing to
8154     * sc->port.pmf here and reading it from the bxe_periodic_task().
8155     */
8156    mb();
8157
8158    /* queue a periodic task */
8159    // XXX schedule task...
8160
8161    // XXX bxe_dcbx_pmf_update(sc);
8162
8163    /* enable nig attention */
8164    val = (0xff0f | (1 << (SC_VN(sc) + 4)));
8165    if (sc->devinfo.int_block == INT_BLOCK_HC) {
8166        REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port*8, val);
8167        REG_WR(sc, HC_REG_LEADING_EDGE_0 + port*8, val);
8168    } else if (!CHIP_IS_E1x(sc)) {
8169        REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
8170        REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
8171    }
8172
8173    bxe_stats_handle(sc, STATS_EVENT_PMF);
8174}
8175
8176static int
8177bxe_mc_assert(struct bxe_softc *sc)
8178{
8179    char last_idx;
8180    int i, rc = 0;
8181    uint32_t row0, row1, row2, row3;
8182
8183    /* XSTORM */
8184    last_idx = REG_RD8(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_INDEX_OFFSET);
8185    if (last_idx)
8186        BLOGE(sc, "XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
8187
8188    /* print the asserts */
8189    for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
8190
8191        row0 = REG_RD(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i));
8192        row1 = REG_RD(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) + 4);
8193        row2 = REG_RD(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) + 8);
8194        row3 = REG_RD(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) + 12);
8195
8196        if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
8197            BLOGE(sc, "XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
8198                  i, row3, row2, row1, row0);
8199            rc++;
8200        } else {
8201            break;
8202        }
8203    }
8204
8205    /* TSTORM */
8206    last_idx = REG_RD8(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_INDEX_OFFSET);
8207    if (last_idx) {
8208        BLOGE(sc, "TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
8209    }
8210
8211    /* print the asserts */
8212    for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
8213
8214        row0 = REG_RD(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i));
8215        row1 = REG_RD(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) + 4);
8216        row2 = REG_RD(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) + 8);
8217        row3 = REG_RD(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) + 12);
8218
8219        if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
8220            BLOGE(sc, "TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
8221                  i, row3, row2, row1, row0);
8222            rc++;
8223        } else {
8224            break;
8225        }
8226    }
8227
8228    /* CSTORM */
8229    last_idx = REG_RD8(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_INDEX_OFFSET);
8230    if (last_idx) {
8231        BLOGE(sc, "CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
8232    }
8233
8234    /* print the asserts */
8235    for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
8236
8237        row0 = REG_RD(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i));
8238        row1 = REG_RD(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) + 4);
8239        row2 = REG_RD(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) + 8);
8240        row3 = REG_RD(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) + 12);
8241
8242        if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
8243            BLOGE(sc, "CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
8244                  i, row3, row2, row1, row0);
8245            rc++;
8246        } else {
8247            break;
8248        }
8249    }
8250
8251    /* USTORM */
8252    last_idx = REG_RD8(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_INDEX_OFFSET);
8253    if (last_idx) {
8254        BLOGE(sc, "USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
8255    }
8256
8257    /* print the asserts */
8258    for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
8259
8260        row0 = REG_RD(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i));
8261        row1 = REG_RD(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) + 4);
8262        row2 = REG_RD(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) + 8);
8263        row3 = REG_RD(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) + 12);
8264
8265        if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
8266            BLOGE(sc, "USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
8267                  i, row3, row2, row1, row0);
8268            rc++;
8269        } else {
8270            break;
8271        }
8272    }
8273
8274    return (rc);
8275}
8276
8277static void
8278bxe_attn_int_deasserted3(struct bxe_softc *sc,
8279                         uint32_t         attn)
8280{
8281    int func = SC_FUNC(sc);
8282    uint32_t val;
8283
8284    if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
8285
8286        if (attn & BXE_PMF_LINK_ASSERT(sc)) {
8287
8288            REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
8289            bxe_read_mf_cfg(sc);
8290            sc->devinfo.mf_info.mf_config[SC_VN(sc)] =
8291                MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
8292            val = SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_status);
8293
8294            if (val & DRV_STATUS_DCC_EVENT_MASK)
8295                bxe_dcc_event(sc, (val & DRV_STATUS_DCC_EVENT_MASK));
8296
8297            if (val & DRV_STATUS_SET_MF_BW)
8298                bxe_set_mf_bw(sc);
8299
8300            if (val & DRV_STATUS_DRV_INFO_REQ)
8301                bxe_handle_drv_info_req(sc);
8302
8303#if 0
8304            if (val & DRV_STATUS_VF_DISABLED)
8305                bxe_vf_handle_flr_event(sc);
8306#endif
8307
8308            if ((sc->port.pmf == 0) && (val & DRV_STATUS_PMF))
8309                bxe_pmf_update(sc);
8310
8311#if 0
8312            if (sc->port.pmf &&
8313                (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
8314                (sc->dcbx_enabled > 0))
8315                /* start dcbx state machine */
8316                bxe_dcbx_set_params(sc, BXE_DCBX_STATE_NEG_RECEIVED);
8317#endif
8318
8319#if 0
8320            if (val & DRV_STATUS_AFEX_EVENT_MASK)
8321                bxe_handle_afex_cmd(sc, val & DRV_STATUS_AFEX_EVENT_MASK);
8322#endif
8323
8324            if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
8325                bxe_handle_eee_event(sc);
8326
8327            if (sc->link_vars.periodic_flags &
8328                ELINK_PERIODIC_FLAGS_LINK_EVENT) {
8329                /* sync with link */
8330		bxe_acquire_phy_lock(sc);
8331                sc->link_vars.periodic_flags &=
8332                    ~ELINK_PERIODIC_FLAGS_LINK_EVENT;
8333		bxe_release_phy_lock(sc);
8334                if (IS_MF(sc))
8335                    ; // XXX bxe_link_sync_notify(sc);
8336                bxe_link_report(sc);
8337            }
8338
8339            /*
8340             * Always call it here: bxe_link_report() will
8341             * prevent the link indication duplication.
8342             */
8343            bxe_link_status_update(sc);
8344
8345        } else if (attn & BXE_MC_ASSERT_BITS) {
8346
8347            BLOGE(sc, "MC assert!\n");
8348            bxe_mc_assert(sc);
8349            REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_10, 0);
8350            REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_9, 0);
8351            REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_8, 0);
8352            REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_7, 0);
8353            bxe_panic(sc, ("MC assert!\n"));
8354
8355        } else if (attn & BXE_MCP_ASSERT) {
8356
8357            BLOGE(sc, "MCP assert!\n");
8358            REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_11, 0);
8359            // XXX bxe_fw_dump(sc);
8360
8361        } else {
8362            BLOGE(sc, "Unknown HW assert! (attn 0x%08x)\n", attn);
8363        }
8364    }
8365
8366    if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
8367        BLOGE(sc, "LATCHED attention 0x%08x (masked)\n", attn);
8368        if (attn & BXE_GRC_TIMEOUT) {
8369            val = CHIP_IS_E1(sc) ? 0 : REG_RD(sc, MISC_REG_GRC_TIMEOUT_ATTN);
8370            BLOGE(sc, "GRC time-out 0x%08x\n", val);
8371        }
8372        if (attn & BXE_GRC_RSV) {
8373            val = CHIP_IS_E1(sc) ? 0 : REG_RD(sc, MISC_REG_GRC_RSV_ATTN);
8374            BLOGE(sc, "GRC reserved 0x%08x\n", val);
8375        }
8376        REG_WR(sc, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
8377    }
8378}
8379
8380static void
8381bxe_attn_int_deasserted2(struct bxe_softc *sc,
8382                         uint32_t         attn)
8383{
8384    int port = SC_PORT(sc);
8385    int reg_offset;
8386    uint32_t val0, mask0, val1, mask1;
8387    uint32_t val;
8388
8389    if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
8390        val = REG_RD(sc, CFC_REG_CFC_INT_STS_CLR);
8391        BLOGE(sc, "CFC hw attention 0x%08x\n", val);
8392        /* CFC error attention */
8393        if (val & 0x2) {
8394            BLOGE(sc, "FATAL error from CFC\n");
8395        }
8396    }
8397
8398    if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
8399        val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_0);
8400        BLOGE(sc, "PXP hw attention-0 0x%08x\n", val);
8401        /* RQ_USDMDP_FIFO_OVERFLOW */
8402        if (val & 0x18000) {
8403            BLOGE(sc, "FATAL error from PXP\n");
8404        }
8405
8406        if (!CHIP_IS_E1x(sc)) {
8407            val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_1);
8408            BLOGE(sc, "PXP hw attention-1 0x%08x\n", val);
8409        }
8410    }
8411
8412#define PXP2_EOP_ERROR_BIT  PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR
8413#define AEU_PXP2_HW_INT_BIT AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT
8414
8415    if (attn & AEU_PXP2_HW_INT_BIT) {
8416        /*  CQ47854 workaround do not panic on
8417         *  PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
8418         */
8419        if (!CHIP_IS_E1x(sc)) {
8420            mask0 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_0);
8421            val1 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_1);
8422            mask1 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_1);
8423            val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_0);
8424            /*
8425             * If the olny PXP2_EOP_ERROR_BIT is set in
8426             * STS0 and STS1 - clear it
8427             *
8428             * probably we lose additional attentions between
8429             * STS0 and STS_CLR0, in this case user will not
8430             * be notified about them
8431             */
8432            if (val0 & mask0 & PXP2_EOP_ERROR_BIT &&
8433                !(val1 & mask1))
8434                val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
8435
8436            /* print the register, since no one can restore it */
8437            BLOGE(sc, "PXP2_REG_PXP2_INT_STS_CLR_0 0x%08x\n", val0);
8438
8439            /*
8440             * if PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
8441             * then notify
8442             */
8443            if (val0 & PXP2_EOP_ERROR_BIT) {
8444                BLOGE(sc, "PXP2_WR_PGLUE_EOP_ERROR\n");
8445
8446                /*
8447                 * if only PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR is
8448                 * set then clear attention from PXP2 block without panic
8449                 */
8450                if (((val0 & mask0) == PXP2_EOP_ERROR_BIT) &&
8451                    ((val1 & mask1) == 0))
8452                    attn &= ~AEU_PXP2_HW_INT_BIT;
8453            }
8454        }
8455    }
8456
8457    if (attn & HW_INTERRUT_ASSERT_SET_2) {
8458        reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
8459                             MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
8460
8461        val = REG_RD(sc, reg_offset);
8462        val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
8463        REG_WR(sc, reg_offset, val);
8464
8465        BLOGE(sc, "FATAL HW block attention set2 0x%x\n",
8466              (uint32_t)(attn & HW_INTERRUT_ASSERT_SET_2));
8467        bxe_panic(sc, ("HW block attention set2\n"));
8468    }
8469}
8470
8471static void
8472bxe_attn_int_deasserted1(struct bxe_softc *sc,
8473                         uint32_t         attn)
8474{
8475    int port = SC_PORT(sc);
8476    int reg_offset;
8477    uint32_t val;
8478
8479    if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
8480        val = REG_RD(sc, DORQ_REG_DORQ_INT_STS_CLR);
8481        BLOGE(sc, "DB hw attention 0x%08x\n", val);
8482        /* DORQ discard attention */
8483        if (val & 0x2) {
8484            BLOGE(sc, "FATAL error from DORQ\n");
8485        }
8486    }
8487
8488    if (attn & HW_INTERRUT_ASSERT_SET_1) {
8489        reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
8490                             MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
8491
8492        val = REG_RD(sc, reg_offset);
8493        val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
8494        REG_WR(sc, reg_offset, val);
8495
8496        BLOGE(sc, "FATAL HW block attention set1 0x%08x\n",
8497              (uint32_t)(attn & HW_INTERRUT_ASSERT_SET_1));
8498        bxe_panic(sc, ("HW block attention set1\n"));
8499    }
8500}
8501
8502static void
8503bxe_attn_int_deasserted0(struct bxe_softc *sc,
8504                         uint32_t         attn)
8505{
8506    int port = SC_PORT(sc);
8507    int reg_offset;
8508    uint32_t val;
8509
8510    reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
8511                          MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
8512
8513    if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
8514        val = REG_RD(sc, reg_offset);
8515        val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
8516        REG_WR(sc, reg_offset, val);
8517
8518        BLOGW(sc, "SPIO5 hw attention\n");
8519
8520        /* Fan failure attention */
8521        elink_hw_reset_phy(&sc->link_params);
8522        bxe_fan_failure(sc);
8523    }
8524
8525    if ((attn & sc->link_vars.aeu_int_mask) && sc->port.pmf) {
8526	bxe_acquire_phy_lock(sc);
8527        elink_handle_module_detect_int(&sc->link_params);
8528	bxe_release_phy_lock(sc);
8529    }
8530
8531    if (attn & HW_INTERRUT_ASSERT_SET_0) {
8532        val = REG_RD(sc, reg_offset);
8533        val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
8534        REG_WR(sc, reg_offset, val);
8535
8536        bxe_panic(sc, ("FATAL HW block attention set0 0x%lx\n",
8537                       (attn & HW_INTERRUT_ASSERT_SET_0)));
8538    }
8539}
8540
8541static void
8542bxe_attn_int_deasserted(struct bxe_softc *sc,
8543                        uint32_t         deasserted)
8544{
8545    struct attn_route attn;
8546    struct attn_route *group_mask;
8547    int port = SC_PORT(sc);
8548    int index;
8549    uint32_t reg_addr;
8550    uint32_t val;
8551    uint32_t aeu_mask;
8552    uint8_t global = FALSE;
8553
8554    /*
8555     * Need to take HW lock because MCP or other port might also
8556     * try to handle this event.
8557     */
8558    bxe_acquire_alr(sc);
8559
8560    if (bxe_chk_parity_attn(sc, &global, TRUE)) {
8561        /* XXX
8562         * In case of parity errors don't handle attentions so that
8563         * other function would "see" parity errors.
8564         */
8565        sc->recovery_state = BXE_RECOVERY_INIT;
8566        // XXX schedule a recovery task...
8567        /* disable HW interrupts */
8568        bxe_int_disable(sc);
8569        bxe_release_alr(sc);
8570        return;
8571    }
8572
8573    attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
8574    attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
8575    attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
8576    attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
8577    if (!CHIP_IS_E1x(sc)) {
8578        attn.sig[4] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
8579    } else {
8580        attn.sig[4] = 0;
8581    }
8582
8583    BLOGD(sc, DBG_INTR, "attn: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
8584          attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
8585
8586    for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
8587        if (deasserted & (1 << index)) {
8588            group_mask = &sc->attn_group[index];
8589
8590            BLOGD(sc, DBG_INTR,
8591                  "group[%d]: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", index,
8592                  group_mask->sig[0], group_mask->sig[1],
8593                  group_mask->sig[2], group_mask->sig[3],
8594                  group_mask->sig[4]);
8595
8596            bxe_attn_int_deasserted4(sc, attn.sig[4] & group_mask->sig[4]);
8597            bxe_attn_int_deasserted3(sc, attn.sig[3] & group_mask->sig[3]);
8598            bxe_attn_int_deasserted1(sc, attn.sig[1] & group_mask->sig[1]);
8599            bxe_attn_int_deasserted2(sc, attn.sig[2] & group_mask->sig[2]);
8600            bxe_attn_int_deasserted0(sc, attn.sig[0] & group_mask->sig[0]);
8601        }
8602    }
8603
8604    bxe_release_alr(sc);
8605
8606    if (sc->devinfo.int_block == INT_BLOCK_HC) {
8607        reg_addr = (HC_REG_COMMAND_REG + port*32 +
8608                    COMMAND_REG_ATTN_BITS_CLR);
8609    } else {
8610        reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
8611    }
8612
8613    val = ~deasserted;
8614    BLOGD(sc, DBG_INTR,
8615          "about to mask 0x%08x at %s addr 0x%08x\n", val,
8616          (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
8617    REG_WR(sc, reg_addr, val);
8618
8619    if (~sc->attn_state & deasserted) {
8620        BLOGE(sc, "IGU error\n");
8621    }
8622
8623    reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
8624                      MISC_REG_AEU_MASK_ATTN_FUNC_0;
8625
8626    bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
8627
8628    aeu_mask = REG_RD(sc, reg_addr);
8629
8630    BLOGD(sc, DBG_INTR, "aeu_mask 0x%08x newly deasserted 0x%08x\n",
8631          aeu_mask, deasserted);
8632    aeu_mask |= (deasserted & 0x3ff);
8633    BLOGD(sc, DBG_INTR, "new mask 0x%08x\n", aeu_mask);
8634
8635    REG_WR(sc, reg_addr, aeu_mask);
8636    bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
8637
8638    BLOGD(sc, DBG_INTR, "attn_state 0x%08x\n", sc->attn_state);
8639    sc->attn_state &= ~deasserted;
8640    BLOGD(sc, DBG_INTR, "new state 0x%08x\n", sc->attn_state);
8641}
8642
8643static void
8644bxe_attn_int(struct bxe_softc *sc)
8645{
8646    /* read local copy of bits */
8647    uint32_t attn_bits = le32toh(sc->def_sb->atten_status_block.attn_bits);
8648    uint32_t attn_ack = le32toh(sc->def_sb->atten_status_block.attn_bits_ack);
8649    uint32_t attn_state = sc->attn_state;
8650
8651    /* look for changed bits */
8652    uint32_t asserted   =  attn_bits & ~attn_ack & ~attn_state;
8653    uint32_t deasserted = ~attn_bits &  attn_ack &  attn_state;
8654
8655    BLOGD(sc, DBG_INTR,
8656          "attn_bits 0x%08x attn_ack 0x%08x asserted 0x%08x deasserted 0x%08x\n",
8657          attn_bits, attn_ack, asserted, deasserted);
8658
8659    if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) {
8660        BLOGE(sc, "BAD attention state\n");
8661    }
8662
8663    /* handle bits that were raised */
8664    if (asserted) {
8665        bxe_attn_int_asserted(sc, asserted);
8666    }
8667
8668    if (deasserted) {
8669        bxe_attn_int_deasserted(sc, deasserted);
8670    }
8671}
8672
8673static uint16_t
8674bxe_update_dsb_idx(struct bxe_softc *sc)
8675{
8676    struct host_sp_status_block *def_sb = sc->def_sb;
8677    uint16_t rc = 0;
8678
8679    mb(); /* status block is written to by the chip */
8680
8681    if (sc->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
8682        sc->def_att_idx = def_sb->atten_status_block.attn_bits_index;
8683        rc |= BXE_DEF_SB_ATT_IDX;
8684    }
8685
8686    if (sc->def_idx != def_sb->sp_sb.running_index) {
8687        sc->def_idx = def_sb->sp_sb.running_index;
8688        rc |= BXE_DEF_SB_IDX;
8689    }
8690
8691    mb();
8692
8693    return (rc);
8694}
8695
8696static inline struct ecore_queue_sp_obj *
8697bxe_cid_to_q_obj(struct bxe_softc *sc,
8698                 uint32_t         cid)
8699{
8700    BLOGD(sc, DBG_SP, "retrieving fp from cid %d\n", cid);
8701    return (&sc->sp_objs[CID_TO_FP(cid, sc)].q_obj);
8702}
8703
8704static void
8705bxe_handle_mcast_eqe(struct bxe_softc *sc)
8706{
8707    struct ecore_mcast_ramrod_params rparam;
8708    int rc;
8709
8710    memset(&rparam, 0, sizeof(rparam));
8711
8712    rparam.mcast_obj = &sc->mcast_obj;
8713
8714    BXE_MCAST_LOCK(sc);
8715
8716    /* clear pending state for the last command */
8717    sc->mcast_obj.raw.clear_pending(&sc->mcast_obj.raw);
8718
8719    /* if there are pending mcast commands - send them */
8720    if (sc->mcast_obj.check_pending(&sc->mcast_obj)) {
8721        rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
8722        if (rc < 0) {
8723            BLOGD(sc, DBG_SP,
8724                  "ERROR: Failed to send pending mcast commands (%d)\n",
8725                  rc);
8726        }
8727    }
8728
8729    BXE_MCAST_UNLOCK(sc);
8730}
8731
8732static void
8733bxe_handle_classification_eqe(struct bxe_softc      *sc,
8734                              union event_ring_elem *elem)
8735{
8736    unsigned long ramrod_flags = 0;
8737    int rc = 0;
8738    uint32_t cid = elem->message.data.eth_event.echo & BXE_SWCID_MASK;
8739    struct ecore_vlan_mac_obj *vlan_mac_obj;
8740
8741    /* always push next commands out, don't wait here */
8742    bit_set(&ramrod_flags, RAMROD_CONT);
8743
8744    switch (le32toh(elem->message.data.eth_event.echo) >> BXE_SWCID_SHIFT) {
8745    case ECORE_FILTER_MAC_PENDING:
8746        BLOGD(sc, DBG_SP, "Got SETUP_MAC completions\n");
8747        vlan_mac_obj = &sc->sp_objs[cid].mac_obj;
8748        break;
8749
8750    case ECORE_FILTER_MCAST_PENDING:
8751        BLOGD(sc, DBG_SP, "Got SETUP_MCAST completions\n");
8752        /*
8753         * This is only relevant for 57710 where multicast MACs are
8754         * configured as unicast MACs using the same ramrod.
8755         */
8756        bxe_handle_mcast_eqe(sc);
8757        return;
8758
8759    default:
8760        BLOGE(sc, "Unsupported classification command: %d\n",
8761              elem->message.data.eth_event.echo);
8762        return;
8763    }
8764
8765    rc = vlan_mac_obj->complete(sc, vlan_mac_obj, elem, &ramrod_flags);
8766
8767    if (rc < 0) {
8768        BLOGE(sc, "Failed to schedule new commands (%d)\n", rc);
8769    } else if (rc > 0) {
8770        BLOGD(sc, DBG_SP, "Scheduled next pending commands...\n");
8771    }
8772}
8773
8774static void
8775bxe_handle_rx_mode_eqe(struct bxe_softc      *sc,
8776                       union event_ring_elem *elem)
8777{
8778    bxe_clear_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
8779
8780    /* send rx_mode command again if was requested */
8781    if (bxe_test_and_clear_bit(ECORE_FILTER_RX_MODE_SCHED,
8782                               &sc->sp_state)) {
8783        bxe_set_storm_rx_mode(sc);
8784    }
8785#if 0
8786    else if (bxe_test_and_clear_bit(ECORE_FILTER_ISCSI_ETH_START_SCHED,
8787                                    &sc->sp_state)) {
8788        bxe_set_iscsi_eth_rx_mode(sc, TRUE);
8789    }
8790    else if (bxe_test_and_clear_bit(ECORE_FILTER_ISCSI_ETH_STOP_SCHED,
8791                                    &sc->sp_state)) {
8792        bxe_set_iscsi_eth_rx_mode(sc, FALSE);
8793    }
8794#endif
8795}
8796
8797static void
8798bxe_update_eq_prod(struct bxe_softc *sc,
8799                   uint16_t         prod)
8800{
8801    storm_memset_eq_prod(sc, prod, SC_FUNC(sc));
8802    wmb(); /* keep prod updates ordered */
8803}
8804
8805static void
8806bxe_eq_int(struct bxe_softc *sc)
8807{
8808    uint16_t hw_cons, sw_cons, sw_prod;
8809    union event_ring_elem *elem;
8810    uint8_t echo;
8811    uint32_t cid;
8812    uint8_t opcode;
8813    int spqe_cnt = 0;
8814    struct ecore_queue_sp_obj *q_obj;
8815    struct ecore_func_sp_obj *f_obj = &sc->func_obj;
8816    struct ecore_raw_obj *rss_raw = &sc->rss_conf_obj.raw;
8817
8818    hw_cons = le16toh(*sc->eq_cons_sb);
8819
8820    /*
8821     * The hw_cons range is 1-255, 257 - the sw_cons range is 0-254, 256.
8822     * when we get to the next-page we need to adjust so the loop
8823     * condition below will be met. The next element is the size of a
8824     * regular element and hence incrementing by 1
8825     */
8826    if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE) {
8827        hw_cons++;
8828    }
8829
8830    /*
8831     * This function may never run in parallel with itself for a
8832     * specific sc and no need for a read memory barrier here.
8833     */
8834    sw_cons = sc->eq_cons;
8835    sw_prod = sc->eq_prod;
8836
8837    BLOGD(sc, DBG_SP,"EQ: hw_cons=%u sw_cons=%u eq_spq_left=0x%lx\n",
8838          hw_cons, sw_cons, atomic_load_acq_long(&sc->eq_spq_left));
8839
8840    for (;
8841         sw_cons != hw_cons;
8842         sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
8843
8844        elem = &sc->eq[EQ_DESC(sw_cons)];
8845
8846#if 0
8847        int rc;
8848        rc = bxe_iov_eq_sp_event(sc, elem);
8849        if (!rc) {
8850            BLOGE(sc, "bxe_iov_eq_sp_event returned %d\n", rc);
8851            goto next_spqe;
8852        }
8853#endif
8854
8855        /* elem CID originates from FW, actually LE */
8856        cid = SW_CID(elem->message.data.cfc_del_event.cid);
8857        opcode = elem->message.opcode;
8858
8859        /* handle eq element */
8860        switch (opcode) {
8861#if 0
8862        case EVENT_RING_OPCODE_VF_PF_CHANNEL:
8863            BLOGD(sc, DBG_SP, "vf/pf channel element on eq\n");
8864            bxe_vf_mbx(sc, &elem->message.data.vf_pf_event);
8865            continue;
8866#endif
8867
8868        case EVENT_RING_OPCODE_STAT_QUERY:
8869            BLOGD(sc, DBG_SP, "got statistics completion event %d\n",
8870                  sc->stats_comp++);
8871            /* nothing to do with stats comp */
8872            goto next_spqe;
8873
8874        case EVENT_RING_OPCODE_CFC_DEL:
8875            /* handle according to cid range */
8876            /* we may want to verify here that the sc state is HALTING */
8877            BLOGD(sc, DBG_SP, "got delete ramrod for MULTI[%d]\n", cid);
8878            q_obj = bxe_cid_to_q_obj(sc, cid);
8879            if (q_obj->complete_cmd(sc, q_obj, ECORE_Q_CMD_CFC_DEL)) {
8880                break;
8881            }
8882            goto next_spqe;
8883
8884        case EVENT_RING_OPCODE_STOP_TRAFFIC:
8885            BLOGD(sc, DBG_SP, "got STOP TRAFFIC\n");
8886            if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_TX_STOP)) {
8887                break;
8888            }
8889            // XXX bxe_dcbx_set_params(sc, BXE_DCBX_STATE_TX_PAUSED);
8890            goto next_spqe;
8891
8892        case EVENT_RING_OPCODE_START_TRAFFIC:
8893            BLOGD(sc, DBG_SP, "got START TRAFFIC\n");
8894            if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_TX_START)) {
8895                break;
8896            }
8897            // XXX bxe_dcbx_set_params(sc, BXE_DCBX_STATE_TX_RELEASED);
8898            goto next_spqe;
8899
8900        case EVENT_RING_OPCODE_FUNCTION_UPDATE:
8901            echo = elem->message.data.function_update_event.echo;
8902            if (echo == SWITCH_UPDATE) {
8903                BLOGD(sc, DBG_SP, "got FUNC_SWITCH_UPDATE ramrod\n");
8904                if (f_obj->complete_cmd(sc, f_obj,
8905                                        ECORE_F_CMD_SWITCH_UPDATE)) {
8906                    break;
8907                }
8908            }
8909            else {
8910                BLOGD(sc, DBG_SP,
8911                      "AFEX: ramrod completed FUNCTION_UPDATE\n");
8912#if 0
8913                f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_AFEX_UPDATE);
8914                /*
8915                 * We will perform the queues update from the sp_core_task as
8916                 * all queue SP operations should run with CORE_LOCK.
8917                 */
8918                bxe_set_bit(BXE_SP_CORE_AFEX_F_UPDATE, &sc->sp_core_state);
8919                taskqueue_enqueue(sc->sp_tq, &sc->sp_tq_task);
8920#endif
8921            }
8922            goto next_spqe;
8923
8924#if 0
8925        case EVENT_RING_OPCODE_AFEX_VIF_LISTS:
8926            f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_AFEX_VIFLISTS);
8927            bxe_after_afex_vif_lists(sc, elem);
8928            goto next_spqe;
8929#endif
8930
8931        case EVENT_RING_OPCODE_FORWARD_SETUP:
8932            q_obj = &bxe_fwd_sp_obj(sc, q_obj);
8933            if (q_obj->complete_cmd(sc, q_obj,
8934                                    ECORE_Q_CMD_SETUP_TX_ONLY)) {
8935                break;
8936            }
8937            goto next_spqe;
8938
8939        case EVENT_RING_OPCODE_FUNCTION_START:
8940            BLOGD(sc, DBG_SP, "got FUNC_START ramrod\n");
8941            if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_START)) {
8942                break;
8943            }
8944            goto next_spqe;
8945
8946        case EVENT_RING_OPCODE_FUNCTION_STOP:
8947            BLOGD(sc, DBG_SP, "got FUNC_STOP ramrod\n");
8948            if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_STOP)) {
8949                break;
8950            }
8951            goto next_spqe;
8952        }
8953
8954        switch (opcode | sc->state) {
8955        case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BXE_STATE_OPEN):
8956        case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BXE_STATE_OPENING_WAITING_PORT):
8957            cid = elem->message.data.eth_event.echo & BXE_SWCID_MASK;
8958            BLOGD(sc, DBG_SP, "got RSS_UPDATE ramrod. CID %d\n", cid);
8959            rss_raw->clear_pending(rss_raw);
8960            break;
8961
8962        case (EVENT_RING_OPCODE_SET_MAC | BXE_STATE_OPEN):
8963        case (EVENT_RING_OPCODE_SET_MAC | BXE_STATE_DIAG):
8964        case (EVENT_RING_OPCODE_SET_MAC | BXE_STATE_CLOSING_WAITING_HALT):
8965        case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BXE_STATE_OPEN):
8966        case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BXE_STATE_DIAG):
8967        case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BXE_STATE_CLOSING_WAITING_HALT):
8968            BLOGD(sc, DBG_SP, "got (un)set mac ramrod\n");
8969            bxe_handle_classification_eqe(sc, elem);
8970            break;
8971
8972        case (EVENT_RING_OPCODE_MULTICAST_RULES | BXE_STATE_OPEN):
8973        case (EVENT_RING_OPCODE_MULTICAST_RULES | BXE_STATE_DIAG):
8974        case (EVENT_RING_OPCODE_MULTICAST_RULES | BXE_STATE_CLOSING_WAITING_HALT):
8975            BLOGD(sc, DBG_SP, "got mcast ramrod\n");
8976            bxe_handle_mcast_eqe(sc);
8977            break;
8978
8979        case (EVENT_RING_OPCODE_FILTERS_RULES | BXE_STATE_OPEN):
8980        case (EVENT_RING_OPCODE_FILTERS_RULES | BXE_STATE_DIAG):
8981        case (EVENT_RING_OPCODE_FILTERS_RULES | BXE_STATE_CLOSING_WAITING_HALT):
8982            BLOGD(sc, DBG_SP, "got rx_mode ramrod\n");
8983            bxe_handle_rx_mode_eqe(sc, elem);
8984            break;
8985
8986        default:
8987            /* unknown event log error and continue */
8988            BLOGE(sc, "Unknown EQ event %d, sc->state 0x%x\n",
8989                  elem->message.opcode, sc->state);
8990        }
8991
8992next_spqe:
8993        spqe_cnt++;
8994    } /* for */
8995
8996    mb();
8997    atomic_add_acq_long(&sc->eq_spq_left, spqe_cnt);
8998
8999    sc->eq_cons = sw_cons;
9000    sc->eq_prod = sw_prod;
9001
9002    /* make sure that above mem writes were issued towards the memory */
9003    wmb();
9004
9005    /* update producer */
9006    bxe_update_eq_prod(sc, sc->eq_prod);
9007}
9008
9009static void
9010bxe_handle_sp_tq(void *context,
9011                 int  pending)
9012{
9013    struct bxe_softc *sc = (struct bxe_softc *)context;
9014    uint16_t status;
9015
9016    BLOGD(sc, DBG_SP, "---> SP TASK <---\n");
9017
9018    /* what work needs to be performed? */
9019    status = bxe_update_dsb_idx(sc);
9020
9021    BLOGD(sc, DBG_SP, "dsb status 0x%04x\n", status);
9022
9023    /* HW attentions */
9024    if (status & BXE_DEF_SB_ATT_IDX) {
9025        BLOGD(sc, DBG_SP, "---> ATTN INTR <---\n");
9026        bxe_attn_int(sc);
9027        status &= ~BXE_DEF_SB_ATT_IDX;
9028    }
9029
9030    /* SP events: STAT_QUERY and others */
9031    if (status & BXE_DEF_SB_IDX) {
9032        /* handle EQ completions */
9033        BLOGD(sc, DBG_SP, "---> EQ INTR <---\n");
9034        bxe_eq_int(sc);
9035        bxe_ack_sb(sc, sc->igu_dsb_id, USTORM_ID,
9036                   le16toh(sc->def_idx), IGU_INT_NOP, 1);
9037        status &= ~BXE_DEF_SB_IDX;
9038    }
9039
9040    /* if status is non zero then something went wrong */
9041    if (__predict_false(status)) {
9042        BLOGE(sc, "Got an unknown SP interrupt! (0x%04x)\n", status);
9043    }
9044
9045    /* ack status block only if something was actually handled */
9046    bxe_ack_sb(sc, sc->igu_dsb_id, ATTENTION_ID,
9047               le16toh(sc->def_att_idx), IGU_INT_ENABLE, 1);
9048
9049    /*
9050     * Must be called after the EQ processing (since eq leads to sriov
9051     * ramrod completion flows).
9052     * This flow may have been scheduled by the arrival of a ramrod
9053     * completion, or by the sriov code rescheduling itself.
9054     */
9055    // XXX bxe_iov_sp_task(sc);
9056
9057#if 0
9058    /* AFEX - poll to check if VIFSET_ACK should be sent to MFW */
9059    if (bxe_test_and_clear_bit(ECORE_AFEX_PENDING_VIFSET_MCP_ACK,
9060                               &sc->sp_state)) {
9061        bxe_link_report(sc);
9062        bxe_fw_command(sc, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
9063    }
9064#endif
9065}
9066
9067static void
9068bxe_handle_fp_tq(void *context,
9069                 int  pending)
9070{
9071    struct bxe_fastpath *fp = (struct bxe_fastpath *)context;
9072    struct bxe_softc *sc = fp->sc;
9073    uint8_t more_tx = FALSE;
9074    uint8_t more_rx = FALSE;
9075
9076    BLOGD(sc, DBG_INTR, "---> FP TASK QUEUE (%d) <---\n", fp->index);
9077
9078    /* XXX
9079     * IFF_DRV_RUNNING state can't be checked here since we process
9080     * slowpath events on a client queue during setup. Instead
9081     * we need to add a "process/continue" flag here that the driver
9082     * can use to tell the task here not to do anything.
9083     */
9084#if 0
9085    if (!(if_getdrvflags(sc->ifp) & IFF_DRV_RUNNING)) {
9086        return;
9087    }
9088#endif
9089
9090    /* update the fastpath index */
9091    bxe_update_fp_sb_idx(fp);
9092
9093    /* XXX add loop here if ever support multiple tx CoS */
9094    /* fp->txdata[cos] */
9095    if (bxe_has_tx_work(fp)) {
9096        BXE_FP_TX_LOCK(fp);
9097        more_tx = bxe_txeof(sc, fp);
9098        BXE_FP_TX_UNLOCK(fp);
9099    }
9100
9101    if (bxe_has_rx_work(fp)) {
9102        more_rx = bxe_rxeof(sc, fp);
9103    }
9104
9105    if (more_rx /*|| more_tx*/) {
9106        /* still more work to do */
9107        taskqueue_enqueue_fast(fp->tq, &fp->tq_task);
9108        return;
9109    }
9110
9111    bxe_ack_sb(sc, fp->igu_sb_id, USTORM_ID,
9112               le16toh(fp->fp_hc_idx), IGU_INT_ENABLE, 1);
9113}
9114
9115static void
9116bxe_task_fp(struct bxe_fastpath *fp)
9117{
9118    struct bxe_softc *sc = fp->sc;
9119    uint8_t more_tx = FALSE;
9120    uint8_t more_rx = FALSE;
9121
9122    BLOGD(sc, DBG_INTR, "---> FP TASK ISR (%d) <---\n", fp->index);
9123
9124    /* update the fastpath index */
9125    bxe_update_fp_sb_idx(fp);
9126
9127    /* XXX add loop here if ever support multiple tx CoS */
9128    /* fp->txdata[cos] */
9129    if (bxe_has_tx_work(fp)) {
9130        BXE_FP_TX_LOCK(fp);
9131        more_tx = bxe_txeof(sc, fp);
9132        BXE_FP_TX_UNLOCK(fp);
9133    }
9134
9135    if (bxe_has_rx_work(fp)) {
9136        more_rx = bxe_rxeof(sc, fp);
9137    }
9138
9139    if (more_rx /*|| more_tx*/) {
9140        /* still more work to do, bail out if this ISR and process later */
9141        taskqueue_enqueue_fast(fp->tq, &fp->tq_task);
9142        return;
9143    }
9144
9145    /*
9146     * Here we write the fastpath index taken before doing any tx or rx work.
9147     * It is very well possible other hw events occurred up to this point and
9148     * they were actually processed accordingly above. Since we're going to
9149     * write an older fastpath index, an interrupt is coming which we might
9150     * not do any work in.
9151     */
9152    bxe_ack_sb(sc, fp->igu_sb_id, USTORM_ID,
9153               le16toh(fp->fp_hc_idx), IGU_INT_ENABLE, 1);
9154}
9155
9156/*
9157 * Legacy interrupt entry point.
9158 *
9159 * Verifies that the controller generated the interrupt and
9160 * then calls a separate routine to handle the various
9161 * interrupt causes: link, RX, and TX.
9162 */
9163static void
9164bxe_intr_legacy(void *xsc)
9165{
9166    struct bxe_softc *sc = (struct bxe_softc *)xsc;
9167    struct bxe_fastpath *fp;
9168    uint16_t status, mask;
9169    int i;
9170
9171    BLOGD(sc, DBG_INTR, "---> BXE INTx <---\n");
9172
9173#if 0
9174    /* Don't handle any interrupts if we're not ready. */
9175    if (__predict_false(sc->intr_sem != 0)) {
9176        return;
9177    }
9178#endif
9179
9180    /*
9181     * 0 for ustorm, 1 for cstorm
9182     * the bits returned from ack_int() are 0-15
9183     * bit 0 = attention status block
9184     * bit 1 = fast path status block
9185     * a mask of 0x2 or more = tx/rx event
9186     * a mask of 1 = slow path event
9187     */
9188
9189    status = bxe_ack_int(sc);
9190
9191    /* the interrupt is not for us */
9192    if (__predict_false(status == 0)) {
9193        BLOGD(sc, DBG_INTR, "Not our interrupt!\n");
9194        return;
9195    }
9196
9197    BLOGD(sc, DBG_INTR, "Interrupt status 0x%04x\n", status);
9198
9199    FOR_EACH_ETH_QUEUE(sc, i) {
9200        fp = &sc->fp[i];
9201        mask = (0x2 << (fp->index + CNIC_SUPPORT(sc)));
9202        if (status & mask) {
9203            /* acknowledge and disable further fastpath interrupts */
9204            bxe_ack_sb(sc, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_DISABLE, 0);
9205            bxe_task_fp(fp);
9206            status &= ~mask;
9207        }
9208    }
9209
9210#if 0
9211    if (CNIC_SUPPORT(sc)) {
9212        mask = 0x2;
9213        if (status & (mask | 0x1)) {
9214            ...
9215            status &= ~mask;
9216        }
9217    }
9218#endif
9219
9220    if (__predict_false(status & 0x1)) {
9221        /* acknowledge and disable further slowpath interrupts */
9222        bxe_ack_sb(sc, sc->igu_dsb_id, USTORM_ID, 0, IGU_INT_DISABLE, 0);
9223
9224        /* schedule slowpath handler */
9225        taskqueue_enqueue_fast(sc->sp_tq, &sc->sp_tq_task);
9226
9227        status &= ~0x1;
9228    }
9229
9230    if (__predict_false(status)) {
9231        BLOGW(sc, "Unexpected fastpath status (0x%08x)!\n", status);
9232    }
9233}
9234
9235/* slowpath interrupt entry point */
9236static void
9237bxe_intr_sp(void *xsc)
9238{
9239    struct bxe_softc *sc = (struct bxe_softc *)xsc;
9240
9241    BLOGD(sc, (DBG_INTR | DBG_SP), "---> SP INTR <---\n");
9242
9243    /* acknowledge and disable further slowpath interrupts */
9244    bxe_ack_sb(sc, sc->igu_dsb_id, USTORM_ID, 0, IGU_INT_DISABLE, 0);
9245
9246    /* schedule slowpath handler */
9247    taskqueue_enqueue_fast(sc->sp_tq, &sc->sp_tq_task);
9248}
9249
9250/* fastpath interrupt entry point */
9251static void
9252bxe_intr_fp(void *xfp)
9253{
9254    struct bxe_fastpath *fp = (struct bxe_fastpath *)xfp;
9255    struct bxe_softc *sc = fp->sc;
9256
9257    BLOGD(sc, DBG_INTR, "---> FP INTR %d <---\n", fp->index);
9258
9259    BLOGD(sc, DBG_INTR,
9260          "(cpu=%d) MSI-X fp=%d fw_sb=%d igu_sb=%d\n",
9261          curcpu, fp->index, fp->fw_sb_id, fp->igu_sb_id);
9262
9263#if 0
9264    /* Don't handle any interrupts if we're not ready. */
9265    if (__predict_false(sc->intr_sem != 0)) {
9266        return;
9267    }
9268#endif
9269
9270    /* acknowledge and disable further fastpath interrupts */
9271    bxe_ack_sb(sc, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_DISABLE, 0);
9272
9273    bxe_task_fp(fp);
9274}
9275
9276/* Release all interrupts allocated by the driver. */
9277static void
9278bxe_interrupt_free(struct bxe_softc *sc)
9279{
9280    int i;
9281
9282    switch (sc->interrupt_mode) {
9283    case INTR_MODE_INTX:
9284        BLOGD(sc, DBG_LOAD, "Releasing legacy INTx vector\n");
9285        if (sc->intr[0].resource != NULL) {
9286            bus_release_resource(sc->dev,
9287                                 SYS_RES_IRQ,
9288                                 sc->intr[0].rid,
9289                                 sc->intr[0].resource);
9290        }
9291        break;
9292    case INTR_MODE_MSI:
9293        for (i = 0; i < sc->intr_count; i++) {
9294            BLOGD(sc, DBG_LOAD, "Releasing MSI vector %d\n", i);
9295            if (sc->intr[i].resource && sc->intr[i].rid) {
9296                bus_release_resource(sc->dev,
9297                                     SYS_RES_IRQ,
9298                                     sc->intr[i].rid,
9299                                     sc->intr[i].resource);
9300            }
9301        }
9302        pci_release_msi(sc->dev);
9303        break;
9304    case INTR_MODE_MSIX:
9305        for (i = 0; i < sc->intr_count; i++) {
9306            BLOGD(sc, DBG_LOAD, "Releasing MSI-X vector %d\n", i);
9307            if (sc->intr[i].resource && sc->intr[i].rid) {
9308                bus_release_resource(sc->dev,
9309                                     SYS_RES_IRQ,
9310                                     sc->intr[i].rid,
9311                                     sc->intr[i].resource);
9312            }
9313        }
9314        pci_release_msi(sc->dev);
9315        break;
9316    default:
9317        /* nothing to do as initial allocation failed */
9318        break;
9319    }
9320}
9321
9322/*
9323 * This function determines and allocates the appropriate
9324 * interrupt based on system capabilites and user request.
9325 *
9326 * The user may force a particular interrupt mode, specify
9327 * the number of receive queues, specify the method for
9328 * distribuitng received frames to receive queues, or use
9329 * the default settings which will automatically select the
9330 * best supported combination.  In addition, the OS may or
9331 * may not support certain combinations of these settings.
9332 * This routine attempts to reconcile the settings requested
9333 * by the user with the capabilites available from the system
9334 * to select the optimal combination of features.
9335 *
9336 * Returns:
9337 *   0 = Success, !0 = Failure.
9338 */
9339static int
9340bxe_interrupt_alloc(struct bxe_softc *sc)
9341{
9342    int msix_count = 0;
9343    int msi_count = 0;
9344    int num_requested = 0;
9345    int num_allocated = 0;
9346    int rid, i, j;
9347    int rc;
9348
9349    /* get the number of available MSI/MSI-X interrupts from the OS */
9350    if (sc->interrupt_mode > 0) {
9351        if (sc->devinfo.pcie_cap_flags & BXE_MSIX_CAPABLE_FLAG) {
9352            msix_count = pci_msix_count(sc->dev);
9353        }
9354
9355        if (sc->devinfo.pcie_cap_flags & BXE_MSI_CAPABLE_FLAG) {
9356            msi_count = pci_msi_count(sc->dev);
9357        }
9358
9359        BLOGD(sc, DBG_LOAD, "%d MSI and %d MSI-X vectors available\n",
9360              msi_count, msix_count);
9361    }
9362
9363    do { /* try allocating MSI-X interrupt resources (at least 2) */
9364        if (sc->interrupt_mode != INTR_MODE_MSIX) {
9365            break;
9366        }
9367
9368        if (((sc->devinfo.pcie_cap_flags & BXE_MSIX_CAPABLE_FLAG) == 0) ||
9369            (msix_count < 2)) {
9370            sc->interrupt_mode = INTR_MODE_MSI; /* try MSI next */
9371            break;
9372        }
9373
9374        /* ask for the necessary number of MSI-X vectors */
9375        num_requested = min((sc->num_queues + 1), msix_count);
9376
9377        BLOGD(sc, DBG_LOAD, "Requesting %d MSI-X vectors\n", num_requested);
9378
9379        num_allocated = num_requested;
9380        if ((rc = pci_alloc_msix(sc->dev, &num_allocated)) != 0) {
9381            BLOGE(sc, "MSI-X alloc failed! (%d)\n", rc);
9382            sc->interrupt_mode = INTR_MODE_MSI; /* try MSI next */
9383            break;
9384        }
9385
9386        if (num_allocated < 2) { /* possible? */
9387            BLOGE(sc, "MSI-X allocation less than 2!\n");
9388            sc->interrupt_mode = INTR_MODE_MSI; /* try MSI next */
9389            pci_release_msi(sc->dev);
9390            break;
9391        }
9392
9393        BLOGI(sc, "MSI-X vectors Requested %d and Allocated %d\n",
9394              num_requested, num_allocated);
9395
9396        /* best effort so use the number of vectors allocated to us */
9397        sc->intr_count = num_allocated;
9398        sc->num_queues = num_allocated - 1;
9399
9400        rid = 1; /* initial resource identifier */
9401
9402        /* allocate the MSI-X vectors */
9403        for (i = 0; i < num_allocated; i++) {
9404            sc->intr[i].rid = (rid + i);
9405
9406            if ((sc->intr[i].resource =
9407                 bus_alloc_resource_any(sc->dev,
9408                                        SYS_RES_IRQ,
9409                                        &sc->intr[i].rid,
9410                                        RF_ACTIVE)) == NULL) {
9411                BLOGE(sc, "Failed to map MSI-X[%d] (rid=%d)!\n",
9412                      i, (rid + i));
9413
9414                for (j = (i - 1); j >= 0; j--) {
9415                    bus_release_resource(sc->dev,
9416                                         SYS_RES_IRQ,
9417                                         sc->intr[j].rid,
9418                                         sc->intr[j].resource);
9419                }
9420
9421                sc->intr_count = 0;
9422                sc->num_queues = 0;
9423                sc->interrupt_mode = INTR_MODE_MSI; /* try MSI next */
9424                pci_release_msi(sc->dev);
9425                break;
9426            }
9427
9428            BLOGD(sc, DBG_LOAD, "Mapped MSI-X[%d] (rid=%d)\n", i, (rid + i));
9429        }
9430    } while (0);
9431
9432    do { /* try allocating MSI vector resources (at least 2) */
9433        if (sc->interrupt_mode != INTR_MODE_MSI) {
9434            break;
9435        }
9436
9437        if (((sc->devinfo.pcie_cap_flags & BXE_MSI_CAPABLE_FLAG) == 0) ||
9438            (msi_count < 1)) {
9439            sc->interrupt_mode = INTR_MODE_INTX; /* try INTx next */
9440            break;
9441        }
9442
9443        /* ask for a single MSI vector */
9444        num_requested = 1;
9445
9446        BLOGD(sc, DBG_LOAD, "Requesting %d MSI vectors\n", num_requested);
9447
9448        num_allocated = num_requested;
9449        if ((rc = pci_alloc_msi(sc->dev, &num_allocated)) != 0) {
9450            BLOGE(sc, "MSI alloc failed (%d)!\n", rc);
9451            sc->interrupt_mode = INTR_MODE_INTX; /* try INTx next */
9452            break;
9453        }
9454
9455        if (num_allocated != 1) { /* possible? */
9456            BLOGE(sc, "MSI allocation is not 1!\n");
9457            sc->interrupt_mode = INTR_MODE_INTX; /* try INTx next */
9458            pci_release_msi(sc->dev);
9459            break;
9460        }
9461
9462        BLOGI(sc, "MSI vectors Requested %d and Allocated %d\n",
9463              num_requested, num_allocated);
9464
9465        /* best effort so use the number of vectors allocated to us */
9466        sc->intr_count = num_allocated;
9467        sc->num_queues = num_allocated;
9468
9469        rid = 1; /* initial resource identifier */
9470
9471        sc->intr[0].rid = rid;
9472
9473        if ((sc->intr[0].resource =
9474             bus_alloc_resource_any(sc->dev,
9475                                    SYS_RES_IRQ,
9476                                    &sc->intr[0].rid,
9477                                    RF_ACTIVE)) == NULL) {
9478            BLOGE(sc, "Failed to map MSI[0] (rid=%d)!\n", rid);
9479            sc->intr_count = 0;
9480            sc->num_queues = 0;
9481            sc->interrupt_mode = INTR_MODE_INTX; /* try INTx next */
9482            pci_release_msi(sc->dev);
9483            break;
9484        }
9485
9486        BLOGD(sc, DBG_LOAD, "Mapped MSI[0] (rid=%d)\n", rid);
9487    } while (0);
9488
9489    do { /* try allocating INTx vector resources */
9490        if (sc->interrupt_mode != INTR_MODE_INTX) {
9491            break;
9492        }
9493
9494        BLOGD(sc, DBG_LOAD, "Requesting legacy INTx interrupt\n");
9495
9496        /* only one vector for INTx */
9497        sc->intr_count = 1;
9498        sc->num_queues = 1;
9499
9500        rid = 0; /* initial resource identifier */
9501
9502        sc->intr[0].rid = rid;
9503
9504        if ((sc->intr[0].resource =
9505             bus_alloc_resource_any(sc->dev,
9506                                    SYS_RES_IRQ,
9507                                    &sc->intr[0].rid,
9508                                    (RF_ACTIVE | RF_SHAREABLE))) == NULL) {
9509            BLOGE(sc, "Failed to map INTx (rid=%d)!\n", rid);
9510            sc->intr_count = 0;
9511            sc->num_queues = 0;
9512            sc->interrupt_mode = -1; /* Failed! */
9513            break;
9514        }
9515
9516        BLOGD(sc, DBG_LOAD, "Mapped INTx (rid=%d)\n", rid);
9517    } while (0);
9518
9519    if (sc->interrupt_mode == -1) {
9520        BLOGE(sc, "Interrupt Allocation: FAILED!!!\n");
9521        rc = 1;
9522    } else {
9523        BLOGD(sc, DBG_LOAD,
9524              "Interrupt Allocation: interrupt_mode=%d, num_queues=%d\n",
9525              sc->interrupt_mode, sc->num_queues);
9526        rc = 0;
9527    }
9528
9529    return (rc);
9530}
9531
9532static void
9533bxe_interrupt_detach(struct bxe_softc *sc)
9534{
9535    struct bxe_fastpath *fp;
9536    int i;
9537
9538    /* release interrupt resources */
9539    for (i = 0; i < sc->intr_count; i++) {
9540        if (sc->intr[i].resource && sc->intr[i].tag) {
9541            BLOGD(sc, DBG_LOAD, "Disabling interrupt vector %d\n", i);
9542            bus_teardown_intr(sc->dev, sc->intr[i].resource, sc->intr[i].tag);
9543        }
9544    }
9545
9546    for (i = 0; i < sc->num_queues; i++) {
9547        fp = &sc->fp[i];
9548        if (fp->tq) {
9549            taskqueue_drain(fp->tq, &fp->tq_task);
9550            taskqueue_free(fp->tq);
9551            fp->tq = NULL;
9552        }
9553    }
9554
9555
9556    if (sc->sp_tq) {
9557        taskqueue_drain(sc->sp_tq, &sc->sp_tq_task);
9558        taskqueue_free(sc->sp_tq);
9559        sc->sp_tq = NULL;
9560    }
9561}
9562
9563/*
9564 * Enables interrupts and attach to the ISR.
9565 *
9566 * When using multiple MSI/MSI-X vectors the first vector
9567 * is used for slowpath operations while all remaining
9568 * vectors are used for fastpath operations.  If only a
9569 * single MSI/MSI-X vector is used (SINGLE_ISR) then the
9570 * ISR must look for both slowpath and fastpath completions.
9571 */
9572static int
9573bxe_interrupt_attach(struct bxe_softc *sc)
9574{
9575    struct bxe_fastpath *fp;
9576    int rc = 0;
9577    int i;
9578
9579    snprintf(sc->sp_tq_name, sizeof(sc->sp_tq_name),
9580             "bxe%d_sp_tq", sc->unit);
9581    TASK_INIT(&sc->sp_tq_task, 0, bxe_handle_sp_tq, sc);
9582    sc->sp_tq = taskqueue_create_fast(sc->sp_tq_name, M_NOWAIT,
9583                                      taskqueue_thread_enqueue,
9584                                      &sc->sp_tq);
9585    taskqueue_start_threads(&sc->sp_tq, 1, PWAIT, /* lower priority */
9586                            "%s", sc->sp_tq_name);
9587
9588
9589    for (i = 0; i < sc->num_queues; i++) {
9590        fp = &sc->fp[i];
9591        snprintf(fp->tq_name, sizeof(fp->tq_name),
9592                 "bxe%d_fp%d_tq", sc->unit, i);
9593        TASK_INIT(&fp->tq_task, 0, bxe_handle_fp_tq, fp);
9594        fp->tq = taskqueue_create_fast(fp->tq_name, M_NOWAIT,
9595                                       taskqueue_thread_enqueue,
9596                                       &fp->tq);
9597        taskqueue_start_threads(&fp->tq, 1, PI_NET, /* higher priority */
9598                                "%s", fp->tq_name);
9599    }
9600
9601    /* setup interrupt handlers */
9602    if (sc->interrupt_mode == INTR_MODE_MSIX) {
9603        BLOGD(sc, DBG_LOAD, "Enabling slowpath MSI-X[0] vector\n");
9604
9605        /*
9606         * Setup the interrupt handler. Note that we pass the driver instance
9607         * to the interrupt handler for the slowpath.
9608         */
9609        if ((rc = bus_setup_intr(sc->dev, sc->intr[0].resource,
9610                                 (INTR_TYPE_NET | INTR_MPSAFE),
9611                                 NULL, bxe_intr_sp, sc,
9612                                 &sc->intr[0].tag)) != 0) {
9613            BLOGE(sc, "Failed to allocate MSI-X[0] vector (%d)\n", rc);
9614            goto bxe_interrupt_attach_exit;
9615        }
9616
9617        bus_describe_intr(sc->dev, sc->intr[0].resource,
9618                          sc->intr[0].tag, "sp");
9619
9620        /* bus_bind_intr(sc->dev, sc->intr[0].resource, 0); */
9621
9622        /* initialize the fastpath vectors (note the first was used for sp) */
9623        for (i = 0; i < sc->num_queues; i++) {
9624            fp = &sc->fp[i];
9625            BLOGD(sc, DBG_LOAD, "Enabling MSI-X[%d] vector\n", (i + 1));
9626
9627            /*
9628             * Setup the interrupt handler. Note that we pass the
9629             * fastpath context to the interrupt handler in this
9630             * case.
9631             */
9632            if ((rc = bus_setup_intr(sc->dev, sc->intr[i + 1].resource,
9633                                     (INTR_TYPE_NET | INTR_MPSAFE),
9634                                     NULL, bxe_intr_fp, fp,
9635                                     &sc->intr[i + 1].tag)) != 0) {
9636                BLOGE(sc, "Failed to allocate MSI-X[%d] vector (%d)\n",
9637                      (i + 1), rc);
9638                goto bxe_interrupt_attach_exit;
9639            }
9640
9641            bus_describe_intr(sc->dev, sc->intr[i + 1].resource,
9642                              sc->intr[i + 1].tag, "fp%02d", i);
9643
9644            /* bind the fastpath instance to a cpu */
9645            if (sc->num_queues > 1) {
9646                bus_bind_intr(sc->dev, sc->intr[i + 1].resource, i);
9647            }
9648
9649            fp->state = BXE_FP_STATE_IRQ;
9650        }
9651    } else if (sc->interrupt_mode == INTR_MODE_MSI) {
9652        BLOGD(sc, DBG_LOAD, "Enabling MSI[0] vector\n");
9653
9654        /*
9655         * Setup the interrupt handler. Note that we pass the
9656         * driver instance to the interrupt handler which
9657         * will handle both the slowpath and fastpath.
9658         */
9659        if ((rc = bus_setup_intr(sc->dev, sc->intr[0].resource,
9660                                 (INTR_TYPE_NET | INTR_MPSAFE),
9661                                 NULL, bxe_intr_legacy, sc,
9662                                 &sc->intr[0].tag)) != 0) {
9663            BLOGE(sc, "Failed to allocate MSI[0] vector (%d)\n", rc);
9664            goto bxe_interrupt_attach_exit;
9665        }
9666
9667    } else { /* (sc->interrupt_mode == INTR_MODE_INTX) */
9668        BLOGD(sc, DBG_LOAD, "Enabling INTx interrupts\n");
9669
9670        /*
9671         * Setup the interrupt handler. Note that we pass the
9672         * driver instance to the interrupt handler which
9673         * will handle both the slowpath and fastpath.
9674         */
9675        if ((rc = bus_setup_intr(sc->dev, sc->intr[0].resource,
9676                                 (INTR_TYPE_NET | INTR_MPSAFE),
9677                                 NULL, bxe_intr_legacy, sc,
9678                                 &sc->intr[0].tag)) != 0) {
9679            BLOGE(sc, "Failed to allocate INTx interrupt (%d)\n", rc);
9680            goto bxe_interrupt_attach_exit;
9681        }
9682    }
9683
9684bxe_interrupt_attach_exit:
9685
9686    return (rc);
9687}
9688
9689static int  bxe_init_hw_common_chip(struct bxe_softc *sc);
9690static int  bxe_init_hw_common(struct bxe_softc *sc);
9691static int  bxe_init_hw_port(struct bxe_softc *sc);
9692static int  bxe_init_hw_func(struct bxe_softc *sc);
9693static void bxe_reset_common(struct bxe_softc *sc);
9694static void bxe_reset_port(struct bxe_softc *sc);
9695static void bxe_reset_func(struct bxe_softc *sc);
9696static int  bxe_gunzip_init(struct bxe_softc *sc);
9697static void bxe_gunzip_end(struct bxe_softc *sc);
9698static int  bxe_init_firmware(struct bxe_softc *sc);
9699static void bxe_release_firmware(struct bxe_softc *sc);
9700
9701static struct
9702ecore_func_sp_drv_ops bxe_func_sp_drv = {
9703    .init_hw_cmn_chip = bxe_init_hw_common_chip,
9704    .init_hw_cmn      = bxe_init_hw_common,
9705    .init_hw_port     = bxe_init_hw_port,
9706    .init_hw_func     = bxe_init_hw_func,
9707
9708    .reset_hw_cmn     = bxe_reset_common,
9709    .reset_hw_port    = bxe_reset_port,
9710    .reset_hw_func    = bxe_reset_func,
9711
9712    .gunzip_init      = bxe_gunzip_init,
9713    .gunzip_end       = bxe_gunzip_end,
9714
9715    .init_fw          = bxe_init_firmware,
9716    .release_fw       = bxe_release_firmware,
9717};
9718
9719static void
9720bxe_init_func_obj(struct bxe_softc *sc)
9721{
9722    sc->dmae_ready = 0;
9723
9724    ecore_init_func_obj(sc,
9725                        &sc->func_obj,
9726                        BXE_SP(sc, func_rdata),
9727                        BXE_SP_MAPPING(sc, func_rdata),
9728                        BXE_SP(sc, func_afex_rdata),
9729                        BXE_SP_MAPPING(sc, func_afex_rdata),
9730                        &bxe_func_sp_drv);
9731}
9732
9733static int
9734bxe_init_hw(struct bxe_softc *sc,
9735            uint32_t         load_code)
9736{
9737    struct ecore_func_state_params func_params = { NULL };
9738    int rc;
9739
9740    /* prepare the parameters for function state transitions */
9741    bit_set(&func_params.ramrod_flags, RAMROD_COMP_WAIT);
9742
9743    func_params.f_obj = &sc->func_obj;
9744    func_params.cmd = ECORE_F_CMD_HW_INIT;
9745
9746    func_params.params.hw_init.load_phase = load_code;
9747
9748    /*
9749     * Via a plethora of function pointers, we will eventually reach
9750     * bxe_init_hw_common(), bxe_init_hw_port(), or bxe_init_hw_func().
9751     */
9752    rc = ecore_func_state_change(sc, &func_params);
9753
9754    return (rc);
9755}
9756
9757static void
9758bxe_fill(struct bxe_softc *sc,
9759         uint32_t         addr,
9760         int              fill,
9761         uint32_t         len)
9762{
9763    uint32_t i;
9764
9765    if (!(len % 4) && !(addr % 4)) {
9766        for (i = 0; i < len; i += 4) {
9767            REG_WR(sc, (addr + i), fill);
9768        }
9769    } else {
9770        for (i = 0; i < len; i++) {
9771            REG_WR8(sc, (addr + i), fill);
9772        }
9773    }
9774}
9775
9776/* writes FP SP data to FW - data_size in dwords */
9777static void
9778bxe_wr_fp_sb_data(struct bxe_softc *sc,
9779                  int              fw_sb_id,
9780                  uint32_t         *sb_data_p,
9781                  uint32_t         data_size)
9782{
9783    int index;
9784
9785    for (index = 0; index < data_size; index++) {
9786        REG_WR(sc,
9787               (BAR_CSTRORM_INTMEM +
9788                CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
9789                (sizeof(uint32_t) * index)),
9790               *(sb_data_p + index));
9791    }
9792}
9793
9794static void
9795bxe_zero_fp_sb(struct bxe_softc *sc,
9796               int              fw_sb_id)
9797{
9798    struct hc_status_block_data_e2 sb_data_e2;
9799    struct hc_status_block_data_e1x sb_data_e1x;
9800    uint32_t *sb_data_p;
9801    uint32_t data_size = 0;
9802
9803    if (!CHIP_IS_E1x(sc)) {
9804        memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
9805        sb_data_e2.common.state = SB_DISABLED;
9806        sb_data_e2.common.p_func.vf_valid = FALSE;
9807        sb_data_p = (uint32_t *)&sb_data_e2;
9808        data_size = (sizeof(struct hc_status_block_data_e2) /
9809                     sizeof(uint32_t));
9810    } else {
9811        memset(&sb_data_e1x, 0, sizeof(struct hc_status_block_data_e1x));
9812        sb_data_e1x.common.state = SB_DISABLED;
9813        sb_data_e1x.common.p_func.vf_valid = FALSE;
9814        sb_data_p = (uint32_t *)&sb_data_e1x;
9815        data_size = (sizeof(struct hc_status_block_data_e1x) /
9816                     sizeof(uint32_t));
9817    }
9818
9819    bxe_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
9820
9821    bxe_fill(sc, (BAR_CSTRORM_INTMEM + CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id)),
9822             0, CSTORM_STATUS_BLOCK_SIZE);
9823    bxe_fill(sc, (BAR_CSTRORM_INTMEM + CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id)),
9824             0, CSTORM_SYNC_BLOCK_SIZE);
9825}
9826
9827static void
9828bxe_wr_sp_sb_data(struct bxe_softc               *sc,
9829                  struct hc_sp_status_block_data *sp_sb_data)
9830{
9831    int i;
9832
9833    for (i = 0;
9834         i < (sizeof(struct hc_sp_status_block_data) / sizeof(uint32_t));
9835         i++) {
9836        REG_WR(sc,
9837               (BAR_CSTRORM_INTMEM +
9838                CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(SC_FUNC(sc)) +
9839                (i * sizeof(uint32_t))),
9840               *((uint32_t *)sp_sb_data + i));
9841    }
9842}
9843
9844static void
9845bxe_zero_sp_sb(struct bxe_softc *sc)
9846{
9847    struct hc_sp_status_block_data sp_sb_data;
9848
9849    memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
9850
9851    sp_sb_data.state           = SB_DISABLED;
9852    sp_sb_data.p_func.vf_valid = FALSE;
9853
9854    bxe_wr_sp_sb_data(sc, &sp_sb_data);
9855
9856    bxe_fill(sc,
9857             (BAR_CSTRORM_INTMEM +
9858              CSTORM_SP_STATUS_BLOCK_OFFSET(SC_FUNC(sc))),
9859              0, CSTORM_SP_STATUS_BLOCK_SIZE);
9860    bxe_fill(sc,
9861             (BAR_CSTRORM_INTMEM +
9862              CSTORM_SP_SYNC_BLOCK_OFFSET(SC_FUNC(sc))),
9863              0, CSTORM_SP_SYNC_BLOCK_SIZE);
9864}
9865
9866static void
9867bxe_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
9868                             int                       igu_sb_id,
9869                             int                       igu_seg_id)
9870{
9871    hc_sm->igu_sb_id      = igu_sb_id;
9872    hc_sm->igu_seg_id     = igu_seg_id;
9873    hc_sm->timer_value    = 0xFF;
9874    hc_sm->time_to_expire = 0xFFFFFFFF;
9875}
9876
9877static void
9878bxe_map_sb_state_machines(struct hc_index_data *index_data)
9879{
9880    /* zero out state machine indices */
9881
9882    /* rx indices */
9883    index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
9884
9885    /* tx indices */
9886    index_data[HC_INDEX_OOO_TX_CQ_CONS].flags      &= ~HC_INDEX_DATA_SM_ID;
9887    index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
9888    index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
9889    index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
9890
9891    /* map indices */
9892
9893    /* rx indices */
9894    index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
9895        (SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
9896
9897    /* tx indices */
9898    index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
9899        (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
9900    index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
9901        (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
9902    index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
9903        (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
9904    index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
9905        (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
9906}
9907
9908static void
9909bxe_init_sb(struct bxe_softc *sc,
9910            bus_addr_t       busaddr,
9911            int              vfid,
9912            uint8_t          vf_valid,
9913            int              fw_sb_id,
9914            int              igu_sb_id)
9915{
9916    struct hc_status_block_data_e2  sb_data_e2;
9917    struct hc_status_block_data_e1x sb_data_e1x;
9918    struct hc_status_block_sm       *hc_sm_p;
9919    uint32_t *sb_data_p;
9920    int igu_seg_id;
9921    int data_size;
9922
9923    if (CHIP_INT_MODE_IS_BC(sc)) {
9924        igu_seg_id = HC_SEG_ACCESS_NORM;
9925    } else {
9926        igu_seg_id = IGU_SEG_ACCESS_NORM;
9927    }
9928
9929    bxe_zero_fp_sb(sc, fw_sb_id);
9930
9931    if (!CHIP_IS_E1x(sc)) {
9932        memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
9933        sb_data_e2.common.state = SB_ENABLED;
9934        sb_data_e2.common.p_func.pf_id = SC_FUNC(sc);
9935        sb_data_e2.common.p_func.vf_id = vfid;
9936        sb_data_e2.common.p_func.vf_valid = vf_valid;
9937        sb_data_e2.common.p_func.vnic_id = SC_VN(sc);
9938        sb_data_e2.common.same_igu_sb_1b = TRUE;
9939        sb_data_e2.common.host_sb_addr.hi = U64_HI(busaddr);
9940        sb_data_e2.common.host_sb_addr.lo = U64_LO(busaddr);
9941        hc_sm_p = sb_data_e2.common.state_machine;
9942        sb_data_p = (uint32_t *)&sb_data_e2;
9943        data_size = (sizeof(struct hc_status_block_data_e2) /
9944                     sizeof(uint32_t));
9945        bxe_map_sb_state_machines(sb_data_e2.index_data);
9946    } else {
9947        memset(&sb_data_e1x, 0, sizeof(struct hc_status_block_data_e1x));
9948        sb_data_e1x.common.state = SB_ENABLED;
9949        sb_data_e1x.common.p_func.pf_id = SC_FUNC(sc);
9950        sb_data_e1x.common.p_func.vf_id = 0xff;
9951        sb_data_e1x.common.p_func.vf_valid = FALSE;
9952        sb_data_e1x.common.p_func.vnic_id = SC_VN(sc);
9953        sb_data_e1x.common.same_igu_sb_1b = TRUE;
9954        sb_data_e1x.common.host_sb_addr.hi = U64_HI(busaddr);
9955        sb_data_e1x.common.host_sb_addr.lo = U64_LO(busaddr);
9956        hc_sm_p = sb_data_e1x.common.state_machine;
9957        sb_data_p = (uint32_t *)&sb_data_e1x;
9958        data_size = (sizeof(struct hc_status_block_data_e1x) /
9959                     sizeof(uint32_t));
9960        bxe_map_sb_state_machines(sb_data_e1x.index_data);
9961    }
9962
9963    bxe_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], igu_sb_id, igu_seg_id);
9964    bxe_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], igu_sb_id, igu_seg_id);
9965
9966    BLOGD(sc, DBG_LOAD, "Init FW SB %d\n", fw_sb_id);
9967
9968    /* write indices to HW - PCI guarantees endianity of regpairs */
9969    bxe_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
9970}
9971
9972static inline uint8_t
9973bxe_fp_qzone_id(struct bxe_fastpath *fp)
9974{
9975    if (CHIP_IS_E1x(fp->sc)) {
9976        return (fp->cl_id + SC_PORT(fp->sc) * ETH_MAX_RX_CLIENTS_E1H);
9977    } else {
9978        return (fp->cl_id);
9979    }
9980}
9981
9982static inline uint32_t
9983bxe_rx_ustorm_prods_offset(struct bxe_softc    *sc,
9984                           struct bxe_fastpath *fp)
9985{
9986    uint32_t offset = BAR_USTRORM_INTMEM;
9987
9988#if 0
9989    if (IS_VF(sc)) {
9990        return (PXP_VF_ADDR_USDM_QUEUES_START +
9991                (sc->acquire_resp.resc.hw_qid[fp->index] *
9992                 sizeof(struct ustorm_queue_zone_data)));
9993    } else
9994#endif
9995    if (!CHIP_IS_E1x(sc)) {
9996        offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
9997    } else {
9998        offset += USTORM_RX_PRODS_E1X_OFFSET(SC_PORT(sc), fp->cl_id);
9999    }
10000
10001    return (offset);
10002}
10003
10004static void
10005bxe_init_eth_fp(struct bxe_softc *sc,
10006                int              idx)
10007{
10008    struct bxe_fastpath *fp = &sc->fp[idx];
10009    uint32_t cids[ECORE_MULTI_TX_COS] = { 0 };
10010    unsigned long q_type = 0;
10011    int cos;
10012
10013    fp->sc    = sc;
10014    fp->index = idx;
10015
10016    snprintf(fp->tx_mtx_name, sizeof(fp->tx_mtx_name),
10017             "bxe%d_fp%d_tx_lock", sc->unit, idx);
10018    mtx_init(&fp->tx_mtx, fp->tx_mtx_name, NULL, MTX_DEF);
10019
10020    snprintf(fp->rx_mtx_name, sizeof(fp->rx_mtx_name),
10021             "bxe%d_fp%d_rx_lock", sc->unit, idx);
10022    mtx_init(&fp->rx_mtx, fp->rx_mtx_name, NULL, MTX_DEF);
10023
10024    fp->igu_sb_id = (sc->igu_base_sb + idx + CNIC_SUPPORT(sc));
10025    fp->fw_sb_id = (sc->base_fw_ndsb + idx + CNIC_SUPPORT(sc));
10026
10027    fp->cl_id = (CHIP_IS_E1x(sc)) ?
10028                    (SC_L_ID(sc) + idx) :
10029                    /* want client ID same as IGU SB ID for non-E1 */
10030                    fp->igu_sb_id;
10031    fp->cl_qzone_id = bxe_fp_qzone_id(fp);
10032
10033    /* setup sb indices */
10034    if (!CHIP_IS_E1x(sc)) {
10035        fp->sb_index_values  = fp->status_block.e2_sb->sb.index_values;
10036        fp->sb_running_index = fp->status_block.e2_sb->sb.running_index;
10037    } else {
10038        fp->sb_index_values  = fp->status_block.e1x_sb->sb.index_values;
10039        fp->sb_running_index = fp->status_block.e1x_sb->sb.running_index;
10040    }
10041
10042    /* init shortcut */
10043    fp->ustorm_rx_prods_offset = bxe_rx_ustorm_prods_offset(sc, fp);
10044
10045    fp->rx_cq_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS];
10046
10047    /*
10048     * XXX If multiple CoS is ever supported then each fastpath structure
10049     * will need to maintain tx producer/consumer/dma/etc values *per* CoS.
10050     */
10051    for (cos = 0; cos < sc->max_cos; cos++) {
10052        cids[cos] = idx;
10053    }
10054    fp->tx_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0];
10055
10056    /* nothing more for a VF to do */
10057    if (IS_VF(sc)) {
10058        return;
10059    }
10060
10061    bxe_init_sb(sc, fp->sb_dma.paddr, BXE_VF_ID_INVALID, FALSE,
10062                fp->fw_sb_id, fp->igu_sb_id);
10063
10064    bxe_update_fp_sb_idx(fp);
10065
10066    /* Configure Queue State object */
10067    bit_set(&q_type, ECORE_Q_TYPE_HAS_RX);
10068    bit_set(&q_type, ECORE_Q_TYPE_HAS_TX);
10069
10070    ecore_init_queue_obj(sc,
10071                         &sc->sp_objs[idx].q_obj,
10072                         fp->cl_id,
10073                         cids,
10074                         sc->max_cos,
10075                         SC_FUNC(sc),
10076                         BXE_SP(sc, q_rdata),
10077                         BXE_SP_MAPPING(sc, q_rdata),
10078                         q_type);
10079
10080    /* configure classification DBs */
10081    ecore_init_mac_obj(sc,
10082                       &sc->sp_objs[idx].mac_obj,
10083                       fp->cl_id,
10084                       idx,
10085                       SC_FUNC(sc),
10086                       BXE_SP(sc, mac_rdata),
10087                       BXE_SP_MAPPING(sc, mac_rdata),
10088                       ECORE_FILTER_MAC_PENDING,
10089                       &sc->sp_state,
10090                       ECORE_OBJ_TYPE_RX_TX,
10091                       &sc->macs_pool);
10092
10093    BLOGD(sc, DBG_LOAD, "fp[%d]: sb=%p cl_id=%d fw_sb=%d igu_sb=%d\n",
10094          idx, fp->status_block.e2_sb, fp->cl_id, fp->fw_sb_id, fp->igu_sb_id);
10095}
10096
10097static inline void
10098bxe_update_rx_prod(struct bxe_softc    *sc,
10099                   struct bxe_fastpath *fp,
10100                   uint16_t            rx_bd_prod,
10101                   uint16_t            rx_cq_prod,
10102                   uint16_t            rx_sge_prod)
10103{
10104    struct ustorm_eth_rx_producers rx_prods = { 0 };
10105    uint32_t i;
10106
10107    /* update producers */
10108    rx_prods.bd_prod  = rx_bd_prod;
10109    rx_prods.cqe_prod = rx_cq_prod;
10110    rx_prods.sge_prod = rx_sge_prod;
10111
10112    /*
10113     * Make sure that the BD and SGE data is updated before updating the
10114     * producers since FW might read the BD/SGE right after the producer
10115     * is updated.
10116     * This is only applicable for weak-ordered memory model archs such
10117     * as IA-64. The following barrier is also mandatory since FW will
10118     * assumes BDs must have buffers.
10119     */
10120    wmb();
10121
10122    for (i = 0; i < (sizeof(rx_prods) / 4); i++) {
10123        REG_WR(sc,
10124               (fp->ustorm_rx_prods_offset + (i * 4)),
10125               ((uint32_t *)&rx_prods)[i]);
10126    }
10127
10128    wmb(); /* keep prod updates ordered */
10129
10130    BLOGD(sc, DBG_RX,
10131          "RX fp[%d]: wrote prods bd_prod=%u cqe_prod=%u sge_prod=%u\n",
10132          fp->index, rx_bd_prod, rx_cq_prod, rx_sge_prod);
10133}
10134
10135static void
10136bxe_init_rx_rings(struct bxe_softc *sc)
10137{
10138    struct bxe_fastpath *fp;
10139    int i;
10140
10141    for (i = 0; i < sc->num_queues; i++) {
10142        fp = &sc->fp[i];
10143
10144        fp->rx_bd_cons = 0;
10145
10146        /*
10147         * Activate the BD ring...
10148         * Warning, this will generate an interrupt (to the TSTORM)
10149         * so this can only be done after the chip is initialized
10150         */
10151        bxe_update_rx_prod(sc, fp,
10152                           fp->rx_bd_prod,
10153                           fp->rx_cq_prod,
10154                           fp->rx_sge_prod);
10155
10156        if (i != 0) {
10157            continue;
10158        }
10159
10160        if (CHIP_IS_E1(sc)) {
10161            REG_WR(sc,
10162                   (BAR_USTRORM_INTMEM +
10163                    USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(SC_FUNC(sc))),
10164                   U64_LO(fp->rcq_dma.paddr));
10165            REG_WR(sc,
10166                   (BAR_USTRORM_INTMEM +
10167                    USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(SC_FUNC(sc)) + 4),
10168                   U64_HI(fp->rcq_dma.paddr));
10169        }
10170    }
10171}
10172
10173static void
10174bxe_init_tx_ring_one(struct bxe_fastpath *fp)
10175{
10176    SET_FLAG(fp->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
10177    fp->tx_db.data.zero_fill1 = 0;
10178    fp->tx_db.data.prod = 0;
10179
10180    fp->tx_pkt_prod = 0;
10181    fp->tx_pkt_cons = 0;
10182    fp->tx_bd_prod = 0;
10183    fp->tx_bd_cons = 0;
10184    fp->eth_q_stats.tx_pkts = 0;
10185}
10186
10187static inline void
10188bxe_init_tx_rings(struct bxe_softc *sc)
10189{
10190    int i;
10191
10192    for (i = 0; i < sc->num_queues; i++) {
10193#if 0
10194        uint8_t cos;
10195        for (cos = 0; cos < sc->max_cos; cos++) {
10196            bxe_init_tx_ring_one(&sc->fp[i].txdata[cos]);
10197        }
10198#else
10199        bxe_init_tx_ring_one(&sc->fp[i]);
10200#endif
10201    }
10202}
10203
10204static void
10205bxe_init_def_sb(struct bxe_softc *sc)
10206{
10207    struct host_sp_status_block *def_sb = sc->def_sb;
10208    bus_addr_t mapping = sc->def_sb_dma.paddr;
10209    int igu_sp_sb_index;
10210    int igu_seg_id;
10211    int port = SC_PORT(sc);
10212    int func = SC_FUNC(sc);
10213    int reg_offset, reg_offset_en5;
10214    uint64_t section;
10215    int index, sindex;
10216    struct hc_sp_status_block_data sp_sb_data;
10217
10218    memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
10219
10220    if (CHIP_INT_MODE_IS_BC(sc)) {
10221        igu_sp_sb_index = DEF_SB_IGU_ID;
10222        igu_seg_id = HC_SEG_ACCESS_DEF;
10223    } else {
10224        igu_sp_sb_index = sc->igu_dsb_id;
10225        igu_seg_id = IGU_SEG_ACCESS_DEF;
10226    }
10227
10228    /* attentions */
10229    section = ((uint64_t)mapping +
10230               offsetof(struct host_sp_status_block, atten_status_block));
10231    def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
10232    sc->attn_state = 0;
10233
10234    reg_offset = (port) ?
10235                     MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
10236                     MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
10237    reg_offset_en5 = (port) ?
10238                         MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
10239                         MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0;
10240
10241    for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
10242        /* take care of sig[0]..sig[4] */
10243        for (sindex = 0; sindex < 4; sindex++) {
10244            sc->attn_group[index].sig[sindex] =
10245                REG_RD(sc, (reg_offset + (sindex * 0x4) + (0x10 * index)));
10246        }
10247
10248        if (!CHIP_IS_E1x(sc)) {
10249            /*
10250             * enable5 is separate from the rest of the registers,
10251             * and the address skip is 4 and not 16 between the
10252             * different groups
10253             */
10254            sc->attn_group[index].sig[4] =
10255                REG_RD(sc, (reg_offset_en5 + (0x4 * index)));
10256        } else {
10257            sc->attn_group[index].sig[4] = 0;
10258        }
10259    }
10260
10261    if (sc->devinfo.int_block == INT_BLOCK_HC) {
10262        reg_offset = (port) ?
10263                         HC_REG_ATTN_MSG1_ADDR_L :
10264                         HC_REG_ATTN_MSG0_ADDR_L;
10265        REG_WR(sc, reg_offset, U64_LO(section));
10266        REG_WR(sc, (reg_offset + 4), U64_HI(section));
10267    } else if (!CHIP_IS_E1x(sc)) {
10268        REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
10269        REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
10270    }
10271
10272    section = ((uint64_t)mapping +
10273               offsetof(struct host_sp_status_block, sp_sb));
10274
10275    bxe_zero_sp_sb(sc);
10276
10277    /* PCI guarantees endianity of regpair */
10278    sp_sb_data.state           = SB_ENABLED;
10279    sp_sb_data.host_sb_addr.lo = U64_LO(section);
10280    sp_sb_data.host_sb_addr.hi = U64_HI(section);
10281    sp_sb_data.igu_sb_id       = igu_sp_sb_index;
10282    sp_sb_data.igu_seg_id      = igu_seg_id;
10283    sp_sb_data.p_func.pf_id    = func;
10284    sp_sb_data.p_func.vnic_id  = SC_VN(sc);
10285    sp_sb_data.p_func.vf_id    = 0xff;
10286
10287    bxe_wr_sp_sb_data(sc, &sp_sb_data);
10288
10289    bxe_ack_sb(sc, sc->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
10290}
10291
10292static void
10293bxe_init_sp_ring(struct bxe_softc *sc)
10294{
10295    atomic_store_rel_long(&sc->cq_spq_left, MAX_SPQ_PENDING);
10296    sc->spq_prod_idx = 0;
10297    sc->dsb_sp_prod = &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_ETH_DEF_CONS];
10298    sc->spq_prod_bd = sc->spq;
10299    sc->spq_last_bd = (sc->spq_prod_bd + MAX_SP_DESC_CNT);
10300}
10301
10302static void
10303bxe_init_eq_ring(struct bxe_softc *sc)
10304{
10305    union event_ring_elem *elem;
10306    int i;
10307
10308    for (i = 1; i <= NUM_EQ_PAGES; i++) {
10309        elem = &sc->eq[EQ_DESC_CNT_PAGE * i - 1];
10310
10311        elem->next_page.addr.hi = htole32(U64_HI(sc->eq_dma.paddr +
10312                                                 BCM_PAGE_SIZE *
10313                                                 (i % NUM_EQ_PAGES)));
10314        elem->next_page.addr.lo = htole32(U64_LO(sc->eq_dma.paddr +
10315                                                 BCM_PAGE_SIZE *
10316                                                 (i % NUM_EQ_PAGES)));
10317    }
10318
10319    sc->eq_cons    = 0;
10320    sc->eq_prod    = NUM_EQ_DESC;
10321    sc->eq_cons_sb = &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_EQ_CONS];
10322
10323    atomic_store_rel_long(&sc->eq_spq_left,
10324                          (min((MAX_SP_DESC_CNT - MAX_SPQ_PENDING),
10325                               NUM_EQ_DESC) - 1));
10326}
10327
10328static void
10329bxe_init_internal_common(struct bxe_softc *sc)
10330{
10331    int i;
10332
10333    if (IS_MF_SI(sc)) {
10334        /*
10335         * In switch independent mode, the TSTORM needs to accept
10336         * packets that failed classification, since approximate match
10337         * mac addresses aren't written to NIG LLH.
10338         */
10339        REG_WR8(sc,
10340                (BAR_TSTRORM_INTMEM + TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET),
10341                2);
10342    } else if (!CHIP_IS_E1(sc)) { /* 57710 doesn't support MF */
10343        REG_WR8(sc,
10344                (BAR_TSTRORM_INTMEM + TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET),
10345                0);
10346    }
10347
10348    /*
10349     * Zero this manually as its initialization is currently missing
10350     * in the initTool.
10351     */
10352    for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) {
10353        REG_WR(sc,
10354               (BAR_USTRORM_INTMEM + USTORM_AGG_DATA_OFFSET + (i * 4)),
10355               0);
10356    }
10357
10358    if (!CHIP_IS_E1x(sc)) {
10359        REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET),
10360                CHIP_INT_MODE_IS_BC(sc) ? HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
10361    }
10362}
10363
10364static void
10365bxe_init_internal(struct bxe_softc *sc,
10366                  uint32_t         load_code)
10367{
10368    switch (load_code) {
10369    case FW_MSG_CODE_DRV_LOAD_COMMON:
10370    case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
10371        bxe_init_internal_common(sc);
10372        /* no break */
10373
10374    case FW_MSG_CODE_DRV_LOAD_PORT:
10375        /* nothing to do */
10376        /* no break */
10377
10378    case FW_MSG_CODE_DRV_LOAD_FUNCTION:
10379        /* internal memory per function is initialized inside bxe_pf_init */
10380        break;
10381
10382    default:
10383        BLOGE(sc, "Unknown load_code (0x%x) from MCP\n", load_code);
10384        break;
10385    }
10386}
10387
10388static void
10389storm_memset_func_cfg(struct bxe_softc                         *sc,
10390                      struct tstorm_eth_function_common_config *tcfg,
10391                      uint16_t                                  abs_fid)
10392{
10393    uint32_t addr;
10394    size_t size;
10395
10396    addr = (BAR_TSTRORM_INTMEM +
10397            TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid));
10398    size = sizeof(struct tstorm_eth_function_common_config);
10399    ecore_storm_memset_struct(sc, addr, size, (uint32_t *)tcfg);
10400}
10401
10402static void
10403bxe_func_init(struct bxe_softc            *sc,
10404              struct bxe_func_init_params *p)
10405{
10406    struct tstorm_eth_function_common_config tcfg = { 0 };
10407
10408    if (CHIP_IS_E1x(sc)) {
10409        storm_memset_func_cfg(sc, &tcfg, p->func_id);
10410    }
10411
10412    /* Enable the function in the FW */
10413    storm_memset_vf_to_pf(sc, p->func_id, p->pf_id);
10414    storm_memset_func_en(sc, p->func_id, 1);
10415
10416    /* spq */
10417    if (p->func_flgs & FUNC_FLG_SPQ) {
10418        storm_memset_spq_addr(sc, p->spq_map, p->func_id);
10419        REG_WR(sc,
10420               (XSEM_REG_FAST_MEMORY + XSTORM_SPQ_PROD_OFFSET(p->func_id)),
10421               p->spq_prod);
10422    }
10423}
10424
10425/*
10426 * Calculates the sum of vn_min_rates.
10427 * It's needed for further normalizing of the min_rates.
10428 * Returns:
10429 *   sum of vn_min_rates.
10430 *     or
10431 *   0 - if all the min_rates are 0.
10432 * In the later case fainess algorithm should be deactivated.
10433 * If all min rates are not zero then those that are zeroes will be set to 1.
10434 */
10435static void
10436bxe_calc_vn_min(struct bxe_softc       *sc,
10437                struct cmng_init_input *input)
10438{
10439    uint32_t vn_cfg;
10440    uint32_t vn_min_rate;
10441    int all_zero = 1;
10442    int vn;
10443
10444    for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
10445        vn_cfg = sc->devinfo.mf_info.mf_config[vn];
10446        vn_min_rate = (((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
10447                        FUNC_MF_CFG_MIN_BW_SHIFT) * 100);
10448
10449        if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
10450            /* skip hidden VNs */
10451            vn_min_rate = 0;
10452        } else if (!vn_min_rate) {
10453            /* If min rate is zero - set it to 100 */
10454            vn_min_rate = DEF_MIN_RATE;
10455        } else {
10456            all_zero = 0;
10457        }
10458
10459        input->vnic_min_rate[vn] = vn_min_rate;
10460    }
10461
10462    /* if ETS or all min rates are zeros - disable fairness */
10463    if (BXE_IS_ETS_ENABLED(sc)) {
10464        input->flags.cmng_enables &= ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
10465        BLOGD(sc, DBG_LOAD, "Fairness disabled (ETS)\n");
10466    } else if (all_zero) {
10467        input->flags.cmng_enables &= ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
10468        BLOGD(sc, DBG_LOAD,
10469              "Fariness disabled (all MIN values are zeroes)\n");
10470    } else {
10471        input->flags.cmng_enables |= CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
10472    }
10473}
10474
10475static inline uint16_t
10476bxe_extract_max_cfg(struct bxe_softc *sc,
10477                    uint32_t         mf_cfg)
10478{
10479    uint16_t max_cfg = ((mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
10480                        FUNC_MF_CFG_MAX_BW_SHIFT);
10481
10482    if (!max_cfg) {
10483        BLOGD(sc, DBG_LOAD, "Max BW configured to 0 - using 100 instead\n");
10484        max_cfg = 100;
10485    }
10486
10487    return (max_cfg);
10488}
10489
10490static void
10491bxe_calc_vn_max(struct bxe_softc       *sc,
10492                int                    vn,
10493                struct cmng_init_input *input)
10494{
10495    uint16_t vn_max_rate;
10496    uint32_t vn_cfg = sc->devinfo.mf_info.mf_config[vn];
10497    uint32_t max_cfg;
10498
10499    if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
10500        vn_max_rate = 0;
10501    } else {
10502        max_cfg = bxe_extract_max_cfg(sc, vn_cfg);
10503
10504        if (IS_MF_SI(sc)) {
10505            /* max_cfg in percents of linkspeed */
10506            vn_max_rate = ((sc->link_vars.line_speed * max_cfg) / 100);
10507        } else { /* SD modes */
10508            /* max_cfg is absolute in 100Mb units */
10509            vn_max_rate = (max_cfg * 100);
10510        }
10511    }
10512
10513    BLOGD(sc, DBG_LOAD, "vn %d: vn_max_rate %d\n", vn, vn_max_rate);
10514
10515    input->vnic_max_rate[vn] = vn_max_rate;
10516}
10517
10518static void
10519bxe_cmng_fns_init(struct bxe_softc *sc,
10520                  uint8_t          read_cfg,
10521                  uint8_t          cmng_type)
10522{
10523    struct cmng_init_input input;
10524    int vn;
10525
10526    memset(&input, 0, sizeof(struct cmng_init_input));
10527
10528    input.port_rate = sc->link_vars.line_speed;
10529
10530    if (cmng_type == CMNG_FNS_MINMAX) {
10531        /* read mf conf from shmem */
10532        if (read_cfg) {
10533            bxe_read_mf_cfg(sc);
10534        }
10535
10536        /* get VN min rate and enable fairness if not 0 */
10537        bxe_calc_vn_min(sc, &input);
10538
10539        /* get VN max rate */
10540        if (sc->port.pmf) {
10541            for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
10542                bxe_calc_vn_max(sc, vn, &input);
10543            }
10544        }
10545
10546        /* always enable rate shaping and fairness */
10547        input.flags.cmng_enables |= CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
10548
10549        ecore_init_cmng(&input, &sc->cmng);
10550        return;
10551    }
10552
10553    /* rate shaping and fairness are disabled */
10554    BLOGD(sc, DBG_LOAD, "rate shaping and fairness have been disabled\n");
10555}
10556
10557static int
10558bxe_get_cmng_fns_mode(struct bxe_softc *sc)
10559{
10560    if (CHIP_REV_IS_SLOW(sc)) {
10561        return (CMNG_FNS_NONE);
10562    }
10563
10564    if (IS_MF(sc)) {
10565        return (CMNG_FNS_MINMAX);
10566    }
10567
10568    return (CMNG_FNS_NONE);
10569}
10570
10571static void
10572storm_memset_cmng(struct bxe_softc *sc,
10573                  struct cmng_init *cmng,
10574                  uint8_t          port)
10575{
10576    int vn;
10577    int func;
10578    uint32_t addr;
10579    size_t size;
10580
10581    addr = (BAR_XSTRORM_INTMEM +
10582            XSTORM_CMNG_PER_PORT_VARS_OFFSET(port));
10583    size = sizeof(struct cmng_struct_per_port);
10584    ecore_storm_memset_struct(sc, addr, size, (uint32_t *)&cmng->port);
10585
10586    for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
10587        func = func_by_vn(sc, vn);
10588
10589        addr = (BAR_XSTRORM_INTMEM +
10590                XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func));
10591        size = sizeof(struct rate_shaping_vars_per_vn);
10592        ecore_storm_memset_struct(sc, addr, size,
10593                                  (uint32_t *)&cmng->vnic.vnic_max_rate[vn]);
10594
10595        addr = (BAR_XSTRORM_INTMEM +
10596                XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func));
10597        size = sizeof(struct fairness_vars_per_vn);
10598        ecore_storm_memset_struct(sc, addr, size,
10599                                  (uint32_t *)&cmng->vnic.vnic_min_rate[vn]);
10600    }
10601}
10602
10603static void
10604bxe_pf_init(struct bxe_softc *sc)
10605{
10606    struct bxe_func_init_params func_init = { 0 };
10607    struct event_ring_data eq_data = { { 0 } };
10608    uint16_t flags;
10609
10610    if (!CHIP_IS_E1x(sc)) {
10611        /* reset IGU PF statistics: MSIX + ATTN */
10612        /* PF */
10613        REG_WR(sc,
10614               (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
10615                (BXE_IGU_STAS_MSG_VF_CNT * 4) +
10616                ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) * 4)),
10617               0);
10618        /* ATTN */
10619        REG_WR(sc,
10620               (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
10621                (BXE_IGU_STAS_MSG_VF_CNT * 4) +
10622                (BXE_IGU_STAS_MSG_PF_CNT * 4) +
10623                ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) * 4)),
10624               0);
10625    }
10626
10627    /* function setup flags */
10628    flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
10629
10630    /*
10631     * This flag is relevant for E1x only.
10632     * E2 doesn't have a TPA configuration in a function level.
10633     */
10634    flags |= (if_getcapenable(sc->ifp) & IFCAP_LRO) ? FUNC_FLG_TPA : 0;
10635
10636    func_init.func_flgs = flags;
10637    func_init.pf_id     = SC_FUNC(sc);
10638    func_init.func_id   = SC_FUNC(sc);
10639    func_init.spq_map   = sc->spq_dma.paddr;
10640    func_init.spq_prod  = sc->spq_prod_idx;
10641
10642    bxe_func_init(sc, &func_init);
10643
10644    memset(&sc->cmng, 0, sizeof(struct cmng_struct_per_port));
10645
10646    /*
10647     * Congestion management values depend on the link rate.
10648     * There is no active link so initial link rate is set to 10Gbps.
10649     * When the link comes up the congestion management values are
10650     * re-calculated according to the actual link rate.
10651     */
10652    sc->link_vars.line_speed = SPEED_10000;
10653    bxe_cmng_fns_init(sc, TRUE, bxe_get_cmng_fns_mode(sc));
10654
10655    /* Only the PMF sets the HW */
10656    if (sc->port.pmf) {
10657        storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
10658    }
10659
10660    /* init Event Queue - PCI bus guarantees correct endainity */
10661    eq_data.base_addr.hi = U64_HI(sc->eq_dma.paddr);
10662    eq_data.base_addr.lo = U64_LO(sc->eq_dma.paddr);
10663    eq_data.producer     = sc->eq_prod;
10664    eq_data.index_id     = HC_SP_INDEX_EQ_CONS;
10665    eq_data.sb_id        = DEF_SB_ID;
10666    storm_memset_eq_data(sc, &eq_data, SC_FUNC(sc));
10667}
10668
10669static void
10670bxe_hc_int_enable(struct bxe_softc *sc)
10671{
10672    int port = SC_PORT(sc);
10673    uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
10674    uint32_t val = REG_RD(sc, addr);
10675    uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX) ? TRUE : FALSE;
10676    uint8_t single_msix = ((sc->interrupt_mode == INTR_MODE_MSIX) &&
10677                           (sc->intr_count == 1)) ? TRUE : FALSE;
10678    uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI) ? TRUE : FALSE;
10679
10680    if (msix) {
10681        val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
10682                 HC_CONFIG_0_REG_INT_LINE_EN_0);
10683        val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
10684                HC_CONFIG_0_REG_ATTN_BIT_EN_0);
10685        if (single_msix) {
10686            val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
10687        }
10688    } else if (msi) {
10689        val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
10690        val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
10691                HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
10692                HC_CONFIG_0_REG_ATTN_BIT_EN_0);
10693    } else {
10694        val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
10695                HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
10696                HC_CONFIG_0_REG_INT_LINE_EN_0 |
10697                HC_CONFIG_0_REG_ATTN_BIT_EN_0);
10698
10699        if (!CHIP_IS_E1(sc)) {
10700            BLOGD(sc, DBG_INTR, "write %x to HC %d (addr 0x%x)\n",
10701                  val, port, addr);
10702
10703            REG_WR(sc, addr, val);
10704
10705            val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
10706        }
10707    }
10708
10709    if (CHIP_IS_E1(sc)) {
10710        REG_WR(sc, (HC_REG_INT_MASK + port*4), 0x1FFFF);
10711    }
10712
10713    BLOGD(sc, DBG_INTR, "write %x to HC %d (addr 0x%x) mode %s\n",
10714          val, port, addr, ((msix) ? "MSI-X" : ((msi) ? "MSI" : "INTx")));
10715
10716    REG_WR(sc, addr, val);
10717
10718    /* ensure that HC_CONFIG is written before leading/trailing edge config */
10719    mb();
10720
10721    if (!CHIP_IS_E1(sc)) {
10722        /* init leading/trailing edge */
10723        if (IS_MF(sc)) {
10724            val = (0xee0f | (1 << (SC_VN(sc) + 4)));
10725            if (sc->port.pmf) {
10726                /* enable nig and gpio3 attention */
10727                val |= 0x1100;
10728            }
10729        } else {
10730            val = 0xffff;
10731        }
10732
10733        REG_WR(sc, (HC_REG_TRAILING_EDGE_0 + port*8), val);
10734        REG_WR(sc, (HC_REG_LEADING_EDGE_0 + port*8), val);
10735    }
10736
10737    /* make sure that interrupts are indeed enabled from here on */
10738    mb();
10739}
10740
10741static void
10742bxe_igu_int_enable(struct bxe_softc *sc)
10743{
10744    uint32_t val;
10745    uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX) ? TRUE : FALSE;
10746    uint8_t single_msix = ((sc->interrupt_mode == INTR_MODE_MSIX) &&
10747                           (sc->intr_count == 1)) ? TRUE : FALSE;
10748    uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI) ? TRUE : FALSE;
10749
10750    val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
10751
10752    if (msix) {
10753        val &= ~(IGU_PF_CONF_INT_LINE_EN |
10754                 IGU_PF_CONF_SINGLE_ISR_EN);
10755        val |= (IGU_PF_CONF_MSI_MSIX_EN |
10756                IGU_PF_CONF_ATTN_BIT_EN);
10757        if (single_msix) {
10758            val |= IGU_PF_CONF_SINGLE_ISR_EN;
10759        }
10760    } else if (msi) {
10761        val &= ~IGU_PF_CONF_INT_LINE_EN;
10762        val |= (IGU_PF_CONF_MSI_MSIX_EN |
10763                IGU_PF_CONF_ATTN_BIT_EN |
10764                IGU_PF_CONF_SINGLE_ISR_EN);
10765    } else {
10766        val &= ~IGU_PF_CONF_MSI_MSIX_EN;
10767        val |= (IGU_PF_CONF_INT_LINE_EN |
10768                IGU_PF_CONF_ATTN_BIT_EN |
10769                IGU_PF_CONF_SINGLE_ISR_EN);
10770    }
10771
10772    /* clean previous status - need to configure igu prior to ack*/
10773    if ((!msix) || single_msix) {
10774        REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
10775        bxe_ack_int(sc);
10776    }
10777
10778    val |= IGU_PF_CONF_FUNC_EN;
10779
10780    BLOGD(sc, DBG_INTR, "write 0x%x to IGU mode %s\n",
10781          val, ((msix) ? "MSI-X" : ((msi) ? "MSI" : "INTx")));
10782
10783    REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
10784
10785    mb();
10786
10787    /* init leading/trailing edge */
10788    if (IS_MF(sc)) {
10789        val = (0xee0f | (1 << (SC_VN(sc) + 4)));
10790        if (sc->port.pmf) {
10791            /* enable nig and gpio3 attention */
10792            val |= 0x1100;
10793        }
10794    } else {
10795        val = 0xffff;
10796    }
10797
10798    REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
10799    REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
10800
10801    /* make sure that interrupts are indeed enabled from here on */
10802    mb();
10803}
10804
10805static void
10806bxe_int_enable(struct bxe_softc *sc)
10807{
10808    if (sc->devinfo.int_block == INT_BLOCK_HC) {
10809        bxe_hc_int_enable(sc);
10810    } else {
10811        bxe_igu_int_enable(sc);
10812    }
10813}
10814
10815static void
10816bxe_hc_int_disable(struct bxe_softc *sc)
10817{
10818    int port = SC_PORT(sc);
10819    uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
10820    uint32_t val = REG_RD(sc, addr);
10821
10822    /*
10823     * In E1 we must use only PCI configuration space to disable MSI/MSIX
10824     * capablility. It's forbidden to disable IGU_PF_CONF_MSI_MSIX_EN in HC
10825     * block
10826     */
10827    if (CHIP_IS_E1(sc)) {
10828        /*
10829         * Since IGU_PF_CONF_MSI_MSIX_EN still always on use mask register
10830         * to prevent from HC sending interrupts after we exit the function
10831         */
10832        REG_WR(sc, (HC_REG_INT_MASK + port*4), 0);
10833
10834        val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
10835                 HC_CONFIG_0_REG_INT_LINE_EN_0 |
10836                 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
10837    } else {
10838        val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
10839                 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
10840                 HC_CONFIG_0_REG_INT_LINE_EN_0 |
10841                 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
10842    }
10843
10844    BLOGD(sc, DBG_INTR, "write %x to HC %d (addr 0x%x)\n", val, port, addr);
10845
10846    /* flush all outstanding writes */
10847    mb();
10848
10849    REG_WR(sc, addr, val);
10850    if (REG_RD(sc, addr) != val) {
10851        BLOGE(sc, "proper val not read from HC IGU!\n");
10852    }
10853}
10854
10855static void
10856bxe_igu_int_disable(struct bxe_softc *sc)
10857{
10858    uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
10859
10860    val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
10861             IGU_PF_CONF_INT_LINE_EN |
10862             IGU_PF_CONF_ATTN_BIT_EN);
10863
10864    BLOGD(sc, DBG_INTR, "write %x to IGU\n", val);
10865
10866    /* flush all outstanding writes */
10867    mb();
10868
10869    REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
10870    if (REG_RD(sc, IGU_REG_PF_CONFIGURATION) != val) {
10871        BLOGE(sc, "proper val not read from IGU!\n");
10872    }
10873}
10874
10875static void
10876bxe_int_disable(struct bxe_softc *sc)
10877{
10878    if (sc->devinfo.int_block == INT_BLOCK_HC) {
10879        bxe_hc_int_disable(sc);
10880    } else {
10881        bxe_igu_int_disable(sc);
10882    }
10883}
10884
10885static void
10886bxe_nic_init(struct bxe_softc *sc,
10887             int              load_code)
10888{
10889    int i;
10890
10891    for (i = 0; i < sc->num_queues; i++) {
10892        bxe_init_eth_fp(sc, i);
10893    }
10894
10895    rmb(); /* ensure status block indices were read */
10896
10897    bxe_init_rx_rings(sc);
10898    bxe_init_tx_rings(sc);
10899
10900    if (IS_VF(sc)) {
10901        return;
10902    }
10903
10904    /* initialize MOD_ABS interrupts */
10905    elink_init_mod_abs_int(sc, &sc->link_vars,
10906                           sc->devinfo.chip_id,
10907                           sc->devinfo.shmem_base,
10908                           sc->devinfo.shmem2_base,
10909                           SC_PORT(sc));
10910
10911    bxe_init_def_sb(sc);
10912    bxe_update_dsb_idx(sc);
10913    bxe_init_sp_ring(sc);
10914    bxe_init_eq_ring(sc);
10915    bxe_init_internal(sc, load_code);
10916    bxe_pf_init(sc);
10917    bxe_stats_init(sc);
10918
10919    /* flush all before enabling interrupts */
10920    mb();
10921
10922    bxe_int_enable(sc);
10923
10924    /* check for SPIO5 */
10925    bxe_attn_int_deasserted0(sc,
10926                             REG_RD(sc,
10927                                    (MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
10928                                     SC_PORT(sc)*4)) &
10929                             AEU_INPUTS_ATTN_BITS_SPIO5);
10930}
10931
10932static inline void
10933bxe_init_objs(struct bxe_softc *sc)
10934{
10935    /* mcast rules must be added to tx if tx switching is enabled */
10936    ecore_obj_type o_type =
10937        (sc->flags & BXE_TX_SWITCHING) ? ECORE_OBJ_TYPE_RX_TX :
10938                                         ECORE_OBJ_TYPE_RX;
10939
10940    /* RX_MODE controlling object */
10941    ecore_init_rx_mode_obj(sc, &sc->rx_mode_obj);
10942
10943    /* multicast configuration controlling object */
10944    ecore_init_mcast_obj(sc,
10945                         &sc->mcast_obj,
10946                         sc->fp[0].cl_id,
10947                         sc->fp[0].index,
10948                         SC_FUNC(sc),
10949                         SC_FUNC(sc),
10950                         BXE_SP(sc, mcast_rdata),
10951                         BXE_SP_MAPPING(sc, mcast_rdata),
10952                         ECORE_FILTER_MCAST_PENDING,
10953                         &sc->sp_state,
10954                         o_type);
10955
10956    /* Setup CAM credit pools */
10957    ecore_init_mac_credit_pool(sc,
10958                               &sc->macs_pool,
10959                               SC_FUNC(sc),
10960                               CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
10961                                                 VNICS_PER_PATH(sc));
10962
10963    ecore_init_vlan_credit_pool(sc,
10964                                &sc->vlans_pool,
10965                                SC_ABS_FUNC(sc) >> 1,
10966                                CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
10967                                                  VNICS_PER_PATH(sc));
10968
10969    /* RSS configuration object */
10970    ecore_init_rss_config_obj(sc,
10971                              &sc->rss_conf_obj,
10972                              sc->fp[0].cl_id,
10973                              sc->fp[0].index,
10974                              SC_FUNC(sc),
10975                              SC_FUNC(sc),
10976                              BXE_SP(sc, rss_rdata),
10977                              BXE_SP_MAPPING(sc, rss_rdata),
10978                              ECORE_FILTER_RSS_CONF_PENDING,
10979                              &sc->sp_state, ECORE_OBJ_TYPE_RX);
10980}
10981
10982/*
10983 * Initialize the function. This must be called before sending CLIENT_SETUP
10984 * for the first client.
10985 */
10986static inline int
10987bxe_func_start(struct bxe_softc *sc)
10988{
10989    struct ecore_func_state_params func_params = { NULL };
10990    struct ecore_func_start_params *start_params = &func_params.params.start;
10991
10992    /* Prepare parameters for function state transitions */
10993    bit_set(&func_params.ramrod_flags, RAMROD_COMP_WAIT);
10994
10995    func_params.f_obj = &sc->func_obj;
10996    func_params.cmd = ECORE_F_CMD_START;
10997
10998    /* Function parameters */
10999    start_params->mf_mode     = sc->devinfo.mf_info.mf_mode;
11000    start_params->sd_vlan_tag = OVLAN(sc);
11001
11002    if (CHIP_IS_E2(sc) || CHIP_IS_E3(sc)) {
11003        start_params->network_cos_mode = STATIC_COS;
11004    } else { /* CHIP_IS_E1X */
11005        start_params->network_cos_mode = FW_WRR;
11006    }
11007
11008    start_params->gre_tunnel_mode = 0;
11009    start_params->gre_tunnel_rss  = 0;
11010
11011    return (ecore_func_state_change(sc, &func_params));
11012}
11013
11014static int
11015bxe_set_power_state(struct bxe_softc *sc,
11016                    uint8_t          state)
11017{
11018    uint16_t pmcsr;
11019
11020    /* If there is no power capability, silently succeed */
11021    if (!(sc->devinfo.pcie_cap_flags & BXE_PM_CAPABLE_FLAG)) {
11022        BLOGW(sc, "No power capability\n");
11023        return (0);
11024    }
11025
11026    pmcsr = pci_read_config(sc->dev,
11027                            (sc->devinfo.pcie_pm_cap_reg + PCIR_POWER_STATUS),
11028                            2);
11029
11030    switch (state) {
11031    case PCI_PM_D0:
11032        pci_write_config(sc->dev,
11033                         (sc->devinfo.pcie_pm_cap_reg + PCIR_POWER_STATUS),
11034                         ((pmcsr & ~PCIM_PSTAT_DMASK) | PCIM_PSTAT_PME), 2);
11035
11036        if (pmcsr & PCIM_PSTAT_DMASK) {
11037            /* delay required during transition out of D3hot */
11038            DELAY(20000);
11039        }
11040
11041        break;
11042
11043    case PCI_PM_D3hot:
11044        /* XXX if there are other clients above don't shut down the power */
11045
11046        /* don't shut down the power for emulation and FPGA */
11047        if (CHIP_REV_IS_SLOW(sc)) {
11048            return (0);
11049        }
11050
11051        pmcsr &= ~PCIM_PSTAT_DMASK;
11052        pmcsr |= PCIM_PSTAT_D3;
11053
11054        if (sc->wol) {
11055            pmcsr |= PCIM_PSTAT_PMEENABLE;
11056        }
11057
11058        pci_write_config(sc->dev,
11059                         (sc->devinfo.pcie_pm_cap_reg + PCIR_POWER_STATUS),
11060                         pmcsr, 4);
11061
11062        /*
11063         * No more memory access after this point until device is brought back
11064         * to D0 state.
11065         */
11066        break;
11067
11068    default:
11069        BLOGE(sc, "Can't support PCI power state = %d\n", state);
11070        return (-1);
11071    }
11072
11073    return (0);
11074}
11075
11076
11077/* return true if succeeded to acquire the lock */
11078static uint8_t
11079bxe_trylock_hw_lock(struct bxe_softc *sc,
11080                    uint32_t         resource)
11081{
11082    uint32_t lock_status;
11083    uint32_t resource_bit = (1 << resource);
11084    int func = SC_FUNC(sc);
11085    uint32_t hw_lock_control_reg;
11086
11087    BLOGD(sc, DBG_LOAD, "Trying to take a resource lock 0x%x\n", resource);
11088
11089    /* Validating that the resource is within range */
11090    if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
11091        BLOGD(sc, DBG_LOAD,
11092              "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
11093              resource, HW_LOCK_MAX_RESOURCE_VALUE);
11094        return (FALSE);
11095    }
11096
11097    if (func <= 5) {
11098        hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
11099    } else {
11100        hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
11101    }
11102
11103    /* try to acquire the lock */
11104    REG_WR(sc, hw_lock_control_reg + 4, resource_bit);
11105    lock_status = REG_RD(sc, hw_lock_control_reg);
11106    if (lock_status & resource_bit) {
11107        return (TRUE);
11108    }
11109
11110    BLOGE(sc, "Failed to get a resource lock 0x%x\n", resource);
11111
11112    return (FALSE);
11113}
11114
11115/*
11116 * Get the recovery leader resource id according to the engine this function
11117 * belongs to. Currently only only 2 engines is supported.
11118 */
11119static int
11120bxe_get_leader_lock_resource(struct bxe_softc *sc)
11121{
11122    if (SC_PATH(sc)) {
11123        return (HW_LOCK_RESOURCE_RECOVERY_LEADER_1);
11124    } else {
11125        return (HW_LOCK_RESOURCE_RECOVERY_LEADER_0);
11126    }
11127}
11128
11129/* try to acquire a leader lock for current engine */
11130static uint8_t
11131bxe_trylock_leader_lock(struct bxe_softc *sc)
11132{
11133    return (bxe_trylock_hw_lock(sc, bxe_get_leader_lock_resource(sc)));
11134}
11135
11136static int
11137bxe_release_leader_lock(struct bxe_softc *sc)
11138{
11139    return (bxe_release_hw_lock(sc, bxe_get_leader_lock_resource(sc)));
11140}
11141
11142/* close gates #2, #3 and #4 */
11143static void
11144bxe_set_234_gates(struct bxe_softc *sc,
11145                  uint8_t          close)
11146{
11147    uint32_t val;
11148
11149    /* gates #2 and #4a are closed/opened for "not E1" only */
11150    if (!CHIP_IS_E1(sc)) {
11151        /* #4 */
11152        REG_WR(sc, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
11153        /* #2 */
11154        REG_WR(sc, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
11155    }
11156
11157    /* #3 */
11158    if (CHIP_IS_E1x(sc)) {
11159        /* prevent interrupts from HC on both ports */
11160        val = REG_RD(sc, HC_REG_CONFIG_1);
11161        REG_WR(sc, HC_REG_CONFIG_1,
11162               (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
11163               (val & ~(uint32_t)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
11164
11165        val = REG_RD(sc, HC_REG_CONFIG_0);
11166        REG_WR(sc, HC_REG_CONFIG_0,
11167               (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
11168               (val & ~(uint32_t)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
11169    } else {
11170        /* Prevent incomming interrupts in IGU */
11171        val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
11172
11173        REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION,
11174               (!close) ?
11175               (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
11176               (val & ~(uint32_t)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
11177    }
11178
11179    BLOGD(sc, DBG_LOAD, "%s gates #2, #3 and #4\n",
11180          close ? "closing" : "opening");
11181
11182    wmb();
11183}
11184
11185/* poll for pending writes bit, it should get cleared in no more than 1s */
11186static int
11187bxe_er_poll_igu_vq(struct bxe_softc *sc)
11188{
11189    uint32_t cnt = 1000;
11190    uint32_t pend_bits = 0;
11191
11192    do {
11193        pend_bits = REG_RD(sc, IGU_REG_PENDING_BITS_STATUS);
11194
11195        if (pend_bits == 0) {
11196            break;
11197        }
11198
11199        DELAY(1000);
11200    } while (--cnt > 0);
11201
11202    if (cnt == 0) {
11203        BLOGE(sc, "Still pending IGU requests bits=0x%08x!\n", pend_bits);
11204        return (-1);
11205    }
11206
11207    return (0);
11208}
11209
11210#define SHARED_MF_CLP_MAGIC  0x80000000 /* 'magic' bit */
11211
11212static void
11213bxe_clp_reset_prep(struct bxe_softc *sc,
11214                   uint32_t         *magic_val)
11215{
11216    /* Do some magic... */
11217    uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
11218    *magic_val = val & SHARED_MF_CLP_MAGIC;
11219    MFCFG_WR(sc, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
11220}
11221
11222/* restore the value of the 'magic' bit */
11223static void
11224bxe_clp_reset_done(struct bxe_softc *sc,
11225                   uint32_t         magic_val)
11226{
11227    /* Restore the 'magic' bit value... */
11228    uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
11229    MFCFG_WR(sc, shared_mf_config.clp_mb,
11230              (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
11231}
11232
11233/* prepare for MCP reset, takes care of CLP configurations */
11234static void
11235bxe_reset_mcp_prep(struct bxe_softc *sc,
11236                   uint32_t         *magic_val)
11237{
11238    uint32_t shmem;
11239    uint32_t validity_offset;
11240
11241    /* set `magic' bit in order to save MF config */
11242    if (!CHIP_IS_E1(sc)) {
11243        bxe_clp_reset_prep(sc, magic_val);
11244    }
11245
11246    /* get shmem offset */
11247    shmem = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
11248    validity_offset =
11249        offsetof(struct shmem_region, validity_map[SC_PORT(sc)]);
11250
11251    /* Clear validity map flags */
11252    if (shmem > 0) {
11253        REG_WR(sc, shmem + validity_offset, 0);
11254    }
11255}
11256
11257#define MCP_TIMEOUT      5000   /* 5 seconds (in ms) */
11258#define MCP_ONE_TIMEOUT  100    /* 100 ms */
11259
11260static void
11261bxe_mcp_wait_one(struct bxe_softc *sc)
11262{
11263    /* special handling for emulation and FPGA (10 times longer) */
11264    if (CHIP_REV_IS_SLOW(sc)) {
11265        DELAY((MCP_ONE_TIMEOUT*10) * 1000);
11266    } else {
11267        DELAY((MCP_ONE_TIMEOUT) * 1000);
11268    }
11269}
11270
11271/* initialize shmem_base and waits for validity signature to appear */
11272static int
11273bxe_init_shmem(struct bxe_softc *sc)
11274{
11275    int cnt = 0;
11276    uint32_t val = 0;
11277
11278    do {
11279        sc->devinfo.shmem_base     =
11280        sc->link_params.shmem_base =
11281            REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
11282
11283        if (sc->devinfo.shmem_base) {
11284            val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
11285            if (val & SHR_MEM_VALIDITY_MB)
11286                return (0);
11287        }
11288
11289        bxe_mcp_wait_one(sc);
11290
11291    } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
11292
11293    BLOGE(sc, "BAD MCP validity signature\n");
11294
11295    return (-1);
11296}
11297
11298static int
11299bxe_reset_mcp_comp(struct bxe_softc *sc,
11300                   uint32_t         magic_val)
11301{
11302    int rc = bxe_init_shmem(sc);
11303
11304    /* Restore the `magic' bit value */
11305    if (!CHIP_IS_E1(sc)) {
11306        bxe_clp_reset_done(sc, magic_val);
11307    }
11308
11309    return (rc);
11310}
11311
11312static void
11313bxe_pxp_prep(struct bxe_softc *sc)
11314{
11315    if (!CHIP_IS_E1(sc)) {
11316        REG_WR(sc, PXP2_REG_RD_START_INIT, 0);
11317        REG_WR(sc, PXP2_REG_RQ_RBC_DONE, 0);
11318        wmb();
11319    }
11320}
11321
11322/*
11323 * Reset the whole chip except for:
11324 *      - PCIE core
11325 *      - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by one reset bit)
11326 *      - IGU
11327 *      - MISC (including AEU)
11328 *      - GRC
11329 *      - RBCN, RBCP
11330 */
11331static void
11332bxe_process_kill_chip_reset(struct bxe_softc *sc,
11333                            uint8_t          global)
11334{
11335    uint32_t not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
11336    uint32_t global_bits2, stay_reset2;
11337
11338    /*
11339     * Bits that have to be set in reset_mask2 if we want to reset 'global'
11340     * (per chip) blocks.
11341     */
11342    global_bits2 =
11343        MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
11344        MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
11345
11346    /*
11347     * Don't reset the following blocks.
11348     * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
11349     *            reset, as in 4 port device they might still be owned
11350     *            by the MCP (there is only one leader per path).
11351     */
11352    not_reset_mask1 =
11353        MISC_REGISTERS_RESET_REG_1_RST_HC |
11354        MISC_REGISTERS_RESET_REG_1_RST_PXPV |
11355        MISC_REGISTERS_RESET_REG_1_RST_PXP;
11356
11357    not_reset_mask2 =
11358        MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
11359        MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
11360        MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
11361        MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
11362        MISC_REGISTERS_RESET_REG_2_RST_RBCN |
11363        MISC_REGISTERS_RESET_REG_2_RST_GRC  |
11364        MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
11365        MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
11366        MISC_REGISTERS_RESET_REG_2_RST_ATC |
11367        MISC_REGISTERS_RESET_REG_2_PGLC |
11368        MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
11369        MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
11370        MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
11371        MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
11372        MISC_REGISTERS_RESET_REG_2_UMAC0 |
11373        MISC_REGISTERS_RESET_REG_2_UMAC1;
11374
11375    /*
11376     * Keep the following blocks in reset:
11377     *  - all xxMACs are handled by the elink code.
11378     */
11379    stay_reset2 =
11380        MISC_REGISTERS_RESET_REG_2_XMAC |
11381        MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
11382
11383    /* Full reset masks according to the chip */
11384    reset_mask1 = 0xffffffff;
11385
11386    if (CHIP_IS_E1(sc))
11387        reset_mask2 = 0xffff;
11388    else if (CHIP_IS_E1H(sc))
11389        reset_mask2 = 0x1ffff;
11390    else if (CHIP_IS_E2(sc))
11391        reset_mask2 = 0xfffff;
11392    else /* CHIP_IS_E3 */
11393        reset_mask2 = 0x3ffffff;
11394
11395    /* Don't reset global blocks unless we need to */
11396    if (!global)
11397        reset_mask2 &= ~global_bits2;
11398
11399    /*
11400     * In case of attention in the QM, we need to reset PXP
11401     * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
11402     * because otherwise QM reset would release 'close the gates' shortly
11403     * before resetting the PXP, then the PSWRQ would send a write
11404     * request to PGLUE. Then when PXP is reset, PGLUE would try to
11405     * read the payload data from PSWWR, but PSWWR would not
11406     * respond. The write queue in PGLUE would stuck, dmae commands
11407     * would not return. Therefore it's important to reset the second
11408     * reset register (containing the
11409     * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
11410     * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
11411     * bit).
11412     */
11413    REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
11414           reset_mask2 & (~not_reset_mask2));
11415
11416    REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
11417           reset_mask1 & (~not_reset_mask1));
11418
11419    mb();
11420    wmb();
11421
11422    REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
11423           reset_mask2 & (~stay_reset2));
11424
11425    mb();
11426    wmb();
11427
11428    REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
11429    wmb();
11430}
11431
11432static int
11433bxe_process_kill(struct bxe_softc *sc,
11434                 uint8_t          global)
11435{
11436    int cnt = 1000;
11437    uint32_t val = 0;
11438    uint32_t sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
11439    uint32_t tags_63_32 = 0;
11440
11441    /* Empty the Tetris buffer, wait for 1s */
11442    do {
11443        sr_cnt  = REG_RD(sc, PXP2_REG_RD_SR_CNT);
11444        blk_cnt = REG_RD(sc, PXP2_REG_RD_BLK_CNT);
11445        port_is_idle_0 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_0);
11446        port_is_idle_1 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_1);
11447        pgl_exp_rom2 = REG_RD(sc, PXP2_REG_PGL_EXP_ROM2);
11448        if (CHIP_IS_E3(sc)) {
11449            tags_63_32 = REG_RD(sc, PGLUE_B_REG_TAGS_63_32);
11450        }
11451
11452        if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
11453            ((port_is_idle_0 & 0x1) == 0x1) &&
11454            ((port_is_idle_1 & 0x1) == 0x1) &&
11455            (pgl_exp_rom2 == 0xffffffff) &&
11456            (!CHIP_IS_E3(sc) || (tags_63_32 == 0xffffffff)))
11457            break;
11458        DELAY(1000);
11459    } while (cnt-- > 0);
11460
11461    if (cnt <= 0) {
11462        BLOGE(sc, "ERROR: Tetris buffer didn't get empty or there "
11463                  "are still outstanding read requests after 1s! "
11464                  "sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, "
11465                  "port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
11466              sr_cnt, blk_cnt, port_is_idle_0,
11467              port_is_idle_1, pgl_exp_rom2);
11468        return (-1);
11469    }
11470
11471    mb();
11472
11473    /* Close gates #2, #3 and #4 */
11474    bxe_set_234_gates(sc, TRUE);
11475
11476    /* Poll for IGU VQs for 57712 and newer chips */
11477    if (!CHIP_IS_E1x(sc) && bxe_er_poll_igu_vq(sc)) {
11478        return (-1);
11479    }
11480
11481    /* XXX indicate that "process kill" is in progress to MCP */
11482
11483    /* clear "unprepared" bit */
11484    REG_WR(sc, MISC_REG_UNPREPARED, 0);
11485    mb();
11486
11487    /* Make sure all is written to the chip before the reset */
11488    wmb();
11489
11490    /*
11491     * Wait for 1ms to empty GLUE and PCI-E core queues,
11492     * PSWHST, GRC and PSWRD Tetris buffer.
11493     */
11494    DELAY(1000);
11495
11496    /* Prepare to chip reset: */
11497    /* MCP */
11498    if (global) {
11499        bxe_reset_mcp_prep(sc, &val);
11500    }
11501
11502    /* PXP */
11503    bxe_pxp_prep(sc);
11504    mb();
11505
11506    /* reset the chip */
11507    bxe_process_kill_chip_reset(sc, global);
11508    mb();
11509
11510    /* clear errors in PGB */
11511    if (!CHIP_IS_E1(sc))
11512        REG_WR(sc, PGLUE_B_REG_LATCHED_ERRORS_CLR, 0x7f);
11513
11514    /* Recover after reset: */
11515    /* MCP */
11516    if (global && bxe_reset_mcp_comp(sc, val)) {
11517        return (-1);
11518    }
11519
11520    /* XXX add resetting the NO_MCP mode DB here */
11521
11522    /* Open the gates #2, #3 and #4 */
11523    bxe_set_234_gates(sc, FALSE);
11524
11525    /* XXX
11526     * IGU/AEU preparation bring back the AEU/IGU to a reset state
11527     * re-enable attentions
11528     */
11529
11530    return (0);
11531}
11532
11533static int
11534bxe_leader_reset(struct bxe_softc *sc)
11535{
11536    int rc = 0;
11537    uint8_t global = bxe_reset_is_global(sc);
11538    uint32_t load_code;
11539
11540    /*
11541     * If not going to reset MCP, load "fake" driver to reset HW while
11542     * driver is owner of the HW.
11543     */
11544    if (!global && !BXE_NOMCP(sc)) {
11545        load_code = bxe_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
11546                                   DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
11547        if (!load_code) {
11548            BLOGE(sc, "MCP response failure, aborting\n");
11549            rc = -1;
11550            goto exit_leader_reset;
11551        }
11552
11553        if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
11554            (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
11555            BLOGE(sc, "MCP unexpected response, aborting\n");
11556            rc = -1;
11557            goto exit_leader_reset2;
11558        }
11559
11560        load_code = bxe_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
11561        if (!load_code) {
11562            BLOGE(sc, "MCP response failure, aborting\n");
11563            rc = -1;
11564            goto exit_leader_reset2;
11565        }
11566    }
11567
11568    /* try to recover after the failure */
11569    if (bxe_process_kill(sc, global)) {
11570        BLOGE(sc, "Something bad occurred on engine %d!\n", SC_PATH(sc));
11571        rc = -1;
11572        goto exit_leader_reset2;
11573    }
11574
11575    /*
11576     * Clear the RESET_IN_PROGRESS and RESET_GLOBAL bits and update the driver
11577     * state.
11578     */
11579    bxe_set_reset_done(sc);
11580    if (global) {
11581        bxe_clear_reset_global(sc);
11582    }
11583
11584exit_leader_reset2:
11585
11586    /* unload "fake driver" if it was loaded */
11587    if (!global && !BXE_NOMCP(sc)) {
11588        bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
11589        bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
11590    }
11591
11592exit_leader_reset:
11593
11594    sc->is_leader = 0;
11595    bxe_release_leader_lock(sc);
11596
11597    mb();
11598    return (rc);
11599}
11600
11601/*
11602 * prepare INIT transition, parameters configured:
11603 *   - HC configuration
11604 *   - Queue's CDU context
11605 */
11606static void
11607bxe_pf_q_prep_init(struct bxe_softc               *sc,
11608                   struct bxe_fastpath            *fp,
11609                   struct ecore_queue_init_params *init_params)
11610{
11611    uint8_t cos;
11612    int cxt_index, cxt_offset;
11613
11614    bxe_set_bit(ECORE_Q_FLG_HC, &init_params->rx.flags);
11615    bxe_set_bit(ECORE_Q_FLG_HC, &init_params->tx.flags);
11616
11617    bxe_set_bit(ECORE_Q_FLG_HC_EN, &init_params->rx.flags);
11618    bxe_set_bit(ECORE_Q_FLG_HC_EN, &init_params->tx.flags);
11619
11620    /* HC rate */
11621    init_params->rx.hc_rate =
11622        sc->hc_rx_ticks ? (1000000 / sc->hc_rx_ticks) : 0;
11623    init_params->tx.hc_rate =
11624        sc->hc_tx_ticks ? (1000000 / sc->hc_tx_ticks) : 0;
11625
11626    /* FW SB ID */
11627    init_params->rx.fw_sb_id = init_params->tx.fw_sb_id = fp->fw_sb_id;
11628
11629    /* CQ index among the SB indices */
11630    init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
11631    init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
11632
11633    /* set maximum number of COSs supported by this queue */
11634    init_params->max_cos = sc->max_cos;
11635
11636    BLOGD(sc, DBG_LOAD, "fp %d setting queue params max cos to %d\n",
11637          fp->index, init_params->max_cos);
11638
11639    /* set the context pointers queue object */
11640    for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
11641        /* XXX change index/cid here if ever support multiple tx CoS */
11642        /* fp->txdata[cos]->cid */
11643        cxt_index = fp->index / ILT_PAGE_CIDS;
11644        cxt_offset = fp->index - (cxt_index * ILT_PAGE_CIDS);
11645        init_params->cxts[cos] = &sc->context[cxt_index].vcxt[cxt_offset].eth;
11646    }
11647}
11648
11649/* set flags that are common for the Tx-only and not normal connections */
11650static unsigned long
11651bxe_get_common_flags(struct bxe_softc    *sc,
11652                     struct bxe_fastpath *fp,
11653                     uint8_t             zero_stats)
11654{
11655    unsigned long flags = 0;
11656
11657    /* PF driver will always initialize the Queue to an ACTIVE state */
11658    bxe_set_bit(ECORE_Q_FLG_ACTIVE, &flags);
11659
11660    /*
11661     * tx only connections collect statistics (on the same index as the
11662     * parent connection). The statistics are zeroed when the parent
11663     * connection is initialized.
11664     */
11665
11666    bxe_set_bit(ECORE_Q_FLG_STATS, &flags);
11667    if (zero_stats) {
11668        bxe_set_bit(ECORE_Q_FLG_ZERO_STATS, &flags);
11669    }
11670
11671    /*
11672     * tx only connections can support tx-switching, though their
11673     * CoS-ness doesn't survive the loopback
11674     */
11675    if (sc->flags & BXE_TX_SWITCHING) {
11676        bxe_set_bit(ECORE_Q_FLG_TX_SWITCH, &flags);
11677    }
11678
11679    bxe_set_bit(ECORE_Q_FLG_PCSUM_ON_PKT, &flags);
11680
11681    return (flags);
11682}
11683
11684static unsigned long
11685bxe_get_q_flags(struct bxe_softc    *sc,
11686                struct bxe_fastpath *fp,
11687                uint8_t             leading)
11688{
11689    unsigned long flags = 0;
11690
11691    if (IS_MF_SD(sc)) {
11692        bxe_set_bit(ECORE_Q_FLG_OV, &flags);
11693    }
11694
11695    if (if_getcapenable(sc->ifp) & IFCAP_LRO) {
11696        bxe_set_bit(ECORE_Q_FLG_TPA, &flags);
11697        bxe_set_bit(ECORE_Q_FLG_TPA_IPV6, &flags);
11698#if 0
11699        if (fp->mode == TPA_MODE_GRO)
11700            __set_bit(ECORE_Q_FLG_TPA_GRO, &flags);
11701#endif
11702    }
11703
11704    if (leading) {
11705        bxe_set_bit(ECORE_Q_FLG_LEADING_RSS, &flags);
11706        bxe_set_bit(ECORE_Q_FLG_MCAST, &flags);
11707    }
11708
11709    bxe_set_bit(ECORE_Q_FLG_VLAN, &flags);
11710
11711#if 0
11712    /* configure silent vlan removal */
11713    if (IS_MF_AFEX(sc)) {
11714        bxe_set_bit(ECORE_Q_FLG_SILENT_VLAN_REM, &flags);
11715    }
11716#endif
11717
11718    /* merge with common flags */
11719    return (flags | bxe_get_common_flags(sc, fp, TRUE));
11720}
11721
11722static void
11723bxe_pf_q_prep_general(struct bxe_softc                  *sc,
11724                      struct bxe_fastpath               *fp,
11725                      struct ecore_general_setup_params *gen_init,
11726                      uint8_t                           cos)
11727{
11728    gen_init->stat_id = bxe_stats_id(fp);
11729    gen_init->spcl_id = fp->cl_id;
11730    gen_init->mtu = sc->mtu;
11731    gen_init->cos = cos;
11732}
11733
11734static void
11735bxe_pf_rx_q_prep(struct bxe_softc              *sc,
11736                 struct bxe_fastpath           *fp,
11737                 struct rxq_pause_params       *pause,
11738                 struct ecore_rxq_setup_params *rxq_init)
11739{
11740    uint8_t max_sge = 0;
11741    uint16_t sge_sz = 0;
11742    uint16_t tpa_agg_size = 0;
11743
11744    pause->sge_th_lo = SGE_TH_LO(sc);
11745    pause->sge_th_hi = SGE_TH_HI(sc);
11746
11747    /* validate SGE ring has enough to cross high threshold */
11748    if (sc->dropless_fc &&
11749            (pause->sge_th_hi + FW_PREFETCH_CNT) >
11750            (RX_SGE_USABLE_PER_PAGE * RX_SGE_NUM_PAGES)) {
11751        BLOGW(sc, "sge ring threshold limit\n");
11752    }
11753
11754    /* minimum max_aggregation_size is 2*MTU (two full buffers) */
11755    tpa_agg_size = (2 * sc->mtu);
11756    if (tpa_agg_size < sc->max_aggregation_size) {
11757        tpa_agg_size = sc->max_aggregation_size;
11758    }
11759
11760    max_sge = SGE_PAGE_ALIGN(sc->mtu) >> SGE_PAGE_SHIFT;
11761    max_sge = ((max_sge + PAGES_PER_SGE - 1) &
11762                   (~(PAGES_PER_SGE - 1))) >> PAGES_PER_SGE_SHIFT;
11763    sge_sz = (uint16_t)min(SGE_PAGES, 0xffff);
11764
11765    /* pause - not for e1 */
11766    if (!CHIP_IS_E1(sc)) {
11767        pause->bd_th_lo = BD_TH_LO(sc);
11768        pause->bd_th_hi = BD_TH_HI(sc);
11769
11770        pause->rcq_th_lo = RCQ_TH_LO(sc);
11771        pause->rcq_th_hi = RCQ_TH_HI(sc);
11772
11773        /* validate rings have enough entries to cross high thresholds */
11774        if (sc->dropless_fc &&
11775            pause->bd_th_hi + FW_PREFETCH_CNT >
11776            sc->rx_ring_size) {
11777            BLOGW(sc, "rx bd ring threshold limit\n");
11778        }
11779
11780        if (sc->dropless_fc &&
11781            pause->rcq_th_hi + FW_PREFETCH_CNT >
11782            RCQ_NUM_PAGES * RCQ_USABLE_PER_PAGE) {
11783            BLOGW(sc, "rcq ring threshold limit\n");
11784        }
11785
11786        pause->pri_map = 1;
11787    }
11788
11789    /* rxq setup */
11790    rxq_init->dscr_map   = fp->rx_dma.paddr;
11791    rxq_init->sge_map    = fp->rx_sge_dma.paddr;
11792    rxq_init->rcq_map    = fp->rcq_dma.paddr;
11793    rxq_init->rcq_np_map = (fp->rcq_dma.paddr + BCM_PAGE_SIZE);
11794
11795    /*
11796     * This should be a maximum number of data bytes that may be
11797     * placed on the BD (not including paddings).
11798     */
11799    rxq_init->buf_sz = (fp->rx_buf_size -
11800                        IP_HEADER_ALIGNMENT_PADDING);
11801
11802    rxq_init->cl_qzone_id     = fp->cl_qzone_id;
11803    rxq_init->tpa_agg_sz      = tpa_agg_size;
11804    rxq_init->sge_buf_sz      = sge_sz;
11805    rxq_init->max_sges_pkt    = max_sge;
11806    rxq_init->rss_engine_id   = SC_FUNC(sc);
11807    rxq_init->mcast_engine_id = SC_FUNC(sc);
11808
11809    /*
11810     * Maximum number or simultaneous TPA aggregation for this Queue.
11811     * For PF Clients it should be the maximum available number.
11812     * VF driver(s) may want to define it to a smaller value.
11813     */
11814    rxq_init->max_tpa_queues = MAX_AGG_QS(sc);
11815
11816    rxq_init->cache_line_log = BXE_RX_ALIGN_SHIFT;
11817    rxq_init->fw_sb_id = fp->fw_sb_id;
11818
11819    rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
11820
11821    /*
11822     * configure silent vlan removal
11823     * if multi function mode is afex, then mask default vlan
11824     */
11825    if (IS_MF_AFEX(sc)) {
11826        rxq_init->silent_removal_value =
11827            sc->devinfo.mf_info.afex_def_vlan_tag;
11828        rxq_init->silent_removal_mask = EVL_VLID_MASK;
11829    }
11830}
11831
11832static void
11833bxe_pf_tx_q_prep(struct bxe_softc              *sc,
11834                 struct bxe_fastpath           *fp,
11835                 struct ecore_txq_setup_params *txq_init,
11836                 uint8_t                       cos)
11837{
11838    /*
11839     * XXX If multiple CoS is ever supported then each fastpath structure
11840     * will need to maintain tx producer/consumer/dma/etc values *per* CoS.
11841     * fp->txdata[cos]->tx_dma.paddr;
11842     */
11843    txq_init->dscr_map     = fp->tx_dma.paddr;
11844    txq_init->sb_cq_index  = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
11845    txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
11846    txq_init->fw_sb_id     = fp->fw_sb_id;
11847
11848    /*
11849     * set the TSS leading client id for TX classfication to the
11850     * leading RSS client id
11851     */
11852    txq_init->tss_leading_cl_id = BXE_FP(sc, 0, cl_id);
11853}
11854
11855/*
11856 * This function performs 2 steps in a queue state machine:
11857 *   1) RESET->INIT
11858 *   2) INIT->SETUP
11859 */
11860static int
11861bxe_setup_queue(struct bxe_softc    *sc,
11862                struct bxe_fastpath *fp,
11863                uint8_t             leading)
11864{
11865    struct ecore_queue_state_params q_params = { NULL };
11866    struct ecore_queue_setup_params *setup_params =
11867                        &q_params.params.setup;
11868#if 0
11869    struct ecore_queue_setup_tx_only_params *tx_only_params =
11870                        &q_params.params.tx_only;
11871    uint8_t tx_index;
11872#endif
11873    int rc;
11874
11875    BLOGD(sc, DBG_LOAD, "setting up queue %d\n", fp->index);
11876
11877    bxe_ack_sb(sc, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
11878
11879    q_params.q_obj = &BXE_SP_OBJ(sc, fp).q_obj;
11880
11881    /* we want to wait for completion in this context */
11882    bxe_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
11883
11884    /* prepare the INIT parameters */
11885    bxe_pf_q_prep_init(sc, fp, &q_params.params.init);
11886
11887    /* Set the command */
11888    q_params.cmd = ECORE_Q_CMD_INIT;
11889
11890    /* Change the state to INIT */
11891    rc = ecore_queue_state_change(sc, &q_params);
11892    if (rc) {
11893        BLOGE(sc, "Queue(%d) INIT failed\n", fp->index);
11894        return (rc);
11895    }
11896
11897    BLOGD(sc, DBG_LOAD, "init complete\n");
11898
11899    /* now move the Queue to the SETUP state */
11900    memset(setup_params, 0, sizeof(*setup_params));
11901
11902    /* set Queue flags */
11903    setup_params->flags = bxe_get_q_flags(sc, fp, leading);
11904
11905    /* set general SETUP parameters */
11906    bxe_pf_q_prep_general(sc, fp, &setup_params->gen_params,
11907                          FIRST_TX_COS_INDEX);
11908
11909    bxe_pf_rx_q_prep(sc, fp,
11910                     &setup_params->pause_params,
11911                     &setup_params->rxq_params);
11912
11913    bxe_pf_tx_q_prep(sc, fp,
11914                     &setup_params->txq_params,
11915                     FIRST_TX_COS_INDEX);
11916
11917    /* Set the command */
11918    q_params.cmd = ECORE_Q_CMD_SETUP;
11919
11920    /* change the state to SETUP */
11921    rc = ecore_queue_state_change(sc, &q_params);
11922    if (rc) {
11923        BLOGE(sc, "Queue(%d) SETUP failed\n", fp->index);
11924        return (rc);
11925    }
11926
11927#if 0
11928    /* loop through the relevant tx-only indices */
11929    for (tx_index = FIRST_TX_ONLY_COS_INDEX;
11930         tx_index < sc->max_cos;
11931         tx_index++) {
11932        /* prepare and send tx-only ramrod*/
11933        rc = bxe_setup_tx_only(sc, fp, &q_params,
11934                               tx_only_params, tx_index, leading);
11935        if (rc) {
11936            BLOGE(sc, "Queue(%d.%d) TX_ONLY_SETUP failed\n",
11937                  fp->index, tx_index);
11938            return (rc);
11939        }
11940    }
11941#endif
11942
11943    return (rc);
11944}
11945
11946static int
11947bxe_setup_leading(struct bxe_softc *sc)
11948{
11949    return (bxe_setup_queue(sc, &sc->fp[0], TRUE));
11950}
11951
11952static int
11953bxe_config_rss_pf(struct bxe_softc            *sc,
11954                  struct ecore_rss_config_obj *rss_obj,
11955                  uint8_t                     config_hash)
11956{
11957    struct ecore_config_rss_params params = { NULL };
11958    int i;
11959
11960    /*
11961     * Although RSS is meaningless when there is a single HW queue we
11962     * still need it enabled in order to have HW Rx hash generated.
11963     */
11964
11965    params.rss_obj = rss_obj;
11966
11967    bxe_set_bit(RAMROD_COMP_WAIT, &params.ramrod_flags);
11968
11969    bxe_set_bit(ECORE_RSS_MODE_REGULAR, &params.rss_flags);
11970
11971    /* RSS configuration */
11972    bxe_set_bit(ECORE_RSS_IPV4, &params.rss_flags);
11973    bxe_set_bit(ECORE_RSS_IPV4_TCP, &params.rss_flags);
11974    bxe_set_bit(ECORE_RSS_IPV6, &params.rss_flags);
11975    bxe_set_bit(ECORE_RSS_IPV6_TCP, &params.rss_flags);
11976    if (rss_obj->udp_rss_v4) {
11977        bxe_set_bit(ECORE_RSS_IPV4_UDP, &params.rss_flags);
11978    }
11979    if (rss_obj->udp_rss_v6) {
11980        bxe_set_bit(ECORE_RSS_IPV6_UDP, &params.rss_flags);
11981    }
11982
11983    /* Hash bits */
11984    params.rss_result_mask = MULTI_MASK;
11985
11986    memcpy(params.ind_table, rss_obj->ind_table, sizeof(params.ind_table));
11987
11988    if (config_hash) {
11989        /* RSS keys */
11990        for (i = 0; i < sizeof(params.rss_key) / 4; i++) {
11991            params.rss_key[i] = arc4random();
11992        }
11993
11994        bxe_set_bit(ECORE_RSS_SET_SRCH, &params.rss_flags);
11995    }
11996
11997    return (ecore_config_rss(sc, &params));
11998}
11999
12000static int
12001bxe_config_rss_eth(struct bxe_softc *sc,
12002                   uint8_t          config_hash)
12003{
12004    return (bxe_config_rss_pf(sc, &sc->rss_conf_obj, config_hash));
12005}
12006
12007static int
12008bxe_init_rss_pf(struct bxe_softc *sc)
12009{
12010    uint8_t num_eth_queues = BXE_NUM_ETH_QUEUES(sc);
12011    int i;
12012
12013    /*
12014     * Prepare the initial contents of the indirection table if
12015     * RSS is enabled
12016     */
12017    for (i = 0; i < sizeof(sc->rss_conf_obj.ind_table); i++) {
12018        sc->rss_conf_obj.ind_table[i] =
12019            (sc->fp->cl_id + (i % num_eth_queues));
12020    }
12021
12022    if (sc->udp_rss) {
12023        sc->rss_conf_obj.udp_rss_v4 = sc->rss_conf_obj.udp_rss_v6 = 1;
12024    }
12025
12026    /*
12027     * For 57710 and 57711 SEARCHER configuration (rss_keys) is
12028     * per-port, so if explicit configuration is needed, do it only
12029     * for a PMF.
12030     *
12031     * For 57712 and newer it's a per-function configuration.
12032     */
12033    return (bxe_config_rss_eth(sc, sc->port.pmf || !CHIP_IS_E1x(sc)));
12034}
12035
12036static int
12037bxe_set_mac_one(struct bxe_softc          *sc,
12038                uint8_t                   *mac,
12039                struct ecore_vlan_mac_obj *obj,
12040                uint8_t                   set,
12041                int                       mac_type,
12042                unsigned long             *ramrod_flags)
12043{
12044    struct ecore_vlan_mac_ramrod_params ramrod_param;
12045    int rc;
12046
12047    memset(&ramrod_param, 0, sizeof(ramrod_param));
12048
12049    /* fill in general parameters */
12050    ramrod_param.vlan_mac_obj = obj;
12051    ramrod_param.ramrod_flags = *ramrod_flags;
12052
12053    /* fill a user request section if needed */
12054    if (!bxe_test_bit(RAMROD_CONT, ramrod_flags)) {
12055        memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
12056
12057        bxe_set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
12058
12059        /* Set the command: ADD or DEL */
12060        ramrod_param.user_req.cmd = (set) ? ECORE_VLAN_MAC_ADD :
12061                                            ECORE_VLAN_MAC_DEL;
12062    }
12063
12064    rc = ecore_config_vlan_mac(sc, &ramrod_param);
12065
12066    if (rc == ECORE_EXISTS) {
12067        BLOGD(sc, DBG_SP, "Failed to schedule ADD operations (EEXIST)\n");
12068        /* do not treat adding same MAC as error */
12069        rc = 0;
12070    } else if (rc < 0) {
12071        BLOGE(sc, "%s MAC failed (%d)\n", (set ? "Set" : "Delete"), rc);
12072    }
12073
12074    return (rc);
12075}
12076
12077static int
12078bxe_set_eth_mac(struct bxe_softc *sc,
12079                uint8_t          set)
12080{
12081    unsigned long ramrod_flags = 0;
12082
12083    BLOGD(sc, DBG_LOAD, "Adding Ethernet MAC\n");
12084
12085    bxe_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
12086
12087    /* Eth MAC is set on RSS leading client (fp[0]) */
12088    return (bxe_set_mac_one(sc, sc->link_params.mac_addr,
12089                            &sc->sp_objs->mac_obj,
12090                            set, ECORE_ETH_MAC, &ramrod_flags));
12091}
12092
12093#if 0
12094static void
12095bxe_update_max_mf_config(struct bxe_softc *sc,
12096                         uint32_t         value)
12097{
12098    /* load old values */
12099    uint32_t mf_cfg = sc->devinfo.mf_info.mf_config[SC_VN(sc)];
12100
12101    if (value != bxe_extract_max_cfg(sc, mf_cfg)) {
12102        /* leave all but MAX value */
12103        mf_cfg &= ~FUNC_MF_CFG_MAX_BW_MASK;
12104
12105        /* set new MAX value */
12106        mf_cfg |= ((value << FUNC_MF_CFG_MAX_BW_SHIFT) &
12107                   FUNC_MF_CFG_MAX_BW_MASK);
12108
12109        bxe_fw_command(sc, DRV_MSG_CODE_SET_MF_BW, mf_cfg);
12110    }
12111}
12112#endif
12113
12114static int
12115bxe_get_cur_phy_idx(struct bxe_softc *sc)
12116{
12117    uint32_t sel_phy_idx = 0;
12118
12119    if (sc->link_params.num_phys <= 1) {
12120        return (ELINK_INT_PHY);
12121    }
12122
12123    if (sc->link_vars.link_up) {
12124        sel_phy_idx = ELINK_EXT_PHY1;
12125        /* In case link is SERDES, check if the ELINK_EXT_PHY2 is the one */
12126        if ((sc->link_vars.link_status & LINK_STATUS_SERDES_LINK) &&
12127            (sc->link_params.phy[ELINK_EXT_PHY2].supported &
12128             ELINK_SUPPORTED_FIBRE))
12129            sel_phy_idx = ELINK_EXT_PHY2;
12130    } else {
12131        switch (elink_phy_selection(&sc->link_params)) {
12132        case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
12133        case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
12134        case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
12135               sel_phy_idx = ELINK_EXT_PHY1;
12136               break;
12137        case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
12138        case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
12139               sel_phy_idx = ELINK_EXT_PHY2;
12140               break;
12141        }
12142    }
12143
12144    return (sel_phy_idx);
12145}
12146
12147static int
12148bxe_get_link_cfg_idx(struct bxe_softc *sc)
12149{
12150    uint32_t sel_phy_idx = bxe_get_cur_phy_idx(sc);
12151
12152    /*
12153     * The selected activated PHY is always after swapping (in case PHY
12154     * swapping is enabled). So when swapping is enabled, we need to reverse
12155     * the configuration
12156     */
12157
12158    if (sc->link_params.multi_phy_config & PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
12159        if (sel_phy_idx == ELINK_EXT_PHY1)
12160            sel_phy_idx = ELINK_EXT_PHY2;
12161        else if (sel_phy_idx == ELINK_EXT_PHY2)
12162            sel_phy_idx = ELINK_EXT_PHY1;
12163    }
12164
12165    return (ELINK_LINK_CONFIG_IDX(sel_phy_idx));
12166}
12167
12168static void
12169bxe_set_requested_fc(struct bxe_softc *sc)
12170{
12171    /*
12172     * Initialize link parameters structure variables
12173     * It is recommended to turn off RX FC for jumbo frames
12174     * for better performance
12175     */
12176    if (CHIP_IS_E1x(sc) && (sc->mtu > 5000)) {
12177        sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_TX;
12178    } else {
12179        sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_BOTH;
12180    }
12181}
12182
12183static void
12184bxe_calc_fc_adv(struct bxe_softc *sc)
12185{
12186    uint8_t cfg_idx = bxe_get_link_cfg_idx(sc);
12187    switch (sc->link_vars.ieee_fc &
12188            MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
12189    case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
12190    default:
12191        sc->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
12192                                           ADVERTISED_Pause);
12193        break;
12194
12195    case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
12196        sc->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
12197                                          ADVERTISED_Pause);
12198        break;
12199
12200    case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
12201        sc->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
12202        break;
12203    }
12204}
12205
12206static uint16_t
12207bxe_get_mf_speed(struct bxe_softc *sc)
12208{
12209    uint16_t line_speed = sc->link_vars.line_speed;
12210    if (IS_MF(sc)) {
12211        uint16_t maxCfg =
12212            bxe_extract_max_cfg(sc, sc->devinfo.mf_info.mf_config[SC_VN(sc)]);
12213
12214        /* calculate the current MAX line speed limit for the MF devices */
12215        if (IS_MF_SI(sc)) {
12216            line_speed = (line_speed * maxCfg) / 100;
12217        } else { /* SD mode */
12218            uint16_t vn_max_rate = maxCfg * 100;
12219
12220            if (vn_max_rate < line_speed) {
12221                line_speed = vn_max_rate;
12222            }
12223        }
12224    }
12225
12226    return (line_speed);
12227}
12228
12229static void
12230bxe_fill_report_data(struct bxe_softc            *sc,
12231                     struct bxe_link_report_data *data)
12232{
12233    uint16_t line_speed = bxe_get_mf_speed(sc);
12234
12235    memset(data, 0, sizeof(*data));
12236
12237    /* fill the report data with the effective line speed */
12238    data->line_speed = line_speed;
12239
12240    /* Link is down */
12241    if (!sc->link_vars.link_up || (sc->flags & BXE_MF_FUNC_DIS)) {
12242        bxe_set_bit(BXE_LINK_REPORT_LINK_DOWN, &data->link_report_flags);
12243    }
12244
12245    /* Full DUPLEX */
12246    if (sc->link_vars.duplex == DUPLEX_FULL) {
12247        bxe_set_bit(BXE_LINK_REPORT_FULL_DUPLEX, &data->link_report_flags);
12248    }
12249
12250    /* Rx Flow Control is ON */
12251    if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_RX) {
12252        bxe_set_bit(BXE_LINK_REPORT_RX_FC_ON, &data->link_report_flags);
12253    }
12254
12255    /* Tx Flow Control is ON */
12256    if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
12257        bxe_set_bit(BXE_LINK_REPORT_TX_FC_ON, &data->link_report_flags);
12258    }
12259}
12260
12261/* report link status to OS, should be called under phy_lock */
12262static void
12263bxe_link_report_locked(struct bxe_softc *sc)
12264{
12265    struct bxe_link_report_data cur_data;
12266
12267    /* reread mf_cfg */
12268    if (IS_PF(sc) && !CHIP_IS_E1(sc)) {
12269        bxe_read_mf_cfg(sc);
12270    }
12271
12272    /* Read the current link report info */
12273    bxe_fill_report_data(sc, &cur_data);
12274
12275    /* Don't report link down or exactly the same link status twice */
12276    if (!memcmp(&cur_data, &sc->last_reported_link, sizeof(cur_data)) ||
12277        (bxe_test_bit(BXE_LINK_REPORT_LINK_DOWN,
12278                      &sc->last_reported_link.link_report_flags) &&
12279         bxe_test_bit(BXE_LINK_REPORT_LINK_DOWN,
12280                      &cur_data.link_report_flags))) {
12281        return;
12282    }
12283
12284    sc->link_cnt++;
12285
12286    /* report new link params and remember the state for the next time */
12287    memcpy(&sc->last_reported_link, &cur_data, sizeof(cur_data));
12288
12289    if (bxe_test_bit(BXE_LINK_REPORT_LINK_DOWN,
12290                     &cur_data.link_report_flags)) {
12291        if_link_state_change(sc->ifp, LINK_STATE_DOWN);
12292        BLOGI(sc, "NIC Link is Down\n");
12293    } else {
12294        const char *duplex;
12295        const char *flow;
12296
12297        if (bxe_test_and_clear_bit(BXE_LINK_REPORT_FULL_DUPLEX,
12298                                   &cur_data.link_report_flags)) {
12299            duplex = "full";
12300        } else {
12301            duplex = "half";
12302        }
12303
12304        /*
12305         * Handle the FC at the end so that only these flags would be
12306         * possibly set. This way we may easily check if there is no FC
12307         * enabled.
12308         */
12309        if (cur_data.link_report_flags) {
12310            if (bxe_test_bit(BXE_LINK_REPORT_RX_FC_ON,
12311                             &cur_data.link_report_flags) &&
12312                bxe_test_bit(BXE_LINK_REPORT_TX_FC_ON,
12313                             &cur_data.link_report_flags)) {
12314                flow = "ON - receive & transmit";
12315            } else if (bxe_test_bit(BXE_LINK_REPORT_RX_FC_ON,
12316                                    &cur_data.link_report_flags) &&
12317                       !bxe_test_bit(BXE_LINK_REPORT_TX_FC_ON,
12318                                     &cur_data.link_report_flags)) {
12319                flow = "ON - receive";
12320            } else if (!bxe_test_bit(BXE_LINK_REPORT_RX_FC_ON,
12321                                     &cur_data.link_report_flags) &&
12322                       bxe_test_bit(BXE_LINK_REPORT_TX_FC_ON,
12323                                    &cur_data.link_report_flags)) {
12324                flow = "ON - transmit";
12325            } else {
12326                flow = "none"; /* possible? */
12327            }
12328        } else {
12329            flow = "none";
12330        }
12331
12332        if_link_state_change(sc->ifp, LINK_STATE_UP);
12333        BLOGI(sc, "NIC Link is Up, %d Mbps %s duplex, Flow control: %s\n",
12334              cur_data.line_speed, duplex, flow);
12335    }
12336}
12337
12338static void
12339bxe_link_report(struct bxe_softc *sc)
12340{
12341    bxe_acquire_phy_lock(sc);
12342    bxe_link_report_locked(sc);
12343    bxe_release_phy_lock(sc);
12344}
12345
12346static void
12347bxe_link_status_update(struct bxe_softc *sc)
12348{
12349    if (sc->state != BXE_STATE_OPEN) {
12350        return;
12351    }
12352
12353#if 0
12354    /* read updated dcb configuration */
12355    if (IS_PF(sc))
12356        bxe_dcbx_pmf_update(sc);
12357#endif
12358
12359    if (IS_PF(sc) && !CHIP_REV_IS_SLOW(sc)) {
12360        elink_link_status_update(&sc->link_params, &sc->link_vars);
12361    } else {
12362        sc->port.supported[0] |= (ELINK_SUPPORTED_10baseT_Half |
12363                                  ELINK_SUPPORTED_10baseT_Full |
12364                                  ELINK_SUPPORTED_100baseT_Half |
12365                                  ELINK_SUPPORTED_100baseT_Full |
12366                                  ELINK_SUPPORTED_1000baseT_Full |
12367                                  ELINK_SUPPORTED_2500baseX_Full |
12368                                  ELINK_SUPPORTED_10000baseT_Full |
12369                                  ELINK_SUPPORTED_TP |
12370                                  ELINK_SUPPORTED_FIBRE |
12371                                  ELINK_SUPPORTED_Autoneg |
12372                                  ELINK_SUPPORTED_Pause |
12373                                  ELINK_SUPPORTED_Asym_Pause);
12374        sc->port.advertising[0] = sc->port.supported[0];
12375
12376        sc->link_params.sc                = sc;
12377        sc->link_params.port              = SC_PORT(sc);
12378        sc->link_params.req_duplex[0]     = DUPLEX_FULL;
12379        sc->link_params.req_flow_ctrl[0]  = ELINK_FLOW_CTRL_NONE;
12380        sc->link_params.req_line_speed[0] = SPEED_10000;
12381        sc->link_params.speed_cap_mask[0] = 0x7f0000;
12382        sc->link_params.switch_cfg        = ELINK_SWITCH_CFG_10G;
12383
12384        if (CHIP_REV_IS_FPGA(sc)) {
12385            sc->link_vars.mac_type    = ELINK_MAC_TYPE_EMAC;
12386            sc->link_vars.line_speed  = ELINK_SPEED_1000;
12387            sc->link_vars.link_status = (LINK_STATUS_LINK_UP |
12388                                         LINK_STATUS_SPEED_AND_DUPLEX_1000TFD);
12389        } else {
12390            sc->link_vars.mac_type    = ELINK_MAC_TYPE_BMAC;
12391            sc->link_vars.line_speed  = ELINK_SPEED_10000;
12392            sc->link_vars.link_status = (LINK_STATUS_LINK_UP |
12393                                         LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
12394        }
12395
12396        sc->link_vars.link_up = 1;
12397
12398        sc->link_vars.duplex    = DUPLEX_FULL;
12399        sc->link_vars.flow_ctrl = ELINK_FLOW_CTRL_NONE;
12400
12401        if (IS_PF(sc)) {
12402            REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + sc->link_params.port*4, 0);
12403            bxe_stats_handle(sc, STATS_EVENT_LINK_UP);
12404            bxe_link_report(sc);
12405        }
12406    }
12407
12408    if (IS_PF(sc)) {
12409        if (sc->link_vars.link_up) {
12410            bxe_stats_handle(sc, STATS_EVENT_LINK_UP);
12411        } else {
12412            bxe_stats_handle(sc, STATS_EVENT_STOP);
12413        }
12414        bxe_link_report(sc);
12415    } else {
12416        bxe_link_report(sc);
12417        bxe_stats_handle(sc, STATS_EVENT_LINK_UP);
12418    }
12419}
12420
12421static int
12422bxe_initial_phy_init(struct bxe_softc *sc,
12423                     int              load_mode)
12424{
12425    int rc, cfg_idx = bxe_get_link_cfg_idx(sc);
12426    uint16_t req_line_speed = sc->link_params.req_line_speed[cfg_idx];
12427    struct elink_params *lp = &sc->link_params;
12428
12429    bxe_set_requested_fc(sc);
12430
12431    if (CHIP_REV_IS_SLOW(sc)) {
12432        uint32_t bond = CHIP_BOND_ID(sc);
12433        uint32_t feat = 0;
12434
12435        if (CHIP_IS_E2(sc) && CHIP_IS_MODE_4_PORT(sc)) {
12436            feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC;
12437        } else if (bond & 0x4) {
12438            if (CHIP_IS_E3(sc)) {
12439                feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC;
12440            } else {
12441                feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC;
12442            }
12443        } else if (bond & 0x8) {
12444            if (CHIP_IS_E3(sc)) {
12445                feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_UMAC;
12446            } else {
12447                feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC;
12448            }
12449        }
12450
12451        /* disable EMAC for E3 and above */
12452        if (bond & 0x2) {
12453            feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC;
12454        }
12455
12456        sc->link_params.feature_config_flags |= feat;
12457    }
12458
12459    bxe_acquire_phy_lock(sc);
12460
12461    if (load_mode == LOAD_DIAG) {
12462        lp->loopback_mode = ELINK_LOOPBACK_XGXS;
12463        /* Prefer doing PHY loopback at 10G speed, if possible */
12464        if (lp->req_line_speed[cfg_idx] < ELINK_SPEED_10000) {
12465            if (lp->speed_cap_mask[cfg_idx] &
12466                PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) {
12467                lp->req_line_speed[cfg_idx] = ELINK_SPEED_10000;
12468            } else {
12469                lp->req_line_speed[cfg_idx] = ELINK_SPEED_1000;
12470            }
12471        }
12472    }
12473
12474    if (load_mode == LOAD_LOOPBACK_EXT) {
12475        lp->loopback_mode = ELINK_LOOPBACK_EXT;
12476    }
12477
12478    rc = elink_phy_init(&sc->link_params, &sc->link_vars);
12479
12480    bxe_release_phy_lock(sc);
12481
12482    bxe_calc_fc_adv(sc);
12483
12484    if (sc->link_vars.link_up) {
12485        bxe_stats_handle(sc, STATS_EVENT_LINK_UP);
12486        bxe_link_report(sc);
12487    }
12488
12489    if (!CHIP_REV_IS_SLOW(sc)) {
12490        bxe_periodic_start(sc);
12491    }
12492
12493    sc->link_params.req_line_speed[cfg_idx] = req_line_speed;
12494    return (rc);
12495}
12496
12497/* must be called under IF_ADDR_LOCK */
12498
12499static int
12500bxe_set_mc_list(struct bxe_softc *sc)
12501{
12502    struct ecore_mcast_ramrod_params rparam = { NULL };
12503    int rc = 0;
12504    int mc_count = 0;
12505    int mcnt, i;
12506    struct ecore_mcast_list_elem *mc_mac, *mc_mac_start;
12507    unsigned char *mta;
12508    if_t ifp = sc->ifp;
12509
12510    mc_count = if_multiaddr_count(ifp, -1);/* XXX they don't have a limit */
12511    if (!mc_count)
12512        return (0);
12513
12514    mta = malloc(sizeof(unsigned char) * ETHER_ADDR_LEN *
12515            mc_count, M_DEVBUF, M_NOWAIT);
12516
12517    if(mta == NULL) {
12518        BLOGE(sc, "Failed to allocate temp mcast list\n");
12519        return (-1);
12520    }
12521    bzero(mta, (sizeof(unsigned char) * ETHER_ADDR_LEN * mc_count));
12522
12523    mc_mac = malloc(sizeof(*mc_mac) * mc_count, M_DEVBUF, (M_NOWAIT | M_ZERO));
12524    mc_mac_start = mc_mac;
12525
12526    if (!mc_mac) {
12527        free(mta, M_DEVBUF);
12528        BLOGE(sc, "Failed to allocate temp mcast list\n");
12529        return (-1);
12530    }
12531    bzero(mc_mac, (sizeof(*mc_mac) * mc_count));
12532
12533    /* mta and mcnt not expected to be  different */
12534    if_multiaddr_array(ifp, mta, &mcnt, mc_count);
12535
12536
12537    rparam.mcast_obj = &sc->mcast_obj;
12538    ECORE_LIST_INIT(&rparam.mcast_list);
12539
12540    for(i=0; i< mcnt; i++) {
12541
12542        mc_mac->mac = (uint8_t *)(mta + (i * ETHER_ADDR_LEN));
12543        ECORE_LIST_PUSH_TAIL(&mc_mac->link, &rparam.mcast_list);
12544
12545        BLOGD(sc, DBG_LOAD,
12546              "Setting MCAST %02X:%02X:%02X:%02X:%02X:%02X\n",
12547              mc_mac->mac[0], mc_mac->mac[1], mc_mac->mac[2],
12548              mc_mac->mac[3], mc_mac->mac[4], mc_mac->mac[5]);
12549
12550        mc_mac++;
12551    }
12552    rparam.mcast_list_len = mc_count;
12553
12554    BXE_MCAST_LOCK(sc);
12555
12556    /* first, clear all configured multicast MACs */
12557    rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
12558    if (rc < 0) {
12559        BLOGE(sc, "Failed to clear multicast configuration: %d\n", rc);
12560        BXE_MCAST_UNLOCK(sc);
12561    	free(mc_mac_start, M_DEVBUF);
12562        free(mta, M_DEVBUF);
12563        return (rc);
12564    }
12565
12566    /* Now add the new MACs */
12567    rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_ADD);
12568    if (rc < 0) {
12569        BLOGE(sc, "Failed to set new mcast config (%d)\n", rc);
12570    }
12571
12572    BXE_MCAST_UNLOCK(sc);
12573
12574    free(mc_mac_start, M_DEVBUF);
12575    free(mta, M_DEVBUF);
12576
12577    return (rc);
12578}
12579
12580static int
12581bxe_set_uc_list(struct bxe_softc *sc)
12582{
12583    if_t ifp = sc->ifp;
12584    struct ecore_vlan_mac_obj *mac_obj = &sc->sp_objs->mac_obj;
12585    struct ifaddr *ifa;
12586    unsigned long ramrod_flags = 0;
12587    int rc;
12588
12589#if __FreeBSD_version < 800000
12590    IF_ADDR_LOCK(ifp);
12591#else
12592    if_addr_rlock(ifp);
12593#endif
12594
12595    /* first schedule a cleanup up of old configuration */
12596    rc = bxe_del_all_macs(sc, mac_obj, ECORE_UC_LIST_MAC, FALSE);
12597    if (rc < 0) {
12598        BLOGE(sc, "Failed to schedule delete of all ETH MACs (%d)\n", rc);
12599#if __FreeBSD_version < 800000
12600        IF_ADDR_UNLOCK(ifp);
12601#else
12602        if_addr_runlock(ifp);
12603#endif
12604        return (rc);
12605    }
12606
12607    ifa = if_getifaddr(ifp); /* XXX Is this structure */
12608    while (ifa) {
12609        if (ifa->ifa_addr->sa_family != AF_LINK) {
12610            ifa = TAILQ_NEXT(ifa, ifa_link);
12611            continue;
12612        }
12613
12614        rc = bxe_set_mac_one(sc, (uint8_t *)LLADDR((struct sockaddr_dl *)ifa->ifa_addr),
12615                             mac_obj, TRUE, ECORE_UC_LIST_MAC, &ramrod_flags);
12616        if (rc == -EEXIST) {
12617            BLOGD(sc, DBG_SP, "Failed to schedule ADD operations (EEXIST)\n");
12618            /* do not treat adding same MAC as an error */
12619            rc = 0;
12620        } else if (rc < 0) {
12621            BLOGE(sc, "Failed to schedule ADD operations (%d)\n", rc);
12622#if __FreeBSD_version < 800000
12623            IF_ADDR_UNLOCK(ifp);
12624#else
12625            if_addr_runlock(ifp);
12626#endif
12627            return (rc);
12628        }
12629
12630        ifa = TAILQ_NEXT(ifa, ifa_link);
12631    }
12632
12633#if __FreeBSD_version < 800000
12634    IF_ADDR_UNLOCK(ifp);
12635#else
12636    if_addr_runlock(ifp);
12637#endif
12638
12639    /* Execute the pending commands */
12640    bit_set(&ramrod_flags, RAMROD_CONT);
12641    return (bxe_set_mac_one(sc, NULL, mac_obj, FALSE /* don't care */,
12642                            ECORE_UC_LIST_MAC, &ramrod_flags));
12643}
12644
12645static void
12646bxe_set_rx_mode(struct bxe_softc *sc)
12647{
12648    if_t ifp = sc->ifp;
12649    uint32_t rx_mode = BXE_RX_MODE_NORMAL;
12650
12651    if (sc->state != BXE_STATE_OPEN) {
12652        BLOGD(sc, DBG_SP, "state is %x, returning\n", sc->state);
12653        return;
12654    }
12655
12656    BLOGD(sc, DBG_SP, "if_flags(ifp)=0x%x\n", if_getflags(sc->ifp));
12657
12658    if (if_getflags(ifp) & IFF_PROMISC) {
12659        rx_mode = BXE_RX_MODE_PROMISC;
12660    } else if ((if_getflags(ifp) & IFF_ALLMULTI) ||
12661               ((if_getamcount(ifp) > BXE_MAX_MULTICAST) &&
12662                CHIP_IS_E1(sc))) {
12663        rx_mode = BXE_RX_MODE_ALLMULTI;
12664    } else {
12665        if (IS_PF(sc)) {
12666            /* some multicasts */
12667            if (bxe_set_mc_list(sc) < 0) {
12668                rx_mode = BXE_RX_MODE_ALLMULTI;
12669            }
12670            if (bxe_set_uc_list(sc) < 0) {
12671                rx_mode = BXE_RX_MODE_PROMISC;
12672            }
12673        }
12674#if 0
12675        else {
12676            /*
12677             * Configuring mcast to a VF involves sleeping (when we
12678             * wait for the PF's response). Since this function is
12679             * called from a non sleepable context we must schedule
12680             * a work item for this purpose
12681             */
12682            bxe_set_bit(BXE_SP_RTNL_VFPF_MCAST, &sc->sp_rtnl_state);
12683            schedule_delayed_work(&sc->sp_rtnl_task, 0);
12684        }
12685#endif
12686    }
12687
12688    sc->rx_mode = rx_mode;
12689
12690    /* schedule the rx_mode command */
12691    if (bxe_test_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state)) {
12692        BLOGD(sc, DBG_LOAD, "Scheduled setting rx_mode with ECORE...\n");
12693        bxe_set_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state);
12694        return;
12695    }
12696
12697    if (IS_PF(sc)) {
12698        bxe_set_storm_rx_mode(sc);
12699    }
12700#if 0
12701    else {
12702        /*
12703         * Configuring mcast to a VF involves sleeping (when we
12704         * wait for the PF's response). Since this function is
12705         * called from a non sleepable context we must schedule
12706         * a work item for this purpose
12707         */
12708        bxe_set_bit(BXE_SP_RTNL_VFPF_STORM_RX_MODE, &sc->sp_rtnl_state);
12709        schedule_delayed_work(&sc->sp_rtnl_task, 0);
12710    }
12711#endif
12712
12713}
12714
12715
12716/* update flags in shmem */
12717static void
12718bxe_update_drv_flags(struct bxe_softc *sc,
12719                     uint32_t         flags,
12720                     uint32_t         set)
12721{
12722    uint32_t drv_flags;
12723
12724    if (SHMEM2_HAS(sc, drv_flags)) {
12725        bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);
12726        drv_flags = SHMEM2_RD(sc, drv_flags);
12727
12728        if (set) {
12729            SET_FLAGS(drv_flags, flags);
12730        } else {
12731            RESET_FLAGS(drv_flags, flags);
12732        }
12733
12734        SHMEM2_WR(sc, drv_flags, drv_flags);
12735        BLOGD(sc, DBG_LOAD, "drv_flags 0x%08x\n", drv_flags);
12736
12737        bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);
12738    }
12739}
12740
12741/* periodic timer callout routine, only runs when the interface is up */
12742
12743static void
12744bxe_periodic_callout_func(void *xsc)
12745{
12746    struct bxe_softc *sc = (struct bxe_softc *)xsc;
12747    int i;
12748
12749    if (!BXE_CORE_TRYLOCK(sc)) {
12750        /* just bail and try again next time */
12751
12752        if ((sc->state == BXE_STATE_OPEN) &&
12753            (atomic_load_acq_long(&sc->periodic_flags) == PERIODIC_GO)) {
12754            /* schedule the next periodic callout */
12755            callout_reset(&sc->periodic_callout, hz,
12756                          bxe_periodic_callout_func, sc);
12757        }
12758
12759        return;
12760    }
12761
12762    if ((sc->state != BXE_STATE_OPEN) ||
12763        (atomic_load_acq_long(&sc->periodic_flags) == PERIODIC_STOP)) {
12764        BLOGW(sc, "periodic callout exit (state=0x%x)\n", sc->state);
12765        BXE_CORE_UNLOCK(sc);
12766        return;
12767    }
12768
12769    /* Check for TX timeouts on any fastpath. */
12770    FOR_EACH_QUEUE(sc, i) {
12771        if (bxe_watchdog(sc, &sc->fp[i]) != 0) {
12772            /* Ruh-Roh, chip was reset! */
12773            break;
12774        }
12775    }
12776
12777    if (!CHIP_REV_IS_SLOW(sc)) {
12778        /*
12779         * This barrier is needed to ensure the ordering between the writing
12780         * to the sc->port.pmf in the bxe_nic_load() or bxe_pmf_update() and
12781         * the reading here.
12782         */
12783        mb();
12784        if (sc->port.pmf) {
12785	    bxe_acquire_phy_lock(sc);
12786            elink_period_func(&sc->link_params, &sc->link_vars);
12787	    bxe_release_phy_lock(sc);
12788        }
12789    }
12790
12791    if (IS_PF(sc) && !(sc->flags & BXE_NO_PULSE)) {
12792        int mb_idx = SC_FW_MB_IDX(sc);
12793        uint32_t drv_pulse;
12794        uint32_t mcp_pulse;
12795
12796        ++sc->fw_drv_pulse_wr_seq;
12797        sc->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
12798
12799        drv_pulse = sc->fw_drv_pulse_wr_seq;
12800        bxe_drv_pulse(sc);
12801
12802        mcp_pulse = (SHMEM_RD(sc, func_mb[mb_idx].mcp_pulse_mb) &
12803                     MCP_PULSE_SEQ_MASK);
12804
12805        /*
12806         * The delta between driver pulse and mcp response should
12807         * be 1 (before mcp response) or 0 (after mcp response).
12808         */
12809        if ((drv_pulse != mcp_pulse) &&
12810            (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
12811            /* someone lost a heartbeat... */
12812            BLOGE(sc, "drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
12813                  drv_pulse, mcp_pulse);
12814        }
12815    }
12816
12817    /* state is BXE_STATE_OPEN */
12818    bxe_stats_handle(sc, STATS_EVENT_UPDATE);
12819
12820#if 0
12821    /* sample VF bulletin board for new posts from PF */
12822    if (IS_VF(sc)) {
12823        bxe_sample_bulletin(sc);
12824    }
12825#endif
12826
12827    BXE_CORE_UNLOCK(sc);
12828
12829    if ((sc->state == BXE_STATE_OPEN) &&
12830        (atomic_load_acq_long(&sc->periodic_flags) == PERIODIC_GO)) {
12831        /* schedule the next periodic callout */
12832        callout_reset(&sc->periodic_callout, hz,
12833                      bxe_periodic_callout_func, sc);
12834    }
12835}
12836
12837static void
12838bxe_periodic_start(struct bxe_softc *sc)
12839{
12840    atomic_store_rel_long(&sc->periodic_flags, PERIODIC_GO);
12841    callout_reset(&sc->periodic_callout, hz, bxe_periodic_callout_func, sc);
12842}
12843
12844static void
12845bxe_periodic_stop(struct bxe_softc *sc)
12846{
12847    atomic_store_rel_long(&sc->periodic_flags, PERIODIC_STOP);
12848    callout_drain(&sc->periodic_callout);
12849}
12850
12851/* start the controller */
12852static __noinline int
12853bxe_nic_load(struct bxe_softc *sc,
12854             int              load_mode)
12855{
12856    uint32_t val;
12857    int load_code = 0;
12858    int i, rc = 0;
12859
12860    BXE_CORE_LOCK_ASSERT(sc);
12861
12862    BLOGD(sc, DBG_LOAD, "Starting NIC load...\n");
12863
12864    sc->state = BXE_STATE_OPENING_WAITING_LOAD;
12865
12866    if (IS_PF(sc)) {
12867        /* must be called before memory allocation and HW init */
12868        bxe_ilt_set_info(sc);
12869    }
12870
12871    sc->last_reported_link_state = LINK_STATE_UNKNOWN;
12872
12873    bxe_set_fp_rx_buf_size(sc);
12874
12875    if (bxe_alloc_fp_buffers(sc) != 0) {
12876        BLOGE(sc, "Failed to allocate fastpath memory\n");
12877        sc->state = BXE_STATE_CLOSED;
12878        rc = ENOMEM;
12879        goto bxe_nic_load_error0;
12880    }
12881
12882    if (bxe_alloc_mem(sc) != 0) {
12883        sc->state = BXE_STATE_CLOSED;
12884        rc = ENOMEM;
12885        goto bxe_nic_load_error0;
12886    }
12887
12888    if (bxe_alloc_fw_stats_mem(sc) != 0) {
12889        sc->state = BXE_STATE_CLOSED;
12890        rc = ENOMEM;
12891        goto bxe_nic_load_error0;
12892    }
12893
12894    if (IS_PF(sc)) {
12895        /* set pf load just before approaching the MCP */
12896        bxe_set_pf_load(sc);
12897
12898        /* if MCP exists send load request and analyze response */
12899        if (!BXE_NOMCP(sc)) {
12900            /* attempt to load pf */
12901            if (bxe_nic_load_request(sc, &load_code) != 0) {
12902                sc->state = BXE_STATE_CLOSED;
12903                rc = ENXIO;
12904                goto bxe_nic_load_error1;
12905            }
12906
12907            /* what did the MCP say? */
12908            if (bxe_nic_load_analyze_req(sc, load_code) != 0) {
12909                bxe_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
12910                sc->state = BXE_STATE_CLOSED;
12911                rc = ENXIO;
12912                goto bxe_nic_load_error2;
12913            }
12914        } else {
12915            BLOGI(sc, "Device has no MCP!\n");
12916            load_code = bxe_nic_load_no_mcp(sc);
12917        }
12918
12919        /* mark PMF if applicable */
12920        bxe_nic_load_pmf(sc, load_code);
12921
12922        /* Init Function state controlling object */
12923        bxe_init_func_obj(sc);
12924
12925        /* Initialize HW */
12926        if (bxe_init_hw(sc, load_code) != 0) {
12927            BLOGE(sc, "HW init failed\n");
12928            bxe_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
12929            sc->state = BXE_STATE_CLOSED;
12930            rc = ENXIO;
12931            goto bxe_nic_load_error2;
12932        }
12933    }
12934
12935    /* set ALWAYS_ALIVE bit in shmem */
12936    sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
12937    bxe_drv_pulse(sc);
12938    sc->flags |= BXE_NO_PULSE;
12939
12940    /* attach interrupts */
12941    if (bxe_interrupt_attach(sc) != 0) {
12942        sc->state = BXE_STATE_CLOSED;
12943        rc = ENXIO;
12944        goto bxe_nic_load_error2;
12945    }
12946
12947    bxe_nic_init(sc, load_code);
12948
12949    /* Init per-function objects */
12950    if (IS_PF(sc)) {
12951        bxe_init_objs(sc);
12952        // XXX bxe_iov_nic_init(sc);
12953
12954        /* set AFEX default VLAN tag to an invalid value */
12955        sc->devinfo.mf_info.afex_def_vlan_tag = -1;
12956        // XXX bxe_nic_load_afex_dcc(sc, load_code);
12957
12958        sc->state = BXE_STATE_OPENING_WAITING_PORT;
12959        rc = bxe_func_start(sc);
12960        if (rc) {
12961            BLOGE(sc, "Function start failed!\n");
12962            bxe_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
12963            sc->state = BXE_STATE_ERROR;
12964            goto bxe_nic_load_error3;
12965        }
12966
12967        /* send LOAD_DONE command to MCP */
12968        if (!BXE_NOMCP(sc)) {
12969            load_code = bxe_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
12970            if (!load_code) {
12971                BLOGE(sc, "MCP response failure, aborting\n");
12972                sc->state = BXE_STATE_ERROR;
12973                rc = ENXIO;
12974                goto bxe_nic_load_error3;
12975            }
12976        }
12977
12978        rc = bxe_setup_leading(sc);
12979        if (rc) {
12980            BLOGE(sc, "Setup leading failed!\n");
12981            sc->state = BXE_STATE_ERROR;
12982            goto bxe_nic_load_error3;
12983        }
12984
12985        FOR_EACH_NONDEFAULT_ETH_QUEUE(sc, i) {
12986            rc = bxe_setup_queue(sc, &sc->fp[i], FALSE);
12987            if (rc) {
12988                BLOGE(sc, "Queue(%d) setup failed\n", i);
12989                sc->state = BXE_STATE_ERROR;
12990                goto bxe_nic_load_error3;
12991            }
12992        }
12993
12994        rc = bxe_init_rss_pf(sc);
12995        if (rc) {
12996            BLOGE(sc, "PF RSS init failed\n");
12997            sc->state = BXE_STATE_ERROR;
12998            goto bxe_nic_load_error3;
12999        }
13000    }
13001    /* XXX VF */
13002#if 0
13003    else { /* VF */
13004        FOR_EACH_ETH_QUEUE(sc, i) {
13005            rc = bxe_vfpf_setup_q(sc, i);
13006            if (rc) {
13007                BLOGE(sc, "Queue(%d) setup failed\n", i);
13008                sc->state = BXE_STATE_ERROR;
13009                goto bxe_nic_load_error3;
13010            }
13011        }
13012    }
13013#endif
13014
13015    /* now when Clients are configured we are ready to work */
13016    sc->state = BXE_STATE_OPEN;
13017
13018    /* Configure a ucast MAC */
13019    if (IS_PF(sc)) {
13020        rc = bxe_set_eth_mac(sc, TRUE);
13021    }
13022#if 0
13023    else { /* IS_VF(sc) */
13024        rc = bxe_vfpf_set_mac(sc);
13025    }
13026#endif
13027    if (rc) {
13028        BLOGE(sc, "Setting Ethernet MAC failed\n");
13029        sc->state = BXE_STATE_ERROR;
13030        goto bxe_nic_load_error3;
13031    }
13032
13033#if 0
13034    if (IS_PF(sc) && sc->pending_max) {
13035        /* for AFEX */
13036        bxe_update_max_mf_config(sc, sc->pending_max);
13037        sc->pending_max = 0;
13038    }
13039#endif
13040
13041    if (sc->port.pmf) {
13042        rc = bxe_initial_phy_init(sc, /* XXX load_mode */LOAD_OPEN);
13043        if (rc) {
13044            sc->state = BXE_STATE_ERROR;
13045            goto bxe_nic_load_error3;
13046        }
13047    }
13048
13049    sc->link_params.feature_config_flags &=
13050        ~ELINK_FEATURE_CONFIG_BOOT_FROM_SAN;
13051
13052    /* start fast path */
13053
13054    /* Initialize Rx filter */
13055    bxe_set_rx_mode(sc);
13056
13057    /* start the Tx */
13058    switch (/* XXX load_mode */LOAD_OPEN) {
13059    case LOAD_NORMAL:
13060    case LOAD_OPEN:
13061        break;
13062
13063    case LOAD_DIAG:
13064    case LOAD_LOOPBACK_EXT:
13065        sc->state = BXE_STATE_DIAG;
13066        break;
13067
13068    default:
13069        break;
13070    }
13071
13072    if (sc->port.pmf) {
13073        bxe_update_drv_flags(sc, 1 << DRV_FLAGS_PORT_MASK, 0);
13074    } else {
13075        bxe_link_status_update(sc);
13076    }
13077
13078    /* start the periodic timer callout */
13079    bxe_periodic_start(sc);
13080
13081    if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
13082        /* mark driver is loaded in shmem2 */
13083        val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
13084        SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
13085                  (val |
13086                   DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED |
13087                   DRV_FLAGS_CAPABILITIES_LOADED_L2));
13088    }
13089
13090    /* wait for all pending SP commands to complete */
13091    if (IS_PF(sc) && !bxe_wait_sp_comp(sc, ~0x0UL)) {
13092        BLOGE(sc, "Timeout waiting for all SPs to complete!\n");
13093        bxe_periodic_stop(sc);
13094        bxe_nic_unload(sc, UNLOAD_CLOSE, FALSE);
13095        return (ENXIO);
13096    }
13097
13098#if 0
13099    /* If PMF - send ADMIN DCBX msg to MFW to initiate DCBX FSM */
13100    if (sc->port.pmf && (sc->state != BXE_STATE_DIAG)) {
13101        bxe_dcbx_init(sc, FALSE);
13102    }
13103#endif
13104
13105    /* Tell the stack the driver is running! */
13106    if_setdrvflags(sc->ifp, IFF_DRV_RUNNING);
13107
13108    BLOGD(sc, DBG_LOAD, "NIC successfully loaded\n");
13109
13110    return (0);
13111
13112bxe_nic_load_error3:
13113
13114    if (IS_PF(sc)) {
13115        bxe_int_disable_sync(sc, 1);
13116
13117        /* clean out queued objects */
13118        bxe_squeeze_objects(sc);
13119    }
13120
13121    bxe_interrupt_detach(sc);
13122
13123bxe_nic_load_error2:
13124
13125    if (IS_PF(sc) && !BXE_NOMCP(sc)) {
13126        bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
13127        bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
13128    }
13129
13130    sc->port.pmf = 0;
13131
13132bxe_nic_load_error1:
13133
13134    /* clear pf_load status, as it was already set */
13135    if (IS_PF(sc)) {
13136        bxe_clear_pf_load(sc);
13137    }
13138
13139bxe_nic_load_error0:
13140
13141    bxe_free_fw_stats_mem(sc);
13142    bxe_free_fp_buffers(sc);
13143    bxe_free_mem(sc);
13144
13145    return (rc);
13146}
13147
13148static int
13149bxe_init_locked(struct bxe_softc *sc)
13150{
13151    int other_engine = SC_PATH(sc) ? 0 : 1;
13152    uint8_t other_load_status, load_status;
13153    uint8_t global = FALSE;
13154    int rc;
13155
13156    BXE_CORE_LOCK_ASSERT(sc);
13157
13158    /* check if the driver is already running */
13159    if (if_getdrvflags(sc->ifp) & IFF_DRV_RUNNING) {
13160        BLOGD(sc, DBG_LOAD, "Init called while driver is running!\n");
13161        return (0);
13162    }
13163
13164    bxe_set_power_state(sc, PCI_PM_D0);
13165
13166    /*
13167     * If parity occurred during the unload, then attentions and/or
13168     * RECOVERY_IN_PROGRES may still be set. If so we want the first function
13169     * loaded on the current engine to complete the recovery. Parity recovery
13170     * is only relevant for PF driver.
13171     */
13172    if (IS_PF(sc)) {
13173        other_load_status = bxe_get_load_status(sc, other_engine);
13174        load_status = bxe_get_load_status(sc, SC_PATH(sc));
13175
13176        if (!bxe_reset_is_done(sc, SC_PATH(sc)) ||
13177            bxe_chk_parity_attn(sc, &global, TRUE)) {
13178            do {
13179                /*
13180                 * If there are attentions and they are in global blocks, set
13181                 * the GLOBAL_RESET bit regardless whether it will be this
13182                 * function that will complete the recovery or not.
13183                 */
13184                if (global) {
13185                    bxe_set_reset_global(sc);
13186                }
13187
13188                /*
13189                 * Only the first function on the current engine should try
13190                 * to recover in open. In case of attentions in global blocks
13191                 * only the first in the chip should try to recover.
13192                 */
13193                if ((!load_status && (!global || !other_load_status)) &&
13194                    bxe_trylock_leader_lock(sc) && !bxe_leader_reset(sc)) {
13195                    BLOGI(sc, "Recovered during init\n");
13196                    break;
13197                }
13198
13199                /* recovery has failed... */
13200                bxe_set_power_state(sc, PCI_PM_D3hot);
13201                sc->recovery_state = BXE_RECOVERY_FAILED;
13202
13203                BLOGE(sc, "Recovery flow hasn't properly "
13204                          "completed yet, try again later. "
13205                          "If you still see this message after a "
13206                          "few retries then power cycle is required.\n");
13207
13208                rc = ENXIO;
13209                goto bxe_init_locked_done;
13210            } while (0);
13211        }
13212    }
13213
13214    sc->recovery_state = BXE_RECOVERY_DONE;
13215
13216    rc = bxe_nic_load(sc, LOAD_OPEN);
13217
13218bxe_init_locked_done:
13219
13220    if (rc) {
13221        /* Tell the stack the driver is NOT running! */
13222        BLOGE(sc, "Initialization failed, "
13223                  "stack notified driver is NOT running!\n");
13224	if_setdrvflagbits(sc->ifp, 0, IFF_DRV_RUNNING);
13225    }
13226
13227    return (rc);
13228}
13229
13230static int
13231bxe_stop_locked(struct bxe_softc *sc)
13232{
13233    BXE_CORE_LOCK_ASSERT(sc);
13234    return (bxe_nic_unload(sc, UNLOAD_NORMAL, TRUE));
13235}
13236
13237/*
13238 * Handles controller initialization when called from an unlocked routine.
13239 * ifconfig calls this function.
13240 *
13241 * Returns:
13242 *   void
13243 */
13244static void
13245bxe_init(void *xsc)
13246{
13247    struct bxe_softc *sc = (struct bxe_softc *)xsc;
13248
13249    BXE_CORE_LOCK(sc);
13250    bxe_init_locked(sc);
13251    BXE_CORE_UNLOCK(sc);
13252}
13253
13254static int
13255bxe_init_ifnet(struct bxe_softc *sc)
13256{
13257    if_t ifp;
13258    int capabilities;
13259
13260    /* ifconfig entrypoint for media type/status reporting */
13261    ifmedia_init(&sc->ifmedia, IFM_IMASK,
13262                 bxe_ifmedia_update,
13263                 bxe_ifmedia_status);
13264
13265    /* set the default interface values */
13266    ifmedia_add(&sc->ifmedia, (IFM_ETHER | IFM_FDX | sc->media), 0, NULL);
13267    ifmedia_add(&sc->ifmedia, (IFM_ETHER | IFM_AUTO), 0, NULL);
13268    ifmedia_set(&sc->ifmedia, (IFM_ETHER | IFM_AUTO));
13269
13270    sc->ifmedia.ifm_media = sc->ifmedia.ifm_cur->ifm_media; /* XXX ? */
13271
13272    /* allocate the ifnet structure */
13273    if ((ifp = if_gethandle(IFT_ETHER)) == NULL) {
13274        BLOGE(sc, "Interface allocation failed!\n");
13275        return (ENXIO);
13276    }
13277
13278    if_setsoftc(ifp, sc);
13279    if_initname(ifp, device_get_name(sc->dev), device_get_unit(sc->dev));
13280    if_setflags(ifp, (IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST));
13281    if_setioctlfn(ifp, bxe_ioctl);
13282    if_setstartfn(ifp, bxe_tx_start);
13283    if_setgetcounterfn(ifp, bxe_get_counter);
13284#if __FreeBSD_version >= 800000
13285    if_settransmitfn(ifp, bxe_tx_mq_start);
13286    if_setqflushfn(ifp, bxe_mq_flush);
13287#endif
13288#ifdef FreeBSD8_0
13289    if_settimer(ifp, 0);
13290#endif
13291    if_setinitfn(ifp, bxe_init);
13292    if_setmtu(ifp, sc->mtu);
13293    if_sethwassist(ifp, (CSUM_IP      |
13294                        CSUM_TCP      |
13295                        CSUM_UDP      |
13296                        CSUM_TSO      |
13297                        CSUM_TCP_IPV6 |
13298                        CSUM_UDP_IPV6));
13299
13300    capabilities =
13301#if __FreeBSD_version < 700000
13302        (IFCAP_VLAN_MTU       |
13303         IFCAP_VLAN_HWTAGGING |
13304         IFCAP_HWCSUM         |
13305         IFCAP_JUMBO_MTU      |
13306         IFCAP_LRO);
13307#else
13308        (IFCAP_VLAN_MTU       |
13309         IFCAP_VLAN_HWTAGGING |
13310         IFCAP_VLAN_HWTSO     |
13311         IFCAP_VLAN_HWFILTER  |
13312         IFCAP_VLAN_HWCSUM    |
13313         IFCAP_HWCSUM         |
13314         IFCAP_JUMBO_MTU      |
13315         IFCAP_LRO            |
13316         IFCAP_TSO4           |
13317         IFCAP_TSO6           |
13318         IFCAP_WOL_MAGIC);
13319#endif
13320    if_setcapabilitiesbit(ifp, capabilities, 0); /* XXX */
13321    if_setbaudrate(ifp, IF_Gbps(10));
13322/* XXX */
13323    if_setsendqlen(ifp, sc->tx_ring_size);
13324    if_setsendqready(ifp);
13325/* XXX */
13326
13327    sc->ifp = ifp;
13328
13329    /* attach to the Ethernet interface list */
13330    ether_ifattach(ifp, sc->link_params.mac_addr);
13331
13332    return (0);
13333}
13334
13335static void
13336bxe_deallocate_bars(struct bxe_softc *sc)
13337{
13338    int i;
13339
13340    for (i = 0; i < MAX_BARS; i++) {
13341        if (sc->bar[i].resource != NULL) {
13342            bus_release_resource(sc->dev,
13343                                 SYS_RES_MEMORY,
13344                                 sc->bar[i].rid,
13345                                 sc->bar[i].resource);
13346            BLOGD(sc, DBG_LOAD, "Released PCI BAR%d [%02x] memory\n",
13347                  i, PCIR_BAR(i));
13348        }
13349    }
13350}
13351
13352static int
13353bxe_allocate_bars(struct bxe_softc *sc)
13354{
13355    u_int flags;
13356    int i;
13357
13358    memset(sc->bar, 0, sizeof(sc->bar));
13359
13360    for (i = 0; i < MAX_BARS; i++) {
13361
13362        /* memory resources reside at BARs 0, 2, 4 */
13363        /* Run `pciconf -lb` to see mappings */
13364        if ((i != 0) && (i != 2) && (i != 4)) {
13365            continue;
13366        }
13367
13368        sc->bar[i].rid = PCIR_BAR(i);
13369
13370        flags = RF_ACTIVE;
13371        if (i == 0) {
13372            flags |= RF_SHAREABLE;
13373        }
13374
13375        if ((sc->bar[i].resource =
13376             bus_alloc_resource_any(sc->dev,
13377                                    SYS_RES_MEMORY,
13378                                    &sc->bar[i].rid,
13379                                    flags)) == NULL) {
13380#if 0
13381            /* BAR4 doesn't exist for E1 */
13382            BLOGE(sc, "PCI BAR%d [%02x] memory allocation failed\n",
13383                  i, PCIR_BAR(i));
13384#endif
13385            return (0);
13386        }
13387
13388        sc->bar[i].tag    = rman_get_bustag(sc->bar[i].resource);
13389        sc->bar[i].handle = rman_get_bushandle(sc->bar[i].resource);
13390        sc->bar[i].kva    = (vm_offset_t)rman_get_virtual(sc->bar[i].resource);
13391
13392        BLOGI(sc, "PCI BAR%d [%02x] memory allocated: %p-%p (%ld) -> %p\n",
13393              i, PCIR_BAR(i),
13394              (void *)rman_get_start(sc->bar[i].resource),
13395              (void *)rman_get_end(sc->bar[i].resource),
13396              rman_get_size(sc->bar[i].resource),
13397              (void *)sc->bar[i].kva);
13398    }
13399
13400    return (0);
13401}
13402
13403static void
13404bxe_get_function_num(struct bxe_softc *sc)
13405{
13406    uint32_t val = 0;
13407
13408    /*
13409     * Read the ME register to get the function number. The ME register
13410     * holds the relative-function number and absolute-function number. The
13411     * absolute-function number appears only in E2 and above. Before that
13412     * these bits always contained zero, therefore we cannot blindly use them.
13413     */
13414
13415    val = REG_RD(sc, BAR_ME_REGISTER);
13416
13417    sc->pfunc_rel =
13418        (uint8_t)((val & ME_REG_PF_NUM) >> ME_REG_PF_NUM_SHIFT);
13419    sc->path_id =
13420        (uint8_t)((val & ME_REG_ABS_PF_NUM) >> ME_REG_ABS_PF_NUM_SHIFT) & 1;
13421
13422    if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {
13423        sc->pfunc_abs = ((sc->pfunc_rel << 1) | sc->path_id);
13424    } else {
13425        sc->pfunc_abs = (sc->pfunc_rel | sc->path_id);
13426    }
13427
13428    BLOGD(sc, DBG_LOAD,
13429          "Relative function %d, Absolute function %d, Path %d\n",
13430          sc->pfunc_rel, sc->pfunc_abs, sc->path_id);
13431}
13432
13433static uint32_t
13434bxe_get_shmem_mf_cfg_base(struct bxe_softc *sc)
13435{
13436    uint32_t shmem2_size;
13437    uint32_t offset;
13438    uint32_t mf_cfg_offset_value;
13439
13440    /* Non 57712 */
13441    offset = (SHMEM_RD(sc, func_mb) +
13442              (MAX_FUNC_NUM * sizeof(struct drv_func_mb)));
13443
13444    /* 57712 plus */
13445    if (sc->devinfo.shmem2_base != 0) {
13446        shmem2_size = SHMEM2_RD(sc, size);
13447        if (shmem2_size > offsetof(struct shmem2_region, mf_cfg_addr)) {
13448            mf_cfg_offset_value = SHMEM2_RD(sc, mf_cfg_addr);
13449            if (SHMEM_MF_CFG_ADDR_NONE != mf_cfg_offset_value) {
13450                offset = mf_cfg_offset_value;
13451            }
13452        }
13453    }
13454
13455    return (offset);
13456}
13457
13458static uint32_t
13459bxe_pcie_capability_read(struct bxe_softc *sc,
13460                         int    reg,
13461                         int    width)
13462{
13463    int pcie_reg;
13464
13465    /* ensure PCIe capability is enabled */
13466    if (pci_find_cap(sc->dev, PCIY_EXPRESS, &pcie_reg) == 0) {
13467        if (pcie_reg != 0) {
13468            BLOGD(sc, DBG_LOAD, "PCIe capability at 0x%04x\n", pcie_reg);
13469            return (pci_read_config(sc->dev, (pcie_reg + reg), width));
13470        }
13471    }
13472
13473    BLOGE(sc, "PCIe capability NOT FOUND!!!\n");
13474
13475    return (0);
13476}
13477
13478static uint8_t
13479bxe_is_pcie_pending(struct bxe_softc *sc)
13480{
13481    return (bxe_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_STA, 2) &
13482            PCIM_EXP_STA_TRANSACTION_PND);
13483}
13484
13485/*
13486 * Walk the PCI capabiites list for the device to find what features are
13487 * supported. These capabilites may be enabled/disabled by firmware so it's
13488 * best to walk the list rather than make assumptions.
13489 */
13490static void
13491bxe_probe_pci_caps(struct bxe_softc *sc)
13492{
13493    uint16_t link_status;
13494    int reg;
13495
13496    /* check if PCI Power Management is enabled */
13497    if (pci_find_cap(sc->dev, PCIY_PMG, &reg) == 0) {
13498        if (reg != 0) {
13499            BLOGD(sc, DBG_LOAD, "Found PM capability at 0x%04x\n", reg);
13500
13501            sc->devinfo.pcie_cap_flags |= BXE_PM_CAPABLE_FLAG;
13502            sc->devinfo.pcie_pm_cap_reg = (uint16_t)reg;
13503        }
13504    }
13505
13506    link_status = bxe_pcie_capability_read(sc, PCIR_EXPRESS_LINK_STA, 2);
13507
13508    /* handle PCIe 2.0 workarounds for 57710 */
13509    if (CHIP_IS_E1(sc)) {
13510        /* workaround for 57710 errata E4_57710_27462 */
13511        sc->devinfo.pcie_link_speed =
13512            (REG_RD(sc, 0x3d04) & (1 << 24)) ? 2 : 1;
13513
13514        /* workaround for 57710 errata E4_57710_27488 */
13515        sc->devinfo.pcie_link_width =
13516            ((link_status & PCIM_LINK_STA_WIDTH) >> 4);
13517        if (sc->devinfo.pcie_link_speed > 1) {
13518            sc->devinfo.pcie_link_width =
13519                ((link_status & PCIM_LINK_STA_WIDTH) >> 4) >> 1;
13520        }
13521    } else {
13522        sc->devinfo.pcie_link_speed =
13523            (link_status & PCIM_LINK_STA_SPEED);
13524        sc->devinfo.pcie_link_width =
13525            ((link_status & PCIM_LINK_STA_WIDTH) >> 4);
13526    }
13527
13528    BLOGD(sc, DBG_LOAD, "PCIe link speed=%d width=%d\n",
13529          sc->devinfo.pcie_link_speed, sc->devinfo.pcie_link_width);
13530
13531    sc->devinfo.pcie_cap_flags |= BXE_PCIE_CAPABLE_FLAG;
13532    sc->devinfo.pcie_pcie_cap_reg = (uint16_t)reg;
13533
13534    /* check if MSI capability is enabled */
13535    if (pci_find_cap(sc->dev, PCIY_MSI, &reg) == 0) {
13536        if (reg != 0) {
13537            BLOGD(sc, DBG_LOAD, "Found MSI capability at 0x%04x\n", reg);
13538
13539            sc->devinfo.pcie_cap_flags |= BXE_MSI_CAPABLE_FLAG;
13540            sc->devinfo.pcie_msi_cap_reg = (uint16_t)reg;
13541        }
13542    }
13543
13544    /* check if MSI-X capability is enabled */
13545    if (pci_find_cap(sc->dev, PCIY_MSIX, &reg) == 0) {
13546        if (reg != 0) {
13547            BLOGD(sc, DBG_LOAD, "Found MSI-X capability at 0x%04x\n", reg);
13548
13549            sc->devinfo.pcie_cap_flags |= BXE_MSIX_CAPABLE_FLAG;
13550            sc->devinfo.pcie_msix_cap_reg = (uint16_t)reg;
13551        }
13552    }
13553}
13554
13555static int
13556bxe_get_shmem_mf_cfg_info_sd(struct bxe_softc *sc)
13557{
13558    struct bxe_mf_info *mf_info = &sc->devinfo.mf_info;
13559    uint32_t val;
13560
13561    /* get the outer vlan if we're in switch-dependent mode */
13562
13563    val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
13564    mf_info->ext_id = (uint16_t)val;
13565
13566    mf_info->multi_vnics_mode = 1;
13567
13568    if (!VALID_OVLAN(mf_info->ext_id)) {
13569        BLOGE(sc, "Invalid VLAN (%d)\n", mf_info->ext_id);
13570        return (1);
13571    }
13572
13573    /* get the capabilities */
13574    if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK) ==
13575        FUNC_MF_CFG_PROTOCOL_ISCSI) {
13576        mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ISCSI;
13577    } else if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK) ==
13578               FUNC_MF_CFG_PROTOCOL_FCOE) {
13579        mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_FCOE;
13580    } else {
13581        mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ETHERNET;
13582    }
13583
13584    mf_info->vnics_per_port =
13585        (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
13586
13587    return (0);
13588}
13589
13590static uint32_t
13591bxe_get_shmem_ext_proto_support_flags(struct bxe_softc *sc)
13592{
13593    uint32_t retval = 0;
13594    uint32_t val;
13595
13596    val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);
13597
13598    if (val & MACP_FUNC_CFG_FLAGS_ENABLED) {
13599        if (val & MACP_FUNC_CFG_FLAGS_ETHERNET) {
13600            retval |= MF_PROTO_SUPPORT_ETHERNET;
13601        }
13602        if (val & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
13603            retval |= MF_PROTO_SUPPORT_ISCSI;
13604        }
13605        if (val & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
13606            retval |= MF_PROTO_SUPPORT_FCOE;
13607        }
13608    }
13609
13610    return (retval);
13611}
13612
13613static int
13614bxe_get_shmem_mf_cfg_info_si(struct bxe_softc *sc)
13615{
13616    struct bxe_mf_info *mf_info = &sc->devinfo.mf_info;
13617    uint32_t val;
13618
13619    /*
13620     * There is no outer vlan if we're in switch-independent mode.
13621     * If the mac is valid then assume multi-function.
13622     */
13623
13624    val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);
13625
13626    mf_info->multi_vnics_mode = ((val & MACP_FUNC_CFG_FLAGS_MASK) != 0);
13627
13628    mf_info->mf_protos_supported = bxe_get_shmem_ext_proto_support_flags(sc);
13629
13630    mf_info->vnics_per_port =
13631        (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
13632
13633    return (0);
13634}
13635
13636static int
13637bxe_get_shmem_mf_cfg_info_niv(struct bxe_softc *sc)
13638{
13639    struct bxe_mf_info *mf_info = &sc->devinfo.mf_info;
13640    uint32_t e1hov_tag;
13641    uint32_t func_config;
13642    uint32_t niv_config;
13643
13644    mf_info->multi_vnics_mode = 1;
13645
13646    e1hov_tag   = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
13647    func_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
13648    niv_config  = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].afex_config);
13649
13650    mf_info->ext_id =
13651        (uint16_t)((e1hov_tag & FUNC_MF_CFG_E1HOV_TAG_MASK) >>
13652                   FUNC_MF_CFG_E1HOV_TAG_SHIFT);
13653
13654    mf_info->default_vlan =
13655        (uint16_t)((e1hov_tag & FUNC_MF_CFG_AFEX_VLAN_MASK) >>
13656                   FUNC_MF_CFG_AFEX_VLAN_SHIFT);
13657
13658    mf_info->niv_allowed_priorities =
13659        (uint8_t)((niv_config & FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
13660                  FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT);
13661
13662    mf_info->niv_default_cos =
13663        (uint8_t)((func_config & FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
13664                  FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT);
13665
13666    mf_info->afex_vlan_mode =
13667        ((niv_config & FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
13668         FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT);
13669
13670    mf_info->niv_mba_enabled =
13671        ((niv_config & FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK) >>
13672         FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT);
13673
13674    mf_info->mf_protos_supported = bxe_get_shmem_ext_proto_support_flags(sc);
13675
13676    mf_info->vnics_per_port =
13677        (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
13678
13679    return (0);
13680}
13681
13682static int
13683bxe_check_valid_mf_cfg(struct bxe_softc *sc)
13684{
13685    struct bxe_mf_info *mf_info = &sc->devinfo.mf_info;
13686    uint32_t mf_cfg1;
13687    uint32_t mf_cfg2;
13688    uint32_t ovlan1;
13689    uint32_t ovlan2;
13690    uint8_t i, j;
13691
13692    BLOGD(sc, DBG_LOAD, "MF config parameters for function %d\n",
13693          SC_PORT(sc));
13694    BLOGD(sc, DBG_LOAD, "\tmf_config=0x%x\n",
13695          mf_info->mf_config[SC_VN(sc)]);
13696    BLOGD(sc, DBG_LOAD, "\tmulti_vnics_mode=%d\n",
13697          mf_info->multi_vnics_mode);
13698    BLOGD(sc, DBG_LOAD, "\tvnics_per_port=%d\n",
13699          mf_info->vnics_per_port);
13700    BLOGD(sc, DBG_LOAD, "\tovlan/vifid=%d\n",
13701          mf_info->ext_id);
13702    BLOGD(sc, DBG_LOAD, "\tmin_bw=%d/%d/%d/%d\n",
13703          mf_info->min_bw[0], mf_info->min_bw[1],
13704          mf_info->min_bw[2], mf_info->min_bw[3]);
13705    BLOGD(sc, DBG_LOAD, "\tmax_bw=%d/%d/%d/%d\n",
13706          mf_info->max_bw[0], mf_info->max_bw[1],
13707          mf_info->max_bw[2], mf_info->max_bw[3]);
13708    BLOGD(sc, DBG_LOAD, "\tmac_addr: %s\n",
13709          sc->mac_addr_str);
13710
13711    /* various MF mode sanity checks... */
13712
13713    if (mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_HIDE) {
13714        BLOGE(sc, "Enumerated function %d is marked as hidden\n",
13715              SC_PORT(sc));
13716        return (1);
13717    }
13718
13719    if ((mf_info->vnics_per_port > 1) && !mf_info->multi_vnics_mode) {
13720        BLOGE(sc, "vnics_per_port=%d multi_vnics_mode=%d\n",
13721              mf_info->vnics_per_port, mf_info->multi_vnics_mode);
13722        return (1);
13723    }
13724
13725    if (mf_info->mf_mode == MULTI_FUNCTION_SD) {
13726        /* vnic id > 0 must have valid ovlan in switch-dependent mode */
13727        if ((SC_VN(sc) > 0) && !VALID_OVLAN(OVLAN(sc))) {
13728            BLOGE(sc, "mf_mode=SD vnic_id=%d ovlan=%d\n",
13729                  SC_VN(sc), OVLAN(sc));
13730            return (1);
13731        }
13732
13733        if (!VALID_OVLAN(OVLAN(sc)) && mf_info->multi_vnics_mode) {
13734            BLOGE(sc, "mf_mode=SD multi_vnics_mode=%d ovlan=%d\n",
13735                  mf_info->multi_vnics_mode, OVLAN(sc));
13736            return (1);
13737        }
13738
13739        /*
13740         * Verify all functions are either MF or SF mode. If MF, make sure
13741         * sure that all non-hidden functions have a valid ovlan. If SF,
13742         * make sure that all non-hidden functions have an invalid ovlan.
13743         */
13744        FOREACH_ABS_FUNC_IN_PORT(sc, i) {
13745            mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);
13746            ovlan1  = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
13747            if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE) &&
13748                (((mf_info->multi_vnics_mode) && !VALID_OVLAN(ovlan1)) ||
13749                 ((!mf_info->multi_vnics_mode) && VALID_OVLAN(ovlan1)))) {
13750                BLOGE(sc, "mf_mode=SD function %d MF config "
13751                          "mismatch, multi_vnics_mode=%d ovlan=%d\n",
13752                      i, mf_info->multi_vnics_mode, ovlan1);
13753                return (1);
13754            }
13755        }
13756
13757        /* Verify all funcs on the same port each have a different ovlan. */
13758        FOREACH_ABS_FUNC_IN_PORT(sc, i) {
13759            mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);
13760            ovlan1  = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
13761            /* iterate from the next function on the port to the max func */
13762            for (j = i + 2; j < MAX_FUNC_NUM; j += 2) {
13763                mf_cfg2 = MFCFG_RD(sc, func_mf_config[j].config);
13764                ovlan2  = MFCFG_RD(sc, func_mf_config[j].e1hov_tag);
13765                if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE) &&
13766                    VALID_OVLAN(ovlan1) &&
13767                    !(mf_cfg2 & FUNC_MF_CFG_FUNC_HIDE) &&
13768                    VALID_OVLAN(ovlan2) &&
13769                    (ovlan1 == ovlan2)) {
13770                    BLOGE(sc, "mf_mode=SD functions %d and %d "
13771                              "have the same ovlan (%d)\n",
13772                          i, j, ovlan1);
13773                    return (1);
13774                }
13775            }
13776        }
13777    } /* MULTI_FUNCTION_SD */
13778
13779    return (0);
13780}
13781
13782static int
13783bxe_get_mf_cfg_info(struct bxe_softc *sc)
13784{
13785    struct bxe_mf_info *mf_info = &sc->devinfo.mf_info;
13786    uint32_t val, mac_upper;
13787    uint8_t i, vnic;
13788
13789    /* initialize mf_info defaults */
13790    mf_info->vnics_per_port   = 1;
13791    mf_info->multi_vnics_mode = FALSE;
13792    mf_info->path_has_ovlan   = FALSE;
13793    mf_info->mf_mode          = SINGLE_FUNCTION;
13794
13795    if (!CHIP_IS_MF_CAP(sc)) {
13796        return (0);
13797    }
13798
13799    if (sc->devinfo.mf_cfg_base == SHMEM_MF_CFG_ADDR_NONE) {
13800        BLOGE(sc, "Invalid mf_cfg_base!\n");
13801        return (1);
13802    }
13803
13804    /* get the MF mode (switch dependent / independent / single-function) */
13805
13806    val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
13807
13808    switch (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK)
13809    {
13810    case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
13811
13812        mac_upper = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
13813
13814        /* check for legal upper mac bytes */
13815        if (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT) {
13816            mf_info->mf_mode = MULTI_FUNCTION_SI;
13817        } else {
13818            BLOGE(sc, "Invalid config for Switch Independent mode\n");
13819        }
13820
13821        break;
13822
13823    case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
13824    case SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4:
13825
13826        /* get outer vlan configuration */
13827        val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
13828
13829        if ((val & FUNC_MF_CFG_E1HOV_TAG_MASK) !=
13830            FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
13831            mf_info->mf_mode = MULTI_FUNCTION_SD;
13832        } else {
13833            BLOGE(sc, "Invalid config for Switch Dependent mode\n");
13834        }
13835
13836        break;
13837
13838    case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
13839
13840        /* not in MF mode, vnics_per_port=1 and multi_vnics_mode=FALSE */
13841        return (0);
13842
13843    case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
13844
13845        /*
13846         * Mark MF mode as NIV if MCP version includes NPAR-SD support
13847         * and the MAC address is valid.
13848         */
13849        mac_upper = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
13850
13851        if ((SHMEM2_HAS(sc, afex_driver_support)) &&
13852            (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT)) {
13853            mf_info->mf_mode = MULTI_FUNCTION_AFEX;
13854        } else {
13855            BLOGE(sc, "Invalid config for AFEX mode\n");
13856        }
13857
13858        break;
13859
13860    default:
13861
13862        BLOGE(sc, "Unknown MF mode (0x%08x)\n",
13863              (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK));
13864
13865        return (1);
13866    }
13867
13868    /* set path mf_mode (which could be different than function mf_mode) */
13869    if (mf_info->mf_mode == MULTI_FUNCTION_SD) {
13870        mf_info->path_has_ovlan = TRUE;
13871    } else if (mf_info->mf_mode == SINGLE_FUNCTION) {
13872        /*
13873         * Decide on path multi vnics mode. If we're not in MF mode and in
13874         * 4-port mode, this is good enough to check vnic-0 of the other port
13875         * on the same path
13876         */
13877        if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {
13878            uint8_t other_port = !(PORT_ID(sc) & 1);
13879            uint8_t abs_func_other_port = (SC_PATH(sc) + (2 * other_port));
13880
13881            val = MFCFG_RD(sc, func_mf_config[abs_func_other_port].e1hov_tag);
13882
13883            mf_info->path_has_ovlan = VALID_OVLAN((uint16_t)val) ? 1 : 0;
13884        }
13885    }
13886
13887    if (mf_info->mf_mode == SINGLE_FUNCTION) {
13888        /* invalid MF config */
13889        if (SC_VN(sc) >= 1) {
13890            BLOGE(sc, "VNIC ID >= 1 in SF mode\n");
13891            return (1);
13892        }
13893
13894        return (0);
13895    }
13896
13897    /* get the MF configuration */
13898    mf_info->mf_config[SC_VN(sc)] =
13899        MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
13900
13901    switch(mf_info->mf_mode)
13902    {
13903    case MULTI_FUNCTION_SD:
13904
13905        bxe_get_shmem_mf_cfg_info_sd(sc);
13906        break;
13907
13908    case MULTI_FUNCTION_SI:
13909
13910        bxe_get_shmem_mf_cfg_info_si(sc);
13911        break;
13912
13913    case MULTI_FUNCTION_AFEX:
13914
13915        bxe_get_shmem_mf_cfg_info_niv(sc);
13916        break;
13917
13918    default:
13919
13920        BLOGE(sc, "Get MF config failed (mf_mode=0x%08x)\n",
13921              mf_info->mf_mode);
13922        return (1);
13923    }
13924
13925    /* get the congestion management parameters */
13926
13927    vnic = 0;
13928    FOREACH_ABS_FUNC_IN_PORT(sc, i) {
13929        /* get min/max bw */
13930        val = MFCFG_RD(sc, func_mf_config[i].config);
13931        mf_info->min_bw[vnic] =
13932            ((val & FUNC_MF_CFG_MIN_BW_MASK) >> FUNC_MF_CFG_MIN_BW_SHIFT);
13933        mf_info->max_bw[vnic] =
13934            ((val & FUNC_MF_CFG_MAX_BW_MASK) >> FUNC_MF_CFG_MAX_BW_SHIFT);
13935        vnic++;
13936    }
13937
13938    return (bxe_check_valid_mf_cfg(sc));
13939}
13940
13941static int
13942bxe_get_shmem_info(struct bxe_softc *sc)
13943{
13944    int port;
13945    uint32_t mac_hi, mac_lo, val;
13946
13947    port = SC_PORT(sc);
13948    mac_hi = mac_lo = 0;
13949
13950    sc->link_params.sc   = sc;
13951    sc->link_params.port = port;
13952
13953    /* get the hardware config info */
13954    sc->devinfo.hw_config =
13955        SHMEM_RD(sc, dev_info.shared_hw_config.config);
13956    sc->devinfo.hw_config2 =
13957        SHMEM_RD(sc, dev_info.shared_hw_config.config2);
13958
13959    sc->link_params.hw_led_mode =
13960        ((sc->devinfo.hw_config & SHARED_HW_CFG_LED_MODE_MASK) >>
13961         SHARED_HW_CFG_LED_MODE_SHIFT);
13962
13963    /* get the port feature config */
13964    sc->port.config =
13965        SHMEM_RD(sc, dev_info.port_feature_config[port].config),
13966
13967    /* get the link params */
13968    sc->link_params.speed_cap_mask[0] =
13969        SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask);
13970    sc->link_params.speed_cap_mask[1] =
13971        SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask2);
13972
13973    /* get the lane config */
13974    sc->link_params.lane_config =
13975        SHMEM_RD(sc, dev_info.port_hw_config[port].lane_config);
13976
13977    /* get the link config */
13978    val = SHMEM_RD(sc, dev_info.port_feature_config[port].link_config);
13979    sc->port.link_config[ELINK_INT_PHY] = val;
13980    sc->link_params.switch_cfg = (val & PORT_FEATURE_CONNECTED_SWITCH_MASK);
13981    sc->port.link_config[ELINK_EXT_PHY1] =
13982        SHMEM_RD(sc, dev_info.port_feature_config[port].link_config2);
13983
13984    /* get the override preemphasis flag and enable it or turn it off */
13985    val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
13986    if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED) {
13987        sc->link_params.feature_config_flags |=
13988            ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
13989    } else {
13990        sc->link_params.feature_config_flags &=
13991            ~ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
13992    }
13993
13994    /* get the initial value of the link params */
13995    sc->link_params.multi_phy_config =
13996        SHMEM_RD(sc, dev_info.port_hw_config[port].multi_phy_config);
13997
13998    /* get external phy info */
13999    sc->port.ext_phy_config =
14000        SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
14001
14002    /* get the multifunction configuration */
14003    bxe_get_mf_cfg_info(sc);
14004
14005    /* get the mac address */
14006    if (IS_MF(sc)) {
14007        mac_hi = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
14008        mac_lo = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_lower);
14009    } else {
14010        mac_hi = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_upper);
14011        mac_lo = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_lower);
14012    }
14013
14014    if ((mac_lo == 0) && (mac_hi == 0)) {
14015        *sc->mac_addr_str = 0;
14016        BLOGE(sc, "No Ethernet address programmed!\n");
14017    } else {
14018        sc->link_params.mac_addr[0] = (uint8_t)(mac_hi >> 8);
14019        sc->link_params.mac_addr[1] = (uint8_t)(mac_hi);
14020        sc->link_params.mac_addr[2] = (uint8_t)(mac_lo >> 24);
14021        sc->link_params.mac_addr[3] = (uint8_t)(mac_lo >> 16);
14022        sc->link_params.mac_addr[4] = (uint8_t)(mac_lo >> 8);
14023        sc->link_params.mac_addr[5] = (uint8_t)(mac_lo);
14024        snprintf(sc->mac_addr_str, sizeof(sc->mac_addr_str),
14025                 "%02x:%02x:%02x:%02x:%02x:%02x",
14026                 sc->link_params.mac_addr[0], sc->link_params.mac_addr[1],
14027                 sc->link_params.mac_addr[2], sc->link_params.mac_addr[3],
14028                 sc->link_params.mac_addr[4], sc->link_params.mac_addr[5]);
14029        BLOGD(sc, DBG_LOAD, "Ethernet address: %s\n", sc->mac_addr_str);
14030    }
14031
14032#if 0
14033    if (!IS_MF(sc) &&
14034        ((sc->port.config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
14035         PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE)) {
14036        sc->flags |= BXE_NO_ISCSI;
14037    }
14038    if (!IS_MF(sc) &&
14039        ((sc->port.config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
14040         PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI)) {
14041        sc->flags |= BXE_NO_FCOE_FLAG;
14042    }
14043#endif
14044
14045    return (0);
14046}
14047
14048static void
14049bxe_get_tunable_params(struct bxe_softc *sc)
14050{
14051    /* sanity checks */
14052
14053    if ((bxe_interrupt_mode != INTR_MODE_INTX) &&
14054        (bxe_interrupt_mode != INTR_MODE_MSI)  &&
14055        (bxe_interrupt_mode != INTR_MODE_MSIX)) {
14056        BLOGW(sc, "invalid interrupt_mode value (%d)\n", bxe_interrupt_mode);
14057        bxe_interrupt_mode = INTR_MODE_MSIX;
14058    }
14059
14060    if ((bxe_queue_count < 0) || (bxe_queue_count > MAX_RSS_CHAINS)) {
14061        BLOGW(sc, "invalid queue_count value (%d)\n", bxe_queue_count);
14062        bxe_queue_count = 0;
14063    }
14064
14065    if ((bxe_max_rx_bufs < 1) || (bxe_max_rx_bufs > RX_BD_USABLE)) {
14066        if (bxe_max_rx_bufs == 0) {
14067            bxe_max_rx_bufs = RX_BD_USABLE;
14068        } else {
14069            BLOGW(sc, "invalid max_rx_bufs (%d)\n", bxe_max_rx_bufs);
14070            bxe_max_rx_bufs = 2048;
14071        }
14072    }
14073
14074    if ((bxe_hc_rx_ticks < 1) || (bxe_hc_rx_ticks > 100)) {
14075        BLOGW(sc, "invalid hc_rx_ticks (%d)\n", bxe_hc_rx_ticks);
14076        bxe_hc_rx_ticks = 25;
14077    }
14078
14079    if ((bxe_hc_tx_ticks < 1) || (bxe_hc_tx_ticks > 100)) {
14080        BLOGW(sc, "invalid hc_tx_ticks (%d)\n", bxe_hc_tx_ticks);
14081        bxe_hc_tx_ticks = 50;
14082    }
14083
14084    if (bxe_max_aggregation_size == 0) {
14085        bxe_max_aggregation_size = TPA_AGG_SIZE;
14086    }
14087
14088    if (bxe_max_aggregation_size > 0xffff) {
14089        BLOGW(sc, "invalid max_aggregation_size (%d)\n",
14090              bxe_max_aggregation_size);
14091        bxe_max_aggregation_size = TPA_AGG_SIZE;
14092    }
14093
14094    if ((bxe_mrrs < -1) || (bxe_mrrs > 3)) {
14095        BLOGW(sc, "invalid mrrs (%d)\n", bxe_mrrs);
14096        bxe_mrrs = -1;
14097    }
14098
14099    if ((bxe_autogreeen < 0) || (bxe_autogreeen > 2)) {
14100        BLOGW(sc, "invalid autogreeen (%d)\n", bxe_autogreeen);
14101        bxe_autogreeen = 0;
14102    }
14103
14104    if ((bxe_udp_rss < 0) || (bxe_udp_rss > 1)) {
14105        BLOGW(sc, "invalid udp_rss (%d)\n", bxe_udp_rss);
14106        bxe_udp_rss = 0;
14107    }
14108
14109    /* pull in user settings */
14110
14111    sc->interrupt_mode       = bxe_interrupt_mode;
14112    sc->max_rx_bufs          = bxe_max_rx_bufs;
14113    sc->hc_rx_ticks          = bxe_hc_rx_ticks;
14114    sc->hc_tx_ticks          = bxe_hc_tx_ticks;
14115    sc->max_aggregation_size = bxe_max_aggregation_size;
14116    sc->mrrs                 = bxe_mrrs;
14117    sc->autogreeen           = bxe_autogreeen;
14118    sc->udp_rss              = bxe_udp_rss;
14119
14120    if (bxe_interrupt_mode == INTR_MODE_INTX) {
14121        sc->num_queues = 1;
14122    } else { /* INTR_MODE_MSI or INTR_MODE_MSIX */
14123        sc->num_queues =
14124            min((bxe_queue_count ? bxe_queue_count : mp_ncpus),
14125                MAX_RSS_CHAINS);
14126        if (sc->num_queues > mp_ncpus) {
14127            sc->num_queues = mp_ncpus;
14128        }
14129    }
14130
14131    BLOGD(sc, DBG_LOAD,
14132          "User Config: "
14133          "debug=0x%lx "
14134          "interrupt_mode=%d "
14135          "queue_count=%d "
14136          "hc_rx_ticks=%d "
14137          "hc_tx_ticks=%d "
14138          "rx_budget=%d "
14139          "max_aggregation_size=%d "
14140          "mrrs=%d "
14141          "autogreeen=%d "
14142          "udp_rss=%d\n",
14143          bxe_debug,
14144          sc->interrupt_mode,
14145          sc->num_queues,
14146          sc->hc_rx_ticks,
14147          sc->hc_tx_ticks,
14148          bxe_rx_budget,
14149          sc->max_aggregation_size,
14150          sc->mrrs,
14151          sc->autogreeen,
14152          sc->udp_rss);
14153}
14154
14155static void
14156bxe_media_detect(struct bxe_softc *sc)
14157{
14158    uint32_t phy_idx = bxe_get_cur_phy_idx(sc);
14159    switch (sc->link_params.phy[phy_idx].media_type) {
14160    case ELINK_ETH_PHY_SFPP_10G_FIBER:
14161    case ELINK_ETH_PHY_XFP_FIBER:
14162        BLOGI(sc, "Found 10Gb Fiber media.\n");
14163        sc->media = IFM_10G_SR;
14164        break;
14165    case ELINK_ETH_PHY_SFP_1G_FIBER:
14166        BLOGI(sc, "Found 1Gb Fiber media.\n");
14167        sc->media = IFM_1000_SX;
14168        break;
14169    case ELINK_ETH_PHY_KR:
14170    case ELINK_ETH_PHY_CX4:
14171        BLOGI(sc, "Found 10GBase-CX4 media.\n");
14172        sc->media = IFM_10G_CX4;
14173        break;
14174    case ELINK_ETH_PHY_DA_TWINAX:
14175        BLOGI(sc, "Found 10Gb Twinax media.\n");
14176        sc->media = IFM_10G_TWINAX;
14177        break;
14178    case ELINK_ETH_PHY_BASE_T:
14179        if (sc->link_params.speed_cap_mask[0] &
14180            PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) {
14181            BLOGI(sc, "Found 10GBase-T media.\n");
14182            sc->media = IFM_10G_T;
14183        } else {
14184            BLOGI(sc, "Found 1000Base-T media.\n");
14185            sc->media = IFM_1000_T;
14186        }
14187        break;
14188    case ELINK_ETH_PHY_NOT_PRESENT:
14189        BLOGI(sc, "Media not present.\n");
14190        sc->media = 0;
14191        break;
14192    case ELINK_ETH_PHY_UNSPECIFIED:
14193    default:
14194        BLOGI(sc, "Unknown media!\n");
14195        sc->media = 0;
14196        break;
14197    }
14198}
14199
14200#define GET_FIELD(value, fname)                     \
14201    (((value) & (fname##_MASK)) >> (fname##_SHIFT))
14202#define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
14203#define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
14204
14205static int
14206bxe_get_igu_cam_info(struct bxe_softc *sc)
14207{
14208    int pfid = SC_FUNC(sc);
14209    int igu_sb_id;
14210    uint32_t val;
14211    uint8_t fid, igu_sb_cnt = 0;
14212
14213    sc->igu_base_sb = 0xff;
14214
14215    if (CHIP_INT_MODE_IS_BC(sc)) {
14216        int vn = SC_VN(sc);
14217        igu_sb_cnt = sc->igu_sb_cnt;
14218        sc->igu_base_sb = ((CHIP_IS_MODE_4_PORT(sc) ? pfid : vn) *
14219                           FP_SB_MAX_E1x);
14220        sc->igu_dsb_id = (E1HVN_MAX * FP_SB_MAX_E1x +
14221                          (CHIP_IS_MODE_4_PORT(sc) ? pfid : vn));
14222        return (0);
14223    }
14224
14225    /* IGU in normal mode - read CAM */
14226    for (igu_sb_id = 0;
14227         igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
14228         igu_sb_id++) {
14229        val = REG_RD(sc, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
14230        if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) {
14231            continue;
14232        }
14233        fid = IGU_FID(val);
14234        if ((fid & IGU_FID_ENCODE_IS_PF)) {
14235            if ((fid & IGU_FID_PF_NUM_MASK) != pfid) {
14236                continue;
14237            }
14238            if (IGU_VEC(val) == 0) {
14239                /* default status block */
14240                sc->igu_dsb_id = igu_sb_id;
14241            } else {
14242                if (sc->igu_base_sb == 0xff) {
14243                    sc->igu_base_sb = igu_sb_id;
14244                }
14245                igu_sb_cnt++;
14246            }
14247        }
14248    }
14249
14250    /*
14251     * Due to new PF resource allocation by MFW T7.4 and above, it's optional
14252     * that number of CAM entries will not be equal to the value advertised in
14253     * PCI. Driver should use the minimal value of both as the actual status
14254     * block count
14255     */
14256    sc->igu_sb_cnt = min(sc->igu_sb_cnt, igu_sb_cnt);
14257
14258    if (igu_sb_cnt == 0) {
14259        BLOGE(sc, "CAM configuration error\n");
14260        return (-1);
14261    }
14262
14263    return (0);
14264}
14265
14266/*
14267 * Gather various information from the device config space, the device itself,
14268 * shmem, and the user input.
14269 */
14270static int
14271bxe_get_device_info(struct bxe_softc *sc)
14272{
14273    uint32_t val;
14274    int rc;
14275
14276    /* Get the data for the device */
14277    sc->devinfo.vendor_id    = pci_get_vendor(sc->dev);
14278    sc->devinfo.device_id    = pci_get_device(sc->dev);
14279    sc->devinfo.subvendor_id = pci_get_subvendor(sc->dev);
14280    sc->devinfo.subdevice_id = pci_get_subdevice(sc->dev);
14281
14282    /* get the chip revision (chip metal comes from pci config space) */
14283    sc->devinfo.chip_id     =
14284    sc->link_params.chip_id =
14285        (((REG_RD(sc, MISC_REG_CHIP_NUM)                   & 0xffff) << 16) |
14286         ((REG_RD(sc, MISC_REG_CHIP_REV)                   & 0xf)    << 12) |
14287         (((REG_RD(sc, PCICFG_OFFSET + PCI_ID_VAL3) >> 24) & 0xf)    << 4)  |
14288         ((REG_RD(sc, MISC_REG_BOND_ID)                    & 0xf)    << 0));
14289
14290    /* force 57811 according to MISC register */
14291    if (REG_RD(sc, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
14292        if (CHIP_IS_57810(sc)) {
14293            sc->devinfo.chip_id = ((CHIP_NUM_57811 << 16) |
14294                                   (sc->devinfo.chip_id & 0x0000ffff));
14295        } else if (CHIP_IS_57810_MF(sc)) {
14296            sc->devinfo.chip_id = ((CHIP_NUM_57811_MF << 16) |
14297                                   (sc->devinfo.chip_id & 0x0000ffff));
14298        }
14299        sc->devinfo.chip_id |= 0x1;
14300    }
14301
14302    BLOGD(sc, DBG_LOAD,
14303          "chip_id=0x%08x (num=0x%04x rev=0x%01x metal=0x%02x bond=0x%01x)\n",
14304          sc->devinfo.chip_id,
14305          ((sc->devinfo.chip_id >> 16) & 0xffff),
14306          ((sc->devinfo.chip_id >> 12) & 0xf),
14307          ((sc->devinfo.chip_id >>  4) & 0xff),
14308          ((sc->devinfo.chip_id >>  0) & 0xf));
14309
14310    val = (REG_RD(sc, 0x2874) & 0x55);
14311    if ((sc->devinfo.chip_id & 0x1) ||
14312        (CHIP_IS_E1(sc) && val) ||
14313        (CHIP_IS_E1H(sc) && (val == 0x55))) {
14314        sc->flags |= BXE_ONE_PORT_FLAG;
14315        BLOGD(sc, DBG_LOAD, "single port device\n");
14316    }
14317
14318    /* set the doorbell size */
14319    sc->doorbell_size = (1 << BXE_DB_SHIFT);
14320
14321    /* determine whether the device is in 2 port or 4 port mode */
14322    sc->devinfo.chip_port_mode = CHIP_PORT_MODE_NONE; /* E1 & E1h*/
14323    if (CHIP_IS_E2E3(sc)) {
14324        /*
14325         * Read port4mode_en_ovwr[0]:
14326         *   If 1, four port mode is in port4mode_en_ovwr[1].
14327         *   If 0, four port mode is in port4mode_en[0].
14328         */
14329        val = REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR);
14330        if (val & 1) {
14331            val = ((val >> 1) & 1);
14332        } else {
14333            val = REG_RD(sc, MISC_REG_PORT4MODE_EN);
14334        }
14335
14336        sc->devinfo.chip_port_mode =
14337            (val) ? CHIP_4_PORT_MODE : CHIP_2_PORT_MODE;
14338
14339        BLOGD(sc, DBG_LOAD, "Port mode = %s\n", (val) ? "4" : "2");
14340    }
14341
14342    /* get the function and path info for the device */
14343    bxe_get_function_num(sc);
14344
14345    /* get the shared memory base address */
14346    sc->devinfo.shmem_base     =
14347    sc->link_params.shmem_base =
14348        REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
14349    sc->devinfo.shmem2_base =
14350        REG_RD(sc, (SC_PATH(sc) ? MISC_REG_GENERIC_CR_1 :
14351                                  MISC_REG_GENERIC_CR_0));
14352
14353    BLOGD(sc, DBG_LOAD, "shmem_base=0x%08x, shmem2_base=0x%08x\n",
14354          sc->devinfo.shmem_base, sc->devinfo.shmem2_base);
14355
14356    if (!sc->devinfo.shmem_base) {
14357        /* this should ONLY prevent upcoming shmem reads */
14358        BLOGI(sc, "MCP not active\n");
14359        sc->flags |= BXE_NO_MCP_FLAG;
14360        return (0);
14361    }
14362
14363    /* make sure the shared memory contents are valid */
14364    val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
14365    if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) !=
14366        (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) {
14367        BLOGE(sc, "Invalid SHMEM validity signature: 0x%08x\n", val);
14368        return (0);
14369    }
14370    BLOGD(sc, DBG_LOAD, "Valid SHMEM validity signature: 0x%08x\n", val);
14371
14372    /* get the bootcode version */
14373    sc->devinfo.bc_ver = SHMEM_RD(sc, dev_info.bc_rev);
14374    snprintf(sc->devinfo.bc_ver_str,
14375             sizeof(sc->devinfo.bc_ver_str),
14376             "%d.%d.%d",
14377             ((sc->devinfo.bc_ver >> 24) & 0xff),
14378             ((sc->devinfo.bc_ver >> 16) & 0xff),
14379             ((sc->devinfo.bc_ver >>  8) & 0xff));
14380    BLOGD(sc, DBG_LOAD, "Bootcode version: %s\n", sc->devinfo.bc_ver_str);
14381
14382    /* get the bootcode shmem address */
14383    sc->devinfo.mf_cfg_base = bxe_get_shmem_mf_cfg_base(sc);
14384    BLOGD(sc, DBG_LOAD, "mf_cfg_base=0x08%x \n", sc->devinfo.mf_cfg_base);
14385
14386    /* clean indirect addresses as they're not used */
14387    pci_write_config(sc->dev, PCICFG_GRC_ADDRESS, 0, 4);
14388    if (IS_PF(sc)) {
14389        REG_WR(sc, PXP2_REG_PGL_ADDR_88_F0, 0);
14390        REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F0, 0);
14391        REG_WR(sc, PXP2_REG_PGL_ADDR_90_F0, 0);
14392        REG_WR(sc, PXP2_REG_PGL_ADDR_94_F0, 0);
14393        if (CHIP_IS_E1x(sc)) {
14394            REG_WR(sc, PXP2_REG_PGL_ADDR_88_F1, 0);
14395            REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F1, 0);
14396            REG_WR(sc, PXP2_REG_PGL_ADDR_90_F1, 0);
14397            REG_WR(sc, PXP2_REG_PGL_ADDR_94_F1, 0);
14398        }
14399
14400        /*
14401         * Enable internal target-read (in case we are probed after PF
14402         * FLR). Must be done prior to any BAR read access. Only for
14403         * 57712 and up
14404         */
14405        if (!CHIP_IS_E1x(sc)) {
14406            REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
14407        }
14408    }
14409
14410    /* get the nvram size */
14411    val = REG_RD(sc, MCP_REG_MCPR_NVM_CFG4);
14412    sc->devinfo.flash_size =
14413        (NVRAM_1MB_SIZE << (val & MCPR_NVM_CFG4_FLASH_SIZE));
14414    BLOGD(sc, DBG_LOAD, "nvram flash size: %d\n", sc->devinfo.flash_size);
14415
14416    /* get PCI capabilites */
14417    bxe_probe_pci_caps(sc);
14418
14419    bxe_set_power_state(sc, PCI_PM_D0);
14420
14421    /* get various configuration parameters from shmem */
14422    bxe_get_shmem_info(sc);
14423
14424    if (sc->devinfo.pcie_msix_cap_reg != 0) {
14425        val = pci_read_config(sc->dev,
14426                              (sc->devinfo.pcie_msix_cap_reg +
14427                               PCIR_MSIX_CTRL),
14428                              2);
14429        sc->igu_sb_cnt = (val & PCIM_MSIXCTRL_TABLE_SIZE);
14430    } else {
14431        sc->igu_sb_cnt = 1;
14432    }
14433
14434    sc->igu_base_addr = BAR_IGU_INTMEM;
14435
14436    /* initialize IGU parameters */
14437    if (CHIP_IS_E1x(sc)) {
14438        sc->devinfo.int_block = INT_BLOCK_HC;
14439        sc->igu_dsb_id = DEF_SB_IGU_ID;
14440        sc->igu_base_sb = 0;
14441    } else {
14442        sc->devinfo.int_block = INT_BLOCK_IGU;
14443
14444        /* do not allow device reset during IGU info preocessing */
14445        bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
14446
14447        val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
14448
14449        if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
14450            int tout = 5000;
14451
14452            BLOGD(sc, DBG_LOAD, "FORCING IGU Normal Mode\n");
14453
14454            val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
14455            REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION, val);
14456            REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x7f);
14457
14458            while (tout && REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
14459                tout--;
14460                DELAY(1000);
14461            }
14462
14463            if (REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
14464                BLOGD(sc, DBG_LOAD, "FORCING IGU Normal Mode failed!!!\n");
14465                bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
14466                return (-1);
14467            }
14468        }
14469
14470        if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
14471            BLOGD(sc, DBG_LOAD, "IGU Backward Compatible Mode\n");
14472            sc->devinfo.int_block |= INT_BLOCK_MODE_BW_COMP;
14473        } else {
14474            BLOGD(sc, DBG_LOAD, "IGU Normal Mode\n");
14475        }
14476
14477        rc = bxe_get_igu_cam_info(sc);
14478
14479        bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
14480
14481        if (rc) {
14482            return (rc);
14483        }
14484    }
14485
14486    /*
14487     * Get base FW non-default (fast path) status block ID. This value is
14488     * used to initialize the fw_sb_id saved on the fp/queue structure to
14489     * determine the id used by the FW.
14490     */
14491    if (CHIP_IS_E1x(sc)) {
14492        sc->base_fw_ndsb = ((SC_PORT(sc) * FP_SB_MAX_E1x) + SC_L_ID(sc));
14493    } else {
14494        /*
14495         * 57712+ - We currently use one FW SB per IGU SB (Rx and Tx of
14496         * the same queue are indicated on the same IGU SB). So we prefer
14497         * FW and IGU SBs to be the same value.
14498         */
14499        sc->base_fw_ndsb = sc->igu_base_sb;
14500    }
14501
14502    BLOGD(sc, DBG_LOAD,
14503          "igu_dsb_id=%d igu_base_sb=%d igu_sb_cnt=%d base_fw_ndsb=%d\n",
14504          sc->igu_dsb_id, sc->igu_base_sb,
14505          sc->igu_sb_cnt, sc->base_fw_ndsb);
14506
14507    elink_phy_probe(&sc->link_params);
14508
14509    return (0);
14510}
14511
14512static void
14513bxe_link_settings_supported(struct bxe_softc *sc,
14514                            uint32_t         switch_cfg)
14515{
14516    uint32_t cfg_size = 0;
14517    uint32_t idx;
14518    uint8_t port = SC_PORT(sc);
14519
14520    /* aggregation of supported attributes of all external phys */
14521    sc->port.supported[0] = 0;
14522    sc->port.supported[1] = 0;
14523
14524    switch (sc->link_params.num_phys) {
14525    case 1:
14526        sc->port.supported[0] = sc->link_params.phy[ELINK_INT_PHY].supported;
14527        cfg_size = 1;
14528        break;
14529    case 2:
14530        sc->port.supported[0] = sc->link_params.phy[ELINK_EXT_PHY1].supported;
14531        cfg_size = 1;
14532        break;
14533    case 3:
14534        if (sc->link_params.multi_phy_config &
14535            PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
14536            sc->port.supported[1] =
14537                sc->link_params.phy[ELINK_EXT_PHY1].supported;
14538            sc->port.supported[0] =
14539                sc->link_params.phy[ELINK_EXT_PHY2].supported;
14540        } else {
14541            sc->port.supported[0] =
14542                sc->link_params.phy[ELINK_EXT_PHY1].supported;
14543            sc->port.supported[1] =
14544                sc->link_params.phy[ELINK_EXT_PHY2].supported;
14545        }
14546        cfg_size = 2;
14547        break;
14548    }
14549
14550    if (!(sc->port.supported[0] || sc->port.supported[1])) {
14551        BLOGE(sc, "Invalid phy config in NVRAM (PHY1=0x%08x PHY2=0x%08x)\n",
14552              SHMEM_RD(sc,
14553                       dev_info.port_hw_config[port].external_phy_config),
14554              SHMEM_RD(sc,
14555                       dev_info.port_hw_config[port].external_phy_config2));
14556        return;
14557    }
14558
14559    if (CHIP_IS_E3(sc))
14560        sc->port.phy_addr = REG_RD(sc, MISC_REG_WC0_CTRL_PHY_ADDR);
14561    else {
14562        switch (switch_cfg) {
14563        case ELINK_SWITCH_CFG_1G:
14564            sc->port.phy_addr =
14565                REG_RD(sc, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
14566            break;
14567        case ELINK_SWITCH_CFG_10G:
14568            sc->port.phy_addr =
14569                REG_RD(sc, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
14570            break;
14571        default:
14572            BLOGE(sc, "Invalid switch config in link_config=0x%08x\n",
14573                  sc->port.link_config[0]);
14574            return;
14575        }
14576    }
14577
14578    BLOGD(sc, DBG_LOAD, "PHY addr 0x%08x\n", sc->port.phy_addr);
14579
14580    /* mask what we support according to speed_cap_mask per configuration */
14581    for (idx = 0; idx < cfg_size; idx++) {
14582        if (!(sc->link_params.speed_cap_mask[idx] &
14583              PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) {
14584            sc->port.supported[idx] &= ~ELINK_SUPPORTED_10baseT_Half;
14585        }
14586
14587        if (!(sc->link_params.speed_cap_mask[idx] &
14588              PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) {
14589            sc->port.supported[idx] &= ~ELINK_SUPPORTED_10baseT_Full;
14590        }
14591
14592        if (!(sc->link_params.speed_cap_mask[idx] &
14593              PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) {
14594            sc->port.supported[idx] &= ~ELINK_SUPPORTED_100baseT_Half;
14595        }
14596
14597        if (!(sc->link_params.speed_cap_mask[idx] &
14598              PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) {
14599            sc->port.supported[idx] &= ~ELINK_SUPPORTED_100baseT_Full;
14600        }
14601
14602        if (!(sc->link_params.speed_cap_mask[idx] &
14603              PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) {
14604            sc->port.supported[idx] &= ~ELINK_SUPPORTED_1000baseT_Full;
14605        }
14606
14607        if (!(sc->link_params.speed_cap_mask[idx] &
14608              PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) {
14609            sc->port.supported[idx] &= ~ELINK_SUPPORTED_2500baseX_Full;
14610        }
14611
14612        if (!(sc->link_params.speed_cap_mask[idx] &
14613              PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
14614            sc->port.supported[idx] &= ~ELINK_SUPPORTED_10000baseT_Full;
14615        }
14616
14617        if (!(sc->link_params.speed_cap_mask[idx] &
14618              PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) {
14619            sc->port.supported[idx] &= ~ELINK_SUPPORTED_20000baseKR2_Full;
14620        }
14621    }
14622
14623    BLOGD(sc, DBG_LOAD, "PHY supported 0=0x%08x 1=0x%08x\n",
14624          sc->port.supported[0], sc->port.supported[1]);
14625}
14626
14627static void
14628bxe_link_settings_requested(struct bxe_softc *sc)
14629{
14630    uint32_t link_config;
14631    uint32_t idx;
14632    uint32_t cfg_size = 0;
14633
14634    sc->port.advertising[0] = 0;
14635    sc->port.advertising[1] = 0;
14636
14637    switch (sc->link_params.num_phys) {
14638    case 1:
14639    case 2:
14640        cfg_size = 1;
14641        break;
14642    case 3:
14643        cfg_size = 2;
14644        break;
14645    }
14646
14647    for (idx = 0; idx < cfg_size; idx++) {
14648        sc->link_params.req_duplex[idx] = DUPLEX_FULL;
14649        link_config = sc->port.link_config[idx];
14650
14651        switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
14652        case PORT_FEATURE_LINK_SPEED_AUTO:
14653            if (sc->port.supported[idx] & ELINK_SUPPORTED_Autoneg) {
14654                sc->link_params.req_line_speed[idx] = ELINK_SPEED_AUTO_NEG;
14655                sc->port.advertising[idx] |= sc->port.supported[idx];
14656                if (sc->link_params.phy[ELINK_EXT_PHY1].type ==
14657                    PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
14658                    sc->port.advertising[idx] |=
14659                        (ELINK_SUPPORTED_100baseT_Half |
14660                         ELINK_SUPPORTED_100baseT_Full);
14661            } else {
14662                /* force 10G, no AN */
14663                sc->link_params.req_line_speed[idx] = ELINK_SPEED_10000;
14664                sc->port.advertising[idx] |=
14665                    (ADVERTISED_10000baseT_Full | ADVERTISED_FIBRE);
14666                continue;
14667            }
14668            break;
14669
14670        case PORT_FEATURE_LINK_SPEED_10M_FULL:
14671            if (sc->port.supported[idx] & ELINK_SUPPORTED_10baseT_Full) {
14672                sc->link_params.req_line_speed[idx] = ELINK_SPEED_10;
14673                sc->port.advertising[idx] |= (ADVERTISED_10baseT_Full |
14674                                              ADVERTISED_TP);
14675            } else {
14676                BLOGE(sc, "Invalid NVRAM config link_config=0x%08x "
14677                          "speed_cap_mask=0x%08x\n",
14678                      link_config, sc->link_params.speed_cap_mask[idx]);
14679                return;
14680            }
14681            break;
14682
14683        case PORT_FEATURE_LINK_SPEED_10M_HALF:
14684            if (sc->port.supported[idx] & ELINK_SUPPORTED_10baseT_Half) {
14685                sc->link_params.req_line_speed[idx] = ELINK_SPEED_10;
14686                sc->link_params.req_duplex[idx] = DUPLEX_HALF;
14687                sc->port.advertising[idx] |= (ADVERTISED_10baseT_Half |
14688                                              ADVERTISED_TP);
14689            } else {
14690                BLOGE(sc, "Invalid NVRAM config link_config=0x%08x "
14691                          "speed_cap_mask=0x%08x\n",
14692                      link_config, sc->link_params.speed_cap_mask[idx]);
14693                return;
14694            }
14695            break;
14696
14697        case PORT_FEATURE_LINK_SPEED_100M_FULL:
14698            if (sc->port.supported[idx] & ELINK_SUPPORTED_100baseT_Full) {
14699                sc->link_params.req_line_speed[idx] = ELINK_SPEED_100;
14700                sc->port.advertising[idx] |= (ADVERTISED_100baseT_Full |
14701                                              ADVERTISED_TP);
14702            } else {
14703                BLOGE(sc, "Invalid NVRAM config link_config=0x%08x "
14704                          "speed_cap_mask=0x%08x\n",
14705                      link_config, sc->link_params.speed_cap_mask[idx]);
14706                return;
14707            }
14708            break;
14709
14710        case PORT_FEATURE_LINK_SPEED_100M_HALF:
14711            if (sc->port.supported[idx] & ELINK_SUPPORTED_100baseT_Half) {
14712                sc->link_params.req_line_speed[idx] = ELINK_SPEED_100;
14713                sc->link_params.req_duplex[idx] = DUPLEX_HALF;
14714                sc->port.advertising[idx] |= (ADVERTISED_100baseT_Half |
14715                                              ADVERTISED_TP);
14716            } else {
14717                BLOGE(sc, "Invalid NVRAM config link_config=0x%08x "
14718                          "speed_cap_mask=0x%08x\n",
14719                      link_config, sc->link_params.speed_cap_mask[idx]);
14720                return;
14721            }
14722            break;
14723
14724        case PORT_FEATURE_LINK_SPEED_1G:
14725            if (sc->port.supported[idx] & ELINK_SUPPORTED_1000baseT_Full) {
14726                sc->link_params.req_line_speed[idx] = ELINK_SPEED_1000;
14727                sc->port.advertising[idx] |= (ADVERTISED_1000baseT_Full |
14728                                              ADVERTISED_TP);
14729            } else {
14730                BLOGE(sc, "Invalid NVRAM config link_config=0x%08x "
14731                          "speed_cap_mask=0x%08x\n",
14732                      link_config, sc->link_params.speed_cap_mask[idx]);
14733                return;
14734            }
14735            break;
14736
14737        case PORT_FEATURE_LINK_SPEED_2_5G:
14738            if (sc->port.supported[idx] & ELINK_SUPPORTED_2500baseX_Full) {
14739                sc->link_params.req_line_speed[idx] = ELINK_SPEED_2500;
14740                sc->port.advertising[idx] |= (ADVERTISED_2500baseX_Full |
14741                                              ADVERTISED_TP);
14742            } else {
14743                BLOGE(sc, "Invalid NVRAM config link_config=0x%08x "
14744                          "speed_cap_mask=0x%08x\n",
14745                      link_config, sc->link_params.speed_cap_mask[idx]);
14746                return;
14747            }
14748            break;
14749
14750        case PORT_FEATURE_LINK_SPEED_10G_CX4:
14751            if (sc->port.supported[idx] & ELINK_SUPPORTED_10000baseT_Full) {
14752                sc->link_params.req_line_speed[idx] = ELINK_SPEED_10000;
14753                sc->port.advertising[idx] |= (ADVERTISED_10000baseT_Full |
14754                                              ADVERTISED_FIBRE);
14755            } else {
14756                BLOGE(sc, "Invalid NVRAM config link_config=0x%08x "
14757                          "speed_cap_mask=0x%08x\n",
14758                      link_config, sc->link_params.speed_cap_mask[idx]);
14759                return;
14760            }
14761            break;
14762
14763        case PORT_FEATURE_LINK_SPEED_20G:
14764            sc->link_params.req_line_speed[idx] = ELINK_SPEED_20000;
14765            break;
14766
14767        default:
14768            BLOGE(sc, "Invalid NVRAM config link_config=0x%08x "
14769                      "speed_cap_mask=0x%08x\n",
14770                  link_config, sc->link_params.speed_cap_mask[idx]);
14771            sc->link_params.req_line_speed[idx] = ELINK_SPEED_AUTO_NEG;
14772            sc->port.advertising[idx] = sc->port.supported[idx];
14773            break;
14774        }
14775
14776        sc->link_params.req_flow_ctrl[idx] =
14777            (link_config & PORT_FEATURE_FLOW_CONTROL_MASK);
14778
14779        if (sc->link_params.req_flow_ctrl[idx] == ELINK_FLOW_CTRL_AUTO) {
14780            if (!(sc->port.supported[idx] & ELINK_SUPPORTED_Autoneg)) {
14781                sc->link_params.req_flow_ctrl[idx] = ELINK_FLOW_CTRL_NONE;
14782            } else {
14783                bxe_set_requested_fc(sc);
14784            }
14785        }
14786
14787        BLOGD(sc, DBG_LOAD, "req_line_speed=%d req_duplex=%d "
14788                            "req_flow_ctrl=0x%x advertising=0x%x\n",
14789              sc->link_params.req_line_speed[idx],
14790              sc->link_params.req_duplex[idx],
14791              sc->link_params.req_flow_ctrl[idx],
14792              sc->port.advertising[idx]);
14793    }
14794}
14795
14796static void
14797bxe_get_phy_info(struct bxe_softc *sc)
14798{
14799    uint8_t port = SC_PORT(sc);
14800    uint32_t config = sc->port.config;
14801    uint32_t eee_mode;
14802
14803    /* shmem data already read in bxe_get_shmem_info() */
14804
14805    BLOGD(sc, DBG_LOAD, "lane_config=0x%08x speed_cap_mask0=0x%08x "
14806                        "link_config0=0x%08x\n",
14807               sc->link_params.lane_config,
14808               sc->link_params.speed_cap_mask[0],
14809               sc->port.link_config[0]);
14810
14811    bxe_link_settings_supported(sc, sc->link_params.switch_cfg);
14812    bxe_link_settings_requested(sc);
14813
14814    if (sc->autogreeen == AUTO_GREEN_FORCE_ON) {
14815        sc->link_params.feature_config_flags |=
14816            ELINK_FEATURE_CONFIG_AUTOGREEEN_ENABLED;
14817    } else if (sc->autogreeen == AUTO_GREEN_FORCE_OFF) {
14818        sc->link_params.feature_config_flags &=
14819            ~ELINK_FEATURE_CONFIG_AUTOGREEEN_ENABLED;
14820    } else if (config & PORT_FEAT_CFG_AUTOGREEEN_ENABLED) {
14821        sc->link_params.feature_config_flags |=
14822            ELINK_FEATURE_CONFIG_AUTOGREEEN_ENABLED;
14823    }
14824
14825    /* configure link feature according to nvram value */
14826    eee_mode =
14827        (((SHMEM_RD(sc, dev_info.port_feature_config[port].eee_power_mode)) &
14828          PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
14829         PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
14830    if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
14831        sc->link_params.eee_mode = (ELINK_EEE_MODE_ADV_LPI |
14832                                    ELINK_EEE_MODE_ENABLE_LPI |
14833                                    ELINK_EEE_MODE_OUTPUT_TIME);
14834    } else {
14835        sc->link_params.eee_mode = 0;
14836    }
14837
14838    /* get the media type */
14839    bxe_media_detect(sc);
14840}
14841
14842static void
14843bxe_get_params(struct bxe_softc *sc)
14844{
14845    /* get user tunable params */
14846    bxe_get_tunable_params(sc);
14847
14848    /* select the RX and TX ring sizes */
14849    sc->tx_ring_size = TX_BD_USABLE;
14850    sc->rx_ring_size = RX_BD_USABLE;
14851
14852    /* XXX disable WoL */
14853    sc->wol = 0;
14854}
14855
14856static void
14857bxe_set_modes_bitmap(struct bxe_softc *sc)
14858{
14859    uint32_t flags = 0;
14860
14861    if (CHIP_REV_IS_FPGA(sc)) {
14862        SET_FLAGS(flags, MODE_FPGA);
14863    } else if (CHIP_REV_IS_EMUL(sc)) {
14864        SET_FLAGS(flags, MODE_EMUL);
14865    } else {
14866        SET_FLAGS(flags, MODE_ASIC);
14867    }
14868
14869    if (CHIP_IS_MODE_4_PORT(sc)) {
14870        SET_FLAGS(flags, MODE_PORT4);
14871    } else {
14872        SET_FLAGS(flags, MODE_PORT2);
14873    }
14874
14875    if (CHIP_IS_E2(sc)) {
14876        SET_FLAGS(flags, MODE_E2);
14877    } else if (CHIP_IS_E3(sc)) {
14878        SET_FLAGS(flags, MODE_E3);
14879        if (CHIP_REV(sc) == CHIP_REV_Ax) {
14880            SET_FLAGS(flags, MODE_E3_A0);
14881        } else /*if (CHIP_REV(sc) == CHIP_REV_Bx)*/ {
14882            SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
14883        }
14884    }
14885
14886    if (IS_MF(sc)) {
14887        SET_FLAGS(flags, MODE_MF);
14888        switch (sc->devinfo.mf_info.mf_mode) {
14889        case MULTI_FUNCTION_SD:
14890            SET_FLAGS(flags, MODE_MF_SD);
14891            break;
14892        case MULTI_FUNCTION_SI:
14893            SET_FLAGS(flags, MODE_MF_SI);
14894            break;
14895        case MULTI_FUNCTION_AFEX:
14896            SET_FLAGS(flags, MODE_MF_AFEX);
14897            break;
14898        }
14899    } else {
14900        SET_FLAGS(flags, MODE_SF);
14901    }
14902
14903#if defined(__LITTLE_ENDIAN)
14904    SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
14905#else /* __BIG_ENDIAN */
14906    SET_FLAGS(flags, MODE_BIG_ENDIAN);
14907#endif
14908
14909    INIT_MODE_FLAGS(sc) = flags;
14910}
14911
14912static int
14913bxe_alloc_hsi_mem(struct bxe_softc *sc)
14914{
14915    struct bxe_fastpath *fp;
14916    bus_addr_t busaddr;
14917    int max_agg_queues;
14918    int max_segments;
14919    bus_size_t max_size;
14920    bus_size_t max_seg_size;
14921    char buf[32];
14922    int rc;
14923    int i, j;
14924
14925    /* XXX zero out all vars here and call bxe_alloc_hsi_mem on error */
14926
14927    /* allocate the parent bus DMA tag */
14928    rc = bus_dma_tag_create(bus_get_dma_tag(sc->dev), /* parent tag */
14929                            1,                        /* alignment */
14930                            0,                        /* boundary limit */
14931                            BUS_SPACE_MAXADDR,        /* restricted low */
14932                            BUS_SPACE_MAXADDR,        /* restricted hi */
14933                            NULL,                     /* addr filter() */
14934                            NULL,                     /* addr filter() arg */
14935                            BUS_SPACE_MAXSIZE_32BIT,  /* max map size */
14936                            BUS_SPACE_UNRESTRICTED,   /* num discontinuous */
14937                            BUS_SPACE_MAXSIZE_32BIT,  /* max seg size */
14938                            0,                        /* flags */
14939                            NULL,                     /* lock() */
14940                            NULL,                     /* lock() arg */
14941                            &sc->parent_dma_tag);     /* returned dma tag */
14942    if (rc != 0) {
14943        BLOGE(sc, "Failed to alloc parent DMA tag (%d)!\n", rc);
14944        return (1);
14945    }
14946
14947    /************************/
14948    /* DEFAULT STATUS BLOCK */
14949    /************************/
14950
14951    if (bxe_dma_alloc(sc, sizeof(struct host_sp_status_block),
14952                      &sc->def_sb_dma, "default status block") != 0) {
14953        /* XXX */
14954        bus_dma_tag_destroy(sc->parent_dma_tag);
14955        return (1);
14956    }
14957
14958    sc->def_sb = (struct host_sp_status_block *)sc->def_sb_dma.vaddr;
14959
14960    /***************/
14961    /* EVENT QUEUE */
14962    /***************/
14963
14964    if (bxe_dma_alloc(sc, BCM_PAGE_SIZE,
14965                      &sc->eq_dma, "event queue") != 0) {
14966        /* XXX */
14967        bxe_dma_free(sc, &sc->def_sb_dma);
14968        sc->def_sb = NULL;
14969        bus_dma_tag_destroy(sc->parent_dma_tag);
14970        return (1);
14971    }
14972
14973    sc->eq = (union event_ring_elem * )sc->eq_dma.vaddr;
14974
14975    /*************/
14976    /* SLOW PATH */
14977    /*************/
14978
14979    if (bxe_dma_alloc(sc, sizeof(struct bxe_slowpath),
14980                      &sc->sp_dma, "slow path") != 0) {
14981        /* XXX */
14982        bxe_dma_free(sc, &sc->eq_dma);
14983        sc->eq = NULL;
14984        bxe_dma_free(sc, &sc->def_sb_dma);
14985        sc->def_sb = NULL;
14986        bus_dma_tag_destroy(sc->parent_dma_tag);
14987        return (1);
14988    }
14989
14990    sc->sp = (struct bxe_slowpath *)sc->sp_dma.vaddr;
14991
14992    /*******************/
14993    /* SLOW PATH QUEUE */
14994    /*******************/
14995
14996    if (bxe_dma_alloc(sc, BCM_PAGE_SIZE,
14997                      &sc->spq_dma, "slow path queue") != 0) {
14998        /* XXX */
14999        bxe_dma_free(sc, &sc->sp_dma);
15000        sc->sp = NULL;
15001        bxe_dma_free(sc, &sc->eq_dma);
15002        sc->eq = NULL;
15003        bxe_dma_free(sc, &sc->def_sb_dma);
15004        sc->def_sb = NULL;
15005        bus_dma_tag_destroy(sc->parent_dma_tag);
15006        return (1);
15007    }
15008
15009    sc->spq = (struct eth_spe *)sc->spq_dma.vaddr;
15010
15011    /***************************/
15012    /* FW DECOMPRESSION BUFFER */
15013    /***************************/
15014
15015    if (bxe_dma_alloc(sc, FW_BUF_SIZE, &sc->gz_buf_dma,
15016                      "fw decompression buffer") != 0) {
15017        /* XXX */
15018        bxe_dma_free(sc, &sc->spq_dma);
15019        sc->spq = NULL;
15020        bxe_dma_free(sc, &sc->sp_dma);
15021        sc->sp = NULL;
15022        bxe_dma_free(sc, &sc->eq_dma);
15023        sc->eq = NULL;
15024        bxe_dma_free(sc, &sc->def_sb_dma);
15025        sc->def_sb = NULL;
15026        bus_dma_tag_destroy(sc->parent_dma_tag);
15027        return (1);
15028    }
15029
15030    sc->gz_buf = (void *)sc->gz_buf_dma.vaddr;
15031
15032    if ((sc->gz_strm =
15033         malloc(sizeof(*sc->gz_strm), M_DEVBUF, M_NOWAIT)) == NULL) {
15034        /* XXX */
15035        bxe_dma_free(sc, &sc->gz_buf_dma);
15036        sc->gz_buf = NULL;
15037        bxe_dma_free(sc, &sc->spq_dma);
15038        sc->spq = NULL;
15039        bxe_dma_free(sc, &sc->sp_dma);
15040        sc->sp = NULL;
15041        bxe_dma_free(sc, &sc->eq_dma);
15042        sc->eq = NULL;
15043        bxe_dma_free(sc, &sc->def_sb_dma);
15044        sc->def_sb = NULL;
15045        bus_dma_tag_destroy(sc->parent_dma_tag);
15046        return (1);
15047    }
15048
15049    /*************/
15050    /* FASTPATHS */
15051    /*************/
15052
15053    /* allocate DMA memory for each fastpath structure */
15054    for (i = 0; i < sc->num_queues; i++) {
15055        fp = &sc->fp[i];
15056        fp->sc    = sc;
15057        fp->index = i;
15058
15059        /*******************/
15060        /* FP STATUS BLOCK */
15061        /*******************/
15062
15063        snprintf(buf, sizeof(buf), "fp %d status block", i);
15064        if (bxe_dma_alloc(sc, sizeof(union bxe_host_hc_status_block),
15065                          &fp->sb_dma, buf) != 0) {
15066            /* XXX unwind and free previous fastpath allocations */
15067            BLOGE(sc, "Failed to alloc %s\n", buf);
15068            return (1);
15069        } else {
15070            if (CHIP_IS_E2E3(sc)) {
15071                fp->status_block.e2_sb =
15072                    (struct host_hc_status_block_e2 *)fp->sb_dma.vaddr;
15073            } else {
15074                fp->status_block.e1x_sb =
15075                    (struct host_hc_status_block_e1x *)fp->sb_dma.vaddr;
15076            }
15077        }
15078
15079        /******************/
15080        /* FP TX BD CHAIN */
15081        /******************/
15082
15083        snprintf(buf, sizeof(buf), "fp %d tx bd chain", i);
15084        if (bxe_dma_alloc(sc, (BCM_PAGE_SIZE * TX_BD_NUM_PAGES),
15085                          &fp->tx_dma, buf) != 0) {
15086            /* XXX unwind and free previous fastpath allocations */
15087            BLOGE(sc, "Failed to alloc %s\n", buf);
15088            return (1);
15089        } else {
15090            fp->tx_chain = (union eth_tx_bd_types *)fp->tx_dma.vaddr;
15091        }
15092
15093        /* link together the tx bd chain pages */
15094        for (j = 1; j <= TX_BD_NUM_PAGES; j++) {
15095            /* index into the tx bd chain array to last entry per page */
15096            struct eth_tx_next_bd *tx_next_bd =
15097                &fp->tx_chain[TX_BD_TOTAL_PER_PAGE * j - 1].next_bd;
15098            /* point to the next page and wrap from last page */
15099            busaddr = (fp->tx_dma.paddr +
15100                       (BCM_PAGE_SIZE * (j % TX_BD_NUM_PAGES)));
15101            tx_next_bd->addr_hi = htole32(U64_HI(busaddr));
15102            tx_next_bd->addr_lo = htole32(U64_LO(busaddr));
15103        }
15104
15105        /******************/
15106        /* FP RX BD CHAIN */
15107        /******************/
15108
15109        snprintf(buf, sizeof(buf), "fp %d rx bd chain", i);
15110        if (bxe_dma_alloc(sc, (BCM_PAGE_SIZE * RX_BD_NUM_PAGES),
15111                          &fp->rx_dma, buf) != 0) {
15112            /* XXX unwind and free previous fastpath allocations */
15113            BLOGE(sc, "Failed to alloc %s\n", buf);
15114            return (1);
15115        } else {
15116            fp->rx_chain = (struct eth_rx_bd *)fp->rx_dma.vaddr;
15117        }
15118
15119        /* link together the rx bd chain pages */
15120        for (j = 1; j <= RX_BD_NUM_PAGES; j++) {
15121            /* index into the rx bd chain array to last entry per page */
15122            struct eth_rx_bd *rx_bd =
15123                &fp->rx_chain[RX_BD_TOTAL_PER_PAGE * j - 2];
15124            /* point to the next page and wrap from last page */
15125            busaddr = (fp->rx_dma.paddr +
15126                       (BCM_PAGE_SIZE * (j % RX_BD_NUM_PAGES)));
15127            rx_bd->addr_hi = htole32(U64_HI(busaddr));
15128            rx_bd->addr_lo = htole32(U64_LO(busaddr));
15129        }
15130
15131        /*******************/
15132        /* FP RX RCQ CHAIN */
15133        /*******************/
15134
15135        snprintf(buf, sizeof(buf), "fp %d rcq chain", i);
15136        if (bxe_dma_alloc(sc, (BCM_PAGE_SIZE * RCQ_NUM_PAGES),
15137                          &fp->rcq_dma, buf) != 0) {
15138            /* XXX unwind and free previous fastpath allocations */
15139            BLOGE(sc, "Failed to alloc %s\n", buf);
15140            return (1);
15141        } else {
15142            fp->rcq_chain = (union eth_rx_cqe *)fp->rcq_dma.vaddr;
15143        }
15144
15145        /* link together the rcq chain pages */
15146        for (j = 1; j <= RCQ_NUM_PAGES; j++) {
15147            /* index into the rcq chain array to last entry per page */
15148            struct eth_rx_cqe_next_page *rx_cqe_next =
15149                (struct eth_rx_cqe_next_page *)
15150                &fp->rcq_chain[RCQ_TOTAL_PER_PAGE * j - 1];
15151            /* point to the next page and wrap from last page */
15152            busaddr = (fp->rcq_dma.paddr +
15153                       (BCM_PAGE_SIZE * (j % RCQ_NUM_PAGES)));
15154            rx_cqe_next->addr_hi = htole32(U64_HI(busaddr));
15155            rx_cqe_next->addr_lo = htole32(U64_LO(busaddr));
15156        }
15157
15158        /*******************/
15159        /* FP RX SGE CHAIN */
15160        /*******************/
15161
15162        snprintf(buf, sizeof(buf), "fp %d sge chain", i);
15163        if (bxe_dma_alloc(sc, (BCM_PAGE_SIZE * RX_SGE_NUM_PAGES),
15164                          &fp->rx_sge_dma, buf) != 0) {
15165            /* XXX unwind and free previous fastpath allocations */
15166            BLOGE(sc, "Failed to alloc %s\n", buf);
15167            return (1);
15168        } else {
15169            fp->rx_sge_chain = (struct eth_rx_sge *)fp->rx_sge_dma.vaddr;
15170        }
15171
15172        /* link together the sge chain pages */
15173        for (j = 1; j <= RX_SGE_NUM_PAGES; j++) {
15174            /* index into the rcq chain array to last entry per page */
15175            struct eth_rx_sge *rx_sge =
15176                &fp->rx_sge_chain[RX_SGE_TOTAL_PER_PAGE * j - 2];
15177            /* point to the next page and wrap from last page */
15178            busaddr = (fp->rx_sge_dma.paddr +
15179                       (BCM_PAGE_SIZE * (j % RX_SGE_NUM_PAGES)));
15180            rx_sge->addr_hi = htole32(U64_HI(busaddr));
15181            rx_sge->addr_lo = htole32(U64_LO(busaddr));
15182        }
15183
15184        /***********************/
15185        /* FP TX MBUF DMA MAPS */
15186        /***********************/
15187
15188        /* set required sizes before mapping to conserve resources */
15189        if (if_getcapenable(sc->ifp) & (IFCAP_TSO4 | IFCAP_TSO6)) {
15190            max_size     = BXE_TSO_MAX_SIZE;
15191            max_segments = BXE_TSO_MAX_SEGMENTS;
15192            max_seg_size = BXE_TSO_MAX_SEG_SIZE;
15193        } else {
15194            max_size     = (MCLBYTES * BXE_MAX_SEGMENTS);
15195            max_segments = BXE_MAX_SEGMENTS;
15196            max_seg_size = MCLBYTES;
15197        }
15198
15199        /* create a dma tag for the tx mbufs */
15200        rc = bus_dma_tag_create(sc->parent_dma_tag, /* parent tag */
15201                                1,                  /* alignment */
15202                                0,                  /* boundary limit */
15203                                BUS_SPACE_MAXADDR,  /* restricted low */
15204                                BUS_SPACE_MAXADDR,  /* restricted hi */
15205                                NULL,               /* addr filter() */
15206                                NULL,               /* addr filter() arg */
15207                                max_size,           /* max map size */
15208                                max_segments,       /* num discontinuous */
15209                                max_seg_size,       /* max seg size */
15210                                0,                  /* flags */
15211                                NULL,               /* lock() */
15212                                NULL,               /* lock() arg */
15213                                &fp->tx_mbuf_tag);  /* returned dma tag */
15214        if (rc != 0) {
15215            /* XXX unwind and free previous fastpath allocations */
15216            BLOGE(sc, "Failed to create dma tag for "
15217                      "'fp %d tx mbufs' (%d)\n",
15218                  i, rc);
15219            return (1);
15220        }
15221
15222        /* create dma maps for each of the tx mbuf clusters */
15223        for (j = 0; j < TX_BD_TOTAL; j++) {
15224            if (bus_dmamap_create(fp->tx_mbuf_tag,
15225                                  BUS_DMA_NOWAIT,
15226                                  &fp->tx_mbuf_chain[j].m_map)) {
15227                /* XXX unwind and free previous fastpath allocations */
15228                BLOGE(sc, "Failed to create dma map for "
15229                          "'fp %d tx mbuf %d' (%d)\n",
15230                      i, j, rc);
15231                return (1);
15232            }
15233        }
15234
15235        /***********************/
15236        /* FP RX MBUF DMA MAPS */
15237        /***********************/
15238
15239        /* create a dma tag for the rx mbufs */
15240        rc = bus_dma_tag_create(sc->parent_dma_tag, /* parent tag */
15241                                1,                  /* alignment */
15242                                0,                  /* boundary limit */
15243                                BUS_SPACE_MAXADDR,  /* restricted low */
15244                                BUS_SPACE_MAXADDR,  /* restricted hi */
15245                                NULL,               /* addr filter() */
15246                                NULL,               /* addr filter() arg */
15247                                MJUM9BYTES,         /* max map size */
15248                                1,                  /* num discontinuous */
15249                                MJUM9BYTES,         /* max seg size */
15250                                0,                  /* flags */
15251                                NULL,               /* lock() */
15252                                NULL,               /* lock() arg */
15253                                &fp->rx_mbuf_tag);  /* returned dma tag */
15254        if (rc != 0) {
15255            /* XXX unwind and free previous fastpath allocations */
15256            BLOGE(sc, "Failed to create dma tag for "
15257                      "'fp %d rx mbufs' (%d)\n",
15258                  i, rc);
15259            return (1);
15260        }
15261
15262        /* create dma maps for each of the rx mbuf clusters */
15263        for (j = 0; j < RX_BD_TOTAL; j++) {
15264            if (bus_dmamap_create(fp->rx_mbuf_tag,
15265                                  BUS_DMA_NOWAIT,
15266                                  &fp->rx_mbuf_chain[j].m_map)) {
15267                /* XXX unwind and free previous fastpath allocations */
15268                BLOGE(sc, "Failed to create dma map for "
15269                          "'fp %d rx mbuf %d' (%d)\n",
15270                      i, j, rc);
15271                return (1);
15272            }
15273        }
15274
15275        /* create dma map for the spare rx mbuf cluster */
15276        if (bus_dmamap_create(fp->rx_mbuf_tag,
15277                              BUS_DMA_NOWAIT,
15278                              &fp->rx_mbuf_spare_map)) {
15279            /* XXX unwind and free previous fastpath allocations */
15280            BLOGE(sc, "Failed to create dma map for "
15281                      "'fp %d spare rx mbuf' (%d)\n",
15282                  i, rc);
15283            return (1);
15284        }
15285
15286        /***************************/
15287        /* FP RX SGE MBUF DMA MAPS */
15288        /***************************/
15289
15290        /* create a dma tag for the rx sge mbufs */
15291        rc = bus_dma_tag_create(sc->parent_dma_tag, /* parent tag */
15292                                1,                  /* alignment */
15293                                0,                  /* boundary limit */
15294                                BUS_SPACE_MAXADDR,  /* restricted low */
15295                                BUS_SPACE_MAXADDR,  /* restricted hi */
15296                                NULL,               /* addr filter() */
15297                                NULL,               /* addr filter() arg */
15298                                BCM_PAGE_SIZE,      /* max map size */
15299                                1,                  /* num discontinuous */
15300                                BCM_PAGE_SIZE,      /* max seg size */
15301                                0,                  /* flags */
15302                                NULL,               /* lock() */
15303                                NULL,               /* lock() arg */
15304                                &fp->rx_sge_mbuf_tag); /* returned dma tag */
15305        if (rc != 0) {
15306            /* XXX unwind and free previous fastpath allocations */
15307            BLOGE(sc, "Failed to create dma tag for "
15308                      "'fp %d rx sge mbufs' (%d)\n",
15309                  i, rc);
15310            return (1);
15311        }
15312
15313        /* create dma maps for the rx sge mbuf clusters */
15314        for (j = 0; j < RX_SGE_TOTAL; j++) {
15315            if (bus_dmamap_create(fp->rx_sge_mbuf_tag,
15316                                  BUS_DMA_NOWAIT,
15317                                  &fp->rx_sge_mbuf_chain[j].m_map)) {
15318                /* XXX unwind and free previous fastpath allocations */
15319                BLOGE(sc, "Failed to create dma map for "
15320                          "'fp %d rx sge mbuf %d' (%d)\n",
15321                      i, j, rc);
15322                return (1);
15323            }
15324        }
15325
15326        /* create dma map for the spare rx sge mbuf cluster */
15327        if (bus_dmamap_create(fp->rx_sge_mbuf_tag,
15328                              BUS_DMA_NOWAIT,
15329                              &fp->rx_sge_mbuf_spare_map)) {
15330            /* XXX unwind and free previous fastpath allocations */
15331            BLOGE(sc, "Failed to create dma map for "
15332                      "'fp %d spare rx sge mbuf' (%d)\n",
15333                  i, rc);
15334            return (1);
15335        }
15336
15337        /***************************/
15338        /* FP RX TPA MBUF DMA MAPS */
15339        /***************************/
15340
15341        /* create dma maps for the rx tpa mbuf clusters */
15342        max_agg_queues = MAX_AGG_QS(sc);
15343
15344        for (j = 0; j < max_agg_queues; j++) {
15345            if (bus_dmamap_create(fp->rx_mbuf_tag,
15346                                  BUS_DMA_NOWAIT,
15347                                  &fp->rx_tpa_info[j].bd.m_map)) {
15348                /* XXX unwind and free previous fastpath allocations */
15349                BLOGE(sc, "Failed to create dma map for "
15350                          "'fp %d rx tpa mbuf %d' (%d)\n",
15351                      i, j, rc);
15352                return (1);
15353            }
15354        }
15355
15356        /* create dma map for the spare rx tpa mbuf cluster */
15357        if (bus_dmamap_create(fp->rx_mbuf_tag,
15358                              BUS_DMA_NOWAIT,
15359                              &fp->rx_tpa_info_mbuf_spare_map)) {
15360            /* XXX unwind and free previous fastpath allocations */
15361            BLOGE(sc, "Failed to create dma map for "
15362                      "'fp %d spare rx tpa mbuf' (%d)\n",
15363                  i, rc);
15364            return (1);
15365        }
15366
15367        bxe_init_sge_ring_bit_mask(fp);
15368    }
15369
15370    return (0);
15371}
15372
15373static void
15374bxe_free_hsi_mem(struct bxe_softc *sc)
15375{
15376    struct bxe_fastpath *fp;
15377    int max_agg_queues;
15378    int i, j;
15379
15380    if (sc->parent_dma_tag == NULL) {
15381        return; /* assume nothing was allocated */
15382    }
15383
15384    for (i = 0; i < sc->num_queues; i++) {
15385        fp = &sc->fp[i];
15386
15387        /*******************/
15388        /* FP STATUS BLOCK */
15389        /*******************/
15390
15391        bxe_dma_free(sc, &fp->sb_dma);
15392        memset(&fp->status_block, 0, sizeof(fp->status_block));
15393
15394        /******************/
15395        /* FP TX BD CHAIN */
15396        /******************/
15397
15398        bxe_dma_free(sc, &fp->tx_dma);
15399        fp->tx_chain = NULL;
15400
15401        /******************/
15402        /* FP RX BD CHAIN */
15403        /******************/
15404
15405        bxe_dma_free(sc, &fp->rx_dma);
15406        fp->rx_chain = NULL;
15407
15408        /*******************/
15409        /* FP RX RCQ CHAIN */
15410        /*******************/
15411
15412        bxe_dma_free(sc, &fp->rcq_dma);
15413        fp->rcq_chain = NULL;
15414
15415        /*******************/
15416        /* FP RX SGE CHAIN */
15417        /*******************/
15418
15419        bxe_dma_free(sc, &fp->rx_sge_dma);
15420        fp->rx_sge_chain = NULL;
15421
15422        /***********************/
15423        /* FP TX MBUF DMA MAPS */
15424        /***********************/
15425
15426        if (fp->tx_mbuf_tag != NULL) {
15427            for (j = 0; j < TX_BD_TOTAL; j++) {
15428                if (fp->tx_mbuf_chain[j].m_map != NULL) {
15429                    bus_dmamap_unload(fp->tx_mbuf_tag,
15430                                      fp->tx_mbuf_chain[j].m_map);
15431                    bus_dmamap_destroy(fp->tx_mbuf_tag,
15432                                       fp->tx_mbuf_chain[j].m_map);
15433                }
15434            }
15435
15436            bus_dma_tag_destroy(fp->tx_mbuf_tag);
15437            fp->tx_mbuf_tag = NULL;
15438        }
15439
15440        /***********************/
15441        /* FP RX MBUF DMA MAPS */
15442        /***********************/
15443
15444        if (fp->rx_mbuf_tag != NULL) {
15445            for (j = 0; j < RX_BD_TOTAL; j++) {
15446                if (fp->rx_mbuf_chain[j].m_map != NULL) {
15447                    bus_dmamap_unload(fp->rx_mbuf_tag,
15448                                      fp->rx_mbuf_chain[j].m_map);
15449                    bus_dmamap_destroy(fp->rx_mbuf_tag,
15450                                       fp->rx_mbuf_chain[j].m_map);
15451                }
15452            }
15453
15454            if (fp->rx_mbuf_spare_map != NULL) {
15455                bus_dmamap_unload(fp->rx_mbuf_tag, fp->rx_mbuf_spare_map);
15456                bus_dmamap_destroy(fp->rx_mbuf_tag, fp->rx_mbuf_spare_map);
15457            }
15458
15459            /***************************/
15460            /* FP RX TPA MBUF DMA MAPS */
15461            /***************************/
15462
15463            max_agg_queues = MAX_AGG_QS(sc);
15464
15465            for (j = 0; j < max_agg_queues; j++) {
15466                if (fp->rx_tpa_info[j].bd.m_map != NULL) {
15467                    bus_dmamap_unload(fp->rx_mbuf_tag,
15468                                      fp->rx_tpa_info[j].bd.m_map);
15469                    bus_dmamap_destroy(fp->rx_mbuf_tag,
15470                                       fp->rx_tpa_info[j].bd.m_map);
15471                }
15472            }
15473
15474            if (fp->rx_tpa_info_mbuf_spare_map != NULL) {
15475                bus_dmamap_unload(fp->rx_mbuf_tag,
15476                                  fp->rx_tpa_info_mbuf_spare_map);
15477                bus_dmamap_destroy(fp->rx_mbuf_tag,
15478                                   fp->rx_tpa_info_mbuf_spare_map);
15479            }
15480
15481            bus_dma_tag_destroy(fp->rx_mbuf_tag);
15482            fp->rx_mbuf_tag = NULL;
15483        }
15484
15485        /***************************/
15486        /* FP RX SGE MBUF DMA MAPS */
15487        /***************************/
15488
15489        if (fp->rx_sge_mbuf_tag != NULL) {
15490            for (j = 0; j < RX_SGE_TOTAL; j++) {
15491                if (fp->rx_sge_mbuf_chain[j].m_map != NULL) {
15492                    bus_dmamap_unload(fp->rx_sge_mbuf_tag,
15493                                      fp->rx_sge_mbuf_chain[j].m_map);
15494                    bus_dmamap_destroy(fp->rx_sge_mbuf_tag,
15495                                       fp->rx_sge_mbuf_chain[j].m_map);
15496                }
15497            }
15498
15499            if (fp->rx_sge_mbuf_spare_map != NULL) {
15500                bus_dmamap_unload(fp->rx_sge_mbuf_tag,
15501                                  fp->rx_sge_mbuf_spare_map);
15502                bus_dmamap_destroy(fp->rx_sge_mbuf_tag,
15503                                   fp->rx_sge_mbuf_spare_map);
15504            }
15505
15506            bus_dma_tag_destroy(fp->rx_sge_mbuf_tag);
15507            fp->rx_sge_mbuf_tag = NULL;
15508        }
15509    }
15510
15511    /***************************/
15512    /* FW DECOMPRESSION BUFFER */
15513    /***************************/
15514
15515    bxe_dma_free(sc, &sc->gz_buf_dma);
15516    sc->gz_buf = NULL;
15517    free(sc->gz_strm, M_DEVBUF);
15518    sc->gz_strm = NULL;
15519
15520    /*******************/
15521    /* SLOW PATH QUEUE */
15522    /*******************/
15523
15524    bxe_dma_free(sc, &sc->spq_dma);
15525    sc->spq = NULL;
15526
15527    /*************/
15528    /* SLOW PATH */
15529    /*************/
15530
15531    bxe_dma_free(sc, &sc->sp_dma);
15532    sc->sp = NULL;
15533
15534    /***************/
15535    /* EVENT QUEUE */
15536    /***************/
15537
15538    bxe_dma_free(sc, &sc->eq_dma);
15539    sc->eq = NULL;
15540
15541    /************************/
15542    /* DEFAULT STATUS BLOCK */
15543    /************************/
15544
15545    bxe_dma_free(sc, &sc->def_sb_dma);
15546    sc->def_sb = NULL;
15547
15548    bus_dma_tag_destroy(sc->parent_dma_tag);
15549    sc->parent_dma_tag = NULL;
15550}
15551
15552/*
15553 * Previous driver DMAE transaction may have occurred when pre-boot stage
15554 * ended and boot began. This would invalidate the addresses of the
15555 * transaction, resulting in was-error bit set in the PCI causing all
15556 * hw-to-host PCIe transactions to timeout. If this happened we want to clear
15557 * the interrupt which detected this from the pglueb and the was-done bit
15558 */
15559static void
15560bxe_prev_interrupted_dmae(struct bxe_softc *sc)
15561{
15562    uint32_t val;
15563
15564    if (!CHIP_IS_E1x(sc)) {
15565        val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS);
15566        if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
15567            BLOGD(sc, DBG_LOAD,
15568                  "Clearing 'was-error' bit that was set in pglueb");
15569            REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, 1 << SC_FUNC(sc));
15570        }
15571    }
15572}
15573
15574static int
15575bxe_prev_mcp_done(struct bxe_softc *sc)
15576{
15577    uint32_t rc = bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE,
15578                                 DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
15579    if (!rc) {
15580        BLOGE(sc, "MCP response failure, aborting\n");
15581        return (-1);
15582    }
15583
15584    return (0);
15585}
15586
15587static struct bxe_prev_list_node *
15588bxe_prev_path_get_entry(struct bxe_softc *sc)
15589{
15590    struct bxe_prev_list_node *tmp;
15591
15592    LIST_FOREACH(tmp, &bxe_prev_list, node) {
15593        if ((sc->pcie_bus == tmp->bus) &&
15594            (sc->pcie_device == tmp->slot) &&
15595            (SC_PATH(sc) == tmp->path)) {
15596            return (tmp);
15597        }
15598    }
15599
15600    return (NULL);
15601}
15602
15603static uint8_t
15604bxe_prev_is_path_marked(struct bxe_softc *sc)
15605{
15606    struct bxe_prev_list_node *tmp;
15607    int rc = FALSE;
15608
15609    mtx_lock(&bxe_prev_mtx);
15610
15611    tmp = bxe_prev_path_get_entry(sc);
15612    if (tmp) {
15613        if (tmp->aer) {
15614            BLOGD(sc, DBG_LOAD,
15615                  "Path %d/%d/%d was marked by AER\n",
15616                  sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
15617        } else {
15618            rc = TRUE;
15619            BLOGD(sc, DBG_LOAD,
15620                  "Path %d/%d/%d was already cleaned from previous drivers\n",
15621                  sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
15622        }
15623    }
15624
15625    mtx_unlock(&bxe_prev_mtx);
15626
15627    return (rc);
15628}
15629
15630static int
15631bxe_prev_mark_path(struct bxe_softc *sc,
15632                   uint8_t          after_undi)
15633{
15634    struct bxe_prev_list_node *tmp;
15635
15636    mtx_lock(&bxe_prev_mtx);
15637
15638    /* Check whether the entry for this path already exists */
15639    tmp = bxe_prev_path_get_entry(sc);
15640    if (tmp) {
15641        if (!tmp->aer) {
15642            BLOGD(sc, DBG_LOAD,
15643                  "Re-marking AER in path %d/%d/%d\n",
15644                  sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
15645        } else {
15646            BLOGD(sc, DBG_LOAD,
15647                  "Removing AER indication from path %d/%d/%d\n",
15648                  sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
15649            tmp->aer = 0;
15650        }
15651
15652        mtx_unlock(&bxe_prev_mtx);
15653        return (0);
15654    }
15655
15656    mtx_unlock(&bxe_prev_mtx);
15657
15658    /* Create an entry for this path and add it */
15659    tmp = malloc(sizeof(struct bxe_prev_list_node), M_DEVBUF,
15660                 (M_NOWAIT | M_ZERO));
15661    if (!tmp) {
15662        BLOGE(sc, "Failed to allocate 'bxe_prev_list_node'\n");
15663        return (-1);
15664    }
15665
15666    tmp->bus  = sc->pcie_bus;
15667    tmp->slot = sc->pcie_device;
15668    tmp->path = SC_PATH(sc);
15669    tmp->aer  = 0;
15670    tmp->undi = after_undi ? (1 << SC_PORT(sc)) : 0;
15671
15672    mtx_lock(&bxe_prev_mtx);
15673
15674    BLOGD(sc, DBG_LOAD,
15675          "Marked path %d/%d/%d - finished previous unload\n",
15676          sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
15677    LIST_INSERT_HEAD(&bxe_prev_list, tmp, node);
15678
15679    mtx_unlock(&bxe_prev_mtx);
15680
15681    return (0);
15682}
15683
15684static int
15685bxe_do_flr(struct bxe_softc *sc)
15686{
15687    int i;
15688
15689    /* only E2 and onwards support FLR */
15690    if (CHIP_IS_E1x(sc)) {
15691        BLOGD(sc, DBG_LOAD, "FLR not supported in E1/E1H\n");
15692        return (-1);
15693    }
15694
15695    /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
15696    if (sc->devinfo.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
15697        BLOGD(sc, DBG_LOAD, "FLR not supported by BC_VER: 0x%08x\n",
15698              sc->devinfo.bc_ver);
15699        return (-1);
15700    }
15701
15702    /* Wait for Transaction Pending bit clean */
15703    for (i = 0; i < 4; i++) {
15704        if (i) {
15705            DELAY(((1 << (i - 1)) * 100) * 1000);
15706        }
15707
15708        if (!bxe_is_pcie_pending(sc)) {
15709            goto clear;
15710        }
15711    }
15712
15713    BLOGE(sc, "PCIE transaction is not cleared, "
15714              "proceeding with reset anyway\n");
15715
15716clear:
15717
15718    BLOGD(sc, DBG_LOAD, "Initiating FLR\n");
15719    bxe_fw_command(sc, DRV_MSG_CODE_INITIATE_FLR, 0);
15720
15721    return (0);
15722}
15723
15724struct bxe_mac_vals {
15725    uint32_t xmac_addr;
15726    uint32_t xmac_val;
15727    uint32_t emac_addr;
15728    uint32_t emac_val;
15729    uint32_t umac_addr;
15730    uint32_t umac_val;
15731    uint32_t bmac_addr;
15732    uint32_t bmac_val[2];
15733};
15734
15735static void
15736bxe_prev_unload_close_mac(struct bxe_softc *sc,
15737                          struct bxe_mac_vals *vals)
15738{
15739    uint32_t val, base_addr, offset, mask, reset_reg;
15740    uint8_t mac_stopped = FALSE;
15741    uint8_t port = SC_PORT(sc);
15742    uint32_t wb_data[2];
15743
15744    /* reset addresses as they also mark which values were changed */
15745    vals->bmac_addr = 0;
15746    vals->umac_addr = 0;
15747    vals->xmac_addr = 0;
15748    vals->emac_addr = 0;
15749
15750    reset_reg = REG_RD(sc, MISC_REG_RESET_REG_2);
15751
15752    if (!CHIP_IS_E3(sc)) {
15753        val = REG_RD(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
15754        mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
15755        if ((mask & reset_reg) && val) {
15756            BLOGD(sc, DBG_LOAD, "Disable BMAC Rx\n");
15757            base_addr = SC_PORT(sc) ? NIG_REG_INGRESS_BMAC1_MEM
15758                                    : NIG_REG_INGRESS_BMAC0_MEM;
15759            offset = CHIP_IS_E2(sc) ? BIGMAC2_REGISTER_BMAC_CONTROL
15760                                    : BIGMAC_REGISTER_BMAC_CONTROL;
15761
15762            /*
15763             * use rd/wr since we cannot use dmae. This is safe
15764             * since MCP won't access the bus due to the request
15765             * to unload, and no function on the path can be
15766             * loaded at this time.
15767             */
15768            wb_data[0] = REG_RD(sc, base_addr + offset);
15769            wb_data[1] = REG_RD(sc, base_addr + offset + 0x4);
15770            vals->bmac_addr = base_addr + offset;
15771            vals->bmac_val[0] = wb_data[0];
15772            vals->bmac_val[1] = wb_data[1];
15773            wb_data[0] &= ~ELINK_BMAC_CONTROL_RX_ENABLE;
15774            REG_WR(sc, vals->bmac_addr, wb_data[0]);
15775            REG_WR(sc, vals->bmac_addr + 0x4, wb_data[1]);
15776        }
15777
15778        BLOGD(sc, DBG_LOAD, "Disable EMAC Rx\n");
15779        vals->emac_addr = NIG_REG_NIG_EMAC0_EN + SC_PORT(sc)*4;
15780        vals->emac_val = REG_RD(sc, vals->emac_addr);
15781        REG_WR(sc, vals->emac_addr, 0);
15782        mac_stopped = TRUE;
15783    } else {
15784        if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
15785            BLOGD(sc, DBG_LOAD, "Disable XMAC Rx\n");
15786            base_addr = SC_PORT(sc) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
15787            val = REG_RD(sc, base_addr + XMAC_REG_PFC_CTRL_HI);
15788            REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI, val & ~(1 << 1));
15789            REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI, val | (1 << 1));
15790            vals->xmac_addr = base_addr + XMAC_REG_CTRL;
15791            vals->xmac_val = REG_RD(sc, vals->xmac_addr);
15792            REG_WR(sc, vals->xmac_addr, 0);
15793            mac_stopped = TRUE;
15794        }
15795
15796        mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
15797        if (mask & reset_reg) {
15798            BLOGD(sc, DBG_LOAD, "Disable UMAC Rx\n");
15799            base_addr = SC_PORT(sc) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
15800            vals->umac_addr = base_addr + UMAC_REG_COMMAND_CONFIG;
15801            vals->umac_val = REG_RD(sc, vals->umac_addr);
15802            REG_WR(sc, vals->umac_addr, 0);
15803            mac_stopped = TRUE;
15804        }
15805    }
15806
15807    if (mac_stopped) {
15808        DELAY(20000);
15809    }
15810}
15811
15812#define BXE_PREV_UNDI_PROD_ADDR(p)  (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
15813#define BXE_PREV_UNDI_RCQ(val)      ((val) & 0xffff)
15814#define BXE_PREV_UNDI_BD(val)       ((val) >> 16 & 0xffff)
15815#define BXE_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
15816
15817static void
15818bxe_prev_unload_undi_inc(struct bxe_softc *sc,
15819                         uint8_t          port,
15820                         uint8_t          inc)
15821{
15822    uint16_t rcq, bd;
15823    uint32_t tmp_reg = REG_RD(sc, BXE_PREV_UNDI_PROD_ADDR(port));
15824
15825    rcq = BXE_PREV_UNDI_RCQ(tmp_reg) + inc;
15826    bd = BXE_PREV_UNDI_BD(tmp_reg) + inc;
15827
15828    tmp_reg = BXE_PREV_UNDI_PROD(rcq, bd);
15829    REG_WR(sc, BXE_PREV_UNDI_PROD_ADDR(port), tmp_reg);
15830
15831    BLOGD(sc, DBG_LOAD,
15832          "UNDI producer [%d] rings bd -> 0x%04x, rcq -> 0x%04x\n",
15833          port, bd, rcq);
15834}
15835
15836static int
15837bxe_prev_unload_common(struct bxe_softc *sc)
15838{
15839    uint32_t reset_reg, tmp_reg = 0, rc;
15840    uint8_t prev_undi = FALSE;
15841    struct bxe_mac_vals mac_vals;
15842    uint32_t timer_count = 1000;
15843    uint32_t prev_brb;
15844
15845    /*
15846     * It is possible a previous function received 'common' answer,
15847     * but hasn't loaded yet, therefore creating a scenario of
15848     * multiple functions receiving 'common' on the same path.
15849     */
15850    BLOGD(sc, DBG_LOAD, "Common unload Flow\n");
15851
15852    memset(&mac_vals, 0, sizeof(mac_vals));
15853
15854    if (bxe_prev_is_path_marked(sc)) {
15855        return (bxe_prev_mcp_done(sc));
15856    }
15857
15858    reset_reg = REG_RD(sc, MISC_REG_RESET_REG_1);
15859
15860    /* Reset should be performed after BRB is emptied */
15861    if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
15862        /* Close the MAC Rx to prevent BRB from filling up */
15863        bxe_prev_unload_close_mac(sc, &mac_vals);
15864
15865        /* close LLH filters towards the BRB */
15866        elink_set_rx_filter(&sc->link_params, 0);
15867
15868        /*
15869         * Check if the UNDI driver was previously loaded.
15870         * UNDI driver initializes CID offset for normal bell to 0x7
15871         */
15872        if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
15873            tmp_reg = REG_RD(sc, DORQ_REG_NORM_CID_OFST);
15874            if (tmp_reg == 0x7) {
15875                BLOGD(sc, DBG_LOAD, "UNDI previously loaded\n");
15876                prev_undi = TRUE;
15877                /* clear the UNDI indication */
15878                REG_WR(sc, DORQ_REG_NORM_CID_OFST, 0);
15879                /* clear possible idle check errors */
15880                REG_RD(sc, NIG_REG_NIG_INT_STS_CLR_0);
15881            }
15882        }
15883
15884        /* wait until BRB is empty */
15885        tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
15886        while (timer_count) {
15887            prev_brb = tmp_reg;
15888
15889            tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
15890            if (!tmp_reg) {
15891                break;
15892            }
15893
15894            BLOGD(sc, DBG_LOAD, "BRB still has 0x%08x\n", tmp_reg);
15895
15896            /* reset timer as long as BRB actually gets emptied */
15897            if (prev_brb > tmp_reg) {
15898                timer_count = 1000;
15899            } else {
15900                timer_count--;
15901            }
15902
15903            /* If UNDI resides in memory, manually increment it */
15904            if (prev_undi) {
15905                bxe_prev_unload_undi_inc(sc, SC_PORT(sc), 1);
15906            }
15907
15908            DELAY(10);
15909        }
15910
15911        if (!timer_count) {
15912            BLOGE(sc, "Failed to empty BRB\n");
15913        }
15914    }
15915
15916    /* No packets are in the pipeline, path is ready for reset */
15917    bxe_reset_common(sc);
15918
15919    if (mac_vals.xmac_addr) {
15920        REG_WR(sc, mac_vals.xmac_addr, mac_vals.xmac_val);
15921    }
15922    if (mac_vals.umac_addr) {
15923        REG_WR(sc, mac_vals.umac_addr, mac_vals.umac_val);
15924    }
15925    if (mac_vals.emac_addr) {
15926        REG_WR(sc, mac_vals.emac_addr, mac_vals.emac_val);
15927    }
15928    if (mac_vals.bmac_addr) {
15929        REG_WR(sc, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
15930        REG_WR(sc, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
15931    }
15932
15933    rc = bxe_prev_mark_path(sc, prev_undi);
15934    if (rc) {
15935        bxe_prev_mcp_done(sc);
15936        return (rc);
15937    }
15938
15939    return (bxe_prev_mcp_done(sc));
15940}
15941
15942static int
15943bxe_prev_unload_uncommon(struct bxe_softc *sc)
15944{
15945    int rc;
15946
15947    BLOGD(sc, DBG_LOAD, "Uncommon unload Flow\n");
15948
15949    /* Test if previous unload process was already finished for this path */
15950    if (bxe_prev_is_path_marked(sc)) {
15951        return (bxe_prev_mcp_done(sc));
15952    }
15953
15954    BLOGD(sc, DBG_LOAD, "Path is unmarked\n");
15955
15956    /*
15957     * If function has FLR capabilities, and existing FW version matches
15958     * the one required, then FLR will be sufficient to clean any residue
15959     * left by previous driver
15960     */
15961    rc = bxe_nic_load_analyze_req(sc, FW_MSG_CODE_DRV_LOAD_FUNCTION);
15962    if (!rc) {
15963        /* fw version is good */
15964        BLOGD(sc, DBG_LOAD, "FW version matches our own, attempting FLR\n");
15965        rc = bxe_do_flr(sc);
15966    }
15967
15968    if (!rc) {
15969        /* FLR was performed */
15970        BLOGD(sc, DBG_LOAD, "FLR successful\n");
15971        return (0);
15972    }
15973
15974    BLOGD(sc, DBG_LOAD, "Could not FLR\n");
15975
15976    /* Close the MCP request, return failure*/
15977    rc = bxe_prev_mcp_done(sc);
15978    if (!rc) {
15979        rc = BXE_PREV_WAIT_NEEDED;
15980    }
15981
15982    return (rc);
15983}
15984
15985static int
15986bxe_prev_unload(struct bxe_softc *sc)
15987{
15988    int time_counter = 10;
15989    uint32_t fw, hw_lock_reg, hw_lock_val;
15990    uint32_t rc = 0;
15991
15992    /*
15993     * Clear HW from errors which may have resulted from an interrupted
15994     * DMAE transaction.
15995     */
15996    bxe_prev_interrupted_dmae(sc);
15997
15998    /* Release previously held locks */
15999    hw_lock_reg =
16000        (SC_FUNC(sc) <= 5) ?
16001            (MISC_REG_DRIVER_CONTROL_1 + SC_FUNC(sc) * 8) :
16002            (MISC_REG_DRIVER_CONTROL_7 + (SC_FUNC(sc) - 6) * 8);
16003
16004    hw_lock_val = (REG_RD(sc, hw_lock_reg));
16005    if (hw_lock_val) {
16006        if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
16007            BLOGD(sc, DBG_LOAD, "Releasing previously held NVRAM lock\n");
16008            REG_WR(sc, MCP_REG_MCPR_NVM_SW_ARB,
16009                   (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << SC_PORT(sc)));
16010        }
16011        BLOGD(sc, DBG_LOAD, "Releasing previously held HW lock\n");
16012        REG_WR(sc, hw_lock_reg, 0xffffffff);
16013    } else {
16014        BLOGD(sc, DBG_LOAD, "No need to release HW/NVRAM locks\n");
16015    }
16016
16017    if (MCPR_ACCESS_LOCK_LOCK & REG_RD(sc, MCP_REG_MCPR_ACCESS_LOCK)) {
16018        BLOGD(sc, DBG_LOAD, "Releasing previously held ALR\n");
16019        REG_WR(sc, MCP_REG_MCPR_ACCESS_LOCK, 0);
16020    }
16021
16022    do {
16023        /* Lock MCP using an unload request */
16024        fw = bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
16025        if (!fw) {
16026            BLOGE(sc, "MCP response failure, aborting\n");
16027            rc = -1;
16028            break;
16029        }
16030
16031        if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON) {
16032            rc = bxe_prev_unload_common(sc);
16033            break;
16034        }
16035
16036        /* non-common reply from MCP night require looping */
16037        rc = bxe_prev_unload_uncommon(sc);
16038        if (rc != BXE_PREV_WAIT_NEEDED) {
16039            break;
16040        }
16041
16042        DELAY(20000);
16043    } while (--time_counter);
16044
16045    if (!time_counter || rc) {
16046        BLOGE(sc, "Failed to unload previous driver!\n");
16047        rc = -1;
16048    }
16049
16050    return (rc);
16051}
16052
16053void
16054bxe_dcbx_set_state(struct bxe_softc *sc,
16055                   uint8_t          dcb_on,
16056                   uint32_t         dcbx_enabled)
16057{
16058    if (!CHIP_IS_E1x(sc)) {
16059        sc->dcb_state = dcb_on;
16060        sc->dcbx_enabled = dcbx_enabled;
16061    } else {
16062        sc->dcb_state = FALSE;
16063        sc->dcbx_enabled = BXE_DCBX_ENABLED_INVALID;
16064    }
16065    BLOGD(sc, DBG_LOAD,
16066          "DCB state [%s:%s]\n",
16067          dcb_on ? "ON" : "OFF",
16068          (dcbx_enabled == BXE_DCBX_ENABLED_OFF) ? "user-mode" :
16069          (dcbx_enabled == BXE_DCBX_ENABLED_ON_NEG_OFF) ? "on-chip static" :
16070          (dcbx_enabled == BXE_DCBX_ENABLED_ON_NEG_ON) ?
16071          "on-chip with negotiation" : "invalid");
16072}
16073
16074/* must be called after sriov-enable */
16075static int
16076bxe_set_qm_cid_count(struct bxe_softc *sc)
16077{
16078    int cid_count = BXE_L2_MAX_CID(sc);
16079
16080    if (IS_SRIOV(sc)) {
16081        cid_count += BXE_VF_CIDS;
16082    }
16083
16084    if (CNIC_SUPPORT(sc)) {
16085        cid_count += CNIC_CID_MAX;
16086    }
16087
16088    return (roundup(cid_count, QM_CID_ROUND));
16089}
16090
16091static void
16092bxe_init_multi_cos(struct bxe_softc *sc)
16093{
16094    int pri, cos;
16095
16096    uint32_t pri_map = 0; /* XXX change to user config */
16097
16098    for (pri = 0; pri < BXE_MAX_PRIORITY; pri++) {
16099        cos = ((pri_map & (0xf << (pri * 4))) >> (pri * 4));
16100        if (cos < sc->max_cos) {
16101            sc->prio_to_cos[pri] = cos;
16102        } else {
16103            BLOGW(sc, "Invalid COS %d for priority %d "
16104                      "(max COS is %d), setting to 0\n",
16105                  cos, pri, (sc->max_cos - 1));
16106            sc->prio_to_cos[pri] = 0;
16107        }
16108    }
16109}
16110
16111static int
16112bxe_sysctl_state(SYSCTL_HANDLER_ARGS)
16113{
16114    struct bxe_softc *sc;
16115    int error, result;
16116
16117    result = 0;
16118    error = sysctl_handle_int(oidp, &result, 0, req);
16119
16120    if (error || !req->newptr) {
16121        return (error);
16122    }
16123
16124    if (result == 1) {
16125	uint32_t  temp;
16126        sc = (struct bxe_softc *)arg1;
16127
16128        BLOGI(sc, "... dumping driver state ...\n");
16129	temp = SHMEM2_RD(sc, temperature_in_half_celsius);
16130	BLOGI(sc, "\t Device Temperature = %d Celsius\n", (temp/2));
16131    }
16132
16133    return (error);
16134}
16135
16136static int
16137bxe_sysctl_eth_stat(SYSCTL_HANDLER_ARGS)
16138{
16139    struct bxe_softc *sc = (struct bxe_softc *)arg1;
16140    uint32_t *eth_stats = (uint32_t *)&sc->eth_stats;
16141    uint32_t *offset;
16142    uint64_t value = 0;
16143    int index = (int)arg2;
16144
16145    if (index >= BXE_NUM_ETH_STATS) {
16146        BLOGE(sc, "bxe_eth_stats index out of range (%d)\n", index);
16147        return (-1);
16148    }
16149
16150    offset = (eth_stats + bxe_eth_stats_arr[index].offset);
16151
16152    switch (bxe_eth_stats_arr[index].size) {
16153    case 4:
16154        value = (uint64_t)*offset;
16155        break;
16156    case 8:
16157        value = HILO_U64(*offset, *(offset + 1));
16158        break;
16159    default:
16160        BLOGE(sc, "Invalid bxe_eth_stats size (index=%d size=%d)\n",
16161              index, bxe_eth_stats_arr[index].size);
16162        return (-1);
16163    }
16164
16165    return (sysctl_handle_64(oidp, &value, 0, req));
16166}
16167
16168static int
16169bxe_sysctl_eth_q_stat(SYSCTL_HANDLER_ARGS)
16170{
16171    struct bxe_softc *sc = (struct bxe_softc *)arg1;
16172    uint32_t *eth_stats;
16173    uint32_t *offset;
16174    uint64_t value = 0;
16175    uint32_t q_stat = (uint32_t)arg2;
16176    uint32_t fp_index = ((q_stat >> 16) & 0xffff);
16177    uint32_t index = (q_stat & 0xffff);
16178
16179    eth_stats = (uint32_t *)&sc->fp[fp_index].eth_q_stats;
16180
16181    if (index >= BXE_NUM_ETH_Q_STATS) {
16182        BLOGE(sc, "bxe_eth_q_stats index out of range (%d)\n", index);
16183        return (-1);
16184    }
16185
16186    offset = (eth_stats + bxe_eth_q_stats_arr[index].offset);
16187
16188    switch (bxe_eth_q_stats_arr[index].size) {
16189    case 4:
16190        value = (uint64_t)*offset;
16191        break;
16192    case 8:
16193        value = HILO_U64(*offset, *(offset + 1));
16194        break;
16195    default:
16196        BLOGE(sc, "Invalid bxe_eth_q_stats size (index=%d size=%d)\n",
16197              index, bxe_eth_q_stats_arr[index].size);
16198        return (-1);
16199    }
16200
16201    return (sysctl_handle_64(oidp, &value, 0, req));
16202}
16203
16204static void
16205bxe_add_sysctls(struct bxe_softc *sc)
16206{
16207    struct sysctl_ctx_list *ctx;
16208    struct sysctl_oid_list *children;
16209    struct sysctl_oid *queue_top, *queue;
16210    struct sysctl_oid_list *queue_top_children, *queue_children;
16211    char queue_num_buf[32];
16212    uint32_t q_stat;
16213    int i, j;
16214
16215    ctx = device_get_sysctl_ctx(sc->dev);
16216    children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev));
16217
16218    SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "version",
16219                      CTLFLAG_RD, BXE_DRIVER_VERSION, 0,
16220                      "version");
16221
16222    SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "bc_version",
16223                      CTLFLAG_RD, sc->devinfo.bc_ver_str, 0,
16224                      "bootcode version");
16225
16226    snprintf(sc->fw_ver_str, sizeof(sc->fw_ver_str), "%d.%d.%d.%d",
16227             BCM_5710_FW_MAJOR_VERSION,
16228             BCM_5710_FW_MINOR_VERSION,
16229             BCM_5710_FW_REVISION_VERSION,
16230             BCM_5710_FW_ENGINEERING_VERSION);
16231    SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "fw_version",
16232                      CTLFLAG_RD, sc->fw_ver_str, 0,
16233                      "firmware version");
16234
16235    snprintf(sc->mf_mode_str, sizeof(sc->mf_mode_str), "%s",
16236        ((sc->devinfo.mf_info.mf_mode == SINGLE_FUNCTION)     ? "Single"  :
16237         (sc->devinfo.mf_info.mf_mode == MULTI_FUNCTION_SD)   ? "MF-SD"   :
16238         (sc->devinfo.mf_info.mf_mode == MULTI_FUNCTION_SI)   ? "MF-SI"   :
16239         (sc->devinfo.mf_info.mf_mode == MULTI_FUNCTION_AFEX) ? "MF-AFEX" :
16240                                                                "Unknown"));
16241    SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "mf_mode",
16242                      CTLFLAG_RD, sc->mf_mode_str, 0,
16243                      "multifunction mode");
16244
16245    SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "mf_vnics",
16246                    CTLFLAG_RD, &sc->devinfo.mf_info.vnics_per_port, 0,
16247                    "multifunction vnics per port");
16248
16249    SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "mac_addr",
16250                      CTLFLAG_RD, sc->mac_addr_str, 0,
16251                      "mac address");
16252
16253    snprintf(sc->pci_link_str, sizeof(sc->pci_link_str), "%s x%d",
16254        ((sc->devinfo.pcie_link_speed == 1) ? "2.5GT/s" :
16255         (sc->devinfo.pcie_link_speed == 2) ? "5.0GT/s" :
16256         (sc->devinfo.pcie_link_speed == 4) ? "8.0GT/s" :
16257                                              "???GT/s"),
16258        sc->devinfo.pcie_link_width);
16259    SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "pci_link",
16260                      CTLFLAG_RD, sc->pci_link_str, 0,
16261                      "pci link status");
16262
16263    sc->debug = bxe_debug;
16264    SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "debug",
16265                    CTLFLAG_RW, &sc->debug,
16266                    "debug logging mode");
16267
16268    sc->rx_budget = bxe_rx_budget;
16269    SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rx_budget",
16270                    CTLFLAG_RW, &sc->rx_budget, 0,
16271                    "rx processing budget");
16272
16273    SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "state",
16274                    CTLTYPE_UINT | CTLFLAG_RW, sc, 0,
16275                    bxe_sysctl_state, "IU", "dump driver state");
16276
16277    for (i = 0; i < BXE_NUM_ETH_STATS; i++) {
16278        SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
16279                        bxe_eth_stats_arr[i].string,
16280                        CTLTYPE_U64 | CTLFLAG_RD, sc, i,
16281                        bxe_sysctl_eth_stat, "LU",
16282                        bxe_eth_stats_arr[i].string);
16283    }
16284
16285    /* add a new parent node for all queues "dev.bxe.#.queue" */
16286    queue_top = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "queue",
16287                                CTLFLAG_RD, NULL, "queue");
16288    queue_top_children = SYSCTL_CHILDREN(queue_top);
16289
16290    for (i = 0; i < sc->num_queues; i++) {
16291        /* add a new parent node for a single queue "dev.bxe.#.queue.#" */
16292        snprintf(queue_num_buf, sizeof(queue_num_buf), "%d", i);
16293        queue = SYSCTL_ADD_NODE(ctx, queue_top_children, OID_AUTO,
16294                                queue_num_buf, CTLFLAG_RD, NULL,
16295                                "single queue");
16296        queue_children = SYSCTL_CHILDREN(queue);
16297
16298        for (j = 0; j < BXE_NUM_ETH_Q_STATS; j++) {
16299            q_stat = ((i << 16) | j);
16300            SYSCTL_ADD_PROC(ctx, queue_children, OID_AUTO,
16301                            bxe_eth_q_stats_arr[j].string,
16302                            CTLTYPE_U64 | CTLFLAG_RD, sc, q_stat,
16303                            bxe_sysctl_eth_q_stat, "LU",
16304                            bxe_eth_q_stats_arr[j].string);
16305        }
16306    }
16307}
16308
16309/*
16310 * Device attach function.
16311 *
16312 * Allocates device resources, performs secondary chip identification, and
16313 * initializes driver instance variables. This function is called from driver
16314 * load after a successful probe.
16315 *
16316 * Returns:
16317 *   0 = Success, >0 = Failure
16318 */
16319static int
16320bxe_attach(device_t dev)
16321{
16322    struct bxe_softc *sc;
16323
16324    sc = device_get_softc(dev);
16325
16326    BLOGD(sc, DBG_LOAD, "Starting attach...\n");
16327
16328    sc->state = BXE_STATE_CLOSED;
16329
16330    sc->dev  = dev;
16331    sc->unit = device_get_unit(dev);
16332
16333    BLOGD(sc, DBG_LOAD, "softc = %p\n", sc);
16334
16335    sc->pcie_bus    = pci_get_bus(dev);
16336    sc->pcie_device = pci_get_slot(dev);
16337    sc->pcie_func   = pci_get_function(dev);
16338
16339    /* enable bus master capability */
16340    pci_enable_busmaster(dev);
16341
16342    /* get the BARs */
16343    if (bxe_allocate_bars(sc) != 0) {
16344        return (ENXIO);
16345    }
16346
16347    /* initialize the mutexes */
16348    bxe_init_mutexes(sc);
16349
16350    /* prepare the periodic callout */
16351    callout_init(&sc->periodic_callout, 0);
16352
16353    /* prepare the chip taskqueue */
16354    sc->chip_tq_flags = CHIP_TQ_NONE;
16355    snprintf(sc->chip_tq_name, sizeof(sc->chip_tq_name),
16356             "bxe%d_chip_tq", sc->unit);
16357    TASK_INIT(&sc->chip_tq_task, 0, bxe_handle_chip_tq, sc);
16358    sc->chip_tq = taskqueue_create(sc->chip_tq_name, M_NOWAIT,
16359                                   taskqueue_thread_enqueue,
16360                                   &sc->chip_tq);
16361    taskqueue_start_threads(&sc->chip_tq, 1, PWAIT, /* lower priority */
16362                            "%s", sc->chip_tq_name);
16363
16364    /* get device info and set params */
16365    if (bxe_get_device_info(sc) != 0) {
16366        BLOGE(sc, "getting device info\n");
16367        bxe_deallocate_bars(sc);
16368        pci_disable_busmaster(dev);
16369        return (ENXIO);
16370    }
16371
16372    /* get final misc params */
16373    bxe_get_params(sc);
16374
16375    /* set the default MTU (changed via ifconfig) */
16376    sc->mtu = ETHERMTU;
16377
16378    bxe_set_modes_bitmap(sc);
16379
16380    /* XXX
16381     * If in AFEX mode and the function is configured for FCoE
16382     * then bail... no L2 allowed.
16383     */
16384
16385    /* get phy settings from shmem and 'and' against admin settings */
16386    bxe_get_phy_info(sc);
16387
16388    /* initialize the FreeBSD ifnet interface */
16389    if (bxe_init_ifnet(sc) != 0) {
16390        bxe_release_mutexes(sc);
16391        bxe_deallocate_bars(sc);
16392        pci_disable_busmaster(dev);
16393        return (ENXIO);
16394    }
16395
16396    /* allocate device interrupts */
16397    if (bxe_interrupt_alloc(sc) != 0) {
16398        if (sc->ifp != NULL) {
16399            ether_ifdetach(sc->ifp);
16400        }
16401        ifmedia_removeall(&sc->ifmedia);
16402        bxe_release_mutexes(sc);
16403        bxe_deallocate_bars(sc);
16404        pci_disable_busmaster(dev);
16405        return (ENXIO);
16406    }
16407
16408    /* allocate ilt */
16409    if (bxe_alloc_ilt_mem(sc) != 0) {
16410        bxe_interrupt_free(sc);
16411        if (sc->ifp != NULL) {
16412            ether_ifdetach(sc->ifp);
16413        }
16414        ifmedia_removeall(&sc->ifmedia);
16415        bxe_release_mutexes(sc);
16416        bxe_deallocate_bars(sc);
16417        pci_disable_busmaster(dev);
16418        return (ENXIO);
16419    }
16420
16421    /* allocate the host hardware/software hsi structures */
16422    if (bxe_alloc_hsi_mem(sc) != 0) {
16423        bxe_free_ilt_mem(sc);
16424        bxe_interrupt_free(sc);
16425        if (sc->ifp != NULL) {
16426            ether_ifdetach(sc->ifp);
16427        }
16428        ifmedia_removeall(&sc->ifmedia);
16429        bxe_release_mutexes(sc);
16430        bxe_deallocate_bars(sc);
16431        pci_disable_busmaster(dev);
16432        return (ENXIO);
16433    }
16434
16435    /* need to reset chip if UNDI was active */
16436    if (IS_PF(sc) && !BXE_NOMCP(sc)) {
16437        /* init fw_seq */
16438        sc->fw_seq =
16439            (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
16440             DRV_MSG_SEQ_NUMBER_MASK);
16441        BLOGD(sc, DBG_LOAD, "prev unload fw_seq 0x%04x\n", sc->fw_seq);
16442        bxe_prev_unload(sc);
16443    }
16444
16445#if 1
16446    /* XXX */
16447    bxe_dcbx_set_state(sc, FALSE, BXE_DCBX_ENABLED_OFF);
16448#else
16449    if (SHMEM2_HAS(sc, dcbx_lldp_params_offset) &&
16450        SHMEM2_HAS(sc, dcbx_lldp_dcbx_stat_offset) &&
16451        SHMEM2_RD(sc, dcbx_lldp_params_offset) &&
16452        SHMEM2_RD(sc, dcbx_lldp_dcbx_stat_offset)) {
16453        bxe_dcbx_set_state(sc, TRUE, BXE_DCBX_ENABLED_ON_NEG_ON);
16454        bxe_dcbx_init_params(sc);
16455    } else {
16456        bxe_dcbx_set_state(sc, FALSE, BXE_DCBX_ENABLED_OFF);
16457    }
16458#endif
16459
16460    /* calculate qm_cid_count */
16461    sc->qm_cid_count = bxe_set_qm_cid_count(sc);
16462    BLOGD(sc, DBG_LOAD, "qm_cid_count=%d\n", sc->qm_cid_count);
16463
16464    sc->max_cos = 1;
16465    bxe_init_multi_cos(sc);
16466
16467    bxe_add_sysctls(sc);
16468
16469    return (0);
16470}
16471
16472/*
16473 * Device detach function.
16474 *
16475 * Stops the controller, resets the controller, and releases resources.
16476 *
16477 * Returns:
16478 *   0 = Success, >0 = Failure
16479 */
16480static int
16481bxe_detach(device_t dev)
16482{
16483    struct bxe_softc *sc;
16484    if_t ifp;
16485
16486    sc = device_get_softc(dev);
16487
16488    BLOGD(sc, DBG_LOAD, "Starting detach...\n");
16489
16490    ifp = sc->ifp;
16491    if (ifp != NULL && if_vlantrunkinuse(ifp)) {
16492        BLOGE(sc, "Cannot detach while VLANs are in use.\n");
16493        return(EBUSY);
16494    }
16495
16496    /* stop the periodic callout */
16497    bxe_periodic_stop(sc);
16498
16499    /* stop the chip taskqueue */
16500    atomic_store_rel_long(&sc->chip_tq_flags, CHIP_TQ_NONE);
16501    if (sc->chip_tq) {
16502        taskqueue_drain(sc->chip_tq, &sc->chip_tq_task);
16503        taskqueue_free(sc->chip_tq);
16504        sc->chip_tq = NULL;
16505    }
16506
16507    /* stop and reset the controller if it was open */
16508    if (sc->state != BXE_STATE_CLOSED) {
16509        BXE_CORE_LOCK(sc);
16510        bxe_nic_unload(sc, UNLOAD_CLOSE, TRUE);
16511        BXE_CORE_UNLOCK(sc);
16512    }
16513
16514    /* release the network interface */
16515    if (ifp != NULL) {
16516        ether_ifdetach(ifp);
16517    }
16518    ifmedia_removeall(&sc->ifmedia);
16519
16520    /* XXX do the following based on driver state... */
16521
16522    /* free the host hardware/software hsi structures */
16523    bxe_free_hsi_mem(sc);
16524
16525    /* free ilt */
16526    bxe_free_ilt_mem(sc);
16527
16528    /* release the interrupts */
16529    bxe_interrupt_free(sc);
16530
16531    /* Release the mutexes*/
16532    bxe_release_mutexes(sc);
16533
16534    /* Release the PCIe BAR mapped memory */
16535    bxe_deallocate_bars(sc);
16536
16537    /* Release the FreeBSD interface. */
16538    if (sc->ifp != NULL) {
16539        if_free(sc->ifp);
16540    }
16541
16542    pci_disable_busmaster(dev);
16543
16544    return (0);
16545}
16546
16547/*
16548 * Device shutdown function.
16549 *
16550 * Stops and resets the controller.
16551 *
16552 * Returns:
16553 *   Nothing
16554 */
16555static int
16556bxe_shutdown(device_t dev)
16557{
16558    struct bxe_softc *sc;
16559
16560    sc = device_get_softc(dev);
16561
16562    BLOGD(sc, DBG_LOAD, "Starting shutdown...\n");
16563
16564    /* stop the periodic callout */
16565    bxe_periodic_stop(sc);
16566
16567    BXE_CORE_LOCK(sc);
16568    bxe_nic_unload(sc, UNLOAD_NORMAL, FALSE);
16569    BXE_CORE_UNLOCK(sc);
16570
16571    return (0);
16572}
16573
16574void
16575bxe_igu_ack_sb(struct bxe_softc *sc,
16576               uint8_t          igu_sb_id,
16577               uint8_t          segment,
16578               uint16_t         index,
16579               uint8_t          op,
16580               uint8_t          update)
16581{
16582    uint32_t igu_addr = sc->igu_base_addr;
16583    igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
16584    bxe_igu_ack_sb_gen(sc, igu_sb_id, segment, index, op, update, igu_addr);
16585}
16586
16587static void
16588bxe_igu_clear_sb_gen(struct bxe_softc *sc,
16589                     uint8_t          func,
16590                     uint8_t          idu_sb_id,
16591                     uint8_t          is_pf)
16592{
16593    uint32_t data, ctl, cnt = 100;
16594    uint32_t igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
16595    uint32_t igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
16596    uint32_t igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
16597    uint32_t sb_bit =  1 << (idu_sb_id%32);
16598    uint32_t func_encode = func | (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
16599    uint32_t addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
16600
16601    /* Not supported in BC mode */
16602    if (CHIP_INT_MODE_IS_BC(sc)) {
16603        return;
16604    }
16605
16606    data = ((IGU_USE_REGISTER_cstorm_type_0_sb_cleanup <<
16607             IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
16608            IGU_REGULAR_CLEANUP_SET |
16609            IGU_REGULAR_BCLEANUP);
16610
16611    ctl = ((addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT) |
16612           (func_encode << IGU_CTRL_REG_FID_SHIFT) |
16613           (IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT));
16614
16615    BLOGD(sc, DBG_LOAD, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
16616            data, igu_addr_data);
16617    REG_WR(sc, igu_addr_data, data);
16618
16619    bus_space_barrier(sc->bar[BAR0].tag, sc->bar[BAR0].handle, 0, 0,
16620                      BUS_SPACE_BARRIER_WRITE);
16621    mb();
16622
16623    BLOGD(sc, DBG_LOAD, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
16624            ctl, igu_addr_ctl);
16625    REG_WR(sc, igu_addr_ctl, ctl);
16626
16627    bus_space_barrier(sc->bar[BAR0].tag, sc->bar[BAR0].handle, 0, 0,
16628                      BUS_SPACE_BARRIER_WRITE);
16629    mb();
16630
16631    /* wait for clean up to finish */
16632    while (!(REG_RD(sc, igu_addr_ack) & sb_bit) && --cnt) {
16633        DELAY(20000);
16634    }
16635
16636    if (!(REG_RD(sc, igu_addr_ack) & sb_bit)) {
16637        BLOGD(sc, DBG_LOAD,
16638              "Unable to finish IGU cleanup: "
16639              "idu_sb_id %d offset %d bit %d (cnt %d)\n",
16640              idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
16641    }
16642}
16643
16644static void
16645bxe_igu_clear_sb(struct bxe_softc *sc,
16646                 uint8_t          idu_sb_id)
16647{
16648    bxe_igu_clear_sb_gen(sc, SC_FUNC(sc), idu_sb_id, TRUE /*PF*/);
16649}
16650
16651
16652
16653
16654
16655
16656
16657/*******************/
16658/* ECORE CALLBACKS */
16659/*******************/
16660
16661static void
16662bxe_reset_common(struct bxe_softc *sc)
16663{
16664    uint32_t val = 0x1400;
16665
16666    /* reset_common */
16667    REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR), 0xd3ffff7f);
16668
16669    if (CHIP_IS_E3(sc)) {
16670        val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
16671        val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
16672    }
16673
16674    REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR), val);
16675}
16676
16677static void
16678bxe_common_init_phy(struct bxe_softc *sc)
16679{
16680    uint32_t shmem_base[2];
16681    uint32_t shmem2_base[2];
16682
16683    /* Avoid common init in case MFW supports LFA */
16684    if (SHMEM2_RD(sc, size) >
16685        (uint32_t)offsetof(struct shmem2_region,
16686                           lfa_host_addr[SC_PORT(sc)])) {
16687        return;
16688    }
16689
16690    shmem_base[0]  = sc->devinfo.shmem_base;
16691    shmem2_base[0] = sc->devinfo.shmem2_base;
16692
16693    if (!CHIP_IS_E1x(sc)) {
16694        shmem_base[1]  = SHMEM2_RD(sc, other_shmem_base_addr);
16695        shmem2_base[1] = SHMEM2_RD(sc, other_shmem2_base_addr);
16696    }
16697
16698    bxe_acquire_phy_lock(sc);
16699    elink_common_init_phy(sc, shmem_base, shmem2_base,
16700                          sc->devinfo.chip_id, 0);
16701    bxe_release_phy_lock(sc);
16702}
16703
16704static void
16705bxe_pf_disable(struct bxe_softc *sc)
16706{
16707    uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
16708
16709    val &= ~IGU_PF_CONF_FUNC_EN;
16710
16711    REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
16712    REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
16713    REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 0);
16714}
16715
16716static void
16717bxe_init_pxp(struct bxe_softc *sc)
16718{
16719    uint16_t devctl;
16720    int r_order, w_order;
16721
16722    devctl = bxe_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_CTL, 2);
16723
16724    BLOGD(sc, DBG_LOAD, "read 0x%08x from devctl\n", devctl);
16725
16726    w_order = ((devctl & PCIM_EXP_CTL_MAX_PAYLOAD) >> 5);
16727
16728    if (sc->mrrs == -1) {
16729        r_order = ((devctl & PCIM_EXP_CTL_MAX_READ_REQUEST) >> 12);
16730    } else {
16731        BLOGD(sc, DBG_LOAD, "forcing read order to %d\n", sc->mrrs);
16732        r_order = sc->mrrs;
16733    }
16734
16735    ecore_init_pxp_arb(sc, r_order, w_order);
16736}
16737
16738static uint32_t
16739bxe_get_pretend_reg(struct bxe_softc *sc)
16740{
16741    uint32_t base = PXP2_REG_PGL_PRETEND_FUNC_F0;
16742    uint32_t stride = (PXP2_REG_PGL_PRETEND_FUNC_F1 - base);
16743    return (base + (SC_ABS_FUNC(sc)) * stride);
16744}
16745
16746/*
16747 * Called only on E1H or E2.
16748 * When pretending to be PF, the pretend value is the function number 0..7.
16749 * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
16750 * combination.
16751 */
16752static int
16753bxe_pretend_func(struct bxe_softc *sc,
16754                 uint16_t         pretend_func_val)
16755{
16756    uint32_t pretend_reg;
16757
16758    if (CHIP_IS_E1H(sc) && (pretend_func_val > E1H_FUNC_MAX)) {
16759        return (-1);
16760    }
16761
16762    /* get my own pretend register */
16763    pretend_reg = bxe_get_pretend_reg(sc);
16764    REG_WR(sc, pretend_reg, pretend_func_val);
16765    REG_RD(sc, pretend_reg);
16766    return (0);
16767}
16768
16769static void
16770bxe_iov_init_dmae(struct bxe_softc *sc)
16771{
16772    return;
16773#if 0
16774    BLOGD(sc, DBG_LOAD, "SRIOV is %s\n", IS_SRIOV(sc) ? "ON" : "OFF");
16775
16776    if (!IS_SRIOV(sc)) {
16777        return;
16778    }
16779
16780    REG_WR(sc, DMAE_REG_BACKWARD_COMP_EN, 0);
16781#endif
16782}
16783
16784#if 0
16785static int
16786bxe_iov_init_ilt(struct bxe_softc *sc,
16787                 uint16_t         line)
16788{
16789    return (line);
16790#if 0
16791    int i;
16792    struct ecore_ilt* ilt = sc->ilt;
16793
16794    if (!IS_SRIOV(sc)) {
16795        return (line);
16796    }
16797
16798    /* set vfs ilt lines */
16799    for (i = 0; i < BXE_VF_CIDS/ILT_PAGE_CIDS ; i++) {
16800        struct hw_dma *hw_cxt = SC_VF_CXT_PAGE(sc,i);
16801        ilt->lines[line+i].page = hw_cxt->addr;
16802        ilt->lines[line+i].page_mapping = hw_cxt->mapping;
16803        ilt->lines[line+i].size = hw_cxt->size; /* doesn't matter */
16804    }
16805    return (line+i);
16806#endif
16807}
16808#endif
16809
16810static void
16811bxe_iov_init_dq(struct bxe_softc *sc)
16812{
16813    return;
16814#if 0
16815    if (!IS_SRIOV(sc)) {
16816        return;
16817    }
16818
16819    /* Set the DQ such that the CID reflect the abs_vfid */
16820    REG_WR(sc, DORQ_REG_VF_NORM_VF_BASE, 0);
16821    REG_WR(sc, DORQ_REG_MAX_RVFID_SIZE, ilog2(BNX2X_MAX_NUM_OF_VFS));
16822
16823    /*
16824     * Set VFs starting CID. If its > 0 the preceding CIDs are belong to
16825     * the PF L2 queues
16826     */
16827    REG_WR(sc, DORQ_REG_VF_NORM_CID_BASE, BNX2X_FIRST_VF_CID);
16828
16829    /* The VF window size is the log2 of the max number of CIDs per VF */
16830    REG_WR(sc, DORQ_REG_VF_NORM_CID_WND_SIZE, BNX2X_VF_CID_WND);
16831
16832    /*
16833     * The VF doorbell size  0 - *B, 4 - 128B. We set it here to match
16834     * the Pf doorbell size although the 2 are independent.
16835     */
16836    REG_WR(sc, DORQ_REG_VF_NORM_CID_OFST,
16837           BNX2X_DB_SHIFT - BNX2X_DB_MIN_SHIFT);
16838
16839    /*
16840     * No security checks for now -
16841     * configure single rule (out of 16) mask = 0x1, value = 0x0,
16842     * CID range 0 - 0x1ffff
16843     */
16844    REG_WR(sc, DORQ_REG_VF_TYPE_MASK_0, 1);
16845    REG_WR(sc, DORQ_REG_VF_TYPE_VALUE_0, 0);
16846    REG_WR(sc, DORQ_REG_VF_TYPE_MIN_MCID_0, 0);
16847    REG_WR(sc, DORQ_REG_VF_TYPE_MAX_MCID_0, 0x1ffff);
16848
16849    /* set the number of VF alllowed doorbells to the full DQ range */
16850    REG_WR(sc, DORQ_REG_VF_NORM_MAX_CID_COUNT, 0x20000);
16851
16852    /* set the VF doorbell threshold */
16853    REG_WR(sc, DORQ_REG_VF_USAGE_CT_LIMIT, 4);
16854#endif
16855}
16856
16857/* send a NIG loopback debug packet */
16858static void
16859bxe_lb_pckt(struct bxe_softc *sc)
16860{
16861    uint32_t wb_write[3];
16862
16863    /* Ethernet source and destination addresses */
16864    wb_write[0] = 0x55555555;
16865    wb_write[1] = 0x55555555;
16866    wb_write[2] = 0x20;     /* SOP */
16867    REG_WR_DMAE(sc, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
16868
16869    /* NON-IP protocol */
16870    wb_write[0] = 0x09000000;
16871    wb_write[1] = 0x55555555;
16872    wb_write[2] = 0x10;     /* EOP, eop_bvalid = 0 */
16873    REG_WR_DMAE(sc, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
16874}
16875
16876/*
16877 * Some of the internal memories are not directly readable from the driver.
16878 * To test them we send debug packets.
16879 */
16880static int
16881bxe_int_mem_test(struct bxe_softc *sc)
16882{
16883    int factor;
16884    int count, i;
16885    uint32_t val = 0;
16886
16887    if (CHIP_REV_IS_FPGA(sc)) {
16888        factor = 120;
16889    } else if (CHIP_REV_IS_EMUL(sc)) {
16890        factor = 200;
16891    } else {
16892        factor = 1;
16893    }
16894
16895    /* disable inputs of parser neighbor blocks */
16896    REG_WR(sc, TSDM_REG_ENABLE_IN1, 0x0);
16897    REG_WR(sc, TCM_REG_PRS_IFEN, 0x0);
16898    REG_WR(sc, CFC_REG_DEBUG0, 0x1);
16899    REG_WR(sc, NIG_REG_PRS_REQ_IN_EN, 0x0);
16900
16901    /*  write 0 to parser credits for CFC search request */
16902    REG_WR(sc, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
16903
16904    /* send Ethernet packet */
16905    bxe_lb_pckt(sc);
16906
16907    /* TODO do i reset NIG statistic? */
16908    /* Wait until NIG register shows 1 packet of size 0x10 */
16909    count = 1000 * factor;
16910    while (count) {
16911        bxe_read_dmae(sc, NIG_REG_STAT2_BRB_OCTET, 2);
16912        val = *BXE_SP(sc, wb_data[0]);
16913        if (val == 0x10) {
16914            break;
16915        }
16916
16917        DELAY(10000);
16918        count--;
16919    }
16920
16921    if (val != 0x10) {
16922        BLOGE(sc, "NIG timeout val=0x%x\n", val);
16923        return (-1);
16924    }
16925
16926    /* wait until PRS register shows 1 packet */
16927    count = (1000 * factor);
16928    while (count) {
16929        val = REG_RD(sc, PRS_REG_NUM_OF_PACKETS);
16930        if (val == 1) {
16931            break;
16932        }
16933
16934        DELAY(10000);
16935        count--;
16936    }
16937
16938    if (val != 0x1) {
16939        BLOGE(sc, "PRS timeout val=0x%x\n", val);
16940        return (-2);
16941    }
16942
16943    /* Reset and init BRB, PRS */
16944    REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
16945    DELAY(50000);
16946    REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
16947    DELAY(50000);
16948    ecore_init_block(sc, BLOCK_BRB1, PHASE_COMMON);
16949    ecore_init_block(sc, BLOCK_PRS, PHASE_COMMON);
16950
16951    /* Disable inputs of parser neighbor blocks */
16952    REG_WR(sc, TSDM_REG_ENABLE_IN1, 0x0);
16953    REG_WR(sc, TCM_REG_PRS_IFEN, 0x0);
16954    REG_WR(sc, CFC_REG_DEBUG0, 0x1);
16955    REG_WR(sc, NIG_REG_PRS_REQ_IN_EN, 0x0);
16956
16957    /* Write 0 to parser credits for CFC search request */
16958    REG_WR(sc, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
16959
16960    /* send 10 Ethernet packets */
16961    for (i = 0; i < 10; i++) {
16962        bxe_lb_pckt(sc);
16963    }
16964
16965    /* Wait until NIG register shows 10+1 packets of size 11*0x10 = 0xb0 */
16966    count = (1000 * factor);
16967    while (count) {
16968        bxe_read_dmae(sc, NIG_REG_STAT2_BRB_OCTET, 2);
16969        val = *BXE_SP(sc, wb_data[0]);
16970        if (val == 0xb0) {
16971            break;
16972        }
16973
16974        DELAY(10000);
16975        count--;
16976    }
16977
16978    if (val != 0xb0) {
16979        BLOGE(sc, "NIG timeout val=0x%x\n", val);
16980        return (-3);
16981    }
16982
16983    /* Wait until PRS register shows 2 packets */
16984    val = REG_RD(sc, PRS_REG_NUM_OF_PACKETS);
16985    if (val != 2) {
16986        BLOGE(sc, "PRS timeout val=0x%x\n", val);
16987    }
16988
16989    /* Write 1 to parser credits for CFC search request */
16990    REG_WR(sc, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
16991
16992    /* Wait until PRS register shows 3 packets */
16993    DELAY(10000 * factor);
16994
16995    /* Wait until NIG register shows 1 packet of size 0x10 */
16996    val = REG_RD(sc, PRS_REG_NUM_OF_PACKETS);
16997    if (val != 3) {
16998        BLOGE(sc, "PRS timeout val=0x%x\n", val);
16999    }
17000
17001    /* clear NIG EOP FIFO */
17002    for (i = 0; i < 11; i++) {
17003        REG_RD(sc, NIG_REG_INGRESS_EOP_LB_FIFO);
17004    }
17005
17006    val = REG_RD(sc, NIG_REG_INGRESS_EOP_LB_EMPTY);
17007    if (val != 1) {
17008        BLOGE(sc, "clear of NIG failed\n");
17009        return (-4);
17010    }
17011
17012    /* Reset and init BRB, PRS, NIG */
17013    REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
17014    DELAY(50000);
17015    REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
17016    DELAY(50000);
17017    ecore_init_block(sc, BLOCK_BRB1, PHASE_COMMON);
17018    ecore_init_block(sc, BLOCK_PRS, PHASE_COMMON);
17019    if (!CNIC_SUPPORT(sc)) {
17020        /* set NIC mode */
17021        REG_WR(sc, PRS_REG_NIC_MODE, 1);
17022    }
17023
17024    /* Enable inputs of parser neighbor blocks */
17025    REG_WR(sc, TSDM_REG_ENABLE_IN1, 0x7fffffff);
17026    REG_WR(sc, TCM_REG_PRS_IFEN, 0x1);
17027    REG_WR(sc, CFC_REG_DEBUG0, 0x0);
17028    REG_WR(sc, NIG_REG_PRS_REQ_IN_EN, 0x1);
17029
17030    return (0);
17031}
17032
17033static void
17034bxe_setup_fan_failure_detection(struct bxe_softc *sc)
17035{
17036    int is_required;
17037    uint32_t val;
17038    int port;
17039
17040    is_required = 0;
17041    val = (SHMEM_RD(sc, dev_info.shared_hw_config.config2) &
17042           SHARED_HW_CFG_FAN_FAILURE_MASK);
17043
17044    if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED) {
17045        is_required = 1;
17046    }
17047    /*
17048     * The fan failure mechanism is usually related to the PHY type since
17049     * the power consumption of the board is affected by the PHY. Currently,
17050     * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
17051     */
17052    else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) {
17053        for (port = PORT_0; port < PORT_MAX; port++) {
17054            is_required |= elink_fan_failure_det_req(sc,
17055                                                     sc->devinfo.shmem_base,
17056                                                     sc->devinfo.shmem2_base,
17057                                                     port);
17058        }
17059    }
17060
17061    BLOGD(sc, DBG_LOAD, "fan detection setting: %d\n", is_required);
17062
17063    if (is_required == 0) {
17064        return;
17065    }
17066
17067    /* Fan failure is indicated by SPIO 5 */
17068    bxe_set_spio(sc, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
17069
17070    /* set to active low mode */
17071    val = REG_RD(sc, MISC_REG_SPIO_INT);
17072    val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
17073    REG_WR(sc, MISC_REG_SPIO_INT, val);
17074
17075    /* enable interrupt to signal the IGU */
17076    val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
17077    val |= MISC_SPIO_SPIO5;
17078    REG_WR(sc, MISC_REG_SPIO_EVENT_EN, val);
17079}
17080
17081static void
17082bxe_enable_blocks_attention(struct bxe_softc *sc)
17083{
17084    uint32_t val;
17085
17086    REG_WR(sc, PXP_REG_PXP_INT_MASK_0, 0);
17087    if (!CHIP_IS_E1x(sc)) {
17088        REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0x40);
17089    } else {
17090        REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0);
17091    }
17092    REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
17093    REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
17094    /*
17095     * mask read length error interrupts in brb for parser
17096     * (parsing unit and 'checksum and crc' unit)
17097     * these errors are legal (PU reads fixed length and CAC can cause
17098     * read length error on truncated packets)
17099     */
17100    REG_WR(sc, BRB1_REG_BRB1_INT_MASK, 0xFC00);
17101    REG_WR(sc, QM_REG_QM_INT_MASK, 0);
17102    REG_WR(sc, TM_REG_TM_INT_MASK, 0);
17103    REG_WR(sc, XSDM_REG_XSDM_INT_MASK_0, 0);
17104    REG_WR(sc, XSDM_REG_XSDM_INT_MASK_1, 0);
17105    REG_WR(sc, XCM_REG_XCM_INT_MASK, 0);
17106/*      REG_WR(sc, XSEM_REG_XSEM_INT_MASK_0, 0); */
17107/*      REG_WR(sc, XSEM_REG_XSEM_INT_MASK_1, 0); */
17108    REG_WR(sc, USDM_REG_USDM_INT_MASK_0, 0);
17109    REG_WR(sc, USDM_REG_USDM_INT_MASK_1, 0);
17110    REG_WR(sc, UCM_REG_UCM_INT_MASK, 0);
17111/*      REG_WR(sc, USEM_REG_USEM_INT_MASK_0, 0); */
17112/*      REG_WR(sc, USEM_REG_USEM_INT_MASK_1, 0); */
17113    REG_WR(sc, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
17114    REG_WR(sc, CSDM_REG_CSDM_INT_MASK_0, 0);
17115    REG_WR(sc, CSDM_REG_CSDM_INT_MASK_1, 0);
17116    REG_WR(sc, CCM_REG_CCM_INT_MASK, 0);
17117/*      REG_WR(sc, CSEM_REG_CSEM_INT_MASK_0, 0); */
17118/*      REG_WR(sc, CSEM_REG_CSEM_INT_MASK_1, 0); */
17119
17120    val = (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT |
17121           PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
17122           PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN);
17123    if (!CHIP_IS_E1x(sc)) {
17124        val |= (PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
17125                PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED);
17126    }
17127    REG_WR(sc, PXP2_REG_PXP2_INT_MASK_0, val);
17128
17129    REG_WR(sc, TSDM_REG_TSDM_INT_MASK_0, 0);
17130    REG_WR(sc, TSDM_REG_TSDM_INT_MASK_1, 0);
17131    REG_WR(sc, TCM_REG_TCM_INT_MASK, 0);
17132/*      REG_WR(sc, TSEM_REG_TSEM_INT_MASK_0, 0); */
17133
17134    if (!CHIP_IS_E1x(sc)) {
17135        /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
17136        REG_WR(sc, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
17137    }
17138
17139    REG_WR(sc, CDU_REG_CDU_INT_MASK, 0);
17140    REG_WR(sc, DMAE_REG_DMAE_INT_MASK, 0);
17141/*      REG_WR(sc, MISC_REG_MISC_INT_MASK, 0); */
17142    REG_WR(sc, PBF_REG_PBF_INT_MASK, 0x18);     /* bit 3,4 masked */
17143}
17144
17145/**
17146 * bxe_init_hw_common - initialize the HW at the COMMON phase.
17147 *
17148 * @sc:     driver handle
17149 */
17150static int
17151bxe_init_hw_common(struct bxe_softc *sc)
17152{
17153    uint8_t abs_func_id;
17154    uint32_t val;
17155
17156    BLOGD(sc, DBG_LOAD, "starting common init for func %d\n",
17157          SC_ABS_FUNC(sc));
17158
17159    /*
17160     * take the RESET lock to protect undi_unload flow from accessing
17161     * registers while we are resetting the chip
17162     */
17163    bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
17164
17165    bxe_reset_common(sc);
17166
17167    REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET), 0xffffffff);
17168
17169    val = 0xfffc;
17170    if (CHIP_IS_E3(sc)) {
17171        val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
17172        val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
17173    }
17174
17175    REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET), val);
17176
17177    bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
17178
17179    ecore_init_block(sc, BLOCK_MISC, PHASE_COMMON);
17180    BLOGD(sc, DBG_LOAD, "after misc block init\n");
17181
17182    if (!CHIP_IS_E1x(sc)) {
17183        /*
17184         * 4-port mode or 2-port mode we need to turn off master-enable for
17185         * everyone. After that we turn it back on for self. So, we disregard
17186         * multi-function, and always disable all functions on the given path,
17187         * this means 0,2,4,6 for path 0 and 1,3,5,7 for path 1
17188         */
17189        for (abs_func_id = SC_PATH(sc);
17190             abs_func_id < (E2_FUNC_MAX * 2);
17191             abs_func_id += 2) {
17192            if (abs_func_id == SC_ABS_FUNC(sc)) {
17193                REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
17194                continue;
17195            }
17196
17197            bxe_pretend_func(sc, abs_func_id);
17198
17199            /* clear pf enable */
17200            bxe_pf_disable(sc);
17201
17202            bxe_pretend_func(sc, SC_ABS_FUNC(sc));
17203        }
17204    }
17205
17206    BLOGD(sc, DBG_LOAD, "after pf disable\n");
17207
17208    ecore_init_block(sc, BLOCK_PXP, PHASE_COMMON);
17209
17210    if (CHIP_IS_E1(sc)) {
17211        /*
17212         * enable HW interrupt from PXP on USDM overflow
17213         * bit 16 on INT_MASK_0
17214         */
17215        REG_WR(sc, PXP_REG_PXP_INT_MASK_0, 0);
17216    }
17217
17218    ecore_init_block(sc, BLOCK_PXP2, PHASE_COMMON);
17219    bxe_init_pxp(sc);
17220
17221#ifdef __BIG_ENDIAN
17222    REG_WR(sc, PXP2_REG_RQ_QM_ENDIAN_M, 1);
17223    REG_WR(sc, PXP2_REG_RQ_TM_ENDIAN_M, 1);
17224    REG_WR(sc, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
17225    REG_WR(sc, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
17226    REG_WR(sc, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
17227    /* make sure this value is 0 */
17228    REG_WR(sc, PXP2_REG_RQ_HC_ENDIAN_M, 0);
17229
17230    //REG_WR(sc, PXP2_REG_RD_PBF_SWAP_MODE, 1);
17231    REG_WR(sc, PXP2_REG_RD_QM_SWAP_MODE, 1);
17232    REG_WR(sc, PXP2_REG_RD_TM_SWAP_MODE, 1);
17233    REG_WR(sc, PXP2_REG_RD_SRC_SWAP_MODE, 1);
17234    REG_WR(sc, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
17235#endif
17236
17237    ecore_ilt_init_page_size(sc, INITOP_SET);
17238
17239    if (CHIP_REV_IS_FPGA(sc) && CHIP_IS_E1H(sc)) {
17240        REG_WR(sc, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
17241    }
17242
17243    /* let the HW do it's magic... */
17244    DELAY(100000);
17245
17246    /* finish PXP init */
17247    val = REG_RD(sc, PXP2_REG_RQ_CFG_DONE);
17248    if (val != 1) {
17249        BLOGE(sc, "PXP2 CFG failed\n");
17250        return (-1);
17251    }
17252    val = REG_RD(sc, PXP2_REG_RD_INIT_DONE);
17253    if (val != 1) {
17254        BLOGE(sc, "PXP2 RD_INIT failed\n");
17255        return (-1);
17256    }
17257
17258    BLOGD(sc, DBG_LOAD, "after pxp init\n");
17259
17260    /*
17261     * Timer bug workaround for E2 only. We need to set the entire ILT to have
17262     * entries with value "0" and valid bit on. This needs to be done by the
17263     * first PF that is loaded in a path (i.e. common phase)
17264     */
17265    if (!CHIP_IS_E1x(sc)) {
17266/*
17267 * In E2 there is a bug in the timers block that can cause function 6 / 7
17268 * (i.e. vnic3) to start even if it is marked as "scan-off".
17269 * This occurs when a different function (func2,3) is being marked
17270 * as "scan-off". Real-life scenario for example: if a driver is being
17271 * load-unloaded while func6,7 are down. This will cause the timer to access
17272 * the ilt, translate to a logical address and send a request to read/write.
17273 * Since the ilt for the function that is down is not valid, this will cause
17274 * a translation error which is unrecoverable.
17275 * The Workaround is intended to make sure that when this happens nothing
17276 * fatal will occur. The workaround:
17277 *  1.  First PF driver which loads on a path will:
17278 *      a.  After taking the chip out of reset, by using pretend,
17279 *          it will write "0" to the following registers of
17280 *          the other vnics.
17281 *          REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
17282 *          REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
17283 *          REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
17284 *          And for itself it will write '1' to
17285 *          PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
17286 *          dmae-operations (writing to pram for example.)
17287 *          note: can be done for only function 6,7 but cleaner this
17288 *            way.
17289 *      b.  Write zero+valid to the entire ILT.
17290 *      c.  Init the first_timers_ilt_entry, last_timers_ilt_entry of
17291 *          VNIC3 (of that port). The range allocated will be the
17292 *          entire ILT. This is needed to prevent  ILT range error.
17293 *  2.  Any PF driver load flow:
17294 *      a.  ILT update with the physical addresses of the allocated
17295 *          logical pages.
17296 *      b.  Wait 20msec. - note that this timeout is needed to make
17297 *          sure there are no requests in one of the PXP internal
17298 *          queues with "old" ILT addresses.
17299 *      c.  PF enable in the PGLC.
17300 *      d.  Clear the was_error of the PF in the PGLC. (could have
17301 *          occurred while driver was down)
17302 *      e.  PF enable in the CFC (WEAK + STRONG)
17303 *      f.  Timers scan enable
17304 *  3.  PF driver unload flow:
17305 *      a.  Clear the Timers scan_en.
17306 *      b.  Polling for scan_on=0 for that PF.
17307 *      c.  Clear the PF enable bit in the PXP.
17308 *      d.  Clear the PF enable in the CFC (WEAK + STRONG)
17309 *      e.  Write zero+valid to all ILT entries (The valid bit must
17310 *          stay set)
17311 *      f.  If this is VNIC 3 of a port then also init
17312 *          first_timers_ilt_entry to zero and last_timers_ilt_entry
17313 *          to the last enrty in the ILT.
17314 *
17315 *      Notes:
17316 *      Currently the PF error in the PGLC is non recoverable.
17317 *      In the future the there will be a recovery routine for this error.
17318 *      Currently attention is masked.
17319 *      Having an MCP lock on the load/unload process does not guarantee that
17320 *      there is no Timer disable during Func6/7 enable. This is because the
17321 *      Timers scan is currently being cleared by the MCP on FLR.
17322 *      Step 2.d can be done only for PF6/7 and the driver can also check if
17323 *      there is error before clearing it. But the flow above is simpler and
17324 *      more general.
17325 *      All ILT entries are written by zero+valid and not just PF6/7
17326 *      ILT entries since in the future the ILT entries allocation for
17327 *      PF-s might be dynamic.
17328 */
17329        struct ilt_client_info ilt_cli;
17330        struct ecore_ilt ilt;
17331
17332        memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
17333        memset(&ilt, 0, sizeof(struct ecore_ilt));
17334
17335        /* initialize dummy TM client */
17336        ilt_cli.start      = 0;
17337        ilt_cli.end        = ILT_NUM_PAGE_ENTRIES - 1;
17338        ilt_cli.client_num = ILT_CLIENT_TM;
17339
17340        /*
17341         * Step 1: set zeroes to all ilt page entries with valid bit on
17342         * Step 2: set the timers first/last ilt entry to point
17343         * to the entire range to prevent ILT range error for 3rd/4th
17344         * vnic (this code assumes existence of the vnic)
17345         *
17346         * both steps performed by call to ecore_ilt_client_init_op()
17347         * with dummy TM client
17348         *
17349         * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
17350         * and his brother are split registers
17351         */
17352
17353        bxe_pretend_func(sc, (SC_PATH(sc) + 6));
17354        ecore_ilt_client_init_op_ilt(sc, &ilt, &ilt_cli, INITOP_CLEAR);
17355        bxe_pretend_func(sc, SC_ABS_FUNC(sc));
17356
17357        REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN, BXE_PXP_DRAM_ALIGN);
17358        REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_RD, BXE_PXP_DRAM_ALIGN);
17359        REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
17360    }
17361
17362    REG_WR(sc, PXP2_REG_RQ_DISABLE_INPUTS, 0);
17363    REG_WR(sc, PXP2_REG_RD_DISABLE_INPUTS, 0);
17364
17365    if (!CHIP_IS_E1x(sc)) {
17366        int factor = CHIP_REV_IS_EMUL(sc) ? 1000 :
17367                     (CHIP_REV_IS_FPGA(sc) ? 400 : 0);
17368
17369        ecore_init_block(sc, BLOCK_PGLUE_B, PHASE_COMMON);
17370        ecore_init_block(sc, BLOCK_ATC, PHASE_COMMON);
17371
17372        /* let the HW do it's magic... */
17373        do {
17374            DELAY(200000);
17375            val = REG_RD(sc, ATC_REG_ATC_INIT_DONE);
17376        } while (factor-- && (val != 1));
17377
17378        if (val != 1) {
17379            BLOGE(sc, "ATC_INIT failed\n");
17380            return (-1);
17381        }
17382    }
17383
17384    BLOGD(sc, DBG_LOAD, "after pglue and atc init\n");
17385
17386    ecore_init_block(sc, BLOCK_DMAE, PHASE_COMMON);
17387
17388    bxe_iov_init_dmae(sc);
17389
17390    /* clean the DMAE memory */
17391    sc->dmae_ready = 1;
17392    ecore_init_fill(sc, TSEM_REG_PRAM, 0, 8, 1);
17393
17394    ecore_init_block(sc, BLOCK_TCM, PHASE_COMMON);
17395
17396    ecore_init_block(sc, BLOCK_UCM, PHASE_COMMON);
17397
17398    ecore_init_block(sc, BLOCK_CCM, PHASE_COMMON);
17399
17400    ecore_init_block(sc, BLOCK_XCM, PHASE_COMMON);
17401
17402    bxe_read_dmae(sc, XSEM_REG_PASSIVE_BUFFER, 3);
17403    bxe_read_dmae(sc, CSEM_REG_PASSIVE_BUFFER, 3);
17404    bxe_read_dmae(sc, TSEM_REG_PASSIVE_BUFFER, 3);
17405    bxe_read_dmae(sc, USEM_REG_PASSIVE_BUFFER, 3);
17406
17407    ecore_init_block(sc, BLOCK_QM, PHASE_COMMON);
17408
17409    /* QM queues pointers table */
17410    ecore_qm_init_ptr_table(sc, sc->qm_cid_count, INITOP_SET);
17411
17412    /* soft reset pulse */
17413    REG_WR(sc, QM_REG_SOFT_RESET, 1);
17414    REG_WR(sc, QM_REG_SOFT_RESET, 0);
17415
17416    if (CNIC_SUPPORT(sc))
17417        ecore_init_block(sc, BLOCK_TM, PHASE_COMMON);
17418
17419    ecore_init_block(sc, BLOCK_DORQ, PHASE_COMMON);
17420    REG_WR(sc, DORQ_REG_DPM_CID_OFST, BXE_DB_SHIFT);
17421    if (!CHIP_REV_IS_SLOW(sc)) {
17422        /* enable hw interrupt from doorbell Q */
17423        REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
17424    }
17425
17426    ecore_init_block(sc, BLOCK_BRB1, PHASE_COMMON);
17427
17428    ecore_init_block(sc, BLOCK_PRS, PHASE_COMMON);
17429    REG_WR(sc, PRS_REG_A_PRSU_20, 0xf);
17430
17431    if (!CHIP_IS_E1(sc)) {
17432        REG_WR(sc, PRS_REG_E1HOV_MODE, sc->devinfo.mf_info.path_has_ovlan);
17433    }
17434
17435    if (!CHIP_IS_E1x(sc) && !CHIP_IS_E3B0(sc)) {
17436        if (IS_MF_AFEX(sc)) {
17437            /*
17438             * configure that AFEX and VLAN headers must be
17439             * received in AFEX mode
17440             */
17441            REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC, 0xE);
17442            REG_WR(sc, PRS_REG_MUST_HAVE_HDRS, 0xA);
17443            REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
17444            REG_WR(sc, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
17445            REG_WR(sc, PRS_REG_TAG_LEN_0, 0x4);
17446        } else {
17447            /*
17448             * Bit-map indicating which L2 hdrs may appear
17449             * after the basic Ethernet header
17450             */
17451            REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC,
17452                   sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);
17453        }
17454    }
17455
17456    ecore_init_block(sc, BLOCK_TSDM, PHASE_COMMON);
17457    ecore_init_block(sc, BLOCK_CSDM, PHASE_COMMON);
17458    ecore_init_block(sc, BLOCK_USDM, PHASE_COMMON);
17459    ecore_init_block(sc, BLOCK_XSDM, PHASE_COMMON);
17460
17461    if (!CHIP_IS_E1x(sc)) {
17462        /* reset VFC memories */
17463        REG_WR(sc, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
17464               VFC_MEMORIES_RST_REG_CAM_RST |
17465               VFC_MEMORIES_RST_REG_RAM_RST);
17466        REG_WR(sc, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
17467               VFC_MEMORIES_RST_REG_CAM_RST |
17468               VFC_MEMORIES_RST_REG_RAM_RST);
17469
17470        DELAY(20000);
17471    }
17472
17473    ecore_init_block(sc, BLOCK_TSEM, PHASE_COMMON);
17474    ecore_init_block(sc, BLOCK_USEM, PHASE_COMMON);
17475    ecore_init_block(sc, BLOCK_CSEM, PHASE_COMMON);
17476    ecore_init_block(sc, BLOCK_XSEM, PHASE_COMMON);
17477
17478    /* sync semi rtc */
17479    REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
17480           0x80000000);
17481    REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
17482           0x80000000);
17483
17484    ecore_init_block(sc, BLOCK_UPB, PHASE_COMMON);
17485    ecore_init_block(sc, BLOCK_XPB, PHASE_COMMON);
17486    ecore_init_block(sc, BLOCK_PBF, PHASE_COMMON);
17487
17488    if (!CHIP_IS_E1x(sc)) {
17489        if (IS_MF_AFEX(sc)) {
17490            /*
17491             * configure that AFEX and VLAN headers must be
17492             * sent in AFEX mode
17493             */
17494            REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC, 0xE);
17495            REG_WR(sc, PBF_REG_MUST_HAVE_HDRS, 0xA);
17496            REG_WR(sc, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
17497            REG_WR(sc, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
17498            REG_WR(sc, PBF_REG_TAG_LEN_0, 0x4);
17499        } else {
17500            REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC,
17501                   sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);
17502        }
17503    }
17504
17505    REG_WR(sc, SRC_REG_SOFT_RST, 1);
17506
17507    ecore_init_block(sc, BLOCK_SRC, PHASE_COMMON);
17508
17509    if (CNIC_SUPPORT(sc)) {
17510        REG_WR(sc, SRC_REG_KEYSEARCH_0, 0x63285672);
17511        REG_WR(sc, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
17512        REG_WR(sc, SRC_REG_KEYSEARCH_2, 0x223aef9b);
17513        REG_WR(sc, SRC_REG_KEYSEARCH_3, 0x26001e3a);
17514        REG_WR(sc, SRC_REG_KEYSEARCH_4, 0x7ae91116);
17515        REG_WR(sc, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
17516        REG_WR(sc, SRC_REG_KEYSEARCH_6, 0x298d8adf);
17517        REG_WR(sc, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
17518        REG_WR(sc, SRC_REG_KEYSEARCH_8, 0x1830f82f);
17519        REG_WR(sc, SRC_REG_KEYSEARCH_9, 0x01e46be7);
17520    }
17521    REG_WR(sc, SRC_REG_SOFT_RST, 0);
17522
17523    if (sizeof(union cdu_context) != 1024) {
17524        /* we currently assume that a context is 1024 bytes */
17525        BLOGE(sc, "please adjust the size of cdu_context(%ld)\n",
17526              (long)sizeof(union cdu_context));
17527    }
17528
17529    ecore_init_block(sc, BLOCK_CDU, PHASE_COMMON);
17530    val = (4 << 24) + (0 << 12) + 1024;
17531    REG_WR(sc, CDU_REG_CDU_GLOBAL_PARAMS, val);
17532
17533    ecore_init_block(sc, BLOCK_CFC, PHASE_COMMON);
17534
17535    REG_WR(sc, CFC_REG_INIT_REG, 0x7FF);
17536    /* enable context validation interrupt from CFC */
17537    REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
17538
17539    /* set the thresholds to prevent CFC/CDU race */
17540    REG_WR(sc, CFC_REG_DEBUG0, 0x20020000);
17541    ecore_init_block(sc, BLOCK_HC, PHASE_COMMON);
17542
17543    if (!CHIP_IS_E1x(sc) && BXE_NOMCP(sc)) {
17544        REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x36);
17545    }
17546
17547    ecore_init_block(sc, BLOCK_IGU, PHASE_COMMON);
17548    ecore_init_block(sc, BLOCK_MISC_AEU, PHASE_COMMON);
17549
17550    /* Reset PCIE errors for debug */
17551    REG_WR(sc, 0x2814, 0xffffffff);
17552    REG_WR(sc, 0x3820, 0xffffffff);
17553
17554    if (!CHIP_IS_E1x(sc)) {
17555        REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
17556               (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
17557                PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
17558        REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
17559               (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
17560                PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
17561                PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
17562        REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
17563               (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
17564                PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
17565                PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
17566    }
17567
17568    ecore_init_block(sc, BLOCK_NIG, PHASE_COMMON);
17569
17570    if (!CHIP_IS_E1(sc)) {
17571        /* in E3 this done in per-port section */
17572        if (!CHIP_IS_E3(sc))
17573            REG_WR(sc, NIG_REG_LLH_MF_MODE, IS_MF(sc));
17574    }
17575
17576    if (CHIP_IS_E1H(sc)) {
17577        /* not applicable for E2 (and above ...) */
17578        REG_WR(sc, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(sc));
17579    }
17580
17581    if (CHIP_REV_IS_SLOW(sc)) {
17582        DELAY(200000);
17583    }
17584
17585    /* finish CFC init */
17586    val = reg_poll(sc, CFC_REG_LL_INIT_DONE, 1, 100, 10);
17587    if (val != 1) {
17588        BLOGE(sc, "CFC LL_INIT failed\n");
17589        return (-1);
17590    }
17591    val = reg_poll(sc, CFC_REG_AC_INIT_DONE, 1, 100, 10);
17592    if (val != 1) {
17593        BLOGE(sc, "CFC AC_INIT failed\n");
17594        return (-1);
17595    }
17596    val = reg_poll(sc, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
17597    if (val != 1) {
17598        BLOGE(sc, "CFC CAM_INIT failed\n");
17599        return (-1);
17600    }
17601    REG_WR(sc, CFC_REG_DEBUG0, 0);
17602
17603    if (CHIP_IS_E1(sc)) {
17604        /* read NIG statistic to see if this is our first up since powerup */
17605        bxe_read_dmae(sc, NIG_REG_STAT2_BRB_OCTET, 2);
17606        val = *BXE_SP(sc, wb_data[0]);
17607
17608        /* do internal memory self test */
17609        if ((val == 0) && bxe_int_mem_test(sc)) {
17610            BLOGE(sc, "internal mem self test failed\n");
17611            return (-1);
17612        }
17613    }
17614
17615    bxe_setup_fan_failure_detection(sc);
17616
17617    /* clear PXP2 attentions */
17618    REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
17619
17620    bxe_enable_blocks_attention(sc);
17621
17622    if (!CHIP_REV_IS_SLOW(sc)) {
17623        ecore_enable_blocks_parity(sc);
17624    }
17625
17626    if (!BXE_NOMCP(sc)) {
17627        if (CHIP_IS_E1x(sc)) {
17628            bxe_common_init_phy(sc);
17629        }
17630    }
17631
17632    return (0);
17633}
17634
17635/**
17636 * bxe_init_hw_common_chip - init HW at the COMMON_CHIP phase.
17637 *
17638 * @sc:     driver handle
17639 */
17640static int
17641bxe_init_hw_common_chip(struct bxe_softc *sc)
17642{
17643    int rc = bxe_init_hw_common(sc);
17644
17645    if (rc) {
17646        return (rc);
17647    }
17648
17649    /* In E2 2-PORT mode, same ext phy is used for the two paths */
17650    if (!BXE_NOMCP(sc)) {
17651        bxe_common_init_phy(sc);
17652    }
17653
17654    return (0);
17655}
17656
17657static int
17658bxe_init_hw_port(struct bxe_softc *sc)
17659{
17660    int port = SC_PORT(sc);
17661    int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
17662    uint32_t low, high;
17663    uint32_t val;
17664
17665    BLOGD(sc, DBG_LOAD, "starting port init for port %d\n", port);
17666
17667    REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
17668
17669    ecore_init_block(sc, BLOCK_MISC, init_phase);
17670    ecore_init_block(sc, BLOCK_PXP, init_phase);
17671    ecore_init_block(sc, BLOCK_PXP2, init_phase);
17672
17673    /*
17674     * Timers bug workaround: disables the pf_master bit in pglue at
17675     * common phase, we need to enable it here before any dmae access are
17676     * attempted. Therefore we manually added the enable-master to the
17677     * port phase (it also happens in the function phase)
17678     */
17679    if (!CHIP_IS_E1x(sc)) {
17680        REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
17681    }
17682
17683    ecore_init_block(sc, BLOCK_ATC, init_phase);
17684    ecore_init_block(sc, BLOCK_DMAE, init_phase);
17685    ecore_init_block(sc, BLOCK_PGLUE_B, init_phase);
17686    ecore_init_block(sc, BLOCK_QM, init_phase);
17687
17688    ecore_init_block(sc, BLOCK_TCM, init_phase);
17689    ecore_init_block(sc, BLOCK_UCM, init_phase);
17690    ecore_init_block(sc, BLOCK_CCM, init_phase);
17691    ecore_init_block(sc, BLOCK_XCM, init_phase);
17692
17693    /* QM cid (connection) count */
17694    ecore_qm_init_cid_count(sc, sc->qm_cid_count, INITOP_SET);
17695
17696    if (CNIC_SUPPORT(sc)) {
17697        ecore_init_block(sc, BLOCK_TM, init_phase);
17698        REG_WR(sc, TM_REG_LIN0_SCAN_TIME + port*4, 20);
17699        REG_WR(sc, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
17700    }
17701
17702    ecore_init_block(sc, BLOCK_DORQ, init_phase);
17703
17704    ecore_init_block(sc, BLOCK_BRB1, init_phase);
17705
17706    if (CHIP_IS_E1(sc) || CHIP_IS_E1H(sc)) {
17707        if (IS_MF(sc)) {
17708            low = (BXE_ONE_PORT(sc) ? 160 : 246);
17709        } else if (sc->mtu > 4096) {
17710            if (BXE_ONE_PORT(sc)) {
17711                low = 160;
17712            } else {
17713                val = sc->mtu;
17714                /* (24*1024 + val*4)/256 */
17715                low = (96 + (val / 64) + ((val % 64) ? 1 : 0));
17716            }
17717        } else {
17718            low = (BXE_ONE_PORT(sc) ? 80 : 160);
17719        }
17720        high = (low + 56); /* 14*1024/256 */
17721        REG_WR(sc, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
17722        REG_WR(sc, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
17723    }
17724
17725    if (CHIP_IS_MODE_4_PORT(sc)) {
17726        REG_WR(sc, SC_PORT(sc) ?
17727               BRB1_REG_MAC_GUARANTIED_1 :
17728               BRB1_REG_MAC_GUARANTIED_0, 40);
17729    }
17730
17731    ecore_init_block(sc, BLOCK_PRS, init_phase);
17732    if (CHIP_IS_E3B0(sc)) {
17733        if (IS_MF_AFEX(sc)) {
17734            /* configure headers for AFEX mode */
17735            REG_WR(sc, SC_PORT(sc) ?
17736                   PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
17737                   PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE);
17738            REG_WR(sc, SC_PORT(sc) ?
17739                   PRS_REG_HDRS_AFTER_TAG_0_PORT_1 :
17740                   PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6);
17741            REG_WR(sc, SC_PORT(sc) ?
17742                   PRS_REG_MUST_HAVE_HDRS_PORT_1 :
17743                   PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
17744        } else {
17745            /* Ovlan exists only if we are in multi-function +
17746             * switch-dependent mode, in switch-independent there
17747             * is no ovlan headers
17748             */
17749            REG_WR(sc, SC_PORT(sc) ?
17750                   PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
17751                   PRS_REG_HDRS_AFTER_BASIC_PORT_0,
17752                   (sc->devinfo.mf_info.path_has_ovlan ? 7 : 6));
17753        }
17754    }
17755
17756    ecore_init_block(sc, BLOCK_TSDM, init_phase);
17757    ecore_init_block(sc, BLOCK_CSDM, init_phase);
17758    ecore_init_block(sc, BLOCK_USDM, init_phase);
17759    ecore_init_block(sc, BLOCK_XSDM, init_phase);
17760
17761    ecore_init_block(sc, BLOCK_TSEM, init_phase);
17762    ecore_init_block(sc, BLOCK_USEM, init_phase);
17763    ecore_init_block(sc, BLOCK_CSEM, init_phase);
17764    ecore_init_block(sc, BLOCK_XSEM, init_phase);
17765
17766    ecore_init_block(sc, BLOCK_UPB, init_phase);
17767    ecore_init_block(sc, BLOCK_XPB, init_phase);
17768
17769    ecore_init_block(sc, BLOCK_PBF, init_phase);
17770
17771    if (CHIP_IS_E1x(sc)) {
17772        /* configure PBF to work without PAUSE mtu 9000 */
17773        REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
17774
17775        /* update threshold */
17776        REG_WR(sc, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
17777        /* update init credit */
17778        REG_WR(sc, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
17779
17780        /* probe changes */
17781        REG_WR(sc, PBF_REG_INIT_P0 + port*4, 1);
17782        DELAY(50);
17783        REG_WR(sc, PBF_REG_INIT_P0 + port*4, 0);
17784    }
17785
17786    if (CNIC_SUPPORT(sc)) {
17787        ecore_init_block(sc, BLOCK_SRC, init_phase);
17788    }
17789
17790    ecore_init_block(sc, BLOCK_CDU, init_phase);
17791    ecore_init_block(sc, BLOCK_CFC, init_phase);
17792
17793    if (CHIP_IS_E1(sc)) {
17794        REG_WR(sc, HC_REG_LEADING_EDGE_0 + port*8, 0);
17795        REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port*8, 0);
17796    }
17797    ecore_init_block(sc, BLOCK_HC, init_phase);
17798
17799    ecore_init_block(sc, BLOCK_IGU, init_phase);
17800
17801    ecore_init_block(sc, BLOCK_MISC_AEU, init_phase);
17802    /* init aeu_mask_attn_func_0/1:
17803     *  - SF mode: bits 3-7 are masked. only bits 0-2 are in use
17804     *  - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
17805     *             bits 4-7 are used for "per vn group attention" */
17806    val = IS_MF(sc) ? 0xF7 : 0x7;
17807    /* Enable DCBX attention for all but E1 */
17808    val |= CHIP_IS_E1(sc) ? 0 : 0x10;
17809    REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
17810
17811    ecore_init_block(sc, BLOCK_NIG, init_phase);
17812
17813    if (!CHIP_IS_E1x(sc)) {
17814        /* Bit-map indicating which L2 hdrs may appear after the
17815         * basic Ethernet header
17816         */
17817        if (IS_MF_AFEX(sc)) {
17818            REG_WR(sc, SC_PORT(sc) ?
17819                   NIG_REG_P1_HDRS_AFTER_BASIC :
17820                   NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
17821        } else {
17822            REG_WR(sc, SC_PORT(sc) ?
17823                   NIG_REG_P1_HDRS_AFTER_BASIC :
17824                   NIG_REG_P0_HDRS_AFTER_BASIC,
17825                   IS_MF_SD(sc) ? 7 : 6);
17826        }
17827
17828        if (CHIP_IS_E3(sc)) {
17829            REG_WR(sc, SC_PORT(sc) ?
17830                   NIG_REG_LLH1_MF_MODE :
17831                   NIG_REG_LLH_MF_MODE, IS_MF(sc));
17832        }
17833    }
17834    if (!CHIP_IS_E3(sc)) {
17835        REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
17836    }
17837
17838    if (!CHIP_IS_E1(sc)) {
17839        /* 0x2 disable mf_ov, 0x1 enable */
17840        REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
17841               (IS_MF_SD(sc) ? 0x1 : 0x2));
17842
17843        if (!CHIP_IS_E1x(sc)) {
17844            val = 0;
17845            switch (sc->devinfo.mf_info.mf_mode) {
17846            case MULTI_FUNCTION_SD:
17847                val = 1;
17848                break;
17849            case MULTI_FUNCTION_SI:
17850            case MULTI_FUNCTION_AFEX:
17851                val = 2;
17852                break;
17853            }
17854
17855            REG_WR(sc, (SC_PORT(sc) ? NIG_REG_LLH1_CLS_TYPE :
17856                        NIG_REG_LLH0_CLS_TYPE), val);
17857        }
17858        REG_WR(sc, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
17859        REG_WR(sc, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
17860        REG_WR(sc, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
17861    }
17862
17863    /* If SPIO5 is set to generate interrupts, enable it for this port */
17864    val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
17865    if (val & MISC_SPIO_SPIO5) {
17866        uint32_t reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
17867                                    MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
17868        val = REG_RD(sc, reg_addr);
17869        val |= AEU_INPUTS_ATTN_BITS_SPIO5;
17870        REG_WR(sc, reg_addr, val);
17871    }
17872
17873    return (0);
17874}
17875
17876static uint32_t
17877bxe_flr_clnup_reg_poll(struct bxe_softc *sc,
17878                       uint32_t         reg,
17879                       uint32_t         expected,
17880                       uint32_t         poll_count)
17881{
17882    uint32_t cur_cnt = poll_count;
17883    uint32_t val;
17884
17885    while ((val = REG_RD(sc, reg)) != expected && cur_cnt--) {
17886        DELAY(FLR_WAIT_INTERVAL);
17887    }
17888
17889    return (val);
17890}
17891
17892static int
17893bxe_flr_clnup_poll_hw_counter(struct bxe_softc *sc,
17894                              uint32_t         reg,
17895                              char             *msg,
17896                              uint32_t         poll_cnt)
17897{
17898    uint32_t val = bxe_flr_clnup_reg_poll(sc, reg, 0, poll_cnt);
17899
17900    if (val != 0) {
17901        BLOGE(sc, "%s usage count=%d\n", msg, val);
17902        return (1);
17903    }
17904
17905    return (0);
17906}
17907
17908/* Common routines with VF FLR cleanup */
17909static uint32_t
17910bxe_flr_clnup_poll_count(struct bxe_softc *sc)
17911{
17912    /* adjust polling timeout */
17913    if (CHIP_REV_IS_EMUL(sc)) {
17914        return (FLR_POLL_CNT * 2000);
17915    }
17916
17917    if (CHIP_REV_IS_FPGA(sc)) {
17918        return (FLR_POLL_CNT * 120);
17919    }
17920
17921    return (FLR_POLL_CNT);
17922}
17923
17924static int
17925bxe_poll_hw_usage_counters(struct bxe_softc *sc,
17926                           uint32_t         poll_cnt)
17927{
17928    /* wait for CFC PF usage-counter to zero (includes all the VFs) */
17929    if (bxe_flr_clnup_poll_hw_counter(sc,
17930                                      CFC_REG_NUM_LCIDS_INSIDE_PF,
17931                                      "CFC PF usage counter timed out",
17932                                      poll_cnt)) {
17933        return (1);
17934    }
17935
17936    /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
17937    if (bxe_flr_clnup_poll_hw_counter(sc,
17938                                      DORQ_REG_PF_USAGE_CNT,
17939                                      "DQ PF usage counter timed out",
17940                                      poll_cnt)) {
17941        return (1);
17942    }
17943
17944    /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
17945    if (bxe_flr_clnup_poll_hw_counter(sc,
17946                                      QM_REG_PF_USG_CNT_0 + 4*SC_FUNC(sc),
17947                                      "QM PF usage counter timed out",
17948                                      poll_cnt)) {
17949        return (1);
17950    }
17951
17952    /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
17953    if (bxe_flr_clnup_poll_hw_counter(sc,
17954                                      TM_REG_LIN0_VNIC_UC + 4*SC_PORT(sc),
17955                                      "Timers VNIC usage counter timed out",
17956                                      poll_cnt)) {
17957        return (1);
17958    }
17959
17960    if (bxe_flr_clnup_poll_hw_counter(sc,
17961                                      TM_REG_LIN0_NUM_SCANS + 4*SC_PORT(sc),
17962                                      "Timers NUM_SCANS usage counter timed out",
17963                                      poll_cnt)) {
17964        return (1);
17965    }
17966
17967    /* Wait DMAE PF usage counter to zero */
17968    if (bxe_flr_clnup_poll_hw_counter(sc,
17969                                      dmae_reg_go_c[INIT_DMAE_C(sc)],
17970                                      "DMAE dommand register timed out",
17971                                      poll_cnt)) {
17972        return (1);
17973    }
17974
17975    return (0);
17976}
17977
17978#define OP_GEN_PARAM(param)                                            \
17979    (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
17980#define OP_GEN_TYPE(type)                                           \
17981    (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
17982#define OP_GEN_AGG_VECT(index)                                             \
17983    (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
17984
17985static int
17986bxe_send_final_clnup(struct bxe_softc *sc,
17987                     uint8_t          clnup_func,
17988                     uint32_t         poll_cnt)
17989{
17990    uint32_t op_gen_command = 0;
17991    uint32_t comp_addr = (BAR_CSTRORM_INTMEM +
17992                          CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func));
17993    int ret = 0;
17994
17995    if (REG_RD(sc, comp_addr)) {
17996        BLOGE(sc, "Cleanup complete was not 0 before sending\n");
17997        return (1);
17998    }
17999
18000    op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
18001    op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
18002    op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
18003    op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
18004
18005    BLOGD(sc, DBG_LOAD, "sending FW Final cleanup\n");
18006    REG_WR(sc, XSDM_REG_OPERATION_GEN, op_gen_command);
18007
18008    if (bxe_flr_clnup_reg_poll(sc, comp_addr, 1, poll_cnt) != 1) {
18009        BLOGE(sc, "FW final cleanup did not succeed\n");
18010        BLOGD(sc, DBG_LOAD, "At timeout completion address contained %x\n",
18011              (REG_RD(sc, comp_addr)));
18012        bxe_panic(sc, ("FLR cleanup failed\n"));
18013        return (1);
18014    }
18015
18016    /* Zero completion for nxt FLR */
18017    REG_WR(sc, comp_addr, 0);
18018
18019    return (ret);
18020}
18021
18022static void
18023bxe_pbf_pN_buf_flushed(struct bxe_softc       *sc,
18024                       struct pbf_pN_buf_regs *regs,
18025                       uint32_t               poll_count)
18026{
18027    uint32_t init_crd, crd, crd_start, crd_freed, crd_freed_start;
18028    uint32_t cur_cnt = poll_count;
18029
18030    crd_freed = crd_freed_start = REG_RD(sc, regs->crd_freed);
18031    crd = crd_start = REG_RD(sc, regs->crd);
18032    init_crd = REG_RD(sc, regs->init_crd);
18033
18034    BLOGD(sc, DBG_LOAD, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
18035    BLOGD(sc, DBG_LOAD, "CREDIT[%d]      : s:%x\n", regs->pN, crd);
18036    BLOGD(sc, DBG_LOAD, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
18037
18038    while ((crd != init_crd) &&
18039           ((uint32_t)((int32_t)crd_freed - (int32_t)crd_freed_start) <
18040            (init_crd - crd_start))) {
18041        if (cur_cnt--) {
18042            DELAY(FLR_WAIT_INTERVAL);
18043            crd = REG_RD(sc, regs->crd);
18044            crd_freed = REG_RD(sc, regs->crd_freed);
18045        } else {
18046            BLOGD(sc, DBG_LOAD, "PBF tx buffer[%d] timed out\n", regs->pN);
18047            BLOGD(sc, DBG_LOAD, "CREDIT[%d]      : c:%x\n", regs->pN, crd);
18048            BLOGD(sc, DBG_LOAD, "CREDIT_FREED[%d]: c:%x\n", regs->pN, crd_freed);
18049            break;
18050        }
18051    }
18052
18053    BLOGD(sc, DBG_LOAD, "Waited %d*%d usec for PBF tx buffer[%d]\n",
18054          poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
18055}
18056
18057static void
18058bxe_pbf_pN_cmd_flushed(struct bxe_softc       *sc,
18059                       struct pbf_pN_cmd_regs *regs,
18060                       uint32_t               poll_count)
18061{
18062    uint32_t occup, to_free, freed, freed_start;
18063    uint32_t cur_cnt = poll_count;
18064
18065    occup = to_free = REG_RD(sc, regs->lines_occup);
18066    freed = freed_start = REG_RD(sc, regs->lines_freed);
18067
18068    BLOGD(sc, DBG_LOAD, "OCCUPANCY[%d]   : s:%x\n", regs->pN, occup);
18069    BLOGD(sc, DBG_LOAD, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
18070
18071    while (occup &&
18072           ((uint32_t)((int32_t)freed - (int32_t)freed_start) < to_free)) {
18073        if (cur_cnt--) {
18074            DELAY(FLR_WAIT_INTERVAL);
18075            occup = REG_RD(sc, regs->lines_occup);
18076            freed = REG_RD(sc, regs->lines_freed);
18077        } else {
18078            BLOGD(sc, DBG_LOAD, "PBF cmd queue[%d] timed out\n", regs->pN);
18079            BLOGD(sc, DBG_LOAD, "OCCUPANCY[%d]   : s:%x\n", regs->pN, occup);
18080            BLOGD(sc, DBG_LOAD, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
18081            break;
18082        }
18083    }
18084
18085    BLOGD(sc, DBG_LOAD, "Waited %d*%d usec for PBF cmd queue[%d]\n",
18086          poll_count - cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
18087}
18088
18089static void
18090bxe_tx_hw_flushed(struct bxe_softc *sc, uint32_t poll_count)
18091{
18092    struct pbf_pN_cmd_regs cmd_regs[] = {
18093        {0, (CHIP_IS_E3B0(sc)) ?
18094            PBF_REG_TQ_OCCUPANCY_Q0 :
18095            PBF_REG_P0_TQ_OCCUPANCY,
18096            (CHIP_IS_E3B0(sc)) ?
18097            PBF_REG_TQ_LINES_FREED_CNT_Q0 :
18098            PBF_REG_P0_TQ_LINES_FREED_CNT},
18099        {1, (CHIP_IS_E3B0(sc)) ?
18100            PBF_REG_TQ_OCCUPANCY_Q1 :
18101            PBF_REG_P1_TQ_OCCUPANCY,
18102            (CHIP_IS_E3B0(sc)) ?
18103            PBF_REG_TQ_LINES_FREED_CNT_Q1 :
18104            PBF_REG_P1_TQ_LINES_FREED_CNT},
18105        {4, (CHIP_IS_E3B0(sc)) ?
18106            PBF_REG_TQ_OCCUPANCY_LB_Q :
18107            PBF_REG_P4_TQ_OCCUPANCY,
18108            (CHIP_IS_E3B0(sc)) ?
18109            PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
18110            PBF_REG_P4_TQ_LINES_FREED_CNT}
18111    };
18112
18113    struct pbf_pN_buf_regs buf_regs[] = {
18114        {0, (CHIP_IS_E3B0(sc)) ?
18115            PBF_REG_INIT_CRD_Q0 :
18116            PBF_REG_P0_INIT_CRD ,
18117            (CHIP_IS_E3B0(sc)) ?
18118            PBF_REG_CREDIT_Q0 :
18119            PBF_REG_P0_CREDIT,
18120            (CHIP_IS_E3B0(sc)) ?
18121            PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
18122            PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
18123        {1, (CHIP_IS_E3B0(sc)) ?
18124            PBF_REG_INIT_CRD_Q1 :
18125            PBF_REG_P1_INIT_CRD,
18126            (CHIP_IS_E3B0(sc)) ?
18127            PBF_REG_CREDIT_Q1 :
18128            PBF_REG_P1_CREDIT,
18129            (CHIP_IS_E3B0(sc)) ?
18130            PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
18131            PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
18132        {4, (CHIP_IS_E3B0(sc)) ?
18133            PBF_REG_INIT_CRD_LB_Q :
18134            PBF_REG_P4_INIT_CRD,
18135            (CHIP_IS_E3B0(sc)) ?
18136            PBF_REG_CREDIT_LB_Q :
18137            PBF_REG_P4_CREDIT,
18138            (CHIP_IS_E3B0(sc)) ?
18139            PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
18140            PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
18141    };
18142
18143    int i;
18144
18145    /* Verify the command queues are flushed P0, P1, P4 */
18146    for (i = 0; i < ARRAY_SIZE(cmd_regs); i++) {
18147        bxe_pbf_pN_cmd_flushed(sc, &cmd_regs[i], poll_count);
18148    }
18149
18150    /* Verify the transmission buffers are flushed P0, P1, P4 */
18151    for (i = 0; i < ARRAY_SIZE(buf_regs); i++) {
18152        bxe_pbf_pN_buf_flushed(sc, &buf_regs[i], poll_count);
18153    }
18154}
18155
18156static void
18157bxe_hw_enable_status(struct bxe_softc *sc)
18158{
18159    uint32_t val;
18160
18161    val = REG_RD(sc, CFC_REG_WEAK_ENABLE_PF);
18162    BLOGD(sc, DBG_LOAD, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
18163
18164    val = REG_RD(sc, PBF_REG_DISABLE_PF);
18165    BLOGD(sc, DBG_LOAD, "PBF_REG_DISABLE_PF is 0x%x\n", val);
18166
18167    val = REG_RD(sc, IGU_REG_PCI_PF_MSI_EN);
18168    BLOGD(sc, DBG_LOAD, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
18169
18170    val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_EN);
18171    BLOGD(sc, DBG_LOAD, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
18172
18173    val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
18174    BLOGD(sc, DBG_LOAD, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
18175
18176    val = REG_RD(sc, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
18177    BLOGD(sc, DBG_LOAD, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
18178
18179    val = REG_RD(sc, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
18180    BLOGD(sc, DBG_LOAD, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
18181
18182    val = REG_RD(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
18183    BLOGD(sc, DBG_LOAD, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n", val);
18184}
18185
18186static int
18187bxe_pf_flr_clnup(struct bxe_softc *sc)
18188{
18189    uint32_t poll_cnt = bxe_flr_clnup_poll_count(sc);
18190
18191    BLOGD(sc, DBG_LOAD, "Cleanup after FLR PF[%d]\n", SC_ABS_FUNC(sc));
18192
18193    /* Re-enable PF target read access */
18194    REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
18195
18196    /* Poll HW usage counters */
18197    BLOGD(sc, DBG_LOAD, "Polling usage counters\n");
18198    if (bxe_poll_hw_usage_counters(sc, poll_cnt)) {
18199        return (-1);
18200    }
18201
18202    /* Zero the igu 'trailing edge' and 'leading edge' */
18203
18204    /* Send the FW cleanup command */
18205    if (bxe_send_final_clnup(sc, (uint8_t)SC_FUNC(sc), poll_cnt)) {
18206        return (-1);
18207    }
18208
18209    /* ATC cleanup */
18210
18211    /* Verify TX hw is flushed */
18212    bxe_tx_hw_flushed(sc, poll_cnt);
18213
18214    /* Wait 100ms (not adjusted according to platform) */
18215    DELAY(100000);
18216
18217    /* Verify no pending pci transactions */
18218    if (bxe_is_pcie_pending(sc)) {
18219        BLOGE(sc, "PCIE Transactions still pending\n");
18220    }
18221
18222    /* Debug */
18223    bxe_hw_enable_status(sc);
18224
18225    /*
18226     * Master enable - Due to WB DMAE writes performed before this
18227     * register is re-initialized as part of the regular function init
18228     */
18229    REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
18230
18231    return (0);
18232}
18233
18234#if 0
18235static void
18236bxe_init_searcher(struct bxe_softc *sc)
18237{
18238    int port = SC_PORT(sc);
18239    ecore_src_init_t2(sc, sc->t2, sc->t2_mapping, SRC_CONN_NUM);
18240    /* T1 hash bits value determines the T1 number of entries */
18241    REG_WR(sc, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
18242}
18243#endif
18244
18245static int
18246bxe_init_hw_func(struct bxe_softc *sc)
18247{
18248    int port = SC_PORT(sc);
18249    int func = SC_FUNC(sc);
18250    int init_phase = PHASE_PF0 + func;
18251    struct ecore_ilt *ilt = sc->ilt;
18252    uint16_t cdu_ilt_start;
18253    uint32_t addr, val;
18254    uint32_t main_mem_base, main_mem_size, main_mem_prty_clr;
18255    int i, main_mem_width, rc;
18256
18257    BLOGD(sc, DBG_LOAD, "starting func init for func %d\n", func);
18258
18259    /* FLR cleanup */
18260    if (!CHIP_IS_E1x(sc)) {
18261        rc = bxe_pf_flr_clnup(sc);
18262        if (rc) {
18263            BLOGE(sc, "FLR cleanup failed!\n");
18264            // XXX bxe_fw_dump(sc);
18265            // XXX bxe_idle_chk(sc);
18266            return (rc);
18267        }
18268    }
18269
18270    /* set MSI reconfigure capability */
18271    if (sc->devinfo.int_block == INT_BLOCK_HC) {
18272        addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
18273        val = REG_RD(sc, addr);
18274        val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
18275        REG_WR(sc, addr, val);
18276    }
18277
18278    ecore_init_block(sc, BLOCK_PXP, init_phase);
18279    ecore_init_block(sc, BLOCK_PXP2, init_phase);
18280
18281    ilt = sc->ilt;
18282    cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
18283
18284#if 0
18285    if (IS_SRIOV(sc)) {
18286        cdu_ilt_start += BXE_FIRST_VF_CID/ILT_PAGE_CIDS;
18287    }
18288    cdu_ilt_start = bxe_iov_init_ilt(sc, cdu_ilt_start);
18289
18290#if (BXE_FIRST_VF_CID > 0)
18291    /*
18292     * If BXE_FIRST_VF_CID > 0 then the PF L2 cids precedes
18293     * those of the VFs, so start line should be reset
18294     */
18295    cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
18296#endif
18297#endif
18298
18299    for (i = 0; i < L2_ILT_LINES(sc); i++) {
18300        ilt->lines[cdu_ilt_start + i].page = sc->context[i].vcxt;
18301        ilt->lines[cdu_ilt_start + i].page_mapping =
18302            sc->context[i].vcxt_dma.paddr;
18303        ilt->lines[cdu_ilt_start + i].size = sc->context[i].size;
18304    }
18305    ecore_ilt_init_op(sc, INITOP_SET);
18306
18307#if 0
18308    if (!CONFIGURE_NIC_MODE(sc)) {
18309        bxe_init_searcher(sc);
18310        REG_WR(sc, PRS_REG_NIC_MODE, 0);
18311        BLOGD(sc, DBG_LOAD, "NIC MODE disabled\n");
18312    } else
18313#endif
18314    {
18315        /* Set NIC mode */
18316        REG_WR(sc, PRS_REG_NIC_MODE, 1);
18317        BLOGD(sc, DBG_LOAD, "NIC MODE configured\n");
18318    }
18319
18320    if (!CHIP_IS_E1x(sc)) {
18321        uint32_t pf_conf = IGU_PF_CONF_FUNC_EN;
18322
18323        /* Turn on a single ISR mode in IGU if driver is going to use
18324         * INT#x or MSI
18325         */
18326        if (sc->interrupt_mode != INTR_MODE_MSIX) {
18327            pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
18328        }
18329
18330        /*
18331         * Timers workaround bug: function init part.
18332         * Need to wait 20msec after initializing ILT,
18333         * needed to make sure there are no requests in
18334         * one of the PXP internal queues with "old" ILT addresses
18335         */
18336        DELAY(20000);
18337
18338        /*
18339         * Master enable - Due to WB DMAE writes performed before this
18340         * register is re-initialized as part of the regular function
18341         * init
18342         */
18343        REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
18344        /* Enable the function in IGU */
18345        REG_WR(sc, IGU_REG_PF_CONFIGURATION, pf_conf);
18346    }
18347
18348    sc->dmae_ready = 1;
18349
18350    ecore_init_block(sc, BLOCK_PGLUE_B, init_phase);
18351
18352    if (!CHIP_IS_E1x(sc))
18353        REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
18354
18355    ecore_init_block(sc, BLOCK_ATC, init_phase);
18356    ecore_init_block(sc, BLOCK_DMAE, init_phase);
18357    ecore_init_block(sc, BLOCK_NIG, init_phase);
18358    ecore_init_block(sc, BLOCK_SRC, init_phase);
18359    ecore_init_block(sc, BLOCK_MISC, init_phase);
18360    ecore_init_block(sc, BLOCK_TCM, init_phase);
18361    ecore_init_block(sc, BLOCK_UCM, init_phase);
18362    ecore_init_block(sc, BLOCK_CCM, init_phase);
18363    ecore_init_block(sc, BLOCK_XCM, init_phase);
18364    ecore_init_block(sc, BLOCK_TSEM, init_phase);
18365    ecore_init_block(sc, BLOCK_USEM, init_phase);
18366    ecore_init_block(sc, BLOCK_CSEM, init_phase);
18367    ecore_init_block(sc, BLOCK_XSEM, init_phase);
18368
18369    if (!CHIP_IS_E1x(sc))
18370        REG_WR(sc, QM_REG_PF_EN, 1);
18371
18372    if (!CHIP_IS_E1x(sc)) {
18373        REG_WR(sc, TSEM_REG_VFPF_ERR_NUM, BXE_MAX_NUM_OF_VFS + func);
18374        REG_WR(sc, USEM_REG_VFPF_ERR_NUM, BXE_MAX_NUM_OF_VFS + func);
18375        REG_WR(sc, CSEM_REG_VFPF_ERR_NUM, BXE_MAX_NUM_OF_VFS + func);
18376        REG_WR(sc, XSEM_REG_VFPF_ERR_NUM, BXE_MAX_NUM_OF_VFS + func);
18377    }
18378    ecore_init_block(sc, BLOCK_QM, init_phase);
18379
18380    ecore_init_block(sc, BLOCK_TM, init_phase);
18381    ecore_init_block(sc, BLOCK_DORQ, init_phase);
18382
18383    bxe_iov_init_dq(sc);
18384
18385    ecore_init_block(sc, BLOCK_BRB1, init_phase);
18386    ecore_init_block(sc, BLOCK_PRS, init_phase);
18387    ecore_init_block(sc, BLOCK_TSDM, init_phase);
18388    ecore_init_block(sc, BLOCK_CSDM, init_phase);
18389    ecore_init_block(sc, BLOCK_USDM, init_phase);
18390    ecore_init_block(sc, BLOCK_XSDM, init_phase);
18391    ecore_init_block(sc, BLOCK_UPB, init_phase);
18392    ecore_init_block(sc, BLOCK_XPB, init_phase);
18393    ecore_init_block(sc, BLOCK_PBF, init_phase);
18394    if (!CHIP_IS_E1x(sc))
18395        REG_WR(sc, PBF_REG_DISABLE_PF, 0);
18396
18397    ecore_init_block(sc, BLOCK_CDU, init_phase);
18398
18399    ecore_init_block(sc, BLOCK_CFC, init_phase);
18400
18401    if (!CHIP_IS_E1x(sc))
18402        REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 1);
18403
18404    if (IS_MF(sc)) {
18405        REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port*8, 1);
18406        REG_WR(sc, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, OVLAN(sc));
18407    }
18408
18409    ecore_init_block(sc, BLOCK_MISC_AEU, init_phase);
18410
18411    /* HC init per function */
18412    if (sc->devinfo.int_block == INT_BLOCK_HC) {
18413        if (CHIP_IS_E1H(sc)) {
18414            REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
18415
18416            REG_WR(sc, HC_REG_LEADING_EDGE_0 + port*8, 0);
18417            REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port*8, 0);
18418        }
18419        ecore_init_block(sc, BLOCK_HC, init_phase);
18420
18421    } else {
18422        int num_segs, sb_idx, prod_offset;
18423
18424        REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
18425
18426        if (!CHIP_IS_E1x(sc)) {
18427            REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);
18428            REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);
18429        }
18430
18431        ecore_init_block(sc, BLOCK_IGU, init_phase);
18432
18433        if (!CHIP_IS_E1x(sc)) {
18434            int dsb_idx = 0;
18435            /**
18436             * Producer memory:
18437             * E2 mode: address 0-135 match to the mapping memory;
18438             * 136 - PF0 default prod; 137 - PF1 default prod;
18439             * 138 - PF2 default prod; 139 - PF3 default prod;
18440             * 140 - PF0 attn prod;    141 - PF1 attn prod;
18441             * 142 - PF2 attn prod;    143 - PF3 attn prod;
18442             * 144-147 reserved.
18443             *
18444             * E1.5 mode - In backward compatible mode;
18445             * for non default SB; each even line in the memory
18446             * holds the U producer and each odd line hold
18447             * the C producer. The first 128 producers are for
18448             * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
18449             * producers are for the DSB for each PF.
18450             * Each PF has five segments: (the order inside each
18451             * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
18452             * 132-135 C prods; 136-139 X prods; 140-143 T prods;
18453             * 144-147 attn prods;
18454             */
18455            /* non-default-status-blocks */
18456            num_segs = CHIP_INT_MODE_IS_BC(sc) ?
18457                IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
18458            for (sb_idx = 0; sb_idx < sc->igu_sb_cnt; sb_idx++) {
18459                prod_offset = (sc->igu_base_sb + sb_idx) *
18460                    num_segs;
18461
18462                for (i = 0; i < num_segs; i++) {
18463                    addr = IGU_REG_PROD_CONS_MEMORY +
18464                            (prod_offset + i) * 4;
18465                    REG_WR(sc, addr, 0);
18466                }
18467                /* send consumer update with value 0 */
18468                bxe_ack_sb(sc, sc->igu_base_sb + sb_idx,
18469                           USTORM_ID, 0, IGU_INT_NOP, 1);
18470                bxe_igu_clear_sb(sc, sc->igu_base_sb + sb_idx);
18471            }
18472
18473            /* default-status-blocks */
18474            num_segs = CHIP_INT_MODE_IS_BC(sc) ?
18475                IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
18476
18477            if (CHIP_IS_MODE_4_PORT(sc))
18478                dsb_idx = SC_FUNC(sc);
18479            else
18480                dsb_idx = SC_VN(sc);
18481
18482            prod_offset = (CHIP_INT_MODE_IS_BC(sc) ?
18483                       IGU_BC_BASE_DSB_PROD + dsb_idx :
18484                       IGU_NORM_BASE_DSB_PROD + dsb_idx);
18485
18486            /*
18487             * igu prods come in chunks of E1HVN_MAX (4) -
18488             * does not matters what is the current chip mode
18489             */
18490            for (i = 0; i < (num_segs * E1HVN_MAX);
18491                 i += E1HVN_MAX) {
18492                addr = IGU_REG_PROD_CONS_MEMORY +
18493                            (prod_offset + i)*4;
18494                REG_WR(sc, addr, 0);
18495            }
18496            /* send consumer update with 0 */
18497            if (CHIP_INT_MODE_IS_BC(sc)) {
18498                bxe_ack_sb(sc, sc->igu_dsb_id,
18499                           USTORM_ID, 0, IGU_INT_NOP, 1);
18500                bxe_ack_sb(sc, sc->igu_dsb_id,
18501                           CSTORM_ID, 0, IGU_INT_NOP, 1);
18502                bxe_ack_sb(sc, sc->igu_dsb_id,
18503                           XSTORM_ID, 0, IGU_INT_NOP, 1);
18504                bxe_ack_sb(sc, sc->igu_dsb_id,
18505                           TSTORM_ID, 0, IGU_INT_NOP, 1);
18506                bxe_ack_sb(sc, sc->igu_dsb_id,
18507                           ATTENTION_ID, 0, IGU_INT_NOP, 1);
18508            } else {
18509                bxe_ack_sb(sc, sc->igu_dsb_id,
18510                           USTORM_ID, 0, IGU_INT_NOP, 1);
18511                bxe_ack_sb(sc, sc->igu_dsb_id,
18512                           ATTENTION_ID, 0, IGU_INT_NOP, 1);
18513            }
18514            bxe_igu_clear_sb(sc, sc->igu_dsb_id);
18515
18516            /* !!! these should become driver const once
18517               rf-tool supports split-68 const */
18518            REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
18519            REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
18520            REG_WR(sc, IGU_REG_SB_MASK_LSB, 0);
18521            REG_WR(sc, IGU_REG_SB_MASK_MSB, 0);
18522            REG_WR(sc, IGU_REG_PBA_STATUS_LSB, 0);
18523            REG_WR(sc, IGU_REG_PBA_STATUS_MSB, 0);
18524        }
18525    }
18526
18527    /* Reset PCIE errors for debug */
18528    REG_WR(sc, 0x2114, 0xffffffff);
18529    REG_WR(sc, 0x2120, 0xffffffff);
18530
18531    if (CHIP_IS_E1x(sc)) {
18532        main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
18533        main_mem_base = HC_REG_MAIN_MEMORY +
18534                SC_PORT(sc) * (main_mem_size * 4);
18535        main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
18536        main_mem_width = 8;
18537
18538        val = REG_RD(sc, main_mem_prty_clr);
18539        if (val) {
18540            BLOGD(sc, DBG_LOAD,
18541                  "Parity errors in HC block during function init (0x%x)!\n",
18542                  val);
18543        }
18544
18545        /* Clear "false" parity errors in MSI-X table */
18546        for (i = main_mem_base;
18547             i < main_mem_base + main_mem_size * 4;
18548             i += main_mem_width) {
18549            bxe_read_dmae(sc, i, main_mem_width / 4);
18550            bxe_write_dmae(sc, BXE_SP_MAPPING(sc, wb_data),
18551                           i, main_mem_width / 4);
18552        }
18553        /* Clear HC parity attention */
18554        REG_RD(sc, main_mem_prty_clr);
18555    }
18556
18557#if 1
18558    /* Enable STORMs SP logging */
18559    REG_WR8(sc, BAR_USTRORM_INTMEM +
18560           USTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
18561    REG_WR8(sc, BAR_TSTRORM_INTMEM +
18562           TSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
18563    REG_WR8(sc, BAR_CSTRORM_INTMEM +
18564           CSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
18565    REG_WR8(sc, BAR_XSTRORM_INTMEM +
18566           XSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
18567#endif
18568
18569    elink_phy_probe(&sc->link_params);
18570
18571    return (0);
18572}
18573
18574static void
18575bxe_link_reset(struct bxe_softc *sc)
18576{
18577    if (!BXE_NOMCP(sc)) {
18578	bxe_acquire_phy_lock(sc);
18579        elink_lfa_reset(&sc->link_params, &sc->link_vars);
18580	bxe_release_phy_lock(sc);
18581    } else {
18582        if (!CHIP_REV_IS_SLOW(sc)) {
18583            BLOGW(sc, "Bootcode is missing - cannot reset link\n");
18584        }
18585    }
18586}
18587
18588static void
18589bxe_reset_port(struct bxe_softc *sc)
18590{
18591    int port = SC_PORT(sc);
18592    uint32_t val;
18593
18594    /* reset physical Link */
18595    bxe_link_reset(sc);
18596
18597    REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
18598
18599    /* Do not rcv packets to BRB */
18600    REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
18601    /* Do not direct rcv packets that are not for MCP to the BRB */
18602    REG_WR(sc, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
18603               NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
18604
18605    /* Configure AEU */
18606    REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
18607
18608    DELAY(100000);
18609
18610    /* Check for BRB port occupancy */
18611    val = REG_RD(sc, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
18612    if (val) {
18613        BLOGD(sc, DBG_LOAD,
18614              "BRB1 is not empty, %d blocks are occupied\n", val);
18615    }
18616
18617    /* TODO: Close Doorbell port? */
18618}
18619
18620static void
18621bxe_ilt_wr(struct bxe_softc *sc,
18622           uint32_t         index,
18623           bus_addr_t       addr)
18624{
18625    int reg;
18626    uint32_t wb_write[2];
18627
18628    if (CHIP_IS_E1(sc)) {
18629        reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
18630    } else {
18631        reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
18632    }
18633
18634    wb_write[0] = ONCHIP_ADDR1(addr);
18635    wb_write[1] = ONCHIP_ADDR2(addr);
18636    REG_WR_DMAE(sc, reg, wb_write, 2);
18637}
18638
18639static void
18640bxe_clear_func_ilt(struct bxe_softc *sc,
18641                   uint32_t         func)
18642{
18643    uint32_t i, base = FUNC_ILT_BASE(func);
18644    for (i = base; i < base + ILT_PER_FUNC; i++) {
18645        bxe_ilt_wr(sc, i, 0);
18646    }
18647}
18648
18649static void
18650bxe_reset_func(struct bxe_softc *sc)
18651{
18652    struct bxe_fastpath *fp;
18653    int port = SC_PORT(sc);
18654    int func = SC_FUNC(sc);
18655    int i;
18656
18657    /* Disable the function in the FW */
18658    REG_WR8(sc, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
18659    REG_WR8(sc, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
18660    REG_WR8(sc, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
18661    REG_WR8(sc, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
18662
18663    /* FP SBs */
18664    FOR_EACH_ETH_QUEUE(sc, i) {
18665        fp = &sc->fp[i];
18666        REG_WR8(sc, BAR_CSTRORM_INTMEM +
18667                CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
18668                SB_DISABLED);
18669    }
18670
18671#if 0
18672    if (CNIC_LOADED(sc)) {
18673        /* CNIC SB */
18674        REG_WR8(sc, BAR_CSTRORM_INTMEM +
18675                CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET
18676                (bxe_cnic_fw_sb_id(sc)), SB_DISABLED);
18677    }
18678#endif
18679
18680    /* SP SB */
18681    REG_WR8(sc, BAR_CSTRORM_INTMEM +
18682            CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
18683            SB_DISABLED);
18684
18685    for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++) {
18686        REG_WR(sc, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func), 0);
18687    }
18688
18689    /* Configure IGU */
18690    if (sc->devinfo.int_block == INT_BLOCK_HC) {
18691        REG_WR(sc, HC_REG_LEADING_EDGE_0 + port*8, 0);
18692        REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port*8, 0);
18693    } else {
18694        REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);
18695        REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);
18696    }
18697
18698    if (CNIC_LOADED(sc)) {
18699        /* Disable Timer scan */
18700        REG_WR(sc, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
18701        /*
18702         * Wait for at least 10ms and up to 2 second for the timers
18703         * scan to complete
18704         */
18705        for (i = 0; i < 200; i++) {
18706            DELAY(10000);
18707            if (!REG_RD(sc, TM_REG_LIN0_SCAN_ON + port*4))
18708                break;
18709        }
18710    }
18711
18712    /* Clear ILT */
18713    bxe_clear_func_ilt(sc, func);
18714
18715    /*
18716     * Timers workaround bug for E2: if this is vnic-3,
18717     * we need to set the entire ilt range for this timers.
18718     */
18719    if (!CHIP_IS_E1x(sc) && SC_VN(sc) == 3) {
18720        struct ilt_client_info ilt_cli;
18721        /* use dummy TM client */
18722        memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
18723        ilt_cli.start = 0;
18724        ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
18725        ilt_cli.client_num = ILT_CLIENT_TM;
18726
18727        ecore_ilt_boundry_init_op(sc, &ilt_cli, 0, INITOP_CLEAR);
18728    }
18729
18730    /* this assumes that reset_port() called before reset_func()*/
18731    if (!CHIP_IS_E1x(sc)) {
18732        bxe_pf_disable(sc);
18733    }
18734
18735    sc->dmae_ready = 0;
18736}
18737
18738static int
18739bxe_gunzip_init(struct bxe_softc *sc)
18740{
18741    return (0);
18742}
18743
18744static void
18745bxe_gunzip_end(struct bxe_softc *sc)
18746{
18747    return;
18748}
18749
18750static int
18751bxe_init_firmware(struct bxe_softc *sc)
18752{
18753    if (CHIP_IS_E1(sc)) {
18754        ecore_init_e1_firmware(sc);
18755        sc->iro_array = e1_iro_arr;
18756    } else if (CHIP_IS_E1H(sc)) {
18757        ecore_init_e1h_firmware(sc);
18758        sc->iro_array = e1h_iro_arr;
18759    } else if (!CHIP_IS_E1x(sc)) {
18760        ecore_init_e2_firmware(sc);
18761        sc->iro_array = e2_iro_arr;
18762    } else {
18763        BLOGE(sc, "Unsupported chip revision\n");
18764        return (-1);
18765    }
18766
18767    return (0);
18768}
18769
18770static void
18771bxe_release_firmware(struct bxe_softc *sc)
18772{
18773    /* Do nothing */
18774    return;
18775}
18776
18777static int
18778ecore_gunzip(struct bxe_softc *sc,
18779             const uint8_t    *zbuf,
18780             int              len)
18781{
18782    /* XXX : Implement... */
18783    BLOGD(sc, DBG_LOAD, "ECORE_GUNZIP NOT IMPLEMENTED\n");
18784    return (FALSE);
18785}
18786
18787static void
18788ecore_reg_wr_ind(struct bxe_softc *sc,
18789                 uint32_t         addr,
18790                 uint32_t         val)
18791{
18792    bxe_reg_wr_ind(sc, addr, val);
18793}
18794
18795static void
18796ecore_write_dmae_phys_len(struct bxe_softc *sc,
18797                          bus_addr_t       phys_addr,
18798                          uint32_t         addr,
18799                          uint32_t         len)
18800{
18801    bxe_write_dmae_phys_len(sc, phys_addr, addr, len);
18802}
18803
18804void
18805ecore_storm_memset_struct(struct bxe_softc *sc,
18806                          uint32_t         addr,
18807                          size_t           size,
18808                          uint32_t         *data)
18809{
18810    uint8_t i;
18811    for (i = 0; i < size/4; i++) {
18812        REG_WR(sc, addr + (i * 4), data[i]);
18813    }
18814}
18815
18816