1331722Seadler/* 2191762Simp * Copyright (c) 2007 The DragonFly Project. All rights reserved. 3191762Simp * 4191762Simp * This code is derived from software contributed to The DragonFly Project 5191762Simp * by Sepherosa Ziehau <sepherosa@gmail.com> 6191762Simp * 7191762Simp * Redistribution and use in source and binary forms, with or without 8191762Simp * modification, are permitted provided that the following conditions 9191762Simp * are met: 10191762Simp * 11191762Simp * 1. Redistributions of source code must retain the above copyright 12191762Simp * notice, this list of conditions and the following disclaimer. 13191762Simp * 2. Redistributions in binary form must reproduce the above copyright 14191762Simp * notice, this list of conditions and the following disclaimer in 15191762Simp * the documentation and/or other materials provided with the 16191762Simp * distribution. 17191762Simp * 3. Neither the name of The DragonFly Project nor the names of its 18191762Simp * contributors may be used to endorse or promote products derived 19191762Simp * from this software without specific, prior written permission. 20191762Simp * 21191762Simp * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22191762Simp * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23191762Simp * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 24191762Simp * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 25191762Simp * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 26191762Simp * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 27191762Simp * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 28191762Simp * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 29191762Simp * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30191762Simp * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 31191762Simp * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32191762Simp * SUCH DAMAGE. 33191762Simp * 34191762Simp * $DragonFly: src/sys/dev/netif/bwi/if_bwivar.h,v 1.14 2008/02/15 11:15:38 sephe Exp $ 35191762Simp * $FreeBSD: stable/11/sys/dev/bwi/if_bwivar.h 345636 2019-03-28 09:50:25Z avos $ 36191762Simp */ 37191762Simp 38191762Simp#ifndef _IF_BWIVAR_H 39191762Simp#define _IF_BWIVAR_H 40191762Simp 41191762Simp#define BWI_ALIGN 0x1000 42191762Simp#define BWI_RING_ALIGN BWI_ALIGN 43191762Simp#define BWI_BUS_SPACE_MAXADDR 0x3fffffff 44191762Simp 45191762Simp#define BWI_TX_NRING 6 46191762Simp#define BWI_TXRX_NRING 6 47191762Simp#define BWI_TX_NDESC 128 48191762Simp#define BWI_RX_NDESC 64 49191762Simp#define BWI_TXSTATS_NDESC 64 50191762Simp#define BWI_TX_NSPRDESC 2 51191762Simp#define BWI_TX_DATA_RING 1 52191762Simp 53191762Simp/* XXX Onoe/Sample/AMRR probably need different configuration */ 54191762Simp#define BWI_SHRETRY 7 55191762Simp#define BWI_LGRETRY 4 56191762Simp#define BWI_SHRETRY_FB 3 57191762Simp#define BWI_LGRETRY_FB 2 58191762Simp 59191762Simp#define BWI_LED_EVENT_NONE -1 60191762Simp#define BWI_LED_EVENT_POLL 0 61191762Simp#define BWI_LED_EVENT_TX 1 62191762Simp#define BWI_LED_EVENT_RX 2 63191762Simp#define BWI_LED_SLOWDOWN(dur) (dur) = (((dur) * 3) / 2) 64191762Simp 65191762Simpenum bwi_txpwrcb_type { 66191762Simp BWI_TXPWR_INIT = 0, 67191762Simp BWI_TXPWR_FORCE = 1, 68191762Simp BWI_TXPWR_CALIB = 2 69191762Simp}; 70191762Simp 71191762Simp#define BWI_NOISE_FLOOR -95 /* TODO: noise floor calc */ 72191762Simp#define BWI_FRAME_MIN_LEN(hdr) \ 73191762Simp ((hdr) + sizeof(struct ieee80211_frame_ack) + IEEE80211_CRC_LEN) 74191762Simp 75191762Simp#define CSR_READ_4(sc, reg) \ 76191762Simp bus_space_read_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg)) 77191762Simp#define CSR_READ_2(sc, reg) \ 78191762Simp bus_space_read_2((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg)) 79191762Simp 80191762Simp#define CSR_WRITE_4(sc, reg, val) \ 81191762Simp bus_space_write_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val)) 82191762Simp#define CSR_WRITE_2(sc, reg, val) \ 83191762Simp bus_space_write_2((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val)) 84191762Simp 85191762Simp#define CSR_SETBITS_4(sc, reg, bits) \ 86191762Simp CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) | (bits)) 87191762Simp#define CSR_SETBITS_2(sc, reg, bits) \ 88191762Simp CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) | (bits)) 89191762Simp 90191762Simp#define CSR_FILT_SETBITS_4(sc, reg, filt, bits) \ 91191762Simp CSR_WRITE_4((sc), (reg), (CSR_READ_4((sc), (reg)) & (filt)) | (bits)) 92191762Simp#define CSR_FILT_SETBITS_2(sc, reg, filt, bits) \ 93191762Simp CSR_WRITE_2((sc), (reg), (CSR_READ_2((sc), (reg)) & (filt)) | (bits)) 94191762Simp 95191762Simp#define CSR_CLRBITS_4(sc, reg, bits) \ 96191762Simp CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) & ~(bits)) 97191762Simp#define CSR_CLRBITS_2(sc, reg, bits) \ 98191762Simp CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) & ~(bits)) 99191762Simp 100191762Simp#ifdef BWI_DEBUG 101191762Simp 102191762Simp#define DPRINTF(sc, dbg, fmt, ...) \ 103191762Simpdo { \ 104191762Simp if ((sc)->sc_debug & (dbg)) \ 105191762Simp device_printf((sc)->sc_dev, fmt, __VA_ARGS__); \ 106191762Simp} while (0) 107191762Simp 108191762Simp#define _DPRINTF(sc, dbg, fmt, ...) \ 109191762Simpdo { \ 110191762Simp if ((sc)->sc_debug & (dbg)) \ 111191762Simp printf(fmt, __VA_ARGS__); \ 112191762Simp} while (0) 113191762Simp 114191762Simp#else /* !BWI_DEBUG */ 115191762Simp 116191762Simp#define DPRINTF(sc, dbg, fmt, ...) ((void)0) 117191762Simp#define _DPRINTF(sc, dbg, fmt, ...) ((void)0) 118191762Simp 119191762Simp#endif /* BWI_DEBUG */ 120191762Simp 121191762Simpstruct bwi_desc32 { 122191762Simp /* Little endian */ 123191762Simp uint32_t ctrl; 124191762Simp uint32_t addr; /* BWI_DESC32_A_ */ 125191762Simp} __packed; 126191762Simp 127191762Simp#define BWI_DESC32_A_FUNC_TXRX 0x1 128191762Simp#define BWI_DESC32_A_FUNC_MASK __BITS(31, 30) 129191762Simp#define BWI_DESC32_A_ADDR_MASK __BITS(29, 0) 130191762Simp 131191762Simp#define BWI_DESC32_C_BUFLEN_MASK __BITS(12, 0) 132191762Simp#define BWI_DESC32_C_ADDRHI_MASK __BITS(17, 16) 133191762Simp#define BWI_DESC32_C_EOR __BIT(28) 134191762Simp#define BWI_DESC32_C_INTR __BIT(29) 135191762Simp#define BWI_DESC32_C_FRAME_END __BIT(30) 136191762Simp#define BWI_DESC32_C_FRAME_START __BIT(31) 137191762Simp 138191762Simpstruct bwi_desc64 { 139191762Simp /* Little endian */ 140191762Simp uint32_t ctrl0; 141191762Simp uint32_t ctrl1; 142191762Simp uint32_t addr_lo; 143191762Simp uint32_t addr_hi; 144191762Simp} __packed; 145191762Simp 146191762Simpstruct bwi_rxbuf_hdr { 147191762Simp /* Little endian */ 148191762Simp uint16_t rxh_buflen; /* exclude bwi_rxbuf_hdr */ 149191762Simp uint8_t rxh_pad1[2]; 150191762Simp uint16_t rxh_flags1; /* BWI_RXH_F1_ */ 151191762Simp uint8_t rxh_rssi; 152191762Simp uint8_t rxh_sq; 153191762Simp uint16_t rxh_phyinfo; /* BWI_RXH_PHYINFO_ */ 154191762Simp uint16_t rxh_flags3; /* BWI_RXH_F3_ */ 155191762Simp uint16_t rxh_flags2; /* BWI_RXH_F2_ */ 156191762Simp uint16_t rxh_tsf; 157191762Simp uint8_t rxh_pad3[14]; /* Padded to 30bytes */ 158191762Simp} __packed; 159191762Simp 160191762Simp#define BWI_RXH_F1_BCM2053_RSSI __BIT(14) 161191762Simp#define BWI_RXH_F1_SHPREAMBLE __BIT(7) 162191762Simp#define BWI_RXH_F1_OFDM __BIT(0) 163191762Simp 164191762Simp#define BWI_RXH_F2_TYPE2FRAME __BIT(2) 165191762Simp 166191762Simp#define BWI_RXH_F3_BCM2050_RSSI __BIT(10) 167191762Simp 168191762Simp#define BWI_RXH_PHYINFO_LNAGAIN __BITS(15, 14) 169191762Simp 170191762Simpstruct bwi_txbuf_hdr { 171191762Simp /* Little endian */ 172191762Simp uint32_t txh_mac_ctrl; /* BWI_TXH_MAC_C_ */ 173191762Simp uint8_t txh_fc[2]; 174191762Simp uint16_t txh_unknown1; 175191762Simp uint16_t txh_phy_ctrl; /* BWI_TXH_PHY_C_ */ 176191762Simp uint8_t txh_ivs[16]; 177191762Simp uint8_t txh_addr1[IEEE80211_ADDR_LEN]; 178191762Simp uint16_t txh_unknown2; 179191762Simp uint8_t txh_rts_fb_plcp[4]; 180191762Simp uint16_t txh_rts_fb_duration; 181191762Simp uint8_t txh_fb_plcp[4]; 182191762Simp uint16_t txh_fb_duration; 183191762Simp uint8_t txh_pad2[2]; 184191762Simp uint16_t txh_id; /* BWI_TXH_ID_ */ 185191762Simp uint16_t txh_unknown3; 186191762Simp uint8_t txh_rts_plcp[6]; 187191762Simp uint8_t txh_rts_fc[2]; 188191762Simp uint16_t txh_rts_duration; 189191762Simp uint8_t txh_rts_ra[IEEE80211_ADDR_LEN]; 190191762Simp uint8_t txh_rts_ta[IEEE80211_ADDR_LEN]; 191191762Simp uint8_t txh_pad3[2]; 192191762Simp uint8_t txh_plcp[6]; 193191762Simp} __packed; 194191762Simp 195191762Simp#define BWI_TXH_ID_RING_MASK __BITS(15, 13) 196191762Simp#define BWI_TXH_ID_IDX_MASK __BITS(12, 0) 197191762Simp 198191762Simp#define BWI_TXH_PHY_C_OFDM __BIT(0) 199191762Simp#define BWI_TXH_PHY_C_SHPREAMBLE __BIT(4) 200191762Simp#define BWI_TXH_PHY_C_ANTMODE_MASK __BITS(9, 8) 201191762Simp 202191762Simp#define BWI_TXH_MAC_C_ACK __BIT(0) 203191762Simp#define BWI_TXH_MAC_C_FIRST_FRAG __BIT(3) 204191762Simp#define BWI_TXH_MAC_C_HWSEQ __BIT(4) 205191762Simp#define BWI_TXH_MAC_C_FB_OFDM __BIT(8) 206191762Simp 207191762Simpstruct bwi_txstats { 208191762Simp /* Little endian */ 209191762Simp uint8_t txs_pad1[4]; 210191762Simp uint16_t txs_id; 211191762Simp uint8_t txs_flags; /* BWI_TXS_F_ */ 212191762Simp uint8_t txs_txcnt; /* BWI_TXS_TXCNT_ */ 213191762Simp uint8_t txs_pad2[2]; 214191762Simp uint16_t txs_seq; 215191762Simp uint16_t txs_unknown; 216191762Simp uint8_t txs_pad3[2]; /* Padded to 16bytes */ 217191762Simp} __packed; 218191762Simp 219191762Simp#define BWI_TXS_TXCNT_DATA __BITS(7, 4) 220191762Simp 221191762Simp#define BWI_TXS_F_ACKED __BIT(0) 222191762Simp#define BWI_TXS_F_PENDING __BIT(5) 223191762Simp 224191762Simpstruct bwi_ring_data { 225191762Simp uint32_t rdata_txrx_ctrl; 226191762Simp bus_dmamap_t rdata_dmap; 227191762Simp bus_addr_t rdata_paddr; 228191762Simp void *rdata_desc; 229191762Simp}; 230191762Simp 231191762Simpstruct bwi_txbuf { 232191762Simp struct mbuf *tb_mbuf; 233191762Simp bus_dmamap_t tb_dmap; 234191762Simp 235191762Simp struct ieee80211_node *tb_ni; 236191762Simp int tb_rate[2]; 237191762Simp}; 238191762Simp 239191762Simpstruct bwi_txbuf_data { 240191762Simp struct bwi_txbuf tbd_buf[BWI_TX_NDESC]; 241191762Simp int tbd_used; 242191762Simp int tbd_idx; 243191762Simp}; 244191762Simp 245191762Simpstruct bwi_rxbuf { 246191762Simp struct mbuf *rb_mbuf; 247191762Simp bus_addr_t rb_paddr; 248191762Simp bus_dmamap_t rb_dmap; 249191762Simp}; 250191762Simp 251191762Simpstruct bwi_rxbuf_data { 252191762Simp struct bwi_rxbuf rbd_buf[BWI_RX_NDESC]; 253191762Simp bus_dmamap_t rbd_tmp_dmap; 254191762Simp int rbd_idx; 255191762Simp}; 256191762Simp 257191762Simpstruct bwi_txstats_data { 258191762Simp bus_dma_tag_t stats_ring_dtag; 259191762Simp bus_dmamap_t stats_ring_dmap; 260191762Simp bus_addr_t stats_ring_paddr; 261191762Simp void *stats_ring; 262191762Simp 263191762Simp bus_dma_tag_t stats_dtag; 264191762Simp bus_dmamap_t stats_dmap; 265191762Simp bus_addr_t stats_paddr; 266191762Simp struct bwi_txstats *stats; 267191762Simp 268191762Simp uint32_t stats_ctrl_base; 269191762Simp int stats_idx; 270191762Simp}; 271191762Simp 272191762Simpstruct bwi_fwhdr { 273191762Simp /* Big endian */ 274191762Simp uint8_t fw_type; /* BWI_FW_T_ */ 275191762Simp uint8_t fw_gen; /* BWI_FW_GEN */ 276191762Simp uint8_t fw_pad[2]; 277191762Simp uint32_t fw_size; 278191762Simp#define fw_iv_cnt fw_size 279191762Simp} __packed; 280191762Simp 281191762Simp#define BWI_FWHDR_SZ sizeof(struct bwi_fwhdr) 282191762Simp 283191762Simp#define BWI_FW_T_UCODE 'u' 284191762Simp#define BWI_FW_T_PCM 'p' 285191762Simp#define BWI_FW_T_IV 'i' 286191762Simp 287191762Simp#define BWI_FW_GEN_1 1 288191762Simp 289191762Simp#define BWI_FW_VERSION3 3 290191762Simp#define BWI_FW_VERSION4 4 291191762Simp#define BWI_FW_VERSION3_REVMAX 0x128 292191762Simp 293191762Simp#define BWI_FW_PATH "bwi_v%d_" 294191762Simp#define BWI_FW_STUB_PATH BWI_FW_PATH "ucode" 295191762Simp#define BWI_FW_UCODE_PATH BWI_FW_PATH "ucode%d" 296191762Simp#define BWI_FW_PCM_PATH BWI_FW_PATH "pcm%d" 297191762Simp#define BWI_FW_IV_PATH BWI_FW_PATH "b0g0initvals%d" 298191762Simp#define BWI_FW_IV_EXT_PATH BWI_FW_PATH "b0g0bsinitvals%d" 299191762Simp 300191762Simpstruct bwi_fw_iv { 301191762Simp /* Big endian */ 302191762Simp uint16_t iv_ofs; 303191762Simp union { 304191762Simp uint32_t val32; 305191762Simp uint16_t val16; 306191762Simp } iv_val; 307191762Simp} __packed; 308191762Simp 309191762Simp#define BWI_FW_IV_OFS_MASK __BITS(14, 0) 310191762Simp#define BWI_FW_IV_IS_32BIT __BIT(15) 311191762Simp 312191762Simpstruct bwi_led { 313191762Simp uint8_t l_flags; /* BWI_LED_F_ */ 314191762Simp uint8_t l_act; /* BWI_LED_ACT_ */ 315191762Simp uint8_t l_mask; 316191762Simp}; 317191762Simp 318191762Simp#define BWI_LED_F_ACTLOW 0x1 319191762Simp#define BWI_LED_F_BLINK 0x2 320191762Simp#define BWI_LED_F_POLLABLE 0x4 321191762Simp#define BWI_LED_F_SLOW 0x8 322191762Simp 323191762Simpenum bwi_clock_mode { 324191762Simp BWI_CLOCK_MODE_SLOW, 325191762Simp BWI_CLOCK_MODE_FAST, 326191762Simp BWI_CLOCK_MODE_DYN 327191762Simp}; 328191762Simp 329191762Simpstruct bwi_regwin { 330191762Simp uint32_t rw_flags; /* BWI_REGWIN_F_ */ 331191762Simp uint16_t rw_type; /* BWI_REGWIN_T_ */ 332191762Simp uint8_t rw_id; 333191762Simp uint8_t rw_rev; 334191762Simp}; 335191762Simp 336191762Simp#define BWI_REGWIN_F_EXIST 0x1 337191762Simp 338191762Simp#define BWI_CREATE_REGWIN(rw, id, type, rev) \ 339191762Simpdo { \ 340191762Simp (rw)->rw_flags = BWI_REGWIN_F_EXIST; \ 341191762Simp (rw)->rw_type = (type); \ 342191762Simp (rw)->rw_id = (id); \ 343191762Simp (rw)->rw_rev = (rev); \ 344191762Simp} while (0) 345191762Simp 346191762Simp#define BWI_REGWIN_EXIST(rw) ((rw)->rw_flags & BWI_REGWIN_F_EXIST) 347191762Simp#define BWI_GPIO_REGWIN(sc) \ 348191762Simp (BWI_REGWIN_EXIST(&(sc)->sc_com_regwin) ? \ 349191762Simp &(sc)->sc_com_regwin : &(sc)->sc_bus_regwin) 350191762Simp 351191762Simpstruct bwi_mac; 352191762Simp 353191762Simpstruct bwi_phy { 354191762Simp enum ieee80211_phymode phy_mode; 355191762Simp int phy_rev; 356191762Simp int phy_version; 357191762Simp 358191762Simp uint32_t phy_flags; /* BWI_PHY_F_ */ 359191762Simp uint16_t phy_tbl_ctrl; 360191762Simp uint16_t phy_tbl_data_lo; 361191762Simp uint16_t phy_tbl_data_hi; 362191762Simp 363191762Simp void (*phy_init)(struct bwi_mac *); 364191762Simp}; 365191762Simp 366191762Simp#define BWI_PHY_F_CALIBRATED 0x1 367191762Simp#define BWI_PHY_F_LINKED 0x2 368191762Simp#define BWI_CLEAR_PHY_FLAGS (BWI_PHY_F_CALIBRATED) 369191762Simp 370191762Simp/* TX power control */ 371191762Simpstruct bwi_tpctl { 372191762Simp uint16_t bbp_atten; /* BBP attenuation: 4bits */ 373191762Simp uint16_t rf_atten; /* RF attenuation */ 374191762Simp uint16_t tp_ctrl1; /* ??: 3bits */ 375191762Simp uint16_t tp_ctrl2; /* ??: 4bits */ 376191762Simp}; 377191762Simp 378191762Simp#define BWI_RF_ATTEN_FACTOR 4 379191762Simp#define BWI_RF_ATTEN_MAX0 9 380191762Simp#define BWI_RF_ATTEN_MAX1 31 381191762Simp#define BWI_BBP_ATTEN_MAX 11 382191762Simp#define BWI_TPCTL1_MAX 7 383191762Simp 384191762Simpstruct bwi_rf_lo { 385191762Simp int8_t ctrl_lo; 386191762Simp int8_t ctrl_hi; 387191762Simp}; 388191762Simp 389191762Simpstruct bwi_rf { 390191762Simp uint16_t rf_type; /* BWI_RF_T_ */ 391191762Simp uint16_t rf_manu; 392191762Simp int rf_rev; 393191762Simp 394191762Simp uint32_t rf_flags; /* BWI_RF_F_ */ 395191762Simp 396191762Simp#define BWI_RFLO_MAX 56 397191762Simp struct bwi_rf_lo rf_lo[BWI_RFLO_MAX]; 398191762Simp uint8_t rf_lo_used[8]; 399191762Simp 400191762Simp#define BWI_INVALID_NRSSI -1000 401191762Simp int16_t rf_nrssi[2]; /* Narrow RSSI */ 402191762Simp int32_t rf_nrssi_slope; 403191762Simp 404191762Simp#define BWI_NRSSI_TBLSZ 64 405191762Simp int8_t rf_nrssi_table[BWI_NRSSI_TBLSZ]; 406191762Simp 407191762Simp uint16_t rf_lo_gain; /* loopback gain */ 408191762Simp uint16_t rf_rx_gain; /* TRSW RX gain */ 409191762Simp 410191762Simp uint16_t rf_calib; /* RF calibration value */ 411191762Simp u_int rf_curchan; /* current channel */ 412191762Simp 413191762Simp uint16_t rf_ctrl_rd; 414191762Simp int rf_ctrl_adj; 415191762Simp void (*rf_off)(struct bwi_mac *); 416191762Simp void (*rf_on)(struct bwi_mac *); 417191762Simp 418191762Simp void (*rf_set_nrssi_thr)(struct bwi_mac *); 419191762Simp void (*rf_calc_nrssi_slope)(struct bwi_mac *); 420191762Simp int (*rf_calc_rssi) 421191762Simp (struct bwi_mac *, 422191762Simp const struct bwi_rxbuf_hdr *); 423191762Simp int (*rf_calc_noise)(struct bwi_mac *); 424191762Simp 425191762Simp void (*rf_lo_update)(struct bwi_mac *); 426191762Simp 427191762Simp#define BWI_TSSI_MAX 64 428191762Simp int8_t rf_txpower_map0[BWI_TSSI_MAX]; 429191762Simp /* Indexed by TSSI */ 430191762Simp int rf_idle_tssi0; 431191762Simp 432191762Simp int8_t rf_txpower_map[BWI_TSSI_MAX]; 433191762Simp int rf_idle_tssi; 434191762Simp 435191762Simp int rf_base_tssi; 436191762Simp 437191762Simp int rf_txpower_max; /* dBm */ 438191762Simp 439191762Simp int rf_ant_mode; /* BWI_ANT_MODE_ */ 440191762Simp}; 441191762Simp 442191762Simp#define BWI_RF_F_INITED 0x1 443191762Simp#define BWI_RF_F_ON 0x2 444191762Simp#define BWI_RF_CLEAR_FLAGS (BWI_RF_F_INITED) 445191762Simp 446191762Simp#define BWI_ANT_MODE_0 0 447191762Simp#define BWI_ANT_MODE_1 1 448191762Simp#define BWI_ANT_MODE_UNKN 2 449191762Simp#define BWI_ANT_MODE_AUTO 3 450191762Simp 451191762Simpstruct bwi_softc; 452191762Simpstruct firmware; 453191762Simp 454191762Simpstruct bwi_mac { 455191762Simp struct bwi_regwin mac_regwin; /* MUST be first field */ 456191762Simp#define mac_rw_flags mac_regwin.rw_flags 457191762Simp#define mac_type mac_regwin.rw_type 458191762Simp#define mac_id mac_regwin.rw_id 459191762Simp#define mac_rev mac_regwin.rw_rev 460191762Simp 461191762Simp struct bwi_softc *mac_sc; 462191762Simp 463191762Simp struct bwi_phy mac_phy; /* PHY I/F */ 464191762Simp struct bwi_rf mac_rf; /* RF I/F */ 465191762Simp 466191762Simp struct bwi_tpctl mac_tpctl; /* TX power control */ 467191762Simp uint32_t mac_flags; /* BWI_MAC_F_ */ 468191762Simp 469191762Simp const struct firmware *mac_stub; 470191762Simp const struct firmware *mac_ucode; 471191762Simp const struct firmware *mac_pcm; 472191762Simp const struct firmware *mac_iv; 473191762Simp const struct firmware *mac_iv_ext; 474191762Simp}; 475191762Simp 476191762Simp#define BWI_MAC_F_BSWAP 0x1 477191762Simp#define BWI_MAC_F_TPCTL_INITED 0x2 478191762Simp#define BWI_MAC_F_HAS_TXSTATS 0x4 479191762Simp#define BWI_MAC_F_INITED 0x8 480191762Simp#define BWI_MAC_F_ENABLED 0x10 481191762Simp#define BWI_MAC_F_LOCKED 0x20 /* for debug */ 482191762Simp#define BWI_MAC_F_TPCTL_ERROR 0x40 483191762Simp#define BWI_MAC_F_PHYE_RESET 0x80 484191762Simp 485191762Simp#define BWI_CREATE_MAC(mac, sc, id, rev) \ 486191762Simpdo { \ 487191762Simp BWI_CREATE_REGWIN(&(mac)->mac_regwin, \ 488191762Simp (id), \ 489191762Simp BWI_REGWIN_T_MAC, \ 490191762Simp (rev)); \ 491191762Simp (mac)->mac_sc = (sc); \ 492191762Simp} while (0) 493191762Simp 494191762Simp#define BWI_MAC_MAX 2 495191762Simp#define BWI_LED_MAX 4 496191762Simp 497191762Simpenum bwi_bus_space { 498191762Simp BWI_BUS_SPACE_30BIT = 1, 499191762Simp BWI_BUS_SPACE_32BIT, 500191762Simp BWI_BUS_SPACE_64BIT 501191762Simp}; 502191762Simp 503191762Simp#define BWI_TX_RADIOTAP_PRESENT \ 504191762Simp ((1 << IEEE80211_RADIOTAP_FLAGS) | \ 505191762Simp (1 << IEEE80211_RADIOTAP_RATE) | \ 506191762Simp (1 << IEEE80211_RADIOTAP_CHANNEL)) 507191762Simp 508191762Simpstruct bwi_tx_radiotap_hdr { 509191762Simp struct ieee80211_radiotap_header wt_ihdr; 510191762Simp uint8_t wt_flags; 511191762Simp uint8_t wt_rate; 512191762Simp uint16_t wt_chan_freq; 513191762Simp uint16_t wt_chan_flags; 514345636Savos} __packed; 515191762Simp 516191762Simp#define BWI_RX_RADIOTAP_PRESENT \ 517191762Simp ((1 << IEEE80211_RADIOTAP_TSFT) | \ 518191762Simp (1 << IEEE80211_RADIOTAP_FLAGS) | \ 519191762Simp (1 << IEEE80211_RADIOTAP_RATE) | \ 520191762Simp (1 << IEEE80211_RADIOTAP_CHANNEL) | \ 521191762Simp (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) | \ 522191762Simp (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE)) 523191762Simp 524191762Simpstruct bwi_rx_radiotap_hdr { 525191762Simp struct ieee80211_radiotap_header wr_ihdr; 526191762Simp uint64_t wr_tsf; 527191762Simp uint8_t wr_flags; 528191762Simp uint8_t wr_rate; 529191762Simp uint16_t wr_chan_freq; 530191762Simp uint16_t wr_chan_flags; 531191762Simp int8_t wr_antsignal; 532191762Simp int8_t wr_antnoise; 533191762Simp /* TODO: sq */ 534345636Savos} __packed __aligned(8); 535191762Simp 536191762Simpstruct bwi_vap { 537191762Simp struct ieee80211vap bv_vap; 538191762Simp int (*bv_newstate)(struct ieee80211vap *, 539191762Simp enum ieee80211_state, int); 540191762Simp}; 541191762Simp#define BWI_VAP(vap) ((struct bwi_vap *)(vap)) 542191762Simp 543191762Simpstruct bwi_softc { 544191762Simp uint32_t sc_flags; /* BWI_F_ */ 545191762Simp device_t sc_dev; 546191762Simp struct mtx sc_mtx; 547287197Sglebius struct ieee80211com sc_ic; 548287197Sglebius struct mbufq sc_snd; 549191762Simp int sc_invalid; 550191762Simp 551191762Simp uint32_t sc_cap; /* BWI_CAP_ */ 552191762Simp uint16_t sc_bbp_id; /* BWI_BBPID_ */ 553191762Simp uint8_t sc_bbp_rev; 554191762Simp uint8_t sc_bbp_pkg; 555191762Simp 556191762Simp uint8_t sc_pci_revid; 557191762Simp uint16_t sc_pci_did; 558191762Simp uint16_t sc_pci_subvid; 559191762Simp uint16_t sc_pci_subdid; 560191762Simp 561191762Simp uint16_t sc_card_flags; /* BWI_CARD_F_ */ 562191762Simp uint16_t sc_pwron_delay; 563191762Simp int sc_locale; 564191762Simp 565191762Simp int sc_irq_rid; 566191762Simp struct resource *sc_irq_res; 567191762Simp void *sc_irq_handle; 568191762Simp 569191762Simp int sc_mem_rid; 570191762Simp struct resource *sc_mem_res; 571191762Simp bus_space_tag_t sc_mem_bt; 572191762Simp bus_space_handle_t sc_mem_bh; 573191762Simp 574191762Simp struct callout sc_calib_ch; 575199198Sjhb struct callout sc_watchdog_timer; 576191762Simp 577191762Simp struct bwi_regwin *sc_cur_regwin; 578191762Simp struct bwi_regwin sc_com_regwin; 579191762Simp struct bwi_regwin sc_bus_regwin; 580191762Simp 581191762Simp int sc_nmac; 582191762Simp struct bwi_mac sc_mac[BWI_MAC_MAX]; 583191762Simp 584191762Simp int sc_rx_rate; 585191762Simp int sc_tx_rate; 586191762Simp enum bwi_txpwrcb_type sc_txpwrcb_type; 587191762Simp 588191762Simp int sc_led_blinking; 589191762Simp int sc_led_ticks; 590191762Simp struct bwi_led *sc_blink_led; 591191762Simp struct callout sc_led_blink_ch; 592191762Simp int sc_led_blink_offdur; 593191762Simp struct bwi_led sc_leds[BWI_LED_MAX]; 594191762Simp 595191762Simp enum bwi_bus_space sc_bus_space; 596191762Simp bus_dma_tag_t sc_parent_dtag; 597191762Simp 598191762Simp bus_dma_tag_t sc_buf_dtag; 599191762Simp struct bwi_txbuf_data sc_tx_bdata[BWI_TX_NRING]; 600191762Simp struct bwi_rxbuf_data sc_rx_bdata; 601191762Simp 602191762Simp bus_dma_tag_t sc_txring_dtag; 603191762Simp struct bwi_ring_data sc_tx_rdata[BWI_TX_NRING]; 604191762Simp bus_dma_tag_t sc_rxring_dtag; 605191762Simp struct bwi_ring_data sc_rx_rdata; 606191762Simp 607191762Simp struct bwi_txstats_data *sc_txstats; 608191762Simp 609191762Simp int sc_tx_timer; 610191762Simp const struct ieee80211_rate_table *sc_rates; 611191762Simp 612191762Simp struct bwi_tx_radiotap_hdr sc_tx_th; 613191762Simp struct bwi_rx_radiotap_hdr sc_rx_th; 614191762Simp 615191762Simp struct taskqueue *sc_tq; 616191762Simp struct task sc_restart_task; 617191762Simp 618191762Simp int (*sc_init_tx_ring)(struct bwi_softc *, int); 619191762Simp void (*sc_free_tx_ring)(struct bwi_softc *, int); 620191762Simp 621191762Simp int (*sc_init_rx_ring)(struct bwi_softc *); 622191762Simp void (*sc_free_rx_ring)(struct bwi_softc *); 623191762Simp 624191762Simp int (*sc_init_txstats)(struct bwi_softc *); 625191762Simp void (*sc_free_txstats)(struct bwi_softc *); 626191762Simp 627191762Simp void (*sc_setup_rxdesc) 628191762Simp (struct bwi_softc *, int, bus_addr_t, int); 629191762Simp int (*sc_rxeof)(struct bwi_softc *); 630191762Simp 631191762Simp void (*sc_setup_txdesc) 632191762Simp (struct bwi_softc *, struct bwi_ring_data *, 633191762Simp int, bus_addr_t, int); 634191762Simp void (*sc_start_tx) 635191762Simp (struct bwi_softc *, uint32_t, int); 636191762Simp 637191762Simp void (*sc_txeof_status)(struct bwi_softc *); 638191762Simp 639191762Simp /* Sysctl variables */ 640191762Simp int sc_fw_version; /* BWI_FW_VERSION[34] */ 641191762Simp int sc_dwell_time; /* milliseconds */ 642191762Simp int sc_led_idle; 643191762Simp int sc_led_blink; 644191762Simp int sc_txpwr_calib; 645191762Simp uint32_t sc_debug; /* BWI_DBG_ */ 646191762Simp}; 647191762Simp 648191762Simp#define BWI_F_BUS_INITED 0x1 649191762Simp#define BWI_F_PROMISC 0x2 650191762Simp#define BWI_F_STOP 0x4 651287197Sglebius#define BWI_F_RUNNING 0x8 652191762Simp 653191762Simp#define BWI_DBG_MAC 0x00000001 654191762Simp#define BWI_DBG_RF 0x00000002 655191762Simp#define BWI_DBG_PHY 0x00000004 656191762Simp#define BWI_DBG_MISC 0x00000008 657191762Simp 658191762Simp#define BWI_DBG_ATTACH 0x00000010 659191762Simp#define BWI_DBG_INIT 0x00000020 660191762Simp#define BWI_DBG_FIRMWARE 0x00000040 661191762Simp#define BWI_DBG_80211 0x00000080 662191762Simp#define BWI_DBG_TXPOWER 0x00000100 663191762Simp#define BWI_DBG_INTR 0x00000200 664191762Simp#define BWI_DBG_RX 0x00000400 665191762Simp#define BWI_DBG_TX 0x00000800 666191762Simp#define BWI_DBG_TXEOF 0x00001000 667191762Simp#define BWI_DBG_LED 0x00002000 668191762Simp 669191762Simp#define BWI_LOCK_INIT(sc) \ 670191762Simp mtx_init(&(sc)->sc_mtx, device_get_nameunit((sc)->sc_dev), \ 671191762Simp MTX_NETWORK_LOCK, MTX_DEF | MTX_RECURSE) 672191762Simp#define BWI_LOCK_DESTROY(sc) mtx_destroy(&(sc)->sc_mtx) 673191762Simp#define BWI_LOCK(sc) mtx_lock(&(sc)->sc_mtx) 674191762Simp#define BWI_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx) 675191762Simp#define BWI_ASSERT_LOCKED(sc) mtx_assert(&(sc)->sc_mtx, MA_OWNED) 676191762Simp 677191762Simpint bwi_attach(struct bwi_softc *); 678191762Simpint bwi_detach(struct bwi_softc *); 679191762Simpvoid bwi_suspend(struct bwi_softc *); 680191762Simpvoid bwi_resume(struct bwi_softc *); 681191762Simpint bwi_shutdown(struct bwi_softc *); 682191762Simpvoid bwi_intr(void *); 683191762Simp 684191762Simpint bwi_bus_init(struct bwi_softc *, struct bwi_mac *mac); 685191762Simp 686191762Simpuint16_t bwi_read_sprom(struct bwi_softc *, uint16_t); 687191762Simpint bwi_regwin_switch(struct bwi_softc *, struct bwi_regwin *, 688191762Simp struct bwi_regwin **); 689191762Simpint bwi_regwin_is_enabled(struct bwi_softc *, struct bwi_regwin *); 690191762Simpvoid bwi_regwin_enable(struct bwi_softc *, struct bwi_regwin *, 691191762Simp uint32_t); 692191762Simpvoid bwi_regwin_disable(struct bwi_softc *, struct bwi_regwin *, 693191762Simp uint32_t); 694191762Simp 695191762Simp#define abs(a) __builtin_abs(a) 696191762Simp 697191762Simp/* XXX does not belong here */ 698191762Simpstruct ieee80211_ds_plcp_hdr { 699191762Simp uint8_t i_signal; 700191762Simp uint8_t i_service; 701191762Simp uint16_t i_length; 702191762Simp uint16_t i_crc; 703191762Simp} __packed; 704191762Simp 705191762Simp#endif /* !_IF_BWIVAR_H */ 706