if_bm.c revision 182670
1179645Smarcel/*- 2179645Smarcel * Copyright 2008 Nathan Whitehorn. All rights reserved. 3179645Smarcel * Copyright 2003 by Peter Grehan. All rights reserved. 4179645Smarcel * Copyright (C) 1998, 1999, 2000 Tsubai Masanari. All rights reserved. 5179645Smarcel * 6179645Smarcel * Redistribution and use in source and binary forms, with or without 7179645Smarcel * modification, are permitted provided that the following conditions 8179645Smarcel * are met: 9179645Smarcel * 1. Redistributions of source code must retain the above copyright 10179645Smarcel * notice, this list of conditions and the following disclaimer. 11179645Smarcel * 2. Redistributions in binary form must reproduce the above copyright 12179645Smarcel * notice, this list of conditions and the following disclaimer in the 13179645Smarcel * documentation and/or other materials provided with the distribution. 14179645Smarcel * 3. The name of the author may not be used to endorse or promote products 15179645Smarcel * derived from this software without specific prior written permission. 16179645Smarcel * 17179645Smarcel * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18179645Smarcel * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19179645Smarcel * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20179645Smarcel * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21179645Smarcel * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 22179645Smarcel * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 23179645Smarcel * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 24179645Smarcel * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25179645Smarcel * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26179645Smarcel * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27179645Smarcel * SUCH DAMAGE. 28179645Smarcel * 29179645Smarcel * From: 30179645Smarcel * NetBSD: if_bm.c,v 1.9.2.1 2000/11/01 15:02:49 tv Exp 31179645Smarcel */ 32179645Smarcel 33179645Smarcel/* 34179645Smarcel * BMAC/BMAC+ Macio cell 10/100 ethernet driver 35179645Smarcel * The low-cost, low-feature Apple variant of the Sun HME 36179645Smarcel */ 37179645Smarcel 38179645Smarcel#include <sys/cdefs.h> 39179645Smarcel__FBSDID("$FreeBSD: head/sys/dev/bm/if_bm.c 182670 2008-09-02 02:50:52Z nwhitehorn $"); 40179645Smarcel 41179645Smarcel#include <sys/param.h> 42179645Smarcel#include <sys/systm.h> 43179645Smarcel#include <sys/sockio.h> 44179645Smarcel#include <sys/endian.h> 45179645Smarcel#include <sys/mbuf.h> 46179645Smarcel#include <sys/module.h> 47179645Smarcel#include <sys/malloc.h> 48179645Smarcel#include <sys/kernel.h> 49179645Smarcel#include <sys/socket.h> 50179645Smarcel 51179645Smarcel#include <net/bpf.h> 52179645Smarcel#include <net/if.h> 53179645Smarcel#include <net/if_arp.h> 54179645Smarcel#include <net/ethernet.h> 55179645Smarcel#include <net/if_dl.h> 56179645Smarcel#include <net/if_media.h> 57179645Smarcel#include <net/if_types.h> 58179645Smarcel 59179645Smarcel#include <machine/pio.h> 60179645Smarcel#include <machine/bus.h> 61179645Smarcel#include <machine/resource.h> 62179645Smarcel#include <sys/bus.h> 63179645Smarcel#include <sys/rman.h> 64179645Smarcel 65179645Smarcel#include <dev/mii/mii.h> 66179645Smarcel#include <dev/mii/miivar.h> 67179645Smarcel 68179645Smarcel#include <dev/ofw/ofw_bus.h> 69179645Smarcel#include <dev/ofw/openfirm.h> 70179645Smarcel#include <machine/dbdma.h> 71179645Smarcel 72179645SmarcelMODULE_DEPEND(bm, ether, 1, 1, 1); 73179645SmarcelMODULE_DEPEND(bm, miibus, 1, 1, 1); 74179645Smarcel 75179645Smarcel/* "controller miibus0" required. See GENERIC if you get errors here. */ 76179645Smarcel#include "miibus_if.h" 77179645Smarcel 78179645Smarcel#include "if_bmreg.h" 79179645Smarcel#include "if_bmvar.h" 80179645Smarcel 81179645Smarcelstatic int bm_probe (device_t); 82179645Smarcelstatic int bm_attach (device_t); 83179645Smarcelstatic int bm_detach (device_t); 84179645Smarcelstatic void bm_shutdown (device_t); 85179645Smarcel 86179645Smarcelstatic void bm_start (struct ifnet *); 87179645Smarcelstatic void bm_start_locked (struct ifnet *); 88179645Smarcelstatic int bm_encap (struct bm_softc *sc, struct mbuf **m_head); 89179645Smarcelstatic int bm_ioctl (struct ifnet *, u_long, caddr_t); 90179645Smarcelstatic void bm_init (void *); 91179645Smarcelstatic void bm_init_locked (struct bm_softc *sc); 92179645Smarcelstatic void bm_chip_setup (struct bm_softc *sc); 93179645Smarcelstatic void bm_stop (struct bm_softc *sc); 94179645Smarcelstatic void bm_setladrf (struct bm_softc *sc); 95179645Smarcelstatic void bm_dummypacket (struct bm_softc *sc); 96179645Smarcelstatic void bm_txintr (void *xsc); 97179645Smarcelstatic void bm_rxintr (void *xsc); 98179645Smarcel 99179645Smarcelstatic int bm_add_rxbuf (struct bm_softc *sc, int i); 100179645Smarcelstatic int bm_add_rxbuf_dma (struct bm_softc *sc, int i); 101179645Smarcelstatic void bm_enable_interrupts (struct bm_softc *sc); 102179645Smarcelstatic void bm_disable_interrupts (struct bm_softc *sc); 103179645Smarcelstatic void bm_tick (void *xsc); 104179645Smarcel 105179645Smarcelstatic int bm_ifmedia_upd (struct ifnet *); 106179645Smarcelstatic void bm_ifmedia_sts (struct ifnet *, struct ifmediareq *); 107179645Smarcel 108179645Smarcelstatic void bm_miicsr_dwrite (struct bm_softc *, u_int16_t); 109179645Smarcelstatic void bm_mii_writebit (struct bm_softc *, int); 110179645Smarcelstatic int bm_mii_readbit (struct bm_softc *); 111179645Smarcelstatic void bm_mii_sync (struct bm_softc *); 112179645Smarcelstatic void bm_mii_send (struct bm_softc *, u_int32_t, int); 113179645Smarcelstatic int bm_mii_readreg (struct bm_softc *, struct bm_mii_frame *); 114179645Smarcelstatic int bm_mii_writereg (struct bm_softc *, struct bm_mii_frame *); 115179645Smarcelstatic int bm_miibus_readreg (device_t, int, int); 116179645Smarcelstatic int bm_miibus_writereg (device_t, int, int, int); 117179645Smarcelstatic void bm_miibus_statchg (device_t); 118179645Smarcel 119179645Smarcelstatic device_method_t bm_methods[] = { 120179645Smarcel /* Device interface */ 121179645Smarcel DEVMETHOD(device_probe, bm_probe), 122179645Smarcel DEVMETHOD(device_attach, bm_attach), 123179645Smarcel DEVMETHOD(device_detach, bm_detach), 124179645Smarcel DEVMETHOD(device_shutdown, bm_shutdown), 125179645Smarcel 126179645Smarcel /* bus interface, for miibus */ 127179645Smarcel DEVMETHOD(bus_print_child, bus_generic_print_child), 128179645Smarcel DEVMETHOD(bus_driver_added, bus_generic_driver_added), 129179645Smarcel 130179645Smarcel /* MII interface */ 131179645Smarcel DEVMETHOD(miibus_readreg, bm_miibus_readreg), 132179645Smarcel DEVMETHOD(miibus_writereg, bm_miibus_writereg), 133179645Smarcel DEVMETHOD(miibus_statchg, bm_miibus_statchg), 134179645Smarcel { 0, 0 } 135179645Smarcel}; 136179645Smarcel 137179645Smarcelstatic driver_t bm_macio_driver = { 138179645Smarcel "bm", 139179645Smarcel bm_methods, 140179645Smarcel sizeof(struct bm_softc) 141179645Smarcel}; 142179645Smarcel 143179645Smarcelstatic devclass_t bm_devclass; 144179645Smarcel 145179645SmarcelDRIVER_MODULE(bm, macio, bm_macio_driver, bm_devclass, 0, 0); 146179645SmarcelDRIVER_MODULE(miibus, bm, miibus_driver, miibus_devclass, 0, 0); 147179645Smarcel 148179645Smarcel/* 149179645Smarcel * MII internal routines 150179645Smarcel */ 151179645Smarcel 152179645Smarcel/* 153179645Smarcel * Write to the MII csr, introducing a delay to allow valid 154179645Smarcel * MII clock pulses to be formed 155179645Smarcel */ 156179645Smarcelstatic void 157179645Smarcelbm_miicsr_dwrite(struct bm_softc *sc, u_int16_t val) 158179645Smarcel{ 159179645Smarcel CSR_WRITE_2(sc, BM_MII_CSR, val); 160179645Smarcel /* 161179645Smarcel * Assume this is a clock toggle and generate a 1us delay 162179645Smarcel * to cover both MII's 160ns high/low minimum and 400ns 163179645Smarcel * cycle miniumum 164179645Smarcel */ 165179645Smarcel DELAY(1); 166179645Smarcel} 167179645Smarcel 168179645Smarcel/* 169179645Smarcel * Write a bit to the MII bus. 170179645Smarcel */ 171179645Smarcelstatic void 172179645Smarcelbm_mii_writebit(struct bm_softc *sc, int bit) 173179645Smarcel{ 174179645Smarcel u_int16_t regval; 175179645Smarcel 176179645Smarcel regval = BM_MII_OENABLE; 177179645Smarcel if (bit) 178179645Smarcel regval |= BM_MII_DATAOUT; 179179645Smarcel 180179645Smarcel bm_miicsr_dwrite(sc, regval); 181179645Smarcel bm_miicsr_dwrite(sc, regval | BM_MII_CLK); 182179645Smarcel bm_miicsr_dwrite(sc, regval); 183179645Smarcel} 184179645Smarcel 185179645Smarcel/* 186179645Smarcel * Read a bit from the MII bus. 187179645Smarcel */ 188179645Smarcelstatic int 189179645Smarcelbm_mii_readbit(struct bm_softc *sc) 190179645Smarcel{ 191179645Smarcel u_int16_t regval, bitin; 192179645Smarcel 193179645Smarcel /* ~BM_MII_OENABLE */ 194179645Smarcel regval = 0; 195179645Smarcel 196179645Smarcel bm_miicsr_dwrite(sc, regval); 197179645Smarcel bm_miicsr_dwrite(sc, regval | BM_MII_CLK); 198179645Smarcel bm_miicsr_dwrite(sc, regval); 199179645Smarcel bitin = CSR_READ_2(sc, BM_MII_CSR) & BM_MII_DATAIN; 200179645Smarcel 201179645Smarcel return (bitin == BM_MII_DATAIN); 202179645Smarcel} 203179645Smarcel 204179645Smarcel/* 205179645Smarcel * Sync the PHYs by setting data bit and strobing the clock 32 times. 206179645Smarcel */ 207179645Smarcelstatic void 208179645Smarcelbm_mii_sync(struct bm_softc *sc) 209179645Smarcel{ 210179645Smarcel int i; 211179645Smarcel u_int16_t regval; 212179645Smarcel 213179645Smarcel regval = BM_MII_OENABLE | BM_MII_DATAOUT; 214179645Smarcel 215179645Smarcel bm_miicsr_dwrite(sc, regval); 216179645Smarcel for (i = 0; i < 32; i++) { 217179645Smarcel bm_miicsr_dwrite(sc, regval | BM_MII_CLK); 218179645Smarcel bm_miicsr_dwrite(sc, regval); 219179645Smarcel } 220179645Smarcel} 221179645Smarcel 222179645Smarcel/* 223179645Smarcel * Clock a series of bits through the MII. 224179645Smarcel */ 225179645Smarcelstatic void 226179645Smarcelbm_mii_send(struct bm_softc *sc, u_int32_t bits, int cnt) 227179645Smarcel{ 228179645Smarcel int i; 229179645Smarcel 230179645Smarcel for (i = (0x1 << (cnt - 1)); i; i >>= 1) 231179645Smarcel bm_mii_writebit(sc, bits & i); 232179645Smarcel} 233179645Smarcel 234179645Smarcel/* 235179645Smarcel * Read a PHY register through the MII. 236179645Smarcel */ 237179645Smarcelstatic int 238179645Smarcelbm_mii_readreg(struct bm_softc *sc, struct bm_mii_frame *frame) 239179645Smarcel{ 240179645Smarcel int i, ack, bit; 241179645Smarcel 242179645Smarcel /* 243179645Smarcel * Set up frame for RX. 244179645Smarcel */ 245179645Smarcel frame->mii_stdelim = BM_MII_STARTDELIM; 246179645Smarcel frame->mii_opcode = BM_MII_READOP; 247179645Smarcel frame->mii_turnaround = 0; 248179645Smarcel frame->mii_data = 0; 249179645Smarcel 250179645Smarcel /* 251179645Smarcel * Sync the PHYs 252179645Smarcel */ 253179645Smarcel bm_mii_sync(sc); 254179645Smarcel 255179645Smarcel /* 256179645Smarcel * Send command/address info 257179645Smarcel */ 258179645Smarcel bm_mii_send(sc, frame->mii_stdelim, 2); 259179645Smarcel bm_mii_send(sc, frame->mii_opcode, 2); 260179645Smarcel bm_mii_send(sc, frame->mii_phyaddr, 5); 261179645Smarcel bm_mii_send(sc, frame->mii_regaddr, 5); 262179645Smarcel 263179645Smarcel /* 264179645Smarcel * Check for ack. 265179645Smarcel */ 266179645Smarcel ack = bm_mii_readbit(sc); 267179645Smarcel 268179645Smarcel /* 269179645Smarcel * Now try reading data bits. If the ack failed, we still 270179645Smarcel * need to clock through 16 cycles to keep the PHY(s) in sync. 271179645Smarcel */ 272179645Smarcel for (i = 0x8000; i; i >>= 1) { 273179645Smarcel bit = bm_mii_readbit(sc); 274179645Smarcel if (!ack && bit) 275179645Smarcel frame->mii_data |= i; 276179645Smarcel } 277179645Smarcel 278179645Smarcel /* 279179645Smarcel * Skip through idle bit-times 280179645Smarcel */ 281179645Smarcel bm_mii_writebit(sc, 0); 282179645Smarcel bm_mii_writebit(sc, 0); 283179645Smarcel 284179645Smarcel return ((ack) ? 1 : 0); 285179645Smarcel} 286179645Smarcel 287179645Smarcel/* 288179645Smarcel * Write to a PHY register through the MII. 289179645Smarcel */ 290179645Smarcelstatic int 291179645Smarcelbm_mii_writereg(struct bm_softc *sc, struct bm_mii_frame *frame) 292179645Smarcel{ 293179645Smarcel /* 294179645Smarcel * Set up frame for tx 295179645Smarcel */ 296179645Smarcel frame->mii_stdelim = BM_MII_STARTDELIM; 297179645Smarcel frame->mii_opcode = BM_MII_WRITEOP; 298179645Smarcel frame->mii_turnaround = BM_MII_TURNAROUND; 299179645Smarcel 300179645Smarcel /* 301179645Smarcel * Sync the phy and start the bitbang write sequence 302179645Smarcel */ 303179645Smarcel bm_mii_sync(sc); 304179645Smarcel 305179645Smarcel bm_mii_send(sc, frame->mii_stdelim, 2); 306179645Smarcel bm_mii_send(sc, frame->mii_opcode, 2); 307179645Smarcel bm_mii_send(sc, frame->mii_phyaddr, 5); 308179645Smarcel bm_mii_send(sc, frame->mii_regaddr, 5); 309179645Smarcel bm_mii_send(sc, frame->mii_turnaround, 2); 310179645Smarcel bm_mii_send(sc, frame->mii_data, 16); 311179645Smarcel 312179645Smarcel /* 313179645Smarcel * Idle bit. 314179645Smarcel */ 315179645Smarcel bm_mii_writebit(sc, 0); 316179645Smarcel 317179645Smarcel return (0); 318179645Smarcel} 319179645Smarcel 320179645Smarcel/* 321179645Smarcel * MII bus i/f 322179645Smarcel */ 323179645Smarcelstatic int 324179645Smarcelbm_miibus_readreg(device_t dev, int phy, int reg) 325179645Smarcel{ 326179645Smarcel struct bm_softc *sc; 327179645Smarcel struct bm_mii_frame frame; 328179645Smarcel 329179645Smarcel sc = device_get_softc(dev); 330179645Smarcel bzero(&frame, sizeof(frame)); 331179645Smarcel 332179645Smarcel frame.mii_phyaddr = phy; 333179645Smarcel frame.mii_regaddr = reg; 334179645Smarcel 335179645Smarcel bm_mii_readreg(sc, &frame); 336179645Smarcel 337179645Smarcel return (frame.mii_data); 338179645Smarcel} 339179645Smarcel 340179645Smarcelstatic int 341179645Smarcelbm_miibus_writereg(device_t dev, int phy, int reg, int data) 342179645Smarcel{ 343179645Smarcel struct bm_softc *sc; 344179645Smarcel struct bm_mii_frame frame; 345179645Smarcel 346179645Smarcel sc = device_get_softc(dev); 347179645Smarcel bzero(&frame, sizeof(frame)); 348179645Smarcel 349179645Smarcel frame.mii_phyaddr = phy; 350179645Smarcel frame.mii_regaddr = reg; 351179645Smarcel frame.mii_data = data; 352179645Smarcel 353179645Smarcel bm_mii_writereg(sc, &frame); 354179645Smarcel 355179645Smarcel return (0); 356179645Smarcel} 357179645Smarcel 358179645Smarcelstatic void 359179645Smarcelbm_miibus_statchg(device_t dev) 360179645Smarcel{ 361179645Smarcel struct bm_softc *sc = device_get_softc(dev); 362179645Smarcel uint16_t reg; 363179645Smarcel int new_duplex; 364179645Smarcel 365179645Smarcel reg = CSR_READ_2(sc, BM_TX_CONFIG); 366179645Smarcel new_duplex = IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX; 367179645Smarcel 368179645Smarcel if (new_duplex != sc->sc_duplex) { 369179645Smarcel /* Turn off TX MAC while we fiddle its settings */ 370179645Smarcel reg &= ~BM_ENABLE; 371179645Smarcel 372179645Smarcel CSR_WRITE_2(sc, BM_TX_CONFIG, reg); 373179645Smarcel while (CSR_READ_2(sc, BM_TX_CONFIG) & BM_ENABLE) 374179645Smarcel DELAY(10); 375179645Smarcel } 376179645Smarcel 377179645Smarcel if (new_duplex && !sc->sc_duplex) 378179645Smarcel reg |= BM_TX_IGNORECOLL | BM_TX_FULLDPX; 379179645Smarcel else if (!new_duplex && sc->sc_duplex) 380179645Smarcel reg &= ~(BM_TX_IGNORECOLL | BM_TX_FULLDPX); 381179645Smarcel 382179645Smarcel if (new_duplex != sc->sc_duplex) { 383179645Smarcel /* Turn TX MAC back on */ 384179645Smarcel reg |= BM_ENABLE; 385179645Smarcel 386179645Smarcel CSR_WRITE_2(sc, BM_TX_CONFIG, reg); 387179645Smarcel sc->sc_duplex = new_duplex; 388179645Smarcel } 389179645Smarcel} 390179645Smarcel 391179645Smarcel/* 392179645Smarcel * ifmedia/mii callbacks 393179645Smarcel */ 394179645Smarcelstatic int 395179645Smarcelbm_ifmedia_upd(struct ifnet *ifp) 396179645Smarcel{ 397179645Smarcel struct bm_softc *sc = ifp->if_softc; 398179645Smarcel int error; 399179645Smarcel 400179645Smarcel BM_LOCK(sc); 401179645Smarcel error = mii_mediachg(sc->sc_mii); 402179645Smarcel BM_UNLOCK(sc); 403179645Smarcel return (error); 404179645Smarcel} 405179645Smarcel 406179645Smarcelstatic void 407179645Smarcelbm_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifm) 408179645Smarcel{ 409179645Smarcel struct bm_softc *sc = ifp->if_softc; 410179645Smarcel 411179645Smarcel BM_LOCK(sc); 412179645Smarcel mii_pollstat(sc->sc_mii); 413179645Smarcel ifm->ifm_active = sc->sc_mii->mii_media_active; 414179645Smarcel ifm->ifm_status = sc->sc_mii->mii_media_status; 415179645Smarcel BM_UNLOCK(sc); 416179645Smarcel} 417179645Smarcel 418179645Smarcel/* 419179645Smarcel * Macio probe/attach 420179645Smarcel */ 421179645Smarcelstatic int 422179645Smarcelbm_probe(device_t dev) 423179645Smarcel{ 424179645Smarcel const char *dname = ofw_bus_get_name(dev); 425179645Smarcel const char *dcompat = ofw_bus_get_compat(dev); 426179645Smarcel 427179645Smarcel /* 428179645Smarcel * BMAC+ cells have a name of "ethernet" and 429179645Smarcel * a compatible property of "bmac+" 430179645Smarcel */ 431179645Smarcel if (strcmp(dname, "bmac") == 0) { 432179645Smarcel device_set_desc(dev, "Apple BMAC Ethernet Adaptor"); 433179645Smarcel } else if (strcmp(dcompat, "bmac+") == 0) { 434179645Smarcel device_set_desc(dev, "Apple BMAC+ Ethernet Adaptor"); 435179645Smarcel } else 436179645Smarcel return (ENXIO); 437179645Smarcel 438179645Smarcel return (0); 439179645Smarcel} 440179645Smarcel 441179645Smarcelstatic int 442179645Smarcelbm_attach(device_t dev) 443179645Smarcel{ 444179645Smarcel phandle_t node; 445179645Smarcel u_char *eaddr; 446179645Smarcel struct ifnet *ifp; 447179645Smarcel int error, cellid, i; 448179645Smarcel struct bm_txsoft *txs; 449179645Smarcel struct bm_softc *sc = device_get_softc(dev); 450179645Smarcel 451179645Smarcel ifp = sc->sc_ifp = if_alloc(IFT_ETHER); 452179645Smarcel ifp->if_softc = sc; 453179645Smarcel sc->sc_dev = dev; 454179645Smarcel sc->sc_duplex = ~IFM_FDX; 455179645Smarcel 456179645Smarcel error = 0; 457179645Smarcel mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 458180233Snwhitehorn MTX_DEF); 459179645Smarcel callout_init_mtx(&sc->sc_tick_ch, &sc->sc_mtx, 0); 460179645Smarcel 461179645Smarcel /* Check for an improved version of Paddington */ 462179645Smarcel sc->sc_streaming = 0; 463179645Smarcel cellid = -1; 464179645Smarcel node = ofw_bus_get_node(dev); 465179645Smarcel 466179645Smarcel OF_getprop(node, "cell-id", &cellid, sizeof(cellid)); 467179645Smarcel if (cellid >= 0xc4) 468179645Smarcel sc->sc_streaming = 1; 469179645Smarcel 470179645Smarcel sc->sc_memrid = 0; 471179645Smarcel sc->sc_memr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 472179645Smarcel &sc->sc_memrid, RF_ACTIVE); 473179645Smarcel if (sc->sc_memr == NULL) { 474179645Smarcel device_printf(dev, "Could not alloc chip registers!\n"); 475179645Smarcel return (ENXIO); 476179645Smarcel } 477179645Smarcel 478179645Smarcel sc->sc_txdmarid = BM_TXDMA_REGISTERS; 479179645Smarcel sc->sc_rxdmarid = BM_RXDMA_REGISTERS; 480179645Smarcel 481179645Smarcel sc->sc_txdmar = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 482179645Smarcel &sc->sc_txdmarid, RF_ACTIVE); 483179645Smarcel sc->sc_rxdmar = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 484179645Smarcel &sc->sc_rxdmarid, RF_ACTIVE); 485179645Smarcel 486179645Smarcel if (sc->sc_txdmar == NULL || sc->sc_rxdmar == NULL) { 487179645Smarcel device_printf(dev, "Could not map DBDMA registers!\n"); 488179645Smarcel return (ENXIO); 489179645Smarcel } 490179645Smarcel 491179645Smarcel error = dbdma_allocate_channel(sc->sc_txdmar, bus_get_dma_tag(dev), 492179645Smarcel BM_MAX_DMA_COMMANDS, &sc->sc_txdma); 493179645Smarcel error += dbdma_allocate_channel(sc->sc_rxdmar, bus_get_dma_tag(dev), 494179645Smarcel BM_MAX_DMA_COMMANDS, &sc->sc_rxdma); 495179645Smarcel 496179645Smarcel if (error) { 497179645Smarcel device_printf(dev,"Could not allocate DBDMA channel!\n"); 498179645Smarcel return (ENXIO); 499179645Smarcel } 500179645Smarcel 501179645Smarcel /* alloc DMA tags and buffers */ 502179645Smarcel error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 503179645Smarcel BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 504179645Smarcel BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, 505179645Smarcel NULL, &sc->sc_pdma_tag); 506179645Smarcel 507179645Smarcel if (error) { 508179645Smarcel device_printf(dev,"Could not allocate DMA tag!\n"); 509179645Smarcel return (ENXIO); 510179645Smarcel } 511179645Smarcel 512179645Smarcel error = bus_dma_tag_create(sc->sc_pdma_tag, 1, 0, BUS_SPACE_MAXADDR, 513179645Smarcel BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, MCLBYTES, 514179645Smarcel BUS_DMA_ALLOCNOW, NULL, NULL, &sc->sc_rdma_tag); 515179645Smarcel 516179645Smarcel if (error) { 517179645Smarcel device_printf(dev,"Could not allocate RX DMA channel!\n"); 518179645Smarcel return (ENXIO); 519179645Smarcel } 520179645Smarcel 521179645Smarcel error = bus_dma_tag_create(sc->sc_pdma_tag, 1, 0, BUS_SPACE_MAXADDR, 522179645Smarcel BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES * BM_NTXSEGS, BM_NTXSEGS, 523179645Smarcel MCLBYTES, BUS_DMA_ALLOCNOW, NULL, NULL, &sc->sc_tdma_tag); 524179645Smarcel 525179645Smarcel if (error) { 526179645Smarcel device_printf(dev,"Could not allocate TX DMA tag!\n"); 527179645Smarcel return (ENXIO); 528179645Smarcel } 529179645Smarcel 530179645Smarcel /* init transmit descriptors */ 531179645Smarcel STAILQ_INIT(&sc->sc_txfreeq); 532179645Smarcel STAILQ_INIT(&sc->sc_txdirtyq); 533179645Smarcel 534179645Smarcel /* create TX DMA maps */ 535179645Smarcel error = ENOMEM; 536179645Smarcel for (i = 0; i < BM_MAX_TX_PACKETS; i++) { 537179645Smarcel txs = &sc->sc_txsoft[i]; 538179645Smarcel txs->txs_mbuf = NULL; 539179645Smarcel error = bus_dmamap_create(sc->sc_tdma_tag, 0, &txs->txs_dmamap); 540179645Smarcel if (error) { 541179645Smarcel device_printf(sc->sc_dev, 542179645Smarcel "unable to create TX DMA map %d, error = %d\n", 543179645Smarcel i, error); 544179645Smarcel } 545179645Smarcel STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 546179645Smarcel } 547179645Smarcel 548179645Smarcel /* Create the receive buffer DMA maps. */ 549179645Smarcel for (i = 0; i < BM_MAX_RX_PACKETS; i++) { 550179645Smarcel error = bus_dmamap_create(sc->sc_rdma_tag, 0, 551179645Smarcel &sc->sc_rxsoft[i].rxs_dmamap); 552179645Smarcel if (error) { 553179645Smarcel device_printf(sc->sc_dev, 554179645Smarcel "unable to create RX DMA map %d, error = %d\n", 555179645Smarcel i, error); 556179645Smarcel } 557179645Smarcel sc->sc_rxsoft[i].rxs_mbuf = NULL; 558179645Smarcel } 559179645Smarcel 560179645Smarcel /* alloc interrupt */ 561179645Smarcel 562179645Smarcel sc->sc_txdmairqid = BM_TXDMA_INTERRUPT; 563179645Smarcel sc->sc_txdmairq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 564179645Smarcel &sc->sc_txdmairqid, RF_ACTIVE); 565179645Smarcel 566179645Smarcel if (error) { 567179645Smarcel device_printf(dev,"Could not allocate TX interrupt!\n"); 568179645Smarcel return (ENXIO); 569179645Smarcel } 570179645Smarcel 571179645Smarcel bus_setup_intr(dev,sc->sc_txdmairq, 572179645Smarcel INTR_TYPE_MISC | INTR_MPSAFE | INTR_ENTROPY, NULL, bm_txintr, sc, 573179645Smarcel &sc->sc_txihtx); 574179645Smarcel 575179645Smarcel sc->sc_rxdmairqid = BM_RXDMA_INTERRUPT; 576179645Smarcel sc->sc_rxdmairq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 577179645Smarcel &sc->sc_rxdmairqid, RF_ACTIVE); 578179645Smarcel 579179645Smarcel if (error) { 580179645Smarcel device_printf(dev,"Could not allocate RX interrupt!\n"); 581179645Smarcel return (ENXIO); 582179645Smarcel } 583179645Smarcel 584179645Smarcel bus_setup_intr(dev,sc->sc_rxdmairq, 585179645Smarcel INTR_TYPE_MISC | INTR_MPSAFE | INTR_ENTROPY, NULL, bm_rxintr, sc, 586179645Smarcel &sc->sc_rxih); 587179645Smarcel 588179645Smarcel /* 589179645Smarcel * Get the ethernet address from OpenFirmware 590179645Smarcel */ 591179645Smarcel eaddr = sc->sc_enaddr; 592179645Smarcel OF_getprop(node, "local-mac-address", eaddr, ETHER_ADDR_LEN); 593179645Smarcel 594179645Smarcel /* reset the adapter */ 595179645Smarcel bm_chip_setup(sc); 596179645Smarcel 597179645Smarcel /* setup MII */ 598179645Smarcel error = mii_phy_probe(dev, &sc->sc_miibus, bm_ifmedia_upd, 599179645Smarcel bm_ifmedia_sts); 600179645Smarcel if (error != 0) 601179645Smarcel device_printf(dev,"PHY probe failed: %d\n", error); 602179645Smarcel 603179645Smarcel sc->sc_mii = device_get_softc(sc->sc_miibus); 604179645Smarcel 605179645Smarcel if_initname(ifp, device_get_name(sc->sc_dev), 606179645Smarcel device_get_unit(sc->sc_dev)); 607179645Smarcel ifp->if_mtu = ETHERMTU; 608179645Smarcel ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 609179645Smarcel ifp->if_start = bm_start; 610179645Smarcel ifp->if_ioctl = bm_ioctl; 611179645Smarcel ifp->if_init = bm_init; 612179645Smarcel IFQ_SET_MAXLEN(&ifp->if_snd, BM_MAX_TX_PACKETS); 613179645Smarcel ifp->if_snd.ifq_drv_maxlen = BM_MAX_TX_PACKETS; 614179645Smarcel IFQ_SET_READY(&ifp->if_snd); 615179645Smarcel 616179645Smarcel /* Attach the interface. */ 617179645Smarcel ether_ifattach(ifp, sc->sc_enaddr); 618179645Smarcel ifp->if_hwassist = 0; 619179645Smarcel 620179645Smarcel return (0); 621179645Smarcel} 622179645Smarcel 623179645Smarcelstatic int 624179645Smarcelbm_detach(device_t dev) 625179645Smarcel{ 626179645Smarcel struct bm_softc *sc = device_get_softc(dev); 627179645Smarcel 628179645Smarcel BM_LOCK(sc); 629179645Smarcel bm_stop(sc); 630180233Snwhitehorn BM_UNLOCK(sc); 631179645Smarcel 632180233Snwhitehorn callout_drain(&sc->sc_tick_ch); 633180233Snwhitehorn ether_ifdetach(sc->sc_ifp); 634180233Snwhitehorn bus_teardown_intr(dev, sc->sc_txdmairq, sc->sc_txihtx); 635180233Snwhitehorn bus_teardown_intr(dev, sc->sc_rxdmairq, sc->sc_rxih); 636180233Snwhitehorn 637179645Smarcel dbdma_free_channel(sc->sc_txdma); 638179645Smarcel dbdma_free_channel(sc->sc_rxdma); 639179645Smarcel 640179645Smarcel bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_memrid, sc->sc_memr); 641179645Smarcel bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_txdmarid, 642179645Smarcel sc->sc_txdmar); 643179645Smarcel bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_rxdmarid, 644179645Smarcel sc->sc_rxdmar); 645179645Smarcel 646179645Smarcel bus_release_resource(dev, SYS_RES_IRQ, sc->sc_txdmairqid, 647179645Smarcel sc->sc_txdmairq); 648179645Smarcel bus_release_resource(dev, SYS_RES_IRQ, sc->sc_rxdmairqid, 649179645Smarcel sc->sc_rxdmairq); 650179645Smarcel 651179645Smarcel mtx_destroy(&sc->sc_mtx); 652180233Snwhitehorn if_free(sc->sc_ifp); 653179645Smarcel 654179645Smarcel return (0); 655179645Smarcel} 656179645Smarcel 657179645Smarcelstatic void 658179645Smarcelbm_shutdown(device_t dev) 659179645Smarcel{ 660180233Snwhitehorn struct bm_softc *sc; 661180233Snwhitehorn 662180233Snwhitehorn sc = device_get_softc(dev); 663180233Snwhitehorn 664180233Snwhitehorn BM_LOCK(sc); 665180233Snwhitehorn bm_stop(sc); 666180233Snwhitehorn BM_UNLOCK(sc); 667179645Smarcel} 668179645Smarcel 669179645Smarcelstatic void 670179645Smarcelbm_dummypacket(struct bm_softc *sc) 671179645Smarcel{ 672179645Smarcel struct mbuf *m; 673179645Smarcel struct ifnet *ifp; 674179645Smarcel 675179645Smarcel ifp = sc->sc_ifp; 676179645Smarcel 677179645Smarcel MGETHDR(m, M_DONTWAIT, MT_DATA); 678179645Smarcel 679179645Smarcel if (m == NULL) 680179645Smarcel return; 681179645Smarcel 682179645Smarcel bcopy(sc->sc_enaddr, 683179645Smarcel mtod(m, struct ether_header *)->ether_dhost, ETHER_ADDR_LEN); 684179645Smarcel bcopy(sc->sc_enaddr, 685179645Smarcel mtod(m, struct ether_header *)->ether_shost, ETHER_ADDR_LEN); 686179645Smarcel mtod(m, struct ether_header *)->ether_type = htons(3); 687179645Smarcel mtod(m, unsigned char *)[14] = 0; 688179645Smarcel mtod(m, unsigned char *)[15] = 0; 689179645Smarcel mtod(m, unsigned char *)[16] = 0xE3; 690179645Smarcel m->m_len = m->m_pkthdr.len = sizeof(struct ether_header) + 3; 691179645Smarcel IF_ENQUEUE(&ifp->if_snd, m); 692182670Snwhitehorn bm_start_locked(ifp); 693179645Smarcel} 694179645Smarcel 695179645Smarcelstatic void 696179645Smarcelbm_rxintr(void *xsc) 697179645Smarcel{ 698179645Smarcel struct bm_softc *sc = xsc; 699179645Smarcel struct ifnet *ifp = sc->sc_ifp; 700179645Smarcel struct mbuf *m; 701179645Smarcel int i, prev_stop, new_stop; 702179645Smarcel uint16_t status; 703179645Smarcel 704179645Smarcel BM_LOCK(sc); 705179645Smarcel 706179645Smarcel status = dbdma_get_chan_status(sc->sc_rxdma); 707179645Smarcel if (status & DBDMA_STATUS_DEAD) { 708179645Smarcel dbdma_reset(sc->sc_rxdma); 709179645Smarcel BM_UNLOCK(sc); 710179645Smarcel return; 711179645Smarcel } 712179645Smarcel if (!(status & DBDMA_STATUS_RUN)) { 713179645Smarcel device_printf(sc->sc_dev,"Bad RX Interrupt!\n"); 714179645Smarcel BM_UNLOCK(sc); 715179645Smarcel return; 716179645Smarcel } 717179645Smarcel 718179645Smarcel prev_stop = sc->next_rxdma_slot - 1; 719179645Smarcel if (prev_stop < 0) 720179645Smarcel prev_stop = sc->rxdma_loop_slot - 1; 721179645Smarcel 722179645Smarcel if (prev_stop < 0) { 723179645Smarcel BM_UNLOCK(sc); 724179645Smarcel return; 725179645Smarcel } 726179645Smarcel 727179645Smarcel new_stop = -1; 728179645Smarcel dbdma_sync_commands(sc->sc_rxdma, BUS_DMASYNC_POSTREAD); 729179645Smarcel 730179645Smarcel for (i = sc->next_rxdma_slot; i < BM_MAX_RX_PACKETS; i++) { 731179645Smarcel if (i == sc->rxdma_loop_slot) 732179645Smarcel i = 0; 733179645Smarcel 734179645Smarcel if (i == prev_stop) 735179645Smarcel break; 736179645Smarcel 737179645Smarcel status = dbdma_get_cmd_status(sc->sc_rxdma, i); 738179645Smarcel 739179645Smarcel if (status == 0) 740179645Smarcel break; 741179645Smarcel 742179645Smarcel m = sc->sc_rxsoft[i].rxs_mbuf; 743179645Smarcel 744179645Smarcel if (bm_add_rxbuf(sc, i)) { 745179645Smarcel ifp->if_ierrors++; 746179645Smarcel m = NULL; 747179645Smarcel continue; 748179645Smarcel } 749179645Smarcel 750179645Smarcel if (m == NULL) 751179645Smarcel continue; 752179645Smarcel 753179645Smarcel ifp->if_ipackets++; 754179645Smarcel m->m_pkthdr.rcvif = ifp; 755179645Smarcel m->m_len -= (dbdma_get_residuals(sc->sc_rxdma, i) + 2); 756179645Smarcel m->m_pkthdr.len = m->m_len; 757179645Smarcel 758179645Smarcel /* Send up the stack */ 759179645Smarcel BM_UNLOCK(sc); 760179645Smarcel (*ifp->if_input)(ifp, m); 761179645Smarcel BM_LOCK(sc); 762179645Smarcel 763179645Smarcel /* Clear all fields on this command */ 764179645Smarcel bm_add_rxbuf_dma(sc, i); 765179645Smarcel 766179645Smarcel new_stop = i; 767179645Smarcel } 768179645Smarcel 769179645Smarcel /* Change the last packet we processed to the ring buffer terminator, 770179645Smarcel * and restore a receive buffer to the old terminator */ 771179645Smarcel if (new_stop >= 0) { 772179645Smarcel dbdma_insert_stop(sc->sc_rxdma, new_stop); 773179645Smarcel bm_add_rxbuf_dma(sc, prev_stop); 774179645Smarcel if (i < sc->rxdma_loop_slot) 775179645Smarcel sc->next_rxdma_slot = i; 776179645Smarcel else 777179645Smarcel sc->next_rxdma_slot = 0; 778179645Smarcel } 779179645Smarcel dbdma_sync_commands(sc->sc_rxdma, BUS_DMASYNC_PREWRITE); 780179645Smarcel 781179645Smarcel dbdma_wake(sc->sc_rxdma); 782179645Smarcel 783179645Smarcel BM_UNLOCK(sc); 784179645Smarcel} 785179645Smarcel 786179645Smarcelstatic void 787179645Smarcelbm_txintr(void *xsc) 788179645Smarcel{ 789179645Smarcel struct bm_softc *sc = xsc; 790179645Smarcel struct ifnet *ifp = sc->sc_ifp; 791179645Smarcel struct bm_txsoft *txs; 792179645Smarcel int progress = 0; 793179645Smarcel 794179645Smarcel BM_LOCK(sc); 795179645Smarcel 796179645Smarcel while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 797179645Smarcel if (!dbdma_get_cmd_status(sc->sc_txdma, txs->txs_lastdesc)) 798179645Smarcel break; 799179645Smarcel 800179645Smarcel STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 801179645Smarcel bus_dmamap_unload(sc->sc_tdma_tag, txs->txs_dmamap); 802179645Smarcel 803179645Smarcel if (txs->txs_mbuf != NULL) { 804179645Smarcel m_freem(txs->txs_mbuf); 805179645Smarcel txs->txs_mbuf = NULL; 806179645Smarcel } 807179645Smarcel 808179645Smarcel /* Set the first used TXDMA slot to the location of the 809179645Smarcel * STOP/NOP command associated with this packet. */ 810179645Smarcel 811179645Smarcel sc->first_used_txdma_slot = txs->txs_stopdesc; 812179645Smarcel 813179645Smarcel STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 814179645Smarcel 815179645Smarcel ifp->if_opackets++; 816179645Smarcel progress = 1; 817179645Smarcel } 818179645Smarcel 819179645Smarcel if (progress) { 820179645Smarcel /* 821179645Smarcel * We freed some descriptors, so reset IFF_DRV_OACTIVE 822179645Smarcel * and restart. 823179645Smarcel */ 824179645Smarcel ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 825179645Smarcel sc->sc_wdog_timer = STAILQ_EMPTY(&sc->sc_txdirtyq) ? 0 : 5; 826179645Smarcel 827179645Smarcel if ((ifp->if_drv_flags & IFF_DRV_RUNNING) && 828179645Smarcel !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 829179645Smarcel bm_start_locked(ifp); 830179645Smarcel } 831179645Smarcel 832179645Smarcel BM_UNLOCK(sc); 833179645Smarcel} 834179645Smarcel 835179645Smarcelstatic void 836179645Smarcelbm_start(struct ifnet *ifp) 837179645Smarcel{ 838179645Smarcel struct bm_softc *sc = ifp->if_softc; 839179645Smarcel 840179645Smarcel BM_LOCK(sc); 841179645Smarcel bm_start_locked(ifp); 842179645Smarcel BM_UNLOCK(sc); 843179645Smarcel} 844179645Smarcel 845179645Smarcelstatic void 846179645Smarcelbm_start_locked(struct ifnet *ifp) 847179645Smarcel{ 848179645Smarcel struct bm_softc *sc = ifp->if_softc; 849179645Smarcel struct mbuf *mb_head; 850179645Smarcel int prev_stop; 851179645Smarcel int txqueued = 0; 852179645Smarcel 853179645Smarcel /* 854179645Smarcel * We lay out our DBDMA program in the following manner: 855179645Smarcel * OUTPUT_MORE 856179645Smarcel * ... 857179645Smarcel * OUTPUT_LAST (+ Interrupt) 858179645Smarcel * STOP 859179645Smarcel * 860179645Smarcel * To extend the channel, we append a new program, 861179645Smarcel * then replace STOP with NOP and wake the channel. 862179645Smarcel * If we stalled on the STOP already, the program proceeds, 863179645Smarcel * if not it will sail through the NOP. 864179645Smarcel */ 865179645Smarcel 866179645Smarcel while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 867179645Smarcel IFQ_DRV_DEQUEUE(&ifp->if_snd, mb_head); 868179645Smarcel 869179645Smarcel if (mb_head == NULL) 870179645Smarcel break; 871179645Smarcel 872179645Smarcel prev_stop = sc->next_txdma_slot - 1; 873179645Smarcel 874179645Smarcel if (bm_encap(sc, &mb_head)) { 875179645Smarcel /* Put the packet back and stop */ 876179645Smarcel ifp->if_drv_flags |= IFF_DRV_OACTIVE; 877179645Smarcel IFQ_DRV_PREPEND(&ifp->if_snd, mb_head); 878179645Smarcel break; 879179645Smarcel } 880179645Smarcel 881179645Smarcel dbdma_insert_nop(sc->sc_txdma, prev_stop); 882179645Smarcel 883179645Smarcel txqueued = 1; 884179645Smarcel 885179645Smarcel BPF_MTAP(ifp, mb_head); 886179645Smarcel } 887179645Smarcel 888179645Smarcel dbdma_sync_commands(sc->sc_txdma, BUS_DMASYNC_PREWRITE); 889179645Smarcel 890179645Smarcel if (txqueued) { 891179645Smarcel dbdma_wake(sc->sc_txdma); 892179645Smarcel sc->sc_wdog_timer = 5; 893179645Smarcel } 894179645Smarcel} 895179645Smarcel 896179645Smarcelstatic int 897179645Smarcelbm_encap(struct bm_softc *sc, struct mbuf **m_head) 898179645Smarcel{ 899179645Smarcel bus_dma_segment_t segs[BM_NTXSEGS]; 900179645Smarcel struct bm_txsoft *txs; 901179645Smarcel struct mbuf *m; 902179645Smarcel int nsegs = BM_NTXSEGS; 903179645Smarcel int error = 0; 904179645Smarcel uint8_t branch_type; 905179645Smarcel int i; 906179645Smarcel 907179645Smarcel /* Limit the command size to the number of free DBDMA slots */ 908179645Smarcel 909179645Smarcel if (sc->next_txdma_slot >= sc->first_used_txdma_slot) 910179645Smarcel nsegs = BM_MAX_DMA_COMMANDS - 2 - sc->next_txdma_slot + 911179645Smarcel sc->first_used_txdma_slot; /* -2 for branch and indexing */ 912179645Smarcel else 913179645Smarcel nsegs = sc->first_used_txdma_slot - sc->next_txdma_slot; 914179645Smarcel 915179645Smarcel /* Remove one slot for the STOP/NOP terminator */ 916179645Smarcel nsegs--; 917179645Smarcel 918179645Smarcel if (nsegs > BM_NTXSEGS) 919179645Smarcel nsegs = BM_NTXSEGS; 920179645Smarcel 921179645Smarcel /* Get a work queue entry. */ 922179645Smarcel if ((txs = STAILQ_FIRST(&sc->sc_txfreeq)) == NULL) { 923179645Smarcel /* Ran out of descriptors. */ 924179645Smarcel return (ENOBUFS); 925179645Smarcel } 926179645Smarcel 927179645Smarcel error = bus_dmamap_load_mbuf_sg(sc->sc_tdma_tag, txs->txs_dmamap, 928179645Smarcel *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 929179645Smarcel 930179645Smarcel if (error == EFBIG) { 931179645Smarcel m = m_collapse(*m_head, M_DONTWAIT, nsegs); 932179645Smarcel if (m == NULL) { 933179645Smarcel m_freem(*m_head); 934179645Smarcel *m_head = NULL; 935179645Smarcel return (ENOBUFS); 936179645Smarcel } 937179645Smarcel *m_head = m; 938179645Smarcel 939179645Smarcel error = bus_dmamap_load_mbuf_sg(sc->sc_tdma_tag, 940179645Smarcel txs->txs_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 941179645Smarcel if (error != 0) { 942179645Smarcel m_freem(*m_head); 943179645Smarcel *m_head = NULL; 944179645Smarcel return (error); 945179645Smarcel } 946179645Smarcel } else if (error != 0) 947179645Smarcel return (error); 948179645Smarcel 949179645Smarcel if (nsegs == 0) { 950179645Smarcel m_freem(*m_head); 951179645Smarcel *m_head = NULL; 952179645Smarcel return (EIO); 953179645Smarcel } 954179645Smarcel 955179645Smarcel txs->txs_ndescs = nsegs; 956179645Smarcel txs->txs_firstdesc = sc->next_txdma_slot; 957179645Smarcel 958179645Smarcel for (i = 0; i < nsegs; i++) { 959179645Smarcel /* Loop back to the beginning if this is our last slot */ 960179645Smarcel if (sc->next_txdma_slot == (BM_MAX_DMA_COMMANDS - 1)) 961179645Smarcel branch_type = DBDMA_ALWAYS; 962179645Smarcel else 963179645Smarcel branch_type = DBDMA_NEVER; 964179645Smarcel 965179645Smarcel if (i+1 == nsegs) 966179645Smarcel txs->txs_lastdesc = sc->next_txdma_slot; 967179645Smarcel 968179645Smarcel dbdma_insert_command(sc->sc_txdma, sc->next_txdma_slot++, 969179645Smarcel (i + 1 < nsegs) ? DBDMA_OUTPUT_MORE : DBDMA_OUTPUT_LAST, 970179645Smarcel 0, segs[i].ds_addr, segs[i].ds_len, 971179645Smarcel (i + 1 < nsegs) ? DBDMA_NEVER : DBDMA_ALWAYS, 972179645Smarcel branch_type, DBDMA_NEVER, 0); 973179645Smarcel 974179645Smarcel if (branch_type == DBDMA_ALWAYS) 975179645Smarcel sc->next_txdma_slot = 0; 976179645Smarcel } 977179645Smarcel 978179645Smarcel /* We have a corner case where the STOP command is the last slot, 979179645Smarcel * but you can't branch in STOP commands. So add a NOP branch here 980179645Smarcel * and the STOP in slot 0. */ 981179645Smarcel 982179645Smarcel if (sc->next_txdma_slot == (BM_MAX_DMA_COMMANDS - 1)) { 983179645Smarcel dbdma_insert_branch(sc->sc_txdma, sc->next_txdma_slot, 0); 984179645Smarcel sc->next_txdma_slot = 0; 985179645Smarcel } 986179645Smarcel 987179645Smarcel txs->txs_stopdesc = sc->next_txdma_slot; 988179645Smarcel dbdma_insert_stop(sc->sc_txdma, sc->next_txdma_slot++); 989179645Smarcel 990179645Smarcel STAILQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 991179645Smarcel STAILQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 992179645Smarcel txs->txs_mbuf = *m_head; 993179645Smarcel 994179645Smarcel return (0); 995179645Smarcel} 996179645Smarcel 997179645Smarcelstatic int 998179645Smarcelbm_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 999179645Smarcel{ 1000179645Smarcel struct bm_softc *sc = ifp->if_softc; 1001179645Smarcel struct ifreq *ifr = (struct ifreq *)data; 1002179645Smarcel int error; 1003179645Smarcel 1004179645Smarcel error = 0; 1005179645Smarcel 1006179645Smarcel switch(cmd) { 1007179645Smarcel case SIOCSIFFLAGS: 1008179645Smarcel BM_LOCK(sc); 1009179645Smarcel if ((ifp->if_flags & IFF_UP) != 0) { 1010179645Smarcel if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 1011179645Smarcel ((ifp->if_flags ^ sc->sc_ifpflags) & 1012179645Smarcel (IFF_ALLMULTI | IFF_PROMISC)) != 0) 1013179645Smarcel bm_setladrf(sc); 1014179645Smarcel else 1015179645Smarcel bm_init_locked(sc); 1016179645Smarcel } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1017179645Smarcel bm_stop(sc); 1018179645Smarcel sc->sc_ifpflags = ifp->if_flags; 1019179645Smarcel BM_UNLOCK(sc); 1020179645Smarcel break; 1021179645Smarcel case SIOCADDMULTI: 1022179645Smarcel case SIOCDELMULTI: 1023179645Smarcel BM_LOCK(sc); 1024179645Smarcel bm_setladrf(sc); 1025179645Smarcel BM_UNLOCK(sc); 1026179645Smarcel case SIOCGIFMEDIA: 1027179645Smarcel case SIOCSIFMEDIA: 1028179645Smarcel error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii->mii_media, cmd); 1029179645Smarcel break; 1030179645Smarcel default: 1031179645Smarcel error = ether_ioctl(ifp, cmd, data); 1032179645Smarcel break; 1033179645Smarcel } 1034179645Smarcel 1035179645Smarcel return (error); 1036179645Smarcel} 1037179645Smarcel 1038179645Smarcelstatic void 1039179645Smarcelbm_setladrf(struct bm_softc *sc) 1040179645Smarcel{ 1041179645Smarcel struct ifnet *ifp = sc->sc_ifp; 1042179645Smarcel struct ifmultiaddr *inm; 1043179645Smarcel uint16_t hash[4]; 1044179645Smarcel uint16_t reg; 1045179645Smarcel uint32_t crc; 1046179645Smarcel 1047179645Smarcel reg = BM_CRC_ENABLE | BM_REJECT_OWN_PKTS; 1048179645Smarcel 1049179645Smarcel /* Turn off RX MAC while we fiddle its settings */ 1050179645Smarcel CSR_WRITE_2(sc, BM_RX_CONFIG, reg); 1051179645Smarcel while (CSR_READ_2(sc, BM_RX_CONFIG) & BM_ENABLE) 1052179645Smarcel DELAY(10); 1053179645Smarcel 1054179645Smarcel if ((ifp->if_flags & IFF_PROMISC) != 0) { 1055179645Smarcel reg |= BM_PROMISC; 1056179645Smarcel 1057179645Smarcel CSR_WRITE_2(sc, BM_RX_CONFIG, reg); 1058179645Smarcel 1059179645Smarcel DELAY(15); 1060179645Smarcel 1061179645Smarcel reg = CSR_READ_2(sc, BM_RX_CONFIG); 1062179645Smarcel reg |= BM_ENABLE; 1063179645Smarcel CSR_WRITE_2(sc, BM_RX_CONFIG, reg); 1064179645Smarcel return; 1065179645Smarcel } 1066179645Smarcel 1067179645Smarcel if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 1068179645Smarcel hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1069179645Smarcel } else { 1070179645Smarcel /* Clear the hash table. */ 1071179645Smarcel memset(hash, 0, sizeof(hash)); 1072179645Smarcel 1073179645Smarcel IF_ADDR_LOCK(ifp); 1074179645Smarcel TAILQ_FOREACH(inm, &ifp->if_multiaddrs, ifma_link) { 1075179645Smarcel if (inm->ifma_addr->sa_family != AF_LINK) 1076179645Smarcel continue; 1077179645Smarcel crc = ether_crc32_le(LLADDR((struct sockaddr_dl *) 1078179645Smarcel inm->ifma_addr), ETHER_ADDR_LEN); 1079179645Smarcel 1080179645Smarcel /* We just want the 6 most significant bits */ 1081179645Smarcel crc >>= 26; 1082179645Smarcel 1083179645Smarcel /* Set the corresponding bit in the filter. */ 1084179645Smarcel hash[crc >> 4] |= 1 << (crc & 0xf); 1085179645Smarcel } 1086179645Smarcel IF_ADDR_UNLOCK(ifp); 1087179645Smarcel } 1088179645Smarcel 1089179645Smarcel /* Write out new hash table */ 1090179645Smarcel CSR_WRITE_2(sc, BM_HASHTAB0, hash[0]); 1091179645Smarcel CSR_WRITE_2(sc, BM_HASHTAB1, hash[1]); 1092179645Smarcel CSR_WRITE_2(sc, BM_HASHTAB2, hash[2]); 1093179645Smarcel CSR_WRITE_2(sc, BM_HASHTAB3, hash[3]); 1094179645Smarcel 1095179645Smarcel /* And turn the RX MAC back on, this time with the hash bit set */ 1096179645Smarcel reg |= BM_HASH_FILTER_ENABLE; 1097179645Smarcel CSR_WRITE_2(sc, BM_RX_CONFIG, reg); 1098179645Smarcel 1099179645Smarcel while (!(CSR_READ_2(sc, BM_RX_CONFIG) & BM_HASH_FILTER_ENABLE)) 1100179645Smarcel DELAY(10); 1101179645Smarcel 1102179645Smarcel reg = CSR_READ_2(sc, BM_RX_CONFIG); 1103179645Smarcel reg |= BM_ENABLE; 1104179645Smarcel CSR_WRITE_2(sc, BM_RX_CONFIG, reg); 1105179645Smarcel} 1106179645Smarcel 1107179645Smarcelstatic void 1108179645Smarcelbm_init(void *xsc) 1109179645Smarcel{ 1110179645Smarcel struct bm_softc *sc = xsc; 1111179645Smarcel 1112179645Smarcel BM_LOCK(sc); 1113179645Smarcel bm_init_locked(sc); 1114179645Smarcel BM_UNLOCK(sc); 1115179645Smarcel} 1116179645Smarcel 1117179645Smarcelstatic void 1118179645Smarcelbm_chip_setup(struct bm_softc *sc) 1119179645Smarcel{ 1120179645Smarcel uint16_t reg; 1121179645Smarcel uint16_t *eaddr_sect; 1122179645Smarcel char hrow_path[128]; 1123179645Smarcel ihandle_t hrow_ih; 1124179645Smarcel 1125179645Smarcel eaddr_sect = (uint16_t *)(sc->sc_enaddr); 1126179645Smarcel 1127179645Smarcel /* Enable BMAC cell */ 1128179645Smarcel OF_package_to_path(OF_parent(ofw_bus_get_node(sc->sc_dev)), 1129179645Smarcel hrow_path, sizeof(hrow_path)); 1130179645Smarcel hrow_ih = OF_open(hrow_path); 1131179645Smarcel if (hrow_ih == -1) { 1132179645Smarcel device_printf(sc->sc_dev, 1133179645Smarcel "Enabling BMAC cell failed! Hoping it's already active.\n"); 1134179645Smarcel } else { 1135179645Smarcel OF_call_method("enable-enet", hrow_ih, 0, 0); 1136179645Smarcel OF_close(hrow_ih); 1137179645Smarcel } 1138179645Smarcel 1139179645Smarcel /* Reset chip */ 1140179645Smarcel CSR_WRITE_2(sc, BM_RX_RESET, 0x0000); 1141179645Smarcel CSR_WRITE_2(sc, BM_TX_RESET, 0x0001); 1142179645Smarcel do { 1143179645Smarcel reg = CSR_READ_2(sc, BM_TX_RESET); 1144179645Smarcel } while (reg & 0x0001); 1145179645Smarcel 1146179645Smarcel /* Some random junk. OS X uses the system time. We use 1147179645Smarcel * the low 16 bits of the MAC address. */ 1148179645Smarcel CSR_WRITE_2(sc, BM_TX_RANDSEED, eaddr_sect[2]); 1149179645Smarcel 1150179645Smarcel /* Enable transmit */ 1151179645Smarcel reg = CSR_READ_2(sc, BM_TX_IFC); 1152179645Smarcel reg |= BM_ENABLE; 1153179645Smarcel CSR_WRITE_2(sc, BM_TX_IFC, reg); 1154179645Smarcel 1155179645Smarcel CSR_READ_2(sc, BM_TX_PEAKCNT); 1156179645Smarcel} 1157179645Smarcel 1158179645Smarcelstatic void 1159179645Smarcelbm_stop(struct bm_softc *sc) 1160179645Smarcel{ 1161179645Smarcel struct bm_txsoft *txs; 1162179645Smarcel uint16_t reg; 1163179645Smarcel 1164179645Smarcel /* Disable TX and RX MACs */ 1165179645Smarcel reg = CSR_READ_2(sc, BM_TX_CONFIG); 1166179645Smarcel reg &= ~BM_ENABLE; 1167179645Smarcel CSR_WRITE_2(sc, BM_TX_CONFIG, reg); 1168179645Smarcel 1169179645Smarcel reg = CSR_READ_2(sc, BM_RX_CONFIG); 1170179645Smarcel reg &= ~BM_ENABLE; 1171179645Smarcel CSR_WRITE_2(sc, BM_RX_CONFIG, reg); 1172179645Smarcel 1173179645Smarcel DELAY(100); 1174179645Smarcel 1175179645Smarcel /* Stop DMA engine */ 1176179645Smarcel dbdma_stop(sc->sc_rxdma); 1177179645Smarcel dbdma_stop(sc->sc_txdma); 1178179645Smarcel sc->next_rxdma_slot = 0; 1179179645Smarcel sc->rxdma_loop_slot = 0; 1180179645Smarcel 1181179645Smarcel /* Disable interrupts */ 1182179645Smarcel bm_disable_interrupts(sc); 1183179645Smarcel 1184179645Smarcel /* Don't worry about pending transmits anymore */ 1185179645Smarcel while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1186179645Smarcel STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1187179645Smarcel if (txs->txs_ndescs != 0) { 1188179645Smarcel bus_dmamap_sync(sc->sc_tdma_tag, txs->txs_dmamap, 1189179645Smarcel BUS_DMASYNC_POSTWRITE); 1190179645Smarcel bus_dmamap_unload(sc->sc_tdma_tag, txs->txs_dmamap); 1191179645Smarcel if (txs->txs_mbuf != NULL) { 1192179645Smarcel m_freem(txs->txs_mbuf); 1193179645Smarcel txs->txs_mbuf = NULL; 1194179645Smarcel } 1195179645Smarcel } 1196179645Smarcel STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1197179645Smarcel } 1198179645Smarcel 1199179645Smarcel /* And we're down */ 1200179645Smarcel sc->sc_ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1201179645Smarcel sc->sc_wdog_timer = 0; 1202180233Snwhitehorn callout_stop(&sc->sc_tick_ch); 1203179645Smarcel} 1204179645Smarcel 1205179645Smarcelstatic void 1206179645Smarcelbm_init_locked(struct bm_softc *sc) 1207179645Smarcel{ 1208179645Smarcel uint16_t reg; 1209179645Smarcel uint16_t *eaddr_sect; 1210179645Smarcel struct bm_rxsoft *rxs; 1211179645Smarcel int i; 1212179645Smarcel 1213179645Smarcel eaddr_sect = (uint16_t *)(sc->sc_enaddr); 1214179645Smarcel 1215179645Smarcel /* Zero RX slot info and stop DMA */ 1216179645Smarcel dbdma_stop(sc->sc_rxdma); 1217179645Smarcel dbdma_stop(sc->sc_txdma); 1218179645Smarcel sc->next_rxdma_slot = 0; 1219179645Smarcel sc->rxdma_loop_slot = 0; 1220179645Smarcel 1221179645Smarcel /* Initialize TX/RX DBDMA programs */ 1222179645Smarcel dbdma_insert_stop(sc->sc_rxdma, 0); 1223179645Smarcel dbdma_insert_stop(sc->sc_txdma, 0); 1224179645Smarcel dbdma_set_current_cmd(sc->sc_rxdma, 0); 1225179645Smarcel dbdma_set_current_cmd(sc->sc_txdma, 0); 1226179645Smarcel 1227179645Smarcel sc->next_rxdma_slot = 0; 1228179645Smarcel sc->next_txdma_slot = 1; 1229179645Smarcel sc->first_used_txdma_slot = 0; 1230179645Smarcel 1231179645Smarcel for (i = 0; i < BM_MAX_RX_PACKETS; i++) { 1232179645Smarcel rxs = &sc->sc_rxsoft[i]; 1233179645Smarcel rxs->dbdma_slot = i; 1234179645Smarcel 1235179645Smarcel if (rxs->rxs_mbuf == NULL) { 1236179645Smarcel bm_add_rxbuf(sc, i); 1237179645Smarcel 1238179645Smarcel if (rxs->rxs_mbuf == NULL) { 1239179645Smarcel /* If we can't add anymore, mark the problem */ 1240179645Smarcel rxs->dbdma_slot = -1; 1241179645Smarcel break; 1242179645Smarcel } 1243179645Smarcel } 1244179645Smarcel 1245179645Smarcel if (i > 0) 1246179645Smarcel bm_add_rxbuf_dma(sc, i); 1247179645Smarcel } 1248179645Smarcel 1249179645Smarcel /* 1250179645Smarcel * Now terminate the RX ring buffer, and follow with the loop to 1251179645Smarcel * the beginning. 1252179645Smarcel */ 1253179645Smarcel dbdma_insert_stop(sc->sc_rxdma, i - 1); 1254179645Smarcel dbdma_insert_branch(sc->sc_rxdma, i, 0); 1255179645Smarcel sc->rxdma_loop_slot = i; 1256179645Smarcel 1257179645Smarcel /* Now add in the first element of the RX DMA chain */ 1258179645Smarcel bm_add_rxbuf_dma(sc, 0); 1259179645Smarcel 1260179645Smarcel dbdma_sync_commands(sc->sc_rxdma, BUS_DMASYNC_PREWRITE); 1261179645Smarcel dbdma_sync_commands(sc->sc_txdma, BUS_DMASYNC_PREWRITE); 1262179645Smarcel 1263179645Smarcel /* Zero collision counters */ 1264179645Smarcel CSR_WRITE_2(sc, BM_TX_NCCNT, 0); 1265179645Smarcel CSR_WRITE_2(sc, BM_TX_FCCNT, 0); 1266179645Smarcel CSR_WRITE_2(sc, BM_TX_EXCNT, 0); 1267179645Smarcel CSR_WRITE_2(sc, BM_TX_LTCNT, 0); 1268179645Smarcel 1269179645Smarcel /* Zero receive counters */ 1270179645Smarcel CSR_WRITE_2(sc, BM_RX_FRCNT, 0); 1271179645Smarcel CSR_WRITE_2(sc, BM_RX_LECNT, 0); 1272179645Smarcel CSR_WRITE_2(sc, BM_RX_AECNT, 0); 1273179645Smarcel CSR_WRITE_2(sc, BM_RX_FECNT, 0); 1274179645Smarcel CSR_WRITE_2(sc, BM_RXCV, 0); 1275179645Smarcel 1276179645Smarcel /* Prime transmit */ 1277179645Smarcel CSR_WRITE_2(sc, BM_TX_THRESH, 0xff); 1278179645Smarcel 1279179645Smarcel CSR_WRITE_2(sc, BM_TXFIFO_CSR, 0); 1280179645Smarcel CSR_WRITE_2(sc, BM_TXFIFO_CSR, 0x0001); 1281179645Smarcel 1282179645Smarcel /* Prime receive */ 1283179645Smarcel CSR_WRITE_2(sc, BM_RXFIFO_CSR, 0); 1284179645Smarcel CSR_WRITE_2(sc, BM_RXFIFO_CSR, 0x0001); 1285179645Smarcel 1286179645Smarcel /* Clear status reg */ 1287179645Smarcel CSR_READ_2(sc, BM_STATUS); 1288179645Smarcel 1289179645Smarcel /* Zero hash filters */ 1290179645Smarcel CSR_WRITE_2(sc, BM_HASHTAB0, 0); 1291179645Smarcel CSR_WRITE_2(sc, BM_HASHTAB1, 0); 1292179645Smarcel CSR_WRITE_2(sc, BM_HASHTAB2, 0); 1293179645Smarcel CSR_WRITE_2(sc, BM_HASHTAB3, 0); 1294179645Smarcel 1295179645Smarcel /* Write MAC address to chip */ 1296179645Smarcel CSR_WRITE_2(sc, BM_MACADDR0, eaddr_sect[0]); 1297179645Smarcel CSR_WRITE_2(sc, BM_MACADDR1, eaddr_sect[1]); 1298179645Smarcel CSR_WRITE_2(sc, BM_MACADDR2, eaddr_sect[2]); 1299179645Smarcel 1300179645Smarcel /* Final receive engine setup */ 1301179645Smarcel reg = BM_CRC_ENABLE | BM_REJECT_OWN_PKTS | BM_HASH_FILTER_ENABLE; 1302179645Smarcel CSR_WRITE_2(sc, BM_RX_CONFIG, reg); 1303179645Smarcel 1304179645Smarcel /* Now turn it all on! */ 1305179645Smarcel dbdma_reset(sc->sc_rxdma); 1306179645Smarcel dbdma_reset(sc->sc_txdma); 1307179645Smarcel 1308179645Smarcel /* Enable RX and TX MACs. Setting the address filter has 1309179645Smarcel * the side effect of enabling the RX MAC. */ 1310179645Smarcel bm_setladrf(sc); 1311179645Smarcel 1312179645Smarcel reg = CSR_READ_2(sc, BM_TX_CONFIG); 1313179645Smarcel reg |= BM_ENABLE; 1314179645Smarcel CSR_WRITE_2(sc, BM_TX_CONFIG, reg); 1315179645Smarcel 1316179645Smarcel /* 1317179645Smarcel * Enable interrupts, unwedge the controller with a dummy packet, 1318179645Smarcel * and nudge the DMA queue. 1319179645Smarcel */ 1320179645Smarcel bm_enable_interrupts(sc); 1321179645Smarcel bm_dummypacket(sc); 1322179645Smarcel dbdma_wake(sc->sc_rxdma); /* Nudge RXDMA */ 1323179645Smarcel 1324179645Smarcel sc->sc_ifp->if_drv_flags |= IFF_DRV_RUNNING; 1325179645Smarcel sc->sc_ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1326179645Smarcel sc->sc_ifpflags = sc->sc_ifp->if_flags; 1327179645Smarcel 1328179645Smarcel /* Resync PHY and MAC states */ 1329179645Smarcel sc->sc_mii = device_get_softc(sc->sc_miibus); 1330179645Smarcel sc->sc_duplex = ~IFM_FDX; 1331179645Smarcel mii_mediachg(sc->sc_mii); 1332179645Smarcel 1333179645Smarcel /* Start the one second timer. */ 1334179645Smarcel sc->sc_wdog_timer = 0; 1335179645Smarcel callout_reset(&sc->sc_tick_ch, hz, bm_tick, sc); 1336179645Smarcel} 1337179645Smarcel 1338179645Smarcelstatic void 1339179645Smarcelbm_tick(void *arg) 1340179645Smarcel{ 1341179645Smarcel struct bm_softc *sc = arg; 1342179645Smarcel 1343179645Smarcel /* Read error counters */ 1344179645Smarcel sc->sc_ifp->if_collisions += CSR_READ_2(sc, BM_TX_NCCNT) + 1345179645Smarcel CSR_READ_2(sc, BM_TX_FCCNT) + CSR_READ_2(sc, BM_TX_EXCNT) + 1346179645Smarcel CSR_READ_2(sc, BM_TX_LTCNT); 1347179645Smarcel 1348179645Smarcel sc->sc_ifp->if_ierrors += CSR_READ_2(sc, BM_RX_LECNT) + 1349179645Smarcel CSR_READ_2(sc, BM_RX_AECNT) + CSR_READ_2(sc, BM_RX_FECNT); 1350179645Smarcel 1351179645Smarcel /* Zero collision counters */ 1352179645Smarcel CSR_WRITE_2(sc, BM_TX_NCCNT, 0); 1353179645Smarcel CSR_WRITE_2(sc, BM_TX_FCCNT, 0); 1354179645Smarcel CSR_WRITE_2(sc, BM_TX_EXCNT, 0); 1355179645Smarcel CSR_WRITE_2(sc, BM_TX_LTCNT, 0); 1356179645Smarcel 1357179645Smarcel /* Zero receive counters */ 1358179645Smarcel CSR_WRITE_2(sc, BM_RX_FRCNT, 0); 1359179645Smarcel CSR_WRITE_2(sc, BM_RX_LECNT, 0); 1360179645Smarcel CSR_WRITE_2(sc, BM_RX_AECNT, 0); 1361179645Smarcel CSR_WRITE_2(sc, BM_RX_FECNT, 0); 1362179645Smarcel CSR_WRITE_2(sc, BM_RXCV, 0); 1363179645Smarcel 1364179645Smarcel /* Check for link changes and run watchdog */ 1365179645Smarcel mii_tick(sc->sc_mii); 1366179645Smarcel bm_miibus_statchg(sc->sc_dev); 1367179645Smarcel 1368180233Snwhitehorn if (sc->sc_wdog_timer == 0 || --sc->sc_wdog_timer != 0) { 1369180233Snwhitehorn callout_reset(&sc->sc_tick_ch, hz, bm_tick, sc); 1370179645Smarcel return; 1371180233Snwhitehorn } 1372179645Smarcel 1373180233Snwhitehorn /* Problems */ 1374179645Smarcel device_printf(sc->sc_dev, "device timeout\n"); 1375179645Smarcel 1376179645Smarcel bm_init_locked(sc); 1377179645Smarcel} 1378179645Smarcel 1379179645Smarcelstatic int 1380179645Smarcelbm_add_rxbuf(struct bm_softc *sc, int idx) 1381179645Smarcel{ 1382179645Smarcel struct bm_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1383179645Smarcel struct mbuf *m; 1384179645Smarcel bus_dma_segment_t segs[1]; 1385179645Smarcel int error, nsegs; 1386179645Smarcel 1387179645Smarcel m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1388179645Smarcel if (m == NULL) 1389179645Smarcel return (ENOBUFS); 1390179645Smarcel m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 1391179645Smarcel 1392179645Smarcel if (rxs->rxs_mbuf != NULL) { 1393179645Smarcel bus_dmamap_sync(sc->sc_rdma_tag, rxs->rxs_dmamap, 1394179645Smarcel BUS_DMASYNC_POSTREAD); 1395179645Smarcel bus_dmamap_unload(sc->sc_rdma_tag, rxs->rxs_dmamap); 1396179645Smarcel } 1397179645Smarcel 1398179645Smarcel error = bus_dmamap_load_mbuf_sg(sc->sc_rdma_tag, rxs->rxs_dmamap, m, 1399179645Smarcel segs, &nsegs, BUS_DMA_NOWAIT); 1400179645Smarcel if (error != 0) { 1401179645Smarcel device_printf(sc->sc_dev, 1402179645Smarcel "cannot load RS DMA map %d, error = %d\n", idx, error); 1403179645Smarcel m_freem(m); 1404179645Smarcel return (error); 1405179645Smarcel } 1406179645Smarcel /* If nsegs is wrong then the stack is corrupt. */ 1407179645Smarcel KASSERT(nsegs == 1, 1408179645Smarcel ("%s: too many DMA segments (%d)", __func__, nsegs)); 1409179645Smarcel rxs->rxs_mbuf = m; 1410179645Smarcel rxs->segment = segs[0]; 1411179645Smarcel 1412179645Smarcel bus_dmamap_sync(sc->sc_rdma_tag, rxs->rxs_dmamap, BUS_DMASYNC_PREREAD); 1413179645Smarcel 1414179645Smarcel return (0); 1415179645Smarcel} 1416179645Smarcel 1417179645Smarcelstatic int 1418179645Smarcelbm_add_rxbuf_dma(struct bm_softc *sc, int idx) 1419179645Smarcel{ 1420179645Smarcel struct bm_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1421179645Smarcel 1422179645Smarcel dbdma_insert_command(sc->sc_rxdma, idx, DBDMA_INPUT_LAST, 0, 1423179645Smarcel rxs->segment.ds_addr, rxs->segment.ds_len, DBDMA_ALWAYS, 1424179645Smarcel DBDMA_NEVER, DBDMA_NEVER, 0); 1425179645Smarcel 1426179645Smarcel return (0); 1427179645Smarcel} 1428179645Smarcel 1429179645Smarcelstatic void 1430179645Smarcelbm_enable_interrupts(struct bm_softc *sc) 1431179645Smarcel{ 1432179645Smarcel CSR_WRITE_2(sc, BM_INTR_DISABLE, 1433179645Smarcel (sc->sc_streaming) ? BM_INTR_NONE : BM_INTR_NORMAL); 1434179645Smarcel} 1435179645Smarcel 1436179645Smarcelstatic void 1437179645Smarcelbm_disable_interrupts(struct bm_softc *sc) 1438179645Smarcel{ 1439179645Smarcel CSR_WRITE_2(sc, BM_INTR_DISABLE, BM_INTR_NONE); 1440179645Smarcel} 1441