if_bm.c revision 180233
1/*- 2 * Copyright 2008 Nathan Whitehorn. All rights reserved. 3 * Copyright 2003 by Peter Grehan. All rights reserved. 4 * Copyright (C) 1998, 1999, 2000 Tsubai Masanari. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * From: 30 * NetBSD: if_bm.c,v 1.9.2.1 2000/11/01 15:02:49 tv Exp 31 */ 32 33/* 34 * BMAC/BMAC+ Macio cell 10/100 ethernet driver 35 * The low-cost, low-feature Apple variant of the Sun HME 36 */ 37 38#include <sys/cdefs.h> 39__FBSDID("$FreeBSD: head/sys/dev/bm/if_bm.c 180233 2008-07-03 21:51:30Z nwhitehorn $"); 40 41#include <sys/param.h> 42#include <sys/systm.h> 43#include <sys/sockio.h> 44#include <sys/endian.h> 45#include <sys/mbuf.h> 46#include <sys/module.h> 47#include <sys/malloc.h> 48#include <sys/kernel.h> 49#include <sys/socket.h> 50 51#include <net/bpf.h> 52#include <net/if.h> 53#include <net/if_arp.h> 54#include <net/ethernet.h> 55#include <net/if_dl.h> 56#include <net/if_media.h> 57#include <net/if_types.h> 58 59#include <machine/pio.h> 60#include <machine/bus.h> 61#include <machine/resource.h> 62#include <sys/bus.h> 63#include <sys/rman.h> 64 65#include <dev/mii/mii.h> 66#include <dev/mii/miivar.h> 67 68#include <dev/ofw/ofw_bus.h> 69#include <dev/ofw/openfirm.h> 70#include <machine/dbdma.h> 71 72MODULE_DEPEND(bm, ether, 1, 1, 1); 73MODULE_DEPEND(bm, miibus, 1, 1, 1); 74 75/* "controller miibus0" required. See GENERIC if you get errors here. */ 76#include "miibus_if.h" 77 78#include "if_bmreg.h" 79#include "if_bmvar.h" 80 81static int bm_probe (device_t); 82static int bm_attach (device_t); 83static int bm_detach (device_t); 84static void bm_shutdown (device_t); 85 86static void bm_start (struct ifnet *); 87static void bm_start_locked (struct ifnet *); 88static int bm_encap (struct bm_softc *sc, struct mbuf **m_head); 89static int bm_ioctl (struct ifnet *, u_long, caddr_t); 90static void bm_init (void *); 91static void bm_init_locked (struct bm_softc *sc); 92static void bm_chip_setup (struct bm_softc *sc); 93static void bm_stop (struct bm_softc *sc); 94static void bm_setladrf (struct bm_softc *sc); 95static void bm_dummypacket (struct bm_softc *sc); 96static void bm_txintr (void *xsc); 97static void bm_rxintr (void *xsc); 98 99static int bm_add_rxbuf (struct bm_softc *sc, int i); 100static int bm_add_rxbuf_dma (struct bm_softc *sc, int i); 101static void bm_enable_interrupts (struct bm_softc *sc); 102static void bm_disable_interrupts (struct bm_softc *sc); 103static void bm_tick (void *xsc); 104 105static int bm_ifmedia_upd (struct ifnet *); 106static void bm_ifmedia_sts (struct ifnet *, struct ifmediareq *); 107 108static void bm_miicsr_dwrite (struct bm_softc *, u_int16_t); 109static void bm_mii_writebit (struct bm_softc *, int); 110static int bm_mii_readbit (struct bm_softc *); 111static void bm_mii_sync (struct bm_softc *); 112static void bm_mii_send (struct bm_softc *, u_int32_t, int); 113static int bm_mii_readreg (struct bm_softc *, struct bm_mii_frame *); 114static int bm_mii_writereg (struct bm_softc *, struct bm_mii_frame *); 115static int bm_miibus_readreg (device_t, int, int); 116static int bm_miibus_writereg (device_t, int, int, int); 117static void bm_miibus_statchg (device_t); 118 119static device_method_t bm_methods[] = { 120 /* Device interface */ 121 DEVMETHOD(device_probe, bm_probe), 122 DEVMETHOD(device_attach, bm_attach), 123 DEVMETHOD(device_detach, bm_detach), 124 DEVMETHOD(device_shutdown, bm_shutdown), 125 126 /* bus interface, for miibus */ 127 DEVMETHOD(bus_print_child, bus_generic_print_child), 128 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 129 130 /* MII interface */ 131 DEVMETHOD(miibus_readreg, bm_miibus_readreg), 132 DEVMETHOD(miibus_writereg, bm_miibus_writereg), 133 DEVMETHOD(miibus_statchg, bm_miibus_statchg), 134 { 0, 0 } 135}; 136 137static driver_t bm_macio_driver = { 138 "bm", 139 bm_methods, 140 sizeof(struct bm_softc) 141}; 142 143static devclass_t bm_devclass; 144 145DRIVER_MODULE(bm, macio, bm_macio_driver, bm_devclass, 0, 0); 146DRIVER_MODULE(miibus, bm, miibus_driver, miibus_devclass, 0, 0); 147 148/* 149 * MII internal routines 150 */ 151 152/* 153 * Write to the MII csr, introducing a delay to allow valid 154 * MII clock pulses to be formed 155 */ 156static void 157bm_miicsr_dwrite(struct bm_softc *sc, u_int16_t val) 158{ 159 CSR_WRITE_2(sc, BM_MII_CSR, val); 160 /* 161 * Assume this is a clock toggle and generate a 1us delay 162 * to cover both MII's 160ns high/low minimum and 400ns 163 * cycle miniumum 164 */ 165 DELAY(1); 166} 167 168/* 169 * Write a bit to the MII bus. 170 */ 171static void 172bm_mii_writebit(struct bm_softc *sc, int bit) 173{ 174 u_int16_t regval; 175 176 regval = BM_MII_OENABLE; 177 if (bit) 178 regval |= BM_MII_DATAOUT; 179 180 bm_miicsr_dwrite(sc, regval); 181 bm_miicsr_dwrite(sc, regval | BM_MII_CLK); 182 bm_miicsr_dwrite(sc, regval); 183} 184 185/* 186 * Read a bit from the MII bus. 187 */ 188static int 189bm_mii_readbit(struct bm_softc *sc) 190{ 191 u_int16_t regval, bitin; 192 193 /* ~BM_MII_OENABLE */ 194 regval = 0; 195 196 bm_miicsr_dwrite(sc, regval); 197 bm_miicsr_dwrite(sc, regval | BM_MII_CLK); 198 bm_miicsr_dwrite(sc, regval); 199 bitin = CSR_READ_2(sc, BM_MII_CSR) & BM_MII_DATAIN; 200 201 return (bitin == BM_MII_DATAIN); 202} 203 204/* 205 * Sync the PHYs by setting data bit and strobing the clock 32 times. 206 */ 207static void 208bm_mii_sync(struct bm_softc *sc) 209{ 210 int i; 211 u_int16_t regval; 212 213 regval = BM_MII_OENABLE | BM_MII_DATAOUT; 214 215 bm_miicsr_dwrite(sc, regval); 216 for (i = 0; i < 32; i++) { 217 bm_miicsr_dwrite(sc, regval | BM_MII_CLK); 218 bm_miicsr_dwrite(sc, regval); 219 } 220} 221 222/* 223 * Clock a series of bits through the MII. 224 */ 225static void 226bm_mii_send(struct bm_softc *sc, u_int32_t bits, int cnt) 227{ 228 int i; 229 230 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 231 bm_mii_writebit(sc, bits & i); 232} 233 234/* 235 * Read a PHY register through the MII. 236 */ 237static int 238bm_mii_readreg(struct bm_softc *sc, struct bm_mii_frame *frame) 239{ 240 int i, ack, bit; 241 242 /* 243 * Set up frame for RX. 244 */ 245 frame->mii_stdelim = BM_MII_STARTDELIM; 246 frame->mii_opcode = BM_MII_READOP; 247 frame->mii_turnaround = 0; 248 frame->mii_data = 0; 249 250 /* 251 * Sync the PHYs 252 */ 253 bm_mii_sync(sc); 254 255 /* 256 * Send command/address info 257 */ 258 bm_mii_send(sc, frame->mii_stdelim, 2); 259 bm_mii_send(sc, frame->mii_opcode, 2); 260 bm_mii_send(sc, frame->mii_phyaddr, 5); 261 bm_mii_send(sc, frame->mii_regaddr, 5); 262 263 /* 264 * Check for ack. 265 */ 266 ack = bm_mii_readbit(sc); 267 268 /* 269 * Now try reading data bits. If the ack failed, we still 270 * need to clock through 16 cycles to keep the PHY(s) in sync. 271 */ 272 for (i = 0x8000; i; i >>= 1) { 273 bit = bm_mii_readbit(sc); 274 if (!ack && bit) 275 frame->mii_data |= i; 276 } 277 278 /* 279 * Skip through idle bit-times 280 */ 281 bm_mii_writebit(sc, 0); 282 bm_mii_writebit(sc, 0); 283 284 return ((ack) ? 1 : 0); 285} 286 287/* 288 * Write to a PHY register through the MII. 289 */ 290static int 291bm_mii_writereg(struct bm_softc *sc, struct bm_mii_frame *frame) 292{ 293 /* 294 * Set up frame for tx 295 */ 296 frame->mii_stdelim = BM_MII_STARTDELIM; 297 frame->mii_opcode = BM_MII_WRITEOP; 298 frame->mii_turnaround = BM_MII_TURNAROUND; 299 300 /* 301 * Sync the phy and start the bitbang write sequence 302 */ 303 bm_mii_sync(sc); 304 305 bm_mii_send(sc, frame->mii_stdelim, 2); 306 bm_mii_send(sc, frame->mii_opcode, 2); 307 bm_mii_send(sc, frame->mii_phyaddr, 5); 308 bm_mii_send(sc, frame->mii_regaddr, 5); 309 bm_mii_send(sc, frame->mii_turnaround, 2); 310 bm_mii_send(sc, frame->mii_data, 16); 311 312 /* 313 * Idle bit. 314 */ 315 bm_mii_writebit(sc, 0); 316 317 return (0); 318} 319 320/* 321 * MII bus i/f 322 */ 323static int 324bm_miibus_readreg(device_t dev, int phy, int reg) 325{ 326 struct bm_softc *sc; 327 struct bm_mii_frame frame; 328 329 sc = device_get_softc(dev); 330 bzero(&frame, sizeof(frame)); 331 332 frame.mii_phyaddr = phy; 333 frame.mii_regaddr = reg; 334 335 bm_mii_readreg(sc, &frame); 336 337 return (frame.mii_data); 338} 339 340static int 341bm_miibus_writereg(device_t dev, int phy, int reg, int data) 342{ 343 struct bm_softc *sc; 344 struct bm_mii_frame frame; 345 346 sc = device_get_softc(dev); 347 bzero(&frame, sizeof(frame)); 348 349 frame.mii_phyaddr = phy; 350 frame.mii_regaddr = reg; 351 frame.mii_data = data; 352 353 bm_mii_writereg(sc, &frame); 354 355 return (0); 356} 357 358static void 359bm_miibus_statchg(device_t dev) 360{ 361 struct bm_softc *sc = device_get_softc(dev); 362 uint16_t reg; 363 int new_duplex; 364 365 reg = CSR_READ_2(sc, BM_TX_CONFIG); 366 new_duplex = IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX; 367 368 if (new_duplex != sc->sc_duplex) { 369 /* Turn off TX MAC while we fiddle its settings */ 370 reg &= ~BM_ENABLE; 371 372 CSR_WRITE_2(sc, BM_TX_CONFIG, reg); 373 while (CSR_READ_2(sc, BM_TX_CONFIG) & BM_ENABLE) 374 DELAY(10); 375 } 376 377 if (new_duplex && !sc->sc_duplex) 378 reg |= BM_TX_IGNORECOLL | BM_TX_FULLDPX; 379 else if (!new_duplex && sc->sc_duplex) 380 reg &= ~(BM_TX_IGNORECOLL | BM_TX_FULLDPX); 381 382 if (new_duplex != sc->sc_duplex) { 383 /* Turn TX MAC back on */ 384 reg |= BM_ENABLE; 385 386 CSR_WRITE_2(sc, BM_TX_CONFIG, reg); 387 sc->sc_duplex = new_duplex; 388 } 389} 390 391/* 392 * ifmedia/mii callbacks 393 */ 394static int 395bm_ifmedia_upd(struct ifnet *ifp) 396{ 397 struct bm_softc *sc = ifp->if_softc; 398 int error; 399 400 BM_LOCK(sc); 401 error = mii_mediachg(sc->sc_mii); 402 BM_UNLOCK(sc); 403 return (error); 404} 405 406static void 407bm_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifm) 408{ 409 struct bm_softc *sc = ifp->if_softc; 410 411 BM_LOCK(sc); 412 mii_pollstat(sc->sc_mii); 413 ifm->ifm_active = sc->sc_mii->mii_media_active; 414 ifm->ifm_status = sc->sc_mii->mii_media_status; 415 BM_UNLOCK(sc); 416} 417 418/* 419 * Macio probe/attach 420 */ 421static int 422bm_probe(device_t dev) 423{ 424 const char *dname = ofw_bus_get_name(dev); 425 const char *dcompat = ofw_bus_get_compat(dev); 426 427 /* 428 * BMAC+ cells have a name of "ethernet" and 429 * a compatible property of "bmac+" 430 */ 431 if (strcmp(dname, "bmac") == 0) { 432 device_set_desc(dev, "Apple BMAC Ethernet Adaptor"); 433 } else if (strcmp(dcompat, "bmac+") == 0) { 434 device_set_desc(dev, "Apple BMAC+ Ethernet Adaptor"); 435 } else 436 return (ENXIO); 437 438 return (0); 439} 440 441static int 442bm_attach(device_t dev) 443{ 444 phandle_t node; 445 u_char *eaddr; 446 struct ifnet *ifp; 447 int error, cellid, i; 448 struct bm_txsoft *txs; 449 struct bm_softc *sc = device_get_softc(dev); 450 451 ifp = sc->sc_ifp = if_alloc(IFT_ETHER); 452 ifp->if_softc = sc; 453 sc->sc_dev = dev; 454 sc->sc_duplex = ~IFM_FDX; 455 456 error = 0; 457 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 458 MTX_DEF); 459 callout_init_mtx(&sc->sc_tick_ch, &sc->sc_mtx, 0); 460 461 /* Check for an improved version of Paddington */ 462 sc->sc_streaming = 0; 463 cellid = -1; 464 node = ofw_bus_get_node(dev); 465 466 OF_getprop(node, "cell-id", &cellid, sizeof(cellid)); 467 if (cellid >= 0xc4) 468 sc->sc_streaming = 1; 469 470 sc->sc_memrid = 0; 471 sc->sc_memr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 472 &sc->sc_memrid, RF_ACTIVE); 473 if (sc->sc_memr == NULL) { 474 device_printf(dev, "Could not alloc chip registers!\n"); 475 return (ENXIO); 476 } 477 478 sc->sc_txdmarid = BM_TXDMA_REGISTERS; 479 sc->sc_rxdmarid = BM_RXDMA_REGISTERS; 480 481 sc->sc_txdmar = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 482 &sc->sc_txdmarid, RF_ACTIVE); 483 sc->sc_rxdmar = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 484 &sc->sc_rxdmarid, RF_ACTIVE); 485 486 if (sc->sc_txdmar == NULL || sc->sc_rxdmar == NULL) { 487 device_printf(dev, "Could not map DBDMA registers!\n"); 488 return (ENXIO); 489 } 490 491 error = dbdma_allocate_channel(sc->sc_txdmar, bus_get_dma_tag(dev), 492 BM_MAX_DMA_COMMANDS, &sc->sc_txdma); 493 error += dbdma_allocate_channel(sc->sc_rxdmar, bus_get_dma_tag(dev), 494 BM_MAX_DMA_COMMANDS, &sc->sc_rxdma); 495 496 if (error) { 497 device_printf(dev,"Could not allocate DBDMA channel!\n"); 498 return (ENXIO); 499 } 500 501 /* alloc DMA tags and buffers */ 502 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 503 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 504 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, 505 NULL, &sc->sc_pdma_tag); 506 507 if (error) { 508 device_printf(dev,"Could not allocate DMA tag!\n"); 509 return (ENXIO); 510 } 511 512 error = bus_dma_tag_create(sc->sc_pdma_tag, 1, 0, BUS_SPACE_MAXADDR, 513 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, MCLBYTES, 514 BUS_DMA_ALLOCNOW, NULL, NULL, &sc->sc_rdma_tag); 515 516 if (error) { 517 device_printf(dev,"Could not allocate RX DMA channel!\n"); 518 return (ENXIO); 519 } 520 521 error = bus_dma_tag_create(sc->sc_pdma_tag, 1, 0, BUS_SPACE_MAXADDR, 522 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES * BM_NTXSEGS, BM_NTXSEGS, 523 MCLBYTES, BUS_DMA_ALLOCNOW, NULL, NULL, &sc->sc_tdma_tag); 524 525 if (error) { 526 device_printf(dev,"Could not allocate TX DMA tag!\n"); 527 return (ENXIO); 528 } 529 530 /* init transmit descriptors */ 531 STAILQ_INIT(&sc->sc_txfreeq); 532 STAILQ_INIT(&sc->sc_txdirtyq); 533 534 /* create TX DMA maps */ 535 error = ENOMEM; 536 for (i = 0; i < BM_MAX_TX_PACKETS; i++) { 537 txs = &sc->sc_txsoft[i]; 538 txs->txs_mbuf = NULL; 539 error = bus_dmamap_create(sc->sc_tdma_tag, 0, &txs->txs_dmamap); 540 if (error) { 541 device_printf(sc->sc_dev, 542 "unable to create TX DMA map %d, error = %d\n", 543 i, error); 544 } 545 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 546 } 547 548 /* Create the receive buffer DMA maps. */ 549 for (i = 0; i < BM_MAX_RX_PACKETS; i++) { 550 error = bus_dmamap_create(sc->sc_rdma_tag, 0, 551 &sc->sc_rxsoft[i].rxs_dmamap); 552 if (error) { 553 device_printf(sc->sc_dev, 554 "unable to create RX DMA map %d, error = %d\n", 555 i, error); 556 } 557 sc->sc_rxsoft[i].rxs_mbuf = NULL; 558 } 559 560 /* alloc interrupt */ 561 562 sc->sc_txdmairqid = BM_TXDMA_INTERRUPT; 563 sc->sc_txdmairq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 564 &sc->sc_txdmairqid, RF_ACTIVE); 565 566 if (error) { 567 device_printf(dev,"Could not allocate TX interrupt!\n"); 568 return (ENXIO); 569 } 570 571 bus_setup_intr(dev,sc->sc_txdmairq, 572 INTR_TYPE_MISC | INTR_MPSAFE | INTR_ENTROPY, NULL, bm_txintr, sc, 573 &sc->sc_txihtx); 574 575 sc->sc_rxdmairqid = BM_RXDMA_INTERRUPT; 576 sc->sc_rxdmairq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 577 &sc->sc_rxdmairqid, RF_ACTIVE); 578 579 if (error) { 580 device_printf(dev,"Could not allocate RX interrupt!\n"); 581 return (ENXIO); 582 } 583 584 bus_setup_intr(dev,sc->sc_rxdmairq, 585 INTR_TYPE_MISC | INTR_MPSAFE | INTR_ENTROPY, NULL, bm_rxintr, sc, 586 &sc->sc_rxih); 587 588 /* 589 * Get the ethernet address from OpenFirmware 590 */ 591 eaddr = sc->sc_enaddr; 592 OF_getprop(node, "local-mac-address", eaddr, ETHER_ADDR_LEN); 593 594 /* reset the adapter */ 595 bm_chip_setup(sc); 596 597 /* setup MII */ 598 error = mii_phy_probe(dev, &sc->sc_miibus, bm_ifmedia_upd, 599 bm_ifmedia_sts); 600 if (error != 0) 601 device_printf(dev,"PHY probe failed: %d\n", error); 602 603 sc->sc_mii = device_get_softc(sc->sc_miibus); 604 605 if_initname(ifp, device_get_name(sc->sc_dev), 606 device_get_unit(sc->sc_dev)); 607 ifp->if_mtu = ETHERMTU; 608 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 609 ifp->if_start = bm_start; 610 ifp->if_ioctl = bm_ioctl; 611 ifp->if_init = bm_init; 612 IFQ_SET_MAXLEN(&ifp->if_snd, BM_MAX_TX_PACKETS); 613 ifp->if_snd.ifq_drv_maxlen = BM_MAX_TX_PACKETS; 614 IFQ_SET_READY(&ifp->if_snd); 615 616 /* Attach the interface. */ 617 ether_ifattach(ifp, sc->sc_enaddr); 618 ifp->if_hwassist = 0; 619 620 return (0); 621} 622 623static int 624bm_detach(device_t dev) 625{ 626 struct bm_softc *sc = device_get_softc(dev); 627 628 BM_LOCK(sc); 629 bm_stop(sc); 630 BM_UNLOCK(sc); 631 632 callout_drain(&sc->sc_tick_ch); 633 ether_ifdetach(sc->sc_ifp); 634 bus_teardown_intr(dev, sc->sc_txdmairq, sc->sc_txihtx); 635 bus_teardown_intr(dev, sc->sc_rxdmairq, sc->sc_rxih); 636 637 dbdma_free_channel(sc->sc_txdma); 638 dbdma_free_channel(sc->sc_rxdma); 639 640 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_memrid, sc->sc_memr); 641 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_txdmarid, 642 sc->sc_txdmar); 643 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_rxdmarid, 644 sc->sc_rxdmar); 645 646 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_txdmairqid, 647 sc->sc_txdmairq); 648 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_rxdmairqid, 649 sc->sc_rxdmairq); 650 651 mtx_destroy(&sc->sc_mtx); 652 if_free(sc->sc_ifp); 653 654 return (0); 655} 656 657static void 658bm_shutdown(device_t dev) 659{ 660 struct bm_softc *sc; 661 662 sc = device_get_softc(dev); 663 664 BM_LOCK(sc); 665 bm_stop(sc); 666 BM_UNLOCK(sc); 667} 668 669static void 670bm_dummypacket(struct bm_softc *sc) 671{ 672 struct mbuf *m; 673 struct ifnet *ifp; 674 675 ifp = sc->sc_ifp; 676 677 MGETHDR(m, M_DONTWAIT, MT_DATA); 678 679 if (m == NULL) 680 return; 681 682 bcopy(sc->sc_enaddr, 683 mtod(m, struct ether_header *)->ether_dhost, ETHER_ADDR_LEN); 684 bcopy(sc->sc_enaddr, 685 mtod(m, struct ether_header *)->ether_shost, ETHER_ADDR_LEN); 686 mtod(m, struct ether_header *)->ether_type = htons(3); 687 mtod(m, unsigned char *)[14] = 0; 688 mtod(m, unsigned char *)[15] = 0; 689 mtod(m, unsigned char *)[16] = 0xE3; 690 m->m_len = m->m_pkthdr.len = sizeof(struct ether_header) + 3; 691 IF_ENQUEUE(&ifp->if_snd, m); 692 bm_start(ifp); 693} 694 695static void 696bm_rxintr(void *xsc) 697{ 698 struct bm_softc *sc = xsc; 699 struct ifnet *ifp = sc->sc_ifp; 700 struct mbuf *m; 701 int i, prev_stop, new_stop; 702 uint16_t status; 703 704 BM_LOCK(sc); 705 706 status = dbdma_get_chan_status(sc->sc_rxdma); 707 if (status & DBDMA_STATUS_DEAD) { 708 dbdma_reset(sc->sc_rxdma); 709 BM_UNLOCK(sc); 710 return; 711 } 712 if (!(status & DBDMA_STATUS_RUN)) { 713 device_printf(sc->sc_dev,"Bad RX Interrupt!\n"); 714 BM_UNLOCK(sc); 715 return; 716 } 717 718 prev_stop = sc->next_rxdma_slot - 1; 719 if (prev_stop < 0) 720 prev_stop = sc->rxdma_loop_slot - 1; 721 722 if (prev_stop < 0) { 723 BM_UNLOCK(sc); 724 return; 725 } 726 727 new_stop = -1; 728 dbdma_sync_commands(sc->sc_rxdma, BUS_DMASYNC_POSTREAD); 729 730 for (i = sc->next_rxdma_slot; i < BM_MAX_RX_PACKETS; i++) { 731 if (i == sc->rxdma_loop_slot) 732 i = 0; 733 734 if (i == prev_stop) 735 break; 736 737 status = dbdma_get_cmd_status(sc->sc_rxdma, i); 738 739 if (status == 0) 740 break; 741 742 m = sc->sc_rxsoft[i].rxs_mbuf; 743 744 if (bm_add_rxbuf(sc, i)) { 745 ifp->if_ierrors++; 746 m = NULL; 747 continue; 748 } 749 750 if (m == NULL) 751 continue; 752 753 ifp->if_ipackets++; 754 m->m_pkthdr.rcvif = ifp; 755 m->m_len -= (dbdma_get_residuals(sc->sc_rxdma, i) + 2); 756 m->m_pkthdr.len = m->m_len; 757 758 /* Send up the stack */ 759 BM_UNLOCK(sc); 760 (*ifp->if_input)(ifp, m); 761 BM_LOCK(sc); 762 763 /* Clear all fields on this command */ 764 bm_add_rxbuf_dma(sc, i); 765 766 new_stop = i; 767 } 768 769 /* Change the last packet we processed to the ring buffer terminator, 770 * and restore a receive buffer to the old terminator */ 771 if (new_stop >= 0) { 772 dbdma_insert_stop(sc->sc_rxdma, new_stop); 773 bm_add_rxbuf_dma(sc, prev_stop); 774 if (i < sc->rxdma_loop_slot) 775 sc->next_rxdma_slot = i; 776 else 777 sc->next_rxdma_slot = 0; 778 } 779 dbdma_sync_commands(sc->sc_rxdma, BUS_DMASYNC_PREWRITE); 780 781 dbdma_wake(sc->sc_rxdma); 782 783 BM_UNLOCK(sc); 784} 785 786static void 787bm_txintr(void *xsc) 788{ 789 struct bm_softc *sc = xsc; 790 struct ifnet *ifp = sc->sc_ifp; 791 struct bm_txsoft *txs; 792 int progress = 0; 793 794 BM_LOCK(sc); 795 796 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 797 if (!dbdma_get_cmd_status(sc->sc_txdma, txs->txs_lastdesc)) 798 break; 799 800 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 801 bus_dmamap_unload(sc->sc_tdma_tag, txs->txs_dmamap); 802 803 if (txs->txs_mbuf != NULL) { 804 m_freem(txs->txs_mbuf); 805 txs->txs_mbuf = NULL; 806 } 807 808 /* Set the first used TXDMA slot to the location of the 809 * STOP/NOP command associated with this packet. */ 810 811 sc->first_used_txdma_slot = txs->txs_stopdesc; 812 813 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 814 815 ifp->if_opackets++; 816 progress = 1; 817 } 818 819 if (progress) { 820 /* 821 * We freed some descriptors, so reset IFF_DRV_OACTIVE 822 * and restart. 823 */ 824 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 825 sc->sc_wdog_timer = STAILQ_EMPTY(&sc->sc_txdirtyq) ? 0 : 5; 826 827 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) && 828 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 829 bm_start_locked(ifp); 830 } 831 832 BM_UNLOCK(sc); 833} 834 835static void 836bm_start(struct ifnet *ifp) 837{ 838 struct bm_softc *sc = ifp->if_softc; 839 840 BM_LOCK(sc); 841 bm_start_locked(ifp); 842 BM_UNLOCK(sc); 843} 844 845static void 846bm_start_locked(struct ifnet *ifp) 847{ 848 struct bm_softc *sc = ifp->if_softc; 849 struct mbuf *mb_head; 850 int prev_stop; 851 int txqueued = 0; 852 853 /* 854 * We lay out our DBDMA program in the following manner: 855 * OUTPUT_MORE 856 * ... 857 * OUTPUT_LAST (+ Interrupt) 858 * STOP 859 * 860 * To extend the channel, we append a new program, 861 * then replace STOP with NOP and wake the channel. 862 * If we stalled on the STOP already, the program proceeds, 863 * if not it will sail through the NOP. 864 */ 865 866 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 867 IFQ_DRV_DEQUEUE(&ifp->if_snd, mb_head); 868 869 if (mb_head == NULL) 870 break; 871 872 prev_stop = sc->next_txdma_slot - 1; 873 874 if (bm_encap(sc, &mb_head)) { 875 /* Put the packet back and stop */ 876 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 877 IFQ_DRV_PREPEND(&ifp->if_snd, mb_head); 878 break; 879 } 880 881 dbdma_insert_nop(sc->sc_txdma, prev_stop); 882 883 txqueued = 1; 884 885 BPF_MTAP(ifp, mb_head); 886 } 887 888 dbdma_sync_commands(sc->sc_txdma, BUS_DMASYNC_PREWRITE); 889 890 if (txqueued) { 891 dbdma_wake(sc->sc_txdma); 892 sc->sc_wdog_timer = 5; 893 } 894} 895 896static int 897bm_encap(struct bm_softc *sc, struct mbuf **m_head) 898{ 899 bus_dma_segment_t segs[BM_NTXSEGS]; 900 struct bm_txsoft *txs; 901 struct mbuf *m; 902 int nsegs = BM_NTXSEGS; 903 int error = 0; 904 uint8_t branch_type; 905 int i; 906 907 /* Limit the command size to the number of free DBDMA slots */ 908 909 if (sc->next_txdma_slot >= sc->first_used_txdma_slot) 910 nsegs = BM_MAX_DMA_COMMANDS - 2 - sc->next_txdma_slot + 911 sc->first_used_txdma_slot; /* -2 for branch and indexing */ 912 else 913 nsegs = sc->first_used_txdma_slot - sc->next_txdma_slot; 914 915 /* Remove one slot for the STOP/NOP terminator */ 916 nsegs--; 917 918 if (nsegs > BM_NTXSEGS) 919 nsegs = BM_NTXSEGS; 920 921 /* Get a work queue entry. */ 922 if ((txs = STAILQ_FIRST(&sc->sc_txfreeq)) == NULL) { 923 /* Ran out of descriptors. */ 924 return (ENOBUFS); 925 } 926 927 error = bus_dmamap_load_mbuf_sg(sc->sc_tdma_tag, txs->txs_dmamap, 928 *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 929 930 if (error == EFBIG) { 931 m = m_collapse(*m_head, M_DONTWAIT, nsegs); 932 if (m == NULL) { 933 m_freem(*m_head); 934 *m_head = NULL; 935 return (ENOBUFS); 936 } 937 *m_head = m; 938 939 error = bus_dmamap_load_mbuf_sg(sc->sc_tdma_tag, 940 txs->txs_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 941 if (error != 0) { 942 m_freem(*m_head); 943 *m_head = NULL; 944 return (error); 945 } 946 } else if (error != 0) 947 return (error); 948 949 if (nsegs == 0) { 950 m_freem(*m_head); 951 *m_head = NULL; 952 return (EIO); 953 } 954 955 txs->txs_ndescs = nsegs; 956 txs->txs_firstdesc = sc->next_txdma_slot; 957 958 for (i = 0; i < nsegs; i++) { 959 /* Loop back to the beginning if this is our last slot */ 960 if (sc->next_txdma_slot == (BM_MAX_DMA_COMMANDS - 1)) 961 branch_type = DBDMA_ALWAYS; 962 else 963 branch_type = DBDMA_NEVER; 964 965 if (i+1 == nsegs) 966 txs->txs_lastdesc = sc->next_txdma_slot; 967 968 dbdma_insert_command(sc->sc_txdma, sc->next_txdma_slot++, 969 (i + 1 < nsegs) ? DBDMA_OUTPUT_MORE : DBDMA_OUTPUT_LAST, 970 0, segs[i].ds_addr, segs[i].ds_len, 971 (i + 1 < nsegs) ? DBDMA_NEVER : DBDMA_ALWAYS, 972 branch_type, DBDMA_NEVER, 0); 973 974 if (branch_type == DBDMA_ALWAYS) 975 sc->next_txdma_slot = 0; 976 } 977 978 /* We have a corner case where the STOP command is the last slot, 979 * but you can't branch in STOP commands. So add a NOP branch here 980 * and the STOP in slot 0. */ 981 982 if (sc->next_txdma_slot == (BM_MAX_DMA_COMMANDS - 1)) { 983 dbdma_insert_branch(sc->sc_txdma, sc->next_txdma_slot, 0); 984 sc->next_txdma_slot = 0; 985 } 986 987 txs->txs_stopdesc = sc->next_txdma_slot; 988 dbdma_insert_stop(sc->sc_txdma, sc->next_txdma_slot++); 989 990 STAILQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 991 STAILQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 992 txs->txs_mbuf = *m_head; 993 994 return (0); 995} 996 997static int 998bm_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 999{ 1000 struct bm_softc *sc = ifp->if_softc; 1001 struct ifreq *ifr = (struct ifreq *)data; 1002 int error; 1003 1004 error = 0; 1005 1006 switch(cmd) { 1007 case SIOCSIFFLAGS: 1008 BM_LOCK(sc); 1009 if ((ifp->if_flags & IFF_UP) != 0) { 1010 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 1011 ((ifp->if_flags ^ sc->sc_ifpflags) & 1012 (IFF_ALLMULTI | IFF_PROMISC)) != 0) 1013 bm_setladrf(sc); 1014 else 1015 bm_init_locked(sc); 1016 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1017 bm_stop(sc); 1018 sc->sc_ifpflags = ifp->if_flags; 1019 BM_UNLOCK(sc); 1020 break; 1021 case SIOCADDMULTI: 1022 case SIOCDELMULTI: 1023 BM_LOCK(sc); 1024 bm_setladrf(sc); 1025 BM_UNLOCK(sc); 1026 case SIOCGIFMEDIA: 1027 case SIOCSIFMEDIA: 1028 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii->mii_media, cmd); 1029 break; 1030 default: 1031 error = ether_ioctl(ifp, cmd, data); 1032 break; 1033 } 1034 1035 return (error); 1036} 1037 1038static void 1039bm_setladrf(struct bm_softc *sc) 1040{ 1041 struct ifnet *ifp = sc->sc_ifp; 1042 struct ifmultiaddr *inm; 1043 uint16_t hash[4]; 1044 uint16_t reg; 1045 uint32_t crc; 1046 1047 reg = BM_CRC_ENABLE | BM_REJECT_OWN_PKTS; 1048 1049 /* Turn off RX MAC while we fiddle its settings */ 1050 CSR_WRITE_2(sc, BM_RX_CONFIG, reg); 1051 while (CSR_READ_2(sc, BM_RX_CONFIG) & BM_ENABLE) 1052 DELAY(10); 1053 1054 if ((ifp->if_flags & IFF_PROMISC) != 0) { 1055 reg |= BM_PROMISC; 1056 1057 CSR_WRITE_2(sc, BM_RX_CONFIG, reg); 1058 1059 DELAY(15); 1060 1061 reg = CSR_READ_2(sc, BM_RX_CONFIG); 1062 reg |= BM_ENABLE; 1063 CSR_WRITE_2(sc, BM_RX_CONFIG, reg); 1064 return; 1065 } 1066 1067 if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 1068 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1069 } else { 1070 /* Clear the hash table. */ 1071 memset(hash, 0, sizeof(hash)); 1072 1073 IF_ADDR_LOCK(ifp); 1074 TAILQ_FOREACH(inm, &ifp->if_multiaddrs, ifma_link) { 1075 if (inm->ifma_addr->sa_family != AF_LINK) 1076 continue; 1077 crc = ether_crc32_le(LLADDR((struct sockaddr_dl *) 1078 inm->ifma_addr), ETHER_ADDR_LEN); 1079 1080 /* We just want the 6 most significant bits */ 1081 crc >>= 26; 1082 1083 /* Set the corresponding bit in the filter. */ 1084 hash[crc >> 4] |= 1 << (crc & 0xf); 1085 } 1086 IF_ADDR_UNLOCK(ifp); 1087 } 1088 1089 /* Write out new hash table */ 1090 CSR_WRITE_2(sc, BM_HASHTAB0, hash[0]); 1091 CSR_WRITE_2(sc, BM_HASHTAB1, hash[1]); 1092 CSR_WRITE_2(sc, BM_HASHTAB2, hash[2]); 1093 CSR_WRITE_2(sc, BM_HASHTAB3, hash[3]); 1094 1095 /* And turn the RX MAC back on, this time with the hash bit set */ 1096 reg |= BM_HASH_FILTER_ENABLE; 1097 CSR_WRITE_2(sc, BM_RX_CONFIG, reg); 1098 1099 while (!(CSR_READ_2(sc, BM_RX_CONFIG) & BM_HASH_FILTER_ENABLE)) 1100 DELAY(10); 1101 1102 reg = CSR_READ_2(sc, BM_RX_CONFIG); 1103 reg |= BM_ENABLE; 1104 CSR_WRITE_2(sc, BM_RX_CONFIG, reg); 1105} 1106 1107static void 1108bm_init(void *xsc) 1109{ 1110 struct bm_softc *sc = xsc; 1111 1112 BM_LOCK(sc); 1113 bm_init_locked(sc); 1114 BM_UNLOCK(sc); 1115} 1116 1117static void 1118bm_chip_setup(struct bm_softc *sc) 1119{ 1120 uint16_t reg; 1121 uint16_t *eaddr_sect; 1122 char hrow_path[128]; 1123 ihandle_t hrow_ih; 1124 1125 eaddr_sect = (uint16_t *)(sc->sc_enaddr); 1126 1127 /* Enable BMAC cell */ 1128 OF_package_to_path(OF_parent(ofw_bus_get_node(sc->sc_dev)), 1129 hrow_path, sizeof(hrow_path)); 1130 hrow_ih = OF_open(hrow_path); 1131 if (hrow_ih == -1) { 1132 device_printf(sc->sc_dev, 1133 "Enabling BMAC cell failed! Hoping it's already active.\n"); 1134 } else { 1135 OF_call_method("enable-enet", hrow_ih, 0, 0); 1136 OF_close(hrow_ih); 1137 } 1138 1139 /* Reset chip */ 1140 CSR_WRITE_2(sc, BM_RX_RESET, 0x0000); 1141 CSR_WRITE_2(sc, BM_TX_RESET, 0x0001); 1142 do { 1143 reg = CSR_READ_2(sc, BM_TX_RESET); 1144 } while (reg & 0x0001); 1145 1146 /* Some random junk. OS X uses the system time. We use 1147 * the low 16 bits of the MAC address. */ 1148 CSR_WRITE_2(sc, BM_TX_RANDSEED, eaddr_sect[2]); 1149 1150 /* Enable transmit */ 1151 reg = CSR_READ_2(sc, BM_TX_IFC); 1152 reg |= BM_ENABLE; 1153 CSR_WRITE_2(sc, BM_TX_IFC, reg); 1154 1155 CSR_READ_2(sc, BM_TX_PEAKCNT); 1156} 1157 1158static void 1159bm_stop(struct bm_softc *sc) 1160{ 1161 struct bm_txsoft *txs; 1162 uint16_t reg; 1163 1164 /* Disable TX and RX MACs */ 1165 reg = CSR_READ_2(sc, BM_TX_CONFIG); 1166 reg &= ~BM_ENABLE; 1167 CSR_WRITE_2(sc, BM_TX_CONFIG, reg); 1168 1169 reg = CSR_READ_2(sc, BM_RX_CONFIG); 1170 reg &= ~BM_ENABLE; 1171 CSR_WRITE_2(sc, BM_RX_CONFIG, reg); 1172 1173 DELAY(100); 1174 1175 /* Stop DMA engine */ 1176 dbdma_stop(sc->sc_rxdma); 1177 dbdma_stop(sc->sc_txdma); 1178 sc->next_rxdma_slot = 0; 1179 sc->rxdma_loop_slot = 0; 1180 1181 /* Disable interrupts */ 1182 bm_disable_interrupts(sc); 1183 1184 /* Don't worry about pending transmits anymore */ 1185 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1186 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1187 if (txs->txs_ndescs != 0) { 1188 bus_dmamap_sync(sc->sc_tdma_tag, txs->txs_dmamap, 1189 BUS_DMASYNC_POSTWRITE); 1190 bus_dmamap_unload(sc->sc_tdma_tag, txs->txs_dmamap); 1191 if (txs->txs_mbuf != NULL) { 1192 m_freem(txs->txs_mbuf); 1193 txs->txs_mbuf = NULL; 1194 } 1195 } 1196 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1197 } 1198 1199 /* And we're down */ 1200 sc->sc_ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1201 sc->sc_wdog_timer = 0; 1202 callout_stop(&sc->sc_tick_ch); 1203} 1204 1205static void 1206bm_init_locked(struct bm_softc *sc) 1207{ 1208 uint16_t reg; 1209 uint16_t *eaddr_sect; 1210 struct bm_rxsoft *rxs; 1211 int i; 1212 1213 eaddr_sect = (uint16_t *)(sc->sc_enaddr); 1214 1215 /* Zero RX slot info and stop DMA */ 1216 dbdma_stop(sc->sc_rxdma); 1217 dbdma_stop(sc->sc_txdma); 1218 sc->next_rxdma_slot = 0; 1219 sc->rxdma_loop_slot = 0; 1220 1221 /* Initialize TX/RX DBDMA programs */ 1222 dbdma_insert_stop(sc->sc_rxdma, 0); 1223 dbdma_insert_stop(sc->sc_txdma, 0); 1224 dbdma_set_current_cmd(sc->sc_rxdma, 0); 1225 dbdma_set_current_cmd(sc->sc_txdma, 0); 1226 1227 sc->next_rxdma_slot = 0; 1228 sc->next_txdma_slot = 1; 1229 sc->first_used_txdma_slot = 0; 1230 1231 for (i = 0; i < BM_MAX_RX_PACKETS; i++) { 1232 rxs = &sc->sc_rxsoft[i]; 1233 rxs->dbdma_slot = i; 1234 1235 if (rxs->rxs_mbuf == NULL) { 1236 bm_add_rxbuf(sc, i); 1237 1238 if (rxs->rxs_mbuf == NULL) { 1239 /* If we can't add anymore, mark the problem */ 1240 rxs->dbdma_slot = -1; 1241 break; 1242 } 1243 } 1244 1245 if (i > 0) 1246 bm_add_rxbuf_dma(sc, i); 1247 } 1248 1249 /* 1250 * Now terminate the RX ring buffer, and follow with the loop to 1251 * the beginning. 1252 */ 1253 dbdma_insert_stop(sc->sc_rxdma, i - 1); 1254 dbdma_insert_branch(sc->sc_rxdma, i, 0); 1255 sc->rxdma_loop_slot = i; 1256 1257 /* Now add in the first element of the RX DMA chain */ 1258 bm_add_rxbuf_dma(sc, 0); 1259 1260 dbdma_sync_commands(sc->sc_rxdma, BUS_DMASYNC_PREWRITE); 1261 dbdma_sync_commands(sc->sc_txdma, BUS_DMASYNC_PREWRITE); 1262 1263 /* Zero collision counters */ 1264 CSR_WRITE_2(sc, BM_TX_NCCNT, 0); 1265 CSR_WRITE_2(sc, BM_TX_FCCNT, 0); 1266 CSR_WRITE_2(sc, BM_TX_EXCNT, 0); 1267 CSR_WRITE_2(sc, BM_TX_LTCNT, 0); 1268 1269 /* Zero receive counters */ 1270 CSR_WRITE_2(sc, BM_RX_FRCNT, 0); 1271 CSR_WRITE_2(sc, BM_RX_LECNT, 0); 1272 CSR_WRITE_2(sc, BM_RX_AECNT, 0); 1273 CSR_WRITE_2(sc, BM_RX_FECNT, 0); 1274 CSR_WRITE_2(sc, BM_RXCV, 0); 1275 1276 /* Prime transmit */ 1277 CSR_WRITE_2(sc, BM_TX_THRESH, 0xff); 1278 1279 CSR_WRITE_2(sc, BM_TXFIFO_CSR, 0); 1280 CSR_WRITE_2(sc, BM_TXFIFO_CSR, 0x0001); 1281 1282 /* Prime receive */ 1283 CSR_WRITE_2(sc, BM_RXFIFO_CSR, 0); 1284 CSR_WRITE_2(sc, BM_RXFIFO_CSR, 0x0001); 1285 1286 /* Clear status reg */ 1287 CSR_READ_2(sc, BM_STATUS); 1288 1289 /* Zero hash filters */ 1290 CSR_WRITE_2(sc, BM_HASHTAB0, 0); 1291 CSR_WRITE_2(sc, BM_HASHTAB1, 0); 1292 CSR_WRITE_2(sc, BM_HASHTAB2, 0); 1293 CSR_WRITE_2(sc, BM_HASHTAB3, 0); 1294 1295 /* Write MAC address to chip */ 1296 CSR_WRITE_2(sc, BM_MACADDR0, eaddr_sect[0]); 1297 CSR_WRITE_2(sc, BM_MACADDR1, eaddr_sect[1]); 1298 CSR_WRITE_2(sc, BM_MACADDR2, eaddr_sect[2]); 1299 1300 /* Final receive engine setup */ 1301 reg = BM_CRC_ENABLE | BM_REJECT_OWN_PKTS | BM_HASH_FILTER_ENABLE; 1302 CSR_WRITE_2(sc, BM_RX_CONFIG, reg); 1303 1304 /* Now turn it all on! */ 1305 dbdma_reset(sc->sc_rxdma); 1306 dbdma_reset(sc->sc_txdma); 1307 1308 /* Enable RX and TX MACs. Setting the address filter has 1309 * the side effect of enabling the RX MAC. */ 1310 bm_setladrf(sc); 1311 1312 reg = CSR_READ_2(sc, BM_TX_CONFIG); 1313 reg |= BM_ENABLE; 1314 CSR_WRITE_2(sc, BM_TX_CONFIG, reg); 1315 1316 /* 1317 * Enable interrupts, unwedge the controller with a dummy packet, 1318 * and nudge the DMA queue. 1319 */ 1320 bm_enable_interrupts(sc); 1321 bm_dummypacket(sc); 1322 dbdma_wake(sc->sc_rxdma); /* Nudge RXDMA */ 1323 1324 sc->sc_ifp->if_drv_flags |= IFF_DRV_RUNNING; 1325 sc->sc_ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1326 sc->sc_ifpflags = sc->sc_ifp->if_flags; 1327 1328 /* Resync PHY and MAC states */ 1329 sc->sc_mii = device_get_softc(sc->sc_miibus); 1330 sc->sc_duplex = ~IFM_FDX; 1331 mii_mediachg(sc->sc_mii); 1332 1333 /* Start the one second timer. */ 1334 sc->sc_wdog_timer = 0; 1335 callout_reset(&sc->sc_tick_ch, hz, bm_tick, sc); 1336} 1337 1338static void 1339bm_tick(void *arg) 1340{ 1341 struct bm_softc *sc = arg; 1342 1343 /* Read error counters */ 1344 sc->sc_ifp->if_collisions += CSR_READ_2(sc, BM_TX_NCCNT) + 1345 CSR_READ_2(sc, BM_TX_FCCNT) + CSR_READ_2(sc, BM_TX_EXCNT) + 1346 CSR_READ_2(sc, BM_TX_LTCNT); 1347 1348 sc->sc_ifp->if_ierrors += CSR_READ_2(sc, BM_RX_LECNT) + 1349 CSR_READ_2(sc, BM_RX_AECNT) + CSR_READ_2(sc, BM_RX_FECNT); 1350 1351 /* Zero collision counters */ 1352 CSR_WRITE_2(sc, BM_TX_NCCNT, 0); 1353 CSR_WRITE_2(sc, BM_TX_FCCNT, 0); 1354 CSR_WRITE_2(sc, BM_TX_EXCNT, 0); 1355 CSR_WRITE_2(sc, BM_TX_LTCNT, 0); 1356 1357 /* Zero receive counters */ 1358 CSR_WRITE_2(sc, BM_RX_FRCNT, 0); 1359 CSR_WRITE_2(sc, BM_RX_LECNT, 0); 1360 CSR_WRITE_2(sc, BM_RX_AECNT, 0); 1361 CSR_WRITE_2(sc, BM_RX_FECNT, 0); 1362 CSR_WRITE_2(sc, BM_RXCV, 0); 1363 1364 /* Check for link changes and run watchdog */ 1365 mii_tick(sc->sc_mii); 1366 bm_miibus_statchg(sc->sc_dev); 1367 1368 if (sc->sc_wdog_timer == 0 || --sc->sc_wdog_timer != 0) { 1369 callout_reset(&sc->sc_tick_ch, hz, bm_tick, sc); 1370 return; 1371 } 1372 1373 /* Problems */ 1374 device_printf(sc->sc_dev, "device timeout\n"); 1375 1376 bm_init_locked(sc); 1377} 1378 1379static int 1380bm_add_rxbuf(struct bm_softc *sc, int idx) 1381{ 1382 struct bm_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1383 struct mbuf *m; 1384 bus_dma_segment_t segs[1]; 1385 int error, nsegs; 1386 1387 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1388 if (m == NULL) 1389 return (ENOBUFS); 1390 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 1391 1392 if (rxs->rxs_mbuf != NULL) { 1393 bus_dmamap_sync(sc->sc_rdma_tag, rxs->rxs_dmamap, 1394 BUS_DMASYNC_POSTREAD); 1395 bus_dmamap_unload(sc->sc_rdma_tag, rxs->rxs_dmamap); 1396 } 1397 1398 error = bus_dmamap_load_mbuf_sg(sc->sc_rdma_tag, rxs->rxs_dmamap, m, 1399 segs, &nsegs, BUS_DMA_NOWAIT); 1400 if (error != 0) { 1401 device_printf(sc->sc_dev, 1402 "cannot load RS DMA map %d, error = %d\n", idx, error); 1403 m_freem(m); 1404 return (error); 1405 } 1406 /* If nsegs is wrong then the stack is corrupt. */ 1407 KASSERT(nsegs == 1, 1408 ("%s: too many DMA segments (%d)", __func__, nsegs)); 1409 rxs->rxs_mbuf = m; 1410 rxs->segment = segs[0]; 1411 1412 bus_dmamap_sync(sc->sc_rdma_tag, rxs->rxs_dmamap, BUS_DMASYNC_PREREAD); 1413 1414 return (0); 1415} 1416 1417static int 1418bm_add_rxbuf_dma(struct bm_softc *sc, int idx) 1419{ 1420 struct bm_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1421 1422 dbdma_insert_command(sc->sc_rxdma, idx, DBDMA_INPUT_LAST, 0, 1423 rxs->segment.ds_addr, rxs->segment.ds_len, DBDMA_ALWAYS, 1424 DBDMA_NEVER, DBDMA_NEVER, 0); 1425 1426 return (0); 1427} 1428 1429static void 1430bm_enable_interrupts(struct bm_softc *sc) 1431{ 1432 CSR_WRITE_2(sc, BM_INTR_DISABLE, 1433 (sc->sc_streaming) ? BM_INTR_NONE : BM_INTR_NORMAL); 1434} 1435 1436static void 1437bm_disable_interrupts(struct bm_softc *sc) 1438{ 1439 CSR_WRITE_2(sc, BM_INTR_DISABLE, BM_INTR_NONE); 1440} 1441