bhnd_pcireg.h revision 296077
12311Sjkh/*- 22311Sjkh * Copyright (c) 2015 Landon Fuller <landon@landonf.org> 32311Sjkh * Copyright (c) 2010 Broadcom Corporation 42311Sjkh * All rights reserved. 52311Sjkh * 62311Sjkh * This file is derived from the hndsoc.h, pci_core.h, and pcie_core.h headers 72311Sjkh * distributed with Broadcom's initial brcm80211 Linux driver release, as 82311Sjkh * contributed to the Linux staging repository. 92311Sjkh * 102311Sjkh * Permission to use, copy, modify, and/or distribute this software for any 112311Sjkh * purpose with or without fee is hereby granted, provided that the above 122311Sjkh * copyright notice and this permission notice appear in all copies. 132311Sjkh * 142311Sjkh * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 152311Sjkh * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 165176Sache * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 172311Sjkh * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 182311Sjkh * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 192311Sjkh * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 2015161Sscrappy * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 212311Sjkh * 222311Sjkh * $FreeBSD: head/sys/dev/bhnd/cores/pci/bhnd_pcireg.h 296077 2016-02-26 03:34:08Z adrian $ 232311Sjkh */ 242311Sjkh 252311Sjkh#ifndef _BHND_CORES_PCI_BHND_PCIREG_H_ 262311Sjkh#define _BHND_CORES_PCI_BHND_PCIREG_H_ 272311Sjkh 282311Sjkh/* 292311Sjkh * PCI/PCIe-Gen1 DMA Constants 302311Sjkh */ 312311Sjkh 322311Sjkh#define BHND_PCI_DMA32_TRANSLATION 0x40000000 /* Client Mode sb2pcitranslation2 (1 GB) */ 332311Sjkh#define BHND_PCI_DMA32_SZ 0x40000000 /* Client Mode sb2pcitranslation2 size in bytes */ 342311Sjkh 352311Sjkh#define BHND_PCIE_DMA32_TRANSLATION BHND_PCI_DMA32_TRANSLATION 362311Sjkh#define BHND_PCIE_DMA32_SZ BHND_PCI_DMA32_SZ 372311Sjkh 382311Sjkh#define BHND_PCIE_DMA64_L32 0x00000000 /**< 64-bit client mode sb2pcitranslation2 (2 ZettaBytes, low 32 bits) */ 392311Sjkh#define BHND_PCIE_DMA64_H32 0x80000000 /**< 64-bit client mode sb2pcitranslation2 (2 ZettaBytes, high 32 bits) */ 402311Sjkh 412311Sjkh/* 422311Sjkh * PCI Core Registers 432311Sjkh */ 442311Sjkh 452311Sjkh#define BHND_PCI_CTL 0x000 /**< PCI core control*/ 462311Sjkh#define BHND_PCI_ARB_CTL 0x010 /**< PCI arbiter control */ 472311Sjkh#define BHND_PCI_CLKRUN_CTL 0x014 /**< PCI clckrun control (>= rev11) */ 482311Sjkh#define BHND_PCI_INTR_STATUS 0x020 /**< Interrupt status */ 492311Sjkh#define BHND_PCI_INTR_MASK 0x024 /**< Interrupt mask */ 502311Sjkh#define BHND_PCI_SBTOPCI_MBOX 0x028 /**< Sonics to PCI mailbox */ 512311Sjkh#define BHND_PCI_BCAST_ADDR 0x050 /**< Sonics broadcast address (pci) */ 522311Sjkh#define BHND_PCI_BCAST_DATA 0x054 /**< Sonics broadcast data (pci) */ 532311Sjkh#define BHND_PCI_GPIO_IN 0x060 /**< GPIO input (>= rev2) */ 542311Sjkh#define BHND_PCI_GPIO_OUT 0x064 /**< GPIO output (>= rev2) */ 552311Sjkh#define BHND_PCI_GPIO_EN 0x068 /**< GPIO output enable (>= rev2) */ 562311Sjkh#define BHND_PCI_GPIO_CTL 0x06C /**< GPIO control (>= rev2) */ 572311Sjkh#define BHND_PCI_SBTOPCI0 0x100 /**< Sonics to PCI translation 0 */ 582311Sjkh#define BHND_PCI_SBTOPCI1 0x104 /**< Sonics to PCI translation 1 */ 592311Sjkh#define BHND_PCI_SBTOPCI2 0x108 /**< Sonics to PCI translation 2 */ 602311Sjkh#define BHND_PCI_FUNC0_CFG 0x400 /**< PCI function 0 cfg space (>= rev8) */ 612311Sjkh#define BHND_PCI_FUNC1_CFG 0x500 /**< PCI function 1 cfg space (>= rev8) */ 622311Sjkh#define BHND_PCI_FUNC2_CFG 0x600 /**< PCI function 2 cfg space (>= rev8) */ 632311Sjkh#define BHND_PCI_FUNC3_CFG 0x700 /**< PCI function 3 cfg space (>= rev8) */ 642311Sjkh#define BHND_PCI_SPROM_SHADOW 0x800 /**< PCI SPROM shadow */ 652311Sjkh 662311Sjkh/* BHND_PCI_CTL */ 672311Sjkh#define BHND_PCI_CTL_RST_OE 0x01 /* When set, drives PCI_RESET out to pin */ 682311Sjkh#define BHND_PCI_CTL_RST 0x02 /* Value driven out to pin */ 692311Sjkh#define BHND_PCI_CTL_CLK_OE 0x04 /* When set, drives clock as gated by PCI_CLK out to pin */ 702311Sjkh#define BHND_PCI_CTL_CLK 0x08 /* Gate for clock driven out to pin */ 712311Sjkh 722311Sjkh/* BHND_PCI_ARB_CTL */ 732311Sjkh#define BHND_PCI_ARB_INT 0x01 /* When set, use an internal arbiter */ 742311Sjkh#define BHND_PCI_ARB_EXT 0x02 /* When set, use an external arbiter */ 752311Sjkh 762311Sjkh/* BHND_PCI_ARB_CTL - ParkID (>= rev8) */ 772311Sjkh#define BHND_PCI_ARB_PARKID_MASK 0x1c /* Selects which agent is parked on an idle bus */ 782311Sjkh#define BHND_PCI_ARB_PARKID_SHIFT 2 792311Sjkh#define BHND_PCI_ARB_PARKID_EXT0 0 /* External master 0 */ 802311Sjkh#define BHND_PCI_ARB_PARKID_EXT1 1 /* External master 1 */ 812311Sjkh#define BHND_PCI_ARB_PARKID_EXT2 2 /* External master 2 */ 822311Sjkh#define BHND_PCI_ARB_PARKID_EXT3 3 /* External master 3 (rev >= 11) */ 832311Sjkh#define BHND_PCI_ARB_PARKID_INT_r10 3 /* Internal master (rev < 11) */ 842311Sjkh#define BHND_PCI_ARB_PARKID_INT_r11 4 /* Internal master (rev >= 11) */ 852311Sjkh#define BHND_PCI_ARB_PARKID_LAST_r10 4 /* Last active master (rev < 11) */ 862311Sjkh#define BHND_PCI_ARB_PARKID_LAST_r11 5 /* Last active master (rev >= 11) */ 872311Sjkh 882311Sjkh/* BHND_PCI_CLKRUN_CTL */ 892311Sjkh#define BHND_PCI_CLKRUN_DSBL 0x8000 /* Bit 15 forceClkrun */ 902311Sjkh 912311Sjkh/* BHND_PCI_INTR_STATUS / BHND_PCI_INTR_MASK */ 922311Sjkh#define BHND_PCI_INTR_A 0x01 /* PCI INTA# is asserted */ 932311Sjkh#define BHND_PCI_INTR_B 0x02 /* PCI INTB# is asserted */ 942311Sjkh#define BHND_PCI_INTR_SERR 0x04 /* PCI SERR# has been asserted (write one to clear) */ 952311Sjkh#define BHND_PCI_INTR_PERR 0x08 /* PCI PERR# has been asserted (write one to clear) */ 962311Sjkh 972311Sjkh/* BHND_PCI_SBTOPCI_MBOX 982311Sjkh * (General) PCI/SB mailbox interrupts, two bits per pci function */ 992311Sjkh#define BHND_PCI_SBTOPCI_MBOX_F0_0 0x100 /* function 0, int 0 */ 1002311Sjkh#define BHND_PCI_SBTOPCI_MBOX_F0_1 0x200 /* function 0, int 1 */ 1012311Sjkh#define BHND_PCI_SBTOPCI_MBOX_F1_0 0x400 /* function 1, int 0 */ 1022311Sjkh#define BHND_PCI_SBTOPCI_MBOX_F1_1 0x800 /* function 1, int 1 */ 1032311Sjkh#define BHND_PCI_SBTOPCI_MBOX_F2_0 0x1000 /* function 2, int 0 */ 1042311Sjkh#define BHND_PCI_SBTOPCI_MBOX_F2_1 0x2000 /* function 2, int 1 */ 1052311Sjkh#define BHND_PCI_SBTOPCI_MBOX_F3_0 0x4000 /* function 3, int 0 */ 1062311Sjkh#define BHND_PCI_SBTOPCI_MBOX_F3_1 0x8000 /* function 3, int 1 */ 1072311Sjkh 1082311Sjkh/* BHND_PCI_BCAST_ADDR */ 1092311Sjkh#define BHNC_PCI_BCAST_ADDR_MASK 0xFF /* Broadcast register address */ 1102311Sjkh 1112311Sjkh/* Sonics to PCI translation types */ 1122311Sjkh#define BHND_PCI_SBTOPCI0_MASK 0xfc000000 1132311Sjkh#define BHND_PCI_SBTOPCI1_MASK 0xfc000000 1142311Sjkh#define BHND_PCI_SBTOPCI2_MASK 0xc0000000 1152311Sjkh 1162311Sjkh/* Access type bits (0:1) */ 1172311Sjkh#define BHND_PCI_SBTOPCI_MEM 0 1182311Sjkh#define BHND_PCI_SBTOPCI_IO 1 1192311Sjkh#define BHND_PCI_SBTOPCI_CFG0 2 1202311Sjkh#define BHND_PCI_SBTOPCI_CFG1 3 1212311Sjkh 1222311Sjkh#define BHND_PCI_SBTOPCI_PREF 0x4 /* prefetch enable */ 1232311Sjkh#define BHND_PCI_SBTOPCI_BURST 0x8 /* burst enable */ 1242311Sjkh 1252311Sjkh#define BHND_PCI_SBTOPCI_RC_MASK 0x30 /* read command (>= rev11) */ 1262311Sjkh#define BHND_PCI_SBTOPCI_RC_READ 0x00 /* memory read */ 1272311Sjkh#define BHND_PCI_SBTOPCI_RC_READLINE 0x10 /* memory read line */ 1282311Sjkh#define BHND_PCI_SBTOPCI_RC_READMULTI 0x20 /* memory read multiple */ 1292311Sjkh 1302311Sjkh/* PCI core index in SROM shadow area */ 1312311Sjkh#define BHND_PCI_SRSH_PI_OFFSET 0 /* first word */ 1322311Sjkh#define BHND_PCI_SRSH_PI_MASK 0xf000 /* bit 15:12 */ 1338857Srgrimes#define BHND_PCI_SRSH_PI_SHIFT 12 /* bit 15:12 */ 1342311Sjkh 1352311Sjkh 1362311Sjkh 1372311Sjkh/* 1382311Sjkh * PCIe-Gen1 Core Registers 1392311Sjkh */ 1402311Sjkh 1412311Sjkh#define BHND_PCIE_CTL BHND_PCI_CTL /**< PCI core control*/ 1422311Sjkh#define BHND_PCIE_BIST_STATUS 0x00C /**< BIST status */ 1432311Sjkh#define BHND_PCIE_GPIO_SEL 0x010 /**< GPIO select */ 1442311Sjkh#define BHND_PCIE_GPIO_OUT_EN 0x014 /**< GPIO output enable */ 1452311Sjkh#define BHND_PCIE_INTR_STATUS BHND_PCI_INTR_STATUS /**< Interrupt status */ 1462311Sjkh#define BHND_PCIE_INTR_MASK BHND_PCI_INTR_MASK /**< Interrupt mask */ 1472311Sjkh#define BHND_PCIE_SBTOPCI_MBOX BHND_PCI_SBTOPCI_MBOX /**< Sonics to PCI mailbox */ 1482311Sjkh#define BHND_PCIE_SBTOPCI0 BHND_PCI_SBTOPCI0 /**< Sonics to PCI translation 0 */ 1492311Sjkh#define BHND_PCIE_SBTOPCI1 BHND_PCI_SBTOPCI1 /**< Sonics to PCI translation 1 */ 1502311Sjkh#define BHND_PCIE_SBTOPCI2 BHND_PCI_SBTOPCI2 /**< Sonics to PCI translation 2 */ 1512311Sjkh 1522311Sjkh/* indirect pci config space access */ 1532311Sjkh#define BHND_PCIE_CFG_ADDR 0x120 /**< pcie config space address */ 1542311Sjkh#define BHND_PCIE_CFG_DATA 0x124 /**< pcie config space data */ 1552311Sjkh 1562311Sjkh/* mdio register access */ 1572311Sjkh#define BHND_PCIE_MDIO_CTL 0x128 /**< mdio control */ 1582311Sjkh#define BHND_PCIE_MDIO_DATA 0x12C /**< mdio data */ 1592311Sjkh 1602311Sjkh/* indirect protocol phy/dllp/tlp register access */ 1612311Sjkh#define BHND_PCIE_IND_ADDR 0x130 /**< internal protocol register address */ 1622311Sjkh#define BHND_PCIE_IND_DATA 0x134 /**< internal protocol register data */ 1632311Sjkh 1642311Sjkh#define BHND_PCIE_CLKREQEN_CTL 0x138 /**< clkreq rdma control */ 1652311Sjkh#define BHND_PCIE_FUNC0_CFG BHND_PCI_FUNC0_CFG /**< PCI function 0 cfg space */ 1662311Sjkh#define BHND_PCIE_FUNC1_CFG BHND_PCI_FUNC1_CFG /**< PCI function 1 cfg space */ 1672311Sjkh#define BHND_PCIE_FUNC2_CFG BHND_PCI_FUNC2_CFG /**< PCI function 2 cfg space */ 1682311Sjkh#define BHND_PCIE_FUNC3_CFG BHND_PCI_FUNC3_CFG /**< PCI function 3 cfg space */ 1692311Sjkh#define BHND_PCIE_SPROM_SHADOW BHND_PCI_SPROM_SHADOW /**< PCI SPROM shadow */ 1702311Sjkh 1712311Sjkh/* BHND_PCIE_CTL */ 1722311Sjkh#define BHND_PCIE_CTL_RST_OE BHND_PCI_CTL_RST_OE /* When set, drives PCI_RESET out to pin */ 1732311Sjkh#define BHND_PCIE_CTL_RST BHND_PCI_CTL_RST_OE /* Value driven out to pin */ 1742311Sjkh 1752311Sjkh/* BHND_PCI_INTR_STATUS / BHND_PCI_INTR_MASK */ 1762311Sjkh#define BHND_PCIE_INTR_A BHND_PCI_INTR_A /* PCIE INTA message is received */ 1772311Sjkh#define BHND_PCIE_INTR_B BHND_PCI_INTR_B /* PCIE INTB message is received */ 1782311Sjkh#define BHND_PCIE_INTR_FATAL 0x04 /* PCIE INTFATAL message is received */ 1792311Sjkh#define BHND_PCIE_INTR_NFATAL 0x08 /* PCIE INTNONFATAL message is received */ 1802311Sjkh#define BHND_PCIE_INTR_CORR 0x10 /* PCIE INTCORR message is received */ 1812311Sjkh#define BHND_PCIE_INTR_PME 0x20 /* PCIE INTPME message is received */ 1822311Sjkh 1832311Sjkh/* SB to PCIE translation masks */ 1842311Sjkh#define BHND_PCIE_SBTOPCI0_MASK BHND_PCI_SBTOPCI0_MASK 1852311Sjkh#define BHND_PCIE_SBTOPCI1_MASK BHND_PCI_SBTOPCI1_MASK 1862311Sjkh#define BHND_PCIE_SBTOPCI2_MASK BHND_PCI_SBTOPCI2_MASK 1872311Sjkh 1882311Sjkh/* Access type bits (0:1) */ 1892311Sjkh#define BHND_PCIE_SBTOPCI_MEM BHND_PCI_SBTOPCI_MEM 1902311Sjkh#define BHND_PCIE_SBTOPCI_IO BHND_PCI_SBTOPCI_IO 1912311Sjkh#define BHND_PCIE_SBTOPCI_CFG0 BHND_PCI_SBTOPCI_CFG0 1922311Sjkh#define BHND_PCIE_SBTOPCI_CFG1 BHND_PCI_SBTOPCI_CFG1 1932311Sjkh 1942311Sjkh#define BHND_PCIE_SBTOPCI_PREF BHND_PCI_SBTOPCI_PREF /* prefetch enable */ 1952311Sjkh#define BHND_PCIE_SBTOPCI_BURST BHND_PCI_SBTOPCI_BURST /* burst enable */ 1962311Sjkh 1972311Sjkh/* BHND_PCIE_CFG_ADDR / BHND_PCIE_CFG_DATA */ 1982311Sjkh#define BHND_PCIE_CFG_ADDR_FUNC_MASK 0x7000 1992311Sjkh#define BHND_PCIE_CFG_ADDR_FUNC_SHIFT 12 2002311Sjkh#define BHND_PCIE_CFG_ADDR_REG_MASK 0x0FFF 2012311Sjkh#define BHND_PCIE_CFG_ADDR_REG_SHIFT 0 2022311Sjkh 2032311Sjkh#define BHND_PCIE_CFG_OFFSET(f, r) \ 2042311Sjkh ((((f) & BHND_PCIE_CFG_ADDR_FUNC_MASK) << BHND_PCIE_CFG_ADDR_FUNC_SHIFT) | \ 2052311Sjkh (((r) & BHND_PCIE_CFG_ADDR_FUNC_SHIFT) << BHND_PCIE_CFG_ADDR_REG_SHIFT)) 2062311Sjkh 2072311Sjkh/* PCIE protocol PHY diagnostic registers */ 2082311Sjkh#define BHND_PCIE_PLP_MODEREG 0x200 /* Mode */ 2092311Sjkh#define BHND_PCIE_PLP_STATUSREG 0x204 /* Status */ 2102311Sjkh#define BHND_PCIE_PLP_LTSSMCTRLREG 0x208 /* LTSSM control */ 2112311Sjkh#define BHND_PCIE_PLP_LTLINKNUMREG 0x20c /* Link Training Link number */ 2122311Sjkh#define BHND_PCIE_PLP_LTLANENUMREG 0x210 /* Link Training Lane number */ 2132311Sjkh#define BHND_PCIE_PLP_LTNFTSREG 0x214 /* Link Training N_FTS */ 2142311Sjkh#define BHND_PCIE_PLP_ATTNREG 0x218 /* Attention */ 2152311Sjkh#define BHND_PCIE_PLP_ATTNMASKREG 0x21C /* Attention Mask */ 2162311Sjkh#define BHND_PCIE_PLP_RXERRCTR 0x220 /* Rx Error */ 2172311Sjkh#define BHND_PCIE_PLP_RXFRMERRCTR 0x224 /* Rx Framing Error */ 2182311Sjkh#define BHND_PCIE_PLP_RXERRTHRESHREG 0x228 /* Rx Error threshold */ 2192311Sjkh#define BHND_PCIE_PLP_TESTCTRLREG 0x22C /* Test Control reg */ 2202311Sjkh#define BHND_PCIE_PLP_SERDESCTRLOVRDREG 0x230 /* SERDES Control Override */ 2212311Sjkh#define BHND_PCIE_PLP_TIMINGOVRDREG 0x234 /* Timing param override */ 2222311Sjkh#define BHND_PCIE_PLP_RXTXSMDIAGREG 0x238 /* RXTX State Machine Diag */ 2232311Sjkh#define BHND_PCIE_PLP_LTSSMDIAGREG 0x23C /* LTSSM State Machine Diag */ 2242311Sjkh 2252311Sjkh/* PCIE protocol DLLP diagnostic registers */ 2262311Sjkh#define BHND_PCIE_DLLP_LCREG 0x100 /* Link Control */ 2272311Sjkh#define BHND_PCIE_DLLP_LCREG_PCIPM_EN 0x40 /* Enable PCI-PM power management */ 2282311Sjkh#define BHND_PCIE_DLLP_LSREG 0x104 /* Link Status */ 2292311Sjkh#define BHND_PCIE_DLLP_LAREG 0x108 /* Link Attention */ 2302311Sjkh#define BHND_PCIE_DLLP_LAMASKREG 0x10C /* Link Attention Mask */ 2312311Sjkh#define BHND_PCIE_DLLP_NEXTTXSEQNUMREG 0x110 /* Next Tx Seq Num */ 2322311Sjkh#define BHND_PCIE_DLLP_ACKEDTXSEQNUMREG 0x114 /* Acked Tx Seq Num */ 2332311Sjkh#define BHND_PCIE_DLLP_PURGEDTXSEQNUMREG 0x118 /* Purged Tx Seq Num */ 2342311Sjkh#define BHND_PCIE_DLLP_RXSEQNUMREG 0x11C /* Rx Sequence Number */ 2352311Sjkh#define BHND_PCIE_DLLP_LRREG 0x120 /* Link Replay */ 2362311Sjkh#define BHND_PCIE_DLLP_LACKTOREG 0x124 /* Link Ack Timeout */ 2372311Sjkh#define BHND_PCIE_DLLP_PMTHRESHREG 0x128 /* Power Management Threshold */ 2382311Sjkh#define BHND_PCIE_L0THRESHOLDTIME_MASK 0xFF00 /* bits 0 - 7 */ 2392311Sjkh#define BHND_PCIE_L1THRESHOLDTIME_MASK 0xFF00 /* bits 8 - 15 */ 2402311Sjkh#define BHND_PCIE_L1THRESHOLDTIME_SHIFT 8 /* PCIE_L1THRESHOLDTIME_SHIFT */ 2412311Sjkh#define BHND_PCIE_L1THRESHOLD_WARVAL 0x72 /* WAR value */ 2422311Sjkh#define BHND_PCIE_ASPMTIMER_EXTEND 0x1000000 /* > rev7: enable extend ASPM timer */ 2432311Sjkh#define BHND_PCIE_DLLP_RTRYWPREG 0x12C /* Retry buffer write ptr */ 2442311Sjkh#define BHND_PCIE_DLLP_RTRYRPREG 0x130 /* Retry buffer Read ptr */ 2452311Sjkh#define BHND_PCIE_DLLP_RTRYPPREG 0x134 /* Retry buffer Purged ptr */ 2462311Sjkh#define BHND_PCIE_DLLP_RTRRWREG 0x138 /* Retry buffer Read/Write */ 2472311Sjkh#define BHND_PCIE_DLLP_ECTHRESHREG 0x13C /* Error Count Threshold */ 2482311Sjkh#define BHND_PCIE_DLLP_TLPERRCTRREG 0x140 /* TLP Error Counter */ 2492311Sjkh#define BHND_PCIE_DLLP_ERRCTRREG 0x144 /* Error Counter */ 2502311Sjkh#define BHND_PCIE_DLLP_NAKRXCTRREG 0x148 /* NAK Received Counter */ 2512311Sjkh#define BHND_PCIE_DLLP_TESTREG 0x14C /* Test */ 2522311Sjkh#define BHND_PCIE_DLLP_PKTBIST 0x150 /* Packet BIST */ 2532311Sjkh#define BHND_PCIE_DLLP_PCIE11 0x154 /* DLLP PCIE 1.1 reg */ 2542311Sjkh 2552311Sjkh#define BHND_PCIE_DLLP_LSREG_LINKUP (1 << 16) 2562311Sjkh 2572311Sjkh/* PCIE protocol TLP diagnostic registers */ 2582311Sjkh#define BHND_PCIE_TLP_CONFIGREG 0x000 /* Configuration */ 2592311Sjkh#define BHND_PCIE_TLP_WORKAROUNDSREG 0x004 /* TLP Workarounds */ 2602311Sjkh#define BHND_PCIE_TLP_WORKAROUND_URBIT 0x8 /* If enabled, UR status bit is set 2612311Sjkh * on memory access of an unmatched 2622311Sjkh * address */ 2632311Sjkh 2642311Sjkh#define BHND_PCIE_TLP_WRDMAUPPER 0x010 /* Write DMA Upper Address */ 2652311Sjkh#define BHND_PCIE_TLP_WRDMALOWER 0x014 /* Write DMA Lower Address */ 2662311Sjkh#define BHND_PCIE_TLP_WRDMAREQ_LBEREG 0x018 /* Write DMA Len/ByteEn Req */ 2672311Sjkh#define BHND_PCIE_TLP_RDDMAUPPER 0x01C /* Read DMA Upper Address */ 2682311Sjkh#define BHND_PCIE_TLP_RDDMALOWER 0x020 /* Read DMA Lower Address */ 2692311Sjkh#define BHND_PCIE_TLP_RDDMALENREG 0x024 /* Read DMA Len Req */ 2702311Sjkh#define BHND_PCIE_TLP_MSIDMAUPPER 0x028 /* MSI DMA Upper Address */ 2712311Sjkh#define BHND_PCIE_TLP_MSIDMALOWER 0x02C /* MSI DMA Lower Address */ 2722311Sjkh#define BHND_PCIE_TLP_MSIDMALENREG 0x030 /* MSI DMA Len Req */ 2732311Sjkh#define BHND_PCIE_TLP_SLVREQLENREG 0x034 /* Slave Request Len */ 2742311Sjkh#define BHND_PCIE_TLP_FCINPUTSREQ 0x038 /* Flow Control Inputs */ 2752311Sjkh#define BHND_PCIE_TLP_TXSMGRSREQ 0x03C /* Tx StateMachine and Gated Req */ 2762311Sjkh#define BHND_PCIE_TLP_ADRACKCNTARBLEN 0x040 /* Address Ack XferCnt and ARB Len */ 2772311Sjkh#define BHND_PCIE_TLP_DMACPLHDR0 0x044 /* DMA Completion Hdr 0 */ 2782311Sjkh#define BHND_PCIE_TLP_DMACPLHDR1 0x048 /* DMA Completion Hdr 1 */ 2792311Sjkh#define BHND_PCIE_TLP_DMACPLHDR2 0x04C /* DMA Completion Hdr 2 */ 2802311Sjkh#define BHND_PCIE_TLP_DMACPLMISC0 0x050 /* DMA Completion Misc0 */ 2812311Sjkh#define BHND_PCIE_TLP_DMACPLMISC1 0x054 /* DMA Completion Misc1 */ 2822311Sjkh#define BHND_PCIE_TLP_DMACPLMISC2 0x058 /* DMA Completion Misc2 */ 2832311Sjkh#define BHND_PCIE_TLP_SPTCTRLLEN 0x05C /* Split Controller Req len */ 2842311Sjkh#define BHND_PCIE_TLP_SPTCTRLMSIC0 0x060 /* Split Controller Misc 0 */ 2852311Sjkh#define BHND_PCIE_TLP_SPTCTRLMSIC1 0x064 /* Split Controller Misc 1 */ 2862311Sjkh#define BHND_PCIE_TLP_BUSDEVFUNC 0x068 /* Bus/Device/Func */ 2872311Sjkh#define BHND_PCIE_TLP_RESETCTR 0x06C /* Reset Counter */ 2882311Sjkh#define BHND_PCIE_TLP_RTRYBUF 0x070 /* Retry Buffer value */ 2892311Sjkh#define BHND_PCIE_TLP_TGTDEBUG1 0x074 /* Target Debug Reg1 */ 2902311Sjkh#define BHND_PCIE_TLP_TGTDEBUG2 0x078 /* Target Debug Reg2 */ 2912311Sjkh#define BHND_PCIE_TLP_TGTDEBUG3 0x07C /* Target Debug Reg3 */ 2922311Sjkh#define BHND_PCIE_TLP_TGTDEBUG4 0x080 /* Target Debug Reg4 */ 2932311Sjkh 2942311Sjkh 2952311Sjkh/* 2962311Sjkh * PCIe-G1 SerDes MDIO Registers (>= rev10) 2972311Sjkh */ 2982311Sjkh#define BHND_PCIE_PHYADDR_SD 0x0 /* serdes PHY address */ 2992311Sjkh#define BHND_PCIE_DEVAD_SD 0x1 /* serdes pseudo-devad (PMA) recognized by 3002311Sjkh the bhnd_mdio_pcie driver */ 3012311Sjkh 3022311Sjkh#define BHND_PCIE_SD_ADDREXT 0x1F /* serdes address extension register */ 3032311Sjkh#define BHND_PCIE_SD_ADDREXT_BLK_MASK 0xFFF0 /* register block mask */ 3042311Sjkh#define BHND_PCIE_SD_ADDREXT_REG_MASK 0x000F /* register address mask */ 3052311Sjkh 3062311Sjkh#define BHND_PCIE_SD_REGS_IEEE0 0x0000 /* IEEE0 AN CTRL block */ 3072311Sjkh#define BHND_PCIE_SD_REGS_IEEE1 0x0010 /* IEEE1 AN ADV block */ 3082311Sjkh#define BHND_PCIE_SD_REGS_BLK0 0x8000 /* ??? */ 3092311Sjkh#define BHND_PCIE_SD_REGS_BLK1 0x8010 /* ??? */ 3102311Sjkh#define BHND_PCIE_SD_REGS_BLK2 0x8020 /* ??? */ 3112311Sjkh#define BHND_PCIE_SD_REGS_BLK3 0x8030 /* ??? */ 3122311Sjkh#define BHND_PCIE_SD_REGS_BLK4 0x8040 /* ??? */ 3132311Sjkh#define BHND_PCIE_SD_REGS_TXPLL 0x8080 /* TXPLL register block */ 3142311Sjkh#define BHND_PCIE_SD_REGS_TXCTRL0 0x8200 /* ??? */ 3152311Sjkh#define BHND_PCIE_SD_REGS_SERDESID 0x8310 /* ??? */ 3162311Sjkh#define BHND_PCIE_SD_REGS_RXCTRL0 0x8400 /* ??? */ 3172311Sjkh 3182311Sjkh/* 3192311Sjkh * PCIe-G1 SerDes-R9 MDIO Registers (<= rev9) 3202311Sjkh * 3212311Sjkh * These register definitions appear to match those provided in the 3222311Sjkh * "PCI Express SerDes Registers" section of the BCM5761 Ethernet Controller 3232311Sjkh * Programmer's Reference Guide. 3242311Sjkh */ 3252311Sjkh#define BHND_PCIE_PHY_SDR9_PLL 0x1C /* SerDes PLL PHY Address*/ 3262311Sjkh#define BHND_PCIE_SDR9_PLL_CTRL 0x17 /* PLL control reg */ 3272311Sjkh#define BHND_PCIE_SDR9_PLL_CTRL_FREQDET_EN 0x4000 /* bit 14 is FREQDET on */ 3282311Sjkh#define BHND_PCIE_PHY_SDR9_TXRX 0x0F /* SerDes RX/TX PHY Address */ 3292311Sjkh 3302311Sjkh#define BHND_PCIE_SDR9_RX_CTRL 0x11 /* RX ctrl register */ 3312311Sjkh#define BHND_PCIE_SDR9_RX_CTRL_FORCE 0x80 /* rxpolarity_force */ 3325176Sache#define BHND_PCIE_SDR9_RX_CTRL_POLARITY_INV 0x40 /* rxpolarity_value (if set, inverse polarity) */ 3332311Sjkh 3342311Sjkh#define BHND_PCIE_SDR9_RX_CDR 0x16 /* RX CDR ctrl register */ 3352311Sjkh#define BHND_PCIE_SDR9_RX_CDR_FREQ_OVR_EN 0x0100 /* freq_override_en flag */ 3362311Sjkh#define BHND_PCIE_SDR9_RX_CDR_FREQ_OVR_MASK 0x00FF /* freq_override_val */ 3372311Sjkh#define BHND_PCIE_SDR9_RX_CDR_FREQ_OVR_SHIFT 0 3382311Sjkh 3392311Sjkh#define BHND_PCIE_SDR9_RX_CDRBW 0x17 /* RX CDR bandwidth (PLL tuning) */ 3402311Sjkh#define BHND_PCIE_SDR9_RX_CDRBW_INTGTRK_MASK 0x7000 /* integral loop bandwidth (phase tracking mode) */ 3412311Sjkh#define BHND_PCIE_SDR9_RX_CDRBW_INTGTRK_SHIFT 11 3422311Sjkh#define BHND_PCIE_SDR9_RX_CDRBW_INTGACQ_MASK 0x0700 /* integral loop bandwidth (phase acquisition mode) */ 3432311Sjkh#define BHND_PCIE_SDR9_RX_CDRBW_INTGACQ_SHIFT 8 3442311Sjkh#define BHND_PCIE_SDR9_RX_CDRBW_PROPTRK_MASK 0x0070 /* proportional loop bandwidth (phase tracking mode) */ 3452311Sjkh#define BHND_PCIE_SDR9_RX_CDRBW_PROPTRK_SHIFT 4 3462311Sjkh#define BHND_PCIE_SDR9_RX_CDRBW_PROPACQ_MASK 0x0007 /* proportional loop bandwidth (phase acquisition mode) */ 3472311Sjkh#define BHND_PCIE_SDR9_RX_CDRBW_PROPACQ_SHIFT 0 3482311Sjkh 3492311Sjkh#define BHND_PCIE_SDR9_RX_TIMER1 0x12 /* timer1 register */ 3502311Sjkh#define BHND_PCIE_SDR9_RX_TIMER1_LKTRK_MASK 0xFF00 /* phase tracking delay before asserting RX seq completion (in 16ns units) */ 3512311Sjkh#define BHND_PCIE_SDR9_RX_TIMER1_LKTRK_SHIFT 8 3522311Sjkh#define BHND_PCIE_SDR9_RX_TIMER1_LKACQ_MASK 0x00FF /* phase acquisition mode time (in 1024ns units) */ 3532311Sjkh#define BHND_PCIE_SDR9_RX_TIMER1_LKACQ_SHIFT 0 3542311Sjkh 3552311Sjkh 3562311Sjkh/* SPROM offsets */ 3572311Sjkh#define BHND_PCIE_SRSH_PI_OFFSET BHND_PCI_SRSH_PI_OFFSET /**< PCI core index in SROM shadow area */ 3582311Sjkh#define BHND_PCIE_SRSH_PI_MASK BHND_PCI_SRSH_PI_MASK 3592311Sjkh#define BHND_PCIE_SRSH_PI_SHIFT BHND_PCI_SRSH_PI_SHIFT 3602311Sjkh 3612311Sjkh#define BHND_PCIE_SRSH_ASPM_OFFSET 8 /* word 4 */ 3625176Sache#define BHND_PCIE_SRSH_ASPM_ENB 0x18 /* bit 3, 4 */ 3632311Sjkh#define BHND_PCIE_SRSH_ASPM_L1_ENB 0x10 /* bit 4 */ 3642311Sjkh#define BHND_PCIE_SRSH_ASPM_L0s_ENB 0x8 /* bit 3 */ 3652311Sjkh#define BHND_PCIE_SRSH_PCIE_MISC_CONFIG 10 /* word 5 */ 3662311Sjkh#define BHND_PCIE_SRSH_L23READY_EXIT_NOPRST 0x8000 /* bit 15 */ 3675176Sache#define BHND_PCIE_SRSH_CLKREQ_OFFSET_REV5 40 /* word 20 for srom rev <= 5 */ 3685176Sache#define BHND_PCIE_SRSH_CLKREQ_OFFSET_REV8 104 /* word 52 for srom rev 8 */ 3692311Sjkh#define BHND_PCIE_SRSH_CLKREQ_ENB 0x0800 /* bit 11 */ 3702311Sjkh#define BHND_PCIE_SRSH_BD_OFFSET 12 /* word 6 */ 3712311Sjkh#define BHND_PCIE_SRSH_AUTOINIT_OFFSET 36 /* auto initialization enable */ 3722311Sjkh 3732311Sjkh/* Linkcontrol reg offset in PCIE Cap */ 3742311Sjkh#define BHND_PCIE_CAP_LINKCTRL_OFFSET 16 /* linkctrl offset in pcie cap */ 3752311Sjkh#define BHND_PCIE_CAP_LCREG_ASPML0s 0x01 /* ASPM L0s in linkctrl */ 3762311Sjkh#define BHND_PCIE_CAP_LCREG_ASPML1 0x02 /* ASPM L1 in linkctrl */ 3772311Sjkh#define BHND_PCIE_CLKREQ_ENAB 0x100 /* CLKREQ Enab in linkctrl */ 3782311Sjkh 3792311Sjkh#define BHND_PCIE_ASPM_ENAB 3 /* ASPM L0s & L1 in linkctrl */ 3802311Sjkh#define BHND_PCIE_ASPM_L1_ENAB 2 /* ASPM L0s & L1 in linkctrl */ 3812311Sjkh#define BHND_PCIE_ASPM_L0s_ENAB 1 /* ASPM L0s & L1 in linkctrl */ 3822311Sjkh#define BHND_PCIE_ASPM_DISAB 0 /* ASPM L0s & L1 in linkctrl */ 3832311Sjkh 3842311Sjkh/* Status reg PCIE_PLP_STATUSREG */ 3852311Sjkh#define BHND_PCIE_PLP_POLARITY_INV 0x10 /* lane polarity is inverted */ 3862311Sjkh 3872311Sjkh#endif /* _BHND_CORES_PCI_BHND_PCIREG_H_ */ 3882311Sjkh