1296077Sadrian/*- 2296077Sadrian * Copyright (c) 2015 Landon Fuller <landon@landonf.org> 3296077Sadrian * Copyright (c) 2010 Broadcom Corporation 4296077Sadrian * All rights reserved. 5296077Sadrian * 6296077Sadrian * This file is derived from the hndsoc.h, pci_core.h, and pcie_core.h headers 7296077Sadrian * distributed with Broadcom's initial brcm80211 Linux driver release, as 8296077Sadrian * contributed to the Linux staging repository. 9296077Sadrian * 10296077Sadrian * Permission to use, copy, modify, and/or distribute this software for any 11296077Sadrian * purpose with or without fee is hereby granted, provided that the above 12296077Sadrian * copyright notice and this permission notice appear in all copies. 13296077Sadrian * 14296077Sadrian * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 15296077Sadrian * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 16296077Sadrian * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 17296077Sadrian * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 18296077Sadrian * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 19296077Sadrian * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 20296077Sadrian * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 21296077Sadrian * 22296077Sadrian * $FreeBSD$ 23296077Sadrian */ 24296077Sadrian 25296077Sadrian#ifndef _BHND_CORES_PCI_BHND_PCIREG_H_ 26296077Sadrian#define _BHND_CORES_PCI_BHND_PCIREG_H_ 27296077Sadrian 28296077Sadrian/* 29296077Sadrian * PCI/PCIe-Gen1 DMA Constants 30296077Sadrian */ 31296077Sadrian 32296077Sadrian#define BHND_PCI_DMA32_TRANSLATION 0x40000000 /* Client Mode sb2pcitranslation2 (1 GB) */ 33296077Sadrian#define BHND_PCI_DMA32_SZ 0x40000000 /* Client Mode sb2pcitranslation2 size in bytes */ 34296077Sadrian 35296077Sadrian#define BHND_PCIE_DMA32_TRANSLATION BHND_PCI_DMA32_TRANSLATION 36296077Sadrian#define BHND_PCIE_DMA32_SZ BHND_PCI_DMA32_SZ 37296077Sadrian 38296077Sadrian#define BHND_PCIE_DMA64_L32 0x00000000 /**< 64-bit client mode sb2pcitranslation2 (2 ZettaBytes, low 32 bits) */ 39296077Sadrian#define BHND_PCIE_DMA64_H32 0x80000000 /**< 64-bit client mode sb2pcitranslation2 (2 ZettaBytes, high 32 bits) */ 40296077Sadrian 41296077Sadrian/* 42296077Sadrian * PCI Core Registers 43296077Sadrian */ 44296077Sadrian 45296077Sadrian#define BHND_PCI_CTL 0x000 /**< PCI core control*/ 46296077Sadrian#define BHND_PCI_ARB_CTL 0x010 /**< PCI arbiter control */ 47296077Sadrian#define BHND_PCI_CLKRUN_CTL 0x014 /**< PCI clckrun control (>= rev11) */ 48296077Sadrian#define BHND_PCI_INTR_STATUS 0x020 /**< Interrupt status */ 49296077Sadrian#define BHND_PCI_INTR_MASK 0x024 /**< Interrupt mask */ 50296077Sadrian#define BHND_PCI_SBTOPCI_MBOX 0x028 /**< Sonics to PCI mailbox */ 51296077Sadrian#define BHND_PCI_BCAST_ADDR 0x050 /**< Sonics broadcast address (pci) */ 52296077Sadrian#define BHND_PCI_BCAST_DATA 0x054 /**< Sonics broadcast data (pci) */ 53296077Sadrian#define BHND_PCI_GPIO_IN 0x060 /**< GPIO input (>= rev2) */ 54296077Sadrian#define BHND_PCI_GPIO_OUT 0x064 /**< GPIO output (>= rev2) */ 55296077Sadrian#define BHND_PCI_GPIO_EN 0x068 /**< GPIO output enable (>= rev2) */ 56296077Sadrian#define BHND_PCI_GPIO_CTL 0x06C /**< GPIO control (>= rev2) */ 57296077Sadrian#define BHND_PCI_SBTOPCI0 0x100 /**< Sonics to PCI translation 0 */ 58296077Sadrian#define BHND_PCI_SBTOPCI1 0x104 /**< Sonics to PCI translation 1 */ 59296077Sadrian#define BHND_PCI_SBTOPCI2 0x108 /**< Sonics to PCI translation 2 */ 60296077Sadrian#define BHND_PCI_FUNC0_CFG 0x400 /**< PCI function 0 cfg space (>= rev8) */ 61296077Sadrian#define BHND_PCI_FUNC1_CFG 0x500 /**< PCI function 1 cfg space (>= rev8) */ 62296077Sadrian#define BHND_PCI_FUNC2_CFG 0x600 /**< PCI function 2 cfg space (>= rev8) */ 63296077Sadrian#define BHND_PCI_FUNC3_CFG 0x700 /**< PCI function 3 cfg space (>= rev8) */ 64296077Sadrian#define BHND_PCI_SPROM_SHADOW 0x800 /**< PCI SPROM shadow */ 65296077Sadrian 66296077Sadrian/* BHND_PCI_CTL */ 67296077Sadrian#define BHND_PCI_CTL_RST_OE 0x01 /* When set, drives PCI_RESET out to pin */ 68296077Sadrian#define BHND_PCI_CTL_RST 0x02 /* Value driven out to pin */ 69296077Sadrian#define BHND_PCI_CTL_CLK_OE 0x04 /* When set, drives clock as gated by PCI_CLK out to pin */ 70296077Sadrian#define BHND_PCI_CTL_CLK 0x08 /* Gate for clock driven out to pin */ 71296077Sadrian 72296077Sadrian/* BHND_PCI_ARB_CTL */ 73296077Sadrian#define BHND_PCI_ARB_INT 0x01 /* When set, use an internal arbiter */ 74296077Sadrian#define BHND_PCI_ARB_EXT 0x02 /* When set, use an external arbiter */ 75296077Sadrian 76296077Sadrian/* BHND_PCI_ARB_CTL - ParkID (>= rev8) */ 77296077Sadrian#define BHND_PCI_ARB_PARKID_MASK 0x1c /* Selects which agent is parked on an idle bus */ 78296077Sadrian#define BHND_PCI_ARB_PARKID_SHIFT 2 79296077Sadrian#define BHND_PCI_ARB_PARKID_EXT0 0 /* External master 0 */ 80296077Sadrian#define BHND_PCI_ARB_PARKID_EXT1 1 /* External master 1 */ 81296077Sadrian#define BHND_PCI_ARB_PARKID_EXT2 2 /* External master 2 */ 82296077Sadrian#define BHND_PCI_ARB_PARKID_EXT3 3 /* External master 3 (rev >= 11) */ 83296077Sadrian#define BHND_PCI_ARB_PARKID_INT_r10 3 /* Internal master (rev < 11) */ 84296077Sadrian#define BHND_PCI_ARB_PARKID_INT_r11 4 /* Internal master (rev >= 11) */ 85296077Sadrian#define BHND_PCI_ARB_PARKID_LAST_r10 4 /* Last active master (rev < 11) */ 86296077Sadrian#define BHND_PCI_ARB_PARKID_LAST_r11 5 /* Last active master (rev >= 11) */ 87296077Sadrian 88296077Sadrian/* BHND_PCI_CLKRUN_CTL */ 89296077Sadrian#define BHND_PCI_CLKRUN_DSBL 0x8000 /* Bit 15 forceClkrun */ 90296077Sadrian 91296077Sadrian/* BHND_PCI_INTR_STATUS / BHND_PCI_INTR_MASK */ 92296077Sadrian#define BHND_PCI_INTR_A 0x01 /* PCI INTA# is asserted */ 93296077Sadrian#define BHND_PCI_INTR_B 0x02 /* PCI INTB# is asserted */ 94296077Sadrian#define BHND_PCI_INTR_SERR 0x04 /* PCI SERR# has been asserted (write one to clear) */ 95296077Sadrian#define BHND_PCI_INTR_PERR 0x08 /* PCI PERR# has been asserted (write one to clear) */ 96296077Sadrian 97296077Sadrian/* BHND_PCI_SBTOPCI_MBOX 98296077Sadrian * (General) PCI/SB mailbox interrupts, two bits per pci function */ 99296077Sadrian#define BHND_PCI_SBTOPCI_MBOX_F0_0 0x100 /* function 0, int 0 */ 100296077Sadrian#define BHND_PCI_SBTOPCI_MBOX_F0_1 0x200 /* function 0, int 1 */ 101296077Sadrian#define BHND_PCI_SBTOPCI_MBOX_F1_0 0x400 /* function 1, int 0 */ 102296077Sadrian#define BHND_PCI_SBTOPCI_MBOX_F1_1 0x800 /* function 1, int 1 */ 103296077Sadrian#define BHND_PCI_SBTOPCI_MBOX_F2_0 0x1000 /* function 2, int 0 */ 104296077Sadrian#define BHND_PCI_SBTOPCI_MBOX_F2_1 0x2000 /* function 2, int 1 */ 105296077Sadrian#define BHND_PCI_SBTOPCI_MBOX_F3_0 0x4000 /* function 3, int 0 */ 106296077Sadrian#define BHND_PCI_SBTOPCI_MBOX_F3_1 0x8000 /* function 3, int 1 */ 107296077Sadrian 108296077Sadrian/* BHND_PCI_BCAST_ADDR */ 109296077Sadrian#define BHNC_PCI_BCAST_ADDR_MASK 0xFF /* Broadcast register address */ 110296077Sadrian 111296077Sadrian/* Sonics to PCI translation types */ 112296077Sadrian#define BHND_PCI_SBTOPCI0_MASK 0xfc000000 113296077Sadrian#define BHND_PCI_SBTOPCI1_MASK 0xfc000000 114296077Sadrian#define BHND_PCI_SBTOPCI2_MASK 0xc0000000 115296077Sadrian 116296077Sadrian/* Access type bits (0:1) */ 117296077Sadrian#define BHND_PCI_SBTOPCI_MEM 0 118296077Sadrian#define BHND_PCI_SBTOPCI_IO 1 119296077Sadrian#define BHND_PCI_SBTOPCI_CFG0 2 120296077Sadrian#define BHND_PCI_SBTOPCI_CFG1 3 121296077Sadrian 122296077Sadrian#define BHND_PCI_SBTOPCI_PREF 0x4 /* prefetch enable */ 123296077Sadrian#define BHND_PCI_SBTOPCI_BURST 0x8 /* burst enable */ 124296077Sadrian 125296077Sadrian#define BHND_PCI_SBTOPCI_RC_MASK 0x30 /* read command (>= rev11) */ 126296077Sadrian#define BHND_PCI_SBTOPCI_RC_READ 0x00 /* memory read */ 127296077Sadrian#define BHND_PCI_SBTOPCI_RC_READLINE 0x10 /* memory read line */ 128296077Sadrian#define BHND_PCI_SBTOPCI_RC_READMULTI 0x20 /* memory read multiple */ 129296077Sadrian 130296077Sadrian/* PCI core index in SROM shadow area */ 131296077Sadrian#define BHND_PCI_SRSH_PI_OFFSET 0 /* first word */ 132296077Sadrian#define BHND_PCI_SRSH_PI_MASK 0xf000 /* bit 15:12 */ 133296077Sadrian#define BHND_PCI_SRSH_PI_SHIFT 12 /* bit 15:12 */ 134296077Sadrian 135296077Sadrian 136296077Sadrian 137296077Sadrian/* 138296077Sadrian * PCIe-Gen1 Core Registers 139296077Sadrian */ 140296077Sadrian 141296077Sadrian#define BHND_PCIE_CTL BHND_PCI_CTL /**< PCI core control*/ 142296077Sadrian#define BHND_PCIE_BIST_STATUS 0x00C /**< BIST status */ 143296077Sadrian#define BHND_PCIE_GPIO_SEL 0x010 /**< GPIO select */ 144296077Sadrian#define BHND_PCIE_GPIO_OUT_EN 0x014 /**< GPIO output enable */ 145296077Sadrian#define BHND_PCIE_INTR_STATUS BHND_PCI_INTR_STATUS /**< Interrupt status */ 146296077Sadrian#define BHND_PCIE_INTR_MASK BHND_PCI_INTR_MASK /**< Interrupt mask */ 147296077Sadrian#define BHND_PCIE_SBTOPCI_MBOX BHND_PCI_SBTOPCI_MBOX /**< Sonics to PCI mailbox */ 148296077Sadrian#define BHND_PCIE_SBTOPCI0 BHND_PCI_SBTOPCI0 /**< Sonics to PCI translation 0 */ 149296077Sadrian#define BHND_PCIE_SBTOPCI1 BHND_PCI_SBTOPCI1 /**< Sonics to PCI translation 1 */ 150296077Sadrian#define BHND_PCIE_SBTOPCI2 BHND_PCI_SBTOPCI2 /**< Sonics to PCI translation 2 */ 151296077Sadrian 152296077Sadrian/* indirect pci config space access */ 153296077Sadrian#define BHND_PCIE_CFG_ADDR 0x120 /**< pcie config space address */ 154296077Sadrian#define BHND_PCIE_CFG_DATA 0x124 /**< pcie config space data */ 155296077Sadrian 156296077Sadrian/* mdio register access */ 157296077Sadrian#define BHND_PCIE_MDIO_CTL 0x128 /**< mdio control */ 158296077Sadrian#define BHND_PCIE_MDIO_DATA 0x12C /**< mdio data */ 159296077Sadrian 160296077Sadrian/* indirect protocol phy/dllp/tlp register access */ 161296077Sadrian#define BHND_PCIE_IND_ADDR 0x130 /**< internal protocol register address */ 162296077Sadrian#define BHND_PCIE_IND_DATA 0x134 /**< internal protocol register data */ 163296077Sadrian 164296077Sadrian#define BHND_PCIE_CLKREQEN_CTL 0x138 /**< clkreq rdma control */ 165296077Sadrian#define BHND_PCIE_FUNC0_CFG BHND_PCI_FUNC0_CFG /**< PCI function 0 cfg space */ 166296077Sadrian#define BHND_PCIE_FUNC1_CFG BHND_PCI_FUNC1_CFG /**< PCI function 1 cfg space */ 167296077Sadrian#define BHND_PCIE_FUNC2_CFG BHND_PCI_FUNC2_CFG /**< PCI function 2 cfg space */ 168296077Sadrian#define BHND_PCIE_FUNC3_CFG BHND_PCI_FUNC3_CFG /**< PCI function 3 cfg space */ 169296077Sadrian#define BHND_PCIE_SPROM_SHADOW BHND_PCI_SPROM_SHADOW /**< PCI SPROM shadow */ 170296077Sadrian 171296077Sadrian/* BHND_PCIE_CTL */ 172296077Sadrian#define BHND_PCIE_CTL_RST_OE BHND_PCI_CTL_RST_OE /* When set, drives PCI_RESET out to pin */ 173296077Sadrian#define BHND_PCIE_CTL_RST BHND_PCI_CTL_RST_OE /* Value driven out to pin */ 174296077Sadrian 175296077Sadrian/* BHND_PCI_INTR_STATUS / BHND_PCI_INTR_MASK */ 176296077Sadrian#define BHND_PCIE_INTR_A BHND_PCI_INTR_A /* PCIE INTA message is received */ 177296077Sadrian#define BHND_PCIE_INTR_B BHND_PCI_INTR_B /* PCIE INTB message is received */ 178296077Sadrian#define BHND_PCIE_INTR_FATAL 0x04 /* PCIE INTFATAL message is received */ 179296077Sadrian#define BHND_PCIE_INTR_NFATAL 0x08 /* PCIE INTNONFATAL message is received */ 180296077Sadrian#define BHND_PCIE_INTR_CORR 0x10 /* PCIE INTCORR message is received */ 181296077Sadrian#define BHND_PCIE_INTR_PME 0x20 /* PCIE INTPME message is received */ 182296077Sadrian 183296077Sadrian/* SB to PCIE translation masks */ 184296077Sadrian#define BHND_PCIE_SBTOPCI0_MASK BHND_PCI_SBTOPCI0_MASK 185296077Sadrian#define BHND_PCIE_SBTOPCI1_MASK BHND_PCI_SBTOPCI1_MASK 186296077Sadrian#define BHND_PCIE_SBTOPCI2_MASK BHND_PCI_SBTOPCI2_MASK 187296077Sadrian 188296077Sadrian/* Access type bits (0:1) */ 189296077Sadrian#define BHND_PCIE_SBTOPCI_MEM BHND_PCI_SBTOPCI_MEM 190296077Sadrian#define BHND_PCIE_SBTOPCI_IO BHND_PCI_SBTOPCI_IO 191296077Sadrian#define BHND_PCIE_SBTOPCI_CFG0 BHND_PCI_SBTOPCI_CFG0 192296077Sadrian#define BHND_PCIE_SBTOPCI_CFG1 BHND_PCI_SBTOPCI_CFG1 193296077Sadrian 194296077Sadrian#define BHND_PCIE_SBTOPCI_PREF BHND_PCI_SBTOPCI_PREF /* prefetch enable */ 195296077Sadrian#define BHND_PCIE_SBTOPCI_BURST BHND_PCI_SBTOPCI_BURST /* burst enable */ 196296077Sadrian 197296077Sadrian/* BHND_PCIE_CFG_ADDR / BHND_PCIE_CFG_DATA */ 198296077Sadrian#define BHND_PCIE_CFG_ADDR_FUNC_MASK 0x7000 199296077Sadrian#define BHND_PCIE_CFG_ADDR_FUNC_SHIFT 12 200296077Sadrian#define BHND_PCIE_CFG_ADDR_REG_MASK 0x0FFF 201296077Sadrian#define BHND_PCIE_CFG_ADDR_REG_SHIFT 0 202296077Sadrian 203296077Sadrian#define BHND_PCIE_CFG_OFFSET(f, r) \ 204296077Sadrian ((((f) & BHND_PCIE_CFG_ADDR_FUNC_MASK) << BHND_PCIE_CFG_ADDR_FUNC_SHIFT) | \ 205296077Sadrian (((r) & BHND_PCIE_CFG_ADDR_FUNC_SHIFT) << BHND_PCIE_CFG_ADDR_REG_SHIFT)) 206298479Sadrian 207298479Sadrian/* BHND_PCIE_MDIO_CTL control */ 208298479Sadrian#define BHND_PCIE_MDIOCTL_DIVISOR_MASK 0x7f /* clock divisor mask */ 209298479Sadrian#define BHND_PCIE_MDIOCTL_DIVISOR_VAL 0x2 /* default clock divisor */ 210298479Sadrian#define BHND_PCIE_MDIOCTL_PREAM_EN 0x80 /* enable preamble mode */ 211298479Sadrian#define BHND_PCIE_MDIOCTL_DONE 0x100 /* tranaction completed */ 212296077Sadrian 213298479Sadrian/* PCIe BHND_PCIE_MDIO_DATA Data */ 214298479Sadrian#define BHND_PCIE_MDIODATA_PHYADDR_MASK 0x0f800000 /* phy addr */ 215298479Sadrian#define BHND_PCIE_MDIODATA_PHYADDR_SHIFT 23 216298479Sadrian#define BHND_PCIE_MDIODATA_REGADDR_MASK 0x007c0000 /* reg/dev addr */ 217298479Sadrian#define BHND_PCIE_MDIODATA_REGADDR_SHIFT 18 218298479Sadrian#define BHND_PCIE_MDIODATA_DATA_MASK 0x0000ffff /* data */ 219298479Sadrian 220298479Sadrian#define BHND_PCIE_MDIODATA_TA 0x00020000 /* slave turnaround time */ 221298479Sadrian#define BHND_PCIE_MDIODATA_START 0x40000000 /* start of transaction */ 222298479Sadrian#define BHND_PCIE_MDIODATA_CMD_WRITE 0x10000000 /* write command */ 223298479Sadrian#define BHND_PCIE_MDIODATA_CMD_READ 0x20000000 /* read command */ 224298479Sadrian 225298479Sadrian#define BHND_PCIE_MDIODATA_ADDR(_phyaddr, _regaddr) ( \ 226298479Sadrian (((_phyaddr) << BHND_PCIE_MDIODATA_PHYADDR_SHIFT) & \ 227298479Sadrian BHND_PCIE_MDIODATA_PHYADDR_MASK) | \ 228298479Sadrian (((_regaddr) << BHND_PCIE_MDIODATA_REGADDR_SHIFT) & \ 229298479Sadrian BHND_PCIE_MDIODATA_REGADDR_MASK) \ 230298479Sadrian) 231298479Sadrian 232296077Sadrian/* PCIE protocol PHY diagnostic registers */ 233296077Sadrian#define BHND_PCIE_PLP_MODEREG 0x200 /* Mode */ 234296077Sadrian#define BHND_PCIE_PLP_STATUSREG 0x204 /* Status */ 235296077Sadrian#define BHND_PCIE_PLP_LTSSMCTRLREG 0x208 /* LTSSM control */ 236296077Sadrian#define BHND_PCIE_PLP_LTLINKNUMREG 0x20c /* Link Training Link number */ 237296077Sadrian#define BHND_PCIE_PLP_LTLANENUMREG 0x210 /* Link Training Lane number */ 238296077Sadrian#define BHND_PCIE_PLP_LTNFTSREG 0x214 /* Link Training N_FTS */ 239296077Sadrian#define BHND_PCIE_PLP_ATTNREG 0x218 /* Attention */ 240296077Sadrian#define BHND_PCIE_PLP_ATTNMASKREG 0x21C /* Attention Mask */ 241296077Sadrian#define BHND_PCIE_PLP_RXERRCTR 0x220 /* Rx Error */ 242296077Sadrian#define BHND_PCIE_PLP_RXFRMERRCTR 0x224 /* Rx Framing Error */ 243296077Sadrian#define BHND_PCIE_PLP_RXERRTHRESHREG 0x228 /* Rx Error threshold */ 244296077Sadrian#define BHND_PCIE_PLP_TESTCTRLREG 0x22C /* Test Control reg */ 245296077Sadrian#define BHND_PCIE_PLP_SERDESCTRLOVRDREG 0x230 /* SERDES Control Override */ 246296077Sadrian#define BHND_PCIE_PLP_TIMINGOVRDREG 0x234 /* Timing param override */ 247296077Sadrian#define BHND_PCIE_PLP_RXTXSMDIAGREG 0x238 /* RXTX State Machine Diag */ 248296077Sadrian#define BHND_PCIE_PLP_LTSSMDIAGREG 0x23C /* LTSSM State Machine Diag */ 249296077Sadrian 250296077Sadrian/* PCIE protocol DLLP diagnostic registers */ 251296077Sadrian#define BHND_PCIE_DLLP_LCREG 0x100 /* Link Control */ 252296077Sadrian#define BHND_PCIE_DLLP_LCREG_PCIPM_EN 0x40 /* Enable PCI-PM power management */ 253296077Sadrian#define BHND_PCIE_DLLP_LSREG 0x104 /* Link Status */ 254296077Sadrian#define BHND_PCIE_DLLP_LAREG 0x108 /* Link Attention */ 255296077Sadrian#define BHND_PCIE_DLLP_LAMASKREG 0x10C /* Link Attention Mask */ 256296077Sadrian#define BHND_PCIE_DLLP_NEXTTXSEQNUMREG 0x110 /* Next Tx Seq Num */ 257296077Sadrian#define BHND_PCIE_DLLP_ACKEDTXSEQNUMREG 0x114 /* Acked Tx Seq Num */ 258296077Sadrian#define BHND_PCIE_DLLP_PURGEDTXSEQNUMREG 0x118 /* Purged Tx Seq Num */ 259296077Sadrian#define BHND_PCIE_DLLP_RXSEQNUMREG 0x11C /* Rx Sequence Number */ 260296077Sadrian#define BHND_PCIE_DLLP_LRREG 0x120 /* Link Replay */ 261296077Sadrian#define BHND_PCIE_DLLP_LACKTOREG 0x124 /* Link Ack Timeout */ 262296077Sadrian#define BHND_PCIE_DLLP_PMTHRESHREG 0x128 /* Power Management Threshold */ 263296077Sadrian#define BHND_PCIE_L0THRESHOLDTIME_MASK 0xFF00 /* bits 0 - 7 */ 264296077Sadrian#define BHND_PCIE_L1THRESHOLDTIME_MASK 0xFF00 /* bits 8 - 15 */ 265296077Sadrian#define BHND_PCIE_L1THRESHOLDTIME_SHIFT 8 /* PCIE_L1THRESHOLDTIME_SHIFT */ 266296077Sadrian#define BHND_PCIE_L1THRESHOLD_WARVAL 0x72 /* WAR value */ 267296077Sadrian#define BHND_PCIE_ASPMTIMER_EXTEND 0x1000000 /* > rev7: enable extend ASPM timer */ 268296077Sadrian#define BHND_PCIE_DLLP_RTRYWPREG 0x12C /* Retry buffer write ptr */ 269296077Sadrian#define BHND_PCIE_DLLP_RTRYRPREG 0x130 /* Retry buffer Read ptr */ 270296077Sadrian#define BHND_PCIE_DLLP_RTRYPPREG 0x134 /* Retry buffer Purged ptr */ 271296077Sadrian#define BHND_PCIE_DLLP_RTRRWREG 0x138 /* Retry buffer Read/Write */ 272296077Sadrian#define BHND_PCIE_DLLP_ECTHRESHREG 0x13C /* Error Count Threshold */ 273296077Sadrian#define BHND_PCIE_DLLP_TLPERRCTRREG 0x140 /* TLP Error Counter */ 274296077Sadrian#define BHND_PCIE_DLLP_ERRCTRREG 0x144 /* Error Counter */ 275296077Sadrian#define BHND_PCIE_DLLP_NAKRXCTRREG 0x148 /* NAK Received Counter */ 276296077Sadrian#define BHND_PCIE_DLLP_TESTREG 0x14C /* Test */ 277296077Sadrian#define BHND_PCIE_DLLP_PKTBIST 0x150 /* Packet BIST */ 278296077Sadrian#define BHND_PCIE_DLLP_PCIE11 0x154 /* DLLP PCIE 1.1 reg */ 279296077Sadrian 280296077Sadrian#define BHND_PCIE_DLLP_LSREG_LINKUP (1 << 16) 281296077Sadrian 282296077Sadrian/* PCIE protocol TLP diagnostic registers */ 283296077Sadrian#define BHND_PCIE_TLP_CONFIGREG 0x000 /* Configuration */ 284296077Sadrian#define BHND_PCIE_TLP_WORKAROUNDSREG 0x004 /* TLP Workarounds */ 285296077Sadrian#define BHND_PCIE_TLP_WORKAROUND_URBIT 0x8 /* If enabled, UR status bit is set 286296077Sadrian * on memory access of an unmatched 287296077Sadrian * address */ 288296077Sadrian 289296077Sadrian#define BHND_PCIE_TLP_WRDMAUPPER 0x010 /* Write DMA Upper Address */ 290296077Sadrian#define BHND_PCIE_TLP_WRDMALOWER 0x014 /* Write DMA Lower Address */ 291296077Sadrian#define BHND_PCIE_TLP_WRDMAREQ_LBEREG 0x018 /* Write DMA Len/ByteEn Req */ 292296077Sadrian#define BHND_PCIE_TLP_RDDMAUPPER 0x01C /* Read DMA Upper Address */ 293296077Sadrian#define BHND_PCIE_TLP_RDDMALOWER 0x020 /* Read DMA Lower Address */ 294296077Sadrian#define BHND_PCIE_TLP_RDDMALENREG 0x024 /* Read DMA Len Req */ 295296077Sadrian#define BHND_PCIE_TLP_MSIDMAUPPER 0x028 /* MSI DMA Upper Address */ 296296077Sadrian#define BHND_PCIE_TLP_MSIDMALOWER 0x02C /* MSI DMA Lower Address */ 297296077Sadrian#define BHND_PCIE_TLP_MSIDMALENREG 0x030 /* MSI DMA Len Req */ 298296077Sadrian#define BHND_PCIE_TLP_SLVREQLENREG 0x034 /* Slave Request Len */ 299296077Sadrian#define BHND_PCIE_TLP_FCINPUTSREQ 0x038 /* Flow Control Inputs */ 300296077Sadrian#define BHND_PCIE_TLP_TXSMGRSREQ 0x03C /* Tx StateMachine and Gated Req */ 301296077Sadrian#define BHND_PCIE_TLP_ADRACKCNTARBLEN 0x040 /* Address Ack XferCnt and ARB Len */ 302296077Sadrian#define BHND_PCIE_TLP_DMACPLHDR0 0x044 /* DMA Completion Hdr 0 */ 303296077Sadrian#define BHND_PCIE_TLP_DMACPLHDR1 0x048 /* DMA Completion Hdr 1 */ 304296077Sadrian#define BHND_PCIE_TLP_DMACPLHDR2 0x04C /* DMA Completion Hdr 2 */ 305296077Sadrian#define BHND_PCIE_TLP_DMACPLMISC0 0x050 /* DMA Completion Misc0 */ 306296077Sadrian#define BHND_PCIE_TLP_DMACPLMISC1 0x054 /* DMA Completion Misc1 */ 307296077Sadrian#define BHND_PCIE_TLP_DMACPLMISC2 0x058 /* DMA Completion Misc2 */ 308296077Sadrian#define BHND_PCIE_TLP_SPTCTRLLEN 0x05C /* Split Controller Req len */ 309296077Sadrian#define BHND_PCIE_TLP_SPTCTRLMSIC0 0x060 /* Split Controller Misc 0 */ 310296077Sadrian#define BHND_PCIE_TLP_SPTCTRLMSIC1 0x064 /* Split Controller Misc 1 */ 311296077Sadrian#define BHND_PCIE_TLP_BUSDEVFUNC 0x068 /* Bus/Device/Func */ 312296077Sadrian#define BHND_PCIE_TLP_RESETCTR 0x06C /* Reset Counter */ 313296077Sadrian#define BHND_PCIE_TLP_RTRYBUF 0x070 /* Retry Buffer value */ 314296077Sadrian#define BHND_PCIE_TLP_TGTDEBUG1 0x074 /* Target Debug Reg1 */ 315296077Sadrian#define BHND_PCIE_TLP_TGTDEBUG2 0x078 /* Target Debug Reg2 */ 316296077Sadrian#define BHND_PCIE_TLP_TGTDEBUG3 0x07C /* Target Debug Reg3 */ 317296077Sadrian#define BHND_PCIE_TLP_TGTDEBUG4 0x080 /* Target Debug Reg4 */ 318296077Sadrian 319296077Sadrian 320296077Sadrian/* 321296077Sadrian * PCIe-G1 SerDes MDIO Registers (>= rev10) 322296077Sadrian */ 323296077Sadrian#define BHND_PCIE_PHYADDR_SD 0x0 /* serdes PHY address */ 324296077Sadrian 325296077Sadrian#define BHND_PCIE_SD_ADDREXT 0x1F /* serdes address extension register */ 326296077Sadrian 327296077Sadrian#define BHND_PCIE_SD_REGS_IEEE0 0x0000 /* IEEE0 AN CTRL block */ 328296077Sadrian#define BHND_PCIE_SD_REGS_IEEE1 0x0010 /* IEEE1 AN ADV block */ 329296077Sadrian#define BHND_PCIE_SD_REGS_BLK0 0x8000 /* ??? */ 330296077Sadrian#define BHND_PCIE_SD_REGS_BLK1 0x8010 /* ??? */ 331296077Sadrian#define BHND_PCIE_SD_REGS_BLK2 0x8020 /* ??? */ 332296077Sadrian#define BHND_PCIE_SD_REGS_BLK3 0x8030 /* ??? */ 333296077Sadrian#define BHND_PCIE_SD_REGS_BLK4 0x8040 /* ??? */ 334300015Sadrian#define BHND_PCIE_SD_REGS_PLL 0x8080 /* (?) PLL register block */ 335300015Sadrian#define BHND_PCIE_SD_REGS_TX0 0x8200 /* (?) Transmit 0 block */ 336300015Sadrian#define BHND_PCIE_SD_REGS_SERDESID 0x8310 /* ??? */ 337300015Sadrian#define BHND_PCIE_SD_REGS_RX0 0x8400 /* (?) Receive 0 register block */ 338296077Sadrian 339300015Sadrian/* The interpretation of these registers and values are just guesses based on 340300015Sadrian * the limited available documentation from other (likely similar) Broadcom 341300015Sadrian * SerDes IP. */ 342300015Sadrian#define BHND_PCIE_SD_TX_DRIVER 0x17 /* TX transmit driver register */ 343300015Sadrian#define BHND_PCIE_SD_TX_DRIVER_IFIR_MASK 0x000E /* unconfirmed */ 344300015Sadrian#define BHND_PCIE_SD_TX_DRIVER_IFIR_SHIFT 1 /* unconfirmed */ 345300015Sadrian#define BHND_PCIE_SD_TX_DRIVER_IPRE_MASK 0x00F0 /* unconfirmed */ 346300015Sadrian#define BHND_PCIE_SD_TX_DRIVER_IPRE_SHIFT 4 /* unconfirmed */ 347300015Sadrian#define BHND_PCIE_SD_TX_DRIVER_IDRIVER_MASK 0x0F00 /* unconfirmed */ 348300015Sadrian#define BHND_PCIE_SD_TX_DRIVER_IDRIVER_SHIFT 8 /* unconfirmed */ 349300015Sadrian#define BHND_PCIE_SD_TX_DRIVER_P2_COEFF_SHIFT 12 /* unconfirmed */ 350300015Sadrian#define BHND_PCIE_SD_TX_DRIVER_P2_COEFF_MASK 0xF000 /* unconfirmed */ 351300015Sadrian 352300015Sadrian/* Constants used with host bridge quirk handling */ 353300015Sadrian#define BHND_PCIE_APPLE_TX_P2_COEFF_MAX 0x7 /* 9.6dB pre-emphassis coeff (???) */ 354300015Sadrian#define BHND_PCIE_APPLE_TX_IDRIVER_MAX 0xF /* 1400mV voltage range (???) */ 355300015Sadrian 356300015Sadrian#define BHND_PCIE_APPLE_TX_P2_COEFF_700MV 0x7 /* 2.3dB pre-emphassis coeff (???) */ 357300015Sadrian#define BHND_PCIE_APPLE_TX_IDRIVER_700MV 0x0 /* 670mV voltage range (???) */ 358300015Sadrian 359296077Sadrian/* 360296077Sadrian * PCIe-G1 SerDes-R9 MDIO Registers (<= rev9) 361296077Sadrian * 362296077Sadrian * These register definitions appear to match those provided in the 363296077Sadrian * "PCI Express SerDes Registers" section of the BCM5761 Ethernet Controller 364296077Sadrian * Programmer's Reference Guide. 365296077Sadrian */ 366296077Sadrian#define BHND_PCIE_PHY_SDR9_PLL 0x1C /* SerDes PLL PHY Address*/ 367296077Sadrian#define BHND_PCIE_SDR9_PLL_CTRL 0x17 /* PLL control reg */ 368296077Sadrian#define BHND_PCIE_SDR9_PLL_CTRL_FREQDET_EN 0x4000 /* bit 14 is FREQDET on */ 369296077Sadrian#define BHND_PCIE_PHY_SDR9_TXRX 0x0F /* SerDes RX/TX PHY Address */ 370296077Sadrian 371296077Sadrian#define BHND_PCIE_SDR9_RX_CTRL 0x11 /* RX ctrl register */ 372296077Sadrian#define BHND_PCIE_SDR9_RX_CTRL_FORCE 0x80 /* rxpolarity_force */ 373296077Sadrian#define BHND_PCIE_SDR9_RX_CTRL_POLARITY_INV 0x40 /* rxpolarity_value (if set, inverse polarity) */ 374296077Sadrian 375296077Sadrian#define BHND_PCIE_SDR9_RX_CDR 0x16 /* RX CDR ctrl register */ 376296077Sadrian#define BHND_PCIE_SDR9_RX_CDR_FREQ_OVR_EN 0x0100 /* freq_override_en flag */ 377296077Sadrian#define BHND_PCIE_SDR9_RX_CDR_FREQ_OVR_MASK 0x00FF /* freq_override_val */ 378296077Sadrian#define BHND_PCIE_SDR9_RX_CDR_FREQ_OVR_SHIFT 0 379296077Sadrian 380296077Sadrian#define BHND_PCIE_SDR9_RX_CDRBW 0x17 /* RX CDR bandwidth (PLL tuning) */ 381296077Sadrian#define BHND_PCIE_SDR9_RX_CDRBW_INTGTRK_MASK 0x7000 /* integral loop bandwidth (phase tracking mode) */ 382296077Sadrian#define BHND_PCIE_SDR9_RX_CDRBW_INTGTRK_SHIFT 11 383296077Sadrian#define BHND_PCIE_SDR9_RX_CDRBW_INTGACQ_MASK 0x0700 /* integral loop bandwidth (phase acquisition mode) */ 384296077Sadrian#define BHND_PCIE_SDR9_RX_CDRBW_INTGACQ_SHIFT 8 385296077Sadrian#define BHND_PCIE_SDR9_RX_CDRBW_PROPTRK_MASK 0x0070 /* proportional loop bandwidth (phase tracking mode) */ 386296077Sadrian#define BHND_PCIE_SDR9_RX_CDRBW_PROPTRK_SHIFT 4 387296077Sadrian#define BHND_PCIE_SDR9_RX_CDRBW_PROPACQ_MASK 0x0007 /* proportional loop bandwidth (phase acquisition mode) */ 388296077Sadrian#define BHND_PCIE_SDR9_RX_CDRBW_PROPACQ_SHIFT 0 389296077Sadrian 390296077Sadrian#define BHND_PCIE_SDR9_RX_TIMER1 0x12 /* timer1 register */ 391296077Sadrian#define BHND_PCIE_SDR9_RX_TIMER1_LKTRK_MASK 0xFF00 /* phase tracking delay before asserting RX seq completion (in 16ns units) */ 392296077Sadrian#define BHND_PCIE_SDR9_RX_TIMER1_LKTRK_SHIFT 8 393296077Sadrian#define BHND_PCIE_SDR9_RX_TIMER1_LKACQ_MASK 0x00FF /* phase acquisition mode time (in 1024ns units) */ 394296077Sadrian#define BHND_PCIE_SDR9_RX_TIMER1_LKACQ_SHIFT 0 395296077Sadrian 396296077Sadrian 397296077Sadrian/* SPROM offsets */ 398296077Sadrian#define BHND_PCIE_SRSH_PI_OFFSET BHND_PCI_SRSH_PI_OFFSET /**< PCI core index in SROM shadow area */ 399296077Sadrian#define BHND_PCIE_SRSH_PI_MASK BHND_PCI_SRSH_PI_MASK 400296077Sadrian#define BHND_PCIE_SRSH_PI_SHIFT BHND_PCI_SRSH_PI_SHIFT 401296077Sadrian 402296077Sadrian#define BHND_PCIE_SRSH_ASPM_OFFSET 8 /* word 4 */ 403296077Sadrian#define BHND_PCIE_SRSH_ASPM_ENB 0x18 /* bit 3, 4 */ 404296077Sadrian#define BHND_PCIE_SRSH_ASPM_L1_ENB 0x10 /* bit 4 */ 405296077Sadrian#define BHND_PCIE_SRSH_ASPM_L0s_ENB 0x8 /* bit 3 */ 406296077Sadrian#define BHND_PCIE_SRSH_PCIE_MISC_CONFIG 10 /* word 5 */ 407296077Sadrian#define BHND_PCIE_SRSH_L23READY_EXIT_NOPRST 0x8000 /* bit 15 */ 408300015Sadrian#define BHND_PCIE_SRSH_CLKREQ_OFFSET_R5 40 /* word 20 for srom rev <= 5 */ 409300015Sadrian#define BHND_PCIE_SRSH_CLKREQ_OFFSET_R8 104 /* word 52 for srom rev 8 */ 410296077Sadrian#define BHND_PCIE_SRSH_CLKREQ_ENB 0x0800 /* bit 11 */ 411296077Sadrian#define BHND_PCIE_SRSH_BD_OFFSET 12 /* word 6 */ 412296077Sadrian#define BHND_PCIE_SRSH_AUTOINIT_OFFSET 36 /* auto initialization enable */ 413296077Sadrian 414296077Sadrian/* Status reg PCIE_PLP_STATUSREG */ 415296077Sadrian#define BHND_PCIE_PLP_POLARITY_INV 0x10 /* lane polarity is inverted */ 416296077Sadrian 417296077Sadrian#endif /* _BHND_CORES_PCI_BHND_PCIREG_H_ */ 418