1298479Sadrian/*- 2298479Sadrian * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org> 3298479Sadrian * All rights reserved. 4298479Sadrian * 5298479Sadrian * Redistribution and use in source and binary forms, with or without 6298479Sadrian * modification, are permitted provided that the following conditions 7298479Sadrian * are met: 8298479Sadrian * 1. Redistributions of source code must retain the above copyright 9298479Sadrian * notice, this list of conditions and the following disclaimer, 10298479Sadrian * without modification. 11298479Sadrian * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12298479Sadrian * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13298479Sadrian * redistribution must be conditioned upon including a substantially 14298479Sadrian * similar Disclaimer requirement for further binary redistribution. 15298479Sadrian * 16298479Sadrian * NO WARRANTY 17298479Sadrian * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18298479Sadrian * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19298479Sadrian * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20298479Sadrian * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21298479Sadrian * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22298479Sadrian * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23298479Sadrian * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24298479Sadrian * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25298479Sadrian * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26298479Sadrian * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27298479Sadrian * THE POSSIBILITY OF SUCH DAMAGES. 28298479Sadrian * 29298479Sadrian * $FreeBSD$ 30298479Sadrian */ 31298479Sadrian 32298479Sadrian#ifndef _BHND_CORES_PCI_BHND_PCI_HOSTBVAR_H_ 33298479Sadrian#define _BHND_CORES_PCI_BHND_PCI_HOSTBVAR_H_ 34298479Sadrian 35298479Sadrian/* 36298479Sadrian * PCI/PCIe-Gen1 Host Bridge definitions. 37298479Sadrian */ 38298479Sadrian 39298479Sadrian#include <sys/param.h> 40298479Sadrian#include <sys/bus.h> 41298479Sadrian 42298479Sadrian#include "bhnd_pcivar.h" 43298479Sadrian 44298479SadrianDECLARE_CLASS(bhnd_pci_hostb_driver); 45298479Sadrian 46300015Sadrian/** 47298479Sadrian * PCI/PCIe-Gen1 endpoint-mode device quirks 48298479Sadrian */ 49298479Sadrianenum { 50298479Sadrian /** No quirks */ 51298479Sadrian BHND_PCI_QUIRK_NONE = 0, 52298479Sadrian 53298479Sadrian /** 54298479Sadrian * SBTOPCI_PREF and SBTOPCI_BURST must be set on the 55298479Sadrian * SSB_PCICORE_SBTOPCI2 register. 56298479Sadrian */ 57298479Sadrian BHND_PCI_QUIRK_SBTOPCI2_PREF_BURST = (1<<1), 58298479Sadrian 59298479Sadrian /** 60298479Sadrian * SBTOPCI_RC_READMULTI must be set on the SSB_PCICORE_SBTOPCI2 61298479Sadrian * register. 62298479Sadrian */ 63298479Sadrian BHND_PCI_QUIRK_SBTOPCI2_READMULTI = (1<<2), 64298479Sadrian 65298479Sadrian /** 66298479Sadrian * PCI CLKRUN# should be disabled on attach (via CLKRUN_DSBL). 67298479Sadrian * 68298479Sadrian * The purpose of this work-around is unclear; there is some 69298479Sadrian * documentation regarding earlier Broadcom drivers supporting 70298479Sadrian * a "force CLKRUN#" *enable* registry key for use on mobile 71298479Sadrian * hardware. 72298479Sadrian */ 73298479Sadrian BHND_PCI_QUIRK_CLKRUN_DSBL = (1<<3), 74298479Sadrian 75298479Sadrian /** 76300015Sadrian * On PCI-attached BCM4321CB* boards, the PCI latency timer must be set 77300015Sadrian * to 960ns on initial attach. 78300015Sadrian */ 79300015Sadrian BHND_PCI_QUIRK_960NS_LATTIM_OVR = (1<<4), 80300015Sadrian 81300015Sadrian /** 82298479Sadrian * TLP workaround for unmatched address handling is required. 83298479Sadrian * 84298479Sadrian * This TLP workaround will enable setting of the PCIe UR status bit 85298479Sadrian * on memory access to an unmatched address. 86298479Sadrian */ 87300015Sadrian BHND_PCIE_QUIRK_UR_STATUS_FIX = (1<<5), 88298479Sadrian 89298479Sadrian /** 90298479Sadrian * PCI-PM power management must be explicitly enabled via 91298479Sadrian * the data link control register. 92298479Sadrian */ 93300015Sadrian BHND_PCIE_QUIRK_PCIPM_REQEN = (1<<6), 94298479Sadrian 95298479Sadrian /** 96298479Sadrian * Fix L0s to L0 exit transition on SerDes <= rev9 devices. 97298479Sadrian * 98298479Sadrian * On these devices, PCIe/SerDes symbol lock can be lost if the 99298479Sadrian * reference clock has not fully stabilized during the L0s to L0 100298479Sadrian * exit transition, triggering an internal reset of the chip. 101298479Sadrian * 102298479Sadrian * The SerDes RX CDR phase lock timers and proportional/integral 103298479Sadrian * filters must be tweaked to ensure the CDR has fully stabilized 104298479Sadrian * before asserting receive sequencer completion. 105298479Sadrian */ 106300015Sadrian BHND_PCIE_QUIRK_SDR9_L0s_HANG = (1<<7), 107298479Sadrian 108298479Sadrian /** 109298479Sadrian * The idle time for entering L1 low-power state must be 110298479Sadrian * explicitly set (to 114ns) to fix slow L1->L0 transition issues. 111298479Sadrian */ 112300015Sadrian BHND_PCIE_QUIRK_L1_IDLE_THRESH = (1<<8), 113298479Sadrian 114298479Sadrian /** 115298479Sadrian * The ASPM L1 entry timer should be extended for better performance, 116298479Sadrian * and restored for better power savings. 117298479Sadrian */ 118300015Sadrian BHND_PCIE_QUIRK_L1_TIMER_PERF = (1<<9), 119298479Sadrian 120298479Sadrian /** 121298479Sadrian * ASPM and ECPM settings must be overridden manually. 122300015Sadrian * Applies to 4311B0/4321B1 chipset revisions. 123298479Sadrian * 124298479Sadrian * The override behavior is controlled by the BHND_BFL2_PCIEWAR_OVR 125300015Sadrian * flag; if set, ASPM and CLKREQ should be explicitly disabled. If not 126300015Sadrian * set, they should be explicitly enabled. 127298479Sadrian * 128298479Sadrian * Attach/Resume: 129300015Sadrian * - Update SRSH_ASPM_ENB flag in the SPROM ASPM register. 130300015Sadrian * - Update SRSH_CLKREQ_ENB flag in the SPROM CLKREQ_REV5 131300015Sadrian * register. 132300015Sadrian * - Update ASPM L0S/L1 flags in PCIER_LINK_CTL register. 133300015Sadrian * - Clear CLKREQ (ECPM) flag in PCIER_LINK_CTL register. 134298479Sadrian * 135300015Sadrian * Suspend: 136300015Sadrian * - Clear ASPM L1 flag in the PCIER_LINK_CTL register. 137300015Sadrian * - Set CLKREQ (ECPM) flag in the PCIER_LINK_CTL register. 138300015Sadrian * 139300015Sadrian * Detach: 140300015Sadrian * - Set CLKREQ (ECPM) flag in the PCIER_LINK_CTL register. 141298479Sadrian */ 142300015Sadrian BHND_PCIE_QUIRK_ASPM_OVR = (1<<10), 143299996Sadrian 144298479Sadrian /** 145299996Sadrian * A subset of Apple devices did not set the BHND_BFL2_PCIEWAR_OVR 146299996Sadrian * flag in SPROM; on these devices, the BHND_BFL2_PCIEWAR_OVR flag 147299996Sadrian * should always be treated as if set. 148299996Sadrian */ 149300015Sadrian BHND_PCIE_QUIRK_BFL2_PCIEWAR_EN = (1<<11), 150299996Sadrian 151299996Sadrian /** 152298479Sadrian * Fix SerDes polarity on SerDes <= rev9 devices. 153298479Sadrian * 154298479Sadrian * The SerDes polarity must be saved at device attachment, and 155298479Sadrian * restored on suspend/resume. 156298479Sadrian */ 157300015Sadrian BHND_PCIE_QUIRK_SDR9_POLARITY = (1<<12), 158298479Sadrian 159298479Sadrian /** 160298479Sadrian * SerDes PLL down flag must be manually disabled (by ChipCommon) on 161298479Sadrian * resume. 162298479Sadrian */ 163300015Sadrian BHND_PCIE_QUIRK_SERDES_NOPLLDOWN = (1<<13), 164298479Sadrian 165298479Sadrian /** 166298479Sadrian * On attach and resume, consult the SPROM to determine whether 167298479Sadrian * the L2/L3-Ready w/o PCI RESET work-around must be applied. 168298479Sadrian * 169298479Sadrian * If L23READY_EXIT_NOPRST is not already set in the SPROM, set it 170298479Sadrian */ 171300015Sadrian BHND_PCIE_QUIRK_SPROM_L23_PCI_RESET = (1<<14), 172298479Sadrian 173298479Sadrian /** 174300015Sadrian * The PCIe SerDes PLL must be configured to not retry the startup 175300015Sadrian * sequence upon frequency detection failure on SerDes <= rev9 devices 176298479Sadrian * 177300015Sadrian * The issue this workaround resolves is unknown. 178298479Sadrian */ 179300015Sadrian BHND_PCIE_QUIRK_SDR9_NO_FREQRETRY = (1<<15), 180300015Sadrian 181298479Sadrian /** 182300015Sadrian * Common flag for quirks that require PCIe SerDes TX 183300015Sadrian * drive strength adjustment. 184298479Sadrian * 185300015Sadrian * Only applies to PCIe >= rev10 devices. 186298479Sadrian */ 187300015Sadrian BHND_PCIE_QUIRK_SERDES_TXDRV_ADJUST = (1<<16), 188300015Sadrian 189300015Sadrian /** 190300015Sadrian * On Apple BCM94322X9 devices, the PCIe SerDes TX drive strength 191300015Sadrian * should be set to 700mV. 192300015Sadrian * 193300015Sadrian * The exact issue is unknown, but presumably this workaround 194300015Sadrian * resolves signal integrity issues with these devices. 195300015Sadrian * 196300015Sadrian * Only applies to PCIe >= rev10 devices. 197300015Sadrian */ 198300015Sadrian BHND_PCIE_QUIRK_SERDES_TXDRV_700MV = (1<<17) | 199300015Sadrian BHND_PCIE_QUIRK_SERDES_TXDRV_ADJUST, 200300015Sadrian 201300015Sadrian /** 202300015Sadrian * On some Apple BCM4331-based devices, the PCIe SerDes TX drive 203300015Sadrian * strength should be set to its maximum. 204300015Sadrian * 205300015Sadrian * The exact issue is unknown, but presumably this workaround 206300015Sadrian * resolves signal integrity issues with these devices. 207300015Sadrian */ 208300015Sadrian BHND_PCIE_QUIRK_SERDES_TXDRV_MAX = (1<<18) | 209300015Sadrian BHND_PCIE_QUIRK_SERDES_TXDRV_ADJUST, 210300015Sadrian 211300015Sadrian /** 212300015Sadrian * PCIe cores prior to rev18 do not support an MRRS larger than 213300015Sadrian * 128 bytes. 214300015Sadrian */ 215300015Sadrian BHND_PCIE_QUIRK_MAX_MRRS_128 = (1<<19), 216300015Sadrian 217300015Sadrian /** 218300015Sadrian * The PCIe core should be configured with an MRRS of 512 bytes. 219300015Sadrian */ 220300015Sadrian BHND_PCIE_QUIRK_DEFAULT_MRRS_512 = (1<<20), 221298479Sadrian}; 222298479Sadrian 223298479Sadrian/** 224298479Sadrian * bhnd_pci_hostb driver instance state. 225298479Sadrian */ 226298479Sadrianstruct bhnd_pcihb_softc { 227300015Sadrian struct bhnd_pci_softc common; /**< common bhnd_pci state */ 228300015Sadrian device_t dev; 229300015Sadrian device_t pci_dev; /**< host PCI device */ 230300015Sadrian uint32_t quirks; /**< hostb device quirks */ 231298479Sadrian 232300015Sadrian /** BHND_PCIE_QUIRK_ASPM_OVR state. */ 233300015Sadrian struct { 234300015Sadrian /** 235300015Sadrian * ASPM/CLKREQ override setting. 236300015Sadrian * 237300015Sadrian * If true, ASPM/CLKREQ should be overridden as enabled. 238300015Sadrian * If false, ASPM/CLKREQ should be overridden as disabled. 239300015Sadrian */ 240300015Sadrian bool aspm_en; 241300015Sadrian } aspm_quirk_override; 242300015Sadrian 243298479Sadrian /** BHND_PCIE_QUIRK_SDR9_POLARITY state. */ 244298479Sadrian struct { 245298479Sadrian /** 246298479Sadrian * PCIe SerDes RX polarity. 247298479Sadrian * 248298479Sadrian * Initialized to the PCIe link's RX polarity 249298479Sadrian * at attach time. This is used to restore the 250298479Sadrian * correct polarity on resume */ 251298479Sadrian bool inv; 252298479Sadrian } sdr9_quirk_polarity; 253298479Sadrian}; 254298479Sadrian 255298479Sadrian 256300015Sadrian#endif /* _BHND_CORES_PCI_BHND_PCI_HOSTBVAR_H_ */ 257