chipc_spi.h revision 301409 
1/*-
2 * Copyright (c) 2016 Michael Zhilin <mizhka@gmail.com>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer,
10 *    without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 *    redistribution must be conditioned upon including a substantially
14 *    similar Disclaimer requirement for further binary redistribution.
15 *
16 * NO WARRANTY
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 * THE POSSIBILITY OF SUCH DAMAGES.
28 */
29
30/*
31 * $FreeBSD: head/sys/dev/bhnd/cores/chipc/chipc_spi.h 301409 2016-06-04 19:39:05Z landonf $
32 */
33
34#ifndef _BHND_CORES_CHIPC_CHIPC_SPI_H_
35#define	_BHND_CORES_CHIPC_CHIPC_SPI_H_
36
37#define	CHIPC_SPI_MAXTRIES	1000
38
39#define	CHIPC_SPI_ACTION_INPUT	1
40#define	CHIPC_SPI_ACTION_OUTPUT	2
41
42#define	CHIPC_SPI_FLASHCTL			0x00
43#define		CHIPC_SPI_FLASHCTL_OPCODE	0x000000ff
44#define		CHIPC_SPI_FLASHCTL_ACTION	0x00000700 //
45/*
46 * We don't use action at all. Experimentaly found, that
47 *  action 0 - read current MISO byte to data register (interactive mode)
48 *  action 1 = read 2nd byte to data register
49 *  action 2 = read 4th byte to data register (surprise! see action 6)
50 *  action 3 = read 5th byte to data register
51 *  action 4 = read bytes 5-8 to data register in swapped order
52 *  action 5 = read bytes 9-12 to data register in swapped order
53 *  action 6 = read 3rd byte to data register
54 *  action 7 = read bytes 6-9 to data register in swapped order
55 * It may be wrong if CS bit is 1.
56 * If CS bit is 1, you should write cmd / data to opcode byte-to-byte.
57 */
58#define		CHIPC_SPI_FLASHCTL_CSACTIVE	0x00001000
59#define		CHIPC_SPI_FLASHCTL_START	0x80000000 //same as BUSY
60#define		CHIPC_SPI_FLASHCTL_BUSY		0x80000000 //same as BUSY
61#define	CHIPC_SPI_FLASHADDR			0x04
62#define	CHIPC_SPI_FLASHDATA			0x08
63
64struct chipc_spi_softc {
65	device_t		 dev;
66
67	/* SPI registers */
68	struct resource		*sc_mem_res;
69
70	/* MMIO flash */
71	struct resource		*sc_res;
72};
73
74/* register space access macros */
75#define	SPI_BARRIER_WRITE(sc)	bus_barrier((sc)->sc_mem_res, 0, 0, 	\
76				    BUS_SPACE_BARRIER_WRITE)
77#define	SPI_BARRIER_READ(sc)	bus_barrier((sc)->sc_mem_res, 0, 0, 	\
78				    BUS_SPACE_BARRIER_READ)
79#define	SPI_BARRIER_RW(sc)	bus_barrier((sc)->sc_mem_res, 0, 0, 	\
80			            BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE)
81
82#define SPI_WRITE(sc, reg, val) do {					\
83		bus_write_4(sc->sc_mem_res, (reg), (val));		\
84	} while (0)
85
86#define	SPI_READ(sc, reg)	bus_read_4(sc->sc_mem_res, (reg))
87
88#define	SPI_SET_BITS(sc, reg, bits)					\
89	SPI_WRITE(sc, reg, SPI_READ(sc, (reg)) | (bits))
90
91#define	SPI_CLEAR_BITS(sc, reg, bits)					\
92	SPI_WRITE(sc, reg, SPI_READ(sc, (reg)) & ~(bits))
93
94#endif /* _BHND_CORES_CHIPC_CHIPC_SPI_H_ */
95