if_bfereg.h revision 175787
11592Srgrimes/*- 21592Srgrimes * Copyright (c) 2003 Stuart Walsh 31592Srgrimes * 41592Srgrimes * Redistribution and use in source and binary forms, with or without 51592Srgrimes * modification, are permitted provided that the following conditions 61592Srgrimes * are met: 71592Srgrimes * 1. Redistributions of source code must retain the above copyright 81592Srgrimes * notice, this list of conditions and the following disclaimer. 91592Srgrimes * 2. Redistributions in binary form must reproduce the above copyright 101592Srgrimes * notice, this list of conditions and the following disclaimer in the 111592Srgrimes * documentation and/or other materials provided with the distribution. 121592Srgrimes * 131592Srgrimes * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND 141592Srgrimes * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 151592Srgrimes * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 161592Srgrimes * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 171592Srgrimes * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 181592Srgrimes * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 191592Srgrimes * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 201592Srgrimes * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 211592Srgrimes * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 221592Srgrimes * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 231592Srgrimes * SUCH DAMAGE. 241592Srgrimes */ 251592Srgrimes/* $FreeBSD: head/sys/dev/bfe/if_bfereg.h 175787 2008-01-29 02:15:11Z yongari $ */ 261592Srgrimes 271592Srgrimes#ifndef _BFE_H 281592Srgrimes#define _BFE_H 291592Srgrimes 301592Srgrimes/* PCI registers */ 311592Srgrimes#define BFE_PCI_MEMLO 0x10 3218471Swosch#define BFE_PCI_MEMHIGH 0x14 3324193Simp#define BFE_PCI_INTLINE 0x3C 341592Srgrimes 351592Srgrimes/* Register layout. */ 361592Srgrimes#define BFE_DEVCTRL 0x00000000 /* Device Control */ 371592Srgrimes#define BFE_PFE 0x00000080 /* Pattern Filtering Enable */ 381592Srgrimes#define BFE_IPP 0x00000400 /* Internal EPHY Present */ 391592Srgrimes#define BFE_EPR 0x00008000 /* EPHY Reset */ 401592Srgrimes#define BFE_PME 0x00001000 /* PHY Mode Enable */ 411592Srgrimes#define BFE_PMCE 0x00002000 /* PHY Mode Clocks Enable */ 421592Srgrimes#define BFE_PADDR 0x0007c000 /* PHY Address */ 431592Srgrimes#define BFE_PADDR_SHIFT 18 441592Srgrimes 451592Srgrimes#define BFE_BIST_STAT 0x0000000C /* Built-In Self-Test Status */ 461592Srgrimes#define BFE_WKUP_LEN 0x00000010 /* Wakeup Length */ 471592Srgrimes 481592Srgrimes#define BFE_ISTAT 0x00000020 /* Interrupt Status */ 491592Srgrimes#define BFE_ISTAT_PME 0x00000040 /* Power Management Event */ 501592Srgrimes#define BFE_ISTAT_TO 0x00000080 /* General Purpose Timeout */ 511592Srgrimes#define BFE_ISTAT_DSCE 0x00000400 /* Descriptor Error */ 521592Srgrimes#define BFE_ISTAT_DATAE 0x00000800 /* Data Error */ 531592Srgrimes#define BFE_ISTAT_DPE 0x00001000 /* Descr. Protocol Error */ 541592Srgrimes#define BFE_ISTAT_RDU 0x00002000 /* Receive Descr. Underflow */ 551592Srgrimes#define BFE_ISTAT_RFO 0x00004000 /* Receive FIFO Overflow */ 561592Srgrimes#define BFE_ISTAT_TFU 0x00008000 /* Transmit FIFO Underflow */ 5718458Simp#define BFE_ISTAT_RX 0x00010000 /* RX Interrupt */ 581592Srgrimes#define BFE_ISTAT_TX 0x01000000 /* TX Interrupt */ 591592Srgrimes#define BFE_ISTAT_EMAC 0x04000000 /* EMAC Interrupt */ 601592Srgrimes#define BFE_ISTAT_MII_WRITE 0x08000000 /* MII Write Interrupt */ 611592Srgrimes#define BFE_ISTAT_MII_READ 0x10000000 /* MII Read Interrupt */ 621592Srgrimes#define BFE_ISTAT_ERRORS (BFE_ISTAT_DSCE | BFE_ISTAT_DATAE | BFE_ISTAT_DPE |\ 631592Srgrimes BFE_ISTAT_RDU | BFE_ISTAT_RFO | BFE_ISTAT_TFU) 641592Srgrimes 651592Srgrimes#define BFE_IMASK 0x00000024 /* Interrupt Mask */ 661592Srgrimes#define BFE_IMASK_DEF (BFE_ISTAT_ERRORS | BFE_ISTAT_TO | BFE_ISTAT_RX | \ 671592Srgrimes BFE_ISTAT_TX) 681592Srgrimes 691592Srgrimes#define BFE_MAC_CTRL 0x000000A8 /* MAC Control */ 701592Srgrimes#define BFE_CTRL_CRC32_ENAB 0x00000001 /* CRC32 Generation Enable */ 711592Srgrimes#define BFE_CTRL_PDOWN 0x00000004 /* Onchip EPHY Powerdown */ 721592Srgrimes#define BFE_CTRL_EDET 0x00000008 /* Onchip EPHY Energy Detected */ 731592Srgrimes#define BFE_CTRL_LED 0x000000e0 /* Onchip EPHY LED Control */ 7418458Simp#define BFE_CTRL_LED_SHIFT 5 751592Srgrimes 761592Srgrimes#define BFE_MAC_FLOW 0x000000AC /* MAC Flow Control */ 771592Srgrimes#define BFE_FLOW_RX_HIWAT 0x000000ff /* Onchip FIFO HI Water Mark */ 781592Srgrimes#define BFE_FLOW_PAUSE_ENAB 0x00008000 /* Enable Pause Frame Generation */ 791592Srgrimes 801592Srgrimes#define BFE_RCV_LAZY 0x00000100 /* Lazy Interrupt Control */ 811592Srgrimes#define BFE_LAZY_TO_MASK 0x00ffffff /* Timeout */ 821592Srgrimes#define BFE_LAZY_FC_MASK 0xff000000 /* Frame Count */ 831592Srgrimes#define BFE_LAZY_FC_SHIFT 24 841592Srgrimes 851592Srgrimes#define BFE_DMATX_CTRL 0x00000200 /* DMA TX Control */ 861592Srgrimes#define BFE_TX_CTRL_ENABLE 0x00000001 /* Enable */ 871592Srgrimes#define BFE_TX_CTRL_SUSPEND 0x00000002 /* Suepend Request */ 881592Srgrimes#define BFE_TX_CTRL_LPBACK 0x00000004 /* Loopback Enable */ 891592Srgrimes#define BFE_TX_CTRL_FAIRPRI 0x00000008 /* Fair Priority */ 901592Srgrimes#define BFE_TX_CTRL_FLUSH 0x00000010 /* Flush Request */ 911592Srgrimes 921592Srgrimes#define BFE_DMATX_ADDR 0x00000204 /* DMA TX Descriptor Ring Address */ 931592Srgrimes#define BFE_DMATX_PTR 0x00000208 /* DMA TX Last Posted Descriptor */ 941592Srgrimes#define BFE_DMATX_STAT 0x0000020C /* DMA TX Current Active Desc. + Status */ 951592Srgrimes#define BFE_STAT_CDMASK 0x00000fff /* Current Descriptor Mask */ 961592Srgrimes#define BFE_STAT_SMASK 0x0000f000 /* State Mask */ 971592Srgrimes#define BFE_STAT_DISABLE 0x00000000 /* State Disabled */ 981592Srgrimes#define BFE_STAT_SACTIVE 0x00001000 /* State Active */ 991592Srgrimes#define BFE_STAT_SIDLE 0x00002000 /* State Idle Wait */ 1001592Srgrimes#define BFE_STAT_STOPPED 0x00003000 /* State Stopped */ 1011592Srgrimes#define BFE_STAT_SSUSP 0x00004000 /* State Suspend Pending */ 1021592Srgrimes#define BFE_STAT_EMASK 0x000f0000 /* Error Mask */ 1031592Srgrimes#define BFE_STAT_ENONE 0x00000000 /* Error None */ 1041592Srgrimes#define BFE_STAT_EDPE 0x00010000 /* Error Desc. Protocol Error */ 1051592Srgrimes#define BFE_STAT_EDFU 0x00020000 /* Error Data FIFO Underrun */ 1061592Srgrimes#define BFE_STAT_EBEBR 0x00030000 /* Error Bus Error on Buffer Read */ 1071592Srgrimes#define BFE_STAT_EBEDA 0x00040000 /* Error Bus Error on Desc. Access */ 1081592Srgrimes#define BFE_STAT_FLUSHED 0x00100000 /* Flushed */ 1091592Srgrimes 1101592Srgrimes#define BFE_DMARX_CTRL 0x00000210 /* DMA RX Control */ 1111592Srgrimes#define BFE_RX_CTRL_ENABLE 0x00000001 /* Enable */ 1121592Srgrimes#define BFE_RX_CTRL_ROMASK 0x000000fe /* Receive Offset Mask */ 1131592Srgrimes#define BFE_RX_CTRL_ROSHIFT 1 /* Receive Offset Shift */ 1141592Srgrimes 1151592Srgrimes#define BFE_DMARX_ADDR 0x00000214 /* DMA RX Descriptor Ring Address */ 1161592Srgrimes#define BFE_DMARX_PTR 0x00000218 /* DMA RX Last Posted Descriptor */ 1171592Srgrimes#define BFE_DMARX_STAT 0x0000021C /* DMA RX Current Active Desc. + Status */ 1181592Srgrimes 1191592Srgrimes#define BFE_RXCONF 0x00000400 /* EMAC RX Config */ 12018458Simp#define BFE_RXCONF_DBCAST 0x00000001 /* Disable Broadcast */ 12118458Simp#define BFE_RXCONF_ALLMULTI 0x00000002 /* Accept All Multicast */ 1221592Srgrimes#define BFE_RXCONF_NORXTX 0x00000004 /* Receive Disable While Transmitting */ 1231592Srgrimes#define BFE_RXCONF_PROMISC 0x00000008 /* Promiscuous Enable */ 12418458Simp#define BFE_RXCONF_LPBACK 0x00000010 /* Loopback Enable */ 1251592Srgrimes#define BFE_RXCONF_FLOW 0x00000020 /* Flow Control Enable */ 1261592Srgrimes#define BFE_RXCONF_ACCEPT 0x00000040 /* Accept Unicast Flow Control Frame */ 1271592Srgrimes#define BFE_RXCONF_RFILT 0x00000080 /* Reject Filter */ 1281592Srgrimes 1291592Srgrimes#define BFE_RXMAXLEN 0x00000404 /* EMAC RX Max Packet Length */ 1301592Srgrimes#define BFE_TXMAXLEN 0x00000408 /* EMAC TX Max Packet Length */ 1311592Srgrimes 13218458Simp#define BFE_MDIO_CTRL 0x00000410 /* EMAC MDIO Control */ 13318458Simp#define BFE_MDIO_MAXF_MASK 0x0000007f /* MDC Frequency */ 13418458Simp#define BFE_MDIO_PREAMBLE 0x00000080 /* MII Preamble Enable */ 1351592Srgrimes 1361592Srgrimes#define BFE_MDIO_DATA 0x00000414 /* EMAC MDIO Data */ 1371592Srgrimes#define BFE_MDIO_DATA_DATA 0x0000ffff /* R/W Data */ 1381592Srgrimes#define BFE_MDIO_TA_MASK 0x00030000 /* Turnaround Value */ 1391592Srgrimes#define BFE_MDIO_TA_SHIFT 16 1401592Srgrimes#define BFE_MDIO_TA_VALID 2 1411592Srgrimes 1421592Srgrimes#define BFE_MDIO_RA_MASK 0x007c0000 /* Register Address */ 1431592Srgrimes#define BFE_MDIO_PMD_MASK 0x0f800000 /* Physical Media Device */ 1441592Srgrimes#define BFE_MDIO_OP_MASK 0x30000000 /* Opcode */ 1451592Srgrimes#define BFE_MDIO_SB_MASK 0xc0000000 /* Start Bits */ 1461592Srgrimes#define BFE_MDIO_SB_START 0x40000000 /* Start Of Frame */ 1471592Srgrimes#define BFE_MDIO_RA_SHIFT 18 1481592Srgrimes#define BFE_MDIO_PMD_SHIFT 23 1491592Srgrimes#define BFE_MDIO_OP_SHIFT 28 1501592Srgrimes#define BFE_MDIO_OP_WRITE 1 1511592Srgrimes#define BFE_MDIO_OP_READ 2 15218458Simp#define BFE_MDIO_SB_SHIFT 30 15318458Simp 15418458Simp#define BFE_EMAC_IMASK 0x00000418 /* EMAC Interrupt Mask */ 15518458Simp#define BFE_EMAC_ISTAT 0x0000041C /* EMAC Interrupt Status */ 1561592Srgrimes#define BFE_EMAC_INT_MII 0x00000001 /* MII MDIO Interrupt */ 1571592Srgrimes#define BFE_EMAC_INT_MIB 0x00000002 /* MIB Interrupt */ 1581592Srgrimes#define BFE_EMAC_INT_FLOW 0x00000003 /* Flow Control Interrupt */ 1591592Srgrimes 1601592Srgrimes#define BFE_CAM_DATA_LO 0x00000420 /* EMAC CAM Data Low */ 1611592Srgrimes#define BFE_CAM_DATA_HI 0x00000424 /* EMAC CAM Data High */ 1621592Srgrimes#define BFE_CAM_HI_VALID 0x00010000 /* Valid Bit */ 1631592Srgrimes 1641592Srgrimes#define BFE_CAM_CTRL 0x00000428 /* EMAC CAM Control */ 1651592Srgrimes#define BFE_CAM_ENABLE 0x00000001 /* CAM Enable */ 1661592Srgrimes#define BFE_CAM_MSEL 0x00000002 /* Mask Select */ 1671592Srgrimes#define BFE_CAM_READ 0x00000004 /* Read */ 1681592Srgrimes#define BFE_CAM_WRITE 0x00000008 /* Read */ 1691592Srgrimes#define BFE_CAM_INDEX_MASK 0x003f0000 /* Index Mask */ 1701592Srgrimes#define BFE_CAM_BUSY 0x80000000 /* CAM Busy */ 1711592Srgrimes#define BFE_CAM_INDEX_SHIFT 16 1721592Srgrimes 1731592Srgrimes#define BFE_ENET_CTRL 0x0000042C /* EMAC ENET Control */ 1741592Srgrimes#define BFE_ENET_ENABLE 0x00000001 /* EMAC Enable */ 1751592Srgrimes#define BFE_ENET_DISABLE 0x00000002 /* EMAC Disable */ 1761592Srgrimes#define BFE_ENET_SRST 0x00000004 /* EMAC Soft Reset */ 1771592Srgrimes#define BFE_ENET_EPSEL 0x00000008 /* External PHY Select */ 1781592Srgrimes 1791592Srgrimes#define BFE_TX_CTRL 0x00000430 /* EMAC TX Control */ 1801592Srgrimes#define BFE_TX_DUPLEX 0x00000001 /* Full Duplex */ 1811592Srgrimes#define BFE_TX_FMODE 0x00000002 /* Flow Mode */ 1821592Srgrimes#define BFE_TX_SBENAB 0x00000004 /* Single Backoff Enable */ 1831592Srgrimes#define BFE_TX_SMALL_SLOT 0x00000008 /* Small Slottime */ 1841592Srgrimes 1851592Srgrimes#define BFE_TX_WMARK 0x00000434 /* EMAC TX Watermark */ 1861592Srgrimes 1871592Srgrimes#define BFE_MIB_CTRL 0x00000438 /* EMAC MIB Control */ 1881592Srgrimes#define BFE_MIB_CLR_ON_READ 0x00000001 /* Autoclear on Read */ 1891592Srgrimes 1901592Srgrimes/* Status registers */ 1911592Srgrimes#define BFE_TX_GOOD_O 0x00000500 /* MIB TX Good Octets */ 1921592Srgrimes#define BFE_TX_GOOD_P 0x00000504 /* MIB TX Good Packets */ 1931592Srgrimes#define BFE_TX_O 0x00000508 /* MIB TX Octets */ 1941592Srgrimes#define BFE_TX_P 0x0000050C /* MIB TX Packets */ 1951592Srgrimes#define BFE_TX_BCAST 0x00000510 /* MIB TX Broadcast Packets */ 1961592Srgrimes#define BFE_TX_MCAST 0x00000514 /* MIB TX Multicast Packets */ 1971592Srgrimes#define BFE_TX_64 0x00000518 /* MIB TX <= 64 byte Packets */ 1981592Srgrimes#define BFE_TX_65_127 0x0000051C /* MIB TX 65 to 127 byte Packets */ 1991592Srgrimes#define BFE_TX_128_255 0x00000520 /* MIB TX 128 to 255 byte Packets */ 2001592Srgrimes#define BFE_TX_256_511 0x00000524 /* MIB TX 256 to 511 byte Packets */ 2011592Srgrimes#define BFE_TX_512_1023 0x00000528 /* MIB TX 512 to 1023 byte Packets */ 2021592Srgrimes#define BFE_TX_1024_MAX 0x0000052C /* MIB TX 1024 to max byte Packets */ 2031592Srgrimes#define BFE_TX_JABBER 0x00000530 /* MIB TX Jabber Packets */ 2041592Srgrimes#define BFE_TX_OSIZE 0x00000534 /* MIB TX Oversize Packets */ 2051592Srgrimes#define BFE_TX_FRAG 0x00000538 /* MIB TX Fragment Packets */ 2061592Srgrimes#define BFE_TX_URUNS 0x0000053C /* MIB TX Underruns */ 2071592Srgrimes#define BFE_TX_TCOLS 0x00000540 /* MIB TX Total Collisions */ 2081592Srgrimes#define BFE_TX_SCOLS 0x00000544 /* MIB TX Single Collisions */ 2091592Srgrimes#define BFE_TX_MCOLS 0x00000548 /* MIB TX Multiple Collisions */ 2101592Srgrimes#define BFE_TX_ECOLS 0x0000054C /* MIB TX Excessive Collisions */ 2111592Srgrimes#define BFE_TX_LCOLS 0x00000550 /* MIB TX Late Collisions */ 2121592Srgrimes#define BFE_TX_DEFERED 0x00000554 /* MIB TX Defered Packets */ 2131592Srgrimes#define BFE_TX_CLOST 0x00000558 /* MIB TX Carrier Lost */ 2141592Srgrimes#define BFE_TX_PAUSE 0x0000055C /* MIB TX Pause Packets */ 2151592Srgrimes#define BFE_RX_GOOD_O 0x00000580 /* MIB RX Good Octets */ 2161592Srgrimes#define BFE_RX_GOOD_P 0x00000584 /* MIB RX Good Packets */ 2171592Srgrimes#define BFE_RX_O 0x00000588 /* MIB RX Octets */ 2181592Srgrimes#define BFE_RX_P 0x0000058C /* MIB RX Packets */ 21918458Simp#define BFE_RX_BCAST 0x00000590 /* MIB RX Broadcast Packets */ 22018458Simp#define BFE_RX_MCAST 0x00000594 /* MIB RX Multicast Packets */ 22118458Simp#define BFE_RX_64 0x00000598 /* MIB RX <= 64 byte Packets */ 22218458Simp#define BFE_RX_65_127 0x0000059C /* MIB RX 65 to 127 byte Packets */ 22318458Simp#define BFE_RX_128_255 0x000005A0 /* MIB RX 128 to 255 byte Packets */ 22418458Simp#define BFE_RX_256_511 0x000005A4 /* MIB RX 256 to 511 byte Packets */ 22518458Simp#define BFE_RX_512_1023 0x000005A8 /* MIB RX 512 to 1023 byte Packets */ 22618458Simp#define BFE_RX_1024_MAX 0x000005AC /* MIB RX 1024 to max byte Packets */ 22718458Simp#define BFE_RX_JABBER 0x000005B0 /* MIB RX Jabber Packets */ 22818458Simp#define BFE_RX_OSIZE 0x000005B4 /* MIB RX Oversize Packets */ 22918458Simp#define BFE_RX_FRAG 0x000005B8 /* MIB RX Fragment Packets */ 23018458Simp#define BFE_RX_MISS 0x000005BC /* MIB RX Missed Packets */ 23118458Simp#define BFE_RX_CRCA 0x000005C0 /* MIB RX CRC Align Errors */ 23218458Simp#define BFE_RX_USIZE 0x000005C4 /* MIB RX Undersize Packets */ 23318458Simp#define BFE_RX_CRC 0x000005C8 /* MIB RX CRC Errors */ 23418458Simp#define BFE_RX_ALIGN 0x000005CC /* MIB RX Align Errors */ 23518458Simp#define BFE_RX_SYM 0x000005D0 /* MIB RX Symbol Errors */ 23618458Simp#define BFE_RX_PAUSE 0x000005D4 /* MIB RX Pause Packets */ 23718458Simp#define BFE_RX_NPAUSE 0x000005D8 /* MIB RX Non-Pause Packets */ 23818458Simp 2391592Srgrimes#define BFE_SBIMSTATE 0x00000F90 /* BFE_SB Initiator Agent State */ 2401592Srgrimes#define BFE_PC 0x0000000f /* Pipe Count */ 2411592Srgrimes#define BFE_AP_MASK 0x00000030 /* Arbitration Priority */ 2421592Srgrimes#define BFE_AP_BOTH 0x00000000 /* Use both timeslices and token */ 2431592Srgrimes#define BFE_AP_TS 0x00000010 /* Use timeslices only */ 2441592Srgrimes#define BFE_AP_TK 0x00000020 /* Use token only */ 2451592Srgrimes#define BFE_AP_RSV 0x00000030 /* Reserved */ 2461592Srgrimes#define BFE_IBE 0x00020000 /* In Band Error */ 2471592Srgrimes#define BFE_TO 0x00040000 /* Timeout */ 2481592Srgrimes 2491592Srgrimes 2501592Srgrimes/* Seems the bcm440x has a fairly generic core, we only need be concerned with 2511592Srgrimes * a couple of these 2521592Srgrimes */ 2531592Srgrimes#define BFE_SBINTVEC 0x00000F94 /* BFE_SB Interrupt Mask */ 2541592Srgrimes#define BFE_INTVEC_PCI 0x00000001 /* Enable interrupts for PCI */ 2551592Srgrimes#define BFE_INTVEC_ENET0 0x00000002 /* Enable interrupts for enet 0 */ 2561592Srgrimes#define BFE_INTVEC_ILINE20 0x00000004 /* Enable interrupts for iline20 */ 2571592Srgrimes#define BFE_INTVEC_CODEC 0x00000008 /* Enable interrupts for v90 codec */ 2581592Srgrimes#define BFE_INTVEC_USB 0x00000010 /* Enable interrupts for usb */ 2591592Srgrimes#define BFE_INTVEC_EXTIF 0x00000020 /* Enable interrupts for external i/f */ 2601592Srgrimes#define BFE_INTVEC_ENET1 0x00000040 /* Enable interrupts for enet 1 */ 2611592Srgrimes 2621592Srgrimes#define BFE_SBTMSLOW 0x00000F98 /* BFE_SB Target State Low */ 2631592Srgrimes#define BFE_RESET 0x00000001 /* Reset */ 2641592Srgrimes#define BFE_REJECT 0x00000002 /* Reject */ 2651592Srgrimes#define BFE_CLOCK 0x00010000 /* Clock Enable */ 2661592Srgrimes#define BFE_FGC 0x00020000 /* Force Gated Clocks On */ 2671592Srgrimes#define BFE_PE 0x40000000 /* Power Management Enable */ 2681592Srgrimes#define BFE_BE 0x80000000 /* BIST Enable */ 2691592Srgrimes 2701592Srgrimes#define BFE_SBTMSHIGH 0x00000F9C /* BFE_SB Target State High */ 2711592Srgrimes#define BFE_SERR 0x00000001 /* S-error */ 2721592Srgrimes#define BFE_INT 0x00000002 /* Interrupt */ 2731592Srgrimes#define BFE_BUSY 0x00000004 /* Busy */ 2741592Srgrimes#define BFE_GCR 0x20000000 /* Gated Clock Request */ 2751592Srgrimes#define BFE_BISTF 0x40000000 /* BIST Failed */ 2761592Srgrimes#define BFE_BISTD 0x80000000 /* BIST Done */ 2771592Srgrimes 2781592Srgrimes#define BFE_SBBWA0 0x00000FA0 /* BFE_SB Bandwidth Allocation Table 0 */ 2791592Srgrimes#define BFE_TAB0_MASK 0x0000ffff /* Lookup Table 0 */ 2801592Srgrimes#define BFE_TAB1_MASK 0xffff0000 /* Lookup Table 0 */ 2811592Srgrimes#define BFE_TAB0_SHIFT 0 2821592Srgrimes#define BFE_TAB1_SHIFT 16 2831592Srgrimes 2841592Srgrimes#define BFE_SBIMCFGLOW 0x00000FA8 /* BFE_SB Initiator Configuration Low */ 2851592Srgrimes#define BFE_STO_MASK 0x00000003 /* Service Timeout */ 2861592Srgrimes#define BFE_RTO_MASK 0x00000030 /* Request Timeout */ 2871592Srgrimes#define BFE_CID_MASK 0x00ff0000 /* Connection ID */ 2881592Srgrimes#define BFE_RTO_SHIFT 4 2891592Srgrimes#define BFE_CID_SHIFT 16 2901592Srgrimes 2911592Srgrimes#define BFE_SBIMCFGHIGH 0x00000FAC /* BFE_SB Initiator Configuration High */ 2921592Srgrimes#define BFE_IEM_MASK 0x0000000c /* Inband Error Mode */ 2931592Srgrimes#define BFE_TEM_MASK 0x00000030 /* Timeout Error Mode */ 2941592Srgrimes#define BFE_BEM_MASK 0x000000c0 /* Bus Error Mode */ 2951592Srgrimes#define BFE_TEM_SHIFT 4 2961592Srgrimes#define BFE_BEM_SHIFT 6 2971592Srgrimes 2981592Srgrimes#define BFE_SBTMCFGLOW 0x00000FB8 /* BFE_SB Target Configuration Low */ 2991592Srgrimes#define BFE_LOW_CD_MASK 0x000000ff /* Clock Divide Mask */ 3001592Srgrimes#define BFE_LOW_CO_MASK 0x0000f800 /* Clock Offset Mask */ 3011592Srgrimes#define BFE_LOW_IF_MASK 0x00fc0000 /* Interrupt Flags Mask */ 3021592Srgrimes#define BFE_LOW_IM_MASK 0x03000000 /* Interrupt Mode Mask */ 3031592Srgrimes#define BFE_LOW_CO_SHIFT 11 3041592Srgrimes#define BFE_LOW_IF_SHIFT 18 3051592Srgrimes#define BFE_LOW_IM_SHIFT 24 3061592Srgrimes 3071592Srgrimes#define BFE_SBTMCFGHIGH 0x00000FBC /* BFE_SB Target Configuration High */ 3081592Srgrimes#define BFE_HIGH_BM_MASK 0x00000003 /* Busy Mode */ 3091592Srgrimes#define BFE_HIGH_RM_MASK 0x0000000C /* Retry Mode */ 3101592Srgrimes#define BFE_HIGH_SM_MASK 0x00000030 /* Stop Mode */ 3111592Srgrimes#define BFE_HIGH_EM_MASK 0x00000300 /* Error Mode */ 3121592Srgrimes#define BFE_HIGH_IM_MASK 0x00000c00 /* Interrupt Mode */ 3131592Srgrimes#define BFE_HIGH_RM_SHIFT 2 3141592Srgrimes#define BFE_HIGH_SM_SHIFT 4 3151592Srgrimes#define BFE_HIGH_EM_SHIFT 8 3161592Srgrimes#define BFE_HIGH_IM_SHIFT 10 3171592Srgrimes 3181592Srgrimes#define BFE_SBBCFG 0x00000FC0 /* BFE_SB Broadcast Configuration */ 3191592Srgrimes#define BFE_LAT_MASK 0x00000003 /* BFE_SB Latency */ 3201592Srgrimes#define BFE_MAX0_MASK 0x000f0000 /* MAX Counter 0 */ 3211592Srgrimes#define BFE_MAX1_MASK 0x00f00000 /* MAX Counter 1 */ 3221592Srgrimes#define BFE_MAX0_SHIFT 16 3231592Srgrimes#define BFE_MAX1_SHIFT 20 3241592Srgrimes 3251592Srgrimes#define BFE_SBBSTATE 0x00000FC8 /* BFE_SB Broadcast State */ 3261592Srgrimes#define BFE_SBBSTATE_SRD 0x00000001 /* ST Reg Disable */ 3271592Srgrimes#define BFE_SBBSTATE_HRD 0x00000002 /* Hold Reg Disable */ 3281592Srgrimes 3291592Srgrimes#define BFE_SBACTCNFG 0x00000FD8 /* BFE_SB Activate Configuration */ 3301592Srgrimes#define BFE_SBFLAGST 0x00000FE8 /* BFE_SB Current BFE_SBFLAGS */ 3311592Srgrimes 3321592Srgrimes#define BFE_SBIDLOW 0x00000FF8 /* BFE_SB Identification Low */ 3331592Srgrimes#define BFE_CS_MASK 0x00000003 /* Config Space Mask */ 3341592Srgrimes#define BFE_AR_MASK 0x00000038 /* Num Address Ranges Supported */ 3351592Srgrimes#define BFE_SYNCH 0x00000040 /* Sync */ 3361592Srgrimes#define BFE_INIT 0x00000080 /* Initiator */ 3371592Srgrimes#define BFE_MINLAT_MASK 0x00000f00 /* Minimum Backplane Latency */ 3381592Srgrimes#define BFE_MAXLAT_MASK 0x0000f000 /* Maximum Backplane Latency */ 3391592Srgrimes#define BFE_FIRST 0x00010000 /* This Initiator is First */ 3401592Srgrimes#define BFE_CW_MASK 0x000c0000 /* Cycle Counter Width */ 3411592Srgrimes#define BFE_TP_MASK 0x00f00000 /* Target Ports */ 3421592Srgrimes#define BFE_IP_MASK 0x0f000000 /* Initiator Ports */ 3431592Srgrimes#define BFE_AR_SHIFT 3 3441592Srgrimes#define BFE_MINLAT_SHIFT 8 3451592Srgrimes#define BFE_MAXLAT_SHIFT 12 3461592Srgrimes#define BFE_CW_SHIFT 18 3471592Srgrimes#define BFE_TP_SHIFT 20 3481592Srgrimes#define BFE_IP_SHIFT 24 3491592Srgrimes 3501592Srgrimes#define BFE_SBIDHIGH 0x00000FFC /* BFE_SB Identification High */ 3511592Srgrimes#define BFE_RC_MASK 0x0000000f /* Revision Code */ 3521592Srgrimes#define BFE_CC_MASK 0x0000fff0 /* Core Code */ 3531592Srgrimes#define BFE_VC_MASK 0xffff0000 /* Vendor Code */ 3541592Srgrimes#define BFE_CC_SHIFT 4 3551592Srgrimes#define BFE_VC_SHIFT 16 3561592Srgrimes 3571592Srgrimes#define BFE_CORE_ILINE20 0x801 3581592Srgrimes#define BFE_CORE_SDRAM 0x803 3591592Srgrimes#define BFE_CORE_PCI 0x804 3601592Srgrimes#define BFE_CORE_MIPS 0x805 3611592Srgrimes#define BFE_CORE_ENET 0x806 3621592Srgrimes#define BFE_CORE_CODEC 0x807 3631592Srgrimes#define BFE_CORE_USB 0x808 3641592Srgrimes#define BFE_CORE_ILINE100 0x80a 3651592Srgrimes#define BFE_CORE_EXTIF 0x811 3661592Srgrimes 3671592Srgrimes/* SSB PCI config space registers. */ 3681592Srgrimes#define BFE_BAR0_WIN 0x80 3691592Srgrimes#define BFE_BAR1_WIN 0x84 3701592Srgrimes#define BFE_SPROM_CONTROL 0x88 3711592Srgrimes#define BFE_BAR1_CONTROL 0x8c 3721592Srgrimes 3731592Srgrimes/* SSB core and hsot control registers. */ 3741592Srgrimes#define BFE_SSB_CONTROL 0x00000000 3751592Srgrimes#define BFE_SSB_ARBCONTROL 0x00000010 3761592Srgrimes#define BFE_SSB_ISTAT 0x00000020 3771592Srgrimes#define BFE_SSB_IMASK 0x00000024 3781592Srgrimes#define BFE_SSB_MBOX 0x00000028 3791592Srgrimes#define BFE_SSB_BCAST_ADDR 0x00000050 3801592Srgrimes#define BFE_SSB_BCAST_DATA 0x00000054 3811592Srgrimes#define BFE_SSB_PCI_TRANS_0 0x00000100 3821592Srgrimes#define BFE_SSB_PCI_TRANS_1 0x00000104 3831592Srgrimes#define BFE_SSB_PCI_TRANS_2 0x00000108 3841592Srgrimes#define BFE_SSB_SPROM 0x00000800 3851592Srgrimes 3861592Srgrimes#define BFE_SSB_PCI_MEM 0x00000000 3871592Srgrimes#define BFE_SSB_PCI_IO 0x00000001 3881592Srgrimes#define BFE_SSB_PCI_CFG0 0x00000002 3891592Srgrimes#define BFE_SSB_PCI_CFG1 0x00000003 3901592Srgrimes#define BFE_SSB_PCI_PREF 0x00000004 3911592Srgrimes#define BFE_SSB_PCI_BURST 0x00000008 3921592Srgrimes#define BFE_SSB_PCI_MASK0 0xfc000000 3931592Srgrimes#define BFE_SSB_PCI_MASK1 0xfc000000 3941592Srgrimes#define BFE_SSB_PCI_MASK2 0xc0000000 3951592Srgrimes 3961592Srgrimes#define BFE_DESC_LEN 0x00001fff 3971592Srgrimes#define BFE_DESC_CMASK 0x0ff00000 /* Core specific bits */ 3981592Srgrimes#define BFE_DESC_EOT 0x10000000 /* End of Table */ 3991592Srgrimes#define BFE_DESC_IOC 0x20000000 /* Interrupt On Completion */ 4001592Srgrimes#define BFE_DESC_EOF 0x40000000 /* End of Frame */ 4011592Srgrimes#define BFE_DESC_SOF 0x80000000 /* Start of Frame */ 4021592Srgrimes 4031592Srgrimes#define BFE_RX_CP_THRESHOLD 256 4041592Srgrimes#define BFE_RX_HEADER_LEN 28 4051592Srgrimes 4061592Srgrimes#define BFE_RX_FLAG_OFIFO 0x00000001 /* FIFO Overflow */ 4071592Srgrimes#define BFE_RX_FLAG_CRCERR 0x00000002 /* CRC Error */ 4081592Srgrimes#define BFE_RX_FLAG_SERR 0x00000004 /* Receive Symbol Error */ 4091592Srgrimes#define BFE_RX_FLAG_ODD 0x00000008 /* Frame has odd number of nibbles */ 4101592Srgrimes#define BFE_RX_FLAG_LARGE 0x00000010 /* Frame is > RX MAX Length */ 4116750Sjkh#define BFE_RX_FLAG_MCAST 0x00000020 /* Dest is Multicast Address */ 4121592Srgrimes#define BFE_RX_FLAG_BCAST 0x00000040 /* Dest is Broadcast Address */ 4131592Srgrimes#define BFE_RX_FLAG_MISS 0x00000080 /* Received due to promisc mode */ 4141592Srgrimes#define BFE_RX_FLAG_LAST 0x00000800 /* Last buffer in frame */ 4156750Sjkh#define BFE_RX_FLAG_ERRORS (BFE_RX_FLAG_ODD | BFE_RX_FLAG_SERR | \ 4161592Srgrimes BFE_RX_FLAG_CRCERR | BFE_RX_FLAG_OFIFO) 4171592Srgrimes 4181592Srgrimes#define BFE_MCAST_TBL_SIZE 32 4191592Srgrimes#define BFE_PCI_DMA 0x40000000 4201592Srgrimes#define BFE_REG_PCI 0x18002000 4211592Srgrimes 4221592Srgrimes#define BCOM_VENDORID 0x14E4 4231592Srgrimes#define BCOM_DEVICEID_BCM4401 0x4401 4241592Srgrimes#define BCOM_DEVICEID_BCM4401B0 0x170c 42524193Simp 42624193Simp#define PCI_SETBIT(dev, reg, x, s) \ 4271592Srgrimes pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | (x)), s) 4281592Srgrimes#define PCI_CLRBIT(dev, reg, x, s) \ 4291592Srgrimes pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s) 4301592Srgrimes 4311592Srgrimes#define BFE_RX_RING_SIZE 512 4321592Srgrimes#define BFE_TX_RING_SIZE 512 4331592Srgrimes#define BFE_LINK_DOWN 5 4341592Srgrimes#define BFE_TX_LIST_CNT 128 4351592Srgrimes#define BFE_RX_LIST_CNT 128 4361592Srgrimes#define BFE_TX_LIST_SIZE BFE_TX_LIST_CNT * sizeof(struct bfe_desc) 4371592Srgrimes#define BFE_RX_LIST_SIZE BFE_RX_LIST_CNT * sizeof(struct bfe_desc) 4381592Srgrimes#define BFE_RX_OFFSET 30 43920052Sjoerg#define BFE_TX_QLEN 256 4401592Srgrimes 4411592Srgrimes#define CSR_READ_4(sc, reg) \ 4421592Srgrimes bus_space_read_4(sc->bfe_btag, sc->bfe_bhandle, reg) 4431592Srgrimes 4441592Srgrimes#define CSR_WRITE_4(sc, reg, val) \ 4451592Srgrimes bus_space_write_4(sc->bfe_btag, sc->bfe_bhandle, reg, val) 4461592Srgrimes 4471592Srgrimes#define BFE_OR(sc, name, val) \ 4481592Srgrimes CSR_WRITE_4(sc, name, CSR_READ_4(sc, name) | val) 4491592Srgrimes 4501592Srgrimes#define BFE_AND(sc, name, val) \ 4511592Srgrimes CSR_WRITE_4(sc, name, CSR_READ_4(sc, name) & val) 4521592Srgrimes 4531592Srgrimes#define BFE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->bfe_mtx, MA_OWNED) 4541592Srgrimes#define BFE_LOCK(_sc) mtx_lock(&(_sc)->bfe_mtx) 4551592Srgrimes#define BFE_UNLOCK(_sc) mtx_unlock(&(_sc)->bfe_mtx) 4561592Srgrimes 4571592Srgrimes#define BFE_INC(x, y) (x) = ((x) == ((y)-1)) ? 0 : (x)+1 4581592Srgrimes 4591592Srgrimesstruct bfe_data { 4601592Srgrimes struct mbuf *bfe_mbuf; 4611592Srgrimes bus_dmamap_t bfe_map; 4621592Srgrimes}; 4631592Srgrimes 4641592Srgrimesstruct bfe_desc { 4651592Srgrimes u_int32_t bfe_ctrl; 4661592Srgrimes u_int32_t bfe_addr; 4671592Srgrimes}; 4681592Srgrimes 4691592Srgrimesstruct bfe_rxheader { 4701592Srgrimes u_int16_t len; 4711592Srgrimes u_int16_t flags; 4721592Srgrimes u_int16_t pad[12]; 4731592Srgrimes}; 4741592Srgrimes 4751592Srgrimesstruct bfe_hw_stats { 4761592Srgrimes u_int32_t tx_good_octets, tx_good_pkts, tx_octets; 4771592Srgrimes u_int32_t tx_pkts, tx_broadcast_pkts, tx_multicast_pkts; 4781592Srgrimes u_int32_t tx_len_64, tx_len_65_to_127, tx_len_128_to_255; 4791592Srgrimes u_int32_t tx_len_256_to_511, tx_len_512_to_1023, tx_len_1024_to_max; 4801592Srgrimes u_int32_t tx_jabber_pkts, tx_oversize_pkts, tx_fragment_pkts; 4811592Srgrimes u_int32_t tx_underruns, tx_total_cols, tx_single_cols; 4821592Srgrimes u_int32_t tx_multiple_cols, tx_excessive_cols, tx_late_cols; 4831592Srgrimes u_int32_t tx_defered, tx_carrier_lost, tx_pause_pkts; 4841592Srgrimes u_int32_t __pad1[8]; 4851592Srgrimes 4861592Srgrimes u_int32_t rx_good_octets, rx_good_pkts, rx_octets; 4871592Srgrimes u_int32_t rx_pkts, rx_broadcast_pkts, rx_multicast_pkts; 4881592Srgrimes u_int32_t rx_len_64, rx_len_65_to_127, rx_len_128_to_255; 4891592Srgrimes u_int32_t rx_len_256_to_511, rx_len_512_to_1023, rx_len_1024_to_max; 4901592Srgrimes u_int32_t rx_jabber_pkts, rx_oversize_pkts, rx_fragment_pkts; 4911592Srgrimes u_int32_t rx_missed_pkts, rx_crc_align_errs, rx_undersize; 4921592Srgrimes u_int32_t rx_crc_errs, rx_align_errs, rx_symbol_errs; 4931592Srgrimes u_int32_t rx_pause_pkts, rx_nonpause_pkts; 4941592Srgrimes}; 4951592Srgrimes 4961592Srgrimesstruct bfe_softc 4971592Srgrimes{ 4981592Srgrimes struct ifnet *bfe_ifp; /* interface info */ 4991592Srgrimes device_t bfe_dev; 5001592Srgrimes device_t bfe_miibus; 5011592Srgrimes bus_space_handle_t bfe_bhandle; 5021592Srgrimes vm_offset_t bfe_vhandle; 5031592Srgrimes bus_space_tag_t bfe_btag; 5041592Srgrimes bus_dma_tag_t bfe_tag; 5051592Srgrimes bus_dma_tag_t bfe_parent_tag; 5061592Srgrimes bus_dma_tag_t bfe_tx_tag, bfe_rx_tag; 5071592Srgrimes bus_dmamap_t bfe_tx_map, bfe_rx_map; 5081592Srgrimes void *bfe_intrhand; 5091592Srgrimes struct resource *bfe_irq; 5101592Srgrimes struct resource *bfe_res; 5111592Srgrimes struct callout bfe_stat_co; 5121592Srgrimes struct bfe_hw_stats bfe_hwstats; 5131592Srgrimes struct bfe_desc *bfe_tx_list, *bfe_rx_list; 5141592Srgrimes struct bfe_data bfe_tx_ring[BFE_TX_LIST_CNT]; /* XXX */ 5151592Srgrimes struct bfe_data bfe_rx_ring[BFE_RX_LIST_CNT]; /* XXX */ 5161592Srgrimes struct mtx bfe_mtx; 5171592Srgrimes u_int32_t bfe_flags; 5181592Srgrimes u_int32_t bfe_imask; 5191592Srgrimes u_int32_t bfe_dma_offset; 5201592Srgrimes u_int32_t bfe_tx_cnt, bfe_tx_cons, bfe_tx_prod; 5211592Srgrimes u_int32_t bfe_rx_cnt, bfe_rx_prod, bfe_rx_cons; 5221592Srgrimes u_int32_t bfe_tx_dma, bfe_rx_dma; 5231592Srgrimes u_int32_t bfe_link; 5241592Srgrimes int bfe_watchdog_timer; 5251592Srgrimes u_int8_t bfe_phyaddr; /* Address of the card's PHY */ 5261592Srgrimes u_int8_t bfe_mdc_port; 5271592Srgrimes u_int8_t bfe_unit; /* interface number */ 5281592Srgrimes u_int8_t bfe_core_unit; 5291592Srgrimes u_int8_t bfe_up; 5301592Srgrimes u_char bfe_enaddr[6]; 5311592Srgrimes int bfe_if_flags; 5321592Srgrimes char *bfe_vpd_prodname; 5331592Srgrimes char *bfe_vpd_readonly; 5341592Srgrimes}; 5351592Srgrimes 5361592Srgrimesstruct bfe_type 5371592Srgrimes{ 5381592Srgrimes u_int16_t bfe_vid; 5391592Srgrimes u_int16_t bfe_did; 5401592Srgrimes char *bfe_name; 5411592Srgrimes}; 5421592Srgrimes 5431592Srgrimes#endif /* _BFE_H */ 5441592Srgrimes