if_bfereg.h revision 159015
1139749Simp/*- 2139749Simp * Copyright (c) 2003 Stuart Walsh 3139749Simp * 4127827Swes * Redistribution and use in source and binary forms, with or without 5127827Swes * modification, are permitted provided that the following conditions 6127827Swes * are met: 7127827Swes * 1. Redistributions of source code must retain the above copyright 8127827Swes * notice, this list of conditions and the following disclaimer. 9127827Swes * 2. Redistributions in binary form must reproduce the above copyright 10127827Swes * notice, this list of conditions and the following disclaimer in the 11127827Swes * documentation and/or other materials provided with the distribution. 12127827Swes * 13127827Swes * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND 14127827Swes * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15127827Swes * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16127827Swes * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17127827Swes * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18127827Swes * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19127827Swes * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20127827Swes * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21127827Swes * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22127827Swes * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23127827Swes * SUCH DAMAGE. 24127827Swes */ 25119917Swpaul/* $FreeBSD: head/sys/dev/bfe/if_bfereg.h 159015 2006-05-28 18:44:39Z silby $ */ 26119917Swpaul 27119917Swpaul#ifndef _BFE_H 28119917Swpaul#define _BFE_H 29119917Swpaul 30119917Swpaul/* PCI registers */ 31119917Swpaul#define BFE_PCI_MEMLO 0x10 32119917Swpaul#define BFE_PCI_MEMHIGH 0x14 33119917Swpaul#define BFE_PCI_INTLINE 0x3C 34119917Swpaul 35119917Swpaul/* Register layout. */ 36119917Swpaul#define BFE_DEVCTRL 0x00000000 /* Device Control */ 37119917Swpaul#define BFE_PFE 0x00000080 /* Pattern Filtering Enable */ 38119917Swpaul#define BFE_IPP 0x00000400 /* Internal EPHY Present */ 39119917Swpaul#define BFE_EPR 0x00008000 /* EPHY Reset */ 40119917Swpaul#define BFE_PME 0x00001000 /* PHY Mode Enable */ 41119917Swpaul#define BFE_PMCE 0x00002000 /* PHY Mode Clocks Enable */ 42119917Swpaul#define BFE_PADDR 0x0007c000 /* PHY Address */ 43119917Swpaul#define BFE_PADDR_SHIFT 18 44119917Swpaul 45119917Swpaul#define BFE_BIST_STAT 0x0000000C /* Built-In Self-Test Status */ 46119917Swpaul#define BFE_WKUP_LEN 0x00000010 /* Wakeup Length */ 47119917Swpaul 48119917Swpaul#define BFE_ISTAT 0x00000020 /* Interrupt Status */ 49119917Swpaul#define BFE_ISTAT_PME 0x00000040 /* Power Management Event */ 50119917Swpaul#define BFE_ISTAT_TO 0x00000080 /* General Purpose Timeout */ 51119917Swpaul#define BFE_ISTAT_DSCE 0x00000400 /* Descriptor Error */ 52119917Swpaul#define BFE_ISTAT_DATAE 0x00000800 /* Data Error */ 53119917Swpaul#define BFE_ISTAT_DPE 0x00001000 /* Descr. Protocol Error */ 54119917Swpaul#define BFE_ISTAT_RDU 0x00002000 /* Receive Descr. Underflow */ 55119917Swpaul#define BFE_ISTAT_RFO 0x00004000 /* Receive FIFO Overflow */ 56119917Swpaul#define BFE_ISTAT_TFU 0x00008000 /* Transmit FIFO Underflow */ 57119917Swpaul#define BFE_ISTAT_RX 0x00010000 /* RX Interrupt */ 58119917Swpaul#define BFE_ISTAT_TX 0x01000000 /* TX Interrupt */ 59119917Swpaul#define BFE_ISTAT_EMAC 0x04000000 /* EMAC Interrupt */ 60119917Swpaul#define BFE_ISTAT_MII_WRITE 0x08000000 /* MII Write Interrupt */ 61119917Swpaul#define BFE_ISTAT_MII_READ 0x10000000 /* MII Read Interrupt */ 62119917Swpaul#define BFE_ISTAT_ERRORS (BFE_ISTAT_DSCE | BFE_ISTAT_DATAE | BFE_ISTAT_DPE |\ 63133282Sdes BFE_ISTAT_RDU | BFE_ISTAT_RFO | BFE_ISTAT_TFU) 64119917Swpaul 65119917Swpaul#define BFE_IMASK 0x00000024 /* Interrupt Mask */ 66119917Swpaul#define BFE_IMASK_DEF (BFE_ISTAT_ERRORS | BFE_ISTAT_TO | BFE_ISTAT_RX | \ 67133282Sdes BFE_ISTAT_TX) 68119917Swpaul 69119917Swpaul#define BFE_MAC_CTRL 0x000000A8 /* MAC Control */ 70119917Swpaul#define BFE_CTRL_CRC32_ENAB 0x00000001 /* CRC32 Generation Enable */ 71119917Swpaul#define BFE_CTRL_PDOWN 0x00000004 /* Onchip EPHY Powerdown */ 72119917Swpaul#define BFE_CTRL_EDET 0x00000008 /* Onchip EPHY Energy Detected */ 73119917Swpaul#define BFE_CTRL_LED 0x000000e0 /* Onchip EPHY LED Control */ 74119917Swpaul#define BFE_CTRL_LED_SHIFT 5 75119917Swpaul 76119917Swpaul#define BFE_RCV_LAZY 0x00000100 /* Lazy Interrupt Control */ 77119917Swpaul#define BFE_LAZY_TO_MASK 0x00ffffff /* Timeout */ 78119917Swpaul#define BFE_LAZY_FC_MASK 0xff000000 /* Frame Count */ 79119917Swpaul#define BFE_LAZY_FC_SHIFT 24 80119917Swpaul 81119917Swpaul#define BFE_DMATX_CTRL 0x00000200 /* DMA TX Control */ 82119917Swpaul#define BFE_TX_CTRL_ENABLE 0x00000001 /* Enable */ 83119917Swpaul#define BFE_TX_CTRL_SUSPEND 0x00000002 /* Suepend Request */ 84119917Swpaul#define BFE_TX_CTRL_LPBACK 0x00000004 /* Loopback Enable */ 85119917Swpaul#define BFE_TX_CTRL_FAIRPRI 0x00000008 /* Fair Priority */ 86119917Swpaul#define BFE_TX_CTRL_FLUSH 0x00000010 /* Flush Request */ 87119917Swpaul 88119917Swpaul#define BFE_DMATX_ADDR 0x00000204 /* DMA TX Descriptor Ring Address */ 89119917Swpaul#define BFE_DMATX_PTR 0x00000208 /* DMA TX Last Posted Descriptor */ 90119917Swpaul#define BFE_DMATX_STAT 0x0000020C /* DMA TX Current Active Desc. + Status */ 91119917Swpaul#define BFE_STAT_CDMASK 0x00000fff /* Current Descriptor Mask */ 92119917Swpaul#define BFE_STAT_SMASK 0x0000f000 /* State Mask */ 93119917Swpaul#define BFE_STAT_DISABLE 0x00000000 /* State Disabled */ 94119917Swpaul#define BFE_STAT_SACTIVE 0x00001000 /* State Active */ 95119917Swpaul#define BFE_STAT_SIDLE 0x00002000 /* State Idle Wait */ 96119917Swpaul#define BFE_STAT_STOPPED 0x00003000 /* State Stopped */ 97119917Swpaul#define BFE_STAT_SSUSP 0x00004000 /* State Suspend Pending */ 98119917Swpaul#define BFE_STAT_EMASK 0x000f0000 /* Error Mask */ 99119917Swpaul#define BFE_STAT_ENONE 0x00000000 /* Error None */ 100119917Swpaul#define BFE_STAT_EDPE 0x00010000 /* Error Desc. Protocol Error */ 101119917Swpaul#define BFE_STAT_EDFU 0x00020000 /* Error Data FIFO Underrun */ 102119917Swpaul#define BFE_STAT_EBEBR 0x00030000 /* Error Bus Error on Buffer Read */ 103119917Swpaul#define BFE_STAT_EBEDA 0x00040000 /* Error Bus Error on Desc. Access */ 104119917Swpaul#define BFE_STAT_FLUSHED 0x00100000 /* Flushed */ 105119917Swpaul 106119917Swpaul#define BFE_DMARX_CTRL 0x00000210 /* DMA RX Control */ 107119917Swpaul#define BFE_RX_CTRL_ENABLE 0x00000001 /* Enable */ 108119917Swpaul#define BFE_RX_CTRL_ROMASK 0x000000fe /* Receive Offset Mask */ 109119917Swpaul#define BFE_RX_CTRL_ROSHIFT 1 /* Receive Offset Shift */ 110119917Swpaul 111119917Swpaul#define BFE_DMARX_ADDR 0x00000214 /* DMA RX Descriptor Ring Address */ 112119917Swpaul#define BFE_DMARX_PTR 0x00000218 /* DMA RX Last Posted Descriptor */ 113119917Swpaul#define BFE_DMARX_STAT 0x0000021C /* DMA RX Current Active Desc. + Status */ 114119917Swpaul 115119917Swpaul#define BFE_RXCONF 0x00000400 /* EMAC RX Config */ 116119917Swpaul#define BFE_RXCONF_DBCAST 0x00000001 /* Disable Broadcast */ 117119917Swpaul#define BFE_RXCONF_ALLMULTI 0x00000002 /* Accept All Multicast */ 118119917Swpaul#define BFE_RXCONF_NORXTX 0x00000004 /* Receive Disable While Transmitting */ 119119917Swpaul#define BFE_RXCONF_PROMISC 0x00000008 /* Promiscuous Enable */ 120119917Swpaul#define BFE_RXCONF_LPBACK 0x00000010 /* Loopback Enable */ 121119917Swpaul#define BFE_RXCONF_FLOW 0x00000020 /* Flow Control Enable */ 122119917Swpaul#define BFE_RXCONF_ACCEPT 0x00000040 /* Accept Unicast Flow Control Frame */ 123119917Swpaul#define BFE_RXCONF_RFILT 0x00000080 /* Reject Filter */ 124119917Swpaul 125119917Swpaul#define BFE_RXMAXLEN 0x00000404 /* EMAC RX Max Packet Length */ 126119917Swpaul#define BFE_TXMAXLEN 0x00000408 /* EMAC TX Max Packet Length */ 127119917Swpaul 128119917Swpaul#define BFE_MDIO_CTRL 0x00000410 /* EMAC MDIO Control */ 129119917Swpaul#define BFE_MDIO_MAXF_MASK 0x0000007f /* MDC Frequency */ 130119917Swpaul#define BFE_MDIO_PREAMBLE 0x00000080 /* MII Preamble Enable */ 131119917Swpaul 132119917Swpaul#define BFE_MDIO_DATA 0x00000414 /* EMAC MDIO Data */ 133119917Swpaul#define BFE_MDIO_DATA_DATA 0x0000ffff /* R/W Data */ 134119917Swpaul#define BFE_MDIO_TA_MASK 0x00030000 /* Turnaround Value */ 135119917Swpaul#define BFE_MDIO_TA_SHIFT 16 136119917Swpaul#define BFE_MDIO_TA_VALID 2 137119917Swpaul 138119917Swpaul#define BFE_MDIO_RA_MASK 0x007c0000 /* Register Address */ 139119917Swpaul#define BFE_MDIO_PMD_MASK 0x0f800000 /* Physical Media Device */ 140119917Swpaul#define BFE_MDIO_OP_MASK 0x30000000 /* Opcode */ 141119917Swpaul#define BFE_MDIO_SB_MASK 0xc0000000 /* Start Bits */ 142119917Swpaul#define BFE_MDIO_SB_START 0x40000000 /* Start Of Frame */ 143119917Swpaul#define BFE_MDIO_RA_SHIFT 18 144119917Swpaul#define BFE_MDIO_PMD_SHIFT 23 145119917Swpaul#define BFE_MDIO_OP_SHIFT 28 146119917Swpaul#define BFE_MDIO_OP_WRITE 1 147119917Swpaul#define BFE_MDIO_OP_READ 2 148119917Swpaul#define BFE_MDIO_SB_SHIFT 30 149119917Swpaul 150119917Swpaul#define BFE_EMAC_IMASK 0x00000418 /* EMAC Interrupt Mask */ 151119917Swpaul#define BFE_EMAC_ISTAT 0x0000041C /* EMAC Interrupt Status */ 152119917Swpaul#define BFE_EMAC_INT_MII 0x00000001 /* MII MDIO Interrupt */ 153119917Swpaul#define BFE_EMAC_INT_MIB 0x00000002 /* MIB Interrupt */ 154119917Swpaul#define BFE_EMAC_INT_FLOW 0x00000003 /* Flow Control Interrupt */ 155119917Swpaul 156119917Swpaul#define BFE_CAM_DATA_LO 0x00000420 /* EMAC CAM Data Low */ 157119917Swpaul#define BFE_CAM_DATA_HI 0x00000424 /* EMAC CAM Data High */ 158119917Swpaul#define BFE_CAM_HI_VALID 0x00010000 /* Valid Bit */ 159119917Swpaul 160119917Swpaul#define BFE_CAM_CTRL 0x00000428 /* EMAC CAM Control */ 161119917Swpaul#define BFE_CAM_ENABLE 0x00000001 /* CAM Enable */ 162119917Swpaul#define BFE_CAM_MSEL 0x00000002 /* Mask Select */ 163119917Swpaul#define BFE_CAM_READ 0x00000004 /* Read */ 164119917Swpaul#define BFE_CAM_WRITE 0x00000008 /* Read */ 165119917Swpaul#define BFE_CAM_INDEX_MASK 0x003f0000 /* Index Mask */ 166119917Swpaul#define BFE_CAM_BUSY 0x80000000 /* CAM Busy */ 167119917Swpaul#define BFE_CAM_INDEX_SHIFT 16 168119917Swpaul 169119917Swpaul#define BFE_ENET_CTRL 0x0000042C /* EMAC ENET Control */ 170119917Swpaul#define BFE_ENET_ENABLE 0x00000001 /* EMAC Enable */ 171119917Swpaul#define BFE_ENET_DISABLE 0x00000002 /* EMAC Disable */ 172119917Swpaul#define BFE_ENET_SRST 0x00000004 /* EMAC Soft Reset */ 173119917Swpaul#define BFE_ENET_EPSEL 0x00000008 /* External PHY Select */ 174119917Swpaul 175119917Swpaul#define BFE_TX_CTRL 0x00000430 /* EMAC TX Control */ 176119917Swpaul#define BFE_TX_DUPLEX 0x00000001 /* Full Duplex */ 177119917Swpaul#define BFE_TX_FMODE 0x00000002 /* Flow Mode */ 178119917Swpaul#define BFE_TX_SBENAB 0x00000004 /* Single Backoff Enable */ 179119917Swpaul#define BFE_TX_SMALL_SLOT 0x00000008 /* Small Slottime */ 180119917Swpaul 181119917Swpaul#define BFE_TX_WMARK 0x00000434 /* EMAC TX Watermark */ 182119917Swpaul 183119917Swpaul#define BFE_MIB_CTRL 0x00000438 /* EMAC MIB Control */ 184119917Swpaul#define BFE_MIB_CLR_ON_READ 0x00000001 /* Autoclear on Read */ 185119917Swpaul 186119917Swpaul/* Status registers */ 187119917Swpaul#define BFE_TX_GOOD_O 0x00000500 /* MIB TX Good Octets */ 188119917Swpaul#define BFE_TX_GOOD_P 0x00000504 /* MIB TX Good Packets */ 189119917Swpaul#define BFE_TX_O 0x00000508 /* MIB TX Octets */ 190119917Swpaul#define BFE_TX_P 0x0000050C /* MIB TX Packets */ 191119917Swpaul#define BFE_TX_BCAST 0x00000510 /* MIB TX Broadcast Packets */ 192119917Swpaul#define BFE_TX_MCAST 0x00000514 /* MIB TX Multicast Packets */ 193119917Swpaul#define BFE_TX_64 0x00000518 /* MIB TX <= 64 byte Packets */ 194119917Swpaul#define BFE_TX_65_127 0x0000051C /* MIB TX 65 to 127 byte Packets */ 195119917Swpaul#define BFE_TX_128_255 0x00000520 /* MIB TX 128 to 255 byte Packets */ 196119917Swpaul#define BFE_TX_256_511 0x00000524 /* MIB TX 256 to 511 byte Packets */ 197119917Swpaul#define BFE_TX_512_1023 0x00000528 /* MIB TX 512 to 1023 byte Packets */ 198119917Swpaul#define BFE_TX_1024_MAX 0x0000052C /* MIB TX 1024 to max byte Packets */ 199119917Swpaul#define BFE_TX_JABBER 0x00000530 /* MIB TX Jabber Packets */ 200119917Swpaul#define BFE_TX_OSIZE 0x00000534 /* MIB TX Oversize Packets */ 201119917Swpaul#define BFE_TX_FRAG 0x00000538 /* MIB TX Fragment Packets */ 202119917Swpaul#define BFE_TX_URUNS 0x0000053C /* MIB TX Underruns */ 203119917Swpaul#define BFE_TX_TCOLS 0x00000540 /* MIB TX Total Collisions */ 204119917Swpaul#define BFE_TX_SCOLS 0x00000544 /* MIB TX Single Collisions */ 205119917Swpaul#define BFE_TX_MCOLS 0x00000548 /* MIB TX Multiple Collisions */ 206119917Swpaul#define BFE_TX_ECOLS 0x0000054C /* MIB TX Excessive Collisions */ 207119917Swpaul#define BFE_TX_LCOLS 0x00000550 /* MIB TX Late Collisions */ 208119917Swpaul#define BFE_TX_DEFERED 0x00000554 /* MIB TX Defered Packets */ 209119917Swpaul#define BFE_TX_CLOST 0x00000558 /* MIB TX Carrier Lost */ 210119917Swpaul#define BFE_TX_PAUSE 0x0000055C /* MIB TX Pause Packets */ 211119917Swpaul#define BFE_RX_GOOD_O 0x00000580 /* MIB RX Good Octets */ 212119917Swpaul#define BFE_RX_GOOD_P 0x00000584 /* MIB RX Good Packets */ 213119917Swpaul#define BFE_RX_O 0x00000588 /* MIB RX Octets */ 214119917Swpaul#define BFE_RX_P 0x0000058C /* MIB RX Packets */ 215119917Swpaul#define BFE_RX_BCAST 0x00000590 /* MIB RX Broadcast Packets */ 216119917Swpaul#define BFE_RX_MCAST 0x00000594 /* MIB RX Multicast Packets */ 217119917Swpaul#define BFE_RX_64 0x00000598 /* MIB RX <= 64 byte Packets */ 218119917Swpaul#define BFE_RX_65_127 0x0000059C /* MIB RX 65 to 127 byte Packets */ 219119917Swpaul#define BFE_RX_128_255 0x000005A0 /* MIB RX 128 to 255 byte Packets */ 220119917Swpaul#define BFE_RX_256_511 0x000005A4 /* MIB RX 256 to 511 byte Packets */ 221119917Swpaul#define BFE_RX_512_1023 0x000005A8 /* MIB RX 512 to 1023 byte Packets */ 222119917Swpaul#define BFE_RX_1024_MAX 0x000005AC /* MIB RX 1024 to max byte Packets */ 223119917Swpaul#define BFE_RX_JABBER 0x000005B0 /* MIB RX Jabber Packets */ 224119917Swpaul#define BFE_RX_OSIZE 0x000005B4 /* MIB RX Oversize Packets */ 225119917Swpaul#define BFE_RX_FRAG 0x000005B8 /* MIB RX Fragment Packets */ 226119917Swpaul#define BFE_RX_MISS 0x000005BC /* MIB RX Missed Packets */ 227119917Swpaul#define BFE_RX_CRCA 0x000005C0 /* MIB RX CRC Align Errors */ 228119917Swpaul#define BFE_RX_USIZE 0x000005C4 /* MIB RX Undersize Packets */ 229119917Swpaul#define BFE_RX_CRC 0x000005C8 /* MIB RX CRC Errors */ 230119917Swpaul#define BFE_RX_ALIGN 0x000005CC /* MIB RX Align Errors */ 231119917Swpaul#define BFE_RX_SYM 0x000005D0 /* MIB RX Symbol Errors */ 232119917Swpaul#define BFE_RX_PAUSE 0x000005D4 /* MIB RX Pause Packets */ 233119917Swpaul#define BFE_RX_NPAUSE 0x000005D8 /* MIB RX Non-Pause Packets */ 234119917Swpaul 235119917Swpaul#define BFE_SBIMSTATE 0x00000F90 /* BFE_SB Initiator Agent State */ 236119917Swpaul#define BFE_PC 0x0000000f /* Pipe Count */ 237119917Swpaul#define BFE_AP_MASK 0x00000030 /* Arbitration Priority */ 238119917Swpaul#define BFE_AP_BOTH 0x00000000 /* Use both timeslices and token */ 239119917Swpaul#define BFE_AP_TS 0x00000010 /* Use timeslices only */ 240119917Swpaul#define BFE_AP_TK 0x00000020 /* Use token only */ 241119917Swpaul#define BFE_AP_RSV 0x00000030 /* Reserved */ 242119917Swpaul#define BFE_IBE 0x00020000 /* In Band Error */ 243119917Swpaul#define BFE_TO 0x00040000 /* Timeout */ 244119917Swpaul 245119917Swpaul 246119917Swpaul/* Seems the bcm440x has a fairly generic core, we only need be concerned with 247119917Swpaul * a couple of these 248119917Swpaul */ 249119917Swpaul#define BFE_SBINTVEC 0x00000F94 /* BFE_SB Interrupt Mask */ 250119917Swpaul#define BFE_INTVEC_PCI 0x00000001 /* Enable interrupts for PCI */ 251119917Swpaul#define BFE_INTVEC_ENET0 0x00000002 /* Enable interrupts for enet 0 */ 252119917Swpaul#define BFE_INTVEC_ILINE20 0x00000004 /* Enable interrupts for iline20 */ 253119917Swpaul#define BFE_INTVEC_CODEC 0x00000008 /* Enable interrupts for v90 codec */ 254119917Swpaul#define BFE_INTVEC_USB 0x00000010 /* Enable interrupts for usb */ 255119917Swpaul#define BFE_INTVEC_EXTIF 0x00000020 /* Enable interrupts for external i/f */ 256119917Swpaul#define BFE_INTVEC_ENET1 0x00000040 /* Enable interrupts for enet 1 */ 257119917Swpaul 258119917Swpaul#define BFE_SBTMSLOW 0x00000F98 /* BFE_SB Target State Low */ 259119917Swpaul#define BFE_RESET 0x00000001 /* Reset */ 260119917Swpaul#define BFE_REJECT 0x00000002 /* Reject */ 261119917Swpaul#define BFE_CLOCK 0x00010000 /* Clock Enable */ 262119917Swpaul#define BFE_FGC 0x00020000 /* Force Gated Clocks On */ 263119917Swpaul#define BFE_PE 0x40000000 /* Power Management Enable */ 264119917Swpaul#define BFE_BE 0x80000000 /* BIST Enable */ 265119917Swpaul 266119917Swpaul#define BFE_SBTMSHIGH 0x00000F9C /* BFE_SB Target State High */ 267119917Swpaul#define BFE_SERR 0x00000001 /* S-error */ 268119917Swpaul#define BFE_INT 0x00000002 /* Interrupt */ 269119917Swpaul#define BFE_BUSY 0x00000004 /* Busy */ 270119917Swpaul#define BFE_GCR 0x20000000 /* Gated Clock Request */ 271119917Swpaul#define BFE_BISTF 0x40000000 /* BIST Failed */ 272119917Swpaul#define BFE_BISTD 0x80000000 /* BIST Done */ 273119917Swpaul 274119917Swpaul#define BFE_SBBWA0 0x00000FA0 /* BFE_SB Bandwidth Allocation Table 0 */ 275119917Swpaul#define BFE_TAB0_MASK 0x0000ffff /* Lookup Table 0 */ 276119917Swpaul#define BFE_TAB1_MASK 0xffff0000 /* Lookup Table 0 */ 277119917Swpaul#define BFE_TAB0_SHIFT 0 278119917Swpaul#define BFE_TAB1_SHIFT 16 279119917Swpaul 280119917Swpaul#define BFE_SBIMCFGLOW 0x00000FA8 /* BFE_SB Initiator Configuration Low */ 281119917Swpaul#define BFE_STO_MASK 0x00000003 /* Service Timeout */ 282119917Swpaul#define BFE_RTO_MASK 0x00000030 /* Request Timeout */ 283119917Swpaul#define BFE_CID_MASK 0x00ff0000 /* Connection ID */ 284119917Swpaul#define BFE_RTO_SHIFT 4 285119917Swpaul#define BFE_CID_SHIFT 16 286119917Swpaul 287119917Swpaul#define BFE_SBIMCFGHIGH 0x00000FAC /* BFE_SB Initiator Configuration High */ 288119917Swpaul#define BFE_IEM_MASK 0x0000000c /* Inband Error Mode */ 289119917Swpaul#define BFE_TEM_MASK 0x00000030 /* Timeout Error Mode */ 290119917Swpaul#define BFE_BEM_MASK 0x000000c0 /* Bus Error Mode */ 291119917Swpaul#define BFE_TEM_SHIFT 4 292119917Swpaul#define BFE_BEM_SHIFT 6 293119917Swpaul 294119917Swpaul#define BFE_SBTMCFGLOW 0x00000FB8 /* BFE_SB Target Configuration Low */ 295119917Swpaul#define BFE_LOW_CD_MASK 0x000000ff /* Clock Divide Mask */ 296119917Swpaul#define BFE_LOW_CO_MASK 0x0000f800 /* Clock Offset Mask */ 297119917Swpaul#define BFE_LOW_IF_MASK 0x00fc0000 /* Interrupt Flags Mask */ 298119917Swpaul#define BFE_LOW_IM_MASK 0x03000000 /* Interrupt Mode Mask */ 299119917Swpaul#define BFE_LOW_CO_SHIFT 11 300119917Swpaul#define BFE_LOW_IF_SHIFT 18 301119917Swpaul#define BFE_LOW_IM_SHIFT 24 302119917Swpaul 303119917Swpaul#define BFE_SBTMCFGHIGH 0x00000FBC /* BFE_SB Target Configuration High */ 304119917Swpaul#define BFE_HIGH_BM_MASK 0x00000003 /* Busy Mode */ 305119917Swpaul#define BFE_HIGH_RM_MASK 0x0000000C /* Retry Mode */ 306119917Swpaul#define BFE_HIGH_SM_MASK 0x00000030 /* Stop Mode */ 307119917Swpaul#define BFE_HIGH_EM_MASK 0x00000300 /* Error Mode */ 308119917Swpaul#define BFE_HIGH_IM_MASK 0x00000c00 /* Interrupt Mode */ 309119917Swpaul#define BFE_HIGH_RM_SHIFT 2 310119917Swpaul#define BFE_HIGH_SM_SHIFT 4 311119917Swpaul#define BFE_HIGH_EM_SHIFT 8 312119917Swpaul#define BFE_HIGH_IM_SHIFT 10 313119917Swpaul 314119917Swpaul#define BFE_SBBCFG 0x00000FC0 /* BFE_SB Broadcast Configuration */ 315119917Swpaul#define BFE_LAT_MASK 0x00000003 /* BFE_SB Latency */ 316119917Swpaul#define BFE_MAX0_MASK 0x000f0000 /* MAX Counter 0 */ 317119917Swpaul#define BFE_MAX1_MASK 0x00f00000 /* MAX Counter 1 */ 318119917Swpaul#define BFE_MAX0_SHIFT 16 319119917Swpaul#define BFE_MAX1_SHIFT 20 320119917Swpaul 321119917Swpaul#define BFE_SBBSTATE 0x00000FC8 /* BFE_SB Broadcast State */ 322119917Swpaul#define BFE_SBBSTATE_SRD 0x00000001 /* ST Reg Disable */ 323119917Swpaul#define BFE_SBBSTATE_HRD 0x00000002 /* Hold Reg Disable */ 324119917Swpaul 325119917Swpaul#define BFE_SBACTCNFG 0x00000FD8 /* BFE_SB Activate Configuration */ 326119917Swpaul#define BFE_SBFLAGST 0x00000FE8 /* BFE_SB Current BFE_SBFLAGS */ 327119917Swpaul 328119917Swpaul#define BFE_SBIDLOW 0x00000FF8 /* BFE_SB Identification Low */ 329119917Swpaul#define BFE_CS_MASK 0x00000003 /* Config Space Mask */ 330119917Swpaul#define BFE_AR_MASK 0x00000038 /* Num Address Ranges Supported */ 331119917Swpaul#define BFE_SYNCH 0x00000040 /* Sync */ 332119917Swpaul#define BFE_INIT 0x00000080 /* Initiator */ 333119917Swpaul#define BFE_MINLAT_MASK 0x00000f00 /* Minimum Backplane Latency */ 334119917Swpaul#define BFE_MAXLAT_MASK 0x0000f000 /* Maximum Backplane Latency */ 335119917Swpaul#define BFE_FIRST 0x00010000 /* This Initiator is First */ 336119917Swpaul#define BFE_CW_MASK 0x000c0000 /* Cycle Counter Width */ 337119917Swpaul#define BFE_TP_MASK 0x00f00000 /* Target Ports */ 338119917Swpaul#define BFE_IP_MASK 0x0f000000 /* Initiator Ports */ 339119917Swpaul#define BFE_AR_SHIFT 3 340119917Swpaul#define BFE_MINLAT_SHIFT 8 341119917Swpaul#define BFE_MAXLAT_SHIFT 12 342119917Swpaul#define BFE_CW_SHIFT 18 343119917Swpaul#define BFE_TP_SHIFT 20 344119917Swpaul#define BFE_IP_SHIFT 24 345119917Swpaul 346119917Swpaul#define BFE_SBIDHIGH 0x00000FFC /* BFE_SB Identification High */ 347119917Swpaul#define BFE_RC_MASK 0x0000000f /* Revision Code */ 348119917Swpaul#define BFE_CC_MASK 0x0000fff0 /* Core Code */ 349119917Swpaul#define BFE_VC_MASK 0xffff0000 /* Vendor Code */ 350119917Swpaul#define BFE_CC_SHIFT 4 351119917Swpaul#define BFE_VC_SHIFT 16 352119917Swpaul 353119917Swpaul#define BFE_CORE_ILINE20 0x801 354119917Swpaul#define BFE_CORE_SDRAM 0x803 355119917Swpaul#define BFE_CORE_PCI 0x804 356119917Swpaul#define BFE_CORE_MIPS 0x805 357119917Swpaul#define BFE_CORE_ENET 0x806 358119917Swpaul#define BFE_CORE_CODEC 0x807 359119917Swpaul#define BFE_CORE_USB 0x808 360119917Swpaul#define BFE_CORE_ILINE100 0x80a 361119917Swpaul#define BFE_CORE_EXTIF 0x811 362119917Swpaul 363119917Swpaul/* SSB PCI config space registers. */ 364119917Swpaul#define BFE_BAR0_WIN 0x80 365119917Swpaul#define BFE_BAR1_WIN 0x84 366119917Swpaul#define BFE_SPROM_CONTROL 0x88 367119917Swpaul#define BFE_BAR1_CONTROL 0x8c 368119917Swpaul 369119917Swpaul/* SSB core and hsot control registers. */ 370119917Swpaul#define BFE_SSB_CONTROL 0x00000000 371119917Swpaul#define BFE_SSB_ARBCONTROL 0x00000010 372119917Swpaul#define BFE_SSB_ISTAT 0x00000020 373119917Swpaul#define BFE_SSB_IMASK 0x00000024 374119917Swpaul#define BFE_SSB_MBOX 0x00000028 375119917Swpaul#define BFE_SSB_BCAST_ADDR 0x00000050 376119917Swpaul#define BFE_SSB_BCAST_DATA 0x00000054 377119917Swpaul#define BFE_SSB_PCI_TRANS_0 0x00000100 378119917Swpaul#define BFE_SSB_PCI_TRANS_1 0x00000104 379119917Swpaul#define BFE_SSB_PCI_TRANS_2 0x00000108 380119917Swpaul#define BFE_SSB_SPROM 0x00000800 381119917Swpaul 382119917Swpaul#define BFE_SSB_PCI_MEM 0x00000000 383119917Swpaul#define BFE_SSB_PCI_IO 0x00000001 384119917Swpaul#define BFE_SSB_PCI_CFG0 0x00000002 385119917Swpaul#define BFE_SSB_PCI_CFG1 0x00000003 386119917Swpaul#define BFE_SSB_PCI_PREF 0x00000004 387119917Swpaul#define BFE_SSB_PCI_BURST 0x00000008 388119917Swpaul#define BFE_SSB_PCI_MASK0 0xfc000000 389119917Swpaul#define BFE_SSB_PCI_MASK1 0xfc000000 390119917Swpaul#define BFE_SSB_PCI_MASK2 0xc0000000 391119917Swpaul 392119917Swpaul#define BFE_DESC_LEN 0x00001fff 393119917Swpaul#define BFE_DESC_CMASK 0x0ff00000 /* Core specific bits */ 394119917Swpaul#define BFE_DESC_EOT 0x10000000 /* End of Table */ 395119917Swpaul#define BFE_DESC_IOC 0x20000000 /* Interrupt On Completion */ 396119917Swpaul#define BFE_DESC_EOF 0x40000000 /* End of Frame */ 397119917Swpaul#define BFE_DESC_SOF 0x80000000 /* Start of Frame */ 398119917Swpaul 399119917Swpaul#define BFE_RX_CP_THRESHOLD 256 400119917Swpaul#define BFE_RX_HEADER_LEN 28 401119917Swpaul 402119917Swpaul#define BFE_RX_FLAG_OFIFO 0x00000001 /* FIFO Overflow */ 403119917Swpaul#define BFE_RX_FLAG_CRCERR 0x00000002 /* CRC Error */ 404119917Swpaul#define BFE_RX_FLAG_SERR 0x00000004 /* Receive Symbol Error */ 405119917Swpaul#define BFE_RX_FLAG_ODD 0x00000008 /* Frame has odd number of nibbles */ 406119917Swpaul#define BFE_RX_FLAG_LARGE 0x00000010 /* Frame is > RX MAX Length */ 407119917Swpaul#define BFE_RX_FLAG_MCAST 0x00000020 /* Dest is Multicast Address */ 408119917Swpaul#define BFE_RX_FLAG_BCAST 0x00000040 /* Dest is Broadcast Address */ 409119917Swpaul#define BFE_RX_FLAG_MISS 0x00000080 /* Received due to promisc mode */ 410119917Swpaul#define BFE_RX_FLAG_LAST 0x00000800 /* Last buffer in frame */ 411119917Swpaul#define BFE_RX_FLAG_ERRORS (BFE_RX_FLAG_ODD | BFE_RX_FLAG_SERR | \ 412133282Sdes BFE_RX_FLAG_CRCERR | BFE_RX_FLAG_OFIFO) 413119917Swpaul 414119917Swpaul#define BFE_MCAST_TBL_SIZE 32 415119917Swpaul#define BFE_PCI_DMA 0x40000000 416119917Swpaul#define BFE_REG_PCI 0x18002000 417119917Swpaul 418119917Swpaul#define BCOM_VENDORID 0x14E4 419119917Swpaul#define BCOM_DEVICEID_BCM4401 0x4401 420134590Sdes#define BCOM_DEVICEID_BCM4401B0 0x170c 421119917Swpaul 422119917Swpaul#define PCI_SETBIT(dev, reg, x, s) \ 423119917Swpaul pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | (x)), s) 424119917Swpaul#define PCI_CLRBIT(dev, reg, x, s) \ 425119917Swpaul pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s) 426119917Swpaul 427119917Swpaul#define BFE_RX_RING_SIZE 512 428119917Swpaul#define BFE_TX_RING_SIZE 512 429119917Swpaul#define BFE_LINK_DOWN 5 430159015Ssilby#define BFE_TX_LIST_CNT 128 431159015Ssilby#define BFE_RX_LIST_CNT 128 432119917Swpaul#define BFE_TX_LIST_SIZE BFE_TX_LIST_CNT * sizeof(struct bfe_desc) 433119917Swpaul#define BFE_RX_LIST_SIZE BFE_RX_LIST_CNT * sizeof(struct bfe_desc) 434119917Swpaul#define BFE_RX_OFFSET 30 435119917Swpaul#define BFE_TX_QLEN 256 436119917Swpaul 437119917Swpaul#define CSR_READ_4(sc, reg) \ 438133282Sdes bus_space_read_4(sc->bfe_btag, sc->bfe_bhandle, reg) 439119917Swpaul 440119917Swpaul#define CSR_WRITE_4(sc, reg, val) \ 441133282Sdes bus_space_write_4(sc->bfe_btag, sc->bfe_bhandle, reg, val) 442119917Swpaul 443119917Swpaul#define BFE_OR(sc, name, val) \ 444133282Sdes CSR_WRITE_4(sc, name, CSR_READ_4(sc, name) | val) 445119917Swpaul 446119917Swpaul#define BFE_AND(sc, name, val) \ 447133282Sdes CSR_WRITE_4(sc, name, CSR_READ_4(sc, name) & val) 448119917Swpaul 449136804Smtm#define BFE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->bfe_mtx, MA_OWNED) 450136804Smtm#define BFE_LOCK(_sc) mtx_lock(&(_sc)->bfe_mtx) 451136804Smtm#define BFE_UNLOCK(_sc) mtx_unlock(&(_sc)->bfe_mtx) 452119917Swpaul 453119917Swpaul#define BFE_INC(x, y) (x) = ((x) == ((y)-1)) ? 0 : (x)+1 454119917Swpaul 455119917Swpaulstruct bfe_data { 456119917Swpaul struct mbuf *bfe_mbuf; 457119917Swpaul bus_dmamap_t bfe_map; 458119917Swpaul}; 459119917Swpaul 460119917Swpaulstruct bfe_desc { 461119917Swpaul u_int32_t bfe_ctrl; 462119917Swpaul u_int32_t bfe_addr; 463119917Swpaul}; 464119917Swpaul 465119917Swpaulstruct bfe_rxheader { 466119917Swpaul u_int16_t len; 467119917Swpaul u_int16_t flags; 468119917Swpaul u_int16_t pad[12]; 469119917Swpaul}; 470119917Swpaul 471119917Swpaulstruct bfe_hw_stats { 472119917Swpaul u_int32_t tx_good_octets, tx_good_pkts, tx_octets; 473119917Swpaul u_int32_t tx_pkts, tx_broadcast_pkts, tx_multicast_pkts; 474119917Swpaul u_int32_t tx_len_64, tx_len_65_to_127, tx_len_128_to_255; 475119917Swpaul u_int32_t tx_len_256_to_511, tx_len_512_to_1023, tx_len_1024_to_max; 476119917Swpaul u_int32_t tx_jabber_pkts, tx_oversize_pkts, tx_fragment_pkts; 477119917Swpaul u_int32_t tx_underruns, tx_total_cols, tx_single_cols; 478119917Swpaul u_int32_t tx_multiple_cols, tx_excessive_cols, tx_late_cols; 479119917Swpaul u_int32_t tx_defered, tx_carrier_lost, tx_pause_pkts; 480119917Swpaul u_int32_t __pad1[8]; 481119917Swpaul 482119917Swpaul u_int32_t rx_good_octets, rx_good_pkts, rx_octets; 483119917Swpaul u_int32_t rx_pkts, rx_broadcast_pkts, rx_multicast_pkts; 484119917Swpaul u_int32_t rx_len_64, rx_len_65_to_127, rx_len_128_to_255; 485119917Swpaul u_int32_t rx_len_256_to_511, rx_len_512_to_1023, rx_len_1024_to_max; 486119917Swpaul u_int32_t rx_jabber_pkts, rx_oversize_pkts, rx_fragment_pkts; 487119917Swpaul u_int32_t rx_missed_pkts, rx_crc_align_errs, rx_undersize; 488119917Swpaul u_int32_t rx_crc_errs, rx_align_errs, rx_symbol_errs; 489119917Swpaul u_int32_t rx_pause_pkts, rx_nonpause_pkts; 490119917Swpaul}; 491119917Swpaul 492133282Sdesstruct bfe_softc 493119917Swpaul{ 494147256Sbrooks struct ifnet *bfe_ifp; /* interface info */ 495119917Swpaul device_t bfe_dev; 496119917Swpaul device_t bfe_miibus; 497119917Swpaul bus_space_handle_t bfe_bhandle; 498119917Swpaul vm_offset_t bfe_vhandle; 499119917Swpaul bus_space_tag_t bfe_btag; 500119917Swpaul bus_dma_tag_t bfe_tag; 501119917Swpaul bus_dma_tag_t bfe_parent_tag; 502119917Swpaul bus_dma_tag_t bfe_tx_tag, bfe_rx_tag; 503119917Swpaul bus_dmamap_t bfe_tx_map, bfe_rx_map; 504119917Swpaul void *bfe_intrhand; 505119917Swpaul struct resource *bfe_irq; 506119917Swpaul struct resource *bfe_res; 507119917Swpaul struct callout_handle bfe_stat_ch; 508119917Swpaul struct bfe_hw_stats bfe_hwstats; 509119917Swpaul struct bfe_desc *bfe_tx_list, *bfe_rx_list; 510119917Swpaul struct bfe_data bfe_tx_ring[BFE_TX_LIST_CNT]; /* XXX */ 511119917Swpaul struct bfe_data bfe_rx_ring[BFE_RX_LIST_CNT]; /* XXX */ 512119917Swpaul struct mtx bfe_mtx; 513119917Swpaul u_int32_t bfe_flags; 514119917Swpaul u_int32_t bfe_imask; 515119917Swpaul u_int32_t bfe_dma_offset; 516119917Swpaul u_int32_t bfe_tx_cnt, bfe_tx_cons, bfe_tx_prod; 517119917Swpaul u_int32_t bfe_rx_cnt, bfe_rx_prod, bfe_rx_cons; 518119917Swpaul u_int32_t bfe_tx_dma, bfe_rx_dma; 519119917Swpaul u_int32_t bfe_link; 520119917Swpaul u_int8_t bfe_phyaddr; /* Address of the card's PHY */ 521119917Swpaul u_int8_t bfe_mdc_port; 522119917Swpaul u_int8_t bfe_unit; /* interface number */ 523119917Swpaul u_int8_t bfe_core_unit; 524119917Swpaul u_int8_t bfe_up; 525147256Sbrooks u_char bfe_enaddr[6]; 526119917Swpaul int bfe_if_flags; 527119917Swpaul char *bfe_vpd_prodname; 528119917Swpaul char *bfe_vpd_readonly; 529119917Swpaul}; 530119917Swpaul 531133282Sdesstruct bfe_type 532119917Swpaul{ 533119917Swpaul u_int16_t bfe_vid; 534119917Swpaul u_int16_t bfe_did; 535119917Swpaul char *bfe_name; 536119917Swpaul}; 537119917Swpaul 538119917Swpaul#endif /* _BFE_H */ 539