if_bfereg.h revision 127827
1119917Swpaul/* Copyright (c) 2003 Stuart Walsh */ 2127827Swes/* 3127827Swes * Redistribution and use in source and binary forms, with or without 4127827Swes * modification, are permitted provided that the following conditions 5127827Swes * are met: 6127827Swes * 1. Redistributions of source code must retain the above copyright 7127827Swes * notice, this list of conditions and the following disclaimer. 8127827Swes * 2. Redistributions in binary form must reproduce the above copyright 9127827Swes * notice, this list of conditions and the following disclaimer in the 10127827Swes * documentation and/or other materials provided with the distribution. 11127827Swes * 12127827Swes * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND 13127827Swes * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 14127827Swes * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 15127827Swes * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 16127827Swes * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 17127827Swes * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 18127827Swes * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 19127827Swes * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 20127827Swes * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 21127827Swes * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 22127827Swes * SUCH DAMAGE. 23127827Swes */ 24119917Swpaul/* $FreeBSD: head/sys/dev/bfe/if_bfereg.h 127827 2004-04-04 06:13:56Z wes $ */ 25119917Swpaul 26119917Swpaul#ifndef _BFE_H 27119917Swpaul#define _BFE_H 28119917Swpaul 29119917Swpaul/* PCI registers */ 30119917Swpaul#define BFE_PCI_MEMLO 0x10 31119917Swpaul#define BFE_PCI_MEMHIGH 0x14 32119917Swpaul#define BFE_PCI_INTLINE 0x3C 33119917Swpaul 34119917Swpaul/* Register layout. */ 35119917Swpaul#define BFE_DEVCTRL 0x00000000 /* Device Control */ 36119917Swpaul#define BFE_PFE 0x00000080 /* Pattern Filtering Enable */ 37119917Swpaul#define BFE_IPP 0x00000400 /* Internal EPHY Present */ 38119917Swpaul#define BFE_EPR 0x00008000 /* EPHY Reset */ 39119917Swpaul#define BFE_PME 0x00001000 /* PHY Mode Enable */ 40119917Swpaul#define BFE_PMCE 0x00002000 /* PHY Mode Clocks Enable */ 41119917Swpaul#define BFE_PADDR 0x0007c000 /* PHY Address */ 42119917Swpaul#define BFE_PADDR_SHIFT 18 43119917Swpaul 44119917Swpaul#define BFE_BIST_STAT 0x0000000C /* Built-In Self-Test Status */ 45119917Swpaul#define BFE_WKUP_LEN 0x00000010 /* Wakeup Length */ 46119917Swpaul 47119917Swpaul#define BFE_ISTAT 0x00000020 /* Interrupt Status */ 48119917Swpaul#define BFE_ISTAT_PME 0x00000040 /* Power Management Event */ 49119917Swpaul#define BFE_ISTAT_TO 0x00000080 /* General Purpose Timeout */ 50119917Swpaul#define BFE_ISTAT_DSCE 0x00000400 /* Descriptor Error */ 51119917Swpaul#define BFE_ISTAT_DATAE 0x00000800 /* Data Error */ 52119917Swpaul#define BFE_ISTAT_DPE 0x00001000 /* Descr. Protocol Error */ 53119917Swpaul#define BFE_ISTAT_RDU 0x00002000 /* Receive Descr. Underflow */ 54119917Swpaul#define BFE_ISTAT_RFO 0x00004000 /* Receive FIFO Overflow */ 55119917Swpaul#define BFE_ISTAT_TFU 0x00008000 /* Transmit FIFO Underflow */ 56119917Swpaul#define BFE_ISTAT_RX 0x00010000 /* RX Interrupt */ 57119917Swpaul#define BFE_ISTAT_TX 0x01000000 /* TX Interrupt */ 58119917Swpaul#define BFE_ISTAT_EMAC 0x04000000 /* EMAC Interrupt */ 59119917Swpaul#define BFE_ISTAT_MII_WRITE 0x08000000 /* MII Write Interrupt */ 60119917Swpaul#define BFE_ISTAT_MII_READ 0x10000000 /* MII Read Interrupt */ 61119917Swpaul#define BFE_ISTAT_ERRORS (BFE_ISTAT_DSCE | BFE_ISTAT_DATAE | BFE_ISTAT_DPE |\ 62119917Swpaul BFE_ISTAT_RDU | BFE_ISTAT_RFO | BFE_ISTAT_TFU) 63119917Swpaul 64119917Swpaul#define BFE_IMASK 0x00000024 /* Interrupt Mask */ 65119917Swpaul#define BFE_IMASK_DEF (BFE_ISTAT_ERRORS | BFE_ISTAT_TO | BFE_ISTAT_RX | \ 66119917Swpaul BFE_ISTAT_TX) 67119917Swpaul 68119917Swpaul#define BFE_MAC_CTRL 0x000000A8 /* MAC Control */ 69119917Swpaul#define BFE_CTRL_CRC32_ENAB 0x00000001 /* CRC32 Generation Enable */ 70119917Swpaul#define BFE_CTRL_PDOWN 0x00000004 /* Onchip EPHY Powerdown */ 71119917Swpaul#define BFE_CTRL_EDET 0x00000008 /* Onchip EPHY Energy Detected */ 72119917Swpaul#define BFE_CTRL_LED 0x000000e0 /* Onchip EPHY LED Control */ 73119917Swpaul#define BFE_CTRL_LED_SHIFT 5 74119917Swpaul 75119917Swpaul#define BFE_RCV_LAZY 0x00000100 /* Lazy Interrupt Control */ 76119917Swpaul#define BFE_LAZY_TO_MASK 0x00ffffff /* Timeout */ 77119917Swpaul#define BFE_LAZY_FC_MASK 0xff000000 /* Frame Count */ 78119917Swpaul#define BFE_LAZY_FC_SHIFT 24 79119917Swpaul 80119917Swpaul#define BFE_DMATX_CTRL 0x00000200 /* DMA TX Control */ 81119917Swpaul#define BFE_TX_CTRL_ENABLE 0x00000001 /* Enable */ 82119917Swpaul#define BFE_TX_CTRL_SUSPEND 0x00000002 /* Suepend Request */ 83119917Swpaul#define BFE_TX_CTRL_LPBACK 0x00000004 /* Loopback Enable */ 84119917Swpaul#define BFE_TX_CTRL_FAIRPRI 0x00000008 /* Fair Priority */ 85119917Swpaul#define BFE_TX_CTRL_FLUSH 0x00000010 /* Flush Request */ 86119917Swpaul 87119917Swpaul#define BFE_DMATX_ADDR 0x00000204 /* DMA TX Descriptor Ring Address */ 88119917Swpaul#define BFE_DMATX_PTR 0x00000208 /* DMA TX Last Posted Descriptor */ 89119917Swpaul#define BFE_DMATX_STAT 0x0000020C /* DMA TX Current Active Desc. + Status */ 90119917Swpaul#define BFE_STAT_CDMASK 0x00000fff /* Current Descriptor Mask */ 91119917Swpaul#define BFE_STAT_SMASK 0x0000f000 /* State Mask */ 92119917Swpaul#define BFE_STAT_DISABLE 0x00000000 /* State Disabled */ 93119917Swpaul#define BFE_STAT_SACTIVE 0x00001000 /* State Active */ 94119917Swpaul#define BFE_STAT_SIDLE 0x00002000 /* State Idle Wait */ 95119917Swpaul#define BFE_STAT_STOPPED 0x00003000 /* State Stopped */ 96119917Swpaul#define BFE_STAT_SSUSP 0x00004000 /* State Suspend Pending */ 97119917Swpaul#define BFE_STAT_EMASK 0x000f0000 /* Error Mask */ 98119917Swpaul#define BFE_STAT_ENONE 0x00000000 /* Error None */ 99119917Swpaul#define BFE_STAT_EDPE 0x00010000 /* Error Desc. Protocol Error */ 100119917Swpaul#define BFE_STAT_EDFU 0x00020000 /* Error Data FIFO Underrun */ 101119917Swpaul#define BFE_STAT_EBEBR 0x00030000 /* Error Bus Error on Buffer Read */ 102119917Swpaul#define BFE_STAT_EBEDA 0x00040000 /* Error Bus Error on Desc. Access */ 103119917Swpaul#define BFE_STAT_FLUSHED 0x00100000 /* Flushed */ 104119917Swpaul 105119917Swpaul#define BFE_DMARX_CTRL 0x00000210 /* DMA RX Control */ 106119917Swpaul#define BFE_RX_CTRL_ENABLE 0x00000001 /* Enable */ 107119917Swpaul#define BFE_RX_CTRL_ROMASK 0x000000fe /* Receive Offset Mask */ 108119917Swpaul#define BFE_RX_CTRL_ROSHIFT 1 /* Receive Offset Shift */ 109119917Swpaul 110119917Swpaul#define BFE_DMARX_ADDR 0x00000214 /* DMA RX Descriptor Ring Address */ 111119917Swpaul#define BFE_DMARX_PTR 0x00000218 /* DMA RX Last Posted Descriptor */ 112119917Swpaul#define BFE_DMARX_STAT 0x0000021C /* DMA RX Current Active Desc. + Status */ 113119917Swpaul 114119917Swpaul#define BFE_RXCONF 0x00000400 /* EMAC RX Config */ 115119917Swpaul#define BFE_RXCONF_DBCAST 0x00000001 /* Disable Broadcast */ 116119917Swpaul#define BFE_RXCONF_ALLMULTI 0x00000002 /* Accept All Multicast */ 117119917Swpaul#define BFE_RXCONF_NORXTX 0x00000004 /* Receive Disable While Transmitting */ 118119917Swpaul#define BFE_RXCONF_PROMISC 0x00000008 /* Promiscuous Enable */ 119119917Swpaul#define BFE_RXCONF_LPBACK 0x00000010 /* Loopback Enable */ 120119917Swpaul#define BFE_RXCONF_FLOW 0x00000020 /* Flow Control Enable */ 121119917Swpaul#define BFE_RXCONF_ACCEPT 0x00000040 /* Accept Unicast Flow Control Frame */ 122119917Swpaul#define BFE_RXCONF_RFILT 0x00000080 /* Reject Filter */ 123119917Swpaul 124119917Swpaul#define BFE_RXMAXLEN 0x00000404 /* EMAC RX Max Packet Length */ 125119917Swpaul#define BFE_TXMAXLEN 0x00000408 /* EMAC TX Max Packet Length */ 126119917Swpaul 127119917Swpaul#define BFE_MDIO_CTRL 0x00000410 /* EMAC MDIO Control */ 128119917Swpaul#define BFE_MDIO_MAXF_MASK 0x0000007f /* MDC Frequency */ 129119917Swpaul#define BFE_MDIO_PREAMBLE 0x00000080 /* MII Preamble Enable */ 130119917Swpaul 131119917Swpaul#define BFE_MDIO_DATA 0x00000414 /* EMAC MDIO Data */ 132119917Swpaul#define BFE_MDIO_DATA_DATA 0x0000ffff /* R/W Data */ 133119917Swpaul#define BFE_MDIO_TA_MASK 0x00030000 /* Turnaround Value */ 134119917Swpaul#define BFE_MDIO_TA_SHIFT 16 135119917Swpaul#define BFE_MDIO_TA_VALID 2 136119917Swpaul 137119917Swpaul#define BFE_MDIO_RA_MASK 0x007c0000 /* Register Address */ 138119917Swpaul#define BFE_MDIO_PMD_MASK 0x0f800000 /* Physical Media Device */ 139119917Swpaul#define BFE_MDIO_OP_MASK 0x30000000 /* Opcode */ 140119917Swpaul#define BFE_MDIO_SB_MASK 0xc0000000 /* Start Bits */ 141119917Swpaul#define BFE_MDIO_SB_START 0x40000000 /* Start Of Frame */ 142119917Swpaul#define BFE_MDIO_RA_SHIFT 18 143119917Swpaul#define BFE_MDIO_PMD_SHIFT 23 144119917Swpaul#define BFE_MDIO_OP_SHIFT 28 145119917Swpaul#define BFE_MDIO_OP_WRITE 1 146119917Swpaul#define BFE_MDIO_OP_READ 2 147119917Swpaul#define BFE_MDIO_SB_SHIFT 30 148119917Swpaul 149119917Swpaul#define BFE_EMAC_IMASK 0x00000418 /* EMAC Interrupt Mask */ 150119917Swpaul#define BFE_EMAC_ISTAT 0x0000041C /* EMAC Interrupt Status */ 151119917Swpaul#define BFE_EMAC_INT_MII 0x00000001 /* MII MDIO Interrupt */ 152119917Swpaul#define BFE_EMAC_INT_MIB 0x00000002 /* MIB Interrupt */ 153119917Swpaul#define BFE_EMAC_INT_FLOW 0x00000003 /* Flow Control Interrupt */ 154119917Swpaul 155119917Swpaul#define BFE_CAM_DATA_LO 0x00000420 /* EMAC CAM Data Low */ 156119917Swpaul#define BFE_CAM_DATA_HI 0x00000424 /* EMAC CAM Data High */ 157119917Swpaul#define BFE_CAM_HI_VALID 0x00010000 /* Valid Bit */ 158119917Swpaul 159119917Swpaul#define BFE_CAM_CTRL 0x00000428 /* EMAC CAM Control */ 160119917Swpaul#define BFE_CAM_ENABLE 0x00000001 /* CAM Enable */ 161119917Swpaul#define BFE_CAM_MSEL 0x00000002 /* Mask Select */ 162119917Swpaul#define BFE_CAM_READ 0x00000004 /* Read */ 163119917Swpaul#define BFE_CAM_WRITE 0x00000008 /* Read */ 164119917Swpaul#define BFE_CAM_INDEX_MASK 0x003f0000 /* Index Mask */ 165119917Swpaul#define BFE_CAM_BUSY 0x80000000 /* CAM Busy */ 166119917Swpaul#define BFE_CAM_INDEX_SHIFT 16 167119917Swpaul 168119917Swpaul#define BFE_ENET_CTRL 0x0000042C /* EMAC ENET Control */ 169119917Swpaul#define BFE_ENET_ENABLE 0x00000001 /* EMAC Enable */ 170119917Swpaul#define BFE_ENET_DISABLE 0x00000002 /* EMAC Disable */ 171119917Swpaul#define BFE_ENET_SRST 0x00000004 /* EMAC Soft Reset */ 172119917Swpaul#define BFE_ENET_EPSEL 0x00000008 /* External PHY Select */ 173119917Swpaul 174119917Swpaul#define BFE_TX_CTRL 0x00000430 /* EMAC TX Control */ 175119917Swpaul#define BFE_TX_DUPLEX 0x00000001 /* Full Duplex */ 176119917Swpaul#define BFE_TX_FMODE 0x00000002 /* Flow Mode */ 177119917Swpaul#define BFE_TX_SBENAB 0x00000004 /* Single Backoff Enable */ 178119917Swpaul#define BFE_TX_SMALL_SLOT 0x00000008 /* Small Slottime */ 179119917Swpaul 180119917Swpaul#define BFE_TX_WMARK 0x00000434 /* EMAC TX Watermark */ 181119917Swpaul 182119917Swpaul#define BFE_MIB_CTRL 0x00000438 /* EMAC MIB Control */ 183119917Swpaul#define BFE_MIB_CLR_ON_READ 0x00000001 /* Autoclear on Read */ 184119917Swpaul 185119917Swpaul/* Status registers */ 186119917Swpaul#define BFE_TX_GOOD_O 0x00000500 /* MIB TX Good Octets */ 187119917Swpaul#define BFE_TX_GOOD_P 0x00000504 /* MIB TX Good Packets */ 188119917Swpaul#define BFE_TX_O 0x00000508 /* MIB TX Octets */ 189119917Swpaul#define BFE_TX_P 0x0000050C /* MIB TX Packets */ 190119917Swpaul#define BFE_TX_BCAST 0x00000510 /* MIB TX Broadcast Packets */ 191119917Swpaul#define BFE_TX_MCAST 0x00000514 /* MIB TX Multicast Packets */ 192119917Swpaul#define BFE_TX_64 0x00000518 /* MIB TX <= 64 byte Packets */ 193119917Swpaul#define BFE_TX_65_127 0x0000051C /* MIB TX 65 to 127 byte Packets */ 194119917Swpaul#define BFE_TX_128_255 0x00000520 /* MIB TX 128 to 255 byte Packets */ 195119917Swpaul#define BFE_TX_256_511 0x00000524 /* MIB TX 256 to 511 byte Packets */ 196119917Swpaul#define BFE_TX_512_1023 0x00000528 /* MIB TX 512 to 1023 byte Packets */ 197119917Swpaul#define BFE_TX_1024_MAX 0x0000052C /* MIB TX 1024 to max byte Packets */ 198119917Swpaul#define BFE_TX_JABBER 0x00000530 /* MIB TX Jabber Packets */ 199119917Swpaul#define BFE_TX_OSIZE 0x00000534 /* MIB TX Oversize Packets */ 200119917Swpaul#define BFE_TX_FRAG 0x00000538 /* MIB TX Fragment Packets */ 201119917Swpaul#define BFE_TX_URUNS 0x0000053C /* MIB TX Underruns */ 202119917Swpaul#define BFE_TX_TCOLS 0x00000540 /* MIB TX Total Collisions */ 203119917Swpaul#define BFE_TX_SCOLS 0x00000544 /* MIB TX Single Collisions */ 204119917Swpaul#define BFE_TX_MCOLS 0x00000548 /* MIB TX Multiple Collisions */ 205119917Swpaul#define BFE_TX_ECOLS 0x0000054C /* MIB TX Excessive Collisions */ 206119917Swpaul#define BFE_TX_LCOLS 0x00000550 /* MIB TX Late Collisions */ 207119917Swpaul#define BFE_TX_DEFERED 0x00000554 /* MIB TX Defered Packets */ 208119917Swpaul#define BFE_TX_CLOST 0x00000558 /* MIB TX Carrier Lost */ 209119917Swpaul#define BFE_TX_PAUSE 0x0000055C /* MIB TX Pause Packets */ 210119917Swpaul#define BFE_RX_GOOD_O 0x00000580 /* MIB RX Good Octets */ 211119917Swpaul#define BFE_RX_GOOD_P 0x00000584 /* MIB RX Good Packets */ 212119917Swpaul#define BFE_RX_O 0x00000588 /* MIB RX Octets */ 213119917Swpaul#define BFE_RX_P 0x0000058C /* MIB RX Packets */ 214119917Swpaul#define BFE_RX_BCAST 0x00000590 /* MIB RX Broadcast Packets */ 215119917Swpaul#define BFE_RX_MCAST 0x00000594 /* MIB RX Multicast Packets */ 216119917Swpaul#define BFE_RX_64 0x00000598 /* MIB RX <= 64 byte Packets */ 217119917Swpaul#define BFE_RX_65_127 0x0000059C /* MIB RX 65 to 127 byte Packets */ 218119917Swpaul#define BFE_RX_128_255 0x000005A0 /* MIB RX 128 to 255 byte Packets */ 219119917Swpaul#define BFE_RX_256_511 0x000005A4 /* MIB RX 256 to 511 byte Packets */ 220119917Swpaul#define BFE_RX_512_1023 0x000005A8 /* MIB RX 512 to 1023 byte Packets */ 221119917Swpaul#define BFE_RX_1024_MAX 0x000005AC /* MIB RX 1024 to max byte Packets */ 222119917Swpaul#define BFE_RX_JABBER 0x000005B0 /* MIB RX Jabber Packets */ 223119917Swpaul#define BFE_RX_OSIZE 0x000005B4 /* MIB RX Oversize Packets */ 224119917Swpaul#define BFE_RX_FRAG 0x000005B8 /* MIB RX Fragment Packets */ 225119917Swpaul#define BFE_RX_MISS 0x000005BC /* MIB RX Missed Packets */ 226119917Swpaul#define BFE_RX_CRCA 0x000005C0 /* MIB RX CRC Align Errors */ 227119917Swpaul#define BFE_RX_USIZE 0x000005C4 /* MIB RX Undersize Packets */ 228119917Swpaul#define BFE_RX_CRC 0x000005C8 /* MIB RX CRC Errors */ 229119917Swpaul#define BFE_RX_ALIGN 0x000005CC /* MIB RX Align Errors */ 230119917Swpaul#define BFE_RX_SYM 0x000005D0 /* MIB RX Symbol Errors */ 231119917Swpaul#define BFE_RX_PAUSE 0x000005D4 /* MIB RX Pause Packets */ 232119917Swpaul#define BFE_RX_NPAUSE 0x000005D8 /* MIB RX Non-Pause Packets */ 233119917Swpaul 234119917Swpaul#define BFE_SBIMSTATE 0x00000F90 /* BFE_SB Initiator Agent State */ 235119917Swpaul#define BFE_PC 0x0000000f /* Pipe Count */ 236119917Swpaul#define BFE_AP_MASK 0x00000030 /* Arbitration Priority */ 237119917Swpaul#define BFE_AP_BOTH 0x00000000 /* Use both timeslices and token */ 238119917Swpaul#define BFE_AP_TS 0x00000010 /* Use timeslices only */ 239119917Swpaul#define BFE_AP_TK 0x00000020 /* Use token only */ 240119917Swpaul#define BFE_AP_RSV 0x00000030 /* Reserved */ 241119917Swpaul#define BFE_IBE 0x00020000 /* In Band Error */ 242119917Swpaul#define BFE_TO 0x00040000 /* Timeout */ 243119917Swpaul 244119917Swpaul 245119917Swpaul/* Seems the bcm440x has a fairly generic core, we only need be concerned with 246119917Swpaul * a couple of these 247119917Swpaul */ 248119917Swpaul#define BFE_SBINTVEC 0x00000F94 /* BFE_SB Interrupt Mask */ 249119917Swpaul#define BFE_INTVEC_PCI 0x00000001 /* Enable interrupts for PCI */ 250119917Swpaul#define BFE_INTVEC_ENET0 0x00000002 /* Enable interrupts for enet 0 */ 251119917Swpaul#define BFE_INTVEC_ILINE20 0x00000004 /* Enable interrupts for iline20 */ 252119917Swpaul#define BFE_INTVEC_CODEC 0x00000008 /* Enable interrupts for v90 codec */ 253119917Swpaul#define BFE_INTVEC_USB 0x00000010 /* Enable interrupts for usb */ 254119917Swpaul#define BFE_INTVEC_EXTIF 0x00000020 /* Enable interrupts for external i/f */ 255119917Swpaul#define BFE_INTVEC_ENET1 0x00000040 /* Enable interrupts for enet 1 */ 256119917Swpaul 257119917Swpaul#define BFE_SBTMSLOW 0x00000F98 /* BFE_SB Target State Low */ 258119917Swpaul#define BFE_RESET 0x00000001 /* Reset */ 259119917Swpaul#define BFE_REJECT 0x00000002 /* Reject */ 260119917Swpaul#define BFE_CLOCK 0x00010000 /* Clock Enable */ 261119917Swpaul#define BFE_FGC 0x00020000 /* Force Gated Clocks On */ 262119917Swpaul#define BFE_PE 0x40000000 /* Power Management Enable */ 263119917Swpaul#define BFE_BE 0x80000000 /* BIST Enable */ 264119917Swpaul 265119917Swpaul#define BFE_SBTMSHIGH 0x00000F9C /* BFE_SB Target State High */ 266119917Swpaul#define BFE_SERR 0x00000001 /* S-error */ 267119917Swpaul#define BFE_INT 0x00000002 /* Interrupt */ 268119917Swpaul#define BFE_BUSY 0x00000004 /* Busy */ 269119917Swpaul#define BFE_GCR 0x20000000 /* Gated Clock Request */ 270119917Swpaul#define BFE_BISTF 0x40000000 /* BIST Failed */ 271119917Swpaul#define BFE_BISTD 0x80000000 /* BIST Done */ 272119917Swpaul 273119917Swpaul#define BFE_SBBWA0 0x00000FA0 /* BFE_SB Bandwidth Allocation Table 0 */ 274119917Swpaul#define BFE_TAB0_MASK 0x0000ffff /* Lookup Table 0 */ 275119917Swpaul#define BFE_TAB1_MASK 0xffff0000 /* Lookup Table 0 */ 276119917Swpaul#define BFE_TAB0_SHIFT 0 277119917Swpaul#define BFE_TAB1_SHIFT 16 278119917Swpaul 279119917Swpaul#define BFE_SBIMCFGLOW 0x00000FA8 /* BFE_SB Initiator Configuration Low */ 280119917Swpaul#define BFE_STO_MASK 0x00000003 /* Service Timeout */ 281119917Swpaul#define BFE_RTO_MASK 0x00000030 /* Request Timeout */ 282119917Swpaul#define BFE_CID_MASK 0x00ff0000 /* Connection ID */ 283119917Swpaul#define BFE_RTO_SHIFT 4 284119917Swpaul#define BFE_CID_SHIFT 16 285119917Swpaul 286119917Swpaul#define BFE_SBIMCFGHIGH 0x00000FAC /* BFE_SB Initiator Configuration High */ 287119917Swpaul#define BFE_IEM_MASK 0x0000000c /* Inband Error Mode */ 288119917Swpaul#define BFE_TEM_MASK 0x00000030 /* Timeout Error Mode */ 289119917Swpaul#define BFE_BEM_MASK 0x000000c0 /* Bus Error Mode */ 290119917Swpaul#define BFE_TEM_SHIFT 4 291119917Swpaul#define BFE_BEM_SHIFT 6 292119917Swpaul 293119917Swpaul#define BFE_SBTMCFGLOW 0x00000FB8 /* BFE_SB Target Configuration Low */ 294119917Swpaul#define BFE_LOW_CD_MASK 0x000000ff /* Clock Divide Mask */ 295119917Swpaul#define BFE_LOW_CO_MASK 0x0000f800 /* Clock Offset Mask */ 296119917Swpaul#define BFE_LOW_IF_MASK 0x00fc0000 /* Interrupt Flags Mask */ 297119917Swpaul#define BFE_LOW_IM_MASK 0x03000000 /* Interrupt Mode Mask */ 298119917Swpaul#define BFE_LOW_CO_SHIFT 11 299119917Swpaul#define BFE_LOW_IF_SHIFT 18 300119917Swpaul#define BFE_LOW_IM_SHIFT 24 301119917Swpaul 302119917Swpaul#define BFE_SBTMCFGHIGH 0x00000FBC /* BFE_SB Target Configuration High */ 303119917Swpaul#define BFE_HIGH_BM_MASK 0x00000003 /* Busy Mode */ 304119917Swpaul#define BFE_HIGH_RM_MASK 0x0000000C /* Retry Mode */ 305119917Swpaul#define BFE_HIGH_SM_MASK 0x00000030 /* Stop Mode */ 306119917Swpaul#define BFE_HIGH_EM_MASK 0x00000300 /* Error Mode */ 307119917Swpaul#define BFE_HIGH_IM_MASK 0x00000c00 /* Interrupt Mode */ 308119917Swpaul#define BFE_HIGH_RM_SHIFT 2 309119917Swpaul#define BFE_HIGH_SM_SHIFT 4 310119917Swpaul#define BFE_HIGH_EM_SHIFT 8 311119917Swpaul#define BFE_HIGH_IM_SHIFT 10 312119917Swpaul 313119917Swpaul#define BFE_SBBCFG 0x00000FC0 /* BFE_SB Broadcast Configuration */ 314119917Swpaul#define BFE_LAT_MASK 0x00000003 /* BFE_SB Latency */ 315119917Swpaul#define BFE_MAX0_MASK 0x000f0000 /* MAX Counter 0 */ 316119917Swpaul#define BFE_MAX1_MASK 0x00f00000 /* MAX Counter 1 */ 317119917Swpaul#define BFE_MAX0_SHIFT 16 318119917Swpaul#define BFE_MAX1_SHIFT 20 319119917Swpaul 320119917Swpaul#define BFE_SBBSTATE 0x00000FC8 /* BFE_SB Broadcast State */ 321119917Swpaul#define BFE_SBBSTATE_SRD 0x00000001 /* ST Reg Disable */ 322119917Swpaul#define BFE_SBBSTATE_HRD 0x00000002 /* Hold Reg Disable */ 323119917Swpaul 324119917Swpaul#define BFE_SBACTCNFG 0x00000FD8 /* BFE_SB Activate Configuration */ 325119917Swpaul#define BFE_SBFLAGST 0x00000FE8 /* BFE_SB Current BFE_SBFLAGS */ 326119917Swpaul 327119917Swpaul#define BFE_SBIDLOW 0x00000FF8 /* BFE_SB Identification Low */ 328119917Swpaul#define BFE_CS_MASK 0x00000003 /* Config Space Mask */ 329119917Swpaul#define BFE_AR_MASK 0x00000038 /* Num Address Ranges Supported */ 330119917Swpaul#define BFE_SYNCH 0x00000040 /* Sync */ 331119917Swpaul#define BFE_INIT 0x00000080 /* Initiator */ 332119917Swpaul#define BFE_MINLAT_MASK 0x00000f00 /* Minimum Backplane Latency */ 333119917Swpaul#define BFE_MAXLAT_MASK 0x0000f000 /* Maximum Backplane Latency */ 334119917Swpaul#define BFE_FIRST 0x00010000 /* This Initiator is First */ 335119917Swpaul#define BFE_CW_MASK 0x000c0000 /* Cycle Counter Width */ 336119917Swpaul#define BFE_TP_MASK 0x00f00000 /* Target Ports */ 337119917Swpaul#define BFE_IP_MASK 0x0f000000 /* Initiator Ports */ 338119917Swpaul#define BFE_AR_SHIFT 3 339119917Swpaul#define BFE_MINLAT_SHIFT 8 340119917Swpaul#define BFE_MAXLAT_SHIFT 12 341119917Swpaul#define BFE_CW_SHIFT 18 342119917Swpaul#define BFE_TP_SHIFT 20 343119917Swpaul#define BFE_IP_SHIFT 24 344119917Swpaul 345119917Swpaul#define BFE_SBIDHIGH 0x00000FFC /* BFE_SB Identification High */ 346119917Swpaul#define BFE_RC_MASK 0x0000000f /* Revision Code */ 347119917Swpaul#define BFE_CC_MASK 0x0000fff0 /* Core Code */ 348119917Swpaul#define BFE_VC_MASK 0xffff0000 /* Vendor Code */ 349119917Swpaul#define BFE_CC_SHIFT 4 350119917Swpaul#define BFE_VC_SHIFT 16 351119917Swpaul 352119917Swpaul#define BFE_CORE_ILINE20 0x801 353119917Swpaul#define BFE_CORE_SDRAM 0x803 354119917Swpaul#define BFE_CORE_PCI 0x804 355119917Swpaul#define BFE_CORE_MIPS 0x805 356119917Swpaul#define BFE_CORE_ENET 0x806 357119917Swpaul#define BFE_CORE_CODEC 0x807 358119917Swpaul#define BFE_CORE_USB 0x808 359119917Swpaul#define BFE_CORE_ILINE100 0x80a 360119917Swpaul#define BFE_CORE_EXTIF 0x811 361119917Swpaul 362119917Swpaul/* SSB PCI config space registers. */ 363119917Swpaul#define BFE_BAR0_WIN 0x80 364119917Swpaul#define BFE_BAR1_WIN 0x84 365119917Swpaul#define BFE_SPROM_CONTROL 0x88 366119917Swpaul#define BFE_BAR1_CONTROL 0x8c 367119917Swpaul 368119917Swpaul/* SSB core and hsot control registers. */ 369119917Swpaul#define BFE_SSB_CONTROL 0x00000000 370119917Swpaul#define BFE_SSB_ARBCONTROL 0x00000010 371119917Swpaul#define BFE_SSB_ISTAT 0x00000020 372119917Swpaul#define BFE_SSB_IMASK 0x00000024 373119917Swpaul#define BFE_SSB_MBOX 0x00000028 374119917Swpaul#define BFE_SSB_BCAST_ADDR 0x00000050 375119917Swpaul#define BFE_SSB_BCAST_DATA 0x00000054 376119917Swpaul#define BFE_SSB_PCI_TRANS_0 0x00000100 377119917Swpaul#define BFE_SSB_PCI_TRANS_1 0x00000104 378119917Swpaul#define BFE_SSB_PCI_TRANS_2 0x00000108 379119917Swpaul#define BFE_SSB_SPROM 0x00000800 380119917Swpaul 381119917Swpaul#define BFE_SSB_PCI_MEM 0x00000000 382119917Swpaul#define BFE_SSB_PCI_IO 0x00000001 383119917Swpaul#define BFE_SSB_PCI_CFG0 0x00000002 384119917Swpaul#define BFE_SSB_PCI_CFG1 0x00000003 385119917Swpaul#define BFE_SSB_PCI_PREF 0x00000004 386119917Swpaul#define BFE_SSB_PCI_BURST 0x00000008 387119917Swpaul#define BFE_SSB_PCI_MASK0 0xfc000000 388119917Swpaul#define BFE_SSB_PCI_MASK1 0xfc000000 389119917Swpaul#define BFE_SSB_PCI_MASK2 0xc0000000 390119917Swpaul 391119917Swpaul#define BFE_DESC_LEN 0x00001fff 392119917Swpaul#define BFE_DESC_CMASK 0x0ff00000 /* Core specific bits */ 393119917Swpaul#define BFE_DESC_EOT 0x10000000 /* End of Table */ 394119917Swpaul#define BFE_DESC_IOC 0x20000000 /* Interrupt On Completion */ 395119917Swpaul#define BFE_DESC_EOF 0x40000000 /* End of Frame */ 396119917Swpaul#define BFE_DESC_SOF 0x80000000 /* Start of Frame */ 397119917Swpaul 398119917Swpaul#define BFE_RX_CP_THRESHOLD 256 399119917Swpaul#define BFE_RX_HEADER_LEN 28 400119917Swpaul 401119917Swpaul#define BFE_RX_FLAG_OFIFO 0x00000001 /* FIFO Overflow */ 402119917Swpaul#define BFE_RX_FLAG_CRCERR 0x00000002 /* CRC Error */ 403119917Swpaul#define BFE_RX_FLAG_SERR 0x00000004 /* Receive Symbol Error */ 404119917Swpaul#define BFE_RX_FLAG_ODD 0x00000008 /* Frame has odd number of nibbles */ 405119917Swpaul#define BFE_RX_FLAG_LARGE 0x00000010 /* Frame is > RX MAX Length */ 406119917Swpaul#define BFE_RX_FLAG_MCAST 0x00000020 /* Dest is Multicast Address */ 407119917Swpaul#define BFE_RX_FLAG_BCAST 0x00000040 /* Dest is Broadcast Address */ 408119917Swpaul#define BFE_RX_FLAG_MISS 0x00000080 /* Received due to promisc mode */ 409119917Swpaul#define BFE_RX_FLAG_LAST 0x00000800 /* Last buffer in frame */ 410119917Swpaul#define BFE_RX_FLAG_ERRORS (BFE_RX_FLAG_ODD | BFE_RX_FLAG_SERR | \ 411119917Swpaul BFE_RX_FLAG_CRCERR | BFE_RX_FLAG_OFIFO) 412119917Swpaul 413119917Swpaul#define BFE_MCAST_TBL_SIZE 32 414119917Swpaul#define BFE_PCI_DMA 0x40000000 415119917Swpaul#define BFE_REG_PCI 0x18002000 416119917Swpaul 417119917Swpaul#define BCOM_VENDORID 0x14E4 418119917Swpaul#define BCOM_DEVICEID_BCM4401 0x4401 419119917Swpaul 420119917Swpaul#define PCI_SETBIT(dev, reg, x, s) \ 421119917Swpaul pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | (x)), s) 422119917Swpaul#define PCI_CLRBIT(dev, reg, x, s) \ 423119917Swpaul pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s) 424119917Swpaul 425119917Swpaul#define BFE_RX_RING_SIZE 512 426119917Swpaul#define BFE_TX_RING_SIZE 512 427119917Swpaul#define BFE_LINK_DOWN 5 428119917Swpaul#define BFE_TX_LIST_CNT 511 429119917Swpaul#define BFE_RX_LIST_CNT 511 430119917Swpaul#define BFE_TX_LIST_SIZE BFE_TX_LIST_CNT * sizeof(struct bfe_desc) 431119917Swpaul#define BFE_RX_LIST_SIZE BFE_RX_LIST_CNT * sizeof(struct bfe_desc) 432119917Swpaul#define BFE_RX_OFFSET 30 433119917Swpaul#define BFE_TX_QLEN 256 434119917Swpaul 435119917Swpaul#define CSR_READ_4(sc, reg) \ 436119917Swpaul bus_space_read_4(sc->bfe_btag, sc->bfe_bhandle, reg) 437119917Swpaul 438119917Swpaul#define CSR_WRITE_4(sc, reg, val) \ 439119917Swpaul bus_space_write_4(sc->bfe_btag, sc->bfe_bhandle, reg, val) 440119917Swpaul 441119917Swpaul#define BFE_OR(sc, name, val) \ 442119917Swpaul CSR_WRITE_4(sc, name, CSR_READ_4(sc, name) | val) 443119917Swpaul 444119917Swpaul#define BFE_AND(sc, name, val) \ 445119917Swpaul CSR_WRITE_4(sc, name, CSR_READ_4(sc, name) & val) 446119917Swpaul 447119917Swpaul#define BFE_LOCK(scp) mtx_lock(&sc->bfe_mtx) 448119917Swpaul#define BFE_UNLOCK(scp) mtx_unlock(&sc->bfe_mtx) 449119917Swpaul 450119917Swpaul#define BFE_INC(x, y) (x) = ((x) == ((y)-1)) ? 0 : (x)+1 451119917Swpaul 452119917Swpaulstruct bfe_data { 453119917Swpaul struct mbuf *bfe_mbuf; 454119917Swpaul bus_dmamap_t bfe_map; 455119917Swpaul}; 456119917Swpaul 457119917Swpaulstruct bfe_desc { 458119917Swpaul u_int32_t bfe_ctrl; 459119917Swpaul u_int32_t bfe_addr; 460119917Swpaul}; 461119917Swpaul 462119917Swpaulstruct bfe_rxheader { 463119917Swpaul u_int16_t len; 464119917Swpaul u_int16_t flags; 465119917Swpaul u_int16_t pad[12]; 466119917Swpaul}; 467119917Swpaul 468119917Swpaulstruct bfe_hw_stats { 469119917Swpaul u_int32_t tx_good_octets, tx_good_pkts, tx_octets; 470119917Swpaul u_int32_t tx_pkts, tx_broadcast_pkts, tx_multicast_pkts; 471119917Swpaul u_int32_t tx_len_64, tx_len_65_to_127, tx_len_128_to_255; 472119917Swpaul u_int32_t tx_len_256_to_511, tx_len_512_to_1023, tx_len_1024_to_max; 473119917Swpaul u_int32_t tx_jabber_pkts, tx_oversize_pkts, tx_fragment_pkts; 474119917Swpaul u_int32_t tx_underruns, tx_total_cols, tx_single_cols; 475119917Swpaul u_int32_t tx_multiple_cols, tx_excessive_cols, tx_late_cols; 476119917Swpaul u_int32_t tx_defered, tx_carrier_lost, tx_pause_pkts; 477119917Swpaul u_int32_t __pad1[8]; 478119917Swpaul 479119917Swpaul u_int32_t rx_good_octets, rx_good_pkts, rx_octets; 480119917Swpaul u_int32_t rx_pkts, rx_broadcast_pkts, rx_multicast_pkts; 481119917Swpaul u_int32_t rx_len_64, rx_len_65_to_127, rx_len_128_to_255; 482119917Swpaul u_int32_t rx_len_256_to_511, rx_len_512_to_1023, rx_len_1024_to_max; 483119917Swpaul u_int32_t rx_jabber_pkts, rx_oversize_pkts, rx_fragment_pkts; 484119917Swpaul u_int32_t rx_missed_pkts, rx_crc_align_errs, rx_undersize; 485119917Swpaul u_int32_t rx_crc_errs, rx_align_errs, rx_symbol_errs; 486119917Swpaul u_int32_t rx_pause_pkts, rx_nonpause_pkts; 487119917Swpaul}; 488119917Swpaul 489119917Swpaulstruct bfe_softc 490119917Swpaul{ 491119917Swpaul struct arpcom arpcom; /* interface info */ 492119917Swpaul device_t bfe_dev; 493119917Swpaul device_t bfe_miibus; 494119917Swpaul bus_space_handle_t bfe_bhandle; 495119917Swpaul vm_offset_t bfe_vhandle; 496119917Swpaul bus_space_tag_t bfe_btag; 497119917Swpaul bus_dma_tag_t bfe_tag; 498119917Swpaul bus_dma_tag_t bfe_parent_tag; 499119917Swpaul bus_dma_tag_t bfe_tx_tag, bfe_rx_tag; 500119917Swpaul bus_dmamap_t bfe_tx_map, bfe_rx_map; 501119917Swpaul void *bfe_intrhand; 502119917Swpaul struct resource *bfe_irq; 503119917Swpaul struct resource *bfe_res; 504119917Swpaul struct callout_handle bfe_stat_ch; 505119917Swpaul struct bfe_hw_stats bfe_hwstats; 506119917Swpaul struct bfe_desc *bfe_tx_list, *bfe_rx_list; 507119917Swpaul struct bfe_data bfe_tx_ring[BFE_TX_LIST_CNT]; /* XXX */ 508119917Swpaul struct bfe_data bfe_rx_ring[BFE_RX_LIST_CNT]; /* XXX */ 509119917Swpaul struct mtx bfe_mtx; 510119917Swpaul u_int32_t bfe_flags; 511119917Swpaul u_int32_t bfe_imask; 512119917Swpaul u_int32_t bfe_dma_offset; 513119917Swpaul u_int32_t bfe_tx_cnt, bfe_tx_cons, bfe_tx_prod; 514119917Swpaul u_int32_t bfe_rx_cnt, bfe_rx_prod, bfe_rx_cons; 515119917Swpaul u_int32_t bfe_tx_dma, bfe_rx_dma; 516119917Swpaul u_int32_t bfe_link; 517119917Swpaul u_int8_t bfe_phyaddr; /* Address of the card's PHY */ 518119917Swpaul u_int8_t bfe_mdc_port; 519119917Swpaul u_int8_t bfe_unit; /* interface number */ 520119917Swpaul u_int8_t bfe_core_unit; 521119917Swpaul u_int8_t bfe_up; 522119917Swpaul int bfe_if_flags; 523119917Swpaul char *bfe_vpd_prodname; 524119917Swpaul char *bfe_vpd_readonly; 525119917Swpaul}; 526119917Swpaul 527119917Swpaulstruct bfe_type 528119917Swpaul{ 529119917Swpaul u_int16_t bfe_vid; 530119917Swpaul u_int16_t bfe_did; 531119917Swpaul char *bfe_name; 532119917Swpaul}; 533119917Swpaul 534119917Swpaul#endif /* _BFE_H */ 535