1139749Simp/*- 2139749Simp * Copyright (c) 2003 Stuart Walsh 3139749Simp * 4127827Swes * Redistribution and use in source and binary forms, with or without 5127827Swes * modification, are permitted provided that the following conditions 6127827Swes * are met: 7127827Swes * 1. Redistributions of source code must retain the above copyright 8127827Swes * notice, this list of conditions and the following disclaimer. 9127827Swes * 2. Redistributions in binary form must reproduce the above copyright 10127827Swes * notice, this list of conditions and the following disclaimer in the 11127827Swes * documentation and/or other materials provided with the distribution. 12127827Swes * 13127827Swes * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND 14127827Swes * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15127827Swes * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16127827Swes * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17127827Swes * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18127827Swes * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19127827Swes * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20127827Swes * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21127827Swes * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22127827Swes * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23127827Swes * SUCH DAMAGE. 24127827Swes */ 25119917Swpaul/* $FreeBSD$ */ 26119917Swpaul 27119917Swpaul#ifndef _BFE_H 28119917Swpaul#define _BFE_H 29119917Swpaul 30119917Swpaul/* PCI registers */ 31119917Swpaul#define BFE_PCI_MEMLO 0x10 32119917Swpaul#define BFE_PCI_MEMHIGH 0x14 33119917Swpaul#define BFE_PCI_INTLINE 0x3C 34119917Swpaul 35119917Swpaul/* Register layout. */ 36119917Swpaul#define BFE_DEVCTRL 0x00000000 /* Device Control */ 37119917Swpaul#define BFE_PFE 0x00000080 /* Pattern Filtering Enable */ 38119917Swpaul#define BFE_IPP 0x00000400 /* Internal EPHY Present */ 39119917Swpaul#define BFE_EPR 0x00008000 /* EPHY Reset */ 40119917Swpaul#define BFE_PME 0x00001000 /* PHY Mode Enable */ 41119917Swpaul#define BFE_PMCE 0x00002000 /* PHY Mode Clocks Enable */ 42119917Swpaul#define BFE_PADDR 0x0007c000 /* PHY Address */ 43119917Swpaul#define BFE_PADDR_SHIFT 18 44119917Swpaul 45119917Swpaul#define BFE_BIST_STAT 0x0000000C /* Built-In Self-Test Status */ 46119917Swpaul#define BFE_WKUP_LEN 0x00000010 /* Wakeup Length */ 47119917Swpaul 48119917Swpaul#define BFE_ISTAT 0x00000020 /* Interrupt Status */ 49119917Swpaul#define BFE_ISTAT_PME 0x00000040 /* Power Management Event */ 50119917Swpaul#define BFE_ISTAT_TO 0x00000080 /* General Purpose Timeout */ 51119917Swpaul#define BFE_ISTAT_DSCE 0x00000400 /* Descriptor Error */ 52119917Swpaul#define BFE_ISTAT_DATAE 0x00000800 /* Data Error */ 53119917Swpaul#define BFE_ISTAT_DPE 0x00001000 /* Descr. Protocol Error */ 54119917Swpaul#define BFE_ISTAT_RDU 0x00002000 /* Receive Descr. Underflow */ 55119917Swpaul#define BFE_ISTAT_RFO 0x00004000 /* Receive FIFO Overflow */ 56119917Swpaul#define BFE_ISTAT_TFU 0x00008000 /* Transmit FIFO Underflow */ 57119917Swpaul#define BFE_ISTAT_RX 0x00010000 /* RX Interrupt */ 58119917Swpaul#define BFE_ISTAT_TX 0x01000000 /* TX Interrupt */ 59119917Swpaul#define BFE_ISTAT_EMAC 0x04000000 /* EMAC Interrupt */ 60119917Swpaul#define BFE_ISTAT_MII_WRITE 0x08000000 /* MII Write Interrupt */ 61119917Swpaul#define BFE_ISTAT_MII_READ 0x10000000 /* MII Read Interrupt */ 62119917Swpaul#define BFE_ISTAT_ERRORS (BFE_ISTAT_DSCE | BFE_ISTAT_DATAE | BFE_ISTAT_DPE |\ 63133282Sdes BFE_ISTAT_RDU | BFE_ISTAT_RFO | BFE_ISTAT_TFU) 64119917Swpaul 65119917Swpaul#define BFE_IMASK 0x00000024 /* Interrupt Mask */ 66119917Swpaul#define BFE_IMASK_DEF (BFE_ISTAT_ERRORS | BFE_ISTAT_TO | BFE_ISTAT_RX | \ 67133282Sdes BFE_ISTAT_TX) 68119917Swpaul 69119917Swpaul#define BFE_MAC_CTRL 0x000000A8 /* MAC Control */ 70119917Swpaul#define BFE_CTRL_CRC32_ENAB 0x00000001 /* CRC32 Generation Enable */ 71119917Swpaul#define BFE_CTRL_PDOWN 0x00000004 /* Onchip EPHY Powerdown */ 72119917Swpaul#define BFE_CTRL_EDET 0x00000008 /* Onchip EPHY Energy Detected */ 73119917Swpaul#define BFE_CTRL_LED 0x000000e0 /* Onchip EPHY LED Control */ 74119917Swpaul#define BFE_CTRL_LED_SHIFT 5 75119917Swpaul 76175787Syongari#define BFE_MAC_FLOW 0x000000AC /* MAC Flow Control */ 77175787Syongari#define BFE_FLOW_RX_HIWAT 0x000000ff /* Onchip FIFO HI Water Mark */ 78175787Syongari#define BFE_FLOW_PAUSE_ENAB 0x00008000 /* Enable Pause Frame Generation */ 79175787Syongari 80119917Swpaul#define BFE_RCV_LAZY 0x00000100 /* Lazy Interrupt Control */ 81119917Swpaul#define BFE_LAZY_TO_MASK 0x00ffffff /* Timeout */ 82119917Swpaul#define BFE_LAZY_FC_MASK 0xff000000 /* Frame Count */ 83119917Swpaul#define BFE_LAZY_FC_SHIFT 24 84119917Swpaul 85119917Swpaul#define BFE_DMATX_CTRL 0x00000200 /* DMA TX Control */ 86119917Swpaul#define BFE_TX_CTRL_ENABLE 0x00000001 /* Enable */ 87119917Swpaul#define BFE_TX_CTRL_SUSPEND 0x00000002 /* Suepend Request */ 88119917Swpaul#define BFE_TX_CTRL_LPBACK 0x00000004 /* Loopback Enable */ 89119917Swpaul#define BFE_TX_CTRL_FAIRPRI 0x00000008 /* Fair Priority */ 90119917Swpaul#define BFE_TX_CTRL_FLUSH 0x00000010 /* Flush Request */ 91119917Swpaul 92119917Swpaul#define BFE_DMATX_ADDR 0x00000204 /* DMA TX Descriptor Ring Address */ 93119917Swpaul#define BFE_DMATX_PTR 0x00000208 /* DMA TX Last Posted Descriptor */ 94119917Swpaul#define BFE_DMATX_STAT 0x0000020C /* DMA TX Current Active Desc. + Status */ 95119917Swpaul#define BFE_STAT_CDMASK 0x00000fff /* Current Descriptor Mask */ 96119917Swpaul#define BFE_STAT_SMASK 0x0000f000 /* State Mask */ 97119917Swpaul#define BFE_STAT_DISABLE 0x00000000 /* State Disabled */ 98119917Swpaul#define BFE_STAT_SACTIVE 0x00001000 /* State Active */ 99119917Swpaul#define BFE_STAT_SIDLE 0x00002000 /* State Idle Wait */ 100119917Swpaul#define BFE_STAT_STOPPED 0x00003000 /* State Stopped */ 101119917Swpaul#define BFE_STAT_SSUSP 0x00004000 /* State Suspend Pending */ 102119917Swpaul#define BFE_STAT_EMASK 0x000f0000 /* Error Mask */ 103119917Swpaul#define BFE_STAT_ENONE 0x00000000 /* Error None */ 104119917Swpaul#define BFE_STAT_EDPE 0x00010000 /* Error Desc. Protocol Error */ 105119917Swpaul#define BFE_STAT_EDFU 0x00020000 /* Error Data FIFO Underrun */ 106119917Swpaul#define BFE_STAT_EBEBR 0x00030000 /* Error Bus Error on Buffer Read */ 107119917Swpaul#define BFE_STAT_EBEDA 0x00040000 /* Error Bus Error on Desc. Access */ 108119917Swpaul#define BFE_STAT_FLUSHED 0x00100000 /* Flushed */ 109119917Swpaul 110119917Swpaul#define BFE_DMARX_CTRL 0x00000210 /* DMA RX Control */ 111119917Swpaul#define BFE_RX_CTRL_ENABLE 0x00000001 /* Enable */ 112119917Swpaul#define BFE_RX_CTRL_ROMASK 0x000000fe /* Receive Offset Mask */ 113119917Swpaul#define BFE_RX_CTRL_ROSHIFT 1 /* Receive Offset Shift */ 114119917Swpaul 115119917Swpaul#define BFE_DMARX_ADDR 0x00000214 /* DMA RX Descriptor Ring Address */ 116119917Swpaul#define BFE_DMARX_PTR 0x00000218 /* DMA RX Last Posted Descriptor */ 117119917Swpaul#define BFE_DMARX_STAT 0x0000021C /* DMA RX Current Active Desc. + Status */ 118119917Swpaul 119119917Swpaul#define BFE_RXCONF 0x00000400 /* EMAC RX Config */ 120119917Swpaul#define BFE_RXCONF_DBCAST 0x00000001 /* Disable Broadcast */ 121119917Swpaul#define BFE_RXCONF_ALLMULTI 0x00000002 /* Accept All Multicast */ 122119917Swpaul#define BFE_RXCONF_NORXTX 0x00000004 /* Receive Disable While Transmitting */ 123119917Swpaul#define BFE_RXCONF_PROMISC 0x00000008 /* Promiscuous Enable */ 124119917Swpaul#define BFE_RXCONF_LPBACK 0x00000010 /* Loopback Enable */ 125119917Swpaul#define BFE_RXCONF_FLOW 0x00000020 /* Flow Control Enable */ 126119917Swpaul#define BFE_RXCONF_ACCEPT 0x00000040 /* Accept Unicast Flow Control Frame */ 127119917Swpaul#define BFE_RXCONF_RFILT 0x00000080 /* Reject Filter */ 128119917Swpaul 129119917Swpaul#define BFE_RXMAXLEN 0x00000404 /* EMAC RX Max Packet Length */ 130119917Swpaul#define BFE_TXMAXLEN 0x00000408 /* EMAC TX Max Packet Length */ 131119917Swpaul 132119917Swpaul#define BFE_MDIO_CTRL 0x00000410 /* EMAC MDIO Control */ 133119917Swpaul#define BFE_MDIO_MAXF_MASK 0x0000007f /* MDC Frequency */ 134119917Swpaul#define BFE_MDIO_PREAMBLE 0x00000080 /* MII Preamble Enable */ 135119917Swpaul 136119917Swpaul#define BFE_MDIO_DATA 0x00000414 /* EMAC MDIO Data */ 137119917Swpaul#define BFE_MDIO_DATA_DATA 0x0000ffff /* R/W Data */ 138119917Swpaul#define BFE_MDIO_TA_MASK 0x00030000 /* Turnaround Value */ 139119917Swpaul#define BFE_MDIO_TA_SHIFT 16 140119917Swpaul#define BFE_MDIO_TA_VALID 2 141119917Swpaul 142119917Swpaul#define BFE_MDIO_RA_MASK 0x007c0000 /* Register Address */ 143119917Swpaul#define BFE_MDIO_PMD_MASK 0x0f800000 /* Physical Media Device */ 144119917Swpaul#define BFE_MDIO_OP_MASK 0x30000000 /* Opcode */ 145119917Swpaul#define BFE_MDIO_SB_MASK 0xc0000000 /* Start Bits */ 146119917Swpaul#define BFE_MDIO_SB_START 0x40000000 /* Start Of Frame */ 147119917Swpaul#define BFE_MDIO_RA_SHIFT 18 148119917Swpaul#define BFE_MDIO_PMD_SHIFT 23 149119917Swpaul#define BFE_MDIO_OP_SHIFT 28 150119917Swpaul#define BFE_MDIO_OP_WRITE 1 151119917Swpaul#define BFE_MDIO_OP_READ 2 152119917Swpaul#define BFE_MDIO_SB_SHIFT 30 153119917Swpaul 154119917Swpaul#define BFE_EMAC_IMASK 0x00000418 /* EMAC Interrupt Mask */ 155119917Swpaul#define BFE_EMAC_ISTAT 0x0000041C /* EMAC Interrupt Status */ 156119917Swpaul#define BFE_EMAC_INT_MII 0x00000001 /* MII MDIO Interrupt */ 157119917Swpaul#define BFE_EMAC_INT_MIB 0x00000002 /* MIB Interrupt */ 158119917Swpaul#define BFE_EMAC_INT_FLOW 0x00000003 /* Flow Control Interrupt */ 159119917Swpaul 160119917Swpaul#define BFE_CAM_DATA_LO 0x00000420 /* EMAC CAM Data Low */ 161119917Swpaul#define BFE_CAM_DATA_HI 0x00000424 /* EMAC CAM Data High */ 162119917Swpaul#define BFE_CAM_HI_VALID 0x00010000 /* Valid Bit */ 163119917Swpaul 164119917Swpaul#define BFE_CAM_CTRL 0x00000428 /* EMAC CAM Control */ 165119917Swpaul#define BFE_CAM_ENABLE 0x00000001 /* CAM Enable */ 166119917Swpaul#define BFE_CAM_MSEL 0x00000002 /* Mask Select */ 167119917Swpaul#define BFE_CAM_READ 0x00000004 /* Read */ 168119917Swpaul#define BFE_CAM_WRITE 0x00000008 /* Read */ 169119917Swpaul#define BFE_CAM_INDEX_MASK 0x003f0000 /* Index Mask */ 170119917Swpaul#define BFE_CAM_BUSY 0x80000000 /* CAM Busy */ 171119917Swpaul#define BFE_CAM_INDEX_SHIFT 16 172119917Swpaul 173119917Swpaul#define BFE_ENET_CTRL 0x0000042C /* EMAC ENET Control */ 174119917Swpaul#define BFE_ENET_ENABLE 0x00000001 /* EMAC Enable */ 175119917Swpaul#define BFE_ENET_DISABLE 0x00000002 /* EMAC Disable */ 176119917Swpaul#define BFE_ENET_SRST 0x00000004 /* EMAC Soft Reset */ 177119917Swpaul#define BFE_ENET_EPSEL 0x00000008 /* External PHY Select */ 178119917Swpaul 179119917Swpaul#define BFE_TX_CTRL 0x00000430 /* EMAC TX Control */ 180119917Swpaul#define BFE_TX_DUPLEX 0x00000001 /* Full Duplex */ 181119917Swpaul#define BFE_TX_FMODE 0x00000002 /* Flow Mode */ 182119917Swpaul#define BFE_TX_SBENAB 0x00000004 /* Single Backoff Enable */ 183119917Swpaul#define BFE_TX_SMALL_SLOT 0x00000008 /* Small Slottime */ 184119917Swpaul 185119917Swpaul#define BFE_TX_WMARK 0x00000434 /* EMAC TX Watermark */ 186119917Swpaul 187119917Swpaul#define BFE_MIB_CTRL 0x00000438 /* EMAC MIB Control */ 188119917Swpaul#define BFE_MIB_CLR_ON_READ 0x00000001 /* Autoclear on Read */ 189119917Swpaul 190119917Swpaul/* Status registers */ 191119917Swpaul#define BFE_TX_GOOD_O 0x00000500 /* MIB TX Good Octets */ 192119917Swpaul#define BFE_TX_GOOD_P 0x00000504 /* MIB TX Good Packets */ 193119917Swpaul#define BFE_TX_O 0x00000508 /* MIB TX Octets */ 194119917Swpaul#define BFE_TX_P 0x0000050C /* MIB TX Packets */ 195119917Swpaul#define BFE_TX_BCAST 0x00000510 /* MIB TX Broadcast Packets */ 196119917Swpaul#define BFE_TX_MCAST 0x00000514 /* MIB TX Multicast Packets */ 197119917Swpaul#define BFE_TX_64 0x00000518 /* MIB TX <= 64 byte Packets */ 198119917Swpaul#define BFE_TX_65_127 0x0000051C /* MIB TX 65 to 127 byte Packets */ 199119917Swpaul#define BFE_TX_128_255 0x00000520 /* MIB TX 128 to 255 byte Packets */ 200119917Swpaul#define BFE_TX_256_511 0x00000524 /* MIB TX 256 to 511 byte Packets */ 201119917Swpaul#define BFE_TX_512_1023 0x00000528 /* MIB TX 512 to 1023 byte Packets */ 202119917Swpaul#define BFE_TX_1024_MAX 0x0000052C /* MIB TX 1024 to max byte Packets */ 203119917Swpaul#define BFE_TX_JABBER 0x00000530 /* MIB TX Jabber Packets */ 204119917Swpaul#define BFE_TX_OSIZE 0x00000534 /* MIB TX Oversize Packets */ 205119917Swpaul#define BFE_TX_FRAG 0x00000538 /* MIB TX Fragment Packets */ 206119917Swpaul#define BFE_TX_URUNS 0x0000053C /* MIB TX Underruns */ 207119917Swpaul#define BFE_TX_TCOLS 0x00000540 /* MIB TX Total Collisions */ 208119917Swpaul#define BFE_TX_SCOLS 0x00000544 /* MIB TX Single Collisions */ 209119917Swpaul#define BFE_TX_MCOLS 0x00000548 /* MIB TX Multiple Collisions */ 210119917Swpaul#define BFE_TX_ECOLS 0x0000054C /* MIB TX Excessive Collisions */ 211119917Swpaul#define BFE_TX_LCOLS 0x00000550 /* MIB TX Late Collisions */ 212119917Swpaul#define BFE_TX_DEFERED 0x00000554 /* MIB TX Defered Packets */ 213119917Swpaul#define BFE_TX_CLOST 0x00000558 /* MIB TX Carrier Lost */ 214119917Swpaul#define BFE_TX_PAUSE 0x0000055C /* MIB TX Pause Packets */ 215119917Swpaul#define BFE_RX_GOOD_O 0x00000580 /* MIB RX Good Octets */ 216119917Swpaul#define BFE_RX_GOOD_P 0x00000584 /* MIB RX Good Packets */ 217119917Swpaul#define BFE_RX_O 0x00000588 /* MIB RX Octets */ 218119917Swpaul#define BFE_RX_P 0x0000058C /* MIB RX Packets */ 219119917Swpaul#define BFE_RX_BCAST 0x00000590 /* MIB RX Broadcast Packets */ 220119917Swpaul#define BFE_RX_MCAST 0x00000594 /* MIB RX Multicast Packets */ 221119917Swpaul#define BFE_RX_64 0x00000598 /* MIB RX <= 64 byte Packets */ 222119917Swpaul#define BFE_RX_65_127 0x0000059C /* MIB RX 65 to 127 byte Packets */ 223119917Swpaul#define BFE_RX_128_255 0x000005A0 /* MIB RX 128 to 255 byte Packets */ 224119917Swpaul#define BFE_RX_256_511 0x000005A4 /* MIB RX 256 to 511 byte Packets */ 225119917Swpaul#define BFE_RX_512_1023 0x000005A8 /* MIB RX 512 to 1023 byte Packets */ 226119917Swpaul#define BFE_RX_1024_MAX 0x000005AC /* MIB RX 1024 to max byte Packets */ 227119917Swpaul#define BFE_RX_JABBER 0x000005B0 /* MIB RX Jabber Packets */ 228119917Swpaul#define BFE_RX_OSIZE 0x000005B4 /* MIB RX Oversize Packets */ 229119917Swpaul#define BFE_RX_FRAG 0x000005B8 /* MIB RX Fragment Packets */ 230119917Swpaul#define BFE_RX_MISS 0x000005BC /* MIB RX Missed Packets */ 231119917Swpaul#define BFE_RX_CRCA 0x000005C0 /* MIB RX CRC Align Errors */ 232119917Swpaul#define BFE_RX_USIZE 0x000005C4 /* MIB RX Undersize Packets */ 233119917Swpaul#define BFE_RX_CRC 0x000005C8 /* MIB RX CRC Errors */ 234119917Swpaul#define BFE_RX_ALIGN 0x000005CC /* MIB RX Align Errors */ 235119917Swpaul#define BFE_RX_SYM 0x000005D0 /* MIB RX Symbol Errors */ 236119917Swpaul#define BFE_RX_PAUSE 0x000005D4 /* MIB RX Pause Packets */ 237119917Swpaul#define BFE_RX_NPAUSE 0x000005D8 /* MIB RX Non-Pause Packets */ 238119917Swpaul 239119917Swpaul#define BFE_SBIMSTATE 0x00000F90 /* BFE_SB Initiator Agent State */ 240119917Swpaul#define BFE_PC 0x0000000f /* Pipe Count */ 241119917Swpaul#define BFE_AP_MASK 0x00000030 /* Arbitration Priority */ 242119917Swpaul#define BFE_AP_BOTH 0x00000000 /* Use both timeslices and token */ 243119917Swpaul#define BFE_AP_TS 0x00000010 /* Use timeslices only */ 244119917Swpaul#define BFE_AP_TK 0x00000020 /* Use token only */ 245119917Swpaul#define BFE_AP_RSV 0x00000030 /* Reserved */ 246119917Swpaul#define BFE_IBE 0x00020000 /* In Band Error */ 247119917Swpaul#define BFE_TO 0x00040000 /* Timeout */ 248119917Swpaul 249119917Swpaul 250119917Swpaul/* Seems the bcm440x has a fairly generic core, we only need be concerned with 251119917Swpaul * a couple of these 252119917Swpaul */ 253119917Swpaul#define BFE_SBINTVEC 0x00000F94 /* BFE_SB Interrupt Mask */ 254119917Swpaul#define BFE_INTVEC_PCI 0x00000001 /* Enable interrupts for PCI */ 255119917Swpaul#define BFE_INTVEC_ENET0 0x00000002 /* Enable interrupts for enet 0 */ 256119917Swpaul#define BFE_INTVEC_ILINE20 0x00000004 /* Enable interrupts for iline20 */ 257119917Swpaul#define BFE_INTVEC_CODEC 0x00000008 /* Enable interrupts for v90 codec */ 258119917Swpaul#define BFE_INTVEC_USB 0x00000010 /* Enable interrupts for usb */ 259119917Swpaul#define BFE_INTVEC_EXTIF 0x00000020 /* Enable interrupts for external i/f */ 260119917Swpaul#define BFE_INTVEC_ENET1 0x00000040 /* Enable interrupts for enet 1 */ 261119917Swpaul 262119917Swpaul#define BFE_SBTMSLOW 0x00000F98 /* BFE_SB Target State Low */ 263119917Swpaul#define BFE_RESET 0x00000001 /* Reset */ 264119917Swpaul#define BFE_REJECT 0x00000002 /* Reject */ 265119917Swpaul#define BFE_CLOCK 0x00010000 /* Clock Enable */ 266119917Swpaul#define BFE_FGC 0x00020000 /* Force Gated Clocks On */ 267119917Swpaul#define BFE_PE 0x40000000 /* Power Management Enable */ 268119917Swpaul#define BFE_BE 0x80000000 /* BIST Enable */ 269119917Swpaul 270119917Swpaul#define BFE_SBTMSHIGH 0x00000F9C /* BFE_SB Target State High */ 271119917Swpaul#define BFE_SERR 0x00000001 /* S-error */ 272119917Swpaul#define BFE_INT 0x00000002 /* Interrupt */ 273119917Swpaul#define BFE_BUSY 0x00000004 /* Busy */ 274119917Swpaul#define BFE_GCR 0x20000000 /* Gated Clock Request */ 275119917Swpaul#define BFE_BISTF 0x40000000 /* BIST Failed */ 276119917Swpaul#define BFE_BISTD 0x80000000 /* BIST Done */ 277119917Swpaul 278119917Swpaul#define BFE_SBBWA0 0x00000FA0 /* BFE_SB Bandwidth Allocation Table 0 */ 279119917Swpaul#define BFE_TAB0_MASK 0x0000ffff /* Lookup Table 0 */ 280119917Swpaul#define BFE_TAB1_MASK 0xffff0000 /* Lookup Table 0 */ 281119917Swpaul#define BFE_TAB0_SHIFT 0 282119917Swpaul#define BFE_TAB1_SHIFT 16 283119917Swpaul 284119917Swpaul#define BFE_SBIMCFGLOW 0x00000FA8 /* BFE_SB Initiator Configuration Low */ 285119917Swpaul#define BFE_STO_MASK 0x00000003 /* Service Timeout */ 286119917Swpaul#define BFE_RTO_MASK 0x00000030 /* Request Timeout */ 287119917Swpaul#define BFE_CID_MASK 0x00ff0000 /* Connection ID */ 288119917Swpaul#define BFE_RTO_SHIFT 4 289119917Swpaul#define BFE_CID_SHIFT 16 290119917Swpaul 291119917Swpaul#define BFE_SBIMCFGHIGH 0x00000FAC /* BFE_SB Initiator Configuration High */ 292119917Swpaul#define BFE_IEM_MASK 0x0000000c /* Inband Error Mode */ 293119917Swpaul#define BFE_TEM_MASK 0x00000030 /* Timeout Error Mode */ 294119917Swpaul#define BFE_BEM_MASK 0x000000c0 /* Bus Error Mode */ 295119917Swpaul#define BFE_TEM_SHIFT 4 296119917Swpaul#define BFE_BEM_SHIFT 6 297119917Swpaul 298119917Swpaul#define BFE_SBTMCFGLOW 0x00000FB8 /* BFE_SB Target Configuration Low */ 299119917Swpaul#define BFE_LOW_CD_MASK 0x000000ff /* Clock Divide Mask */ 300119917Swpaul#define BFE_LOW_CO_MASK 0x0000f800 /* Clock Offset Mask */ 301119917Swpaul#define BFE_LOW_IF_MASK 0x00fc0000 /* Interrupt Flags Mask */ 302119917Swpaul#define BFE_LOW_IM_MASK 0x03000000 /* Interrupt Mode Mask */ 303119917Swpaul#define BFE_LOW_CO_SHIFT 11 304119917Swpaul#define BFE_LOW_IF_SHIFT 18 305119917Swpaul#define BFE_LOW_IM_SHIFT 24 306119917Swpaul 307119917Swpaul#define BFE_SBTMCFGHIGH 0x00000FBC /* BFE_SB Target Configuration High */ 308119917Swpaul#define BFE_HIGH_BM_MASK 0x00000003 /* Busy Mode */ 309119917Swpaul#define BFE_HIGH_RM_MASK 0x0000000C /* Retry Mode */ 310119917Swpaul#define BFE_HIGH_SM_MASK 0x00000030 /* Stop Mode */ 311119917Swpaul#define BFE_HIGH_EM_MASK 0x00000300 /* Error Mode */ 312119917Swpaul#define BFE_HIGH_IM_MASK 0x00000c00 /* Interrupt Mode */ 313119917Swpaul#define BFE_HIGH_RM_SHIFT 2 314119917Swpaul#define BFE_HIGH_SM_SHIFT 4 315119917Swpaul#define BFE_HIGH_EM_SHIFT 8 316119917Swpaul#define BFE_HIGH_IM_SHIFT 10 317119917Swpaul 318119917Swpaul#define BFE_SBBCFG 0x00000FC0 /* BFE_SB Broadcast Configuration */ 319119917Swpaul#define BFE_LAT_MASK 0x00000003 /* BFE_SB Latency */ 320119917Swpaul#define BFE_MAX0_MASK 0x000f0000 /* MAX Counter 0 */ 321119917Swpaul#define BFE_MAX1_MASK 0x00f00000 /* MAX Counter 1 */ 322119917Swpaul#define BFE_MAX0_SHIFT 16 323119917Swpaul#define BFE_MAX1_SHIFT 20 324119917Swpaul 325119917Swpaul#define BFE_SBBSTATE 0x00000FC8 /* BFE_SB Broadcast State */ 326119917Swpaul#define BFE_SBBSTATE_SRD 0x00000001 /* ST Reg Disable */ 327119917Swpaul#define BFE_SBBSTATE_HRD 0x00000002 /* Hold Reg Disable */ 328119917Swpaul 329119917Swpaul#define BFE_SBACTCNFG 0x00000FD8 /* BFE_SB Activate Configuration */ 330119917Swpaul#define BFE_SBFLAGST 0x00000FE8 /* BFE_SB Current BFE_SBFLAGS */ 331119917Swpaul 332119917Swpaul#define BFE_SBIDLOW 0x00000FF8 /* BFE_SB Identification Low */ 333119917Swpaul#define BFE_CS_MASK 0x00000003 /* Config Space Mask */ 334119917Swpaul#define BFE_AR_MASK 0x00000038 /* Num Address Ranges Supported */ 335119917Swpaul#define BFE_SYNCH 0x00000040 /* Sync */ 336119917Swpaul#define BFE_INIT 0x00000080 /* Initiator */ 337119917Swpaul#define BFE_MINLAT_MASK 0x00000f00 /* Minimum Backplane Latency */ 338119917Swpaul#define BFE_MAXLAT_MASK 0x0000f000 /* Maximum Backplane Latency */ 339119917Swpaul#define BFE_FIRST 0x00010000 /* This Initiator is First */ 340119917Swpaul#define BFE_CW_MASK 0x000c0000 /* Cycle Counter Width */ 341119917Swpaul#define BFE_TP_MASK 0x00f00000 /* Target Ports */ 342119917Swpaul#define BFE_IP_MASK 0x0f000000 /* Initiator Ports */ 343119917Swpaul#define BFE_AR_SHIFT 3 344119917Swpaul#define BFE_MINLAT_SHIFT 8 345119917Swpaul#define BFE_MAXLAT_SHIFT 12 346119917Swpaul#define BFE_CW_SHIFT 18 347119917Swpaul#define BFE_TP_SHIFT 20 348119917Swpaul#define BFE_IP_SHIFT 24 349119917Swpaul 350119917Swpaul#define BFE_SBIDHIGH 0x00000FFC /* BFE_SB Identification High */ 351119917Swpaul#define BFE_RC_MASK 0x0000000f /* Revision Code */ 352119917Swpaul#define BFE_CC_MASK 0x0000fff0 /* Core Code */ 353119917Swpaul#define BFE_VC_MASK 0xffff0000 /* Vendor Code */ 354119917Swpaul#define BFE_CC_SHIFT 4 355119917Swpaul#define BFE_VC_SHIFT 16 356119917Swpaul 357119917Swpaul#define BFE_CORE_ILINE20 0x801 358119917Swpaul#define BFE_CORE_SDRAM 0x803 359119917Swpaul#define BFE_CORE_PCI 0x804 360119917Swpaul#define BFE_CORE_MIPS 0x805 361119917Swpaul#define BFE_CORE_ENET 0x806 362119917Swpaul#define BFE_CORE_CODEC 0x807 363119917Swpaul#define BFE_CORE_USB 0x808 364119917Swpaul#define BFE_CORE_ILINE100 0x80a 365119917Swpaul#define BFE_CORE_EXTIF 0x811 366119917Swpaul 367119917Swpaul/* SSB PCI config space registers. */ 368119917Swpaul#define BFE_BAR0_WIN 0x80 369119917Swpaul#define BFE_BAR1_WIN 0x84 370119917Swpaul#define BFE_SPROM_CONTROL 0x88 371119917Swpaul#define BFE_BAR1_CONTROL 0x8c 372119917Swpaul 373119917Swpaul/* SSB core and hsot control registers. */ 374119917Swpaul#define BFE_SSB_CONTROL 0x00000000 375119917Swpaul#define BFE_SSB_ARBCONTROL 0x00000010 376119917Swpaul#define BFE_SSB_ISTAT 0x00000020 377119917Swpaul#define BFE_SSB_IMASK 0x00000024 378119917Swpaul#define BFE_SSB_MBOX 0x00000028 379119917Swpaul#define BFE_SSB_BCAST_ADDR 0x00000050 380119917Swpaul#define BFE_SSB_BCAST_DATA 0x00000054 381119917Swpaul#define BFE_SSB_PCI_TRANS_0 0x00000100 382119917Swpaul#define BFE_SSB_PCI_TRANS_1 0x00000104 383119917Swpaul#define BFE_SSB_PCI_TRANS_2 0x00000108 384119917Swpaul#define BFE_SSB_SPROM 0x00000800 385119917Swpaul 386119917Swpaul#define BFE_SSB_PCI_MEM 0x00000000 387119917Swpaul#define BFE_SSB_PCI_IO 0x00000001 388119917Swpaul#define BFE_SSB_PCI_CFG0 0x00000002 389119917Swpaul#define BFE_SSB_PCI_CFG1 0x00000003 390119917Swpaul#define BFE_SSB_PCI_PREF 0x00000004 391119917Swpaul#define BFE_SSB_PCI_BURST 0x00000008 392119917Swpaul#define BFE_SSB_PCI_MASK0 0xfc000000 393119917Swpaul#define BFE_SSB_PCI_MASK1 0xfc000000 394119917Swpaul#define BFE_SSB_PCI_MASK2 0xc0000000 395119917Swpaul 396119917Swpaul#define BFE_DESC_LEN 0x00001fff 397119917Swpaul#define BFE_DESC_CMASK 0x0ff00000 /* Core specific bits */ 398119917Swpaul#define BFE_DESC_EOT 0x10000000 /* End of Table */ 399119917Swpaul#define BFE_DESC_IOC 0x20000000 /* Interrupt On Completion */ 400119917Swpaul#define BFE_DESC_EOF 0x40000000 /* End of Frame */ 401119917Swpaul#define BFE_DESC_SOF 0x80000000 /* Start of Frame */ 402119917Swpaul 403119917Swpaul#define BFE_RX_CP_THRESHOLD 256 404119917Swpaul#define BFE_RX_HEADER_LEN 28 405119917Swpaul 406119917Swpaul#define BFE_RX_FLAG_OFIFO 0x00000001 /* FIFO Overflow */ 407119917Swpaul#define BFE_RX_FLAG_CRCERR 0x00000002 /* CRC Error */ 408119917Swpaul#define BFE_RX_FLAG_SERR 0x00000004 /* Receive Symbol Error */ 409119917Swpaul#define BFE_RX_FLAG_ODD 0x00000008 /* Frame has odd number of nibbles */ 410119917Swpaul#define BFE_RX_FLAG_LARGE 0x00000010 /* Frame is > RX MAX Length */ 411119917Swpaul#define BFE_RX_FLAG_MCAST 0x00000020 /* Dest is Multicast Address */ 412119917Swpaul#define BFE_RX_FLAG_BCAST 0x00000040 /* Dest is Broadcast Address */ 413119917Swpaul#define BFE_RX_FLAG_MISS 0x00000080 /* Received due to promisc mode */ 414119917Swpaul#define BFE_RX_FLAG_LAST 0x00000800 /* Last buffer in frame */ 415119917Swpaul#define BFE_RX_FLAG_ERRORS (BFE_RX_FLAG_ODD | BFE_RX_FLAG_SERR | \ 416133282Sdes BFE_RX_FLAG_CRCERR | BFE_RX_FLAG_OFIFO) 417119917Swpaul 418119917Swpaul#define BFE_MCAST_TBL_SIZE 32 419119917Swpaul#define BFE_PCI_DMA 0x40000000 420119917Swpaul#define BFE_REG_PCI 0x18002000 421119917Swpaul 422119917Swpaul#define BCOM_VENDORID 0x14E4 423119917Swpaul#define BCOM_DEVICEID_BCM4401 0x4401 424134590Sdes#define BCOM_DEVICEID_BCM4401B0 0x170c 425119917Swpaul 426119917Swpaul#define PCI_SETBIT(dev, reg, x, s) \ 427119917Swpaul pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | (x)), s) 428119917Swpaul#define PCI_CLRBIT(dev, reg, x, s) \ 429119917Swpaul pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s) 430119917Swpaul 431159015Ssilby#define BFE_TX_LIST_CNT 128 432159015Ssilby#define BFE_RX_LIST_CNT 128 433119917Swpaul#define BFE_TX_LIST_SIZE BFE_TX_LIST_CNT * sizeof(struct bfe_desc) 434119917Swpaul#define BFE_RX_LIST_SIZE BFE_RX_LIST_CNT * sizeof(struct bfe_desc) 435119917Swpaul#define BFE_RX_OFFSET 30 436119917Swpaul#define BFE_TX_QLEN 256 437119917Swpaul 438181953Syongari#define BFE_RX_RING_ALIGN 4096 439181953Syongari#define BFE_TX_RING_ALIGN 4096 440181953Syongari#define BFE_MAXTXSEGS 16 441181953Syongari#define BFE_DMA_MAXADDR 0x3FFFFFFF /* 1GB DMA address limit. */ 442181953Syongari#define BFE_ADDR_LO(x) ((uint64_t)(x) & 0xFFFFFFFF) 443119917Swpaul 444181953Syongari#define CSR_READ_4(sc, reg) bus_read_4(sc->bfe_res, reg) 445119917Swpaul 446181953Syongari#define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->bfe_res, reg, val) 447181953Syongari 448119917Swpaul#define BFE_OR(sc, name, val) \ 449133282Sdes CSR_WRITE_4(sc, name, CSR_READ_4(sc, name) | val) 450119917Swpaul 451119917Swpaul#define BFE_AND(sc, name, val) \ 452133282Sdes CSR_WRITE_4(sc, name, CSR_READ_4(sc, name) & val) 453119917Swpaul 454136804Smtm#define BFE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->bfe_mtx, MA_OWNED) 455136804Smtm#define BFE_LOCK(_sc) mtx_lock(&(_sc)->bfe_mtx) 456136804Smtm#define BFE_UNLOCK(_sc) mtx_unlock(&(_sc)->bfe_mtx) 457119917Swpaul 458119917Swpaul#define BFE_INC(x, y) (x) = ((x) == ((y)-1)) ? 0 : (x)+1 459119917Swpaul 460181953Syongaristruct bfe_tx_data { 461119917Swpaul struct mbuf *bfe_mbuf; 462119917Swpaul bus_dmamap_t bfe_map; 463119917Swpaul}; 464119917Swpaul 465181953Syongaristruct bfe_rx_data { 466181953Syongari struct mbuf *bfe_mbuf; 467181953Syongari bus_dmamap_t bfe_map; 468181953Syongari u_int32_t bfe_ctrl; 469181953Syongari}; 470181953Syongari 471119917Swpaulstruct bfe_desc { 472119917Swpaul u_int32_t bfe_ctrl; 473119917Swpaul u_int32_t bfe_addr; 474119917Swpaul}; 475119917Swpaul 476119917Swpaulstruct bfe_rxheader { 477119917Swpaul u_int16_t len; 478119917Swpaul u_int16_t flags; 479119917Swpaul u_int16_t pad[12]; 480119917Swpaul}; 481119917Swpaul 482181994Syongari#define MIB_TX_GOOD_O 0 483181994Syongari#define MIB_TX_GOOD_P 1 484181994Syongari#define MIB_TX_O 2 485181994Syongari#define MIB_TX_P 3 486181994Syongari#define MIB_TX_BCAST 4 487181994Syongari#define MIB_TX_MCAST 5 488181994Syongari#define MIB_TX_64 6 489181994Syongari#define MIB_TX_65_127 7 490181994Syongari#define MIB_TX_128_255 8 491181994Syongari#define MIB_TX_256_511 9 492181994Syongari#define MIB_TX_512_1023 10 493181994Syongari#define MIB_TX_1024_MAX 11 494181994Syongari#define MIB_TX_JABBER 12 495181994Syongari#define MIB_TX_OSIZE 13 496181994Syongari#define MIB_TX_FRAG 14 497181994Syongari#define MIB_TX_URUNS 15 498181994Syongari#define MIB_TX_TCOLS 16 499181994Syongari#define MIB_TX_SCOLS 17 500181994Syongari#define MIB_TX_MCOLS 18 501181994Syongari#define MIB_TX_ECOLS 19 502181994Syongari#define MIB_TX_LCOLS 20 503181994Syongari#define MIB_TX_DEFERED 21 504181994Syongari#define MIB_TX_CLOST 22 505181994Syongari#define MIB_TX_PAUSE 23 506181994Syongari#define MIB_RX_GOOD_O 24 507181994Syongari#define MIB_RX_GOOD_P 25 508181994Syongari#define MIB_RX_O 26 509181994Syongari#define MIB_RX_P 27 510181994Syongari#define MIB_RX_BCAST 28 511181994Syongari#define MIB_RX_MCAST 29 512181994Syongari#define MIB_RX_64 30 513181994Syongari#define MIB_RX_65_127 31 514181994Syongari#define MIB_RX_128_255 32 515181994Syongari#define MIB_RX_256_511 33 516181994Syongari#define MIB_RX_512_1023 34 517181994Syongari#define MIB_RX_1024_MAX 35 518181994Syongari#define MIB_RX_JABBER 36 519181994Syongari#define MIB_RX_OSIZE 37 520181994Syongari#define MIB_RX_FRAG 38 521181994Syongari#define MIB_RX_MISS 39 522181994Syongari#define MIB_RX_CRCA 40 523181994Syongari#define MIB_RX_USIZE 41 524181994Syongari#define MIB_RX_CRC 42 525181994Syongari#define MIB_RX_ALIGN 43 526181994Syongari#define MIB_RX_SYM 44 527181994Syongari#define MIB_RX_PAUSE 45 528181994Syongari#define MIB_RX_NPAUSE 46 529181994Syongari 530181994Syongari#define BFE_MIB_CNT (MIB_RX_NPAUSE - MIB_TX_GOOD_O + 1) 531181994Syongari 532119917Swpaulstruct bfe_hw_stats { 533181994Syongari uint64_t tx_good_octets; 534181994Syongari uint64_t tx_good_frames; 535181994Syongari uint64_t tx_octets; 536181994Syongari uint64_t tx_frames; 537181994Syongari uint64_t tx_bcast_frames; 538181994Syongari uint64_t tx_mcast_frames; 539181994Syongari uint64_t tx_pkts_64; 540181994Syongari uint64_t tx_pkts_65_127; 541181994Syongari uint64_t tx_pkts_128_255; 542181994Syongari uint64_t tx_pkts_256_511; 543181994Syongari uint64_t tx_pkts_512_1023; 544181994Syongari uint64_t tx_pkts_1024_max; 545181994Syongari uint32_t tx_jabbers; 546181994Syongari uint64_t tx_oversize_frames; 547181994Syongari uint64_t tx_frag_frames; 548181994Syongari uint32_t tx_underruns; 549181994Syongari uint32_t tx_colls; 550181994Syongari uint32_t tx_single_colls; 551181994Syongari uint32_t tx_multi_colls; 552181994Syongari uint32_t tx_excess_colls; 553181994Syongari uint32_t tx_late_colls; 554181994Syongari uint32_t tx_deferrals; 555181994Syongari uint32_t tx_carrier_losts; 556181994Syongari uint32_t tx_pause_frames; 557119917Swpaul 558181994Syongari uint64_t rx_good_octets; 559181994Syongari uint64_t rx_good_frames; 560181994Syongari uint64_t rx_octets; 561181994Syongari uint64_t rx_frames; 562181994Syongari uint64_t rx_bcast_frames; 563181994Syongari uint64_t rx_mcast_frames; 564181994Syongari uint64_t rx_pkts_64; 565181994Syongari uint64_t rx_pkts_65_127; 566181994Syongari uint64_t rx_pkts_128_255; 567181994Syongari uint64_t rx_pkts_256_511; 568181994Syongari uint64_t rx_pkts_512_1023; 569181994Syongari uint64_t rx_pkts_1024_max; 570181994Syongari uint32_t rx_jabbers; 571181994Syongari uint64_t rx_oversize_frames; 572181994Syongari uint64_t rx_frag_frames; 573181994Syongari uint32_t rx_missed_frames; 574181994Syongari uint32_t rx_crc_align_errs; 575181994Syongari uint32_t rx_runts; 576181994Syongari uint32_t rx_crc_errs; 577181994Syongari uint32_t rx_align_errs; 578181994Syongari uint32_t rx_symbol_errs; 579181994Syongari uint32_t rx_pause_frames; 580181994Syongari uint32_t rx_control_frames; 581119917Swpaul}; 582119917Swpaul 583133282Sdesstruct bfe_softc 584119917Swpaul{ 585147256Sbrooks struct ifnet *bfe_ifp; /* interface info */ 586119917Swpaul device_t bfe_dev; 587119917Swpaul device_t bfe_miibus; 588119917Swpaul bus_dma_tag_t bfe_tag; 589119917Swpaul bus_dma_tag_t bfe_parent_tag; 590119917Swpaul bus_dma_tag_t bfe_tx_tag, bfe_rx_tag; 591119917Swpaul bus_dmamap_t bfe_tx_map, bfe_rx_map; 592181953Syongari bus_dma_tag_t bfe_txmbuf_tag, bfe_rxmbuf_tag; 593181953Syongari bus_dmamap_t bfe_rx_sparemap; 594119917Swpaul void *bfe_intrhand; 595119917Swpaul struct resource *bfe_irq; 596119917Swpaul struct resource *bfe_res; 597175787Syongari struct callout bfe_stat_co; 598181994Syongari struct bfe_hw_stats bfe_stats; 599119917Swpaul struct bfe_desc *bfe_tx_list, *bfe_rx_list; 600181953Syongari struct bfe_tx_data bfe_tx_ring[BFE_TX_LIST_CNT]; /* XXX */ 601181953Syongari struct bfe_rx_data bfe_rx_ring[BFE_RX_LIST_CNT]; /* XXX */ 602119917Swpaul struct mtx bfe_mtx; 603119917Swpaul u_int32_t bfe_flags; 604181976Syongari#define BFE_FLAG_DETACH 0x4000 605181976Syongari#define BFE_FLAG_LINK 0x8000 606119917Swpaul u_int32_t bfe_imask; 607119917Swpaul u_int32_t bfe_dma_offset; 608119917Swpaul u_int32_t bfe_tx_cnt, bfe_tx_cons, bfe_tx_prod; 609181953Syongari u_int32_t bfe_rx_prod, bfe_rx_cons; 610119917Swpaul u_int32_t bfe_tx_dma, bfe_rx_dma; 611175787Syongari int bfe_watchdog_timer; 612119917Swpaul u_int8_t bfe_phyaddr; /* Address of the card's PHY */ 613119917Swpaul u_int8_t bfe_mdc_port; 614119917Swpaul u_int8_t bfe_core_unit; 615147256Sbrooks u_char bfe_enaddr[6]; 616119917Swpaul int bfe_if_flags; 617119917Swpaul}; 618119917Swpaul 619133282Sdesstruct bfe_type 620119917Swpaul{ 621119917Swpaul u_int16_t bfe_vid; 622119917Swpaul u_int16_t bfe_did; 623119917Swpaul char *bfe_name; 624119917Swpaul}; 625119917Swpaul 626119917Swpaul#endif /* _BFE_H */ 627