if_bfe.c revision 213893
1/*-
2 * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk>
3 * and Duncan Barclay<dmlb@dmlb.org>
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27
28#include <sys/cdefs.h>
29__FBSDID("$FreeBSD: head/sys/dev/bfe/if_bfe.c 213893 2010-10-15 14:52:11Z marius $");
30
31#include <sys/param.h>
32#include <sys/systm.h>
33#include <sys/bus.h>
34#include <sys/endian.h>
35#include <sys/kernel.h>
36#include <sys/malloc.h>
37#include <sys/mbuf.h>
38#include <sys/module.h>
39#include <sys/rman.h>
40#include <sys/socket.h>
41#include <sys/sockio.h>
42#include <sys/sysctl.h>
43
44#include <net/bpf.h>
45#include <net/if.h>
46#include <net/ethernet.h>
47#include <net/if_dl.h>
48#include <net/if_media.h>
49#include <net/if_types.h>
50#include <net/if_vlan_var.h>
51
52#include <dev/mii/mii.h>
53#include <dev/mii/miivar.h>
54
55#include <dev/pci/pcireg.h>
56#include <dev/pci/pcivar.h>
57
58#include <machine/bus.h>
59
60#include <dev/bfe/if_bfereg.h>
61
62MODULE_DEPEND(bfe, pci, 1, 1, 1);
63MODULE_DEPEND(bfe, ether, 1, 1, 1);
64MODULE_DEPEND(bfe, miibus, 1, 1, 1);
65
66/* "device miibus" required.  See GENERIC if you get errors here. */
67#include "miibus_if.h"
68
69#define BFE_DEVDESC_MAX		64	/* Maximum device description length */
70
71static struct bfe_type bfe_devs[] = {
72	{ BCOM_VENDORID, BCOM_DEVICEID_BCM4401,
73		"Broadcom BCM4401 Fast Ethernet" },
74	{ BCOM_VENDORID, BCOM_DEVICEID_BCM4401B0,
75		"Broadcom BCM4401-B0 Fast Ethernet" },
76		{ 0, 0, NULL }
77};
78
79static int  bfe_probe				(device_t);
80static int  bfe_attach				(device_t);
81static int  bfe_detach				(device_t);
82static int  bfe_suspend				(device_t);
83static int  bfe_resume				(device_t);
84static void bfe_release_resources	(struct bfe_softc *);
85static void bfe_intr				(void *);
86static int  bfe_encap				(struct bfe_softc *, struct mbuf **);
87static void bfe_start				(struct ifnet *);
88static void bfe_start_locked			(struct ifnet *);
89static int  bfe_ioctl				(struct ifnet *, u_long, caddr_t);
90static void bfe_init				(void *);
91static void bfe_init_locked			(void *);
92static void bfe_stop				(struct bfe_softc *);
93static void bfe_watchdog			(struct bfe_softc *);
94static int  bfe_shutdown			(device_t);
95static void bfe_tick				(void *);
96static void bfe_txeof				(struct bfe_softc *);
97static void bfe_rxeof				(struct bfe_softc *);
98static void bfe_set_rx_mode			(struct bfe_softc *);
99static int  bfe_list_rx_init		(struct bfe_softc *);
100static void bfe_list_tx_init		(struct bfe_softc *);
101static void bfe_discard_buf		(struct bfe_softc *, int);
102static int  bfe_list_newbuf			(struct bfe_softc *, int);
103static void bfe_rx_ring_free		(struct bfe_softc *);
104
105static void bfe_pci_setup			(struct bfe_softc *, u_int32_t);
106static int  bfe_ifmedia_upd			(struct ifnet *);
107static void bfe_ifmedia_sts			(struct ifnet *, struct ifmediareq *);
108static int  bfe_miibus_readreg		(device_t, int, int);
109static int  bfe_miibus_writereg		(device_t, int, int, int);
110static void bfe_miibus_statchg		(device_t);
111static int  bfe_wait_bit			(struct bfe_softc *, u_int32_t, u_int32_t,
112		u_long, const int);
113static void bfe_get_config			(struct bfe_softc *sc);
114static void bfe_read_eeprom			(struct bfe_softc *, u_int8_t *);
115static void bfe_stats_update		(struct bfe_softc *);
116static void bfe_clear_stats			(struct bfe_softc *);
117static int  bfe_readphy				(struct bfe_softc *, u_int32_t, u_int32_t*);
118static int  bfe_writephy			(struct bfe_softc *, u_int32_t, u_int32_t);
119static int  bfe_resetphy			(struct bfe_softc *);
120static int  bfe_setupphy			(struct bfe_softc *);
121static void bfe_chip_reset			(struct bfe_softc *);
122static void bfe_chip_halt			(struct bfe_softc *);
123static void bfe_core_reset			(struct bfe_softc *);
124static void bfe_core_disable		(struct bfe_softc *);
125static int  bfe_dma_alloc			(struct bfe_softc *);
126static void bfe_dma_free		(struct bfe_softc *sc);
127static void bfe_dma_map				(void *, bus_dma_segment_t *, int, int);
128static void bfe_cam_write			(struct bfe_softc *, u_char *, int);
129static int  sysctl_bfe_stats		(SYSCTL_HANDLER_ARGS);
130
131static device_method_t bfe_methods[] = {
132	/* Device interface */
133	DEVMETHOD(device_probe,		bfe_probe),
134	DEVMETHOD(device_attach,	bfe_attach),
135	DEVMETHOD(device_detach,	bfe_detach),
136	DEVMETHOD(device_shutdown,	bfe_shutdown),
137	DEVMETHOD(device_suspend,	bfe_suspend),
138	DEVMETHOD(device_resume,	bfe_resume),
139
140	/* bus interface */
141	DEVMETHOD(bus_print_child,	bus_generic_print_child),
142	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
143
144	/* MII interface */
145	DEVMETHOD(miibus_readreg,	bfe_miibus_readreg),
146	DEVMETHOD(miibus_writereg,	bfe_miibus_writereg),
147	DEVMETHOD(miibus_statchg,	bfe_miibus_statchg),
148
149	{ 0, 0 }
150};
151
152static driver_t bfe_driver = {
153	"bfe",
154	bfe_methods,
155	sizeof(struct bfe_softc)
156};
157
158static devclass_t bfe_devclass;
159
160DRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, 0, 0);
161DRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, 0, 0);
162
163/*
164 * Probe for a Broadcom 4401 chip.
165 */
166static int
167bfe_probe(device_t dev)
168{
169	struct bfe_type *t;
170
171	t = bfe_devs;
172
173	while (t->bfe_name != NULL) {
174		if (pci_get_vendor(dev) == t->bfe_vid &&
175		    pci_get_device(dev) == t->bfe_did) {
176			device_set_desc(dev, t->bfe_name);
177			return (BUS_PROBE_DEFAULT);
178		}
179		t++;
180	}
181
182	return (ENXIO);
183}
184
185struct bfe_dmamap_arg {
186	bus_addr_t	bfe_busaddr;
187};
188
189static int
190bfe_dma_alloc(struct bfe_softc *sc)
191{
192	struct bfe_dmamap_arg ctx;
193	struct bfe_rx_data *rd;
194	struct bfe_tx_data *td;
195	int error, i;
196
197	/*
198	 * parent tag.  Apparently the chip cannot handle any DMA address
199	 * greater than 1GB.
200	 */
201	error = bus_dma_tag_create(bus_get_dma_tag(sc->bfe_dev), /* parent */
202	    1, 0,			/* alignment, boundary */
203	    BFE_DMA_MAXADDR, 		/* lowaddr */
204	    BUS_SPACE_MAXADDR,		/* highaddr */
205	    NULL, NULL,			/* filter, filterarg */
206	    BUS_SPACE_MAXSIZE_32BIT,	/* maxsize */
207	    0,				/* nsegments */
208	    BUS_SPACE_MAXSIZE_32BIT,	/* maxsegsize */
209	    0,				/* flags */
210	    NULL, NULL,			/* lockfunc, lockarg */
211	    &sc->bfe_parent_tag);
212	if (error != 0) {
213		device_printf(sc->bfe_dev, "cannot create parent DMA tag.\n");
214		goto fail;
215	}
216
217	/* Create tag for Tx ring. */
218	error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */
219	    BFE_TX_RING_ALIGN, 0,	/* alignment, boundary */
220	    BUS_SPACE_MAXADDR, 		/* lowaddr */
221	    BUS_SPACE_MAXADDR,		/* highaddr */
222	    NULL, NULL,			/* filter, filterarg */
223	    BFE_TX_LIST_SIZE,		/* maxsize */
224	    1,				/* nsegments */
225	    BFE_TX_LIST_SIZE,		/* maxsegsize */
226	    0,				/* flags */
227	    NULL, NULL,			/* lockfunc, lockarg */
228	    &sc->bfe_tx_tag);
229	if (error != 0) {
230		device_printf(sc->bfe_dev, "cannot create Tx ring DMA tag.\n");
231		goto fail;
232	}
233
234	/* Create tag for Rx ring. */
235	error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */
236	    BFE_RX_RING_ALIGN, 0,	/* alignment, boundary */
237	    BUS_SPACE_MAXADDR, 		/* lowaddr */
238	    BUS_SPACE_MAXADDR,		/* highaddr */
239	    NULL, NULL,			/* filter, filterarg */
240	    BFE_RX_LIST_SIZE,		/* maxsize */
241	    1,				/* nsegments */
242	    BFE_RX_LIST_SIZE,		/* maxsegsize */
243	    0,				/* flags */
244	    NULL, NULL,			/* lockfunc, lockarg */
245	    &sc->bfe_rx_tag);
246	if (error != 0) {
247		device_printf(sc->bfe_dev, "cannot create Rx ring DMA tag.\n");
248		goto fail;
249	}
250
251	/* Create tag for Tx buffers. */
252	error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */
253	    1, 0,			/* alignment, boundary */
254	    BUS_SPACE_MAXADDR, 		/* lowaddr */
255	    BUS_SPACE_MAXADDR,		/* highaddr */
256	    NULL, NULL,			/* filter, filterarg */
257	    MCLBYTES * BFE_MAXTXSEGS,	/* maxsize */
258	    BFE_MAXTXSEGS,		/* nsegments */
259	    MCLBYTES,			/* maxsegsize */
260	    0,				/* flags */
261	    NULL, NULL,			/* lockfunc, lockarg */
262	    &sc->bfe_txmbuf_tag);
263	if (error != 0) {
264		device_printf(sc->bfe_dev,
265		    "cannot create Tx buffer DMA tag.\n");
266		goto fail;
267	}
268
269	/* Create tag for Rx buffers. */
270	error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */
271	    1, 0,			/* alignment, boundary */
272	    BUS_SPACE_MAXADDR, 		/* lowaddr */
273	    BUS_SPACE_MAXADDR,		/* highaddr */
274	    NULL, NULL,			/* filter, filterarg */
275	    MCLBYTES,			/* maxsize */
276	    1,				/* nsegments */
277	    MCLBYTES,			/* maxsegsize */
278	    0,				/* flags */
279	    NULL, NULL,			/* lockfunc, lockarg */
280	    &sc->bfe_rxmbuf_tag);
281	if (error != 0) {
282		device_printf(sc->bfe_dev,
283		    "cannot create Rx buffer DMA tag.\n");
284		goto fail;
285	}
286
287	/* Allocate DMA'able memory and load DMA map. */
288	error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list,
289	  BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->bfe_tx_map);
290	if (error != 0) {
291		device_printf(sc->bfe_dev,
292		    "cannot allocate DMA'able memory for Tx ring.\n");
293		goto fail;
294	}
295	ctx.bfe_busaddr = 0;
296	error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map,
297	    sc->bfe_tx_list, BFE_TX_LIST_SIZE, bfe_dma_map, &ctx,
298	    BUS_DMA_NOWAIT);
299	if (error != 0 || ctx.bfe_busaddr == 0) {
300		device_printf(sc->bfe_dev,
301		    "cannot load DMA'able memory for Tx ring.\n");
302		goto fail;
303	}
304	sc->bfe_tx_dma = BFE_ADDR_LO(ctx.bfe_busaddr);
305
306	error = bus_dmamem_alloc(sc->bfe_rx_tag, (void *)&sc->bfe_rx_list,
307	  BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->bfe_rx_map);
308	if (error != 0) {
309		device_printf(sc->bfe_dev,
310		    "cannot allocate DMA'able memory for Rx ring.\n");
311		goto fail;
312	}
313	ctx.bfe_busaddr = 0;
314	error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map,
315	    sc->bfe_rx_list, BFE_RX_LIST_SIZE, bfe_dma_map, &ctx,
316	    BUS_DMA_NOWAIT);
317	if (error != 0 || ctx.bfe_busaddr == 0) {
318		device_printf(sc->bfe_dev,
319		    "cannot load DMA'able memory for Rx ring.\n");
320		goto fail;
321	}
322	sc->bfe_rx_dma = BFE_ADDR_LO(ctx.bfe_busaddr);
323
324	/* Create DMA maps for Tx buffers. */
325	for (i = 0; i < BFE_TX_LIST_CNT; i++) {
326		td = &sc->bfe_tx_ring[i];
327		td->bfe_mbuf = NULL;
328		td->bfe_map = NULL;
329		error = bus_dmamap_create(sc->bfe_txmbuf_tag, 0, &td->bfe_map);
330		if (error != 0) {
331			device_printf(sc->bfe_dev,
332			    "cannot create DMA map for Tx.\n");
333			goto fail;
334		}
335	}
336
337	/* Create spare DMA map for Rx buffers. */
338	error = bus_dmamap_create(sc->bfe_rxmbuf_tag, 0, &sc->bfe_rx_sparemap);
339	if (error != 0) {
340		device_printf(sc->bfe_dev, "cannot create spare DMA map for Rx.\n");
341		goto fail;
342	}
343	/* Create DMA maps for Rx buffers. */
344	for (i = 0; i < BFE_RX_LIST_CNT; i++) {
345		rd = &sc->bfe_rx_ring[i];
346		rd->bfe_mbuf = NULL;
347		rd->bfe_map = NULL;
348		rd->bfe_ctrl = 0;
349		error = bus_dmamap_create(sc->bfe_rxmbuf_tag, 0, &rd->bfe_map);
350		if (error != 0) {
351			device_printf(sc->bfe_dev,
352			    "cannot create DMA map for Rx.\n");
353			goto fail;
354		}
355	}
356
357fail:
358	return (error);
359}
360
361static void
362bfe_dma_free(struct bfe_softc *sc)
363{
364	struct bfe_tx_data *td;
365	struct bfe_rx_data *rd;
366	int i;
367
368	/* Tx ring. */
369	if (sc->bfe_tx_tag != NULL) {
370		if (sc->bfe_tx_map != NULL)
371			bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map);
372		if (sc->bfe_tx_map != NULL && sc->bfe_tx_list != NULL)
373			bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list,
374			    sc->bfe_tx_map);
375		sc->bfe_tx_map = NULL;
376		sc->bfe_tx_list = NULL;
377		bus_dma_tag_destroy(sc->bfe_tx_tag);
378		sc->bfe_tx_tag = NULL;
379	}
380
381	/* Rx ring. */
382	if (sc->bfe_rx_tag != NULL) {
383		if (sc->bfe_rx_map != NULL)
384			bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map);
385		if (sc->bfe_rx_map != NULL && sc->bfe_rx_list != NULL)
386			bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list,
387			    sc->bfe_rx_map);
388		sc->bfe_rx_map = NULL;
389		sc->bfe_rx_list = NULL;
390		bus_dma_tag_destroy(sc->bfe_rx_tag);
391		sc->bfe_rx_tag = NULL;
392	}
393
394	/* Tx buffers. */
395	if (sc->bfe_txmbuf_tag != NULL) {
396		for (i = 0; i < BFE_TX_LIST_CNT; i++) {
397			td = &sc->bfe_tx_ring[i];
398			if (td->bfe_map != NULL) {
399				bus_dmamap_destroy(sc->bfe_txmbuf_tag,
400				    td->bfe_map);
401				td->bfe_map = NULL;
402			}
403		}
404		bus_dma_tag_destroy(sc->bfe_txmbuf_tag);
405		sc->bfe_txmbuf_tag = NULL;
406	}
407
408	/* Rx buffers. */
409	if (sc->bfe_rxmbuf_tag != NULL) {
410		for (i = 0; i < BFE_RX_LIST_CNT; i++) {
411			rd = &sc->bfe_rx_ring[i];
412			if (rd->bfe_map != NULL) {
413				bus_dmamap_destroy(sc->bfe_rxmbuf_tag,
414				    rd->bfe_map);
415				rd->bfe_map = NULL;
416			}
417		}
418		if (sc->bfe_rx_sparemap != NULL) {
419			bus_dmamap_destroy(sc->bfe_rxmbuf_tag,
420			    sc->bfe_rx_sparemap);
421			sc->bfe_rx_sparemap = NULL;
422		}
423		bus_dma_tag_destroy(sc->bfe_rxmbuf_tag);
424		sc->bfe_rxmbuf_tag = NULL;
425	}
426
427	if (sc->bfe_parent_tag != NULL) {
428		bus_dma_tag_destroy(sc->bfe_parent_tag);
429		sc->bfe_parent_tag = NULL;
430	}
431}
432
433static int
434bfe_attach(device_t dev)
435{
436	struct ifnet *ifp = NULL;
437	struct bfe_softc *sc;
438	int error = 0, rid;
439
440	sc = device_get_softc(dev);
441	mtx_init(&sc->bfe_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
442			MTX_DEF);
443	callout_init_mtx(&sc->bfe_stat_co, &sc->bfe_mtx, 0);
444
445	sc->bfe_dev = dev;
446
447	/*
448	 * Map control/status registers.
449	 */
450	pci_enable_busmaster(dev);
451
452	rid = PCIR_BAR(0);
453	sc->bfe_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
454			RF_ACTIVE);
455	if (sc->bfe_res == NULL) {
456		device_printf(dev, "couldn't map memory\n");
457		error = ENXIO;
458		goto fail;
459	}
460
461	/* Allocate interrupt */
462	rid = 0;
463
464	sc->bfe_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
465			RF_SHAREABLE | RF_ACTIVE);
466	if (sc->bfe_irq == NULL) {
467		device_printf(dev, "couldn't map interrupt\n");
468		error = ENXIO;
469		goto fail;
470	}
471
472	if (bfe_dma_alloc(sc) != 0) {
473		device_printf(dev, "failed to allocate DMA resources\n");
474		error = ENXIO;
475		goto fail;
476	}
477
478	SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
479	    SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
480	    "stats", CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_bfe_stats,
481	    "I", "Statistics");
482
483	/* Set up ifnet structure */
484	ifp = sc->bfe_ifp = if_alloc(IFT_ETHER);
485	if (ifp == NULL) {
486		device_printf(dev, "failed to if_alloc()\n");
487		error = ENOSPC;
488		goto fail;
489	}
490	ifp->if_softc = sc;
491	if_initname(ifp, device_get_name(dev), device_get_unit(dev));
492	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
493	ifp->if_ioctl = bfe_ioctl;
494	ifp->if_start = bfe_start;
495	ifp->if_init = bfe_init;
496	ifp->if_mtu = ETHERMTU;
497	IFQ_SET_MAXLEN(&ifp->if_snd, BFE_TX_QLEN);
498	ifp->if_snd.ifq_drv_maxlen = BFE_TX_QLEN;
499	IFQ_SET_READY(&ifp->if_snd);
500
501	bfe_get_config(sc);
502
503	/* Reset the chip and turn on the PHY */
504	BFE_LOCK(sc);
505	bfe_chip_reset(sc);
506	BFE_UNLOCK(sc);
507
508	error = mii_attach(dev, &sc->bfe_miibus, ifp, bfe_ifmedia_upd,
509	    bfe_ifmedia_sts, BMSR_DEFCAPMASK, sc->bfe_phyaddr, MII_OFFSET_ANY,
510	    0);
511	if (error != 0) {
512		device_printf(dev, "attaching PHYs failed\n");
513		goto fail;
514	}
515
516	ether_ifattach(ifp, sc->bfe_enaddr);
517
518	/*
519	 * Tell the upper layer(s) we support long frames.
520	 */
521	ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
522	ifp->if_capabilities |= IFCAP_VLAN_MTU;
523	ifp->if_capenable |= IFCAP_VLAN_MTU;
524
525	/*
526	 * Hook interrupt last to avoid having to lock softc
527	 */
528	error = bus_setup_intr(dev, sc->bfe_irq, INTR_TYPE_NET | INTR_MPSAFE,
529			NULL, bfe_intr, sc, &sc->bfe_intrhand);
530
531	if (error) {
532		device_printf(dev, "couldn't set up irq\n");
533		goto fail;
534	}
535fail:
536	if (error != 0)
537		bfe_detach(dev);
538	return (error);
539}
540
541static int
542bfe_detach(device_t dev)
543{
544	struct bfe_softc *sc;
545	struct ifnet *ifp;
546
547	sc = device_get_softc(dev);
548
549	ifp = sc->bfe_ifp;
550
551	if (device_is_attached(dev)) {
552		BFE_LOCK(sc);
553		sc->bfe_flags |= BFE_FLAG_DETACH;
554		bfe_stop(sc);
555		BFE_UNLOCK(sc);
556		callout_drain(&sc->bfe_stat_co);
557		if (ifp != NULL)
558			ether_ifdetach(ifp);
559	}
560
561	BFE_LOCK(sc);
562	bfe_chip_reset(sc);
563	BFE_UNLOCK(sc);
564
565	bus_generic_detach(dev);
566	if (sc->bfe_miibus != NULL)
567		device_delete_child(dev, sc->bfe_miibus);
568
569	bfe_release_resources(sc);
570	bfe_dma_free(sc);
571	mtx_destroy(&sc->bfe_mtx);
572
573	return (0);
574}
575
576/*
577 * Stop all chip I/O so that the kernel's probe routines don't
578 * get confused by errant DMAs when rebooting.
579 */
580static int
581bfe_shutdown(device_t dev)
582{
583	struct bfe_softc *sc;
584
585	sc = device_get_softc(dev);
586	BFE_LOCK(sc);
587	bfe_stop(sc);
588
589	BFE_UNLOCK(sc);
590
591	return (0);
592}
593
594static int
595bfe_suspend(device_t dev)
596{
597	struct bfe_softc *sc;
598
599	sc = device_get_softc(dev);
600	BFE_LOCK(sc);
601	bfe_stop(sc);
602	BFE_UNLOCK(sc);
603
604	return (0);
605}
606
607static int
608bfe_resume(device_t dev)
609{
610	struct bfe_softc *sc;
611	struct ifnet *ifp;
612
613	sc = device_get_softc(dev);
614	ifp = sc->bfe_ifp;
615	BFE_LOCK(sc);
616	bfe_chip_reset(sc);
617	if (ifp->if_flags & IFF_UP) {
618		bfe_init_locked(sc);
619		if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
620		    !IFQ_DRV_IS_EMPTY(&ifp->if_snd))
621			bfe_start_locked(ifp);
622	}
623	BFE_UNLOCK(sc);
624
625	return (0);
626}
627
628static int
629bfe_miibus_readreg(device_t dev, int phy, int reg)
630{
631	struct bfe_softc *sc;
632	u_int32_t ret;
633
634	sc = device_get_softc(dev);
635	bfe_readphy(sc, reg, &ret);
636
637	return (ret);
638}
639
640static int
641bfe_miibus_writereg(device_t dev, int phy, int reg, int val)
642{
643	struct bfe_softc *sc;
644
645	sc = device_get_softc(dev);
646	bfe_writephy(sc, reg, val);
647
648	return (0);
649}
650
651static void
652bfe_miibus_statchg(device_t dev)
653{
654	struct bfe_softc *sc;
655	struct mii_data *mii;
656	u_int32_t val, flow;
657
658	sc = device_get_softc(dev);
659	mii = device_get_softc(sc->bfe_miibus);
660
661	sc->bfe_flags &= ~BFE_FLAG_LINK;
662	if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
663	    (IFM_ACTIVE | IFM_AVALID)) {
664		switch (IFM_SUBTYPE(mii->mii_media_active)) {
665		case IFM_10_T:
666		case IFM_100_TX:
667			sc->bfe_flags |= BFE_FLAG_LINK;
668			break;
669		default:
670			break;
671		}
672	}
673
674	/* XXX Should stop Rx/Tx engine prior to touching MAC. */
675	val = CSR_READ_4(sc, BFE_TX_CTRL);
676	val &= ~BFE_TX_DUPLEX;
677	if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
678		val |= BFE_TX_DUPLEX;
679		flow = 0;
680#ifdef notyet
681		flow = CSR_READ_4(sc, BFE_RXCONF);
682		flow &= ~BFE_RXCONF_FLOW;
683		if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) &
684		    IFM_ETH_RXPAUSE) != 0)
685			flow |= BFE_RXCONF_FLOW;
686		CSR_WRITE_4(sc, BFE_RXCONF, flow);
687		/*
688		 * It seems that the hardware has Tx pause issues
689		 * so enable only Rx pause.
690		 */
691		flow = CSR_READ_4(sc, BFE_MAC_FLOW);
692		flow &= ~BFE_FLOW_PAUSE_ENAB;
693		CSR_WRITE_4(sc, BFE_MAC_FLOW, flow);
694#endif
695	}
696	CSR_WRITE_4(sc, BFE_TX_CTRL, val);
697}
698
699static void
700bfe_tx_ring_free(struct bfe_softc *sc)
701{
702	int i;
703
704	for(i = 0; i < BFE_TX_LIST_CNT; i++) {
705		if (sc->bfe_tx_ring[i].bfe_mbuf != NULL) {
706			bus_dmamap_sync(sc->bfe_txmbuf_tag,
707			    sc->bfe_tx_ring[i].bfe_map, BUS_DMASYNC_POSTWRITE);
708			bus_dmamap_unload(sc->bfe_txmbuf_tag,
709			    sc->bfe_tx_ring[i].bfe_map);
710			m_freem(sc->bfe_tx_ring[i].bfe_mbuf);
711			sc->bfe_tx_ring[i].bfe_mbuf = NULL;
712		}
713	}
714	bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE);
715	bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map,
716	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
717}
718
719static void
720bfe_rx_ring_free(struct bfe_softc *sc)
721{
722	int i;
723
724	for (i = 0; i < BFE_RX_LIST_CNT; i++) {
725		if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) {
726			bus_dmamap_sync(sc->bfe_rxmbuf_tag,
727			    sc->bfe_rx_ring[i].bfe_map, BUS_DMASYNC_POSTREAD);
728			bus_dmamap_unload(sc->bfe_rxmbuf_tag,
729			    sc->bfe_rx_ring[i].bfe_map);
730			m_freem(sc->bfe_rx_ring[i].bfe_mbuf);
731			sc->bfe_rx_ring[i].bfe_mbuf = NULL;
732		}
733	}
734	bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE);
735	bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map,
736	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
737}
738
739static int
740bfe_list_rx_init(struct bfe_softc *sc)
741{
742	struct bfe_rx_data *rd;
743	int i;
744
745	sc->bfe_rx_prod = sc->bfe_rx_cons = 0;
746	bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE);
747	for (i = 0; i < BFE_RX_LIST_CNT; i++) {
748		rd = &sc->bfe_rx_ring[i];
749		rd->bfe_mbuf = NULL;
750		rd->bfe_ctrl = 0;
751		if (bfe_list_newbuf(sc, i) != 0)
752			return (ENOBUFS);
753	}
754
755	bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map,
756	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
757	CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc)));
758
759	return (0);
760}
761
762static void
763bfe_list_tx_init(struct bfe_softc *sc)
764{
765	int i;
766
767	sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0;
768	bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE);
769	for (i = 0; i < BFE_TX_LIST_CNT; i++)
770		sc->bfe_tx_ring[i].bfe_mbuf = NULL;
771
772	bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map,
773	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
774}
775
776static void
777bfe_discard_buf(struct bfe_softc *sc, int c)
778{
779	struct bfe_rx_data *r;
780	struct bfe_desc *d;
781
782	r = &sc->bfe_rx_ring[c];
783	d = &sc->bfe_rx_list[c];
784	d->bfe_ctrl = htole32(r->bfe_ctrl);
785}
786
787static int
788bfe_list_newbuf(struct bfe_softc *sc, int c)
789{
790	struct bfe_rxheader *rx_header;
791	struct bfe_desc *d;
792	struct bfe_rx_data *r;
793	struct mbuf *m;
794	bus_dma_segment_t segs[1];
795	bus_dmamap_t map;
796	u_int32_t ctrl;
797	int nsegs;
798
799	m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
800	m->m_len = m->m_pkthdr.len = MCLBYTES;
801
802	if (bus_dmamap_load_mbuf_sg(sc->bfe_rxmbuf_tag, sc->bfe_rx_sparemap,
803	    m, segs, &nsegs, 0) != 0) {
804		m_freem(m);
805		return (ENOBUFS);
806	}
807
808	KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
809	r = &sc->bfe_rx_ring[c];
810	if (r->bfe_mbuf != NULL) {
811		bus_dmamap_sync(sc->bfe_rxmbuf_tag, r->bfe_map,
812		    BUS_DMASYNC_POSTREAD);
813		bus_dmamap_unload(sc->bfe_rxmbuf_tag, r->bfe_map);
814	}
815	map = r->bfe_map;
816	r->bfe_map = sc->bfe_rx_sparemap;
817	sc->bfe_rx_sparemap = map;
818	r->bfe_mbuf = m;
819
820	rx_header = mtod(m, struct bfe_rxheader *);
821	rx_header->len = 0;
822	rx_header->flags = 0;
823	bus_dmamap_sync(sc->bfe_rxmbuf_tag, r->bfe_map, BUS_DMASYNC_PREREAD);
824
825	ctrl = segs[0].ds_len & BFE_DESC_LEN;
826	KASSERT(ctrl > ETHER_MAX_LEN + 32, ("%s: buffer size too small(%d)!",
827	    __func__, ctrl));
828	if (c == BFE_RX_LIST_CNT - 1)
829		ctrl |= BFE_DESC_EOT;
830	r->bfe_ctrl = ctrl;
831
832	d = &sc->bfe_rx_list[c];
833	d->bfe_ctrl = htole32(ctrl);
834	/* The chip needs all addresses to be added to BFE_PCI_DMA. */
835	d->bfe_addr = htole32(BFE_ADDR_LO(segs[0].ds_addr) + BFE_PCI_DMA);
836
837	return (0);
838}
839
840static void
841bfe_get_config(struct bfe_softc *sc)
842{
843	u_int8_t eeprom[128];
844
845	bfe_read_eeprom(sc, eeprom);
846
847	sc->bfe_enaddr[0] = eeprom[79];
848	sc->bfe_enaddr[1] = eeprom[78];
849	sc->bfe_enaddr[2] = eeprom[81];
850	sc->bfe_enaddr[3] = eeprom[80];
851	sc->bfe_enaddr[4] = eeprom[83];
852	sc->bfe_enaddr[5] = eeprom[82];
853
854	sc->bfe_phyaddr = eeprom[90] & 0x1f;
855	sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1;
856
857	sc->bfe_core_unit = 0;
858	sc->bfe_dma_offset = BFE_PCI_DMA;
859}
860
861static void
862bfe_pci_setup(struct bfe_softc *sc, u_int32_t cores)
863{
864	u_int32_t bar_orig, pci_rev, val;
865
866	bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4);
867	pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4);
868	pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK;
869
870	val = CSR_READ_4(sc, BFE_SBINTVEC);
871	val |= cores;
872	CSR_WRITE_4(sc, BFE_SBINTVEC, val);
873
874	val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2);
875	val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST;
876	CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val);
877
878	pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4);
879}
880
881static void
882bfe_clear_stats(struct bfe_softc *sc)
883{
884	uint32_t reg;
885
886	BFE_LOCK_ASSERT(sc);
887
888	CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ);
889	for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4)
890		CSR_READ_4(sc, reg);
891	for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4)
892		CSR_READ_4(sc, reg);
893}
894
895static int
896bfe_resetphy(struct bfe_softc *sc)
897{
898	u_int32_t val;
899
900	bfe_writephy(sc, 0, BMCR_RESET);
901	DELAY(100);
902	bfe_readphy(sc, 0, &val);
903	if (val & BMCR_RESET) {
904		device_printf(sc->bfe_dev, "PHY Reset would not complete.\n");
905		return (ENXIO);
906	}
907	return (0);
908}
909
910static void
911bfe_chip_halt(struct bfe_softc *sc)
912{
913	BFE_LOCK_ASSERT(sc);
914	/* disable interrupts - not that it actually does..*/
915	CSR_WRITE_4(sc, BFE_IMASK, 0);
916	CSR_READ_4(sc, BFE_IMASK);
917
918	CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE);
919	bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1);
920
921	CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0);
922	CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0);
923	DELAY(10);
924}
925
926static void
927bfe_chip_reset(struct bfe_softc *sc)
928{
929	u_int32_t val;
930
931	BFE_LOCK_ASSERT(sc);
932
933	/* Set the interrupt vector for the enet core */
934	bfe_pci_setup(sc, BFE_INTVEC_ENET0);
935
936	/* is core up? */
937	val = CSR_READ_4(sc, BFE_SBTMSLOW) &
938	    (BFE_RESET | BFE_REJECT | BFE_CLOCK);
939	if (val == BFE_CLOCK) {
940		/* It is, so shut it down */
941		CSR_WRITE_4(sc, BFE_RCV_LAZY, 0);
942		CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE);
943		bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1);
944		CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0);
945		if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK)
946			bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE,
947			    100, 0);
948		CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0);
949	}
950
951	bfe_core_reset(sc);
952	bfe_clear_stats(sc);
953
954	/*
955	 * We want the phy registers to be accessible even when
956	 * the driver is "downed" so initialize MDC preamble, frequency,
957	 * and whether internal or external phy here.
958	 */
959
960	/* 4402 has 62.5Mhz SB clock and internal phy */
961	CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d);
962
963	/* Internal or external PHY? */
964	val = CSR_READ_4(sc, BFE_DEVCTRL);
965	if (!(val & BFE_IPP))
966		CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL);
967	else if (CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) {
968		BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR);
969		DELAY(100);
970	}
971
972	/* Enable CRC32 generation and set proper LED modes */
973	BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB | BFE_CTRL_LED);
974
975	/* Reset or clear powerdown control bit  */
976	BFE_AND(sc, BFE_MAC_CTRL, ~BFE_CTRL_PDOWN);
977
978	CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) &
979				BFE_LAZY_FC_MASK));
980
981	/*
982	 * We don't want lazy interrupts, so just send them at
983	 * the end of a frame, please
984	 */
985	BFE_OR(sc, BFE_RCV_LAZY, 0);
986
987	/* Set max lengths, accounting for VLAN tags */
988	CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32);
989	CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32);
990
991	/* Set watermark XXX - magic */
992	CSR_WRITE_4(sc, BFE_TX_WMARK, 56);
993
994	/*
995	 * Initialise DMA channels
996	 * - not forgetting dma addresses need to be added to BFE_PCI_DMA
997	 */
998	CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE);
999	CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA);
1000
1001	CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) |
1002			BFE_RX_CTRL_ENABLE);
1003	CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA);
1004
1005	bfe_resetphy(sc);
1006	bfe_setupphy(sc);
1007}
1008
1009static void
1010bfe_core_disable(struct bfe_softc *sc)
1011{
1012	if ((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET)
1013		return;
1014
1015	/*
1016	 * Set reject, wait for it set, then wait for the core to stop
1017	 * being busy, then set reset and reject and enable the clocks.
1018	 */
1019	CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK));
1020	bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0);
1021	bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1);
1022	CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT |
1023				BFE_RESET));
1024	CSR_READ_4(sc, BFE_SBTMSLOW);
1025	DELAY(10);
1026	/* Leave reset and reject set */
1027	CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET));
1028	DELAY(10);
1029}
1030
1031static void
1032bfe_core_reset(struct bfe_softc *sc)
1033{
1034	u_int32_t val;
1035
1036	/* Disable the core */
1037	bfe_core_disable(sc);
1038
1039	/* and bring it back up */
1040	CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC));
1041	CSR_READ_4(sc, BFE_SBTMSLOW);
1042	DELAY(10);
1043
1044	/* Chip bug, clear SERR, IB and TO if they are set. */
1045	if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR)
1046		CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0);
1047	val = CSR_READ_4(sc, BFE_SBIMSTATE);
1048	if (val & (BFE_IBE | BFE_TO))
1049		CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO));
1050
1051	/* Clear reset and allow it to move through the core */
1052	CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC));
1053	CSR_READ_4(sc, BFE_SBTMSLOW);
1054	DELAY(10);
1055
1056	/* Leave the clock set */
1057	CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK);
1058	CSR_READ_4(sc, BFE_SBTMSLOW);
1059	DELAY(10);
1060}
1061
1062static void
1063bfe_cam_write(struct bfe_softc *sc, u_char *data, int index)
1064{
1065	u_int32_t val;
1066
1067	val  = ((u_int32_t) data[2]) << 24;
1068	val |= ((u_int32_t) data[3]) << 16;
1069	val |= ((u_int32_t) data[4]) <<  8;
1070	val |= ((u_int32_t) data[5]);
1071	CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val);
1072	val = (BFE_CAM_HI_VALID |
1073			(((u_int32_t) data[0]) << 8) |
1074			(((u_int32_t) data[1])));
1075	CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val);
1076	CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE |
1077				((u_int32_t) index << BFE_CAM_INDEX_SHIFT)));
1078	bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1);
1079}
1080
1081static void
1082bfe_set_rx_mode(struct bfe_softc *sc)
1083{
1084	struct ifnet *ifp = sc->bfe_ifp;
1085	struct ifmultiaddr  *ifma;
1086	u_int32_t val;
1087	int i = 0;
1088
1089	BFE_LOCK_ASSERT(sc);
1090
1091	val = CSR_READ_4(sc, BFE_RXCONF);
1092
1093	if (ifp->if_flags & IFF_PROMISC)
1094		val |= BFE_RXCONF_PROMISC;
1095	else
1096		val &= ~BFE_RXCONF_PROMISC;
1097
1098	if (ifp->if_flags & IFF_BROADCAST)
1099		val &= ~BFE_RXCONF_DBCAST;
1100	else
1101		val |= BFE_RXCONF_DBCAST;
1102
1103
1104	CSR_WRITE_4(sc, BFE_CAM_CTRL, 0);
1105	bfe_cam_write(sc, IF_LLADDR(sc->bfe_ifp), i++);
1106
1107	if (ifp->if_flags & IFF_ALLMULTI)
1108		val |= BFE_RXCONF_ALLMULTI;
1109	else {
1110		val &= ~BFE_RXCONF_ALLMULTI;
1111		if_maddr_rlock(ifp);
1112		TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1113			if (ifma->ifma_addr->sa_family != AF_LINK)
1114				continue;
1115			bfe_cam_write(sc,
1116			    LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i++);
1117		}
1118		if_maddr_runlock(ifp);
1119	}
1120
1121	CSR_WRITE_4(sc, BFE_RXCONF, val);
1122	BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE);
1123}
1124
1125static void
1126bfe_dma_map(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1127{
1128	struct bfe_dmamap_arg *ctx;
1129
1130	if (error != 0)
1131		return;
1132
1133	KASSERT(nseg == 1, ("%s : %d segments returned!", __func__, nseg));
1134
1135	ctx = (struct bfe_dmamap_arg *)arg;
1136	ctx->bfe_busaddr = segs[0].ds_addr;
1137}
1138
1139static void
1140bfe_release_resources(struct bfe_softc *sc)
1141{
1142
1143	if (sc->bfe_intrhand != NULL)
1144		bus_teardown_intr(sc->bfe_dev, sc->bfe_irq, sc->bfe_intrhand);
1145
1146	if (sc->bfe_irq != NULL)
1147		bus_release_resource(sc->bfe_dev, SYS_RES_IRQ, 0, sc->bfe_irq);
1148
1149	if (sc->bfe_res != NULL)
1150		bus_release_resource(sc->bfe_dev, SYS_RES_MEMORY, PCIR_BAR(0),
1151		    sc->bfe_res);
1152
1153	if (sc->bfe_ifp != NULL)
1154		if_free(sc->bfe_ifp);
1155}
1156
1157static void
1158bfe_read_eeprom(struct bfe_softc *sc, u_int8_t *data)
1159{
1160	long i;
1161	u_int16_t *ptr = (u_int16_t *)data;
1162
1163	for(i = 0; i < 128; i += 2)
1164		ptr[i/2] = CSR_READ_4(sc, 4096 + i);
1165}
1166
1167static int
1168bfe_wait_bit(struct bfe_softc *sc, u_int32_t reg, u_int32_t bit,
1169		u_long timeout, const int clear)
1170{
1171	u_long i;
1172
1173	for (i = 0; i < timeout; i++) {
1174		u_int32_t val = CSR_READ_4(sc, reg);
1175
1176		if (clear && !(val & bit))
1177			break;
1178		if (!clear && (val & bit))
1179			break;
1180		DELAY(10);
1181	}
1182	if (i == timeout) {
1183		device_printf(sc->bfe_dev,
1184		    "BUG!  Timeout waiting for bit %08x of register "
1185		    "%x to %s.\n", bit, reg, (clear ? "clear" : "set"));
1186		return (-1);
1187	}
1188	return (0);
1189}
1190
1191static int
1192bfe_readphy(struct bfe_softc *sc, u_int32_t reg, u_int32_t *val)
1193{
1194	int err;
1195
1196	/* Clear MII ISR */
1197	CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII);
1198	CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START |
1199				(BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) |
1200				(sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) |
1201				(reg << BFE_MDIO_RA_SHIFT) |
1202				(BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT)));
1203	err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0);
1204	*val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA;
1205
1206	return (err);
1207}
1208
1209static int
1210bfe_writephy(struct bfe_softc *sc, u_int32_t reg, u_int32_t val)
1211{
1212	int status;
1213
1214	CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII);
1215	CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START |
1216				(BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) |
1217				(sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) |
1218				(reg << BFE_MDIO_RA_SHIFT) |
1219				(BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) |
1220				(val & BFE_MDIO_DATA_DATA)));
1221	status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0);
1222
1223	return (status);
1224}
1225
1226/*
1227 * XXX - I think this is handled by the PHY driver, but it can't hurt to do it
1228 * twice
1229 */
1230static int
1231bfe_setupphy(struct bfe_softc *sc)
1232{
1233	u_int32_t val;
1234
1235	/* Enable activity LED */
1236	bfe_readphy(sc, 26, &val);
1237	bfe_writephy(sc, 26, val & 0x7fff);
1238	bfe_readphy(sc, 26, &val);
1239
1240	/* Enable traffic meter LED mode */
1241	bfe_readphy(sc, 27, &val);
1242	bfe_writephy(sc, 27, val | (1 << 6));
1243
1244	return (0);
1245}
1246
1247static void
1248bfe_stats_update(struct bfe_softc *sc)
1249{
1250	struct bfe_hw_stats *stats;
1251	struct ifnet *ifp;
1252	uint32_t mib[BFE_MIB_CNT];
1253	uint32_t reg, *val;
1254
1255	BFE_LOCK_ASSERT(sc);
1256
1257	val = mib;
1258	CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ);
1259	for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4)
1260		*val++ = CSR_READ_4(sc, reg);
1261	for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4)
1262		*val++ = CSR_READ_4(sc, reg);
1263
1264	ifp = sc->bfe_ifp;
1265	stats = &sc->bfe_stats;
1266	/* Tx stat. */
1267	stats->tx_good_octets += mib[MIB_TX_GOOD_O];
1268	stats->tx_good_frames += mib[MIB_TX_GOOD_P];
1269	stats->tx_octets += mib[MIB_TX_O];
1270	stats->tx_frames += mib[MIB_TX_P];
1271	stats->tx_bcast_frames += mib[MIB_TX_BCAST];
1272	stats->tx_mcast_frames += mib[MIB_TX_MCAST];
1273	stats->tx_pkts_64 += mib[MIB_TX_64];
1274	stats->tx_pkts_65_127 += mib[MIB_TX_65_127];
1275	stats->tx_pkts_128_255 += mib[MIB_TX_128_255];
1276	stats->tx_pkts_256_511 += mib[MIB_TX_256_511];
1277	stats->tx_pkts_512_1023 += mib[MIB_TX_512_1023];
1278	stats->tx_pkts_1024_max += mib[MIB_TX_1024_MAX];
1279	stats->tx_jabbers += mib[MIB_TX_JABBER];
1280	stats->tx_oversize_frames += mib[MIB_TX_OSIZE];
1281	stats->tx_frag_frames += mib[MIB_TX_FRAG];
1282	stats->tx_underruns += mib[MIB_TX_URUNS];
1283	stats->tx_colls += mib[MIB_TX_TCOLS];
1284	stats->tx_single_colls += mib[MIB_TX_SCOLS];
1285	stats->tx_multi_colls += mib[MIB_TX_MCOLS];
1286	stats->tx_excess_colls += mib[MIB_TX_ECOLS];
1287	stats->tx_late_colls += mib[MIB_TX_LCOLS];
1288	stats->tx_deferrals += mib[MIB_TX_DEFERED];
1289	stats->tx_carrier_losts += mib[MIB_TX_CLOST];
1290	stats->tx_pause_frames += mib[MIB_TX_PAUSE];
1291	/* Rx stat. */
1292	stats->rx_good_octets += mib[MIB_RX_GOOD_O];
1293	stats->rx_good_frames += mib[MIB_RX_GOOD_P];
1294	stats->rx_octets += mib[MIB_RX_O];
1295	stats->rx_frames += mib[MIB_RX_P];
1296	stats->rx_bcast_frames += mib[MIB_RX_BCAST];
1297	stats->rx_mcast_frames += mib[MIB_RX_MCAST];
1298	stats->rx_pkts_64 += mib[MIB_RX_64];
1299	stats->rx_pkts_65_127 += mib[MIB_RX_65_127];
1300	stats->rx_pkts_128_255 += mib[MIB_RX_128_255];
1301	stats->rx_pkts_256_511 += mib[MIB_RX_256_511];
1302	stats->rx_pkts_512_1023 += mib[MIB_RX_512_1023];
1303	stats->rx_pkts_1024_max += mib[MIB_RX_1024_MAX];
1304	stats->rx_jabbers += mib[MIB_RX_JABBER];
1305	stats->rx_oversize_frames += mib[MIB_RX_OSIZE];
1306	stats->rx_frag_frames += mib[MIB_RX_FRAG];
1307	stats->rx_missed_frames += mib[MIB_RX_MISS];
1308	stats->rx_crc_align_errs += mib[MIB_RX_CRCA];
1309	stats->rx_runts += mib[MIB_RX_USIZE];
1310	stats->rx_crc_errs += mib[MIB_RX_CRC];
1311	stats->rx_align_errs += mib[MIB_RX_ALIGN];
1312	stats->rx_symbol_errs += mib[MIB_RX_SYM];
1313	stats->rx_pause_frames += mib[MIB_RX_PAUSE];
1314	stats->rx_control_frames += mib[MIB_RX_NPAUSE];
1315
1316	/* Update counters in ifnet. */
1317	ifp->if_opackets += (u_long)mib[MIB_TX_GOOD_P];
1318	ifp->if_collisions += (u_long)mib[MIB_TX_TCOLS];
1319	ifp->if_oerrors += (u_long)mib[MIB_TX_URUNS] +
1320	    (u_long)mib[MIB_TX_ECOLS] +
1321	    (u_long)mib[MIB_TX_DEFERED] +
1322	    (u_long)mib[MIB_TX_CLOST];
1323
1324	ifp->if_ipackets += (u_long)mib[MIB_RX_GOOD_P];
1325
1326	ifp->if_ierrors += mib[MIB_RX_JABBER] +
1327	    mib[MIB_RX_MISS] +
1328	    mib[MIB_RX_CRCA] +
1329	    mib[MIB_RX_USIZE] +
1330	    mib[MIB_RX_CRC] +
1331	    mib[MIB_RX_ALIGN] +
1332	    mib[MIB_RX_SYM];
1333}
1334
1335static void
1336bfe_txeof(struct bfe_softc *sc)
1337{
1338	struct bfe_tx_data *r;
1339	struct ifnet *ifp;
1340	int i, chipidx;
1341
1342	BFE_LOCK_ASSERT(sc);
1343
1344	ifp = sc->bfe_ifp;
1345
1346	chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK;
1347	chipidx /= sizeof(struct bfe_desc);
1348
1349	i = sc->bfe_tx_cons;
1350	if (i == chipidx)
1351		return;
1352	bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map,
1353	    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1354	/* Go through the mbufs and free those that have been transmitted */
1355	for (; i != chipidx; BFE_INC(i, BFE_TX_LIST_CNT)) {
1356		r = &sc->bfe_tx_ring[i];
1357		sc->bfe_tx_cnt--;
1358		if (r->bfe_mbuf == NULL)
1359			continue;
1360		bus_dmamap_sync(sc->bfe_txmbuf_tag, r->bfe_map,
1361		    BUS_DMASYNC_POSTWRITE);
1362		bus_dmamap_unload(sc->bfe_txmbuf_tag, r->bfe_map);
1363
1364		m_freem(r->bfe_mbuf);
1365		r->bfe_mbuf = NULL;
1366	}
1367
1368	if (i != sc->bfe_tx_cons) {
1369		/* we freed up some mbufs */
1370		sc->bfe_tx_cons = i;
1371		ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1372	}
1373
1374	if (sc->bfe_tx_cnt == 0)
1375		sc->bfe_watchdog_timer = 0;
1376}
1377
1378/* Pass a received packet up the stack */
1379static void
1380bfe_rxeof(struct bfe_softc *sc)
1381{
1382	struct mbuf *m;
1383	struct ifnet *ifp;
1384	struct bfe_rxheader *rxheader;
1385	struct bfe_rx_data *r;
1386	int cons, prog;
1387	u_int32_t status, current, len, flags;
1388
1389	BFE_LOCK_ASSERT(sc);
1390	cons = sc->bfe_rx_cons;
1391	status = CSR_READ_4(sc, BFE_DMARX_STAT);
1392	current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc);
1393
1394	ifp = sc->bfe_ifp;
1395
1396	bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map,
1397	    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1398
1399	for (prog = 0; current != cons; prog++,
1400	    BFE_INC(cons, BFE_RX_LIST_CNT)) {
1401		r = &sc->bfe_rx_ring[cons];
1402		m = r->bfe_mbuf;
1403		/*
1404		 * Rx status should be read from mbuf such that we can't
1405		 * delay bus_dmamap_sync(9). This hardware limiation
1406		 * results in inefficent mbuf usage as bfe(4) couldn't
1407		 * reuse mapped buffer from errored frame.
1408		 */
1409		if (bfe_list_newbuf(sc, cons) != 0) {
1410			ifp->if_iqdrops++;
1411			bfe_discard_buf(sc, cons);
1412			continue;
1413		}
1414		rxheader = mtod(m, struct bfe_rxheader*);
1415		len = le16toh(rxheader->len);
1416		flags = le16toh(rxheader->flags);
1417
1418		/* Remove CRC bytes. */
1419		len -= ETHER_CRC_LEN;
1420
1421		/* flag an error and try again */
1422		if ((len > ETHER_MAX_LEN+32) || (flags & BFE_RX_FLAG_ERRORS)) {
1423			m_freem(m);
1424			continue;
1425		}
1426
1427		/* Make sure to skip header bytes written by hardware. */
1428		m_adj(m, BFE_RX_OFFSET);
1429		m->m_len = m->m_pkthdr.len = len;
1430
1431		m->m_pkthdr.rcvif = ifp;
1432		BFE_UNLOCK(sc);
1433		(*ifp->if_input)(ifp, m);
1434		BFE_LOCK(sc);
1435	}
1436
1437	if (prog > 0) {
1438		sc->bfe_rx_cons = cons;
1439		bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map,
1440		    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1441	}
1442}
1443
1444static void
1445bfe_intr(void *xsc)
1446{
1447	struct bfe_softc *sc = xsc;
1448	struct ifnet *ifp;
1449	u_int32_t istat;
1450
1451	ifp = sc->bfe_ifp;
1452
1453	BFE_LOCK(sc);
1454
1455	istat = CSR_READ_4(sc, BFE_ISTAT);
1456
1457	/*
1458	 * Defer unsolicited interrupts - This is necessary because setting the
1459	 * chips interrupt mask register to 0 doesn't actually stop the
1460	 * interrupts
1461	 */
1462	istat &= BFE_IMASK_DEF;
1463	CSR_WRITE_4(sc, BFE_ISTAT, istat);
1464	CSR_READ_4(sc, BFE_ISTAT);
1465
1466	/* not expecting this interrupt, disregard it */
1467	if (istat == 0 || (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
1468		BFE_UNLOCK(sc);
1469		return;
1470	}
1471
1472	/* A packet was received */
1473	if (istat & BFE_ISTAT_RX)
1474		bfe_rxeof(sc);
1475
1476	/* A packet was sent */
1477	if (istat & BFE_ISTAT_TX)
1478		bfe_txeof(sc);
1479
1480	if (istat & BFE_ISTAT_ERRORS) {
1481
1482		if (istat & BFE_ISTAT_DSCE) {
1483			device_printf(sc->bfe_dev, "Descriptor Error\n");
1484			bfe_stop(sc);
1485			BFE_UNLOCK(sc);
1486			return;
1487		}
1488
1489		if (istat & BFE_ISTAT_DPE) {
1490			device_printf(sc->bfe_dev,
1491			    "Descriptor Protocol Error\n");
1492			bfe_stop(sc);
1493			BFE_UNLOCK(sc);
1494			return;
1495		}
1496		ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1497		bfe_init_locked(sc);
1498	}
1499
1500	/* We have packets pending, fire them out */
1501	if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1502		bfe_start_locked(ifp);
1503
1504	BFE_UNLOCK(sc);
1505}
1506
1507static int
1508bfe_encap(struct bfe_softc *sc, struct mbuf **m_head)
1509{
1510	struct bfe_desc *d;
1511	struct bfe_tx_data *r, *r1;
1512	struct mbuf *m;
1513	bus_dmamap_t map;
1514	bus_dma_segment_t txsegs[BFE_MAXTXSEGS];
1515	uint32_t cur, si;
1516	int error, i, nsegs;
1517
1518	BFE_LOCK_ASSERT(sc);
1519
1520	M_ASSERTPKTHDR((*m_head));
1521
1522	si = cur = sc->bfe_tx_prod;
1523	r = &sc->bfe_tx_ring[cur];
1524	error = bus_dmamap_load_mbuf_sg(sc->bfe_txmbuf_tag, r->bfe_map, *m_head,
1525	    txsegs, &nsegs, 0);
1526	if (error == EFBIG) {
1527		m = m_collapse(*m_head, M_DONTWAIT, BFE_MAXTXSEGS);
1528		if (m == NULL) {
1529			m_freem(*m_head);
1530			*m_head = NULL;
1531			return (ENOMEM);
1532		}
1533		*m_head = m;
1534		error = bus_dmamap_load_mbuf_sg(sc->bfe_txmbuf_tag, r->bfe_map,
1535		    *m_head, txsegs, &nsegs, 0);
1536		if (error != 0) {
1537			m_freem(*m_head);
1538			*m_head = NULL;
1539			return (error);
1540		}
1541	} else if (error != 0)
1542		return (error);
1543	if (nsegs == 0) {
1544		m_freem(*m_head);
1545		*m_head = NULL;
1546		return (EIO);
1547	}
1548
1549	if (sc->bfe_tx_cnt + nsegs > BFE_TX_LIST_CNT - 1) {
1550		bus_dmamap_unload(sc->bfe_txmbuf_tag, r->bfe_map);
1551		return (ENOBUFS);
1552	}
1553
1554	for (i = 0; i < nsegs; i++) {
1555		d = &sc->bfe_tx_list[cur];
1556		d->bfe_ctrl = htole32(txsegs[i].ds_len & BFE_DESC_LEN);
1557		d->bfe_ctrl |= htole32(BFE_DESC_IOC);
1558		if (cur == BFE_TX_LIST_CNT - 1)
1559			/*
1560			 * Tell the chip to wrap to the start of
1561			 * the descriptor list.
1562			 */
1563			d->bfe_ctrl |= htole32(BFE_DESC_EOT);
1564		/* The chip needs all addresses to be added to BFE_PCI_DMA. */
1565		d->bfe_addr = htole32(BFE_ADDR_LO(txsegs[i].ds_addr) +
1566		    BFE_PCI_DMA);
1567		BFE_INC(cur, BFE_TX_LIST_CNT);
1568	}
1569
1570	/* Update producer index. */
1571	sc->bfe_tx_prod = cur;
1572
1573	/* Set EOF on the last descriptor. */
1574	cur = (cur + BFE_TX_LIST_CNT - 1) % BFE_TX_LIST_CNT;
1575	d = &sc->bfe_tx_list[cur];
1576	d->bfe_ctrl |= htole32(BFE_DESC_EOF);
1577
1578	/* Lastly set SOF on the first descriptor to avoid races. */
1579	d = &sc->bfe_tx_list[si];
1580	d->bfe_ctrl |= htole32(BFE_DESC_SOF);
1581
1582	r1 = &sc->bfe_tx_ring[cur];
1583	map = r->bfe_map;
1584	r->bfe_map = r1->bfe_map;
1585	r1->bfe_map = map;
1586	r1->bfe_mbuf = *m_head;
1587	sc->bfe_tx_cnt += nsegs;
1588
1589	bus_dmamap_sync(sc->bfe_txmbuf_tag, map, BUS_DMASYNC_PREWRITE);
1590
1591	return (0);
1592}
1593
1594/*
1595 * Set up to transmit a packet.
1596 */
1597static void
1598bfe_start(struct ifnet *ifp)
1599{
1600	BFE_LOCK((struct bfe_softc *)ifp->if_softc);
1601	bfe_start_locked(ifp);
1602	BFE_UNLOCK((struct bfe_softc *)ifp->if_softc);
1603}
1604
1605/*
1606 * Set up to transmit a packet. The softc is already locked.
1607 */
1608static void
1609bfe_start_locked(struct ifnet *ifp)
1610{
1611	struct bfe_softc *sc;
1612	struct mbuf *m_head;
1613	int queued;
1614
1615	sc = ifp->if_softc;
1616
1617	BFE_LOCK_ASSERT(sc);
1618
1619	/*
1620	 * Not much point trying to send if the link is down
1621	 * or we have nothing to send.
1622	 */
1623	if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1624	    IFF_DRV_RUNNING || (sc->bfe_flags & BFE_FLAG_LINK) == 0)
1625		return;
1626
1627	for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
1628	    sc->bfe_tx_cnt < BFE_TX_LIST_CNT - 1;) {
1629		IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1630		if (m_head == NULL)
1631			break;
1632
1633		/*
1634		 * Pack the data into the tx ring.  If we dont have
1635		 * enough room, let the chip drain the ring.
1636		 */
1637		if (bfe_encap(sc, &m_head)) {
1638			if (m_head == NULL)
1639				break;
1640			IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
1641			ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1642			break;
1643		}
1644
1645		queued++;
1646
1647		/*
1648		 * If there's a BPF listener, bounce a copy of this frame
1649		 * to him.
1650		 */
1651		BPF_MTAP(ifp, m_head);
1652	}
1653
1654	if (queued) {
1655		bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map,
1656		    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1657		/* Transmit - twice due to apparent hardware bug */
1658		CSR_WRITE_4(sc, BFE_DMATX_PTR,
1659		    sc->bfe_tx_prod * sizeof(struct bfe_desc));
1660		/*
1661		 * XXX It seems the following write is not necessary
1662		 * to kick Tx command. What might be required would be
1663		 * a way flushing PCI posted write. Reading the register
1664		 * back ensures the flush operation. In addition,
1665		 * hardware will execute PCI posted write in the long
1666		 * run and watchdog timer for the kick command was set
1667		 * to 5 seconds. Therefore I think the second write
1668		 * access is not necessary or could be replaced with
1669		 * read operation.
1670		 */
1671		CSR_WRITE_4(sc, BFE_DMATX_PTR,
1672		    sc->bfe_tx_prod * sizeof(struct bfe_desc));
1673
1674		/*
1675		 * Set a timeout in case the chip goes out to lunch.
1676		 */
1677		sc->bfe_watchdog_timer = 5;
1678	}
1679}
1680
1681static void
1682bfe_init(void *xsc)
1683{
1684	BFE_LOCK((struct bfe_softc *)xsc);
1685	bfe_init_locked(xsc);
1686	BFE_UNLOCK((struct bfe_softc *)xsc);
1687}
1688
1689static void
1690bfe_init_locked(void *xsc)
1691{
1692	struct bfe_softc *sc = (struct bfe_softc*)xsc;
1693	struct ifnet *ifp = sc->bfe_ifp;
1694	struct mii_data *mii;
1695
1696	BFE_LOCK_ASSERT(sc);
1697
1698	mii = device_get_softc(sc->bfe_miibus);
1699
1700	if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1701		return;
1702
1703	bfe_stop(sc);
1704	bfe_chip_reset(sc);
1705
1706	if (bfe_list_rx_init(sc) == ENOBUFS) {
1707		device_printf(sc->bfe_dev,
1708		    "%s: Not enough memory for list buffers\n", __func__);
1709		bfe_stop(sc);
1710		return;
1711	}
1712	bfe_list_tx_init(sc);
1713
1714	bfe_set_rx_mode(sc);
1715
1716	/* Enable the chip and core */
1717	BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE);
1718	/* Enable interrupts */
1719	CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF);
1720
1721	/* Clear link state and change media. */
1722	sc->bfe_flags &= ~BFE_FLAG_LINK;
1723	mii_mediachg(mii);
1724
1725	ifp->if_drv_flags |= IFF_DRV_RUNNING;
1726	ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1727
1728	callout_reset(&sc->bfe_stat_co, hz, bfe_tick, sc);
1729}
1730
1731/*
1732 * Set media options.
1733 */
1734static int
1735bfe_ifmedia_upd(struct ifnet *ifp)
1736{
1737	struct bfe_softc *sc;
1738	struct mii_data *mii;
1739	int error;
1740
1741	sc = ifp->if_softc;
1742	BFE_LOCK(sc);
1743
1744	mii = device_get_softc(sc->bfe_miibus);
1745	if (mii->mii_instance) {
1746		struct mii_softc *miisc;
1747		for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
1748				miisc = LIST_NEXT(miisc, mii_list))
1749			mii_phy_reset(miisc);
1750	}
1751	error = mii_mediachg(mii);
1752	BFE_UNLOCK(sc);
1753
1754	return (error);
1755}
1756
1757/*
1758 * Report current media status.
1759 */
1760static void
1761bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1762{
1763	struct bfe_softc *sc = ifp->if_softc;
1764	struct mii_data *mii;
1765
1766	BFE_LOCK(sc);
1767	mii = device_get_softc(sc->bfe_miibus);
1768	mii_pollstat(mii);
1769	ifmr->ifm_active = mii->mii_media_active;
1770	ifmr->ifm_status = mii->mii_media_status;
1771	BFE_UNLOCK(sc);
1772}
1773
1774static int
1775bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
1776{
1777	struct bfe_softc *sc = ifp->if_softc;
1778	struct ifreq *ifr = (struct ifreq *) data;
1779	struct mii_data *mii;
1780	int error = 0;
1781
1782	switch (command) {
1783	case SIOCSIFFLAGS:
1784		BFE_LOCK(sc);
1785		if (ifp->if_flags & IFF_UP) {
1786			if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1787				bfe_set_rx_mode(sc);
1788			else if ((sc->bfe_flags & BFE_FLAG_DETACH) == 0)
1789				bfe_init_locked(sc);
1790		} else if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1791			bfe_stop(sc);
1792		BFE_UNLOCK(sc);
1793		break;
1794	case SIOCADDMULTI:
1795	case SIOCDELMULTI:
1796		BFE_LOCK(sc);
1797		if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1798			bfe_set_rx_mode(sc);
1799		BFE_UNLOCK(sc);
1800		break;
1801	case SIOCGIFMEDIA:
1802	case SIOCSIFMEDIA:
1803		mii = device_get_softc(sc->bfe_miibus);
1804		error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1805		break;
1806	default:
1807		error = ether_ioctl(ifp, command, data);
1808		break;
1809	}
1810
1811	return (error);
1812}
1813
1814static void
1815bfe_watchdog(struct bfe_softc *sc)
1816{
1817	struct ifnet *ifp;
1818
1819	BFE_LOCK_ASSERT(sc);
1820
1821	if (sc->bfe_watchdog_timer == 0 || --sc->bfe_watchdog_timer)
1822		return;
1823
1824	ifp = sc->bfe_ifp;
1825
1826	device_printf(sc->bfe_dev, "watchdog timeout -- resetting\n");
1827
1828	ifp->if_oerrors++;
1829	ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1830	bfe_init_locked(sc);
1831
1832	if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1833		bfe_start_locked(ifp);
1834}
1835
1836static void
1837bfe_tick(void *xsc)
1838{
1839	struct bfe_softc *sc = xsc;
1840	struct mii_data *mii;
1841
1842	BFE_LOCK_ASSERT(sc);
1843
1844	mii = device_get_softc(sc->bfe_miibus);
1845	mii_tick(mii);
1846	bfe_stats_update(sc);
1847	bfe_watchdog(sc);
1848	callout_reset(&sc->bfe_stat_co, hz, bfe_tick, sc);
1849}
1850
1851/*
1852 * Stop the adapter and free any mbufs allocated to the
1853 * RX and TX lists.
1854 */
1855static void
1856bfe_stop(struct bfe_softc *sc)
1857{
1858	struct ifnet *ifp;
1859
1860	BFE_LOCK_ASSERT(sc);
1861
1862	ifp = sc->bfe_ifp;
1863	ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1864	sc->bfe_flags &= ~BFE_FLAG_LINK;
1865	callout_stop(&sc->bfe_stat_co);
1866	sc->bfe_watchdog_timer = 0;
1867
1868	bfe_chip_halt(sc);
1869	bfe_tx_ring_free(sc);
1870	bfe_rx_ring_free(sc);
1871}
1872
1873static int
1874sysctl_bfe_stats(SYSCTL_HANDLER_ARGS)
1875{
1876	struct bfe_softc *sc;
1877	struct bfe_hw_stats *stats;
1878	int error, result;
1879
1880	result = -1;
1881	error = sysctl_handle_int(oidp, &result, 0, req);
1882
1883	if (error != 0 || req->newptr == NULL)
1884		return (error);
1885
1886	if (result != 1)
1887		return (error);
1888
1889	sc = (struct bfe_softc *)arg1;
1890	stats = &sc->bfe_stats;
1891
1892	printf("%s statistics:\n", device_get_nameunit(sc->bfe_dev));
1893	printf("Transmit good octets : %ju\n",
1894	    (uintmax_t)stats->tx_good_octets);
1895	printf("Transmit good frames : %ju\n",
1896	    (uintmax_t)stats->tx_good_frames);
1897	printf("Transmit octets : %ju\n",
1898	    (uintmax_t)stats->tx_octets);
1899	printf("Transmit frames : %ju\n",
1900	    (uintmax_t)stats->tx_frames);
1901	printf("Transmit broadcast frames : %ju\n",
1902	    (uintmax_t)stats->tx_bcast_frames);
1903	printf("Transmit multicast frames : %ju\n",
1904	    (uintmax_t)stats->tx_mcast_frames);
1905	printf("Transmit frames 64 bytes : %ju\n",
1906	    (uint64_t)stats->tx_pkts_64);
1907	printf("Transmit frames 65 to 127 bytes : %ju\n",
1908	    (uint64_t)stats->tx_pkts_65_127);
1909	printf("Transmit frames 128 to 255 bytes : %ju\n",
1910	    (uint64_t)stats->tx_pkts_128_255);
1911	printf("Transmit frames 256 to 511 bytes : %ju\n",
1912	    (uint64_t)stats->tx_pkts_256_511);
1913	printf("Transmit frames 512 to 1023 bytes : %ju\n",
1914	    (uint64_t)stats->tx_pkts_512_1023);
1915	printf("Transmit frames 1024 to max bytes : %ju\n",
1916	    (uint64_t)stats->tx_pkts_1024_max);
1917	printf("Transmit jabber errors : %u\n", stats->tx_jabbers);
1918	printf("Transmit oversized frames : %ju\n",
1919	    (uint64_t)stats->tx_oversize_frames);
1920	printf("Transmit fragmented frames : %ju\n",
1921	    (uint64_t)stats->tx_frag_frames);
1922	printf("Transmit underruns : %u\n", stats->tx_colls);
1923	printf("Transmit total collisions : %u\n", stats->tx_single_colls);
1924	printf("Transmit single collisions : %u\n", stats->tx_single_colls);
1925	printf("Transmit multiple collisions : %u\n", stats->tx_multi_colls);
1926	printf("Transmit excess collisions : %u\n", stats->tx_excess_colls);
1927	printf("Transmit late collisions : %u\n", stats->tx_late_colls);
1928	printf("Transmit deferrals : %u\n", stats->tx_deferrals);
1929	printf("Transmit carrier losts : %u\n", stats->tx_carrier_losts);
1930	printf("Transmit pause frames : %u\n", stats->tx_pause_frames);
1931
1932	printf("Receive good octets : %ju\n",
1933	    (uintmax_t)stats->rx_good_octets);
1934	printf("Receive good frames : %ju\n",
1935	    (uintmax_t)stats->rx_good_frames);
1936	printf("Receive octets : %ju\n",
1937	    (uintmax_t)stats->rx_octets);
1938	printf("Receive frames : %ju\n",
1939	    (uintmax_t)stats->rx_frames);
1940	printf("Receive broadcast frames : %ju\n",
1941	    (uintmax_t)stats->rx_bcast_frames);
1942	printf("Receive multicast frames : %ju\n",
1943	    (uintmax_t)stats->rx_mcast_frames);
1944	printf("Receive frames 64 bytes : %ju\n",
1945	    (uint64_t)stats->rx_pkts_64);
1946	printf("Receive frames 65 to 127 bytes : %ju\n",
1947	    (uint64_t)stats->rx_pkts_65_127);
1948	printf("Receive frames 128 to 255 bytes : %ju\n",
1949	    (uint64_t)stats->rx_pkts_128_255);
1950	printf("Receive frames 256 to 511 bytes : %ju\n",
1951	    (uint64_t)stats->rx_pkts_256_511);
1952	printf("Receive frames 512 to 1023 bytes : %ju\n",
1953	    (uint64_t)stats->rx_pkts_512_1023);
1954	printf("Receive frames 1024 to max bytes : %ju\n",
1955	    (uint64_t)stats->rx_pkts_1024_max);
1956	printf("Receive jabber errors : %u\n", stats->rx_jabbers);
1957	printf("Receive oversized frames : %ju\n",
1958	    (uint64_t)stats->rx_oversize_frames);
1959	printf("Receive fragmented frames : %ju\n",
1960	    (uint64_t)stats->rx_frag_frames);
1961	printf("Receive missed frames : %u\n", stats->rx_missed_frames);
1962	printf("Receive CRC align errors : %u\n", stats->rx_crc_align_errs);
1963	printf("Receive undersized frames : %u\n", stats->rx_runts);
1964	printf("Receive CRC errors : %u\n", stats->rx_crc_errs);
1965	printf("Receive align errors : %u\n", stats->rx_align_errs);
1966	printf("Receive symbol errors : %u\n", stats->rx_symbol_errs);
1967	printf("Receive pause frames : %u\n", stats->rx_pause_frames);
1968	printf("Receive control frames : %u\n", stats->rx_control_frames);
1969
1970	return (error);
1971}
1972