if_bfe.c revision 180954
1/*- 2 * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk> 3 * and Duncan Barclay<dmlb@dmlb.org> 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD: head/sys/dev/bfe/if_bfe.c 180954 2008-07-29 09:02:00Z yongari $"); 30 31#include <sys/param.h> 32#include <sys/systm.h> 33#include <sys/sockio.h> 34#include <sys/mbuf.h> 35#include <sys/malloc.h> 36#include <sys/kernel.h> 37#include <sys/module.h> 38#include <sys/socket.h> 39#include <sys/queue.h> 40 41#include <net/if.h> 42#include <net/if_arp.h> 43#include <net/ethernet.h> 44#include <net/if_dl.h> 45#include <net/if_media.h> 46 47#include <net/bpf.h> 48 49#include <net/if_types.h> 50#include <net/if_vlan_var.h> 51 52#include <netinet/in_systm.h> 53#include <netinet/in.h> 54#include <netinet/ip.h> 55 56#include <machine/bus.h> 57#include <machine/resource.h> 58#include <sys/bus.h> 59#include <sys/rman.h> 60 61#include <dev/mii/mii.h> 62#include <dev/mii/miivar.h> 63#include "miidevs.h" 64 65#include <dev/pci/pcireg.h> 66#include <dev/pci/pcivar.h> 67 68#include <dev/bfe/if_bfereg.h> 69 70MODULE_DEPEND(bfe, pci, 1, 1, 1); 71MODULE_DEPEND(bfe, ether, 1, 1, 1); 72MODULE_DEPEND(bfe, miibus, 1, 1, 1); 73 74/* "device miibus" required. See GENERIC if you get errors here. */ 75#include "miibus_if.h" 76 77#define BFE_DEVDESC_MAX 64 /* Maximum device description length */ 78 79static struct bfe_type bfe_devs[] = { 80 { BCOM_VENDORID, BCOM_DEVICEID_BCM4401, 81 "Broadcom BCM4401 Fast Ethernet" }, 82 { BCOM_VENDORID, BCOM_DEVICEID_BCM4401B0, 83 "Broadcom BCM4401-B0 Fast Ethernet" }, 84 { 0, 0, NULL } 85}; 86 87static int bfe_probe (device_t); 88static int bfe_attach (device_t); 89static int bfe_detach (device_t); 90static int bfe_suspend (device_t); 91static int bfe_resume (device_t); 92static void bfe_release_resources (struct bfe_softc *); 93static void bfe_intr (void *); 94static void bfe_start (struct ifnet *); 95static void bfe_start_locked (struct ifnet *); 96static int bfe_ioctl (struct ifnet *, u_long, caddr_t); 97static void bfe_init (void *); 98static void bfe_init_locked (void *); 99static void bfe_stop (struct bfe_softc *); 100static void bfe_watchdog (struct bfe_softc *); 101static int bfe_shutdown (device_t); 102static void bfe_tick (void *); 103static void bfe_txeof (struct bfe_softc *); 104static void bfe_rxeof (struct bfe_softc *); 105static void bfe_set_rx_mode (struct bfe_softc *); 106static int bfe_list_rx_init (struct bfe_softc *); 107static int bfe_list_newbuf (struct bfe_softc *, int, struct mbuf*); 108static void bfe_rx_ring_free (struct bfe_softc *); 109 110static void bfe_pci_setup (struct bfe_softc *, u_int32_t); 111static int bfe_ifmedia_upd (struct ifnet *); 112static void bfe_ifmedia_sts (struct ifnet *, struct ifmediareq *); 113static int bfe_miibus_readreg (device_t, int, int); 114static int bfe_miibus_writereg (device_t, int, int, int); 115static void bfe_miibus_statchg (device_t); 116static int bfe_wait_bit (struct bfe_softc *, u_int32_t, u_int32_t, 117 u_long, const int); 118static void bfe_get_config (struct bfe_softc *sc); 119static void bfe_read_eeprom (struct bfe_softc *, u_int8_t *); 120static void bfe_stats_update (struct bfe_softc *); 121static void bfe_clear_stats (struct bfe_softc *); 122static int bfe_readphy (struct bfe_softc *, u_int32_t, u_int32_t*); 123static int bfe_writephy (struct bfe_softc *, u_int32_t, u_int32_t); 124static int bfe_resetphy (struct bfe_softc *); 125static int bfe_setupphy (struct bfe_softc *); 126static void bfe_chip_reset (struct bfe_softc *); 127static void bfe_chip_halt (struct bfe_softc *); 128static void bfe_core_reset (struct bfe_softc *); 129static void bfe_core_disable (struct bfe_softc *); 130static int bfe_dma_alloc (device_t); 131static void bfe_dma_map_desc (void *, bus_dma_segment_t *, int, int); 132static void bfe_dma_map (void *, bus_dma_segment_t *, int, int); 133static void bfe_cam_write (struct bfe_softc *, u_char *, int); 134 135static device_method_t bfe_methods[] = { 136 /* Device interface */ 137 DEVMETHOD(device_probe, bfe_probe), 138 DEVMETHOD(device_attach, bfe_attach), 139 DEVMETHOD(device_detach, bfe_detach), 140 DEVMETHOD(device_shutdown, bfe_shutdown), 141 DEVMETHOD(device_suspend, bfe_suspend), 142 DEVMETHOD(device_resume, bfe_resume), 143 144 /* bus interface */ 145 DEVMETHOD(bus_print_child, bus_generic_print_child), 146 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 147 148 /* MII interface */ 149 DEVMETHOD(miibus_readreg, bfe_miibus_readreg), 150 DEVMETHOD(miibus_writereg, bfe_miibus_writereg), 151 DEVMETHOD(miibus_statchg, bfe_miibus_statchg), 152 153 { 0, 0 } 154}; 155 156static driver_t bfe_driver = { 157 "bfe", 158 bfe_methods, 159 sizeof(struct bfe_softc) 160}; 161 162static devclass_t bfe_devclass; 163 164DRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, 0, 0); 165DRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, 0, 0); 166 167/* 168 * Probe for a Broadcom 4401 chip. 169 */ 170static int 171bfe_probe(device_t dev) 172{ 173 struct bfe_type *t; 174 uint16_t vendor, devid; 175 176 t = bfe_devs; 177 vendor = pci_get_vendor(dev); 178 devid = pci_get_device(dev); 179 180 while (t->bfe_name != NULL) { 181 if (vendor == t->bfe_vid && devid == t->bfe_did) { 182 device_set_desc_copy(dev, t->bfe_name); 183 return (BUS_PROBE_DEFAULT); 184 } 185 t++; 186 } 187 188 return (ENXIO); 189} 190 191static int 192bfe_dma_alloc(device_t dev) 193{ 194 struct bfe_softc *sc; 195 int error, i; 196 197 sc = device_get_softc(dev); 198 199 /* 200 * parent tag. Apparently the chip cannot handle any DMA address 201 * greater than 1GB. 202 */ 203 error = bus_dma_tag_create(NULL, /* parent */ 204 4096, 0, /* alignment, boundary */ 205 0x3FFFFFFF, /* lowaddr */ 206 BUS_SPACE_MAXADDR, /* highaddr */ 207 NULL, NULL, /* filter, filterarg */ 208 MAXBSIZE, /* maxsize */ 209 BUS_SPACE_UNRESTRICTED, /* num of segments */ 210 BUS_SPACE_MAXSIZE_32BIT, /* max segment size */ 211 0, /* flags */ 212 NULL, NULL, /* lockfunc, lockarg */ 213 &sc->bfe_parent_tag); 214 215 /* tag for TX ring */ 216 error = bus_dma_tag_create(sc->bfe_parent_tag, 217 4096, 0, 218 BUS_SPACE_MAXADDR, 219 BUS_SPACE_MAXADDR, 220 NULL, NULL, 221 BFE_TX_LIST_SIZE, 222 1, 223 BUS_SPACE_MAXSIZE_32BIT, 224 0, 225 NULL, NULL, 226 &sc->bfe_tx_tag); 227 228 if (error) { 229 device_printf(dev, "could not allocate dma tag\n"); 230 return (ENOMEM); 231 } 232 233 /* tag for RX ring */ 234 error = bus_dma_tag_create(sc->bfe_parent_tag, 235 4096, 0, 236 BUS_SPACE_MAXADDR, 237 BUS_SPACE_MAXADDR, 238 NULL, NULL, 239 BFE_RX_LIST_SIZE, 240 1, 241 BUS_SPACE_MAXSIZE_32BIT, 242 0, 243 NULL, NULL, 244 &sc->bfe_rx_tag); 245 246 if (error) { 247 device_printf(dev, "could not allocate dma tag\n"); 248 return (ENOMEM); 249 } 250 251 /* tag for mbufs */ 252 error = bus_dma_tag_create(sc->bfe_parent_tag, 253 ETHER_ALIGN, 0, 254 BUS_SPACE_MAXADDR, 255 BUS_SPACE_MAXADDR, 256 NULL, NULL, 257 MCLBYTES, 258 1, 259 BUS_SPACE_MAXSIZE_32BIT, 260 BUS_DMA_ALLOCNOW, 261 NULL, NULL, 262 &sc->bfe_tag); 263 264 if (error) { 265 device_printf(dev, "could not allocate dma tag\n"); 266 return (ENOMEM); 267 } 268 269 /* pre allocate dmamaps for RX list */ 270 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 271 error = bus_dmamap_create(sc->bfe_tag, 0, 272 &sc->bfe_rx_ring[i].bfe_map); 273 if (error) { 274 device_printf(dev, "cannot create DMA map for RX\n"); 275 return (ENOMEM); 276 } 277 } 278 279 /* pre allocate dmamaps for TX list */ 280 for (i = 0; i < BFE_TX_LIST_CNT; i++) { 281 error = bus_dmamap_create(sc->bfe_tag, 0, 282 &sc->bfe_tx_ring[i].bfe_map); 283 if (error) { 284 device_printf(dev, "cannot create DMA map for TX\n"); 285 return (ENOMEM); 286 } 287 } 288 289 /* Alloc dma for rx ring */ 290 error = bus_dmamem_alloc(sc->bfe_rx_tag, (void *)&sc->bfe_rx_list, 291 BUS_DMA_NOWAIT, &sc->bfe_rx_map); 292 293 if (error) 294 return (ENOMEM); 295 296 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 297 error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map, 298 sc->bfe_rx_list, sizeof(struct bfe_desc), 299 bfe_dma_map, &sc->bfe_rx_dma, BUS_DMA_NOWAIT); 300 301 if (error) 302 return (ENOMEM); 303 304 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE); 305 306 error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list, 307 BUS_DMA_NOWAIT, &sc->bfe_tx_map); 308 if (error) 309 return (ENOMEM); 310 311 312 error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map, 313 sc->bfe_tx_list, sizeof(struct bfe_desc), 314 bfe_dma_map, &sc->bfe_tx_dma, BUS_DMA_NOWAIT); 315 if (error) 316 return (ENOMEM); 317 318 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 319 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREWRITE); 320 321 return (0); 322} 323 324static int 325bfe_attach(device_t dev) 326{ 327 struct ifnet *ifp = NULL; 328 struct bfe_softc *sc; 329 int error = 0, rid; 330 331 sc = device_get_softc(dev); 332 mtx_init(&sc->bfe_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 333 MTX_DEF); 334 callout_init_mtx(&sc->bfe_stat_co, &sc->bfe_mtx, 0); 335 336 sc->bfe_dev = dev; 337 338 /* 339 * Map control/status registers. 340 */ 341 pci_enable_busmaster(dev); 342 343 rid = BFE_PCI_MEMLO; 344 sc->bfe_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 345 RF_ACTIVE); 346 if (sc->bfe_res == NULL) { 347 device_printf(dev, "couldn't map memory\n"); 348 error = ENXIO; 349 goto fail; 350 } 351 352 sc->bfe_btag = rman_get_bustag(sc->bfe_res); 353 sc->bfe_bhandle = rman_get_bushandle(sc->bfe_res); 354 sc->bfe_vhandle = (vm_offset_t)rman_get_virtual(sc->bfe_res); 355 356 /* Allocate interrupt */ 357 rid = 0; 358 359 sc->bfe_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 360 RF_SHAREABLE | RF_ACTIVE); 361 if (sc->bfe_irq == NULL) { 362 device_printf(dev, "couldn't map interrupt\n"); 363 error = ENXIO; 364 goto fail; 365 } 366 367 if (bfe_dma_alloc(dev)) { 368 device_printf(dev, "failed to allocate DMA resources\n"); 369 error = ENXIO; 370 goto fail; 371 } 372 373 /* Set up ifnet structure */ 374 ifp = sc->bfe_ifp = if_alloc(IFT_ETHER); 375 if (ifp == NULL) { 376 device_printf(dev, "failed to if_alloc()\n"); 377 error = ENOSPC; 378 goto fail; 379 } 380 ifp->if_softc = sc; 381 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 382 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 383 ifp->if_ioctl = bfe_ioctl; 384 ifp->if_start = bfe_start; 385 ifp->if_init = bfe_init; 386 ifp->if_mtu = ETHERMTU; 387 IFQ_SET_MAXLEN(&ifp->if_snd, BFE_TX_QLEN); 388 ifp->if_snd.ifq_drv_maxlen = BFE_TX_QLEN; 389 IFQ_SET_READY(&ifp->if_snd); 390 391 bfe_get_config(sc); 392 393 /* Reset the chip and turn on the PHY */ 394 BFE_LOCK(sc); 395 bfe_chip_reset(sc); 396 BFE_UNLOCK(sc); 397 398 if (mii_phy_probe(dev, &sc->bfe_miibus, 399 bfe_ifmedia_upd, bfe_ifmedia_sts)) { 400 device_printf(dev, "MII without any PHY!\n"); 401 error = ENXIO; 402 goto fail; 403 } 404 405 ether_ifattach(ifp, sc->bfe_enaddr); 406 407 /* 408 * Tell the upper layer(s) we support long frames. 409 */ 410 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 411 ifp->if_capabilities |= IFCAP_VLAN_MTU; 412 ifp->if_capenable |= IFCAP_VLAN_MTU; 413 414 /* 415 * Hook interrupt last to avoid having to lock softc 416 */ 417 error = bus_setup_intr(dev, sc->bfe_irq, INTR_TYPE_NET | INTR_MPSAFE, 418 NULL, bfe_intr, sc, &sc->bfe_intrhand); 419 420 if (error) { 421 device_printf(dev, "couldn't set up irq\n"); 422 goto fail; 423 } 424fail: 425 if (error) 426 bfe_release_resources(sc); 427 return (error); 428} 429 430static int 431bfe_detach(device_t dev) 432{ 433 struct bfe_softc *sc; 434 struct ifnet *ifp; 435 436 sc = device_get_softc(dev); 437 438 KASSERT(mtx_initialized(&sc->bfe_mtx), ("bfe mutex not initialized")); 439 440 ifp = sc->bfe_ifp; 441 442 if (device_is_attached(dev)) { 443 BFE_LOCK(sc); 444 bfe_stop(sc); 445 BFE_UNLOCK(sc); 446 callout_drain(&sc->bfe_stat_co); 447 if (ifp != NULL) 448 ether_ifdetach(ifp); 449 } 450 451 bfe_chip_reset(sc); 452 453 bus_generic_detach(dev); 454 if (sc->bfe_miibus != NULL) 455 device_delete_child(dev, sc->bfe_miibus); 456 457 bfe_release_resources(sc); 458 mtx_destroy(&sc->bfe_mtx); 459 460 return (0); 461} 462 463/* 464 * Stop all chip I/O so that the kernel's probe routines don't 465 * get confused by errant DMAs when rebooting. 466 */ 467static int 468bfe_shutdown(device_t dev) 469{ 470 struct bfe_softc *sc; 471 472 sc = device_get_softc(dev); 473 BFE_LOCK(sc); 474 bfe_stop(sc); 475 476 BFE_UNLOCK(sc); 477 478 return (0); 479} 480 481static int 482bfe_suspend(device_t dev) 483{ 484 struct bfe_softc *sc; 485 486 sc = device_get_softc(dev); 487 BFE_LOCK(sc); 488 bfe_stop(sc); 489 BFE_UNLOCK(sc); 490 491 return (0); 492} 493 494static int 495bfe_resume(device_t dev) 496{ 497 struct bfe_softc *sc; 498 struct ifnet *ifp; 499 500 sc = device_get_softc(dev); 501 ifp = sc->bfe_ifp; 502 BFE_LOCK(sc); 503 bfe_chip_reset(sc); 504 if (ifp->if_flags & IFF_UP) { 505 bfe_init_locked(sc); 506 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 507 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 508 bfe_start_locked(ifp); 509 } 510 BFE_UNLOCK(sc); 511 512 return (0); 513} 514 515static int 516bfe_miibus_readreg(device_t dev, int phy, int reg) 517{ 518 struct bfe_softc *sc; 519 u_int32_t ret; 520 521 sc = device_get_softc(dev); 522 if (phy != sc->bfe_phyaddr) 523 return (0); 524 bfe_readphy(sc, reg, &ret); 525 526 return (ret); 527} 528 529static int 530bfe_miibus_writereg(device_t dev, int phy, int reg, int val) 531{ 532 struct bfe_softc *sc; 533 534 sc = device_get_softc(dev); 535 if (phy != sc->bfe_phyaddr) 536 return (0); 537 bfe_writephy(sc, reg, val); 538 539 return (0); 540} 541 542static void 543bfe_miibus_statchg(device_t dev) 544{ 545 struct bfe_softc *sc; 546 struct mii_data *mii; 547 u_int32_t val, flow; 548 549 sc = device_get_softc(dev); 550 mii = device_get_softc(sc->bfe_miibus); 551 552 if ((mii->mii_media_status & IFM_ACTIVE) != 0) { 553 if (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 554 sc->bfe_link = 1; 555 } else 556 sc->bfe_link = 0; 557 558 /* XXX Should stop Rx/Tx engine prior to touching MAC. */ 559 val = CSR_READ_4(sc, BFE_TX_CTRL); 560 val &= ~BFE_TX_DUPLEX; 561 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 562 val |= BFE_TX_DUPLEX; 563 flow = 0; 564#ifdef notyet 565 flow = CSR_READ_4(sc, BFE_RXCONF); 566 flow &= ~BFE_RXCONF_FLOW; 567 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & 568 IFM_ETH_RXPAUSE) != 0) 569 flow |= BFE_RXCONF_FLOW; 570 CSR_WRITE_4(sc, BFE_RXCONF, flow); 571 /* 572 * It seems that the hardware has Tx pause issues 573 * so enable only Rx pause. 574 */ 575 flow = CSR_READ_4(sc, BFE_MAC_FLOW); 576 flow &= ~BFE_FLOW_PAUSE_ENAB; 577 CSR_WRITE_4(sc, BFE_MAC_FLOW, flow); 578#endif 579 } 580 CSR_WRITE_4(sc, BFE_TX_CTRL, val); 581} 582 583static void 584bfe_tx_ring_free(struct bfe_softc *sc) 585{ 586 int i; 587 588 for(i = 0; i < BFE_TX_LIST_CNT; i++) { 589 if (sc->bfe_tx_ring[i].bfe_mbuf != NULL) { 590 m_freem(sc->bfe_tx_ring[i].bfe_mbuf); 591 sc->bfe_tx_ring[i].bfe_mbuf = NULL; 592 bus_dmamap_unload(sc->bfe_tag, 593 sc->bfe_tx_ring[i].bfe_map); 594 } 595 } 596 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 597 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREWRITE); 598} 599 600static void 601bfe_rx_ring_free(struct bfe_softc *sc) 602{ 603 int i; 604 605 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 606 if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) { 607 m_freem(sc->bfe_rx_ring[i].bfe_mbuf); 608 sc->bfe_rx_ring[i].bfe_mbuf = NULL; 609 bus_dmamap_unload(sc->bfe_tag, 610 sc->bfe_rx_ring[i].bfe_map); 611 } 612 } 613 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 614 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE); 615} 616 617static int 618bfe_list_rx_init(struct bfe_softc *sc) 619{ 620 int i; 621 622 for(i = 0; i < BFE_RX_LIST_CNT; i++) { 623 if (bfe_list_newbuf(sc, i, NULL) == ENOBUFS) 624 return (ENOBUFS); 625 } 626 627 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE); 628 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc))); 629 630 sc->bfe_rx_cons = 0; 631 632 return (0); 633} 634 635static int 636bfe_list_newbuf(struct bfe_softc *sc, int c, struct mbuf *m) 637{ 638 struct bfe_rxheader *rx_header; 639 struct bfe_desc *d; 640 struct bfe_data *r; 641 u_int32_t ctrl; 642 int allocated, error; 643 644 if ((c < 0) || (c >= BFE_RX_LIST_CNT)) 645 return (EINVAL); 646 647 allocated = 0; 648 if (m == NULL) { 649 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 650 if (m == NULL) 651 return (ENOBUFS); 652 m->m_len = m->m_pkthdr.len = MCLBYTES; 653 allocated++; 654 } 655 else 656 m->m_data = m->m_ext.ext_buf; 657 658 rx_header = mtod(m, struct bfe_rxheader *); 659 rx_header->len = 0; 660 rx_header->flags = 0; 661 662 /* Map the mbuf into DMA */ 663 sc->bfe_rx_cnt = c; 664 d = &sc->bfe_rx_list[c]; 665 r = &sc->bfe_rx_ring[c]; 666 error = bus_dmamap_load(sc->bfe_tag, r->bfe_map, mtod(m, void *), 667 MCLBYTES, bfe_dma_map_desc, d, BUS_DMA_NOWAIT); 668 if (error != 0) { 669 if (allocated != 0) 670 m_free(m); 671 if (error != ENOMEM) 672 device_printf(sc->bfe_dev, 673 "failed to map RX buffer, error %d\n", error); 674 return (ENOBUFS); 675 } 676 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_PREWRITE); 677 678 ctrl = ETHER_MAX_LEN + 32; 679 680 if (c == BFE_RX_LIST_CNT - 1) 681 ctrl |= BFE_DESC_EOT; 682 683 d->bfe_ctrl = ctrl; 684 r->bfe_mbuf = m; 685 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE); 686 return (0); 687} 688 689static void 690bfe_get_config(struct bfe_softc *sc) 691{ 692 u_int8_t eeprom[128]; 693 694 bfe_read_eeprom(sc, eeprom); 695 696 sc->bfe_enaddr[0] = eeprom[79]; 697 sc->bfe_enaddr[1] = eeprom[78]; 698 sc->bfe_enaddr[2] = eeprom[81]; 699 sc->bfe_enaddr[3] = eeprom[80]; 700 sc->bfe_enaddr[4] = eeprom[83]; 701 sc->bfe_enaddr[5] = eeprom[82]; 702 703 sc->bfe_phyaddr = eeprom[90] & 0x1f; 704 sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1; 705 706 sc->bfe_core_unit = 0; 707 sc->bfe_dma_offset = BFE_PCI_DMA; 708} 709 710static void 711bfe_pci_setup(struct bfe_softc *sc, u_int32_t cores) 712{ 713 u_int32_t bar_orig, pci_rev, val; 714 715 bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4); 716 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4); 717 pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK; 718 719 val = CSR_READ_4(sc, BFE_SBINTVEC); 720 val |= cores; 721 CSR_WRITE_4(sc, BFE_SBINTVEC, val); 722 723 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2); 724 val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST; 725 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val); 726 727 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4); 728} 729 730static void 731bfe_clear_stats(struct bfe_softc *sc) 732{ 733 u_long reg; 734 735 BFE_LOCK_ASSERT(sc); 736 737 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ); 738 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) 739 CSR_READ_4(sc, reg); 740 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) 741 CSR_READ_4(sc, reg); 742} 743 744static int 745bfe_resetphy(struct bfe_softc *sc) 746{ 747 u_int32_t val; 748 749 bfe_writephy(sc, 0, BMCR_RESET); 750 DELAY(100); 751 bfe_readphy(sc, 0, &val); 752 if (val & BMCR_RESET) { 753 device_printf(sc->bfe_dev, "PHY Reset would not complete.\n"); 754 return (ENXIO); 755 } 756 return (0); 757} 758 759static void 760bfe_chip_halt(struct bfe_softc *sc) 761{ 762 BFE_LOCK_ASSERT(sc); 763 /* disable interrupts - not that it actually does..*/ 764 CSR_WRITE_4(sc, BFE_IMASK, 0); 765 CSR_READ_4(sc, BFE_IMASK); 766 767 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 768 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1); 769 770 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 771 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 772 DELAY(10); 773} 774 775static void 776bfe_chip_reset(struct bfe_softc *sc) 777{ 778 u_int32_t val; 779 780 BFE_LOCK_ASSERT(sc); 781 782 /* Set the interrupt vector for the enet core */ 783 bfe_pci_setup(sc, BFE_INTVEC_ENET0); 784 785 /* is core up? */ 786 val = CSR_READ_4(sc, BFE_SBTMSLOW) & 787 (BFE_RESET | BFE_REJECT | BFE_CLOCK); 788 if (val == BFE_CLOCK) { 789 /* It is, so shut it down */ 790 CSR_WRITE_4(sc, BFE_RCV_LAZY, 0); 791 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 792 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1); 793 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 794 sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0; 795 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK) 796 bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE, 797 100, 0); 798 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 799 sc->bfe_rx_prod = sc->bfe_rx_cons = 0; 800 } 801 802 bfe_core_reset(sc); 803 bfe_clear_stats(sc); 804 805 /* 806 * We want the phy registers to be accessible even when 807 * the driver is "downed" so initialize MDC preamble, frequency, 808 * and whether internal or external phy here. 809 */ 810 811 /* 4402 has 62.5Mhz SB clock and internal phy */ 812 CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d); 813 814 /* Internal or external PHY? */ 815 val = CSR_READ_4(sc, BFE_DEVCTRL); 816 if (!(val & BFE_IPP)) 817 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL); 818 else if (CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) { 819 BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR); 820 DELAY(100); 821 } 822 823 /* Enable CRC32 generation and set proper LED modes */ 824 BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB | BFE_CTRL_LED); 825 826 /* Reset or clear powerdown control bit */ 827 BFE_AND(sc, BFE_MAC_CTRL, ~BFE_CTRL_PDOWN); 828 829 CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) & 830 BFE_LAZY_FC_MASK)); 831 832 /* 833 * We don't want lazy interrupts, so just send them at 834 * the end of a frame, please 835 */ 836 BFE_OR(sc, BFE_RCV_LAZY, 0); 837 838 /* Set max lengths, accounting for VLAN tags */ 839 CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32); 840 CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32); 841 842 /* Set watermark XXX - magic */ 843 CSR_WRITE_4(sc, BFE_TX_WMARK, 56); 844 845 /* 846 * Initialise DMA channels 847 * - not forgetting dma addresses need to be added to BFE_PCI_DMA 848 */ 849 CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE); 850 CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA); 851 852 CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) | 853 BFE_RX_CTRL_ENABLE); 854 CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA); 855 856 bfe_resetphy(sc); 857 bfe_setupphy(sc); 858} 859 860static void 861bfe_core_disable(struct bfe_softc *sc) 862{ 863 if ((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET) 864 return; 865 866 /* 867 * Set reject, wait for it set, then wait for the core to stop 868 * being busy, then set reset and reject and enable the clocks. 869 */ 870 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK)); 871 bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0); 872 bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1); 873 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT | 874 BFE_RESET)); 875 CSR_READ_4(sc, BFE_SBTMSLOW); 876 DELAY(10); 877 /* Leave reset and reject set */ 878 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET)); 879 DELAY(10); 880} 881 882static void 883bfe_core_reset(struct bfe_softc *sc) 884{ 885 u_int32_t val; 886 887 /* Disable the core */ 888 bfe_core_disable(sc); 889 890 /* and bring it back up */ 891 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC)); 892 CSR_READ_4(sc, BFE_SBTMSLOW); 893 DELAY(10); 894 895 /* Chip bug, clear SERR, IB and TO if they are set. */ 896 if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR) 897 CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0); 898 val = CSR_READ_4(sc, BFE_SBIMSTATE); 899 if (val & (BFE_IBE | BFE_TO)) 900 CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO)); 901 902 /* Clear reset and allow it to move through the core */ 903 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC)); 904 CSR_READ_4(sc, BFE_SBTMSLOW); 905 DELAY(10); 906 907 /* Leave the clock set */ 908 CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK); 909 CSR_READ_4(sc, BFE_SBTMSLOW); 910 DELAY(10); 911} 912 913static void 914bfe_cam_write(struct bfe_softc *sc, u_char *data, int index) 915{ 916 u_int32_t val; 917 918 val = ((u_int32_t) data[2]) << 24; 919 val |= ((u_int32_t) data[3]) << 16; 920 val |= ((u_int32_t) data[4]) << 8; 921 val |= ((u_int32_t) data[5]); 922 CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val); 923 val = (BFE_CAM_HI_VALID | 924 (((u_int32_t) data[0]) << 8) | 925 (((u_int32_t) data[1]))); 926 CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val); 927 CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE | 928 ((u_int32_t) index << BFE_CAM_INDEX_SHIFT))); 929 bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1); 930} 931 932static void 933bfe_set_rx_mode(struct bfe_softc *sc) 934{ 935 struct ifnet *ifp = sc->bfe_ifp; 936 struct ifmultiaddr *ifma; 937 u_int32_t val; 938 int i = 0; 939 940 val = CSR_READ_4(sc, BFE_RXCONF); 941 942 if (ifp->if_flags & IFF_PROMISC) 943 val |= BFE_RXCONF_PROMISC; 944 else 945 val &= ~BFE_RXCONF_PROMISC; 946 947 if (ifp->if_flags & IFF_BROADCAST) 948 val &= ~BFE_RXCONF_DBCAST; 949 else 950 val |= BFE_RXCONF_DBCAST; 951 952 953 CSR_WRITE_4(sc, BFE_CAM_CTRL, 0); 954 bfe_cam_write(sc, IF_LLADDR(sc->bfe_ifp), i++); 955 956 if (ifp->if_flags & IFF_ALLMULTI) 957 val |= BFE_RXCONF_ALLMULTI; 958 else { 959 val &= ~BFE_RXCONF_ALLMULTI; 960 IF_ADDR_LOCK(ifp); 961 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 962 if (ifma->ifma_addr->sa_family != AF_LINK) 963 continue; 964 bfe_cam_write(sc, 965 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i++); 966 } 967 IF_ADDR_UNLOCK(ifp); 968 } 969 970 CSR_WRITE_4(sc, BFE_RXCONF, val); 971 BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE); 972} 973 974static void 975bfe_dma_map(void *arg, bus_dma_segment_t *segs, int nseg, int error) 976{ 977 u_int32_t *ptr; 978 979 ptr = arg; 980 *ptr = segs->ds_addr; 981} 982 983static void 984bfe_dma_map_desc(void *arg, bus_dma_segment_t *segs, int nseg, int error) 985{ 986 struct bfe_desc *d; 987 988 d = arg; 989 /* The chip needs all addresses to be added to BFE_PCI_DMA */ 990 d->bfe_addr = segs->ds_addr + BFE_PCI_DMA; 991} 992 993static void 994bfe_release_resources(struct bfe_softc *sc) 995{ 996 device_t dev; 997 int i; 998 999 dev = sc->bfe_dev; 1000 1001 if (sc->bfe_vpd_prodname != NULL) 1002 free(sc->bfe_vpd_prodname, M_DEVBUF); 1003 1004 if (sc->bfe_vpd_readonly != NULL) 1005 free(sc->bfe_vpd_readonly, M_DEVBUF); 1006 1007 if (sc->bfe_intrhand != NULL) 1008 bus_teardown_intr(dev, sc->bfe_irq, sc->bfe_intrhand); 1009 1010 if (sc->bfe_irq != NULL) 1011 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bfe_irq); 1012 1013 if (sc->bfe_res != NULL) 1014 bus_release_resource(dev, SYS_RES_MEMORY, 0x10, sc->bfe_res); 1015 1016 if (sc->bfe_ifp != NULL) 1017 if_free(sc->bfe_ifp); 1018 1019 if (sc->bfe_tx_tag != NULL) { 1020 bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map); 1021 bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list, 1022 sc->bfe_tx_map); 1023 bus_dma_tag_destroy(sc->bfe_tx_tag); 1024 sc->bfe_tx_tag = NULL; 1025 } 1026 1027 if (sc->bfe_rx_tag != NULL) { 1028 bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map); 1029 bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list, 1030 sc->bfe_rx_map); 1031 bus_dma_tag_destroy(sc->bfe_rx_tag); 1032 sc->bfe_rx_tag = NULL; 1033 } 1034 1035 if (sc->bfe_tag != NULL) { 1036 for(i = 0; i < BFE_TX_LIST_CNT; i++) { 1037 bus_dmamap_destroy(sc->bfe_tag, 1038 sc->bfe_tx_ring[i].bfe_map); 1039 } 1040 for(i = 0; i < BFE_RX_LIST_CNT; i++) { 1041 bus_dmamap_destroy(sc->bfe_tag, 1042 sc->bfe_rx_ring[i].bfe_map); 1043 } 1044 bus_dma_tag_destroy(sc->bfe_tag); 1045 sc->bfe_tag = NULL; 1046 } 1047 1048 if (sc->bfe_parent_tag != NULL) 1049 bus_dma_tag_destroy(sc->bfe_parent_tag); 1050 1051 return; 1052} 1053 1054static void 1055bfe_read_eeprom(struct bfe_softc *sc, u_int8_t *data) 1056{ 1057 long i; 1058 u_int16_t *ptr = (u_int16_t *)data; 1059 1060 for(i = 0; i < 128; i += 2) 1061 ptr[i/2] = CSR_READ_4(sc, 4096 + i); 1062} 1063 1064static int 1065bfe_wait_bit(struct bfe_softc *sc, u_int32_t reg, u_int32_t bit, 1066 u_long timeout, const int clear) 1067{ 1068 u_long i; 1069 1070 for (i = 0; i < timeout; i++) { 1071 u_int32_t val = CSR_READ_4(sc, reg); 1072 1073 if (clear && !(val & bit)) 1074 break; 1075 if (!clear && (val & bit)) 1076 break; 1077 DELAY(10); 1078 } 1079 if (i == timeout) { 1080 device_printf(sc->bfe_dev, 1081 "BUG! Timeout waiting for bit %08x of register " 1082 "%x to %s.\n", bit, reg, (clear ? "clear" : "set")); 1083 return (-1); 1084 } 1085 return (0); 1086} 1087 1088static int 1089bfe_readphy(struct bfe_softc *sc, u_int32_t reg, u_int32_t *val) 1090{ 1091 int err; 1092 1093 /* Clear MII ISR */ 1094 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1095 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1096 (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) | 1097 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1098 (reg << BFE_MDIO_RA_SHIFT) | 1099 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT))); 1100 err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1101 *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA; 1102 1103 return (err); 1104} 1105 1106static int 1107bfe_writephy(struct bfe_softc *sc, u_int32_t reg, u_int32_t val) 1108{ 1109 int status; 1110 1111 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1112 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1113 (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) | 1114 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1115 (reg << BFE_MDIO_RA_SHIFT) | 1116 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) | 1117 (val & BFE_MDIO_DATA_DATA))); 1118 status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1119 1120 return (status); 1121} 1122 1123/* 1124 * XXX - I think this is handled by the PHY driver, but it can't hurt to do it 1125 * twice 1126 */ 1127static int 1128bfe_setupphy(struct bfe_softc *sc) 1129{ 1130 u_int32_t val; 1131 1132 /* Enable activity LED */ 1133 bfe_readphy(sc, 26, &val); 1134 bfe_writephy(sc, 26, val & 0x7fff); 1135 bfe_readphy(sc, 26, &val); 1136 1137 /* Enable traffic meter LED mode */ 1138 bfe_readphy(sc, 27, &val); 1139 bfe_writephy(sc, 27, val | (1 << 6)); 1140 1141 return (0); 1142} 1143 1144static void 1145bfe_stats_update(struct bfe_softc *sc) 1146{ 1147 u_long reg; 1148 u_int32_t *val; 1149 1150 val = &sc->bfe_hwstats.tx_good_octets; 1151 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) { 1152 *val++ += CSR_READ_4(sc, reg); 1153 } 1154 val = &sc->bfe_hwstats.rx_good_octets; 1155 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) { 1156 *val++ += CSR_READ_4(sc, reg); 1157 } 1158} 1159 1160static void 1161bfe_txeof(struct bfe_softc *sc) 1162{ 1163 struct ifnet *ifp; 1164 int i, chipidx; 1165 1166 BFE_LOCK_ASSERT(sc); 1167 1168 ifp = sc->bfe_ifp; 1169 1170 chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK; 1171 chipidx /= sizeof(struct bfe_desc); 1172 1173 i = sc->bfe_tx_cons; 1174 /* Go through the mbufs and free those that have been transmitted */ 1175 while (i != chipidx) { 1176 struct bfe_data *r = &sc->bfe_tx_ring[i]; 1177 if (r->bfe_mbuf != NULL) { 1178 ifp->if_opackets++; 1179 m_freem(r->bfe_mbuf); 1180 r->bfe_mbuf = NULL; 1181 } 1182 bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1183 sc->bfe_tx_cnt--; 1184 BFE_INC(i, BFE_TX_LIST_CNT); 1185 } 1186 1187 if (i != sc->bfe_tx_cons) { 1188 /* we freed up some mbufs */ 1189 sc->bfe_tx_cons = i; 1190 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1191 } 1192 1193 if (sc->bfe_tx_cnt == 0) 1194 sc->bfe_watchdog_timer = 0; 1195} 1196 1197/* Pass a received packet up the stack */ 1198static void 1199bfe_rxeof(struct bfe_softc *sc) 1200{ 1201 struct mbuf *m; 1202 struct ifnet *ifp; 1203 struct bfe_rxheader *rxheader; 1204 struct bfe_data *r; 1205 int cons; 1206 u_int32_t status, current, len, flags; 1207 1208 BFE_LOCK_ASSERT(sc); 1209 cons = sc->bfe_rx_cons; 1210 status = CSR_READ_4(sc, BFE_DMARX_STAT); 1211 current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc); 1212 1213 ifp = sc->bfe_ifp; 1214 1215 while (current != cons) { 1216 r = &sc->bfe_rx_ring[cons]; 1217 m = r->bfe_mbuf; 1218 rxheader = mtod(m, struct bfe_rxheader*); 1219 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_POSTREAD); 1220 len = rxheader->len; 1221 r->bfe_mbuf = NULL; 1222 1223 bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1224 flags = rxheader->flags; 1225 1226 len -= ETHER_CRC_LEN; 1227 1228 /* flag an error and try again */ 1229 if ((len > ETHER_MAX_LEN+32) || (flags & BFE_RX_FLAG_ERRORS)) { 1230 ifp->if_ierrors++; 1231 if (flags & BFE_RX_FLAG_SERR) 1232 ifp->if_collisions++; 1233 bfe_list_newbuf(sc, cons, m); 1234 BFE_INC(cons, BFE_RX_LIST_CNT); 1235 continue; 1236 } 1237 1238 /* Go past the rx header */ 1239 if (bfe_list_newbuf(sc, cons, NULL) == 0) { 1240 m_adj(m, BFE_RX_OFFSET); 1241 m->m_len = m->m_pkthdr.len = len; 1242 } else { 1243 bfe_list_newbuf(sc, cons, m); 1244 ifp->if_ierrors++; 1245 BFE_INC(cons, BFE_RX_LIST_CNT); 1246 continue; 1247 } 1248 1249 ifp->if_ipackets++; 1250 m->m_pkthdr.rcvif = ifp; 1251 BFE_UNLOCK(sc); 1252 (*ifp->if_input)(ifp, m); 1253 BFE_LOCK(sc); 1254 1255 BFE_INC(cons, BFE_RX_LIST_CNT); 1256 } 1257 sc->bfe_rx_cons = cons; 1258} 1259 1260static void 1261bfe_intr(void *xsc) 1262{ 1263 struct bfe_softc *sc = xsc; 1264 struct ifnet *ifp; 1265 u_int32_t istat, imask, flag; 1266 1267 ifp = sc->bfe_ifp; 1268 1269 BFE_LOCK(sc); 1270 1271 istat = CSR_READ_4(sc, BFE_ISTAT); 1272 imask = CSR_READ_4(sc, BFE_IMASK); 1273 1274 /* 1275 * Defer unsolicited interrupts - This is necessary because setting the 1276 * chips interrupt mask register to 0 doesn't actually stop the 1277 * interrupts 1278 */ 1279 istat &= imask; 1280 CSR_WRITE_4(sc, BFE_ISTAT, istat); 1281 CSR_READ_4(sc, BFE_ISTAT); 1282 1283 /* not expecting this interrupt, disregard it */ 1284 if (istat == 0) { 1285 BFE_UNLOCK(sc); 1286 return; 1287 } 1288 1289 if (istat & BFE_ISTAT_ERRORS) { 1290 1291 if (istat & BFE_ISTAT_DSCE) { 1292 device_printf(sc->bfe_dev, "Descriptor Error\n"); 1293 bfe_stop(sc); 1294 BFE_UNLOCK(sc); 1295 return; 1296 } 1297 1298 if (istat & BFE_ISTAT_DPE) { 1299 device_printf(sc->bfe_dev, 1300 "Descriptor Protocol Error\n"); 1301 bfe_stop(sc); 1302 BFE_UNLOCK(sc); 1303 return; 1304 } 1305 1306 flag = CSR_READ_4(sc, BFE_DMATX_STAT); 1307 if (flag & BFE_STAT_EMASK) 1308 ifp->if_oerrors++; 1309 1310 flag = CSR_READ_4(sc, BFE_DMARX_STAT); 1311 if (flag & BFE_RX_FLAG_ERRORS) 1312 ifp->if_ierrors++; 1313 1314 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1315 bfe_init_locked(sc); 1316 } 1317 1318 /* A packet was received */ 1319 if (istat & BFE_ISTAT_RX) 1320 bfe_rxeof(sc); 1321 1322 /* A packet was sent */ 1323 if (istat & BFE_ISTAT_TX) 1324 bfe_txeof(sc); 1325 1326 /* We have packets pending, fire them out */ 1327 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1328 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1329 bfe_start_locked(ifp); 1330 1331 BFE_UNLOCK(sc); 1332} 1333 1334static int 1335bfe_encap(struct bfe_softc *sc, struct mbuf **m_head, u_int32_t *txidx) 1336{ 1337 struct bfe_desc *d = NULL; 1338 struct bfe_data *r = NULL; 1339 struct mbuf *m; 1340 u_int32_t frag, cur, cnt = 0; 1341 int chainlen = 0; 1342 int error; 1343 1344 if (BFE_TX_LIST_CNT - sc->bfe_tx_cnt < 2) 1345 return (ENOBUFS); 1346 1347 /* 1348 * Count the number of frags in this chain to see if 1349 * we need to m_defrag. Since the descriptor list is shared 1350 * by all packets, we'll m_defrag long chains so that they 1351 * do not use up the entire list, even if they would fit. 1352 */ 1353 for(m = *m_head; m != NULL; m = m->m_next) 1354 chainlen++; 1355 1356 1357 if ((chainlen > BFE_TX_LIST_CNT / 4) || 1358 ((BFE_TX_LIST_CNT - (chainlen + sc->bfe_tx_cnt)) < 2)) { 1359 m = m_defrag(*m_head, M_DONTWAIT); 1360 if (m == NULL) 1361 return (ENOBUFS); 1362 *m_head = m; 1363 } 1364 1365 /* 1366 * Start packing the mbufs in this chain into 1367 * the fragment pointers. Stop when we run out 1368 * of fragments or hit the end of the mbuf chain. 1369 */ 1370 cur = frag = *txidx; 1371 cnt = 0; 1372 1373 for(m = *m_head; m != NULL; m = m->m_next) { 1374 if (m->m_len != 0) { 1375 if ((BFE_TX_LIST_CNT - (sc->bfe_tx_cnt + cnt)) < 2) 1376 return (ENOBUFS); 1377 1378 d = &sc->bfe_tx_list[cur]; 1379 r = &sc->bfe_tx_ring[cur]; 1380 d->bfe_ctrl = BFE_DESC_LEN & m->m_len; 1381 /* always intterupt on completion */ 1382 d->bfe_ctrl |= BFE_DESC_IOC; 1383 if (cnt == 0) 1384 /* Set start of frame */ 1385 d->bfe_ctrl |= BFE_DESC_SOF; 1386 if (cur == BFE_TX_LIST_CNT - 1) 1387 /* 1388 * Tell the chip to wrap to the start of 1389 * the descriptor list 1390 */ 1391 d->bfe_ctrl |= BFE_DESC_EOT; 1392 1393 error = bus_dmamap_load(sc->bfe_tag, 1394 r->bfe_map, mtod(m, void*), m->m_len, 1395 bfe_dma_map_desc, d, BUS_DMA_NOWAIT); 1396 if (error) 1397 return (ENOBUFS); 1398 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, 1399 BUS_DMASYNC_PREWRITE); 1400 1401 frag = cur; 1402 BFE_INC(cur, BFE_TX_LIST_CNT); 1403 cnt++; 1404 } 1405 } 1406 1407 if (m != NULL) 1408 return (ENOBUFS); 1409 1410 sc->bfe_tx_list[frag].bfe_ctrl |= BFE_DESC_EOF; 1411 sc->bfe_tx_ring[frag].bfe_mbuf = *m_head; 1412 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREWRITE); 1413 1414 *txidx = cur; 1415 sc->bfe_tx_cnt += cnt; 1416 return (0); 1417} 1418 1419/* 1420 * Set up to transmit a packet. 1421 */ 1422static void 1423bfe_start(struct ifnet *ifp) 1424{ 1425 BFE_LOCK((struct bfe_softc *)ifp->if_softc); 1426 bfe_start_locked(ifp); 1427 BFE_UNLOCK((struct bfe_softc *)ifp->if_softc); 1428} 1429 1430/* 1431 * Set up to transmit a packet. The softc is already locked. 1432 */ 1433static void 1434bfe_start_locked(struct ifnet *ifp) 1435{ 1436 struct bfe_softc *sc; 1437 struct mbuf *m_head = NULL; 1438 int idx, queued = 0; 1439 1440 sc = ifp->if_softc; 1441 idx = sc->bfe_tx_prod; 1442 1443 BFE_LOCK_ASSERT(sc); 1444 1445 /* 1446 * Not much point trying to send if the link is down 1447 * or we have nothing to send. 1448 */ 1449 if (!sc->bfe_link && ifp->if_snd.ifq_len < 10) 1450 return; 1451 1452 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1453 IFF_DRV_RUNNING) 1454 return; 1455 1456 while (sc->bfe_tx_ring[idx].bfe_mbuf == NULL) { 1457 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1458 if (m_head == NULL) 1459 break; 1460 1461 /* 1462 * Pack the data into the tx ring. If we dont have 1463 * enough room, let the chip drain the ring. 1464 */ 1465 if (bfe_encap(sc, &m_head, &idx)) { 1466 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1467 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1468 break; 1469 } 1470 1471 queued++; 1472 1473 /* 1474 * If there's a BPF listener, bounce a copy of this frame 1475 * to him. 1476 */ 1477 BPF_MTAP(ifp, m_head); 1478 } 1479 1480 if (queued) { 1481 sc->bfe_tx_prod = idx; 1482 /* Transmit - twice due to apparent hardware bug */ 1483 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1484 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1485 1486 /* 1487 * Set a timeout in case the chip goes out to lunch. 1488 */ 1489 sc->bfe_watchdog_timer = 5; 1490 } 1491} 1492 1493static void 1494bfe_init(void *xsc) 1495{ 1496 BFE_LOCK((struct bfe_softc *)xsc); 1497 bfe_init_locked(xsc); 1498 BFE_UNLOCK((struct bfe_softc *)xsc); 1499} 1500 1501static void 1502bfe_init_locked(void *xsc) 1503{ 1504 struct bfe_softc *sc = (struct bfe_softc*)xsc; 1505 struct ifnet *ifp = sc->bfe_ifp; 1506 struct mii_data *mii; 1507 1508 BFE_LOCK_ASSERT(sc); 1509 1510 mii = device_get_softc(sc->bfe_miibus); 1511 1512 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1513 return; 1514 1515 bfe_stop(sc); 1516 bfe_chip_reset(sc); 1517 1518 if (bfe_list_rx_init(sc) == ENOBUFS) { 1519 device_printf(sc->bfe_dev, 1520 "%s: Not enough memory for list buffers\n", __func__); 1521 bfe_stop(sc); 1522 return; 1523 } 1524 1525 bfe_set_rx_mode(sc); 1526 1527 /* Enable the chip and core */ 1528 BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE); 1529 /* Enable interrupts */ 1530 CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF); 1531 1532 /* Clear link state and change media. */ 1533 sc->bfe_link = 0; 1534 mii_mediachg(mii); 1535 1536 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1537 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1538 1539 callout_reset(&sc->bfe_stat_co, hz, bfe_tick, sc); 1540} 1541 1542/* 1543 * Set media options. 1544 */ 1545static int 1546bfe_ifmedia_upd(struct ifnet *ifp) 1547{ 1548 struct bfe_softc *sc; 1549 struct mii_data *mii; 1550 int error; 1551 1552 sc = ifp->if_softc; 1553 BFE_LOCK(sc); 1554 1555 mii = device_get_softc(sc->bfe_miibus); 1556 if (mii->mii_instance) { 1557 struct mii_softc *miisc; 1558 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1559 miisc = LIST_NEXT(miisc, mii_list)) 1560 mii_phy_reset(miisc); 1561 } 1562 error = mii_mediachg(mii); 1563 BFE_UNLOCK(sc); 1564 1565 return (error); 1566} 1567 1568/* 1569 * Report current media status. 1570 */ 1571static void 1572bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1573{ 1574 struct bfe_softc *sc = ifp->if_softc; 1575 struct mii_data *mii; 1576 1577 BFE_LOCK(sc); 1578 mii = device_get_softc(sc->bfe_miibus); 1579 mii_pollstat(mii); 1580 ifmr->ifm_active = mii->mii_media_active; 1581 ifmr->ifm_status = mii->mii_media_status; 1582 BFE_UNLOCK(sc); 1583} 1584 1585static int 1586bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1587{ 1588 struct bfe_softc *sc = ifp->if_softc; 1589 struct ifreq *ifr = (struct ifreq *) data; 1590 struct mii_data *mii; 1591 int error = 0; 1592 1593 switch (command) { 1594 case SIOCSIFFLAGS: 1595 BFE_LOCK(sc); 1596 if (ifp->if_flags & IFF_UP) 1597 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1598 bfe_set_rx_mode(sc); 1599 else 1600 bfe_init_locked(sc); 1601 else if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1602 bfe_stop(sc); 1603 BFE_UNLOCK(sc); 1604 break; 1605 case SIOCADDMULTI: 1606 case SIOCDELMULTI: 1607 BFE_LOCK(sc); 1608 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1609 bfe_set_rx_mode(sc); 1610 BFE_UNLOCK(sc); 1611 break; 1612 case SIOCGIFMEDIA: 1613 case SIOCSIFMEDIA: 1614 mii = device_get_softc(sc->bfe_miibus); 1615 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1616 break; 1617 default: 1618 error = ether_ioctl(ifp, command, data); 1619 break; 1620 } 1621 1622 return (error); 1623} 1624 1625static void 1626bfe_watchdog(struct bfe_softc *sc) 1627{ 1628 struct ifnet *ifp; 1629 1630 BFE_LOCK_ASSERT(sc); 1631 1632 if (sc->bfe_watchdog_timer == 0 || --sc->bfe_watchdog_timer) 1633 return; 1634 1635 ifp = sc->bfe_ifp; 1636 1637 device_printf(sc->bfe_dev, "watchdog timeout -- resetting\n"); 1638 1639 ifp->if_oerrors++; 1640 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1641 bfe_init_locked(sc); 1642 1643 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1644 bfe_start_locked(ifp); 1645} 1646 1647static void 1648bfe_tick(void *xsc) 1649{ 1650 struct bfe_softc *sc = xsc; 1651 struct mii_data *mii; 1652 1653 BFE_LOCK_ASSERT(sc); 1654 1655 mii = device_get_softc(sc->bfe_miibus); 1656 mii_tick(mii); 1657 bfe_stats_update(sc); 1658 bfe_watchdog(sc); 1659 callout_reset(&sc->bfe_stat_co, hz, bfe_tick, sc); 1660} 1661 1662/* 1663 * Stop the adapter and free any mbufs allocated to the 1664 * RX and TX lists. 1665 */ 1666static void 1667bfe_stop(struct bfe_softc *sc) 1668{ 1669 struct ifnet *ifp; 1670 1671 BFE_LOCK_ASSERT(sc); 1672 1673 ifp = sc->bfe_ifp; 1674 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1675 sc->bfe_link = 0; 1676 callout_stop(&sc->bfe_stat_co); 1677 sc->bfe_watchdog_timer = 0; 1678 1679 bfe_chip_halt(sc); 1680 bfe_tx_ring_free(sc); 1681 bfe_rx_ring_free(sc); 1682} 1683