if_bfe.c revision 178687
1/*- 2 * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk> 3 * and Duncan Barclay<dmlb@dmlb.org> 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD: head/sys/dev/bfe/if_bfe.c 178687 2008-04-30 02:49:24Z yongari $"); 30 31#include <sys/param.h> 32#include <sys/systm.h> 33#include <sys/sockio.h> 34#include <sys/mbuf.h> 35#include <sys/malloc.h> 36#include <sys/kernel.h> 37#include <sys/module.h> 38#include <sys/socket.h> 39#include <sys/queue.h> 40 41#include <net/if.h> 42#include <net/if_arp.h> 43#include <net/ethernet.h> 44#include <net/if_dl.h> 45#include <net/if_media.h> 46 47#include <net/bpf.h> 48 49#include <net/if_types.h> 50#include <net/if_vlan_var.h> 51 52#include <netinet/in_systm.h> 53#include <netinet/in.h> 54#include <netinet/ip.h> 55 56#include <machine/bus.h> 57#include <machine/resource.h> 58#include <sys/bus.h> 59#include <sys/rman.h> 60 61#include <dev/mii/mii.h> 62#include <dev/mii/miivar.h> 63#include "miidevs.h" 64 65#include <dev/pci/pcireg.h> 66#include <dev/pci/pcivar.h> 67 68#include <dev/bfe/if_bfereg.h> 69 70MODULE_DEPEND(bfe, pci, 1, 1, 1); 71MODULE_DEPEND(bfe, ether, 1, 1, 1); 72MODULE_DEPEND(bfe, miibus, 1, 1, 1); 73 74/* "device miibus" required. See GENERIC if you get errors here. */ 75#include "miibus_if.h" 76 77#define BFE_DEVDESC_MAX 64 /* Maximum device description length */ 78 79static struct bfe_type bfe_devs[] = { 80 { BCOM_VENDORID, BCOM_DEVICEID_BCM4401, 81 "Broadcom BCM4401 Fast Ethernet" }, 82 { BCOM_VENDORID, BCOM_DEVICEID_BCM4401B0, 83 "Broadcom BCM4401-B0 Fast Ethernet" }, 84 { 0, 0, NULL } 85}; 86 87static int bfe_probe (device_t); 88static int bfe_attach (device_t); 89static int bfe_detach (device_t); 90static int bfe_suspend (device_t); 91static int bfe_resume (device_t); 92static void bfe_release_resources (struct bfe_softc *); 93static void bfe_intr (void *); 94static void bfe_start (struct ifnet *); 95static void bfe_start_locked (struct ifnet *); 96static int bfe_ioctl (struct ifnet *, u_long, caddr_t); 97static void bfe_init (void *); 98static void bfe_init_locked (void *); 99static void bfe_stop (struct bfe_softc *); 100static void bfe_watchdog (struct bfe_softc *); 101static int bfe_shutdown (device_t); 102static void bfe_tick (void *); 103static void bfe_txeof (struct bfe_softc *); 104static void bfe_rxeof (struct bfe_softc *); 105static void bfe_set_rx_mode (struct bfe_softc *); 106static int bfe_list_rx_init (struct bfe_softc *); 107static int bfe_list_newbuf (struct bfe_softc *, int, struct mbuf*); 108static void bfe_rx_ring_free (struct bfe_softc *); 109 110static void bfe_pci_setup (struct bfe_softc *, u_int32_t); 111static int bfe_ifmedia_upd (struct ifnet *); 112static void bfe_ifmedia_sts (struct ifnet *, struct ifmediareq *); 113static int bfe_miibus_readreg (device_t, int, int); 114static int bfe_miibus_writereg (device_t, int, int, int); 115static void bfe_miibus_statchg (device_t); 116static int bfe_wait_bit (struct bfe_softc *, u_int32_t, u_int32_t, 117 u_long, const int); 118static void bfe_get_config (struct bfe_softc *sc); 119static void bfe_read_eeprom (struct bfe_softc *, u_int8_t *); 120static void bfe_stats_update (struct bfe_softc *); 121static void bfe_clear_stats (struct bfe_softc *); 122static int bfe_readphy (struct bfe_softc *, u_int32_t, u_int32_t*); 123static int bfe_writephy (struct bfe_softc *, u_int32_t, u_int32_t); 124static int bfe_resetphy (struct bfe_softc *); 125static int bfe_setupphy (struct bfe_softc *); 126static void bfe_chip_reset (struct bfe_softc *); 127static void bfe_chip_halt (struct bfe_softc *); 128static void bfe_core_reset (struct bfe_softc *); 129static void bfe_core_disable (struct bfe_softc *); 130static int bfe_dma_alloc (device_t); 131static void bfe_dma_map_desc (void *, bus_dma_segment_t *, int, int); 132static void bfe_dma_map (void *, bus_dma_segment_t *, int, int); 133static void bfe_cam_write (struct bfe_softc *, u_char *, int); 134 135static device_method_t bfe_methods[] = { 136 /* Device interface */ 137 DEVMETHOD(device_probe, bfe_probe), 138 DEVMETHOD(device_attach, bfe_attach), 139 DEVMETHOD(device_detach, bfe_detach), 140 DEVMETHOD(device_shutdown, bfe_shutdown), 141 DEVMETHOD(device_suspend, bfe_suspend), 142 DEVMETHOD(device_resume, bfe_resume), 143 144 /* bus interface */ 145 DEVMETHOD(bus_print_child, bus_generic_print_child), 146 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 147 148 /* MII interface */ 149 DEVMETHOD(miibus_readreg, bfe_miibus_readreg), 150 DEVMETHOD(miibus_writereg, bfe_miibus_writereg), 151 DEVMETHOD(miibus_statchg, bfe_miibus_statchg), 152 153 { 0, 0 } 154}; 155 156static driver_t bfe_driver = { 157 "bfe", 158 bfe_methods, 159 sizeof(struct bfe_softc) 160}; 161 162static devclass_t bfe_devclass; 163 164DRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, 0, 0); 165DRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, 0, 0); 166 167/* 168 * Probe for a Broadcom 4401 chip. 169 */ 170static int 171bfe_probe(device_t dev) 172{ 173 struct bfe_type *t; 174 struct bfe_softc *sc; 175 176 t = bfe_devs; 177 178 sc = device_get_softc(dev); 179 bzero(sc, sizeof(struct bfe_softc)); 180 sc->bfe_unit = device_get_unit(dev); 181 sc->bfe_dev = dev; 182 183 while(t->bfe_name != NULL) { 184 if ((pci_get_vendor(dev) == t->bfe_vid) && 185 (pci_get_device(dev) == t->bfe_did)) { 186 device_set_desc_copy(dev, t->bfe_name); 187 return (BUS_PROBE_DEFAULT); 188 } 189 t++; 190 } 191 192 return (ENXIO); 193} 194 195static int 196bfe_dma_alloc(device_t dev) 197{ 198 struct bfe_softc *sc; 199 int error, i; 200 201 sc = device_get_softc(dev); 202 203 /* 204 * parent tag. Apparently the chip cannot handle any DMA address 205 * greater than 1GB. 206 */ 207 error = bus_dma_tag_create(NULL, /* parent */ 208 4096, 0, /* alignment, boundary */ 209 0x3FFFFFFF, /* lowaddr */ 210 BUS_SPACE_MAXADDR, /* highaddr */ 211 NULL, NULL, /* filter, filterarg */ 212 MAXBSIZE, /* maxsize */ 213 BUS_SPACE_UNRESTRICTED, /* num of segments */ 214 BUS_SPACE_MAXSIZE_32BIT, /* max segment size */ 215 0, /* flags */ 216 NULL, NULL, /* lockfunc, lockarg */ 217 &sc->bfe_parent_tag); 218 219 /* tag for TX ring */ 220 error = bus_dma_tag_create(sc->bfe_parent_tag, 221 4096, 0, 222 BUS_SPACE_MAXADDR, 223 BUS_SPACE_MAXADDR, 224 NULL, NULL, 225 BFE_TX_LIST_SIZE, 226 1, 227 BUS_SPACE_MAXSIZE_32BIT, 228 0, 229 NULL, NULL, 230 &sc->bfe_tx_tag); 231 232 if (error) { 233 device_printf(dev, "could not allocate dma tag\n"); 234 return (ENOMEM); 235 } 236 237 /* tag for RX ring */ 238 error = bus_dma_tag_create(sc->bfe_parent_tag, 239 4096, 0, 240 BUS_SPACE_MAXADDR, 241 BUS_SPACE_MAXADDR, 242 NULL, NULL, 243 BFE_RX_LIST_SIZE, 244 1, 245 BUS_SPACE_MAXSIZE_32BIT, 246 0, 247 NULL, NULL, 248 &sc->bfe_rx_tag); 249 250 if (error) { 251 device_printf(dev, "could not allocate dma tag\n"); 252 return (ENOMEM); 253 } 254 255 /* tag for mbufs */ 256 error = bus_dma_tag_create(sc->bfe_parent_tag, 257 ETHER_ALIGN, 0, 258 BUS_SPACE_MAXADDR, 259 BUS_SPACE_MAXADDR, 260 NULL, NULL, 261 MCLBYTES, 262 1, 263 BUS_SPACE_MAXSIZE_32BIT, 264 BUS_DMA_ALLOCNOW, 265 NULL, NULL, 266 &sc->bfe_tag); 267 268 if (error) { 269 device_printf(dev, "could not allocate dma tag\n"); 270 return (ENOMEM); 271 } 272 273 /* pre allocate dmamaps for RX list */ 274 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 275 error = bus_dmamap_create(sc->bfe_tag, 0, 276 &sc->bfe_rx_ring[i].bfe_map); 277 if (error) { 278 device_printf(dev, "cannot create DMA map for RX\n"); 279 return (ENOMEM); 280 } 281 } 282 283 /* pre allocate dmamaps for TX list */ 284 for (i = 0; i < BFE_TX_LIST_CNT; i++) { 285 error = bus_dmamap_create(sc->bfe_tag, 0, 286 &sc->bfe_tx_ring[i].bfe_map); 287 if (error) { 288 device_printf(dev, "cannot create DMA map for TX\n"); 289 return (ENOMEM); 290 } 291 } 292 293 /* Alloc dma for rx ring */ 294 error = bus_dmamem_alloc(sc->bfe_rx_tag, (void *)&sc->bfe_rx_list, 295 BUS_DMA_NOWAIT, &sc->bfe_rx_map); 296 297 if(error) 298 return (ENOMEM); 299 300 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 301 error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map, 302 sc->bfe_rx_list, sizeof(struct bfe_desc), 303 bfe_dma_map, &sc->bfe_rx_dma, BUS_DMA_NOWAIT); 304 305 if(error) 306 return (ENOMEM); 307 308 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE); 309 310 error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list, 311 BUS_DMA_NOWAIT, &sc->bfe_tx_map); 312 if (error) 313 return (ENOMEM); 314 315 316 error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map, 317 sc->bfe_tx_list, sizeof(struct bfe_desc), 318 bfe_dma_map, &sc->bfe_tx_dma, BUS_DMA_NOWAIT); 319 if(error) 320 return (ENOMEM); 321 322 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 323 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREWRITE); 324 325 return (0); 326} 327 328static int 329bfe_attach(device_t dev) 330{ 331 struct ifnet *ifp = NULL; 332 struct bfe_softc *sc; 333 int unit, error = 0, rid; 334 335 sc = device_get_softc(dev); 336 mtx_init(&sc->bfe_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 337 MTX_DEF); 338 callout_init_mtx(&sc->bfe_stat_co, &sc->bfe_mtx, 0); 339 340 unit = device_get_unit(dev); 341 sc->bfe_dev = dev; 342 sc->bfe_unit = unit; 343 344 /* 345 * Map control/status registers. 346 */ 347 pci_enable_busmaster(dev); 348 349 rid = BFE_PCI_MEMLO; 350 sc->bfe_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 351 RF_ACTIVE); 352 if (sc->bfe_res == NULL) { 353 printf ("bfe%d: couldn't map memory\n", unit); 354 error = ENXIO; 355 goto fail; 356 } 357 358 sc->bfe_btag = rman_get_bustag(sc->bfe_res); 359 sc->bfe_bhandle = rman_get_bushandle(sc->bfe_res); 360 sc->bfe_vhandle = (vm_offset_t)rman_get_virtual(sc->bfe_res); 361 362 /* Allocate interrupt */ 363 rid = 0; 364 365 sc->bfe_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 366 RF_SHAREABLE | RF_ACTIVE); 367 if (sc->bfe_irq == NULL) { 368 printf("bfe%d: couldn't map interrupt\n", unit); 369 error = ENXIO; 370 goto fail; 371 } 372 373 if (bfe_dma_alloc(dev)) { 374 printf("bfe%d: failed to allocate DMA resources\n", 375 sc->bfe_unit); 376 error = ENXIO; 377 goto fail; 378 } 379 380 /* Set up ifnet structure */ 381 ifp = sc->bfe_ifp = if_alloc(IFT_ETHER); 382 if (ifp == NULL) { 383 printf("bfe%d: failed to if_alloc()\n", sc->bfe_unit); 384 error = ENOSPC; 385 goto fail; 386 } 387 ifp->if_softc = sc; 388 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 389 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 390 ifp->if_ioctl = bfe_ioctl; 391 ifp->if_start = bfe_start; 392 ifp->if_init = bfe_init; 393 ifp->if_mtu = ETHERMTU; 394 IFQ_SET_MAXLEN(&ifp->if_snd, BFE_TX_QLEN); 395 ifp->if_snd.ifq_drv_maxlen = BFE_TX_QLEN; 396 IFQ_SET_READY(&ifp->if_snd); 397 398 bfe_get_config(sc); 399 400 /* Reset the chip and turn on the PHY */ 401 BFE_LOCK(sc); 402 bfe_chip_reset(sc); 403 BFE_UNLOCK(sc); 404 405 if (mii_phy_probe(dev, &sc->bfe_miibus, 406 bfe_ifmedia_upd, bfe_ifmedia_sts)) { 407 printf("bfe%d: MII without any PHY!\n", sc->bfe_unit); 408 error = ENXIO; 409 goto fail; 410 } 411 412 ether_ifattach(ifp, sc->bfe_enaddr); 413 414 /* 415 * Tell the upper layer(s) we support long frames. 416 */ 417 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 418 ifp->if_capabilities |= IFCAP_VLAN_MTU; 419 ifp->if_capenable |= IFCAP_VLAN_MTU; 420 421 /* 422 * Hook interrupt last to avoid having to lock softc 423 */ 424 error = bus_setup_intr(dev, sc->bfe_irq, INTR_TYPE_NET | INTR_MPSAFE, 425 NULL, bfe_intr, sc, &sc->bfe_intrhand); 426 427 if (error) { 428 printf("bfe%d: couldn't set up irq\n", unit); 429 goto fail; 430 } 431fail: 432 if (error) 433 bfe_release_resources(sc); 434 return (error); 435} 436 437static int 438bfe_detach(device_t dev) 439{ 440 struct bfe_softc *sc; 441 struct ifnet *ifp; 442 443 sc = device_get_softc(dev); 444 445 KASSERT(mtx_initialized(&sc->bfe_mtx), ("bfe mutex not initialized")); 446 447 ifp = sc->bfe_ifp; 448 449 if (device_is_attached(dev)) { 450 BFE_LOCK(sc); 451 bfe_stop(sc); 452 BFE_UNLOCK(sc); 453 callout_drain(&sc->bfe_stat_co); 454 if (ifp != NULL) 455 ether_ifdetach(ifp); 456 } 457 458 bfe_chip_reset(sc); 459 460 bus_generic_detach(dev); 461 if(sc->bfe_miibus != NULL) 462 device_delete_child(dev, sc->bfe_miibus); 463 464 bfe_release_resources(sc); 465 mtx_destroy(&sc->bfe_mtx); 466 467 return (0); 468} 469 470/* 471 * Stop all chip I/O so that the kernel's probe routines don't 472 * get confused by errant DMAs when rebooting. 473 */ 474static int 475bfe_shutdown(device_t dev) 476{ 477 struct bfe_softc *sc; 478 479 sc = device_get_softc(dev); 480 BFE_LOCK(sc); 481 bfe_stop(sc); 482 483 BFE_UNLOCK(sc); 484 485 return (0); 486} 487 488static int 489bfe_suspend(device_t dev) 490{ 491 struct bfe_softc *sc; 492 493 sc = device_get_softc(dev); 494 BFE_LOCK(sc); 495 bfe_stop(sc); 496 BFE_UNLOCK(sc); 497 498 return (0); 499} 500 501static int 502bfe_resume(device_t dev) 503{ 504 struct bfe_softc *sc; 505 struct ifnet *ifp; 506 507 sc = device_get_softc(dev); 508 ifp = sc->bfe_ifp; 509 BFE_LOCK(sc); 510 bfe_chip_reset(sc); 511 if (ifp->if_flags & IFF_UP) { 512 bfe_init_locked(sc); 513 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 514 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 515 bfe_start_locked(ifp); 516 } 517 BFE_UNLOCK(sc); 518 519 return (0); 520} 521 522static int 523bfe_miibus_readreg(device_t dev, int phy, int reg) 524{ 525 struct bfe_softc *sc; 526 u_int32_t ret; 527 528 sc = device_get_softc(dev); 529 if(phy != sc->bfe_phyaddr) 530 return (0); 531 bfe_readphy(sc, reg, &ret); 532 533 return (ret); 534} 535 536static int 537bfe_miibus_writereg(device_t dev, int phy, int reg, int val) 538{ 539 struct bfe_softc *sc; 540 541 sc = device_get_softc(dev); 542 if(phy != sc->bfe_phyaddr) 543 return (0); 544 bfe_writephy(sc, reg, val); 545 546 return (0); 547} 548 549static void 550bfe_miibus_statchg(device_t dev) 551{ 552 struct bfe_softc *sc; 553 struct mii_data *mii; 554 u_int32_t val, flow; 555 556 sc = device_get_softc(dev); 557 mii = device_get_softc(sc->bfe_miibus); 558 559 if ((mii->mii_media_status & IFM_ACTIVE) != 0) { 560 if (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 561 sc->bfe_link = 1; 562 } else 563 sc->bfe_link = 0; 564 565 /* XXX Should stop Rx/Tx engine prior to touching MAC. */ 566 val = CSR_READ_4(sc, BFE_TX_CTRL); 567 val &= ~BFE_TX_DUPLEX; 568 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 569 val |= BFE_TX_DUPLEX; 570 flow = 0; 571#ifdef notyet 572 flow = CSR_READ_4(sc, BFE_RXCONF); 573 flow &= ~BFE_RXCONF_FLOW; 574 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & 575 IFM_ETH_RXPAUSE) != 0) 576 flow |= BFE_RXCONF_FLOW; 577 CSR_WRITE_4(sc, BFE_RXCONF, flow); 578 /* 579 * It seems that the hardware has Tx pause issues 580 * so enable only Rx pause. 581 */ 582 flow = CSR_READ_4(sc, BFE_MAC_FLOW); 583 flow &= ~BFE_FLOW_PAUSE_ENAB; 584 CSR_WRITE_4(sc, BFE_MAC_FLOW, flow); 585#endif 586 } 587 CSR_WRITE_4(sc, BFE_TX_CTRL, val); 588} 589 590static void 591bfe_tx_ring_free(struct bfe_softc *sc) 592{ 593 int i; 594 595 for(i = 0; i < BFE_TX_LIST_CNT; i++) { 596 if(sc->bfe_tx_ring[i].bfe_mbuf != NULL) { 597 m_freem(sc->bfe_tx_ring[i].bfe_mbuf); 598 sc->bfe_tx_ring[i].bfe_mbuf = NULL; 599 bus_dmamap_unload(sc->bfe_tag, 600 sc->bfe_tx_ring[i].bfe_map); 601 } 602 } 603 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 604 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREWRITE); 605} 606 607static void 608bfe_rx_ring_free(struct bfe_softc *sc) 609{ 610 int i; 611 612 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 613 if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) { 614 m_freem(sc->bfe_rx_ring[i].bfe_mbuf); 615 sc->bfe_rx_ring[i].bfe_mbuf = NULL; 616 bus_dmamap_unload(sc->bfe_tag, 617 sc->bfe_rx_ring[i].bfe_map); 618 } 619 } 620 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 621 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE); 622} 623 624static int 625bfe_list_rx_init(struct bfe_softc *sc) 626{ 627 int i; 628 629 for(i = 0; i < BFE_RX_LIST_CNT; i++) { 630 if(bfe_list_newbuf(sc, i, NULL) == ENOBUFS) 631 return (ENOBUFS); 632 } 633 634 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE); 635 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc))); 636 637 sc->bfe_rx_cons = 0; 638 639 return (0); 640} 641 642static int 643bfe_list_newbuf(struct bfe_softc *sc, int c, struct mbuf *m) 644{ 645 struct bfe_rxheader *rx_header; 646 struct bfe_desc *d; 647 struct bfe_data *r; 648 u_int32_t ctrl; 649 int allocated, error; 650 651 if ((c < 0) || (c >= BFE_RX_LIST_CNT)) 652 return (EINVAL); 653 654 allocated = 0; 655 if(m == NULL) { 656 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 657 if(m == NULL) 658 return (ENOBUFS); 659 m->m_len = m->m_pkthdr.len = MCLBYTES; 660 allocated++; 661 } 662 else 663 m->m_data = m->m_ext.ext_buf; 664 665 rx_header = mtod(m, struct bfe_rxheader *); 666 rx_header->len = 0; 667 rx_header->flags = 0; 668 669 /* Map the mbuf into DMA */ 670 sc->bfe_rx_cnt = c; 671 d = &sc->bfe_rx_list[c]; 672 r = &sc->bfe_rx_ring[c]; 673 error = bus_dmamap_load(sc->bfe_tag, r->bfe_map, mtod(m, void *), 674 MCLBYTES, bfe_dma_map_desc, d, BUS_DMA_NOWAIT); 675 if (error != 0) { 676 if (allocated != 0) 677 m_free(m); 678 if (error != ENOMEM) 679 printf("bfe%d: failed to map RX buffer, error %d\n", 680 sc->bfe_unit, error); 681 return (ENOBUFS); 682 } 683 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_PREWRITE); 684 685 ctrl = ETHER_MAX_LEN + 32; 686 687 if(c == BFE_RX_LIST_CNT - 1) 688 ctrl |= BFE_DESC_EOT; 689 690 d->bfe_ctrl = ctrl; 691 r->bfe_mbuf = m; 692 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE); 693 return (0); 694} 695 696static void 697bfe_get_config(struct bfe_softc *sc) 698{ 699 u_int8_t eeprom[128]; 700 701 bfe_read_eeprom(sc, eeprom); 702 703 sc->bfe_enaddr[0] = eeprom[79]; 704 sc->bfe_enaddr[1] = eeprom[78]; 705 sc->bfe_enaddr[2] = eeprom[81]; 706 sc->bfe_enaddr[3] = eeprom[80]; 707 sc->bfe_enaddr[4] = eeprom[83]; 708 sc->bfe_enaddr[5] = eeprom[82]; 709 710 sc->bfe_phyaddr = eeprom[90] & 0x1f; 711 sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1; 712 713 sc->bfe_core_unit = 0; 714 sc->bfe_dma_offset = BFE_PCI_DMA; 715} 716 717static void 718bfe_pci_setup(struct bfe_softc *sc, u_int32_t cores) 719{ 720 u_int32_t bar_orig, pci_rev, val; 721 722 bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4); 723 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4); 724 pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK; 725 726 val = CSR_READ_4(sc, BFE_SBINTVEC); 727 val |= cores; 728 CSR_WRITE_4(sc, BFE_SBINTVEC, val); 729 730 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2); 731 val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST; 732 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val); 733 734 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4); 735} 736 737static void 738bfe_clear_stats(struct bfe_softc *sc) 739{ 740 u_long reg; 741 742 BFE_LOCK_ASSERT(sc); 743 744 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ); 745 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) 746 CSR_READ_4(sc, reg); 747 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) 748 CSR_READ_4(sc, reg); 749} 750 751static int 752bfe_resetphy(struct bfe_softc *sc) 753{ 754 u_int32_t val; 755 756 bfe_writephy(sc, 0, BMCR_RESET); 757 DELAY(100); 758 bfe_readphy(sc, 0, &val); 759 if (val & BMCR_RESET) { 760 printf("bfe%d: PHY Reset would not complete.\n", sc->bfe_unit); 761 return (ENXIO); 762 } 763 return (0); 764} 765 766static void 767bfe_chip_halt(struct bfe_softc *sc) 768{ 769 BFE_LOCK_ASSERT(sc); 770 /* disable interrupts - not that it actually does..*/ 771 CSR_WRITE_4(sc, BFE_IMASK, 0); 772 CSR_READ_4(sc, BFE_IMASK); 773 774 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 775 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1); 776 777 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 778 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 779 DELAY(10); 780} 781 782static void 783bfe_chip_reset(struct bfe_softc *sc) 784{ 785 u_int32_t val; 786 787 BFE_LOCK_ASSERT(sc); 788 789 /* Set the interrupt vector for the enet core */ 790 bfe_pci_setup(sc, BFE_INTVEC_ENET0); 791 792 /* is core up? */ 793 val = CSR_READ_4(sc, BFE_SBTMSLOW) & 794 (BFE_RESET | BFE_REJECT | BFE_CLOCK); 795 if (val == BFE_CLOCK) { 796 /* It is, so shut it down */ 797 CSR_WRITE_4(sc, BFE_RCV_LAZY, 0); 798 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 799 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1); 800 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 801 sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0; 802 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK) 803 bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE, 804 100, 0); 805 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 806 sc->bfe_rx_prod = sc->bfe_rx_cons = 0; 807 } 808 809 bfe_core_reset(sc); 810 bfe_clear_stats(sc); 811 812 /* 813 * We want the phy registers to be accessible even when 814 * the driver is "downed" so initialize MDC preamble, frequency, 815 * and whether internal or external phy here. 816 */ 817 818 /* 4402 has 62.5Mhz SB clock and internal phy */ 819 CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d); 820 821 /* Internal or external PHY? */ 822 val = CSR_READ_4(sc, BFE_DEVCTRL); 823 if(!(val & BFE_IPP)) 824 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL); 825 else if(CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) { 826 BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR); 827 DELAY(100); 828 } 829 830 /* Enable CRC32 generation and set proper LED modes */ 831 BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB | BFE_CTRL_LED); 832 833 /* Reset or clear powerdown control bit */ 834 BFE_AND(sc, BFE_MAC_CTRL, ~BFE_CTRL_PDOWN); 835 836 CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) & 837 BFE_LAZY_FC_MASK)); 838 839 /* 840 * We don't want lazy interrupts, so just send them at 841 * the end of a frame, please 842 */ 843 BFE_OR(sc, BFE_RCV_LAZY, 0); 844 845 /* Set max lengths, accounting for VLAN tags */ 846 CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32); 847 CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32); 848 849 /* Set watermark XXX - magic */ 850 CSR_WRITE_4(sc, BFE_TX_WMARK, 56); 851 852 /* 853 * Initialise DMA channels 854 * - not forgetting dma addresses need to be added to BFE_PCI_DMA 855 */ 856 CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE); 857 CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA); 858 859 CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) | 860 BFE_RX_CTRL_ENABLE); 861 CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA); 862 863 bfe_resetphy(sc); 864 bfe_setupphy(sc); 865} 866 867static void 868bfe_core_disable(struct bfe_softc *sc) 869{ 870 if((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET) 871 return; 872 873 /* 874 * Set reject, wait for it set, then wait for the core to stop 875 * being busy, then set reset and reject and enable the clocks. 876 */ 877 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK)); 878 bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0); 879 bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1); 880 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT | 881 BFE_RESET)); 882 CSR_READ_4(sc, BFE_SBTMSLOW); 883 DELAY(10); 884 /* Leave reset and reject set */ 885 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET)); 886 DELAY(10); 887} 888 889static void 890bfe_core_reset(struct bfe_softc *sc) 891{ 892 u_int32_t val; 893 894 /* Disable the core */ 895 bfe_core_disable(sc); 896 897 /* and bring it back up */ 898 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC)); 899 CSR_READ_4(sc, BFE_SBTMSLOW); 900 DELAY(10); 901 902 /* Chip bug, clear SERR, IB and TO if they are set. */ 903 if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR) 904 CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0); 905 val = CSR_READ_4(sc, BFE_SBIMSTATE); 906 if (val & (BFE_IBE | BFE_TO)) 907 CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO)); 908 909 /* Clear reset and allow it to move through the core */ 910 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC)); 911 CSR_READ_4(sc, BFE_SBTMSLOW); 912 DELAY(10); 913 914 /* Leave the clock set */ 915 CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK); 916 CSR_READ_4(sc, BFE_SBTMSLOW); 917 DELAY(10); 918} 919 920static void 921bfe_cam_write(struct bfe_softc *sc, u_char *data, int index) 922{ 923 u_int32_t val; 924 925 val = ((u_int32_t) data[2]) << 24; 926 val |= ((u_int32_t) data[3]) << 16; 927 val |= ((u_int32_t) data[4]) << 8; 928 val |= ((u_int32_t) data[5]); 929 CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val); 930 val = (BFE_CAM_HI_VALID | 931 (((u_int32_t) data[0]) << 8) | 932 (((u_int32_t) data[1]))); 933 CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val); 934 CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE | 935 ((u_int32_t) index << BFE_CAM_INDEX_SHIFT))); 936 bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1); 937} 938 939static void 940bfe_set_rx_mode(struct bfe_softc *sc) 941{ 942 struct ifnet *ifp = sc->bfe_ifp; 943 struct ifmultiaddr *ifma; 944 u_int32_t val; 945 int i = 0; 946 947 val = CSR_READ_4(sc, BFE_RXCONF); 948 949 if (ifp->if_flags & IFF_PROMISC) 950 val |= BFE_RXCONF_PROMISC; 951 else 952 val &= ~BFE_RXCONF_PROMISC; 953 954 if (ifp->if_flags & IFF_BROADCAST) 955 val &= ~BFE_RXCONF_DBCAST; 956 else 957 val |= BFE_RXCONF_DBCAST; 958 959 960 CSR_WRITE_4(sc, BFE_CAM_CTRL, 0); 961 bfe_cam_write(sc, IF_LLADDR(sc->bfe_ifp), i++); 962 963 if (ifp->if_flags & IFF_ALLMULTI) 964 val |= BFE_RXCONF_ALLMULTI; 965 else { 966 val &= ~BFE_RXCONF_ALLMULTI; 967 IF_ADDR_LOCK(ifp); 968 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 969 if (ifma->ifma_addr->sa_family != AF_LINK) 970 continue; 971 bfe_cam_write(sc, 972 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i++); 973 } 974 IF_ADDR_UNLOCK(ifp); 975 } 976 977 CSR_WRITE_4(sc, BFE_RXCONF, val); 978 BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE); 979} 980 981static void 982bfe_dma_map(void *arg, bus_dma_segment_t *segs, int nseg, int error) 983{ 984 u_int32_t *ptr; 985 986 ptr = arg; 987 *ptr = segs->ds_addr; 988} 989 990static void 991bfe_dma_map_desc(void *arg, bus_dma_segment_t *segs, int nseg, int error) 992{ 993 struct bfe_desc *d; 994 995 d = arg; 996 /* The chip needs all addresses to be added to BFE_PCI_DMA */ 997 d->bfe_addr = segs->ds_addr + BFE_PCI_DMA; 998} 999 1000static void 1001bfe_release_resources(struct bfe_softc *sc) 1002{ 1003 device_t dev; 1004 int i; 1005 1006 dev = sc->bfe_dev; 1007 1008 if (sc->bfe_vpd_prodname != NULL) 1009 free(sc->bfe_vpd_prodname, M_DEVBUF); 1010 1011 if (sc->bfe_vpd_readonly != NULL) 1012 free(sc->bfe_vpd_readonly, M_DEVBUF); 1013 1014 if (sc->bfe_intrhand != NULL) 1015 bus_teardown_intr(dev, sc->bfe_irq, sc->bfe_intrhand); 1016 1017 if (sc->bfe_irq != NULL) 1018 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bfe_irq); 1019 1020 if (sc->bfe_res != NULL) 1021 bus_release_resource(dev, SYS_RES_MEMORY, 0x10, sc->bfe_res); 1022 1023 if (sc->bfe_ifp != NULL) 1024 if_free(sc->bfe_ifp); 1025 1026 if(sc->bfe_tx_tag != NULL) { 1027 bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map); 1028 bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list, 1029 sc->bfe_tx_map); 1030 bus_dma_tag_destroy(sc->bfe_tx_tag); 1031 sc->bfe_tx_tag = NULL; 1032 } 1033 1034 if(sc->bfe_rx_tag != NULL) { 1035 bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map); 1036 bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list, 1037 sc->bfe_rx_map); 1038 bus_dma_tag_destroy(sc->bfe_rx_tag); 1039 sc->bfe_rx_tag = NULL; 1040 } 1041 1042 if(sc->bfe_tag != NULL) { 1043 for(i = 0; i < BFE_TX_LIST_CNT; i++) { 1044 bus_dmamap_destroy(sc->bfe_tag, 1045 sc->bfe_tx_ring[i].bfe_map); 1046 } 1047 for(i = 0; i < BFE_RX_LIST_CNT; i++) { 1048 bus_dmamap_destroy(sc->bfe_tag, 1049 sc->bfe_rx_ring[i].bfe_map); 1050 } 1051 bus_dma_tag_destroy(sc->bfe_tag); 1052 sc->bfe_tag = NULL; 1053 } 1054 1055 if(sc->bfe_parent_tag != NULL) 1056 bus_dma_tag_destroy(sc->bfe_parent_tag); 1057 1058 return; 1059} 1060 1061static void 1062bfe_read_eeprom(struct bfe_softc *sc, u_int8_t *data) 1063{ 1064 long i; 1065 u_int16_t *ptr = (u_int16_t *)data; 1066 1067 for(i = 0; i < 128; i += 2) 1068 ptr[i/2] = CSR_READ_4(sc, 4096 + i); 1069} 1070 1071static int 1072bfe_wait_bit(struct bfe_softc *sc, u_int32_t reg, u_int32_t bit, 1073 u_long timeout, const int clear) 1074{ 1075 u_long i; 1076 1077 for (i = 0; i < timeout; i++) { 1078 u_int32_t val = CSR_READ_4(sc, reg); 1079 1080 if (clear && !(val & bit)) 1081 break; 1082 if (!clear && (val & bit)) 1083 break; 1084 DELAY(10); 1085 } 1086 if (i == timeout) { 1087 printf("bfe%d: BUG! Timeout waiting for bit %08x of register " 1088 "%x to %s.\n", sc->bfe_unit, bit, reg, 1089 (clear ? "clear" : "set")); 1090 return (-1); 1091 } 1092 return (0); 1093} 1094 1095static int 1096bfe_readphy(struct bfe_softc *sc, u_int32_t reg, u_int32_t *val) 1097{ 1098 int err; 1099 1100 /* Clear MII ISR */ 1101 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1102 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1103 (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) | 1104 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1105 (reg << BFE_MDIO_RA_SHIFT) | 1106 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT))); 1107 err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1108 *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA; 1109 1110 return (err); 1111} 1112 1113static int 1114bfe_writephy(struct bfe_softc *sc, u_int32_t reg, u_int32_t val) 1115{ 1116 int status; 1117 1118 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1119 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1120 (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) | 1121 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1122 (reg << BFE_MDIO_RA_SHIFT) | 1123 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) | 1124 (val & BFE_MDIO_DATA_DATA))); 1125 status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1126 1127 return (status); 1128} 1129 1130/* 1131 * XXX - I think this is handled by the PHY driver, but it can't hurt to do it 1132 * twice 1133 */ 1134static int 1135bfe_setupphy(struct bfe_softc *sc) 1136{ 1137 u_int32_t val; 1138 1139 /* Enable activity LED */ 1140 bfe_readphy(sc, 26, &val); 1141 bfe_writephy(sc, 26, val & 0x7fff); 1142 bfe_readphy(sc, 26, &val); 1143 1144 /* Enable traffic meter LED mode */ 1145 bfe_readphy(sc, 27, &val); 1146 bfe_writephy(sc, 27, val | (1 << 6)); 1147 1148 return (0); 1149} 1150 1151static void 1152bfe_stats_update(struct bfe_softc *sc) 1153{ 1154 u_long reg; 1155 u_int32_t *val; 1156 1157 val = &sc->bfe_hwstats.tx_good_octets; 1158 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) { 1159 *val++ += CSR_READ_4(sc, reg); 1160 } 1161 val = &sc->bfe_hwstats.rx_good_octets; 1162 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) { 1163 *val++ += CSR_READ_4(sc, reg); 1164 } 1165} 1166 1167static void 1168bfe_txeof(struct bfe_softc *sc) 1169{ 1170 struct ifnet *ifp; 1171 int i, chipidx; 1172 1173 BFE_LOCK_ASSERT(sc); 1174 1175 ifp = sc->bfe_ifp; 1176 1177 chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK; 1178 chipidx /= sizeof(struct bfe_desc); 1179 1180 i = sc->bfe_tx_cons; 1181 /* Go through the mbufs and free those that have been transmitted */ 1182 while(i != chipidx) { 1183 struct bfe_data *r = &sc->bfe_tx_ring[i]; 1184 if(r->bfe_mbuf != NULL) { 1185 ifp->if_opackets++; 1186 m_freem(r->bfe_mbuf); 1187 r->bfe_mbuf = NULL; 1188 } 1189 bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1190 sc->bfe_tx_cnt--; 1191 BFE_INC(i, BFE_TX_LIST_CNT); 1192 } 1193 1194 if(i != sc->bfe_tx_cons) { 1195 /* we freed up some mbufs */ 1196 sc->bfe_tx_cons = i; 1197 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1198 } 1199 1200 if (sc->bfe_tx_cnt == 0) 1201 sc->bfe_watchdog_timer = 0; 1202} 1203 1204/* Pass a received packet up the stack */ 1205static void 1206bfe_rxeof(struct bfe_softc *sc) 1207{ 1208 struct mbuf *m; 1209 struct ifnet *ifp; 1210 struct bfe_rxheader *rxheader; 1211 struct bfe_data *r; 1212 int cons; 1213 u_int32_t status, current, len, flags; 1214 1215 BFE_LOCK_ASSERT(sc); 1216 cons = sc->bfe_rx_cons; 1217 status = CSR_READ_4(sc, BFE_DMARX_STAT); 1218 current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc); 1219 1220 ifp = sc->bfe_ifp; 1221 1222 while(current != cons) { 1223 r = &sc->bfe_rx_ring[cons]; 1224 m = r->bfe_mbuf; 1225 rxheader = mtod(m, struct bfe_rxheader*); 1226 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_POSTREAD); 1227 len = rxheader->len; 1228 r->bfe_mbuf = NULL; 1229 1230 bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1231 flags = rxheader->flags; 1232 1233 len -= ETHER_CRC_LEN; 1234 1235 /* flag an error and try again */ 1236 if ((len > ETHER_MAX_LEN+32) || (flags & BFE_RX_FLAG_ERRORS)) { 1237 ifp->if_ierrors++; 1238 if (flags & BFE_RX_FLAG_SERR) 1239 ifp->if_collisions++; 1240 bfe_list_newbuf(sc, cons, m); 1241 BFE_INC(cons, BFE_RX_LIST_CNT); 1242 continue; 1243 } 1244 1245 /* Go past the rx header */ 1246 if (bfe_list_newbuf(sc, cons, NULL) == 0) { 1247 m_adj(m, BFE_RX_OFFSET); 1248 m->m_len = m->m_pkthdr.len = len; 1249 } else { 1250 bfe_list_newbuf(sc, cons, m); 1251 ifp->if_ierrors++; 1252 BFE_INC(cons, BFE_RX_LIST_CNT); 1253 continue; 1254 } 1255 1256 ifp->if_ipackets++; 1257 m->m_pkthdr.rcvif = ifp; 1258 BFE_UNLOCK(sc); 1259 (*ifp->if_input)(ifp, m); 1260 BFE_LOCK(sc); 1261 1262 BFE_INC(cons, BFE_RX_LIST_CNT); 1263 } 1264 sc->bfe_rx_cons = cons; 1265} 1266 1267static void 1268bfe_intr(void *xsc) 1269{ 1270 struct bfe_softc *sc = xsc; 1271 struct ifnet *ifp; 1272 u_int32_t istat, imask, flag; 1273 1274 ifp = sc->bfe_ifp; 1275 1276 BFE_LOCK(sc); 1277 1278 istat = CSR_READ_4(sc, BFE_ISTAT); 1279 imask = CSR_READ_4(sc, BFE_IMASK); 1280 1281 /* 1282 * Defer unsolicited interrupts - This is necessary because setting the 1283 * chips interrupt mask register to 0 doesn't actually stop the 1284 * interrupts 1285 */ 1286 istat &= imask; 1287 CSR_WRITE_4(sc, BFE_ISTAT, istat); 1288 CSR_READ_4(sc, BFE_ISTAT); 1289 1290 /* not expecting this interrupt, disregard it */ 1291 if(istat == 0) { 1292 BFE_UNLOCK(sc); 1293 return; 1294 } 1295 1296 if(istat & BFE_ISTAT_ERRORS) { 1297 1298 if (istat & BFE_ISTAT_DSCE) { 1299 printf("if_bfe Descriptor Error\n"); 1300 bfe_stop(sc); 1301 BFE_UNLOCK(sc); 1302 return; 1303 } 1304 1305 if (istat & BFE_ISTAT_DPE) { 1306 printf("if_bfe Descriptor Protocol Error\n"); 1307 bfe_stop(sc); 1308 BFE_UNLOCK(sc); 1309 return; 1310 } 1311 1312 flag = CSR_READ_4(sc, BFE_DMATX_STAT); 1313 if(flag & BFE_STAT_EMASK) 1314 ifp->if_oerrors++; 1315 1316 flag = CSR_READ_4(sc, BFE_DMARX_STAT); 1317 if(flag & BFE_RX_FLAG_ERRORS) 1318 ifp->if_ierrors++; 1319 1320 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1321 bfe_init_locked(sc); 1322 } 1323 1324 /* A packet was received */ 1325 if(istat & BFE_ISTAT_RX) 1326 bfe_rxeof(sc); 1327 1328 /* A packet was sent */ 1329 if(istat & BFE_ISTAT_TX) 1330 bfe_txeof(sc); 1331 1332 /* We have packets pending, fire them out */ 1333 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1334 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1335 bfe_start_locked(ifp); 1336 1337 BFE_UNLOCK(sc); 1338} 1339 1340static int 1341bfe_encap(struct bfe_softc *sc, struct mbuf **m_head, u_int32_t *txidx) 1342{ 1343 struct bfe_desc *d = NULL; 1344 struct bfe_data *r = NULL; 1345 struct mbuf *m; 1346 u_int32_t frag, cur, cnt = 0; 1347 int chainlen = 0; 1348 int error; 1349 1350 if(BFE_TX_LIST_CNT - sc->bfe_tx_cnt < 2) 1351 return (ENOBUFS); 1352 1353 /* 1354 * Count the number of frags in this chain to see if 1355 * we need to m_defrag. Since the descriptor list is shared 1356 * by all packets, we'll m_defrag long chains so that they 1357 * do not use up the entire list, even if they would fit. 1358 */ 1359 for(m = *m_head; m != NULL; m = m->m_next) 1360 chainlen++; 1361 1362 1363 if ((chainlen > BFE_TX_LIST_CNT / 4) || 1364 ((BFE_TX_LIST_CNT - (chainlen + sc->bfe_tx_cnt)) < 2)) { 1365 m = m_defrag(*m_head, M_DONTWAIT); 1366 if (m == NULL) 1367 return (ENOBUFS); 1368 *m_head = m; 1369 } 1370 1371 /* 1372 * Start packing the mbufs in this chain into 1373 * the fragment pointers. Stop when we run out 1374 * of fragments or hit the end of the mbuf chain. 1375 */ 1376 cur = frag = *txidx; 1377 cnt = 0; 1378 1379 for(m = *m_head; m != NULL; m = m->m_next) { 1380 if(m->m_len != 0) { 1381 if((BFE_TX_LIST_CNT - (sc->bfe_tx_cnt + cnt)) < 2) 1382 return (ENOBUFS); 1383 1384 d = &sc->bfe_tx_list[cur]; 1385 r = &sc->bfe_tx_ring[cur]; 1386 d->bfe_ctrl = BFE_DESC_LEN & m->m_len; 1387 /* always intterupt on completion */ 1388 d->bfe_ctrl |= BFE_DESC_IOC; 1389 if(cnt == 0) 1390 /* Set start of frame */ 1391 d->bfe_ctrl |= BFE_DESC_SOF; 1392 if(cur == BFE_TX_LIST_CNT - 1) 1393 /* 1394 * Tell the chip to wrap to the start of 1395 * the descriptor list 1396 */ 1397 d->bfe_ctrl |= BFE_DESC_EOT; 1398 1399 error = bus_dmamap_load(sc->bfe_tag, 1400 r->bfe_map, mtod(m, void*), m->m_len, 1401 bfe_dma_map_desc, d, BUS_DMA_NOWAIT); 1402 if (error) 1403 return (ENOBUFS); 1404 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, 1405 BUS_DMASYNC_PREWRITE); 1406 1407 frag = cur; 1408 BFE_INC(cur, BFE_TX_LIST_CNT); 1409 cnt++; 1410 } 1411 } 1412 1413 if (m != NULL) 1414 return (ENOBUFS); 1415 1416 sc->bfe_tx_list[frag].bfe_ctrl |= BFE_DESC_EOF; 1417 sc->bfe_tx_ring[frag].bfe_mbuf = *m_head; 1418 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREWRITE); 1419 1420 *txidx = cur; 1421 sc->bfe_tx_cnt += cnt; 1422 return (0); 1423} 1424 1425/* 1426 * Set up to transmit a packet. 1427 */ 1428static void 1429bfe_start(struct ifnet *ifp) 1430{ 1431 BFE_LOCK((struct bfe_softc *)ifp->if_softc); 1432 bfe_start_locked(ifp); 1433 BFE_UNLOCK((struct bfe_softc *)ifp->if_softc); 1434} 1435 1436/* 1437 * Set up to transmit a packet. The softc is already locked. 1438 */ 1439static void 1440bfe_start_locked(struct ifnet *ifp) 1441{ 1442 struct bfe_softc *sc; 1443 struct mbuf *m_head = NULL; 1444 int idx, queued = 0; 1445 1446 sc = ifp->if_softc; 1447 idx = sc->bfe_tx_prod; 1448 1449 BFE_LOCK_ASSERT(sc); 1450 1451 /* 1452 * Not much point trying to send if the link is down 1453 * or we have nothing to send. 1454 */ 1455 if (!sc->bfe_link && ifp->if_snd.ifq_len < 10) 1456 return; 1457 1458 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1459 IFF_DRV_RUNNING) 1460 return; 1461 1462 while(sc->bfe_tx_ring[idx].bfe_mbuf == NULL) { 1463 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1464 if(m_head == NULL) 1465 break; 1466 1467 /* 1468 * Pack the data into the tx ring. If we dont have 1469 * enough room, let the chip drain the ring. 1470 */ 1471 if(bfe_encap(sc, &m_head, &idx)) { 1472 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1473 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1474 break; 1475 } 1476 1477 queued++; 1478 1479 /* 1480 * If there's a BPF listener, bounce a copy of this frame 1481 * to him. 1482 */ 1483 BPF_MTAP(ifp, m_head); 1484 } 1485 1486 if (queued) { 1487 sc->bfe_tx_prod = idx; 1488 /* Transmit - twice due to apparent hardware bug */ 1489 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1490 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1491 1492 /* 1493 * Set a timeout in case the chip goes out to lunch. 1494 */ 1495 sc->bfe_watchdog_timer = 5; 1496 } 1497} 1498 1499static void 1500bfe_init(void *xsc) 1501{ 1502 BFE_LOCK((struct bfe_softc *)xsc); 1503 bfe_init_locked(xsc); 1504 BFE_UNLOCK((struct bfe_softc *)xsc); 1505} 1506 1507static void 1508bfe_init_locked(void *xsc) 1509{ 1510 struct bfe_softc *sc = (struct bfe_softc*)xsc; 1511 struct ifnet *ifp = sc->bfe_ifp; 1512 struct mii_data *mii; 1513 1514 BFE_LOCK_ASSERT(sc); 1515 1516 mii = device_get_softc(sc->bfe_miibus); 1517 1518 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1519 return; 1520 1521 bfe_stop(sc); 1522 bfe_chip_reset(sc); 1523 1524 if (bfe_list_rx_init(sc) == ENOBUFS) { 1525 printf("bfe%d: bfe_init: Not enough memory for list buffers\n", 1526 sc->bfe_unit); 1527 bfe_stop(sc); 1528 return; 1529 } 1530 1531 bfe_set_rx_mode(sc); 1532 1533 /* Enable the chip and core */ 1534 BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE); 1535 /* Enable interrupts */ 1536 CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF); 1537 1538 /* Clear link state and change media. */ 1539 sc->bfe_link = 0; 1540 mii_mediachg(mii); 1541 1542 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1543 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1544 1545 callout_reset(&sc->bfe_stat_co, hz, bfe_tick, sc); 1546} 1547 1548/* 1549 * Set media options. 1550 */ 1551static int 1552bfe_ifmedia_upd(struct ifnet *ifp) 1553{ 1554 struct bfe_softc *sc; 1555 struct mii_data *mii; 1556 int error; 1557 1558 sc = ifp->if_softc; 1559 BFE_LOCK(sc); 1560 1561 mii = device_get_softc(sc->bfe_miibus); 1562 if (mii->mii_instance) { 1563 struct mii_softc *miisc; 1564 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1565 miisc = LIST_NEXT(miisc, mii_list)) 1566 mii_phy_reset(miisc); 1567 } 1568 error = mii_mediachg(mii); 1569 BFE_UNLOCK(sc); 1570 1571 return (error); 1572} 1573 1574/* 1575 * Report current media status. 1576 */ 1577static void 1578bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1579{ 1580 struct bfe_softc *sc = ifp->if_softc; 1581 struct mii_data *mii; 1582 1583 BFE_LOCK(sc); 1584 mii = device_get_softc(sc->bfe_miibus); 1585 mii_pollstat(mii); 1586 ifmr->ifm_active = mii->mii_media_active; 1587 ifmr->ifm_status = mii->mii_media_status; 1588 BFE_UNLOCK(sc); 1589} 1590 1591static int 1592bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1593{ 1594 struct bfe_softc *sc = ifp->if_softc; 1595 struct ifreq *ifr = (struct ifreq *) data; 1596 struct mii_data *mii; 1597 int error = 0; 1598 1599 switch(command) { 1600 case SIOCSIFFLAGS: 1601 BFE_LOCK(sc); 1602 if(ifp->if_flags & IFF_UP) 1603 if(ifp->if_drv_flags & IFF_DRV_RUNNING) 1604 bfe_set_rx_mode(sc); 1605 else 1606 bfe_init_locked(sc); 1607 else if(ifp->if_drv_flags & IFF_DRV_RUNNING) 1608 bfe_stop(sc); 1609 BFE_UNLOCK(sc); 1610 break; 1611 case SIOCADDMULTI: 1612 case SIOCDELMULTI: 1613 BFE_LOCK(sc); 1614 if(ifp->if_drv_flags & IFF_DRV_RUNNING) 1615 bfe_set_rx_mode(sc); 1616 BFE_UNLOCK(sc); 1617 break; 1618 case SIOCGIFMEDIA: 1619 case SIOCSIFMEDIA: 1620 mii = device_get_softc(sc->bfe_miibus); 1621 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 1622 command); 1623 break; 1624 default: 1625 error = ether_ioctl(ifp, command, data); 1626 break; 1627 } 1628 1629 return (error); 1630} 1631 1632static void 1633bfe_watchdog(struct bfe_softc *sc) 1634{ 1635 struct ifnet *ifp; 1636 1637 BFE_LOCK_ASSERT(sc); 1638 1639 if (sc->bfe_watchdog_timer == 0 || --sc->bfe_watchdog_timer) 1640 return; 1641 1642 ifp = sc->bfe_ifp; 1643 1644 printf("bfe%d: watchdog timeout -- resetting\n", sc->bfe_unit); 1645 1646 ifp->if_oerrors++; 1647 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1648 bfe_init_locked(sc); 1649 1650 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1651 bfe_start_locked(ifp); 1652} 1653 1654static void 1655bfe_tick(void *xsc) 1656{ 1657 struct bfe_softc *sc = xsc; 1658 struct mii_data *mii; 1659 1660 BFE_LOCK_ASSERT(sc); 1661 1662 mii = device_get_softc(sc->bfe_miibus); 1663 mii_tick(mii); 1664 bfe_stats_update(sc); 1665 bfe_watchdog(sc); 1666 callout_reset(&sc->bfe_stat_co, hz, bfe_tick, sc); 1667} 1668 1669/* 1670 * Stop the adapter and free any mbufs allocated to the 1671 * RX and TX lists. 1672 */ 1673static void 1674bfe_stop(struct bfe_softc *sc) 1675{ 1676 struct ifnet *ifp; 1677 1678 BFE_LOCK_ASSERT(sc); 1679 1680 ifp = sc->bfe_ifp; 1681 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1682 sc->bfe_link = 0; 1683 callout_stop(&sc->bfe_stat_co); 1684 sc->bfe_watchdog_timer = 0; 1685 1686 bfe_chip_halt(sc); 1687 bfe_tx_ring_free(sc); 1688 bfe_rx_ring_free(sc); 1689} 1690