if_bfe.c revision 243857
1139749Simp/*- 2119917Swpaul * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk> 3119917Swpaul * and Duncan Barclay<dmlb@dmlb.org> 4139749Simp * 5119917Swpaul * Redistribution and use in source and binary forms, with or without 6119917Swpaul * modification, are permitted provided that the following conditions 7119917Swpaul * are met: 8119917Swpaul * 1. Redistributions of source code must retain the above copyright 9119917Swpaul * notice, this list of conditions and the following disclaimer. 10119917Swpaul * 2. Redistributions in binary form must reproduce the above copyright 11119917Swpaul * notice, this list of conditions and the following disclaimer in the 12119917Swpaul * documentation and/or other materials provided with the distribution. 13119917Swpaul * 14119917Swpaul * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND 15119917Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16119917Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17119917Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18119917Swpaul * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19119917Swpaul * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20119917Swpaul * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21119917Swpaul * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22119917Swpaul * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23119917Swpaul * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24119917Swpaul * SUCH DAMAGE. 25119917Swpaul */ 26119917Swpaul 27119917Swpaul 28119917Swpaul#include <sys/cdefs.h> 29119917Swpaul__FBSDID("$FreeBSD: head/sys/dev/bfe/if_bfe.c 243857 2012-12-04 09:32:43Z glebius $"); 30119917Swpaul 31119917Swpaul#include <sys/param.h> 32119917Swpaul#include <sys/systm.h> 33181953Syongari#include <sys/bus.h> 34181953Syongari#include <sys/endian.h> 35181953Syongari#include <sys/kernel.h> 36181953Syongari#include <sys/malloc.h> 37119917Swpaul#include <sys/mbuf.h> 38129879Sphk#include <sys/module.h> 39181953Syongari#include <sys/rman.h> 40119917Swpaul#include <sys/socket.h> 41181953Syongari#include <sys/sockio.h> 42181994Syongari#include <sys/sysctl.h> 43119917Swpaul 44181953Syongari#include <net/bpf.h> 45119917Swpaul#include <net/if.h> 46119917Swpaul#include <net/ethernet.h> 47119917Swpaul#include <net/if_dl.h> 48119917Swpaul#include <net/if_media.h> 49119917Swpaul#include <net/if_types.h> 50119917Swpaul#include <net/if_vlan_var.h> 51119917Swpaul 52119917Swpaul#include <dev/mii/mii.h> 53119917Swpaul#include <dev/mii/miivar.h> 54119917Swpaul 55119917Swpaul#include <dev/pci/pcireg.h> 56119917Swpaul#include <dev/pci/pcivar.h> 57119917Swpaul 58181953Syongari#include <machine/bus.h> 59181953Syongari 60119917Swpaul#include <dev/bfe/if_bfereg.h> 61119917Swpaul 62119917SwpaulMODULE_DEPEND(bfe, pci, 1, 1, 1); 63119917SwpaulMODULE_DEPEND(bfe, ether, 1, 1, 1); 64119917SwpaulMODULE_DEPEND(bfe, miibus, 1, 1, 1); 65119917Swpaul 66151545Simp/* "device miibus" required. See GENERIC if you get errors here. */ 67119917Swpaul#include "miibus_if.h" 68119917Swpaul 69119917Swpaul#define BFE_DEVDESC_MAX 64 /* Maximum device description length */ 70119917Swpaul 71119917Swpaulstatic struct bfe_type bfe_devs[] = { 72119917Swpaul { BCOM_VENDORID, BCOM_DEVICEID_BCM4401, 73119917Swpaul "Broadcom BCM4401 Fast Ethernet" }, 74134590Sdes { BCOM_VENDORID, BCOM_DEVICEID_BCM4401B0, 75134590Sdes "Broadcom BCM4401-B0 Fast Ethernet" }, 76119917Swpaul { 0, 0, NULL } 77119917Swpaul}; 78119917Swpaul 79119917Swpaulstatic int bfe_probe (device_t); 80119917Swpaulstatic int bfe_attach (device_t); 81119917Swpaulstatic int bfe_detach (device_t); 82164456Sjhbstatic int bfe_suspend (device_t); 83164456Sjhbstatic int bfe_resume (device_t); 84119917Swpaulstatic void bfe_release_resources (struct bfe_softc *); 85119917Swpaulstatic void bfe_intr (void *); 86181953Syongaristatic int bfe_encap (struct bfe_softc *, struct mbuf **); 87119917Swpaulstatic void bfe_start (struct ifnet *); 88136804Smtmstatic void bfe_start_locked (struct ifnet *); 89119917Swpaulstatic int bfe_ioctl (struct ifnet *, u_long, caddr_t); 90119917Swpaulstatic void bfe_init (void *); 91136804Smtmstatic void bfe_init_locked (void *); 92119917Swpaulstatic void bfe_stop (struct bfe_softc *); 93175787Syongaristatic void bfe_watchdog (struct bfe_softc *); 94173839Syongaristatic int bfe_shutdown (device_t); 95119917Swpaulstatic void bfe_tick (void *); 96119917Swpaulstatic void bfe_txeof (struct bfe_softc *); 97119917Swpaulstatic void bfe_rxeof (struct bfe_softc *); 98119917Swpaulstatic void bfe_set_rx_mode (struct bfe_softc *); 99119917Swpaulstatic int bfe_list_rx_init (struct bfe_softc *); 100181953Syongaristatic void bfe_list_tx_init (struct bfe_softc *); 101181953Syongaristatic void bfe_discard_buf (struct bfe_softc *, int); 102181953Syongaristatic int bfe_list_newbuf (struct bfe_softc *, int); 103119917Swpaulstatic void bfe_rx_ring_free (struct bfe_softc *); 104119917Swpaul 105119917Swpaulstatic void bfe_pci_setup (struct bfe_softc *, u_int32_t); 106119917Swpaulstatic int bfe_ifmedia_upd (struct ifnet *); 107119917Swpaulstatic void bfe_ifmedia_sts (struct ifnet *, struct ifmediareq *); 108119917Swpaulstatic int bfe_miibus_readreg (device_t, int, int); 109119917Swpaulstatic int bfe_miibus_writereg (device_t, int, int, int); 110119917Swpaulstatic void bfe_miibus_statchg (device_t); 111133282Sdesstatic int bfe_wait_bit (struct bfe_softc *, u_int32_t, u_int32_t, 112119917Swpaul u_long, const int); 113119917Swpaulstatic void bfe_get_config (struct bfe_softc *sc); 114119917Swpaulstatic void bfe_read_eeprom (struct bfe_softc *, u_int8_t *); 115119917Swpaulstatic void bfe_stats_update (struct bfe_softc *); 116119917Swpaulstatic void bfe_clear_stats (struct bfe_softc *); 117119917Swpaulstatic int bfe_readphy (struct bfe_softc *, u_int32_t, u_int32_t*); 118119917Swpaulstatic int bfe_writephy (struct bfe_softc *, u_int32_t, u_int32_t); 119119917Swpaulstatic int bfe_resetphy (struct bfe_softc *); 120119917Swpaulstatic int bfe_setupphy (struct bfe_softc *); 121119917Swpaulstatic void bfe_chip_reset (struct bfe_softc *); 122119917Swpaulstatic void bfe_chip_halt (struct bfe_softc *); 123119917Swpaulstatic void bfe_core_reset (struct bfe_softc *); 124119917Swpaulstatic void bfe_core_disable (struct bfe_softc *); 125181953Syongaristatic int bfe_dma_alloc (struct bfe_softc *); 126181953Syongaristatic void bfe_dma_free (struct bfe_softc *sc); 127119917Swpaulstatic void bfe_dma_map (void *, bus_dma_segment_t *, int, int); 128119917Swpaulstatic void bfe_cam_write (struct bfe_softc *, u_char *, int); 129181994Syongaristatic int sysctl_bfe_stats (SYSCTL_HANDLER_ARGS); 130119917Swpaul 131119917Swpaulstatic device_method_t bfe_methods[] = { 132119917Swpaul /* Device interface */ 133119917Swpaul DEVMETHOD(device_probe, bfe_probe), 134119917Swpaul DEVMETHOD(device_attach, bfe_attach), 135119917Swpaul DEVMETHOD(device_detach, bfe_detach), 136119917Swpaul DEVMETHOD(device_shutdown, bfe_shutdown), 137164456Sjhb DEVMETHOD(device_suspend, bfe_suspend), 138164456Sjhb DEVMETHOD(device_resume, bfe_resume), 139119917Swpaul 140119917Swpaul /* MII interface */ 141119917Swpaul DEVMETHOD(miibus_readreg, bfe_miibus_readreg), 142119917Swpaul DEVMETHOD(miibus_writereg, bfe_miibus_writereg), 143119917Swpaul DEVMETHOD(miibus_statchg, bfe_miibus_statchg), 144119917Swpaul 145227843Smarius DEVMETHOD_END 146119917Swpaul}; 147119917Swpaul 148119917Swpaulstatic driver_t bfe_driver = { 149119917Swpaul "bfe", 150119917Swpaul bfe_methods, 151119917Swpaul sizeof(struct bfe_softc) 152119917Swpaul}; 153119917Swpaul 154119917Swpaulstatic devclass_t bfe_devclass; 155119917Swpaul 156119917SwpaulDRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, 0, 0); 157119917SwpaulDRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, 0, 0); 158119917Swpaul 159119917Swpaul/* 160133282Sdes * Probe for a Broadcom 4401 chip. 161119917Swpaul */ 162119917Swpaulstatic int 163119917Swpaulbfe_probe(device_t dev) 164119917Swpaul{ 165119917Swpaul struct bfe_type *t; 166119917Swpaul 167119917Swpaul t = bfe_devs; 168119917Swpaul 169180954Syongari while (t->bfe_name != NULL) { 170181556Syongari if (pci_get_vendor(dev) == t->bfe_vid && 171181556Syongari pci_get_device(dev) == t->bfe_did) { 172181557Syongari device_set_desc(dev, t->bfe_name); 173143163Simp return (BUS_PROBE_DEFAULT); 174119917Swpaul } 175119917Swpaul t++; 176119917Swpaul } 177119917Swpaul 178133282Sdes return (ENXIO); 179119917Swpaul} 180119917Swpaul 181181953Syongaristruct bfe_dmamap_arg { 182181953Syongari bus_addr_t bfe_busaddr; 183181953Syongari}; 184181953Syongari 185119917Swpaulstatic int 186181953Syongaribfe_dma_alloc(struct bfe_softc *sc) 187119917Swpaul{ 188181953Syongari struct bfe_dmamap_arg ctx; 189181953Syongari struct bfe_rx_data *rd; 190181953Syongari struct bfe_tx_data *td; 191119917Swpaul int error, i; 192119917Swpaul 193158075Sscottl /* 194158075Sscottl * parent tag. Apparently the chip cannot handle any DMA address 195158075Sscottl * greater than 1GB. 196158075Sscottl */ 197181953Syongari error = bus_dma_tag_create(bus_get_dma_tag(sc->bfe_dev), /* parent */ 198181953Syongari 1, 0, /* alignment, boundary */ 199181953Syongari BFE_DMA_MAXADDR, /* lowaddr */ 200181953Syongari BUS_SPACE_MAXADDR, /* highaddr */ 201181953Syongari NULL, NULL, /* filter, filterarg */ 202181953Syongari BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 203181953Syongari 0, /* nsegments */ 204181953Syongari BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 205181953Syongari 0, /* flags */ 206181953Syongari NULL, NULL, /* lockfunc, lockarg */ 207181953Syongari &sc->bfe_parent_tag); 208181953Syongari if (error != 0) { 209181953Syongari device_printf(sc->bfe_dev, "cannot create parent DMA tag.\n"); 210181953Syongari goto fail; 211181953Syongari } 212119917Swpaul 213181953Syongari /* Create tag for Tx ring. */ 214181953Syongari error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */ 215181953Syongari BFE_TX_RING_ALIGN, 0, /* alignment, boundary */ 216181953Syongari BUS_SPACE_MAXADDR, /* lowaddr */ 217181953Syongari BUS_SPACE_MAXADDR, /* highaddr */ 218181953Syongari NULL, NULL, /* filter, filterarg */ 219181953Syongari BFE_TX_LIST_SIZE, /* maxsize */ 220181953Syongari 1, /* nsegments */ 221181953Syongari BFE_TX_LIST_SIZE, /* maxsegsize */ 222181953Syongari 0, /* flags */ 223181953Syongari NULL, NULL, /* lockfunc, lockarg */ 224181953Syongari &sc->bfe_tx_tag); 225181953Syongari if (error != 0) { 226181953Syongari device_printf(sc->bfe_dev, "cannot create Tx ring DMA tag.\n"); 227181953Syongari goto fail; 228181953Syongari } 229119917Swpaul 230181953Syongari /* Create tag for Rx ring. */ 231181953Syongari error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */ 232181953Syongari BFE_RX_RING_ALIGN, 0, /* alignment, boundary */ 233181953Syongari BUS_SPACE_MAXADDR, /* lowaddr */ 234181953Syongari BUS_SPACE_MAXADDR, /* highaddr */ 235181953Syongari NULL, NULL, /* filter, filterarg */ 236181953Syongari BFE_RX_LIST_SIZE, /* maxsize */ 237181953Syongari 1, /* nsegments */ 238181953Syongari BFE_RX_LIST_SIZE, /* maxsegsize */ 239181953Syongari 0, /* flags */ 240181953Syongari NULL, NULL, /* lockfunc, lockarg */ 241181953Syongari &sc->bfe_rx_tag); 242181953Syongari if (error != 0) { 243181953Syongari device_printf(sc->bfe_dev, "cannot create Rx ring DMA tag.\n"); 244181953Syongari goto fail; 245119917Swpaul } 246119917Swpaul 247181953Syongari /* Create tag for Tx buffers. */ 248181953Syongari error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */ 249181953Syongari 1, 0, /* alignment, boundary */ 250181953Syongari BUS_SPACE_MAXADDR, /* lowaddr */ 251181953Syongari BUS_SPACE_MAXADDR, /* highaddr */ 252181953Syongari NULL, NULL, /* filter, filterarg */ 253181953Syongari MCLBYTES * BFE_MAXTXSEGS, /* maxsize */ 254181953Syongari BFE_MAXTXSEGS, /* nsegments */ 255181953Syongari MCLBYTES, /* maxsegsize */ 256181953Syongari 0, /* flags */ 257181953Syongari NULL, NULL, /* lockfunc, lockarg */ 258181953Syongari &sc->bfe_txmbuf_tag); 259181953Syongari if (error != 0) { 260181953Syongari device_printf(sc->bfe_dev, 261181953Syongari "cannot create Tx buffer DMA tag.\n"); 262181953Syongari goto fail; 263181953Syongari } 264119917Swpaul 265181953Syongari /* Create tag for Rx buffers. */ 266181953Syongari error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */ 267181953Syongari 1, 0, /* alignment, boundary */ 268181953Syongari BUS_SPACE_MAXADDR, /* lowaddr */ 269181953Syongari BUS_SPACE_MAXADDR, /* highaddr */ 270181953Syongari NULL, NULL, /* filter, filterarg */ 271181953Syongari MCLBYTES, /* maxsize */ 272181953Syongari 1, /* nsegments */ 273181953Syongari MCLBYTES, /* maxsegsize */ 274181953Syongari 0, /* flags */ 275181953Syongari NULL, NULL, /* lockfunc, lockarg */ 276181953Syongari &sc->bfe_rxmbuf_tag); 277181953Syongari if (error != 0) { 278181953Syongari device_printf(sc->bfe_dev, 279181953Syongari "cannot create Rx buffer DMA tag.\n"); 280181953Syongari goto fail; 281119917Swpaul } 282119917Swpaul 283181953Syongari /* Allocate DMA'able memory and load DMA map. */ 284181953Syongari error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list, 285181953Syongari BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->bfe_tx_map); 286181953Syongari if (error != 0) { 287181953Syongari device_printf(sc->bfe_dev, 288181953Syongari "cannot allocate DMA'able memory for Tx ring.\n"); 289181953Syongari goto fail; 290181953Syongari } 291181953Syongari ctx.bfe_busaddr = 0; 292181953Syongari error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map, 293181953Syongari sc->bfe_tx_list, BFE_TX_LIST_SIZE, bfe_dma_map, &ctx, 294181953Syongari BUS_DMA_NOWAIT); 295181953Syongari if (error != 0 || ctx.bfe_busaddr == 0) { 296181953Syongari device_printf(sc->bfe_dev, 297181953Syongari "cannot load DMA'able memory for Tx ring.\n"); 298181953Syongari goto fail; 299181953Syongari } 300181953Syongari sc->bfe_tx_dma = BFE_ADDR_LO(ctx.bfe_busaddr); 301119917Swpaul 302181953Syongari error = bus_dmamem_alloc(sc->bfe_rx_tag, (void *)&sc->bfe_rx_list, 303181953Syongari BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->bfe_rx_map); 304181953Syongari if (error != 0) { 305181953Syongari device_printf(sc->bfe_dev, 306181953Syongari "cannot allocate DMA'able memory for Rx ring.\n"); 307181953Syongari goto fail; 308119917Swpaul } 309181953Syongari ctx.bfe_busaddr = 0; 310181953Syongari error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map, 311181953Syongari sc->bfe_rx_list, BFE_RX_LIST_SIZE, bfe_dma_map, &ctx, 312181953Syongari BUS_DMA_NOWAIT); 313181953Syongari if (error != 0 || ctx.bfe_busaddr == 0) { 314181953Syongari device_printf(sc->bfe_dev, 315181953Syongari "cannot load DMA'able memory for Rx ring.\n"); 316181953Syongari goto fail; 317181953Syongari } 318181953Syongari sc->bfe_rx_dma = BFE_ADDR_LO(ctx.bfe_busaddr); 319119917Swpaul 320181953Syongari /* Create DMA maps for Tx buffers. */ 321181953Syongari for (i = 0; i < BFE_TX_LIST_CNT; i++) { 322181953Syongari td = &sc->bfe_tx_ring[i]; 323181953Syongari td->bfe_mbuf = NULL; 324181953Syongari td->bfe_map = NULL; 325181953Syongari error = bus_dmamap_create(sc->bfe_txmbuf_tag, 0, &td->bfe_map); 326181953Syongari if (error != 0) { 327181953Syongari device_printf(sc->bfe_dev, 328181953Syongari "cannot create DMA map for Tx.\n"); 329181953Syongari goto fail; 330119917Swpaul } 331119917Swpaul } 332119917Swpaul 333181953Syongari /* Create spare DMA map for Rx buffers. */ 334181953Syongari error = bus_dmamap_create(sc->bfe_rxmbuf_tag, 0, &sc->bfe_rx_sparemap); 335181953Syongari if (error != 0) { 336181953Syongari device_printf(sc->bfe_dev, "cannot create spare DMA map for Rx.\n"); 337181953Syongari goto fail; 338181953Syongari } 339181953Syongari /* Create DMA maps for Rx buffers. */ 340181953Syongari for (i = 0; i < BFE_RX_LIST_CNT; i++) { 341181953Syongari rd = &sc->bfe_rx_ring[i]; 342181953Syongari rd->bfe_mbuf = NULL; 343181953Syongari rd->bfe_map = NULL; 344181953Syongari rd->bfe_ctrl = 0; 345181953Syongari error = bus_dmamap_create(sc->bfe_rxmbuf_tag, 0, &rd->bfe_map); 346181953Syongari if (error != 0) { 347181953Syongari device_printf(sc->bfe_dev, 348181953Syongari "cannot create DMA map for Rx.\n"); 349181953Syongari goto fail; 350119917Swpaul } 351119917Swpaul } 352119917Swpaul 353181953Syongarifail: 354181953Syongari return (error); 355181953Syongari} 356119917Swpaul 357181953Syongaristatic void 358181953Syongaribfe_dma_free(struct bfe_softc *sc) 359181953Syongari{ 360181953Syongari struct bfe_tx_data *td; 361181953Syongari struct bfe_rx_data *rd; 362181953Syongari int i; 363119917Swpaul 364181953Syongari /* Tx ring. */ 365181953Syongari if (sc->bfe_tx_tag != NULL) { 366181953Syongari if (sc->bfe_tx_map != NULL) 367181953Syongari bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map); 368181953Syongari if (sc->bfe_tx_map != NULL && sc->bfe_tx_list != NULL) 369181953Syongari bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list, 370181953Syongari sc->bfe_tx_map); 371181953Syongari sc->bfe_tx_map = NULL; 372181953Syongari sc->bfe_tx_list = NULL; 373181953Syongari bus_dma_tag_destroy(sc->bfe_tx_tag); 374181953Syongari sc->bfe_tx_tag = NULL; 375181953Syongari } 376119917Swpaul 377181953Syongari /* Rx ring. */ 378181953Syongari if (sc->bfe_rx_tag != NULL) { 379181953Syongari if (sc->bfe_rx_map != NULL) 380181953Syongari bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map); 381181953Syongari if (sc->bfe_rx_map != NULL && sc->bfe_rx_list != NULL) 382181953Syongari bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list, 383181953Syongari sc->bfe_rx_map); 384181953Syongari sc->bfe_rx_map = NULL; 385181953Syongari sc->bfe_rx_list = NULL; 386181953Syongari bus_dma_tag_destroy(sc->bfe_rx_tag); 387181953Syongari sc->bfe_rx_tag = NULL; 388181953Syongari } 389119917Swpaul 390181953Syongari /* Tx buffers. */ 391181953Syongari if (sc->bfe_txmbuf_tag != NULL) { 392181953Syongari for (i = 0; i < BFE_TX_LIST_CNT; i++) { 393181953Syongari td = &sc->bfe_tx_ring[i]; 394181953Syongari if (td->bfe_map != NULL) { 395181953Syongari bus_dmamap_destroy(sc->bfe_txmbuf_tag, 396181953Syongari td->bfe_map); 397181953Syongari td->bfe_map = NULL; 398181953Syongari } 399181953Syongari } 400181953Syongari bus_dma_tag_destroy(sc->bfe_txmbuf_tag); 401181953Syongari sc->bfe_txmbuf_tag = NULL; 402181953Syongari } 403119917Swpaul 404181953Syongari /* Rx buffers. */ 405181953Syongari if (sc->bfe_rxmbuf_tag != NULL) { 406181953Syongari for (i = 0; i < BFE_RX_LIST_CNT; i++) { 407181953Syongari rd = &sc->bfe_rx_ring[i]; 408181953Syongari if (rd->bfe_map != NULL) { 409181953Syongari bus_dmamap_destroy(sc->bfe_rxmbuf_tag, 410181953Syongari rd->bfe_map); 411181953Syongari rd->bfe_map = NULL; 412181953Syongari } 413181953Syongari } 414181953Syongari if (sc->bfe_rx_sparemap != NULL) { 415181953Syongari bus_dmamap_destroy(sc->bfe_rxmbuf_tag, 416181953Syongari sc->bfe_rx_sparemap); 417181953Syongari sc->bfe_rx_sparemap = NULL; 418181953Syongari } 419181953Syongari bus_dma_tag_destroy(sc->bfe_rxmbuf_tag); 420181953Syongari sc->bfe_rxmbuf_tag = NULL; 421181953Syongari } 422119917Swpaul 423181953Syongari if (sc->bfe_parent_tag != NULL) { 424181953Syongari bus_dma_tag_destroy(sc->bfe_parent_tag); 425181953Syongari sc->bfe_parent_tag = NULL; 426181953Syongari } 427119917Swpaul} 428119917Swpaul 429119917Swpaulstatic int 430119917Swpaulbfe_attach(device_t dev) 431119917Swpaul{ 432147256Sbrooks struct ifnet *ifp = NULL; 433119917Swpaul struct bfe_softc *sc; 434180950Syongari int error = 0, rid; 435119917Swpaul 436119917Swpaul sc = device_get_softc(dev); 437119917Swpaul mtx_init(&sc->bfe_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 438136804Smtm MTX_DEF); 439175787Syongari callout_init_mtx(&sc->bfe_stat_co, &sc->bfe_mtx, 0); 440119917Swpaul 441119917Swpaul sc->bfe_dev = dev; 442119917Swpaul 443119917Swpaul /* 444119917Swpaul * Map control/status registers. 445119917Swpaul */ 446119917Swpaul pci_enable_busmaster(dev); 447119917Swpaul 448181953Syongari rid = PCIR_BAR(0); 449127135Snjl sc->bfe_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 450119917Swpaul RF_ACTIVE); 451119917Swpaul if (sc->bfe_res == NULL) { 452180950Syongari device_printf(dev, "couldn't map memory\n"); 453119917Swpaul error = ENXIO; 454119917Swpaul goto fail; 455119917Swpaul } 456119917Swpaul 457119917Swpaul /* Allocate interrupt */ 458119917Swpaul rid = 0; 459119917Swpaul 460127135Snjl sc->bfe_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 461119917Swpaul RF_SHAREABLE | RF_ACTIVE); 462119917Swpaul if (sc->bfe_irq == NULL) { 463180950Syongari device_printf(dev, "couldn't map interrupt\n"); 464119917Swpaul error = ENXIO; 465119917Swpaul goto fail; 466119917Swpaul } 467119917Swpaul 468181953Syongari if (bfe_dma_alloc(sc) != 0) { 469180950Syongari device_printf(dev, "failed to allocate DMA resources\n"); 470119917Swpaul error = ENXIO; 471119917Swpaul goto fail; 472119917Swpaul } 473119917Swpaul 474181994Syongari SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 475181994Syongari SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 476181994Syongari "stats", CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_bfe_stats, 477181994Syongari "I", "Statistics"); 478181994Syongari 479119917Swpaul /* Set up ifnet structure */ 480147256Sbrooks ifp = sc->bfe_ifp = if_alloc(IFT_ETHER); 481147256Sbrooks if (ifp == NULL) { 482180950Syongari device_printf(dev, "failed to if_alloc()\n"); 483147256Sbrooks error = ENOSPC; 484147256Sbrooks goto fail; 485147256Sbrooks } 486119917Swpaul ifp->if_softc = sc; 487121816Sbrooks if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 488119917Swpaul ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 489119917Swpaul ifp->if_ioctl = bfe_ioctl; 490119917Swpaul ifp->if_start = bfe_start; 491119917Swpaul ifp->if_init = bfe_init; 492131455Smlaier IFQ_SET_MAXLEN(&ifp->if_snd, BFE_TX_QLEN); 493131455Smlaier ifp->if_snd.ifq_drv_maxlen = BFE_TX_QLEN; 494131455Smlaier IFQ_SET_READY(&ifp->if_snd); 495119917Swpaul 496119917Swpaul bfe_get_config(sc); 497119917Swpaul 498119917Swpaul /* Reset the chip and turn on the PHY */ 499136804Smtm BFE_LOCK(sc); 500119917Swpaul bfe_chip_reset(sc); 501136804Smtm BFE_UNLOCK(sc); 502119917Swpaul 503213893Smarius error = mii_attach(dev, &sc->bfe_miibus, ifp, bfe_ifmedia_upd, 504213893Smarius bfe_ifmedia_sts, BMSR_DEFCAPMASK, sc->bfe_phyaddr, MII_OFFSET_ANY, 505213893Smarius 0); 506213893Smarius if (error != 0) { 507213893Smarius device_printf(dev, "attaching PHYs failed\n"); 508119917Swpaul goto fail; 509119917Swpaul } 510119917Swpaul 511147256Sbrooks ether_ifattach(ifp, sc->bfe_enaddr); 512119917Swpaul 513119917Swpaul /* 514129708Sdes * Tell the upper layer(s) we support long frames. 515129708Sdes */ 516129708Sdes ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 517129708Sdes ifp->if_capabilities |= IFCAP_VLAN_MTU; 518129709Sdes ifp->if_capenable |= IFCAP_VLAN_MTU; 519129708Sdes 520129708Sdes /* 521119917Swpaul * Hook interrupt last to avoid having to lock softc 522119917Swpaul */ 523136804Smtm error = bus_setup_intr(dev, sc->bfe_irq, INTR_TYPE_NET | INTR_MPSAFE, 524166901Spiso NULL, bfe_intr, sc, &sc->bfe_intrhand); 525119917Swpaul 526119917Swpaul if (error) { 527180950Syongari device_printf(dev, "couldn't set up irq\n"); 528119917Swpaul goto fail; 529119917Swpaul } 530119917Swpaulfail: 531181953Syongari if (error != 0) 532181953Syongari bfe_detach(dev); 533133282Sdes return (error); 534119917Swpaul} 535119917Swpaul 536119917Swpaulstatic int 537119917Swpaulbfe_detach(device_t dev) 538119917Swpaul{ 539119917Swpaul struct bfe_softc *sc; 540119917Swpaul struct ifnet *ifp; 541119917Swpaul 542119917Swpaul sc = device_get_softc(dev); 543119917Swpaul 544147256Sbrooks ifp = sc->bfe_ifp; 545119917Swpaul 546119917Swpaul if (device_is_attached(dev)) { 547175787Syongari BFE_LOCK(sc); 548181976Syongari sc->bfe_flags |= BFE_FLAG_DETACH; 549119917Swpaul bfe_stop(sc); 550175787Syongari BFE_UNLOCK(sc); 551175787Syongari callout_drain(&sc->bfe_stat_co); 552175787Syongari if (ifp != NULL) 553175787Syongari ether_ifdetach(ifp); 554119917Swpaul } 555119917Swpaul 556181953Syongari BFE_LOCK(sc); 557119917Swpaul bfe_chip_reset(sc); 558181953Syongari BFE_UNLOCK(sc); 559119917Swpaul 560119917Swpaul bus_generic_detach(dev); 561180954Syongari if (sc->bfe_miibus != NULL) 562119917Swpaul device_delete_child(dev, sc->bfe_miibus); 563119917Swpaul 564119917Swpaul bfe_release_resources(sc); 565181953Syongari bfe_dma_free(sc); 566119917Swpaul mtx_destroy(&sc->bfe_mtx); 567119917Swpaul 568133282Sdes return (0); 569119917Swpaul} 570119917Swpaul 571119917Swpaul/* 572119917Swpaul * Stop all chip I/O so that the kernel's probe routines don't 573119917Swpaul * get confused by errant DMAs when rebooting. 574119917Swpaul */ 575173839Syongaristatic int 576119917Swpaulbfe_shutdown(device_t dev) 577119917Swpaul{ 578119917Swpaul struct bfe_softc *sc; 579119917Swpaul 580119917Swpaul sc = device_get_softc(dev); 581119917Swpaul BFE_LOCK(sc); 582133282Sdes bfe_stop(sc); 583119917Swpaul 584119917Swpaul BFE_UNLOCK(sc); 585173839Syongari 586173839Syongari return (0); 587119917Swpaul} 588119917Swpaul 589119917Swpaulstatic int 590164456Sjhbbfe_suspend(device_t dev) 591164456Sjhb{ 592164456Sjhb struct bfe_softc *sc; 593164456Sjhb 594164456Sjhb sc = device_get_softc(dev); 595164456Sjhb BFE_LOCK(sc); 596164456Sjhb bfe_stop(sc); 597164456Sjhb BFE_UNLOCK(sc); 598164456Sjhb 599164456Sjhb return (0); 600164456Sjhb} 601164456Sjhb 602164456Sjhbstatic int 603164456Sjhbbfe_resume(device_t dev) 604164456Sjhb{ 605164456Sjhb struct bfe_softc *sc; 606164456Sjhb struct ifnet *ifp; 607164456Sjhb 608164456Sjhb sc = device_get_softc(dev); 609164456Sjhb ifp = sc->bfe_ifp; 610164456Sjhb BFE_LOCK(sc); 611164456Sjhb bfe_chip_reset(sc); 612164456Sjhb if (ifp->if_flags & IFF_UP) { 613164456Sjhb bfe_init_locked(sc); 614164456Sjhb if (ifp->if_drv_flags & IFF_DRV_RUNNING && 615164456Sjhb !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 616164456Sjhb bfe_start_locked(ifp); 617164456Sjhb } 618164456Sjhb BFE_UNLOCK(sc); 619164456Sjhb 620164456Sjhb return (0); 621164456Sjhb} 622164456Sjhb 623164456Sjhbstatic int 624119917Swpaulbfe_miibus_readreg(device_t dev, int phy, int reg) 625119917Swpaul{ 626119917Swpaul struct bfe_softc *sc; 627119917Swpaul u_int32_t ret; 628119917Swpaul 629119917Swpaul sc = device_get_softc(dev); 630119917Swpaul bfe_readphy(sc, reg, &ret); 631119917Swpaul 632133282Sdes return (ret); 633119917Swpaul} 634119917Swpaul 635119917Swpaulstatic int 636119917Swpaulbfe_miibus_writereg(device_t dev, int phy, int reg, int val) 637119917Swpaul{ 638119917Swpaul struct bfe_softc *sc; 639119917Swpaul 640119917Swpaul sc = device_get_softc(dev); 641133282Sdes bfe_writephy(sc, reg, val); 642119917Swpaul 643133282Sdes return (0); 644119917Swpaul} 645119917Swpaul 646119917Swpaulstatic void 647119917Swpaulbfe_miibus_statchg(device_t dev) 648119917Swpaul{ 649175787Syongari struct bfe_softc *sc; 650175787Syongari struct mii_data *mii; 651175787Syongari u_int32_t val, flow; 652175787Syongari 653175787Syongari sc = device_get_softc(dev); 654175787Syongari mii = device_get_softc(sc->bfe_miibus); 655175787Syongari 656181976Syongari sc->bfe_flags &= ~BFE_FLAG_LINK; 657181976Syongari if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 658181976Syongari (IFM_ACTIVE | IFM_AVALID)) { 659181976Syongari switch (IFM_SUBTYPE(mii->mii_media_active)) { 660181976Syongari case IFM_10_T: 661181976Syongari case IFM_100_TX: 662181976Syongari sc->bfe_flags |= BFE_FLAG_LINK; 663181976Syongari break; 664181976Syongari default: 665181976Syongari break; 666181976Syongari } 667181976Syongari } 668175787Syongari 669175787Syongari /* XXX Should stop Rx/Tx engine prior to touching MAC. */ 670175787Syongari val = CSR_READ_4(sc, BFE_TX_CTRL); 671175787Syongari val &= ~BFE_TX_DUPLEX; 672175787Syongari if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 673175787Syongari val |= BFE_TX_DUPLEX; 674175787Syongari flow = 0; 675175787Syongari#ifdef notyet 676175787Syongari flow = CSR_READ_4(sc, BFE_RXCONF); 677175787Syongari flow &= ~BFE_RXCONF_FLOW; 678175787Syongari if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & 679175787Syongari IFM_ETH_RXPAUSE) != 0) 680175787Syongari flow |= BFE_RXCONF_FLOW; 681175787Syongari CSR_WRITE_4(sc, BFE_RXCONF, flow); 682175787Syongari /* 683175787Syongari * It seems that the hardware has Tx pause issues 684175787Syongari * so enable only Rx pause. 685175787Syongari */ 686175787Syongari flow = CSR_READ_4(sc, BFE_MAC_FLOW); 687175787Syongari flow &= ~BFE_FLOW_PAUSE_ENAB; 688175787Syongari CSR_WRITE_4(sc, BFE_MAC_FLOW, flow); 689175787Syongari#endif 690175787Syongari } 691175787Syongari CSR_WRITE_4(sc, BFE_TX_CTRL, val); 692119917Swpaul} 693119917Swpaul 694119917Swpaulstatic void 695119917Swpaulbfe_tx_ring_free(struct bfe_softc *sc) 696119917Swpaul{ 697126470Sjulian int i; 698133282Sdes 699126470Sjulian for(i = 0; i < BFE_TX_LIST_CNT; i++) { 700180954Syongari if (sc->bfe_tx_ring[i].bfe_mbuf != NULL) { 701181953Syongari bus_dmamap_sync(sc->bfe_txmbuf_tag, 702181953Syongari sc->bfe_tx_ring[i].bfe_map, BUS_DMASYNC_POSTWRITE); 703181953Syongari bus_dmamap_unload(sc->bfe_txmbuf_tag, 704181953Syongari sc->bfe_tx_ring[i].bfe_map); 705126470Sjulian m_freem(sc->bfe_tx_ring[i].bfe_mbuf); 706126470Sjulian sc->bfe_tx_ring[i].bfe_mbuf = NULL; 707126470Sjulian } 708126470Sjulian } 709126470Sjulian bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 710181953Syongari bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, 711181953Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 712119917Swpaul} 713119917Swpaul 714119917Swpaulstatic void 715119917Swpaulbfe_rx_ring_free(struct bfe_softc *sc) 716119917Swpaul{ 717119917Swpaul int i; 718119917Swpaul 719119917Swpaul for (i = 0; i < BFE_RX_LIST_CNT; i++) { 720119917Swpaul if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) { 721181953Syongari bus_dmamap_sync(sc->bfe_rxmbuf_tag, 722181953Syongari sc->bfe_rx_ring[i].bfe_map, BUS_DMASYNC_POSTREAD); 723181953Syongari bus_dmamap_unload(sc->bfe_rxmbuf_tag, 724181953Syongari sc->bfe_rx_ring[i].bfe_map); 725119917Swpaul m_freem(sc->bfe_rx_ring[i].bfe_mbuf); 726119917Swpaul sc->bfe_rx_ring[i].bfe_mbuf = NULL; 727119917Swpaul } 728119917Swpaul } 729119917Swpaul bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 730181953Syongari bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, 731181953Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 732119917Swpaul} 733119917Swpaul 734133282Sdesstatic int 735119917Swpaulbfe_list_rx_init(struct bfe_softc *sc) 736119917Swpaul{ 737181953Syongari struct bfe_rx_data *rd; 738119917Swpaul int i; 739119917Swpaul 740181953Syongari sc->bfe_rx_prod = sc->bfe_rx_cons = 0; 741181953Syongari bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 742181953Syongari for (i = 0; i < BFE_RX_LIST_CNT; i++) { 743181953Syongari rd = &sc->bfe_rx_ring[i]; 744181953Syongari rd->bfe_mbuf = NULL; 745181953Syongari rd->bfe_ctrl = 0; 746181953Syongari if (bfe_list_newbuf(sc, i) != 0) 747133282Sdes return (ENOBUFS); 748119917Swpaul } 749119917Swpaul 750181953Syongari bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, 751181953Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 752119917Swpaul CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc))); 753119917Swpaul 754133282Sdes return (0); 755119917Swpaul} 756119917Swpaul 757181953Syongaristatic void 758181953Syongaribfe_list_tx_init(struct bfe_softc *sc) 759181953Syongari{ 760181953Syongari int i; 761181953Syongari 762181953Syongari sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0; 763181953Syongari bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 764181953Syongari for (i = 0; i < BFE_TX_LIST_CNT; i++) 765181953Syongari sc->bfe_tx_ring[i].bfe_mbuf = NULL; 766181953Syongari 767181953Syongari bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, 768181953Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 769181953Syongari} 770181953Syongari 771181953Syongaristatic void 772181953Syongaribfe_discard_buf(struct bfe_softc *sc, int c) 773181953Syongari{ 774181953Syongari struct bfe_rx_data *r; 775181953Syongari struct bfe_desc *d; 776181953Syongari 777181953Syongari r = &sc->bfe_rx_ring[c]; 778181953Syongari d = &sc->bfe_rx_list[c]; 779181953Syongari d->bfe_ctrl = htole32(r->bfe_ctrl); 780181953Syongari} 781181953Syongari 782119917Swpaulstatic int 783181953Syongaribfe_list_newbuf(struct bfe_softc *sc, int c) 784119917Swpaul{ 785119917Swpaul struct bfe_rxheader *rx_header; 786119917Swpaul struct bfe_desc *d; 787181953Syongari struct bfe_rx_data *r; 788181953Syongari struct mbuf *m; 789181953Syongari bus_dma_segment_t segs[1]; 790181953Syongari bus_dmamap_t map; 791119917Swpaul u_int32_t ctrl; 792181953Syongari int nsegs; 793119917Swpaul 794243857Sglebius m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 795181953Syongari m->m_len = m->m_pkthdr.len = MCLBYTES; 796119917Swpaul 797181953Syongari if (bus_dmamap_load_mbuf_sg(sc->bfe_rxmbuf_tag, sc->bfe_rx_sparemap, 798181953Syongari m, segs, &nsegs, 0) != 0) { 799181953Syongari m_freem(m); 800181953Syongari return (ENOBUFS); 801119917Swpaul } 802119917Swpaul 803181953Syongari KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 804181953Syongari r = &sc->bfe_rx_ring[c]; 805181953Syongari if (r->bfe_mbuf != NULL) { 806181953Syongari bus_dmamap_sync(sc->bfe_rxmbuf_tag, r->bfe_map, 807181953Syongari BUS_DMASYNC_POSTREAD); 808181953Syongari bus_dmamap_unload(sc->bfe_rxmbuf_tag, r->bfe_map); 809181953Syongari } 810181953Syongari map = r->bfe_map; 811181953Syongari r->bfe_map = sc->bfe_rx_sparemap; 812181953Syongari sc->bfe_rx_sparemap = map; 813181953Syongari r->bfe_mbuf = m; 814181953Syongari 815119917Swpaul rx_header = mtod(m, struct bfe_rxheader *); 816119917Swpaul rx_header->len = 0; 817119917Swpaul rx_header->flags = 0; 818181953Syongari bus_dmamap_sync(sc->bfe_rxmbuf_tag, r->bfe_map, BUS_DMASYNC_PREREAD); 819181953Syongari 820181953Syongari ctrl = segs[0].ds_len & BFE_DESC_LEN; 821181953Syongari KASSERT(ctrl > ETHER_MAX_LEN + 32, ("%s: buffer size too small(%d)!", 822181953Syongari __func__, ctrl)); 823181953Syongari if (c == BFE_RX_LIST_CNT - 1) 824181953Syongari ctrl |= BFE_DESC_EOT; 825181953Syongari r->bfe_ctrl = ctrl; 826119917Swpaul 827119917Swpaul d = &sc->bfe_rx_list[c]; 828181953Syongari d->bfe_ctrl = htole32(ctrl); 829181953Syongari /* The chip needs all addresses to be added to BFE_PCI_DMA. */ 830181953Syongari d->bfe_addr = htole32(BFE_ADDR_LO(segs[0].ds_addr) + BFE_PCI_DMA); 831119917Swpaul 832133282Sdes return (0); 833119917Swpaul} 834119917Swpaul 835119917Swpaulstatic void 836119917Swpaulbfe_get_config(struct bfe_softc *sc) 837119917Swpaul{ 838119917Swpaul u_int8_t eeprom[128]; 839119917Swpaul 840119917Swpaul bfe_read_eeprom(sc, eeprom); 841119917Swpaul 842147256Sbrooks sc->bfe_enaddr[0] = eeprom[79]; 843147256Sbrooks sc->bfe_enaddr[1] = eeprom[78]; 844147256Sbrooks sc->bfe_enaddr[2] = eeprom[81]; 845147256Sbrooks sc->bfe_enaddr[3] = eeprom[80]; 846147256Sbrooks sc->bfe_enaddr[4] = eeprom[83]; 847147256Sbrooks sc->bfe_enaddr[5] = eeprom[82]; 848119917Swpaul 849119917Swpaul sc->bfe_phyaddr = eeprom[90] & 0x1f; 850119917Swpaul sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1; 851119917Swpaul 852133282Sdes sc->bfe_core_unit = 0; 853119917Swpaul sc->bfe_dma_offset = BFE_PCI_DMA; 854119917Swpaul} 855119917Swpaul 856119917Swpaulstatic void 857119917Swpaulbfe_pci_setup(struct bfe_softc *sc, u_int32_t cores) 858119917Swpaul{ 859119917Swpaul u_int32_t bar_orig, pci_rev, val; 860119917Swpaul 861119917Swpaul bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4); 862119917Swpaul pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4); 863119917Swpaul pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK; 864119917Swpaul 865119917Swpaul val = CSR_READ_4(sc, BFE_SBINTVEC); 866119917Swpaul val |= cores; 867119917Swpaul CSR_WRITE_4(sc, BFE_SBINTVEC, val); 868119917Swpaul 869119917Swpaul val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2); 870119917Swpaul val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST; 871119917Swpaul CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val); 872119917Swpaul 873119917Swpaul pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4); 874119917Swpaul} 875119917Swpaul 876133282Sdesstatic void 877119917Swpaulbfe_clear_stats(struct bfe_softc *sc) 878119917Swpaul{ 879181994Syongari uint32_t reg; 880119917Swpaul 881136804Smtm BFE_LOCK_ASSERT(sc); 882119917Swpaul 883119917Swpaul CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ); 884119917Swpaul for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) 885119917Swpaul CSR_READ_4(sc, reg); 886119917Swpaul for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) 887119917Swpaul CSR_READ_4(sc, reg); 888119917Swpaul} 889119917Swpaul 890133282Sdesstatic int 891119917Swpaulbfe_resetphy(struct bfe_softc *sc) 892119917Swpaul{ 893119917Swpaul u_int32_t val; 894119917Swpaul 895119917Swpaul bfe_writephy(sc, 0, BMCR_RESET); 896119917Swpaul DELAY(100); 897119917Swpaul bfe_readphy(sc, 0, &val); 898119917Swpaul if (val & BMCR_RESET) { 899180950Syongari device_printf(sc->bfe_dev, "PHY Reset would not complete.\n"); 900133282Sdes return (ENXIO); 901119917Swpaul } 902133282Sdes return (0); 903119917Swpaul} 904119917Swpaul 905119917Swpaulstatic void 906119917Swpaulbfe_chip_halt(struct bfe_softc *sc) 907119917Swpaul{ 908136804Smtm BFE_LOCK_ASSERT(sc); 909119917Swpaul /* disable interrupts - not that it actually does..*/ 910119917Swpaul CSR_WRITE_4(sc, BFE_IMASK, 0); 911119917Swpaul CSR_READ_4(sc, BFE_IMASK); 912119917Swpaul 913119917Swpaul CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 914119917Swpaul bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1); 915119917Swpaul 916119917Swpaul CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 917119917Swpaul CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 918119917Swpaul DELAY(10); 919119917Swpaul} 920119917Swpaul 921119917Swpaulstatic void 922119917Swpaulbfe_chip_reset(struct bfe_softc *sc) 923119917Swpaul{ 924133282Sdes u_int32_t val; 925119917Swpaul 926136804Smtm BFE_LOCK_ASSERT(sc); 927119917Swpaul 928119917Swpaul /* Set the interrupt vector for the enet core */ 929119917Swpaul bfe_pci_setup(sc, BFE_INTVEC_ENET0); 930119917Swpaul 931119917Swpaul /* is core up? */ 932126470Sjulian val = CSR_READ_4(sc, BFE_SBTMSLOW) & 933126470Sjulian (BFE_RESET | BFE_REJECT | BFE_CLOCK); 934119917Swpaul if (val == BFE_CLOCK) { 935119917Swpaul /* It is, so shut it down */ 936119917Swpaul CSR_WRITE_4(sc, BFE_RCV_LAZY, 0); 937119917Swpaul CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 938119917Swpaul bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1); 939119917Swpaul CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 940133282Sdes if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK) 941126470Sjulian bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE, 942126470Sjulian 100, 0); 943119917Swpaul CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 944119917Swpaul } 945119917Swpaul 946119917Swpaul bfe_core_reset(sc); 947119917Swpaul bfe_clear_stats(sc); 948119917Swpaul 949119917Swpaul /* 950119917Swpaul * We want the phy registers to be accessible even when 951119917Swpaul * the driver is "downed" so initialize MDC preamble, frequency, 952119917Swpaul * and whether internal or external phy here. 953119917Swpaul */ 954119917Swpaul 955119917Swpaul /* 4402 has 62.5Mhz SB clock and internal phy */ 956119917Swpaul CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d); 957119917Swpaul 958119917Swpaul /* Internal or external PHY? */ 959119917Swpaul val = CSR_READ_4(sc, BFE_DEVCTRL); 960180954Syongari if (!(val & BFE_IPP)) 961119917Swpaul CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL); 962180954Syongari else if (CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) { 963119917Swpaul BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR); 964119917Swpaul DELAY(100); 965119917Swpaul } 966119917Swpaul 967133282Sdes /* Enable CRC32 generation and set proper LED modes */ 968133282Sdes BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB | BFE_CTRL_LED); 969129602Sdmlb 970133282Sdes /* Reset or clear powerdown control bit */ 971133282Sdes BFE_AND(sc, BFE_MAC_CTRL, ~BFE_CTRL_PDOWN); 972129602Sdmlb 973133282Sdes CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) & 974119917Swpaul BFE_LAZY_FC_MASK)); 975119917Swpaul 976133282Sdes /* 977126470Sjulian * We don't want lazy interrupts, so just send them at 978133282Sdes * the end of a frame, please 979119917Swpaul */ 980119917Swpaul BFE_OR(sc, BFE_RCV_LAZY, 0); 981119917Swpaul 982119917Swpaul /* Set max lengths, accounting for VLAN tags */ 983119917Swpaul CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32); 984119917Swpaul CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32); 985119917Swpaul 986119917Swpaul /* Set watermark XXX - magic */ 987119917Swpaul CSR_WRITE_4(sc, BFE_TX_WMARK, 56); 988119917Swpaul 989133282Sdes /* 990126470Sjulian * Initialise DMA channels 991133282Sdes * - not forgetting dma addresses need to be added to BFE_PCI_DMA 992119917Swpaul */ 993119917Swpaul CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE); 994119917Swpaul CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA); 995119917Swpaul 996133282Sdes CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) | 997119917Swpaul BFE_RX_CTRL_ENABLE); 998119917Swpaul CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA); 999119917Swpaul 1000119917Swpaul bfe_resetphy(sc); 1001119917Swpaul bfe_setupphy(sc); 1002119917Swpaul} 1003119917Swpaul 1004119917Swpaulstatic void 1005119917Swpaulbfe_core_disable(struct bfe_softc *sc) 1006119917Swpaul{ 1007180954Syongari if ((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET) 1008119917Swpaul return; 1009119917Swpaul 1010133282Sdes /* 1011126470Sjulian * Set reject, wait for it set, then wait for the core to stop 1012126470Sjulian * being busy, then set reset and reject and enable the clocks. 1013119917Swpaul */ 1014119917Swpaul CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK)); 1015119917Swpaul bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0); 1016119917Swpaul bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1); 1017119917Swpaul CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT | 1018119917Swpaul BFE_RESET)); 1019119917Swpaul CSR_READ_4(sc, BFE_SBTMSLOW); 1020119917Swpaul DELAY(10); 1021119917Swpaul /* Leave reset and reject set */ 1022119917Swpaul CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET)); 1023119917Swpaul DELAY(10); 1024119917Swpaul} 1025119917Swpaul 1026119917Swpaulstatic void 1027119917Swpaulbfe_core_reset(struct bfe_softc *sc) 1028119917Swpaul{ 1029119917Swpaul u_int32_t val; 1030119917Swpaul 1031119917Swpaul /* Disable the core */ 1032119917Swpaul bfe_core_disable(sc); 1033119917Swpaul 1034119917Swpaul /* and bring it back up */ 1035119917Swpaul CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC)); 1036119917Swpaul CSR_READ_4(sc, BFE_SBTMSLOW); 1037119917Swpaul DELAY(10); 1038119917Swpaul 1039119917Swpaul /* Chip bug, clear SERR, IB and TO if they are set. */ 1040119917Swpaul if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR) 1041119917Swpaul CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0); 1042119917Swpaul val = CSR_READ_4(sc, BFE_SBIMSTATE); 1043119917Swpaul if (val & (BFE_IBE | BFE_TO)) 1044119917Swpaul CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO)); 1045119917Swpaul 1046119917Swpaul /* Clear reset and allow it to move through the core */ 1047119917Swpaul CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC)); 1048119917Swpaul CSR_READ_4(sc, BFE_SBTMSLOW); 1049119917Swpaul DELAY(10); 1050119917Swpaul 1051119917Swpaul /* Leave the clock set */ 1052119917Swpaul CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK); 1053119917Swpaul CSR_READ_4(sc, BFE_SBTMSLOW); 1054119917Swpaul DELAY(10); 1055119917Swpaul} 1056119917Swpaul 1057133282Sdesstatic void 1058119917Swpaulbfe_cam_write(struct bfe_softc *sc, u_char *data, int index) 1059119917Swpaul{ 1060119917Swpaul u_int32_t val; 1061119917Swpaul 1062119917Swpaul val = ((u_int32_t) data[2]) << 24; 1063119917Swpaul val |= ((u_int32_t) data[3]) << 16; 1064119917Swpaul val |= ((u_int32_t) data[4]) << 8; 1065119917Swpaul val |= ((u_int32_t) data[5]); 1066119917Swpaul CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val); 1067119917Swpaul val = (BFE_CAM_HI_VALID | 1068119917Swpaul (((u_int32_t) data[0]) << 8) | 1069119917Swpaul (((u_int32_t) data[1]))); 1070119917Swpaul CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val); 1071119917Swpaul CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE | 1072129602Sdmlb ((u_int32_t) index << BFE_CAM_INDEX_SHIFT))); 1073119917Swpaul bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1); 1074119917Swpaul} 1075119917Swpaul 1076133282Sdesstatic void 1077119917Swpaulbfe_set_rx_mode(struct bfe_softc *sc) 1078119917Swpaul{ 1079147256Sbrooks struct ifnet *ifp = sc->bfe_ifp; 1080119917Swpaul struct ifmultiaddr *ifma; 1081119917Swpaul u_int32_t val; 1082119917Swpaul int i = 0; 1083119917Swpaul 1084181994Syongari BFE_LOCK_ASSERT(sc); 1085181994Syongari 1086119917Swpaul val = CSR_READ_4(sc, BFE_RXCONF); 1087119917Swpaul 1088119917Swpaul if (ifp->if_flags & IFF_PROMISC) 1089119917Swpaul val |= BFE_RXCONF_PROMISC; 1090119917Swpaul else 1091119917Swpaul val &= ~BFE_RXCONF_PROMISC; 1092119917Swpaul 1093119917Swpaul if (ifp->if_flags & IFF_BROADCAST) 1094119917Swpaul val &= ~BFE_RXCONF_DBCAST; 1095119917Swpaul else 1096119917Swpaul val |= BFE_RXCONF_DBCAST; 1097119917Swpaul 1098119917Swpaul 1099119917Swpaul CSR_WRITE_4(sc, BFE_CAM_CTRL, 0); 1100152315Sru bfe_cam_write(sc, IF_LLADDR(sc->bfe_ifp), i++); 1101119917Swpaul 1102119917Swpaul if (ifp->if_flags & IFF_ALLMULTI) 1103119917Swpaul val |= BFE_RXCONF_ALLMULTI; 1104119917Swpaul else { 1105119917Swpaul val &= ~BFE_RXCONF_ALLMULTI; 1106195049Srwatson if_maddr_rlock(ifp); 1107119917Swpaul TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1108119917Swpaul if (ifma->ifma_addr->sa_family != AF_LINK) 1109119917Swpaul continue; 1110126470Sjulian bfe_cam_write(sc, 1111126470Sjulian LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i++); 1112119917Swpaul } 1113195049Srwatson if_maddr_runlock(ifp); 1114119917Swpaul } 1115119917Swpaul 1116119917Swpaul CSR_WRITE_4(sc, BFE_RXCONF, val); 1117119917Swpaul BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE); 1118119917Swpaul} 1119119917Swpaul 1120119917Swpaulstatic void 1121119917Swpaulbfe_dma_map(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1122119917Swpaul{ 1123181953Syongari struct bfe_dmamap_arg *ctx; 1124119917Swpaul 1125181953Syongari if (error != 0) 1126181953Syongari return; 1127119917Swpaul 1128181953Syongari KASSERT(nseg == 1, ("%s : %d segments returned!", __func__, nseg)); 1129119917Swpaul 1130181953Syongari ctx = (struct bfe_dmamap_arg *)arg; 1131181953Syongari ctx->bfe_busaddr = segs[0].ds_addr; 1132119917Swpaul} 1133119917Swpaul 1134119917Swpaulstatic void 1135119917Swpaulbfe_release_resources(struct bfe_softc *sc) 1136119917Swpaul{ 1137119917Swpaul 1138119917Swpaul if (sc->bfe_intrhand != NULL) 1139181953Syongari bus_teardown_intr(sc->bfe_dev, sc->bfe_irq, sc->bfe_intrhand); 1140119917Swpaul 1141119917Swpaul if (sc->bfe_irq != NULL) 1142181953Syongari bus_release_resource(sc->bfe_dev, SYS_RES_IRQ, 0, sc->bfe_irq); 1143119917Swpaul 1144119917Swpaul if (sc->bfe_res != NULL) 1145181953Syongari bus_release_resource(sc->bfe_dev, SYS_RES_MEMORY, PCIR_BAR(0), 1146181953Syongari sc->bfe_res); 1147119917Swpaul 1148150215Sru if (sc->bfe_ifp != NULL) 1149150215Sru if_free(sc->bfe_ifp); 1150119917Swpaul} 1151119917Swpaul 1152119917Swpaulstatic void 1153119917Swpaulbfe_read_eeprom(struct bfe_softc *sc, u_int8_t *data) 1154119917Swpaul{ 1155119917Swpaul long i; 1156119917Swpaul u_int16_t *ptr = (u_int16_t *)data; 1157119917Swpaul 1158119917Swpaul for(i = 0; i < 128; i += 2) 1159119917Swpaul ptr[i/2] = CSR_READ_4(sc, 4096 + i); 1160119917Swpaul} 1161119917Swpaul 1162119917Swpaulstatic int 1163133282Sdesbfe_wait_bit(struct bfe_softc *sc, u_int32_t reg, u_int32_t bit, 1164119917Swpaul u_long timeout, const int clear) 1165119917Swpaul{ 1166119917Swpaul u_long i; 1167119917Swpaul 1168119917Swpaul for (i = 0; i < timeout; i++) { 1169119917Swpaul u_int32_t val = CSR_READ_4(sc, reg); 1170119917Swpaul 1171119917Swpaul if (clear && !(val & bit)) 1172119917Swpaul break; 1173119917Swpaul if (!clear && (val & bit)) 1174119917Swpaul break; 1175119917Swpaul DELAY(10); 1176119917Swpaul } 1177119917Swpaul if (i == timeout) { 1178180950Syongari device_printf(sc->bfe_dev, 1179180950Syongari "BUG! Timeout waiting for bit %08x of register " 1180180950Syongari "%x to %s.\n", bit, reg, (clear ? "clear" : "set")); 1181133282Sdes return (-1); 1182119917Swpaul } 1183133282Sdes return (0); 1184119917Swpaul} 1185119917Swpaul 1186119917Swpaulstatic int 1187119917Swpaulbfe_readphy(struct bfe_softc *sc, u_int32_t reg, u_int32_t *val) 1188119917Swpaul{ 1189133282Sdes int err; 1190119917Swpaul 1191119917Swpaul /* Clear MII ISR */ 1192119917Swpaul CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1193119917Swpaul CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1194119917Swpaul (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) | 1195119917Swpaul (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1196119917Swpaul (reg << BFE_MDIO_RA_SHIFT) | 1197119917Swpaul (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT))); 1198119917Swpaul err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1199119917Swpaul *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA; 1200119917Swpaul 1201133282Sdes return (err); 1202119917Swpaul} 1203119917Swpaul 1204119917Swpaulstatic int 1205119917Swpaulbfe_writephy(struct bfe_softc *sc, u_int32_t reg, u_int32_t val) 1206119917Swpaul{ 1207119917Swpaul int status; 1208119917Swpaul 1209119917Swpaul CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1210119917Swpaul CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1211119917Swpaul (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) | 1212119917Swpaul (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1213119917Swpaul (reg << BFE_MDIO_RA_SHIFT) | 1214119917Swpaul (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) | 1215119917Swpaul (val & BFE_MDIO_DATA_DATA))); 1216119917Swpaul status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1217119917Swpaul 1218133282Sdes return (status); 1219119917Swpaul} 1220119917Swpaul 1221133282Sdes/* 1222119917Swpaul * XXX - I think this is handled by the PHY driver, but it can't hurt to do it 1223119917Swpaul * twice 1224119917Swpaul */ 1225119917Swpaulstatic int 1226119917Swpaulbfe_setupphy(struct bfe_softc *sc) 1227119917Swpaul{ 1228119917Swpaul u_int32_t val; 1229119917Swpaul 1230119917Swpaul /* Enable activity LED */ 1231119917Swpaul bfe_readphy(sc, 26, &val); 1232133282Sdes bfe_writephy(sc, 26, val & 0x7fff); 1233119917Swpaul bfe_readphy(sc, 26, &val); 1234119917Swpaul 1235119917Swpaul /* Enable traffic meter LED mode */ 1236119917Swpaul bfe_readphy(sc, 27, &val); 1237119917Swpaul bfe_writephy(sc, 27, val | (1 << 6)); 1238119917Swpaul 1239133282Sdes return (0); 1240119917Swpaul} 1241119917Swpaul 1242133282Sdesstatic void 1243119917Swpaulbfe_stats_update(struct bfe_softc *sc) 1244119917Swpaul{ 1245181994Syongari struct bfe_hw_stats *stats; 1246181994Syongari struct ifnet *ifp; 1247181994Syongari uint32_t mib[BFE_MIB_CNT]; 1248181994Syongari uint32_t reg, *val; 1249119917Swpaul 1250181994Syongari BFE_LOCK_ASSERT(sc); 1251181994Syongari 1252181994Syongari val = mib; 1253181994Syongari CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ); 1254181994Syongari for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) 1255181994Syongari *val++ = CSR_READ_4(sc, reg); 1256181994Syongari for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) 1257181994Syongari *val++ = CSR_READ_4(sc, reg); 1258181994Syongari 1259181994Syongari ifp = sc->bfe_ifp; 1260181994Syongari stats = &sc->bfe_stats; 1261181994Syongari /* Tx stat. */ 1262181994Syongari stats->tx_good_octets += mib[MIB_TX_GOOD_O]; 1263181994Syongari stats->tx_good_frames += mib[MIB_TX_GOOD_P]; 1264181994Syongari stats->tx_octets += mib[MIB_TX_O]; 1265181994Syongari stats->tx_frames += mib[MIB_TX_P]; 1266181994Syongari stats->tx_bcast_frames += mib[MIB_TX_BCAST]; 1267181994Syongari stats->tx_mcast_frames += mib[MIB_TX_MCAST]; 1268181994Syongari stats->tx_pkts_64 += mib[MIB_TX_64]; 1269181994Syongari stats->tx_pkts_65_127 += mib[MIB_TX_65_127]; 1270181994Syongari stats->tx_pkts_128_255 += mib[MIB_TX_128_255]; 1271181994Syongari stats->tx_pkts_256_511 += mib[MIB_TX_256_511]; 1272181994Syongari stats->tx_pkts_512_1023 += mib[MIB_TX_512_1023]; 1273181994Syongari stats->tx_pkts_1024_max += mib[MIB_TX_1024_MAX]; 1274181994Syongari stats->tx_jabbers += mib[MIB_TX_JABBER]; 1275181994Syongari stats->tx_oversize_frames += mib[MIB_TX_OSIZE]; 1276181994Syongari stats->tx_frag_frames += mib[MIB_TX_FRAG]; 1277181994Syongari stats->tx_underruns += mib[MIB_TX_URUNS]; 1278181994Syongari stats->tx_colls += mib[MIB_TX_TCOLS]; 1279181994Syongari stats->tx_single_colls += mib[MIB_TX_SCOLS]; 1280181994Syongari stats->tx_multi_colls += mib[MIB_TX_MCOLS]; 1281181994Syongari stats->tx_excess_colls += mib[MIB_TX_ECOLS]; 1282181994Syongari stats->tx_late_colls += mib[MIB_TX_LCOLS]; 1283181994Syongari stats->tx_deferrals += mib[MIB_TX_DEFERED]; 1284181994Syongari stats->tx_carrier_losts += mib[MIB_TX_CLOST]; 1285181994Syongari stats->tx_pause_frames += mib[MIB_TX_PAUSE]; 1286181994Syongari /* Rx stat. */ 1287181994Syongari stats->rx_good_octets += mib[MIB_RX_GOOD_O]; 1288181994Syongari stats->rx_good_frames += mib[MIB_RX_GOOD_P]; 1289181994Syongari stats->rx_octets += mib[MIB_RX_O]; 1290181994Syongari stats->rx_frames += mib[MIB_RX_P]; 1291181994Syongari stats->rx_bcast_frames += mib[MIB_RX_BCAST]; 1292181994Syongari stats->rx_mcast_frames += mib[MIB_RX_MCAST]; 1293181994Syongari stats->rx_pkts_64 += mib[MIB_RX_64]; 1294181994Syongari stats->rx_pkts_65_127 += mib[MIB_RX_65_127]; 1295181994Syongari stats->rx_pkts_128_255 += mib[MIB_RX_128_255]; 1296181994Syongari stats->rx_pkts_256_511 += mib[MIB_RX_256_511]; 1297181994Syongari stats->rx_pkts_512_1023 += mib[MIB_RX_512_1023]; 1298181994Syongari stats->rx_pkts_1024_max += mib[MIB_RX_1024_MAX]; 1299181994Syongari stats->rx_jabbers += mib[MIB_RX_JABBER]; 1300181994Syongari stats->rx_oversize_frames += mib[MIB_RX_OSIZE]; 1301181994Syongari stats->rx_frag_frames += mib[MIB_RX_FRAG]; 1302181994Syongari stats->rx_missed_frames += mib[MIB_RX_MISS]; 1303181994Syongari stats->rx_crc_align_errs += mib[MIB_RX_CRCA]; 1304181994Syongari stats->rx_runts += mib[MIB_RX_USIZE]; 1305181994Syongari stats->rx_crc_errs += mib[MIB_RX_CRC]; 1306181994Syongari stats->rx_align_errs += mib[MIB_RX_ALIGN]; 1307181994Syongari stats->rx_symbol_errs += mib[MIB_RX_SYM]; 1308181994Syongari stats->rx_pause_frames += mib[MIB_RX_PAUSE]; 1309181994Syongari stats->rx_control_frames += mib[MIB_RX_NPAUSE]; 1310181994Syongari 1311181994Syongari /* Update counters in ifnet. */ 1312181994Syongari ifp->if_opackets += (u_long)mib[MIB_TX_GOOD_P]; 1313181994Syongari ifp->if_collisions += (u_long)mib[MIB_TX_TCOLS]; 1314181994Syongari ifp->if_oerrors += (u_long)mib[MIB_TX_URUNS] + 1315181994Syongari (u_long)mib[MIB_TX_ECOLS] + 1316181994Syongari (u_long)mib[MIB_TX_DEFERED] + 1317181994Syongari (u_long)mib[MIB_TX_CLOST]; 1318181994Syongari 1319181994Syongari ifp->if_ipackets += (u_long)mib[MIB_RX_GOOD_P]; 1320181994Syongari 1321181994Syongari ifp->if_ierrors += mib[MIB_RX_JABBER] + 1322181994Syongari mib[MIB_RX_MISS] + 1323181994Syongari mib[MIB_RX_CRCA] + 1324181994Syongari mib[MIB_RX_USIZE] + 1325181994Syongari mib[MIB_RX_CRC] + 1326181994Syongari mib[MIB_RX_ALIGN] + 1327181994Syongari mib[MIB_RX_SYM]; 1328119917Swpaul} 1329119917Swpaul 1330119917Swpaulstatic void 1331119917Swpaulbfe_txeof(struct bfe_softc *sc) 1332119917Swpaul{ 1333181953Syongari struct bfe_tx_data *r; 1334119917Swpaul struct ifnet *ifp; 1335119917Swpaul int i, chipidx; 1336119917Swpaul 1337136804Smtm BFE_LOCK_ASSERT(sc); 1338119917Swpaul 1339147256Sbrooks ifp = sc->bfe_ifp; 1340119917Swpaul 1341119917Swpaul chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK; 1342119917Swpaul chipidx /= sizeof(struct bfe_desc); 1343119917Swpaul 1344126470Sjulian i = sc->bfe_tx_cons; 1345181953Syongari if (i == chipidx) 1346181953Syongari return; 1347181953Syongari bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, 1348181953Syongari BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1349119917Swpaul /* Go through the mbufs and free those that have been transmitted */ 1350181953Syongari for (; i != chipidx; BFE_INC(i, BFE_TX_LIST_CNT)) { 1351181953Syongari r = &sc->bfe_tx_ring[i]; 1352126470Sjulian sc->bfe_tx_cnt--; 1353181953Syongari if (r->bfe_mbuf == NULL) 1354181953Syongari continue; 1355181953Syongari bus_dmamap_sync(sc->bfe_txmbuf_tag, r->bfe_map, 1356181953Syongari BUS_DMASYNC_POSTWRITE); 1357181953Syongari bus_dmamap_unload(sc->bfe_txmbuf_tag, r->bfe_map); 1358181953Syongari 1359181953Syongari m_freem(r->bfe_mbuf); 1360181953Syongari r->bfe_mbuf = NULL; 1361119917Swpaul } 1362119917Swpaul 1363180954Syongari if (i != sc->bfe_tx_cons) { 1364119917Swpaul /* we freed up some mbufs */ 1365119917Swpaul sc->bfe_tx_cons = i; 1366148887Srwatson ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1367119917Swpaul } 1368175787Syongari 1369175787Syongari if (sc->bfe_tx_cnt == 0) 1370175787Syongari sc->bfe_watchdog_timer = 0; 1371119917Swpaul} 1372119917Swpaul 1373119917Swpaul/* Pass a received packet up the stack */ 1374119917Swpaulstatic void 1375119917Swpaulbfe_rxeof(struct bfe_softc *sc) 1376119917Swpaul{ 1377119917Swpaul struct mbuf *m; 1378119917Swpaul struct ifnet *ifp; 1379119917Swpaul struct bfe_rxheader *rxheader; 1380181953Syongari struct bfe_rx_data *r; 1381181953Syongari int cons, prog; 1382119917Swpaul u_int32_t status, current, len, flags; 1383119917Swpaul 1384136804Smtm BFE_LOCK_ASSERT(sc); 1385119917Swpaul cons = sc->bfe_rx_cons; 1386119917Swpaul status = CSR_READ_4(sc, BFE_DMARX_STAT); 1387119917Swpaul current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc); 1388119917Swpaul 1389147256Sbrooks ifp = sc->bfe_ifp; 1390119917Swpaul 1391181953Syongari bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, 1392181953Syongari BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1393181953Syongari 1394181953Syongari for (prog = 0; current != cons; prog++, 1395181953Syongari BFE_INC(cons, BFE_RX_LIST_CNT)) { 1396119917Swpaul r = &sc->bfe_rx_ring[cons]; 1397119917Swpaul m = r->bfe_mbuf; 1398181953Syongari /* 1399181953Syongari * Rx status should be read from mbuf such that we can't 1400181953Syongari * delay bus_dmamap_sync(9). This hardware limiation 1401181953Syongari * results in inefficent mbuf usage as bfe(4) couldn't 1402181953Syongari * reuse mapped buffer from errored frame. 1403181953Syongari */ 1404181953Syongari if (bfe_list_newbuf(sc, cons) != 0) { 1405181953Syongari ifp->if_iqdrops++; 1406181953Syongari bfe_discard_buf(sc, cons); 1407181953Syongari continue; 1408181953Syongari } 1409119917Swpaul rxheader = mtod(m, struct bfe_rxheader*); 1410181953Syongari len = le16toh(rxheader->len); 1411181953Syongari flags = le16toh(rxheader->flags); 1412119917Swpaul 1413181953Syongari /* Remove CRC bytes. */ 1414119917Swpaul len -= ETHER_CRC_LEN; 1415119917Swpaul 1416119917Swpaul /* flag an error and try again */ 1417119917Swpaul if ((len > ETHER_MAX_LEN+32) || (flags & BFE_RX_FLAG_ERRORS)) { 1418181953Syongari m_freem(m); 1419119917Swpaul continue; 1420119917Swpaul } 1421119917Swpaul 1422181953Syongari /* Make sure to skip header bytes written by hardware. */ 1423181953Syongari m_adj(m, BFE_RX_OFFSET); 1424181953Syongari m->m_len = m->m_pkthdr.len = len; 1425119917Swpaul 1426119917Swpaul m->m_pkthdr.rcvif = ifp; 1427122689Ssam BFE_UNLOCK(sc); 1428119917Swpaul (*ifp->if_input)(ifp, m); 1429122689Ssam BFE_LOCK(sc); 1430181953Syongari } 1431119917Swpaul 1432181953Syongari if (prog > 0) { 1433181953Syongari sc->bfe_rx_cons = cons; 1434181953Syongari bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, 1435181953Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1436119917Swpaul } 1437119917Swpaul} 1438119917Swpaul 1439119917Swpaulstatic void 1440119917Swpaulbfe_intr(void *xsc) 1441119917Swpaul{ 1442119917Swpaul struct bfe_softc *sc = xsc; 1443119917Swpaul struct ifnet *ifp; 1444181994Syongari u_int32_t istat; 1445119917Swpaul 1446147256Sbrooks ifp = sc->bfe_ifp; 1447119917Swpaul 1448119917Swpaul BFE_LOCK(sc); 1449119917Swpaul 1450119917Swpaul istat = CSR_READ_4(sc, BFE_ISTAT); 1451119917Swpaul 1452133282Sdes /* 1453119917Swpaul * Defer unsolicited interrupts - This is necessary because setting the 1454119917Swpaul * chips interrupt mask register to 0 doesn't actually stop the 1455119917Swpaul * interrupts 1456119917Swpaul */ 1457181992Syongari istat &= BFE_IMASK_DEF; 1458119917Swpaul CSR_WRITE_4(sc, BFE_ISTAT, istat); 1459119917Swpaul CSR_READ_4(sc, BFE_ISTAT); 1460119917Swpaul 1461119917Swpaul /* not expecting this interrupt, disregard it */ 1462181992Syongari if (istat == 0 || (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1463119917Swpaul BFE_UNLOCK(sc); 1464119917Swpaul return; 1465119917Swpaul } 1466119917Swpaul 1467181994Syongari /* A packet was received */ 1468181994Syongari if (istat & BFE_ISTAT_RX) 1469181994Syongari bfe_rxeof(sc); 1470181994Syongari 1471181994Syongari /* A packet was sent */ 1472181994Syongari if (istat & BFE_ISTAT_TX) 1473181994Syongari bfe_txeof(sc); 1474181994Syongari 1475180954Syongari if (istat & BFE_ISTAT_ERRORS) { 1476159013Ssilby 1477159013Ssilby if (istat & BFE_ISTAT_DSCE) { 1478180950Syongari device_printf(sc->bfe_dev, "Descriptor Error\n"); 1479159013Ssilby bfe_stop(sc); 1480159013Ssilby BFE_UNLOCK(sc); 1481159013Ssilby return; 1482159013Ssilby } 1483159013Ssilby 1484159013Ssilby if (istat & BFE_ISTAT_DPE) { 1485180950Syongari device_printf(sc->bfe_dev, 1486180950Syongari "Descriptor Protocol Error\n"); 1487159013Ssilby bfe_stop(sc); 1488159013Ssilby BFE_UNLOCK(sc); 1489159013Ssilby return; 1490159013Ssilby } 1491148887Srwatson ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1492136804Smtm bfe_init_locked(sc); 1493119917Swpaul } 1494119917Swpaul 1495133282Sdes /* We have packets pending, fire them out */ 1496181992Syongari if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1497136804Smtm bfe_start_locked(ifp); 1498119917Swpaul 1499119917Swpaul BFE_UNLOCK(sc); 1500119917Swpaul} 1501119917Swpaul 1502119917Swpaulstatic int 1503181953Syongaribfe_encap(struct bfe_softc *sc, struct mbuf **m_head) 1504119917Swpaul{ 1505181953Syongari struct bfe_desc *d; 1506181953Syongari struct bfe_tx_data *r, *r1; 1507181953Syongari struct mbuf *m; 1508181953Syongari bus_dmamap_t map; 1509181953Syongari bus_dma_segment_t txsegs[BFE_MAXTXSEGS]; 1510181953Syongari uint32_t cur, si; 1511181953Syongari int error, i, nsegs; 1512119917Swpaul 1513181953Syongari BFE_LOCK_ASSERT(sc); 1514119917Swpaul 1515181953Syongari M_ASSERTPKTHDR((*m_head)); 1516119917Swpaul 1517181953Syongari si = cur = sc->bfe_tx_prod; 1518181953Syongari r = &sc->bfe_tx_ring[cur]; 1519181953Syongari error = bus_dmamap_load_mbuf_sg(sc->bfe_txmbuf_tag, r->bfe_map, *m_head, 1520181953Syongari txsegs, &nsegs, 0); 1521181953Syongari if (error == EFBIG) { 1522243857Sglebius m = m_collapse(*m_head, M_NOWAIT, BFE_MAXTXSEGS); 1523181953Syongari if (m == NULL) { 1524181953Syongari m_freem(*m_head); 1525181953Syongari *m_head = NULL; 1526181953Syongari return (ENOMEM); 1527181953Syongari } 1528158285Ssilby *m_head = m; 1529181953Syongari error = bus_dmamap_load_mbuf_sg(sc->bfe_txmbuf_tag, r->bfe_map, 1530181953Syongari *m_head, txsegs, &nsegs, 0); 1531181953Syongari if (error != 0) { 1532181953Syongari m_freem(*m_head); 1533181953Syongari *m_head = NULL; 1534181953Syongari return (error); 1535181953Syongari } 1536181953Syongari } else if (error != 0) 1537181953Syongari return (error); 1538181953Syongari if (nsegs == 0) { 1539181953Syongari m_freem(*m_head); 1540181953Syongari *m_head = NULL; 1541181953Syongari return (EIO); 1542119917Swpaul } 1543119917Swpaul 1544181953Syongari if (sc->bfe_tx_cnt + nsegs > BFE_TX_LIST_CNT - 1) { 1545181953Syongari bus_dmamap_unload(sc->bfe_txmbuf_tag, r->bfe_map); 1546181953Syongari return (ENOBUFS); 1547181953Syongari } 1548119917Swpaul 1549181953Syongari for (i = 0; i < nsegs; i++) { 1550181953Syongari d = &sc->bfe_tx_list[cur]; 1551181953Syongari d->bfe_ctrl = htole32(txsegs[i].ds_len & BFE_DESC_LEN); 1552181953Syongari d->bfe_ctrl |= htole32(BFE_DESC_IOC); 1553181953Syongari if (cur == BFE_TX_LIST_CNT - 1) 1554181953Syongari /* 1555181953Syongari * Tell the chip to wrap to the start of 1556181953Syongari * the descriptor list. 1557181953Syongari */ 1558181953Syongari d->bfe_ctrl |= htole32(BFE_DESC_EOT); 1559181953Syongari /* The chip needs all addresses to be added to BFE_PCI_DMA. */ 1560181953Syongari d->bfe_addr = htole32(BFE_ADDR_LO(txsegs[i].ds_addr) + 1561181953Syongari BFE_PCI_DMA); 1562181953Syongari BFE_INC(cur, BFE_TX_LIST_CNT); 1563181953Syongari } 1564119917Swpaul 1565181953Syongari /* Update producer index. */ 1566181953Syongari sc->bfe_tx_prod = cur; 1567119917Swpaul 1568181953Syongari /* Set EOF on the last descriptor. */ 1569181953Syongari cur = (cur + BFE_TX_LIST_CNT - 1) % BFE_TX_LIST_CNT; 1570181953Syongari d = &sc->bfe_tx_list[cur]; 1571181953Syongari d->bfe_ctrl |= htole32(BFE_DESC_EOF); 1572119917Swpaul 1573181953Syongari /* Lastly set SOF on the first descriptor to avoid races. */ 1574181953Syongari d = &sc->bfe_tx_list[si]; 1575181953Syongari d->bfe_ctrl |= htole32(BFE_DESC_SOF); 1576119917Swpaul 1577181953Syongari r1 = &sc->bfe_tx_ring[cur]; 1578181953Syongari map = r->bfe_map; 1579181953Syongari r->bfe_map = r1->bfe_map; 1580181953Syongari r1->bfe_map = map; 1581181953Syongari r1->bfe_mbuf = *m_head; 1582181953Syongari sc->bfe_tx_cnt += nsegs; 1583119917Swpaul 1584181953Syongari bus_dmamap_sync(sc->bfe_txmbuf_tag, map, BUS_DMASYNC_PREWRITE); 1585119917Swpaul 1586119917Swpaul return (0); 1587119917Swpaul} 1588119917Swpaul 1589119917Swpaul/* 1590136804Smtm * Set up to transmit a packet. 1591119917Swpaul */ 1592119917Swpaulstatic void 1593119917Swpaulbfe_start(struct ifnet *ifp) 1594119917Swpaul{ 1595136804Smtm BFE_LOCK((struct bfe_softc *)ifp->if_softc); 1596136804Smtm bfe_start_locked(ifp); 1597136804Smtm BFE_UNLOCK((struct bfe_softc *)ifp->if_softc); 1598136804Smtm} 1599136804Smtm 1600136804Smtm/* 1601136804Smtm * Set up to transmit a packet. The softc is already locked. 1602136804Smtm */ 1603136804Smtmstatic void 1604136804Smtmbfe_start_locked(struct ifnet *ifp) 1605136804Smtm{ 1606119917Swpaul struct bfe_softc *sc; 1607181953Syongari struct mbuf *m_head; 1608181953Syongari int queued; 1609119917Swpaul 1610119917Swpaul sc = ifp->if_softc; 1611119917Swpaul 1612136804Smtm BFE_LOCK_ASSERT(sc); 1613119917Swpaul 1614133282Sdes /* 1615126470Sjulian * Not much point trying to send if the link is down 1616126470Sjulian * or we have nothing to send. 1617119917Swpaul */ 1618175787Syongari if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1619181976Syongari IFF_DRV_RUNNING || (sc->bfe_flags & BFE_FLAG_LINK) == 0) 1620119917Swpaul return; 1621119917Swpaul 1622181953Syongari for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 1623181953Syongari sc->bfe_tx_cnt < BFE_TX_LIST_CNT - 1;) { 1624131455Smlaier IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1625180954Syongari if (m_head == NULL) 1626119917Swpaul break; 1627119917Swpaul 1628133282Sdes /* 1629126470Sjulian * Pack the data into the tx ring. If we dont have 1630126470Sjulian * enough room, let the chip drain the ring. 1631119917Swpaul */ 1632181953Syongari if (bfe_encap(sc, &m_head)) { 1633181953Syongari if (m_head == NULL) 1634181953Syongari break; 1635131455Smlaier IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1636148887Srwatson ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1637119917Swpaul break; 1638119917Swpaul } 1639119917Swpaul 1640136269Smlaier queued++; 1641136269Smlaier 1642119917Swpaul /* 1643119917Swpaul * If there's a BPF listener, bounce a copy of this frame 1644119917Swpaul * to him. 1645119917Swpaul */ 1646119917Swpaul BPF_MTAP(ifp, m_head); 1647119917Swpaul } 1648119917Swpaul 1649136269Smlaier if (queued) { 1650181953Syongari bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, 1651181953Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1652136269Smlaier /* Transmit - twice due to apparent hardware bug */ 1653181953Syongari CSR_WRITE_4(sc, BFE_DMATX_PTR, 1654181953Syongari sc->bfe_tx_prod * sizeof(struct bfe_desc)); 1655181953Syongari /* 1656181953Syongari * XXX It seems the following write is not necessary 1657181953Syongari * to kick Tx command. What might be required would be 1658181953Syongari * a way flushing PCI posted write. Reading the register 1659181953Syongari * back ensures the flush operation. In addition, 1660181953Syongari * hardware will execute PCI posted write in the long 1661181953Syongari * run and watchdog timer for the kick command was set 1662181953Syongari * to 5 seconds. Therefore I think the second write 1663181953Syongari * access is not necessary or could be replaced with 1664181953Syongari * read operation. 1665181953Syongari */ 1666181953Syongari CSR_WRITE_4(sc, BFE_DMATX_PTR, 1667181953Syongari sc->bfe_tx_prod * sizeof(struct bfe_desc)); 1668119917Swpaul 1669136269Smlaier /* 1670136269Smlaier * Set a timeout in case the chip goes out to lunch. 1671136269Smlaier */ 1672175787Syongari sc->bfe_watchdog_timer = 5; 1673136269Smlaier } 1674119917Swpaul} 1675119917Swpaul 1676119917Swpaulstatic void 1677119917Swpaulbfe_init(void *xsc) 1678119917Swpaul{ 1679136804Smtm BFE_LOCK((struct bfe_softc *)xsc); 1680136804Smtm bfe_init_locked(xsc); 1681136804Smtm BFE_UNLOCK((struct bfe_softc *)xsc); 1682136804Smtm} 1683136804Smtm 1684136804Smtmstatic void 1685136804Smtmbfe_init_locked(void *xsc) 1686136804Smtm{ 1687119917Swpaul struct bfe_softc *sc = (struct bfe_softc*)xsc; 1688147256Sbrooks struct ifnet *ifp = sc->bfe_ifp; 1689175787Syongari struct mii_data *mii; 1690119917Swpaul 1691136804Smtm BFE_LOCK_ASSERT(sc); 1692119917Swpaul 1693175787Syongari mii = device_get_softc(sc->bfe_miibus); 1694175787Syongari 1695148887Srwatson if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1696119917Swpaul return; 1697119917Swpaul 1698119917Swpaul bfe_stop(sc); 1699119917Swpaul bfe_chip_reset(sc); 1700119917Swpaul 1701119917Swpaul if (bfe_list_rx_init(sc) == ENOBUFS) { 1702180950Syongari device_printf(sc->bfe_dev, 1703180950Syongari "%s: Not enough memory for list buffers\n", __func__); 1704119917Swpaul bfe_stop(sc); 1705119917Swpaul return; 1706119917Swpaul } 1707181953Syongari bfe_list_tx_init(sc); 1708119917Swpaul 1709119917Swpaul bfe_set_rx_mode(sc); 1710119917Swpaul 1711119917Swpaul /* Enable the chip and core */ 1712119917Swpaul BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE); 1713119917Swpaul /* Enable interrupts */ 1714119917Swpaul CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF); 1715119917Swpaul 1716175787Syongari /* Clear link state and change media. */ 1717181976Syongari sc->bfe_flags &= ~BFE_FLAG_LINK; 1718175787Syongari mii_mediachg(mii); 1719175787Syongari 1720148887Srwatson ifp->if_drv_flags |= IFF_DRV_RUNNING; 1721148887Srwatson ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1722119917Swpaul 1723175787Syongari callout_reset(&sc->bfe_stat_co, hz, bfe_tick, sc); 1724119917Swpaul} 1725119917Swpaul 1726119917Swpaul/* 1727119917Swpaul * Set media options. 1728119917Swpaul */ 1729119917Swpaulstatic int 1730119917Swpaulbfe_ifmedia_upd(struct ifnet *ifp) 1731119917Swpaul{ 1732119917Swpaul struct bfe_softc *sc; 1733119917Swpaul struct mii_data *mii; 1734221407Smarius struct mii_softc *miisc; 1735175787Syongari int error; 1736119917Swpaul 1737119917Swpaul sc = ifp->if_softc; 1738175787Syongari BFE_LOCK(sc); 1739119917Swpaul 1740119917Swpaul mii = device_get_softc(sc->bfe_miibus); 1741221407Smarius LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1742221407Smarius PHY_RESET(miisc); 1743175787Syongari error = mii_mediachg(mii); 1744175787Syongari BFE_UNLOCK(sc); 1745119917Swpaul 1746175787Syongari return (error); 1747119917Swpaul} 1748119917Swpaul 1749119917Swpaul/* 1750119917Swpaul * Report current media status. 1751119917Swpaul */ 1752119917Swpaulstatic void 1753119917Swpaulbfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1754119917Swpaul{ 1755119917Swpaul struct bfe_softc *sc = ifp->if_softc; 1756119917Swpaul struct mii_data *mii; 1757119917Swpaul 1758175787Syongari BFE_LOCK(sc); 1759119917Swpaul mii = device_get_softc(sc->bfe_miibus); 1760119917Swpaul mii_pollstat(mii); 1761119917Swpaul ifmr->ifm_active = mii->mii_media_active; 1762119917Swpaul ifmr->ifm_status = mii->mii_media_status; 1763175787Syongari BFE_UNLOCK(sc); 1764119917Swpaul} 1765119917Swpaul 1766119917Swpaulstatic int 1767119917Swpaulbfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1768119917Swpaul{ 1769119917Swpaul struct bfe_softc *sc = ifp->if_softc; 1770119917Swpaul struct ifreq *ifr = (struct ifreq *) data; 1771119917Swpaul struct mii_data *mii; 1772119917Swpaul int error = 0; 1773119917Swpaul 1774180954Syongari switch (command) { 1775180954Syongari case SIOCSIFFLAGS: 1776180954Syongari BFE_LOCK(sc); 1777181976Syongari if (ifp->if_flags & IFF_UP) { 1778180954Syongari if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1779119917Swpaul bfe_set_rx_mode(sc); 1780181976Syongari else if ((sc->bfe_flags & BFE_FLAG_DETACH) == 0) 1781180954Syongari bfe_init_locked(sc); 1782181976Syongari } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1783180954Syongari bfe_stop(sc); 1784180954Syongari BFE_UNLOCK(sc); 1785180954Syongari break; 1786180954Syongari case SIOCADDMULTI: 1787180954Syongari case SIOCDELMULTI: 1788180954Syongari BFE_LOCK(sc); 1789180954Syongari if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1790180954Syongari bfe_set_rx_mode(sc); 1791180954Syongari BFE_UNLOCK(sc); 1792180954Syongari break; 1793180954Syongari case SIOCGIFMEDIA: 1794180954Syongari case SIOCSIFMEDIA: 1795180954Syongari mii = device_get_softc(sc->bfe_miibus); 1796180954Syongari error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1797180954Syongari break; 1798180954Syongari default: 1799180954Syongari error = ether_ioctl(ifp, command, data); 1800180954Syongari break; 1801119917Swpaul } 1802119917Swpaul 1803133282Sdes return (error); 1804119917Swpaul} 1805119917Swpaul 1806119917Swpaulstatic void 1807175787Syongaribfe_watchdog(struct bfe_softc *sc) 1808119917Swpaul{ 1809175787Syongari struct ifnet *ifp; 1810119917Swpaul 1811175787Syongari BFE_LOCK_ASSERT(sc); 1812119917Swpaul 1813175787Syongari if (sc->bfe_watchdog_timer == 0 || --sc->bfe_watchdog_timer) 1814175787Syongari return; 1815119917Swpaul 1816175787Syongari ifp = sc->bfe_ifp; 1817175787Syongari 1818180950Syongari device_printf(sc->bfe_dev, "watchdog timeout -- resetting\n"); 1819119917Swpaul 1820175787Syongari ifp->if_oerrors++; 1821148887Srwatson ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1822136804Smtm bfe_init_locked(sc); 1823119917Swpaul 1824175787Syongari if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1825175787Syongari bfe_start_locked(ifp); 1826119917Swpaul} 1827119917Swpaul 1828119917Swpaulstatic void 1829119917Swpaulbfe_tick(void *xsc) 1830119917Swpaul{ 1831119917Swpaul struct bfe_softc *sc = xsc; 1832119917Swpaul struct mii_data *mii; 1833119917Swpaul 1834175787Syongari BFE_LOCK_ASSERT(sc); 1835119917Swpaul 1836119917Swpaul mii = device_get_softc(sc->bfe_miibus); 1837175787Syongari mii_tick(mii); 1838119917Swpaul bfe_stats_update(sc); 1839175787Syongari bfe_watchdog(sc); 1840175787Syongari callout_reset(&sc->bfe_stat_co, hz, bfe_tick, sc); 1841119917Swpaul} 1842119917Swpaul 1843119917Swpaul/* 1844119917Swpaul * Stop the adapter and free any mbufs allocated to the 1845119917Swpaul * RX and TX lists. 1846119917Swpaul */ 1847119917Swpaulstatic void 1848119917Swpaulbfe_stop(struct bfe_softc *sc) 1849119917Swpaul{ 1850119917Swpaul struct ifnet *ifp; 1851119917Swpaul 1852136804Smtm BFE_LOCK_ASSERT(sc); 1853119917Swpaul 1854147256Sbrooks ifp = sc->bfe_ifp; 1855175787Syongari ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1856181976Syongari sc->bfe_flags &= ~BFE_FLAG_LINK; 1857175787Syongari callout_stop(&sc->bfe_stat_co); 1858175787Syongari sc->bfe_watchdog_timer = 0; 1859119917Swpaul 1860119917Swpaul bfe_chip_halt(sc); 1861126470Sjulian bfe_tx_ring_free(sc); 1862119917Swpaul bfe_rx_ring_free(sc); 1863119917Swpaul} 1864181994Syongari 1865181994Syongaristatic int 1866181994Syongarisysctl_bfe_stats(SYSCTL_HANDLER_ARGS) 1867181994Syongari{ 1868181994Syongari struct bfe_softc *sc; 1869181994Syongari struct bfe_hw_stats *stats; 1870181994Syongari int error, result; 1871181994Syongari 1872181994Syongari result = -1; 1873181994Syongari error = sysctl_handle_int(oidp, &result, 0, req); 1874181994Syongari 1875181994Syongari if (error != 0 || req->newptr == NULL) 1876181994Syongari return (error); 1877181994Syongari 1878181994Syongari if (result != 1) 1879181994Syongari return (error); 1880181994Syongari 1881181994Syongari sc = (struct bfe_softc *)arg1; 1882181994Syongari stats = &sc->bfe_stats; 1883181994Syongari 1884181994Syongari printf("%s statistics:\n", device_get_nameunit(sc->bfe_dev)); 1885181994Syongari printf("Transmit good octets : %ju\n", 1886181994Syongari (uintmax_t)stats->tx_good_octets); 1887181994Syongari printf("Transmit good frames : %ju\n", 1888181994Syongari (uintmax_t)stats->tx_good_frames); 1889181994Syongari printf("Transmit octets : %ju\n", 1890181994Syongari (uintmax_t)stats->tx_octets); 1891181994Syongari printf("Transmit frames : %ju\n", 1892181994Syongari (uintmax_t)stats->tx_frames); 1893181994Syongari printf("Transmit broadcast frames : %ju\n", 1894181994Syongari (uintmax_t)stats->tx_bcast_frames); 1895181994Syongari printf("Transmit multicast frames : %ju\n", 1896181994Syongari (uintmax_t)stats->tx_mcast_frames); 1897181994Syongari printf("Transmit frames 64 bytes : %ju\n", 1898181994Syongari (uint64_t)stats->tx_pkts_64); 1899181994Syongari printf("Transmit frames 65 to 127 bytes : %ju\n", 1900181994Syongari (uint64_t)stats->tx_pkts_65_127); 1901181994Syongari printf("Transmit frames 128 to 255 bytes : %ju\n", 1902181994Syongari (uint64_t)stats->tx_pkts_128_255); 1903181994Syongari printf("Transmit frames 256 to 511 bytes : %ju\n", 1904181994Syongari (uint64_t)stats->tx_pkts_256_511); 1905181994Syongari printf("Transmit frames 512 to 1023 bytes : %ju\n", 1906181994Syongari (uint64_t)stats->tx_pkts_512_1023); 1907181994Syongari printf("Transmit frames 1024 to max bytes : %ju\n", 1908181994Syongari (uint64_t)stats->tx_pkts_1024_max); 1909181994Syongari printf("Transmit jabber errors : %u\n", stats->tx_jabbers); 1910181994Syongari printf("Transmit oversized frames : %ju\n", 1911181994Syongari (uint64_t)stats->tx_oversize_frames); 1912181994Syongari printf("Transmit fragmented frames : %ju\n", 1913181994Syongari (uint64_t)stats->tx_frag_frames); 1914181994Syongari printf("Transmit underruns : %u\n", stats->tx_colls); 1915181994Syongari printf("Transmit total collisions : %u\n", stats->tx_single_colls); 1916181994Syongari printf("Transmit single collisions : %u\n", stats->tx_single_colls); 1917181994Syongari printf("Transmit multiple collisions : %u\n", stats->tx_multi_colls); 1918181994Syongari printf("Transmit excess collisions : %u\n", stats->tx_excess_colls); 1919181994Syongari printf("Transmit late collisions : %u\n", stats->tx_late_colls); 1920181994Syongari printf("Transmit deferrals : %u\n", stats->tx_deferrals); 1921181994Syongari printf("Transmit carrier losts : %u\n", stats->tx_carrier_losts); 1922181994Syongari printf("Transmit pause frames : %u\n", stats->tx_pause_frames); 1923181994Syongari 1924181994Syongari printf("Receive good octets : %ju\n", 1925181994Syongari (uintmax_t)stats->rx_good_octets); 1926181994Syongari printf("Receive good frames : %ju\n", 1927181994Syongari (uintmax_t)stats->rx_good_frames); 1928181994Syongari printf("Receive octets : %ju\n", 1929181994Syongari (uintmax_t)stats->rx_octets); 1930181994Syongari printf("Receive frames : %ju\n", 1931181994Syongari (uintmax_t)stats->rx_frames); 1932181994Syongari printf("Receive broadcast frames : %ju\n", 1933181994Syongari (uintmax_t)stats->rx_bcast_frames); 1934181994Syongari printf("Receive multicast frames : %ju\n", 1935181994Syongari (uintmax_t)stats->rx_mcast_frames); 1936181994Syongari printf("Receive frames 64 bytes : %ju\n", 1937181994Syongari (uint64_t)stats->rx_pkts_64); 1938181994Syongari printf("Receive frames 65 to 127 bytes : %ju\n", 1939181994Syongari (uint64_t)stats->rx_pkts_65_127); 1940181994Syongari printf("Receive frames 128 to 255 bytes : %ju\n", 1941181994Syongari (uint64_t)stats->rx_pkts_128_255); 1942181994Syongari printf("Receive frames 256 to 511 bytes : %ju\n", 1943181994Syongari (uint64_t)stats->rx_pkts_256_511); 1944181994Syongari printf("Receive frames 512 to 1023 bytes : %ju\n", 1945181994Syongari (uint64_t)stats->rx_pkts_512_1023); 1946181994Syongari printf("Receive frames 1024 to max bytes : %ju\n", 1947181994Syongari (uint64_t)stats->rx_pkts_1024_max); 1948181994Syongari printf("Receive jabber errors : %u\n", stats->rx_jabbers); 1949181994Syongari printf("Receive oversized frames : %ju\n", 1950181994Syongari (uint64_t)stats->rx_oversize_frames); 1951181994Syongari printf("Receive fragmented frames : %ju\n", 1952181994Syongari (uint64_t)stats->rx_frag_frames); 1953181994Syongari printf("Receive missed frames : %u\n", stats->rx_missed_frames); 1954181994Syongari printf("Receive CRC align errors : %u\n", stats->rx_crc_align_errs); 1955181994Syongari printf("Receive undersized frames : %u\n", stats->rx_runts); 1956181994Syongari printf("Receive CRC errors : %u\n", stats->rx_crc_errs); 1957181994Syongari printf("Receive align errors : %u\n", stats->rx_align_errs); 1958181994Syongari printf("Receive symbol errors : %u\n", stats->rx_symbol_errs); 1959181994Syongari printf("Receive pause frames : %u\n", stats->rx_pause_frames); 1960181994Syongari printf("Receive control frames : %u\n", stats->rx_control_frames); 1961181994Syongari 1962181994Syongari return (error); 1963181994Syongari} 1964