if_bfe.c revision 119917
1/* 2 * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk> 3 * and Duncan Barclay<dmlb@dmlb.org> 4 */ 5 6/* 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: head/sys/dev/bfe/if_bfe.c 119917 2003-09-09 18:17:23Z wpaul $"); 32 33#include <sys/param.h> 34#include <sys/systm.h> 35#include <sys/sockio.h> 36#include <sys/mbuf.h> 37#include <sys/malloc.h> 38#include <sys/kernel.h> 39#include <sys/socket.h> 40#include <sys/queue.h> 41 42#include <net/if.h> 43#include <net/if_arp.h> 44#include <net/ethernet.h> 45#include <net/if_dl.h> 46#include <net/if_media.h> 47 48#include <net/bpf.h> 49 50#include <net/if_types.h> 51#include <net/if_vlan_var.h> 52 53#include <netinet/in_systm.h> 54#include <netinet/in.h> 55#include <netinet/ip.h> 56 57#include <machine/clock.h> /* for DELAY */ 58#include <machine/bus_memio.h> 59#include <machine/bus.h> 60#include <machine/resource.h> 61#include <sys/bus.h> 62#include <sys/rman.h> 63 64#include <dev/mii/mii.h> 65#include <dev/mii/miivar.h> 66#include "miidevs.h" 67#include <dev/mii/brgphyreg.h> 68 69#include <dev/pci/pcireg.h> 70#include <dev/pci/pcivar.h> 71 72#include <dev/bfe/if_bfereg.h> 73 74MODULE_DEPEND(bfe, pci, 1, 1, 1); 75MODULE_DEPEND(bfe, ether, 1, 1, 1); 76MODULE_DEPEND(bfe, miibus, 1, 1, 1); 77 78/* "controller miibus0" required. See GENERIC if you get errors here. */ 79#include "miibus_if.h" 80 81#define BFE_DEVDESC_MAX 64 /* Maximum device description length */ 82 83static struct bfe_type bfe_devs[] = { 84 { BCOM_VENDORID, BCOM_DEVICEID_BCM4401, 85 "Broadcom BCM4401 Fast Ethernet" }, 86 { 0, 0, NULL } 87}; 88 89static int bfe_probe (device_t); 90static int bfe_attach (device_t); 91static int bfe_detach (device_t); 92static void bfe_release_resources (struct bfe_softc *); 93static void bfe_intr (void *); 94static void bfe_start (struct ifnet *); 95static int bfe_ioctl (struct ifnet *, u_long, caddr_t); 96static void bfe_init (void *); 97static void bfe_stop (struct bfe_softc *); 98static void bfe_watchdog (struct ifnet *); 99static void bfe_shutdown (device_t); 100static void bfe_tick (void *); 101static void bfe_txeof (struct bfe_softc *); 102static void bfe_rxeof (struct bfe_softc *); 103static void bfe_set_rx_mode (struct bfe_softc *); 104static int bfe_list_rx_init (struct bfe_softc *); 105static int bfe_list_newbuf (struct bfe_softc *, int, struct mbuf*); 106static void bfe_rx_ring_free (struct bfe_softc *); 107 108static void bfe_pci_setup (struct bfe_softc *, u_int32_t); 109static int bfe_ifmedia_upd (struct ifnet *); 110static void bfe_ifmedia_sts (struct ifnet *, struct ifmediareq *); 111static int bfe_miibus_readreg (device_t, int, int); 112static int bfe_miibus_writereg (device_t, int, int, int); 113static void bfe_miibus_statchg (device_t); 114static int bfe_wait_bit (struct bfe_softc *, u_int32_t, u_int32_t, 115 u_long, const int); 116static void bfe_get_config (struct bfe_softc *sc); 117static void bfe_read_eeprom (struct bfe_softc *, u_int8_t *); 118static void bfe_stats_update (struct bfe_softc *); 119static void bfe_clear_stats (struct bfe_softc *); 120static int bfe_readphy (struct bfe_softc *, u_int32_t, u_int32_t*); 121static int bfe_writephy (struct bfe_softc *, u_int32_t, u_int32_t); 122static int bfe_resetphy (struct bfe_softc *); 123static int bfe_setupphy (struct bfe_softc *); 124static void bfe_chip_reset (struct bfe_softc *); 125static void bfe_chip_halt (struct bfe_softc *); 126static void bfe_core_reset (struct bfe_softc *); 127static void bfe_core_disable (struct bfe_softc *); 128static int bfe_dma_alloc (device_t); 129static void bfe_dma_map_desc (void *, bus_dma_segment_t *, int, int); 130static void bfe_dma_map (void *, bus_dma_segment_t *, int, int); 131static void bfe_cam_write (struct bfe_softc *, u_char *, int); 132 133static device_method_t bfe_methods[] = { 134 /* Device interface */ 135 DEVMETHOD(device_probe, bfe_probe), 136 DEVMETHOD(device_attach, bfe_attach), 137 DEVMETHOD(device_detach, bfe_detach), 138 DEVMETHOD(device_shutdown, bfe_shutdown), 139 140 /* bus interface */ 141 DEVMETHOD(bus_print_child, bus_generic_print_child), 142 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 143 144 /* MII interface */ 145 DEVMETHOD(miibus_readreg, bfe_miibus_readreg), 146 DEVMETHOD(miibus_writereg, bfe_miibus_writereg), 147 DEVMETHOD(miibus_statchg, bfe_miibus_statchg), 148 149 { 0, 0 } 150}; 151 152static driver_t bfe_driver = { 153 "bfe", 154 bfe_methods, 155 sizeof(struct bfe_softc) 156}; 157 158static devclass_t bfe_devclass; 159 160DRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, 0, 0); 161DRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, 0, 0); 162 163/* 164 * Probe for a Broadcom 4401 chip. 165 */ 166static int 167bfe_probe(device_t dev) 168{ 169 struct bfe_type *t; 170 struct bfe_softc *sc; 171 172 t = bfe_devs; 173 174 sc = device_get_softc(dev); 175 bzero(sc, sizeof(struct bfe_softc)); 176 sc->bfe_unit = device_get_unit(dev); 177 sc->bfe_dev = dev; 178 179 while(t->bfe_name != NULL) { 180 if ((pci_get_vendor(dev) == t->bfe_vid) && 181 (pci_get_device(dev) == t->bfe_did)) { 182 device_set_desc_copy(dev, t->bfe_name); 183 return(0); 184 } 185 t++; 186 } 187 188 return(ENXIO); 189} 190 191static int 192bfe_dma_alloc(device_t dev) 193{ 194 struct bfe_softc *sc; 195 int error, i; 196 197 sc = device_get_softc(dev); 198 199 /* parent tag */ 200 error = bus_dma_tag_create(NULL, /* parent */ 201 PAGE_SIZE, 0, /* alignment, boundary */ 202 BUS_SPACE_MAXADDR, /* lowaddr */ 203 BUS_SPACE_MAXADDR_32BIT, /* highaddr */ 204 NULL, NULL, /* filter, filterarg */ 205 MAXBSIZE, /* maxsize */ 206 BUS_SPACE_UNRESTRICTED, /* num of segments */ 207 BUS_SPACE_MAXSIZE_32BIT, /* max segment size */ 208 BUS_DMA_ALLOCNOW, /* flags */ 209 NULL, NULL, /* lockfunc, lockarg */ 210 &sc->bfe_parent_tag); 211 212 /* tag for TX ring */ 213 error = bus_dma_tag_create(sc->bfe_parent_tag, BFE_TX_LIST_SIZE, 214 BFE_TX_LIST_SIZE, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 215 NULL, NULL, BFE_TX_LIST_SIZE, 1, BUS_SPACE_MAXSIZE_32BIT, 216 0, NULL, NULL, &sc->bfe_tx_tag); 217 218 if (error) { 219 device_printf(dev, "could not allocate dma tag\n"); 220 return(ENOMEM); 221 } 222 223 /* tag for RX ring */ 224 error = bus_dma_tag_create(sc->bfe_parent_tag, BFE_RX_LIST_SIZE, 225 BFE_RX_LIST_SIZE, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 226 NULL, NULL, BFE_RX_LIST_SIZE, 1, BUS_SPACE_MAXSIZE_32BIT, 227 0, NULL, NULL, &sc->bfe_rx_tag); 228 229 if (error) { 230 device_printf(dev, "could not allocate dma tag\n"); 231 return(ENOMEM); 232 } 233 234 /* tag for mbufs */ 235 error = bus_dma_tag_create(sc->bfe_parent_tag, ETHER_ALIGN, 0, 236 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 237 1, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, &sc->bfe_tag); 238 239 if (error) { 240 device_printf(dev, "could not allocate dma tag\n"); 241 return(ENOMEM); 242 } 243 244 /* pre allocate dmamaps for RX list */ 245 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 246 error = bus_dmamap_create(sc->bfe_tag, 0, &sc->bfe_rx_ring[i].bfe_map); 247 if (error) { 248 device_printf(dev, "cannot create DMA map for RX\n"); 249 return(ENOMEM); 250 } 251 } 252 253 /* pre allocate dmamaps for TX list */ 254 for (i = 0; i < BFE_TX_LIST_CNT; i++) { 255 error = bus_dmamap_create(sc->bfe_tag, 0, &sc->bfe_tx_ring[i].bfe_map); 256 if (error) { 257 device_printf(dev, "cannot create DMA map for TX\n"); 258 return(ENOMEM); 259 } 260 } 261 262 /* Alloc dma for rx ring */ 263 error = bus_dmamem_alloc(sc->bfe_rx_tag, (void *)&sc->bfe_rx_list, 264 BUS_DMA_NOWAIT, &sc->bfe_rx_map); 265 266 if(error) 267 return(ENOMEM); 268 269 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 270 error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map, 271 sc->bfe_rx_list, sizeof(struct bfe_desc), 272 bfe_dma_map, &sc->bfe_rx_dma, 0); 273 274 if(error) 275 return(ENOMEM); 276 277 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 278 279 error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list, 280 BUS_DMA_NOWAIT, &sc->bfe_tx_map); 281 if (error) 282 return(ENOMEM); 283 284 285 error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map, 286 sc->bfe_tx_list, sizeof(struct bfe_desc), 287 bfe_dma_map, &sc->bfe_tx_dma, 0); 288 if(error) 289 return(ENOMEM); 290 291 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 292 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 293 294 return(0); 295} 296 297static int 298bfe_attach(device_t dev) 299{ 300 struct ifnet *ifp; 301 struct bfe_softc *sc; 302 int unit, error = 0, rid; 303 304 sc = device_get_softc(dev); 305 mtx_init(&sc->bfe_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 306 MTX_DEF | MTX_RECURSE); 307 308 unit = device_get_unit(dev); 309 sc->bfe_dev = dev; 310 sc->bfe_unit = unit; 311 312 /* 313 * Handle power management nonsense. 314 */ 315 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 316 u_int32_t membase, irq; 317 318 /* Save important PCI config data. */ 319 membase = pci_read_config(dev, BFE_PCI_MEMLO, 4); 320 irq = pci_read_config(dev, BFE_PCI_INTLINE, 4); 321 322 /* Reset the power state. */ 323 printf("bfe%d: chip is is in D%d power mode -- setting to D0\n", 324 sc->bfe_unit, pci_get_powerstate(dev)); 325 326 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 327 328 /* Restore PCI config data. */ 329 pci_write_config(dev, BFE_PCI_MEMLO, membase, 4); 330 pci_write_config(dev, BFE_PCI_INTLINE, irq, 4); 331 } 332 333 /* 334 * Map control/status registers. 335 */ 336 pci_enable_busmaster(dev); 337 338 rid = BFE_PCI_MEMLO; 339 sc->bfe_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 0, ~0, 1, 340 RF_ACTIVE); 341 if (sc->bfe_res == NULL) { 342 printf ("bfe%d: couldn't map memory\n", unit); 343 error = ENXIO; 344 goto fail; 345 } 346 347 sc->bfe_btag = rman_get_bustag(sc->bfe_res); 348 sc->bfe_bhandle = rman_get_bushandle(sc->bfe_res); 349 sc->bfe_vhandle = (vm_offset_t)rman_get_virtual(sc->bfe_res); 350 351 /* Allocate interrupt */ 352 rid = 0; 353 354 sc->bfe_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 355 RF_SHAREABLE | RF_ACTIVE); 356 if (sc->bfe_irq == NULL) { 357 printf("bfe%d: couldn't map interrupt\n", unit); 358 error = ENXIO; 359 goto fail; 360 } 361 362 if (bfe_dma_alloc(dev)) { 363 printf("bfe%d: failed to allocate DMA resources\n", sc->bfe_unit); 364 bfe_release_resources(sc); 365 error = ENXIO; 366 goto fail; 367 } 368 369 /* Set up ifnet structure */ 370 ifp = &sc->arpcom.ac_if; 371 ifp->if_softc = sc; 372 ifp->if_unit = sc->bfe_unit; 373 ifp->if_name = "bfe"; 374 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 375 ifp->if_ioctl = bfe_ioctl; 376 ifp->if_output = ether_output; 377 ifp->if_start = bfe_start; 378 ifp->if_watchdog = bfe_watchdog; 379 ifp->if_init = bfe_init; 380 ifp->if_mtu = ETHERMTU; 381 ifp->if_baudrate = 10000000; 382 ifp->if_snd.ifq_maxlen = BFE_TX_QLEN; 383 384 bfe_get_config(sc); 385 386 printf("bfe%d: Ethernet address: %6D\n", unit, sc->arpcom.ac_enaddr, ":"); 387 388 /* Reset the chip and turn on the PHY */ 389 bfe_chip_reset(sc); 390 391 if (mii_phy_probe(dev, &sc->bfe_miibus, 392 bfe_ifmedia_upd, bfe_ifmedia_sts)) { 393 printf("bfe%d: MII without any PHY!\n", sc->bfe_unit); 394 error = ENXIO; 395 goto fail; 396 } 397 398 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 399 callout_handle_init(&sc->bfe_stat_ch); 400 401 /* 402 * Hook interrupt last to avoid having to lock softc 403 */ 404 error = bus_setup_intr(dev, sc->bfe_irq, INTR_TYPE_NET, 405 bfe_intr, sc, &sc->bfe_intrhand); 406 407 if (error) { 408 bfe_release_resources(sc); 409 printf("bfe%d: couldn't set up irq\n", unit); 410 goto fail; 411 } 412fail: 413 if(error) 414 bfe_release_resources(sc); 415 return(error); 416} 417 418static int 419bfe_detach(device_t dev) 420{ 421 struct bfe_softc *sc; 422 struct ifnet *ifp; 423 424 sc = device_get_softc(dev); 425 426 KASSERT(mtx_initialized(&sc->bfe_mtx), ("bfe mutex not initialized")); 427 BFE_LOCK(scp); 428 429 ifp = &sc->arpcom.ac_if; 430 431 if (device_is_attached(dev)) { 432 bfe_stop(sc); 433 ether_ifdetach(ifp); 434 } 435 436 bfe_chip_reset(sc); 437 438 bus_generic_detach(dev); 439 if(sc->bfe_miibus != NULL) 440 device_delete_child(dev, sc->bfe_miibus); 441 442 bfe_release_resources(sc); 443 BFE_UNLOCK(sc); 444 mtx_destroy(&sc->bfe_mtx); 445 446 return(0); 447} 448 449/* 450 * Stop all chip I/O so that the kernel's probe routines don't 451 * get confused by errant DMAs when rebooting. 452 */ 453static void 454bfe_shutdown(device_t dev) 455{ 456 struct bfe_softc *sc; 457 458 sc = device_get_softc(dev); 459 BFE_LOCK(sc); 460 bfe_stop(sc); 461 462 BFE_UNLOCK(sc); 463 return; 464} 465 466static int 467bfe_miibus_readreg(device_t dev, int phy, int reg) 468{ 469 struct bfe_softc *sc; 470 u_int32_t ret; 471 472 sc = device_get_softc(dev); 473 if(phy != sc->bfe_phyaddr) 474 return(0); 475 bfe_readphy(sc, reg, &ret); 476 477 return(ret); 478} 479 480static int 481bfe_miibus_writereg(device_t dev, int phy, int reg, int val) 482{ 483 struct bfe_softc *sc; 484 485 sc = device_get_softc(dev); 486 if(phy != sc->bfe_phyaddr) 487 return(0); 488 bfe_writephy(sc, reg, val); 489 490 return(0); 491} 492 493static void 494bfe_miibus_statchg(device_t dev) 495{ 496 return; 497} 498 499static void 500bfe_tx_ring_free(struct bfe_softc *sc) 501{ 502 int i; 503 504 for(i = 0; i < BFE_TX_LIST_CNT; i++) { 505 if(sc->bfe_tx_ring[i].bfe_mbuf != NULL) { 506 m_freem(sc->bfe_tx_ring[i].bfe_mbuf); 507 sc->bfe_tx_ring[i].bfe_mbuf = NULL; 508 bus_dmamap_unload(sc->bfe_tag, 509 sc->bfe_tx_ring[i].bfe_map); 510 bus_dmamap_destroy(sc->bfe_tag, 511 sc->bfe_tx_ring[i].bfe_map); 512 } 513 } 514 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 515 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 516} 517 518static void 519bfe_rx_ring_free(struct bfe_softc *sc) 520{ 521 int i; 522 523 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 524 if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) { 525 m_freem(sc->bfe_rx_ring[i].bfe_mbuf); 526 sc->bfe_rx_ring[i].bfe_mbuf = NULL; 527 bus_dmamap_unload(sc->bfe_tag, 528 sc->bfe_rx_ring[i].bfe_map); 529 bus_dmamap_destroy(sc->bfe_tag, 530 sc->bfe_rx_ring[i].bfe_map); 531 } 532 } 533 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 534 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 535} 536 537 538static int 539bfe_list_rx_init(struct bfe_softc *sc) 540{ 541 int i; 542 543 for(i = 0; i < BFE_RX_LIST_CNT; i++) { 544 if(bfe_list_newbuf(sc, i, NULL) == ENOBUFS) 545 return ENOBUFS; 546 } 547 548 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 549 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc))); 550 551 sc->bfe_rx_cons = 0; 552 553 return(0); 554} 555 556static int 557bfe_list_newbuf(struct bfe_softc *sc, int c, struct mbuf *m) 558{ 559 struct bfe_rxheader *rx_header; 560 struct bfe_desc *d; 561 struct bfe_data *r; 562 u_int32_t ctrl; 563 564 if ((c < 0) || (c >= BFE_RX_LIST_CNT)) 565 return(EINVAL); 566 567 if(m == NULL) { 568 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 569 if(m == NULL) 570 return(ENOBUFS); 571 m->m_len = m->m_pkthdr.len = MCLBYTES; 572 } 573 else 574 m->m_data = m->m_ext.ext_buf; 575 576 rx_header = mtod(m, struct bfe_rxheader *); 577 rx_header->len = 0; 578 rx_header->flags = 0; 579 580 /* Map the mbuf into DMA */ 581 sc->bfe_rx_cnt = c; 582 d = &sc->bfe_rx_list[c]; 583 r = &sc->bfe_rx_ring[c]; 584 bus_dmamap_load(sc->bfe_tag, r->bfe_map, mtod(m, void *), 585 MCLBYTES, bfe_dma_map_desc, d, 0); 586 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_PREWRITE); 587 588 ctrl = ETHER_MAX_LEN + 32; 589 590 if(c == BFE_RX_LIST_CNT - 1) 591 ctrl |= BFE_DESC_EOT; 592 593 d->bfe_ctrl = ctrl; 594 r->bfe_mbuf = m; 595 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 596 return(0); 597} 598 599static void 600bfe_get_config(struct bfe_softc *sc) 601{ 602 u_int8_t eeprom[128]; 603 604 bfe_read_eeprom(sc, eeprom); 605 606 sc->arpcom.ac_enaddr[0] = eeprom[79]; 607 sc->arpcom.ac_enaddr[1] = eeprom[78]; 608 sc->arpcom.ac_enaddr[2] = eeprom[81]; 609 sc->arpcom.ac_enaddr[3] = eeprom[80]; 610 sc->arpcom.ac_enaddr[4] = eeprom[83]; 611 sc->arpcom.ac_enaddr[5] = eeprom[82]; 612 613 sc->bfe_phyaddr = eeprom[90] & 0x1f; 614 sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1; 615 616 sc->bfe_core_unit = 0; 617 sc->bfe_dma_offset = BFE_PCI_DMA; 618} 619 620static void 621bfe_pci_setup(struct bfe_softc *sc, u_int32_t cores) 622{ 623 u_int32_t bar_orig, pci_rev, val; 624 625 bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4); 626 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4); 627 pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK; 628 629 val = CSR_READ_4(sc, BFE_SBINTVEC); 630 val |= cores; 631 CSR_WRITE_4(sc, BFE_SBINTVEC, val); 632 633 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2); 634 val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST; 635 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val); 636 637 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4); 638} 639 640static void 641bfe_clear_stats(struct bfe_softc *sc) 642{ 643 u_long reg; 644 645 BFE_LOCK(sc); 646 647 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ); 648 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) 649 CSR_READ_4(sc, reg); 650 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) 651 CSR_READ_4(sc, reg); 652 653 BFE_UNLOCK(sc); 654} 655 656static int 657bfe_resetphy(struct bfe_softc *sc) 658{ 659 u_int32_t val; 660 661 BFE_LOCK(sc); 662 bfe_writephy(sc, 0, BMCR_RESET); 663 DELAY(100); 664 bfe_readphy(sc, 0, &val); 665 if (val & BMCR_RESET) { 666 printf("bfe%d: PHY Reset would not complete.\n", sc->bfe_unit); 667 BFE_UNLOCK(sc); 668 return ENXIO; 669 } 670 BFE_UNLOCK(sc); 671 return 0; 672} 673 674static void 675bfe_chip_halt(struct bfe_softc *sc) 676{ 677 BFE_LOCK(sc); 678 /* disable interrupts - not that it actually does..*/ 679 CSR_WRITE_4(sc, BFE_IMASK, 0); 680 CSR_READ_4(sc, BFE_IMASK); 681 682 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 683 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1); 684 685 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 686 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 687 DELAY(10); 688 689 BFE_UNLOCK(sc); 690} 691 692static void 693bfe_chip_reset(struct bfe_softc *sc) 694{ 695 u_int32_t val; 696 697 BFE_LOCK(sc); 698 699 /* Set the interrupt vector for the enet core */ 700 bfe_pci_setup(sc, BFE_INTVEC_ENET0); 701 702 /* is core up? */ 703 val = CSR_READ_4(sc, BFE_SBTMSLOW) & (BFE_RESET | BFE_REJECT | BFE_CLOCK); 704 if (val == BFE_CLOCK) { 705 /* It is, so shut it down */ 706 CSR_WRITE_4(sc, BFE_RCV_LAZY, 0); 707 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 708 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1); 709 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 710 sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0; 711 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK) 712 bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE, 100, 0); 713 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 714 sc->bfe_rx_prod = sc->bfe_rx_cons = 0; 715 } 716 717 bfe_core_reset(sc); 718 bfe_clear_stats(sc); 719 720 /* 721 * We want the phy registers to be accessible even when 722 * the driver is "downed" so initialize MDC preamble, frequency, 723 * and whether internal or external phy here. 724 */ 725 726 /* 4402 has 62.5Mhz SB clock and internal phy */ 727 CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d); 728 729 /* Internal or external PHY? */ 730 val = CSR_READ_4(sc, BFE_DEVCTRL); 731 if(!(val & BFE_IPP)) 732 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL); 733 else if(CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) { 734 BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR); 735 DELAY(100); 736 } 737 738 BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB); 739 CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) & 740 BFE_LAZY_FC_MASK)); 741 742 /* 743 * We don't want lazy interrupts, so just send them at the end of a frame, 744 * please 745 */ 746 BFE_OR(sc, BFE_RCV_LAZY, 0); 747 748 /* Set max lengths, accounting for VLAN tags */ 749 CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32); 750 CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32); 751 752 /* Set watermark XXX - magic */ 753 CSR_WRITE_4(sc, BFE_TX_WMARK, 56); 754 755 /* 756 * Initialise DMA channels - not forgetting dma addresses need to be added 757 * to BFE_PCI_DMA 758 */ 759 CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE); 760 CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA); 761 762 CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) | 763 BFE_RX_CTRL_ENABLE); 764 CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA); 765 766 bfe_resetphy(sc); 767 bfe_setupphy(sc); 768 769 BFE_UNLOCK(sc); 770} 771 772static void 773bfe_core_disable(struct bfe_softc *sc) 774{ 775 if((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET) 776 return; 777 778 /* 779 * Set reject, wait for it set, then wait for the core to stop being busy 780 * Then set reset and reject and enable the clocks 781 */ 782 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK)); 783 bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0); 784 bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1); 785 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT | 786 BFE_RESET)); 787 CSR_READ_4(sc, BFE_SBTMSLOW); 788 DELAY(10); 789 /* Leave reset and reject set */ 790 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET)); 791 DELAY(10); 792} 793 794static void 795bfe_core_reset(struct bfe_softc *sc) 796{ 797 u_int32_t val; 798 799 /* Disable the core */ 800 bfe_core_disable(sc); 801 802 /* and bring it back up */ 803 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC)); 804 CSR_READ_4(sc, BFE_SBTMSLOW); 805 DELAY(10); 806 807 /* Chip bug, clear SERR, IB and TO if they are set. */ 808 if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR) 809 CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0); 810 val = CSR_READ_4(sc, BFE_SBIMSTATE); 811 if (val & (BFE_IBE | BFE_TO)) 812 CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO)); 813 814 /* Clear reset and allow it to move through the core */ 815 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC)); 816 CSR_READ_4(sc, BFE_SBTMSLOW); 817 DELAY(10); 818 819 /* Leave the clock set */ 820 CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK); 821 CSR_READ_4(sc, BFE_SBTMSLOW); 822 DELAY(10); 823} 824 825static void 826bfe_cam_write(struct bfe_softc *sc, u_char *data, int index) 827{ 828 u_int32_t val; 829 830 val = ((u_int32_t) data[2]) << 24; 831 val |= ((u_int32_t) data[3]) << 16; 832 val |= ((u_int32_t) data[4]) << 8; 833 val |= ((u_int32_t) data[5]); 834 CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val); 835 val = (BFE_CAM_HI_VALID | 836 (((u_int32_t) data[0]) << 8) | 837 (((u_int32_t) data[1]))); 838 CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val); 839 CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE | 840 (index << BFE_CAM_INDEX_SHIFT))); 841 bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1); 842} 843 844static void 845bfe_set_rx_mode(struct bfe_softc *sc) 846{ 847 struct ifnet *ifp = &sc->arpcom.ac_if; 848 struct ifmultiaddr *ifma; 849 u_int32_t val; 850 int i = 0; 851 852 val = CSR_READ_4(sc, BFE_RXCONF); 853 854 if (ifp->if_flags & IFF_PROMISC) 855 val |= BFE_RXCONF_PROMISC; 856 else 857 val &= ~BFE_RXCONF_PROMISC; 858 859 if (ifp->if_flags & IFF_BROADCAST) 860 val &= ~BFE_RXCONF_DBCAST; 861 else 862 val |= BFE_RXCONF_DBCAST; 863 864 865 CSR_WRITE_4(sc, BFE_CAM_CTRL, 0); 866 bfe_cam_write(sc, sc->arpcom.ac_enaddr, i++); 867 868 if (ifp->if_flags & IFF_ALLMULTI) 869 val |= BFE_RXCONF_ALLMULTI; 870 else { 871 val &= ~BFE_RXCONF_ALLMULTI; 872 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 873 if (ifma->ifma_addr->sa_family != AF_LINK) 874 continue; 875 bfe_cam_write(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 876 i++); 877 } 878 } 879 880 CSR_WRITE_4(sc, BFE_RXCONF, val); 881 BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE); 882} 883 884static void 885bfe_dma_map(void *arg, bus_dma_segment_t *segs, int nseg, int error) 886{ 887 u_int32_t *ptr; 888 889 ptr = arg; 890 *ptr = segs->ds_addr; 891} 892 893static void 894bfe_dma_map_desc(void *arg, bus_dma_segment_t *segs, int nseg, int error) 895{ 896 struct bfe_desc *d; 897 898 d = arg; 899 /* The chip needs all addresses to be added to BFE_PCI_DMA */ 900 d->bfe_addr = segs->ds_addr + BFE_PCI_DMA; 901} 902 903static void 904bfe_release_resources(struct bfe_softc *sc) 905{ 906 device_t dev; 907 int i; 908 909 dev = sc->bfe_dev; 910 911 if (sc->bfe_vpd_prodname != NULL) 912 free(sc->bfe_vpd_prodname, M_DEVBUF); 913 914 if (sc->bfe_vpd_readonly != NULL) 915 free(sc->bfe_vpd_readonly, M_DEVBUF); 916 917 if (sc->bfe_intrhand != NULL) 918 bus_teardown_intr(dev, sc->bfe_irq, sc->bfe_intrhand); 919 920 if (sc->bfe_irq != NULL) 921 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bfe_irq); 922 923 if (sc->bfe_res != NULL) 924 bus_release_resource(dev, SYS_RES_MEMORY, 0x10, sc->bfe_res); 925 926 if(sc->bfe_tx_tag != NULL) { 927 bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map); 928 bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list, sc->bfe_tx_map); 929 bus_dma_tag_destroy(sc->bfe_tx_tag); 930 sc->bfe_tx_tag = NULL; 931 } 932 933 if(sc->bfe_rx_tag != NULL) { 934 bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map); 935 bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list, sc->bfe_rx_map); 936 bus_dma_tag_destroy(sc->bfe_rx_tag); 937 sc->bfe_rx_tag = NULL; 938 } 939 940 if(sc->bfe_tag != NULL) { 941 for(i = 0; i < BFE_TX_LIST_CNT; i++) { 942 bus_dmamap_destroy(sc->bfe_tag, sc->bfe_tx_ring[i].bfe_map); 943 } 944 bus_dma_tag_destroy(sc->bfe_tag); 945 sc->bfe_tag = NULL; 946 } 947 948 if(sc->bfe_parent_tag != NULL) 949 bus_dma_tag_destroy(sc->bfe_parent_tag); 950 951 return; 952} 953 954static void 955bfe_read_eeprom(struct bfe_softc *sc, u_int8_t *data) 956{ 957 long i; 958 u_int16_t *ptr = (u_int16_t *)data; 959 960 for(i = 0; i < 128; i += 2) 961 ptr[i/2] = CSR_READ_4(sc, 4096 + i); 962} 963 964static int 965bfe_wait_bit(struct bfe_softc *sc, u_int32_t reg, u_int32_t bit, 966 u_long timeout, const int clear) 967{ 968 u_long i; 969 970 for (i = 0; i < timeout; i++) { 971 u_int32_t val = CSR_READ_4(sc, reg); 972 973 if (clear && !(val & bit)) 974 break; 975 if (!clear && (val & bit)) 976 break; 977 DELAY(10); 978 } 979 if (i == timeout) { 980 printf("bfe%d: BUG! Timeout waiting for bit %08x of register " 981 "%x to %s.\n", sc->bfe_unit, bit, reg, 982 (clear ? "clear" : "set")); 983 return -1; 984 } 985 return 0; 986} 987 988static int 989bfe_readphy(struct bfe_softc *sc, u_int32_t reg, u_int32_t *val) 990{ 991 int err; 992 993 BFE_LOCK(sc); 994 /* Clear MII ISR */ 995 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 996 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 997 (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) | 998 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 999 (reg << BFE_MDIO_RA_SHIFT) | 1000 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT))); 1001 err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1002 *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA; 1003 1004 BFE_UNLOCK(sc); 1005 return err; 1006} 1007 1008static int 1009bfe_writephy(struct bfe_softc *sc, u_int32_t reg, u_int32_t val) 1010{ 1011 int status; 1012 1013 BFE_LOCK(sc); 1014 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1015 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1016 (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) | 1017 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1018 (reg << BFE_MDIO_RA_SHIFT) | 1019 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) | 1020 (val & BFE_MDIO_DATA_DATA))); 1021 status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1022 BFE_UNLOCK(sc); 1023 1024 return status; 1025} 1026 1027/* 1028 * XXX - I think this is handled by the PHY driver, but it can't hurt to do it 1029 * twice 1030 */ 1031static int 1032bfe_setupphy(struct bfe_softc *sc) 1033{ 1034 u_int32_t val; 1035 BFE_LOCK(sc); 1036 1037 /* Enable activity LED */ 1038 bfe_readphy(sc, 26, &val); 1039 bfe_writephy(sc, 26, val & 0x7fff); 1040 bfe_readphy(sc, 26, &val); 1041 1042 /* Enable traffic meter LED mode */ 1043 bfe_readphy(sc, 27, &val); 1044 bfe_writephy(sc, 27, val | (1 << 6)); 1045 1046 BFE_UNLOCK(sc); 1047 return 0; 1048} 1049 1050static void 1051bfe_stats_update(struct bfe_softc *sc) 1052{ 1053 u_long reg; 1054 u_int32_t *val; 1055 1056 val = &sc->bfe_hwstats.tx_good_octets; 1057 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) { 1058 *val++ += CSR_READ_4(sc, reg); 1059 } 1060 val = &sc->bfe_hwstats.rx_good_octets; 1061 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) { 1062 *val++ += CSR_READ_4(sc, reg); 1063 } 1064} 1065 1066static void 1067bfe_txeof(struct bfe_softc *sc) 1068{ 1069 struct ifnet *ifp; 1070 int i, chipidx; 1071 1072 BFE_LOCK(sc); 1073 1074 ifp = &sc->arpcom.ac_if; 1075 1076 chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK; 1077 chipidx /= sizeof(struct bfe_desc); 1078 1079 i = sc->bfe_tx_cons; 1080 /* Go through the mbufs and free those that have been transmitted */ 1081 while(i != chipidx) { 1082 struct bfe_data *r = &sc->bfe_tx_ring[i]; 1083 if(r->bfe_mbuf != NULL) { 1084 ifp->if_opackets++; 1085 m_freem(r->bfe_mbuf); 1086 r->bfe_mbuf = NULL; 1087 bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1088 } 1089 sc->bfe_tx_cnt--; 1090 BFE_INC(i, BFE_TX_LIST_CNT); 1091 } 1092 1093 if(i != sc->bfe_tx_cons) { 1094 /* we freed up some mbufs */ 1095 sc->bfe_tx_cons = i; 1096 ifp->if_flags &= ~IFF_OACTIVE; 1097 } 1098 if(sc->bfe_tx_cnt == 0) 1099 ifp->if_timer = 0; 1100 else 1101 ifp->if_timer = 5; 1102 1103 BFE_UNLOCK(sc); 1104} 1105 1106/* Pass a received packet up the stack */ 1107static void 1108bfe_rxeof(struct bfe_softc *sc) 1109{ 1110 struct mbuf *m; 1111 struct ifnet *ifp; 1112 struct bfe_rxheader *rxheader; 1113 struct bfe_data *r; 1114 int cons; 1115 u_int32_t status, current, len, flags; 1116 1117 BFE_LOCK(sc); 1118 cons = sc->bfe_rx_cons; 1119 status = CSR_READ_4(sc, BFE_DMARX_STAT); 1120 current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc); 1121 1122 ifp = &sc->arpcom.ac_if; 1123 1124 while(current != cons) { 1125 r = &sc->bfe_rx_ring[cons]; 1126 m = r->bfe_mbuf; 1127 rxheader = mtod(m, struct bfe_rxheader*); 1128 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_POSTWRITE); 1129 len = rxheader->len; 1130 r->bfe_mbuf = NULL; 1131 1132 bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1133 flags = rxheader->flags; 1134 1135 len -= ETHER_CRC_LEN; 1136 1137 /* flag an error and try again */ 1138 if ((len > ETHER_MAX_LEN+32) || (flags & BFE_RX_FLAG_ERRORS)) { 1139 ifp->if_ierrors++; 1140 if (flags & BFE_RX_FLAG_SERR) 1141 ifp->if_collisions++; 1142 bfe_list_newbuf(sc, cons, m); 1143 continue; 1144 } 1145 1146 /* Go past the rx header */ 1147 if (bfe_list_newbuf(sc, cons, NULL) == 0) { 1148 m_adj(m, BFE_RX_OFFSET); 1149 m->m_len = m->m_pkthdr.len = len; 1150 } else { 1151 bfe_list_newbuf(sc, cons, m); 1152 ifp->if_ierrors++; 1153 continue; 1154 } 1155 1156 ifp->if_ipackets++; 1157 m->m_pkthdr.rcvif = ifp; 1158 (*ifp->if_input)(ifp, m); 1159 1160 BFE_INC(cons, BFE_RX_LIST_CNT); 1161 } 1162 sc->bfe_rx_cons = cons; 1163 BFE_UNLOCK(sc); 1164} 1165 1166static void 1167bfe_intr(void *xsc) 1168{ 1169 struct bfe_softc *sc = xsc; 1170 struct ifnet *ifp; 1171 u_int32_t istat, imask, flag; 1172 1173 ifp = &sc->arpcom.ac_if; 1174 1175 BFE_LOCK(sc); 1176 1177 istat = CSR_READ_4(sc, BFE_ISTAT); 1178 imask = CSR_READ_4(sc, BFE_IMASK); 1179 1180 /* 1181 * Defer unsolicited interrupts - This is necessary because setting the 1182 * chips interrupt mask register to 0 doesn't actually stop the 1183 * interrupts 1184 */ 1185 istat &= imask; 1186 CSR_WRITE_4(sc, BFE_ISTAT, istat); 1187 CSR_READ_4(sc, BFE_ISTAT); 1188 1189 /* not expecting this interrupt, disregard it */ 1190 if(istat == 0) { 1191 BFE_UNLOCK(sc); 1192 return; 1193 } 1194 1195 if(istat & BFE_ISTAT_ERRORS) { 1196 flag = CSR_READ_4(sc, BFE_DMATX_STAT); 1197 if(flag & BFE_STAT_EMASK) 1198 ifp->if_oerrors++; 1199 1200 flag = CSR_READ_4(sc, BFE_DMARX_STAT); 1201 if(flag & BFE_RX_FLAG_ERRORS) 1202 ifp->if_ierrors++; 1203 1204 ifp->if_flags &= ~IFF_RUNNING; 1205 bfe_init(sc); 1206 } 1207 1208 /* A packet was received */ 1209 if(istat & BFE_ISTAT_RX) 1210 bfe_rxeof(sc); 1211 1212 /* A packet was sent */ 1213 if(istat & BFE_ISTAT_TX) 1214 bfe_txeof(sc); 1215 1216 /* We have packets pending, fire them out */ 1217 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL) 1218 bfe_start(ifp); 1219 1220 BFE_UNLOCK(sc); 1221} 1222 1223static int 1224bfe_encap(struct bfe_softc *sc, struct mbuf *m_head, u_int32_t *txidx) 1225{ 1226 struct bfe_desc *d = NULL; 1227 struct bfe_data *r = NULL; 1228 struct mbuf *m; 1229 u_int32_t frag, cur, cnt = 0; 1230 int chainlen = 0; 1231 1232 if(BFE_TX_LIST_CNT - sc->bfe_tx_cnt < 2) 1233 return(ENOBUFS); 1234 1235 /* 1236 * Count the number of frags in this chain to see if 1237 * we need to m_defrag. Since the descriptor list is shared 1238 * by all packets, we'll m_defrag long chains so that they 1239 * do not use up the entire list, even if they would fit. 1240 */ 1241 for(m = m_head; m != NULL; m = m->m_next) 1242 chainlen++; 1243 1244 1245 if ((chainlen > BFE_TX_LIST_CNT / 4) || 1246 ((BFE_TX_LIST_CNT - (chainlen + sc->bfe_tx_cnt)) < 2)) { 1247 m = m_defrag(m_head, M_DONTWAIT); 1248 if (m == NULL) 1249 return(ENOBUFS); 1250 m_head = m; 1251 } 1252 1253 /* 1254 * Start packing the mbufs in this chain into 1255 * the fragment pointers. Stop when we run out 1256 * of fragments or hit the end of the mbuf chain. 1257 */ 1258 m = m_head; 1259 cur = frag = *txidx; 1260 cnt = 0; 1261 1262 for(m = m_head; m != NULL; m = m->m_next) { 1263 if(m->m_len != 0) { 1264 if((BFE_TX_LIST_CNT - (sc->bfe_tx_cnt + cnt)) < 2) 1265 return(ENOBUFS); 1266 1267 d = &sc->bfe_tx_list[cur]; 1268 r = &sc->bfe_tx_ring[cur]; 1269 d->bfe_ctrl = BFE_DESC_LEN & m->m_len; 1270 /* always intterupt on completion */ 1271 d->bfe_ctrl |= BFE_DESC_IOC; 1272 if(cnt == 0) 1273 /* Set start of frame */ 1274 d->bfe_ctrl |= BFE_DESC_SOF; 1275 if(cur == BFE_TX_LIST_CNT - 1) 1276 /* Tell the chip to wrap to the start of the descriptor list */ 1277 d->bfe_ctrl |= BFE_DESC_EOT; 1278 1279 bus_dmamap_load(sc->bfe_tag, r->bfe_map, mtod(m, void*), m->m_len, 1280 bfe_dma_map_desc, d, 0); 1281 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_PREREAD); 1282 1283 frag = cur; 1284 BFE_INC(cur, BFE_TX_LIST_CNT); 1285 cnt++; 1286 } 1287 } 1288 1289 if (m != NULL) 1290 return(ENOBUFS); 1291 1292 sc->bfe_tx_list[frag].bfe_ctrl |= BFE_DESC_EOF; 1293 sc->bfe_tx_ring[frag].bfe_mbuf = m_head; 1294 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 1295 1296 *txidx = cur; 1297 sc->bfe_tx_cnt += cnt; 1298 return (0); 1299} 1300 1301/* 1302 * Set up to transmit a packet 1303 */ 1304static void 1305bfe_start(struct ifnet *ifp) 1306{ 1307 struct bfe_softc *sc; 1308 struct mbuf *m_head = NULL; 1309 int idx; 1310 1311 sc = ifp->if_softc; 1312 idx = sc->bfe_tx_prod; 1313 1314 BFE_LOCK(sc); 1315 1316 /* 1317 * not much point trying to send if the link is down or we have nothing to 1318 * send 1319 */ 1320 if (!sc->bfe_link && ifp->if_snd.ifq_len < 10) { 1321 BFE_UNLOCK(sc); 1322 return; 1323 } 1324 1325 if (ifp->if_flags & IFF_OACTIVE) { 1326 BFE_UNLOCK(sc); 1327 return; 1328 } 1329 1330 while(sc->bfe_tx_ring[idx].bfe_mbuf == NULL) { 1331 IF_DEQUEUE(&ifp->if_snd, m_head); 1332 if(m_head == NULL) 1333 break; 1334 1335 /* 1336 * Pack the data into the tx ring. If we dont have enough room, let 1337 * the chip drain the ring 1338 */ 1339 if(bfe_encap(sc, m_head, &idx)) { 1340 IF_PREPEND(&ifp->if_snd, m_head); 1341 ifp->if_flags |= IFF_OACTIVE; 1342 break; 1343 } 1344 1345 /* 1346 * If there's a BPF listener, bounce a copy of this frame 1347 * to him. 1348 */ 1349 BPF_MTAP(ifp, m_head); 1350 } 1351 1352 sc->bfe_tx_prod = idx; 1353 /* Transmit - twice due to apparent hardware bug */ 1354 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1355 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1356 1357 /* 1358 * Set a timeout in case the chip goes out to lunch. 1359 */ 1360 ifp->if_timer = 5; 1361 BFE_UNLOCK(sc); 1362} 1363 1364static void 1365bfe_init(void *xsc) 1366{ 1367 struct bfe_softc *sc = (struct bfe_softc*)xsc; 1368 struct ifnet *ifp = &sc->arpcom.ac_if; 1369 1370 BFE_LOCK(sc); 1371 1372 if (ifp->if_flags & IFF_RUNNING) { 1373 BFE_UNLOCK(sc); 1374 return; 1375 } 1376 1377 bfe_stop(sc); 1378 bfe_chip_reset(sc); 1379 1380 if (bfe_list_rx_init(sc) == ENOBUFS) { 1381 printf("bfe%d: bfe_init failed. Not enough memory for list buffers\n", 1382 sc->bfe_unit); 1383 bfe_stop(sc); 1384 return; 1385 } 1386 1387 bfe_set_rx_mode(sc); 1388 1389 /* Enable the chip and core */ 1390 BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE); 1391 /* Enable interrupts */ 1392 CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF); 1393 1394 bfe_ifmedia_upd(ifp); 1395 ifp->if_flags |= IFF_RUNNING; 1396 ifp->if_flags &= ~IFF_OACTIVE; 1397 1398 sc->bfe_stat_ch = timeout(bfe_tick, sc, hz); 1399 BFE_UNLOCK(sc); 1400} 1401 1402/* 1403 * Set media options. 1404 */ 1405static int 1406bfe_ifmedia_upd(struct ifnet *ifp) 1407{ 1408 struct bfe_softc *sc; 1409 struct mii_data *mii; 1410 1411 sc = ifp->if_softc; 1412 1413 BFE_LOCK(sc); 1414 1415 mii = device_get_softc(sc->bfe_miibus); 1416 sc->bfe_link = 0; 1417 if (mii->mii_instance) { 1418 struct mii_softc *miisc; 1419 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1420 miisc = LIST_NEXT(miisc, mii_list)) 1421 mii_phy_reset(miisc); 1422 } 1423 mii_mediachg(mii); 1424 1425 BFE_UNLOCK(sc); 1426 return(0); 1427} 1428 1429/* 1430 * Report current media status. 1431 */ 1432static void 1433bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1434{ 1435 struct bfe_softc *sc = ifp->if_softc; 1436 struct mii_data *mii; 1437 1438 BFE_LOCK(sc); 1439 1440 mii = device_get_softc(sc->bfe_miibus); 1441 mii_pollstat(mii); 1442 ifmr->ifm_active = mii->mii_media_active; 1443 ifmr->ifm_status = mii->mii_media_status; 1444 1445 BFE_UNLOCK(sc); 1446} 1447 1448static int 1449bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1450{ 1451 struct bfe_softc *sc = ifp->if_softc; 1452 struct ifreq *ifr = (struct ifreq *) data; 1453 struct mii_data *mii; 1454 int error = 0; 1455 1456 BFE_LOCK(sc); 1457 1458 switch(command) { 1459 case SIOCSIFFLAGS: 1460 if(ifp->if_flags & IFF_UP) 1461 if(ifp->if_flags & IFF_RUNNING) 1462 bfe_set_rx_mode(sc); 1463 else 1464 bfe_init(sc); 1465 else if(ifp->if_flags & IFF_RUNNING) 1466 bfe_stop(sc); 1467 break; 1468 case SIOCADDMULTI: 1469 case SIOCDELMULTI: 1470 if(ifp->if_flags & IFF_RUNNING) 1471 bfe_set_rx_mode(sc); 1472 break; 1473 case SIOCGIFMEDIA: 1474 case SIOCSIFMEDIA: 1475 mii = device_get_softc(sc->bfe_miibus); 1476 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1477 break; 1478 default: 1479 error = ether_ioctl(ifp, command, data); 1480 break; 1481 } 1482 1483 BFE_UNLOCK(sc); 1484 return error; 1485} 1486 1487static void 1488bfe_watchdog(struct ifnet *ifp) 1489{ 1490 struct bfe_softc *sc; 1491 1492 sc = ifp->if_softc; 1493 1494 BFE_LOCK(sc); 1495 1496 printf("bfe%d: watchdog timeout -- resetting\n", sc->bfe_unit); 1497 1498 ifp->if_flags &= ~IFF_RUNNING; 1499 bfe_init(sc); 1500 1501 ifp->if_oerrors++; 1502 1503 BFE_UNLOCK(sc); 1504} 1505 1506static void 1507bfe_tick(void *xsc) 1508{ 1509 struct bfe_softc *sc = xsc; 1510 struct mii_data *mii; 1511 1512 if (sc == NULL) 1513 return; 1514 1515 BFE_LOCK(sc); 1516 1517 mii = device_get_softc(sc->bfe_miibus); 1518 1519 bfe_stats_update(sc); 1520 sc->bfe_stat_ch = timeout(bfe_tick, sc, hz); 1521 1522 if(sc->bfe_link) { 1523 BFE_UNLOCK(sc); 1524 return; 1525 } 1526 1527 mii_tick(mii); 1528 if (!sc->bfe_link && mii->mii_media_status & IFM_ACTIVE && 1529 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1530 sc->bfe_link++; 1531 1532 BFE_UNLOCK(sc); 1533} 1534 1535/* 1536 * Stop the adapter and free any mbufs allocated to the 1537 * RX and TX lists. 1538 */ 1539static void 1540bfe_stop(struct bfe_softc *sc) 1541{ 1542 struct ifnet *ifp; 1543 1544 BFE_LOCK(sc); 1545 1546 untimeout(bfe_tick, sc, sc->bfe_stat_ch); 1547 1548 ifp = &sc->arpcom.ac_if; 1549 1550 bfe_chip_halt(sc); 1551 bfe_tx_ring_free(sc); 1552 bfe_rx_ring_free(sc); 1553 1554 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1555 1556 BFE_UNLOCK(sc); 1557} 1558