if_bcereg.h revision 218423
1170101Ssimokawa/*- 2170101Ssimokawa * Copyright (c) 2006-2010 Broadcom Corporation 3170101Ssimokawa * David Christensen <davidch@broadcom.com>. All rights reserved. 4170101Ssimokawa * 5170101Ssimokawa * Redistribution and use in source and binary forms, with or without 6170101Ssimokawa * modification, are permitted provided that the following conditions 7170101Ssimokawa * are met: 8170101Ssimokawa * 1. Redistributions of source code must retain the above copyright 9170101Ssimokawa * notice, this list of conditions and the following disclaimer. 10170101Ssimokawa * 2. Redistributions in binary form must reproduce the above copyright 11170101Ssimokawa * notice, this list of conditions and the following disclaimer in the 12170101Ssimokawa * documentation and/or other materials provided with the distribution. 13170101Ssimokawa * 3. Neither the name of Broadcom Corporation nor the name of its contributors 14170101Ssimokawa * may be used to endorse or promote products derived from this software 15170101Ssimokawa * without specific prior written consent. 16170101Ssimokawa * 17170101Ssimokawa * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 18170101Ssimokawa * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19170101Ssimokawa * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20170101Ssimokawa * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 21170101Ssimokawa * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22170101Ssimokawa * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23170101Ssimokawa * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24170101Ssimokawa * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25170101Ssimokawa * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26170101Ssimokawa * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27170101Ssimokawa * THE POSSIBILITY OF SUCH DAMAGE. 28170101Ssimokawa * 29170101Ssimokawa * $FreeBSD: head/sys/dev/bce/if_bcereg.h 218423 2011-02-07 23:00:24Z davidch $ 30170101Ssimokawa */ 31170101Ssimokawa 32170101Ssimokawa#ifndef _BCEREG_H_DEFINED 33170101Ssimokawa#define _BCEREG_H_DEFINED 34170101Ssimokawa 35170101Ssimokawa#ifdef HAVE_KERNEL_OPTION_HEADERS 36170101Ssimokawa#include "opt_device_polling.h" 37170101Ssimokawa#endif 38170101Ssimokawa 39170101Ssimokawa#include <sys/param.h> 40170101Ssimokawa#include <sys/endian.h> 41170101Ssimokawa#include <sys/systm.h> 42170101Ssimokawa#include <sys/sockio.h> 43170101Ssimokawa#include <sys/mbuf.h> 44170101Ssimokawa#include <sys/malloc.h> 45170101Ssimokawa#include <sys/kernel.h> 46170101Ssimokawa#include <sys/module.h> 47170101Ssimokawa#include <sys/socket.h> 48170101Ssimokawa#include <sys/sysctl.h> 49170101Ssimokawa#include <sys/queue.h> 50170101Ssimokawa 51170101Ssimokawa#include <net/bpf.h> 52170101Ssimokawa#include <net/ethernet.h> 53170101Ssimokawa#include <net/if.h> 54170101Ssimokawa#include <net/if_arp.h> 55170101Ssimokawa#include <net/if_dl.h> 56170101Ssimokawa#include <net/if_media.h> 57170101Ssimokawa 58170101Ssimokawa#include <net/if_types.h> 59170101Ssimokawa#include <net/if_vlan_var.h> 60170101Ssimokawa 61170101Ssimokawa#include <netinet/in_systm.h> 62170101Ssimokawa#include <netinet/in.h> 63170101Ssimokawa#include <netinet/if_ether.h> 64170101Ssimokawa#include <netinet/ip.h> 65170101Ssimokawa#include <netinet/ip6.h> 66170101Ssimokawa#include <netinet/tcp.h> 67170101Ssimokawa#include <netinet/udp.h> 68170101Ssimokawa 69170101Ssimokawa#include <machine/bus.h> 70170101Ssimokawa#include <machine/resource.h> 71170101Ssimokawa#include <sys/bus.h> 72170101Ssimokawa#include <sys/rman.h> 73170101Ssimokawa 74170101Ssimokawa#include <dev/mii/mii.h> 75170101Ssimokawa#include <dev/mii/miivar.h> 76170101Ssimokawa#include "miidevs.h" 77170101Ssimokawa#include <dev/mii/brgphyreg.h> 78170101Ssimokawa 79170101Ssimokawa#include <dev/pci/pcireg.h> 80170101Ssimokawa#include <dev/pci/pcivar.h> 81170101Ssimokawa 82170101Ssimokawa#include "miibus_if.h" 83170101Ssimokawa 84170101Ssimokawa/****************************************************************************/ 85170101Ssimokawa/* Conversion to FreeBSD type definitions. */ 86170101Ssimokawa/****************************************************************************/ 87170101Ssimokawa#define u64 uint64_t 88170101Ssimokawa#define u32 uint32_t 89170101Ssimokawa#define u16 uint16_t 90170101Ssimokawa#define u8 uint8_t 91170101Ssimokawa 92170101Ssimokawa#if BYTE_ORDER == BIG_ENDIAN 93170101Ssimokawa#define __BIG_ENDIAN 1 94170101Ssimokawa#undef __LITTLE_ENDIAN 95170101Ssimokawa#else 96170101Ssimokawa#undef __BIG_ENDIAN 97170101Ssimokawa#define __LITTLE_ENDIAN 1 98170101Ssimokawa#endif 99170101Ssimokawa 100170101Ssimokawa#define BCE_DWORD_PRINTFB \ 101170101Ssimokawa "\020" \ 102170101Ssimokawa "\40b31" \ 103170101Ssimokawa "\37b30" \ 104170101Ssimokawa "\36b29" \ 105170101Ssimokawa "\35b28" \ 106170101Ssimokawa "\34b27" \ 107170101Ssimokawa "\33b26" \ 108170101Ssimokawa "\32b25" \ 109170101Ssimokawa "\31b24" \ 110170101Ssimokawa "\30b23" \ 111170101Ssimokawa "\27b22" \ 112170101Ssimokawa "\26b21" \ 113170101Ssimokawa "\25b20" \ 114170101Ssimokawa "\24b19" \ 115170101Ssimokawa "\23b18" \ 116170101Ssimokawa "\22b17" \ 117170101Ssimokawa "\21b16" \ 118170101Ssimokawa "\20b15" \ 119170101Ssimokawa "\17b14" \ 120170101Ssimokawa "\16b13" \ 121170101Ssimokawa "\15b12" \ 122170101Ssimokawa "\14b11" \ 123170101Ssimokawa "\13b10" \ 124170101Ssimokawa "\12b9" \ 125170101Ssimokawa "\11b8" \ 126170101Ssimokawa "\10b7" \ 127170101Ssimokawa "\07b6" \ 128170101Ssimokawa "\06b5" \ 129170101Ssimokawa "\05b4" \ 130170101Ssimokawa "\04b3" \ 131170101Ssimokawa "\03b2" \ 132170101Ssimokawa "\02b1" \ 133170101Ssimokawa "\01b0" 134170101Ssimokawa 135170101Ssimokawa/* MII Control Register 0x0 */ 136170101Ssimokawa#define BCE_BMCR_PRINTFB \ 137170101Ssimokawa "\020" \ 138170101Ssimokawa "\20Reset" \ 139170101Ssimokawa "\17Loopback" \ 140170101Ssimokawa "\16Spd0" \ 141170101Ssimokawa "\15AnegEna" \ 142170101Ssimokawa "\14PwrDn" \ 143170101Ssimokawa "\13Isolate" \ 144170101Ssimokawa "\12RstrtAneg" \ 145170101Ssimokawa "\11FD" \ 146170101Ssimokawa "\10CollTst" \ 147170101Ssimokawa "\07Spd1" \ 148170101Ssimokawa "\06Rsrvd" \ 149170101Ssimokawa "\05Rsrvd" \ 150170101Ssimokawa "\04Rsrvd" \ 151170101Ssimokawa "\03Rsrvd" \ 152170101Ssimokawa "\02Rsrvd" \ 153170101Ssimokawa "\01Rsrvd" 154170101Ssimokawa 155170101Ssimokawa/* MII Status Register 0x1 */ 156170101Ssimokawa#define BCE_BMSR_PRINTFB \ 157170101Ssimokawa "\020" \ 158170101Ssimokawa "\20Cap100T4" \ 159170101Ssimokawa "\17Cap100XFD" \ 160170101Ssimokawa "\16Cap100XHD" \ 161170101Ssimokawa "\15Cap10FD" \ 162170101Ssimokawa "\14Cap10HD" \ 163170101Ssimokawa "\13Cap100T2FD" \ 164170101Ssimokawa "\12Cap100T2HD" \ 165170101Ssimokawa "\11ExtStsPrsnt" \ 166170101Ssimokawa "\10Rsrvd" \ 167170101Ssimokawa "\07PrmblSupp" \ 168170101Ssimokawa "\06AnegCmpl" \ 169170101Ssimokawa "\05RemFaultDet" \ 170170101Ssimokawa "\04AnegCap" \ 171170101Ssimokawa "\03LnkUp" \ 172170101Ssimokawa "\02JabberDet" \ 173170101Ssimokawa "\01ExtCapSupp" 174170101Ssimokawa 175170101Ssimokawa/* MII Autoneg Advertisement Register 0x4 */ 176170101Ssimokawa#define BCE_ANAR_PRINTFB \ 177170101Ssimokawa "\020" \ 178170101Ssimokawa "\20AdvNxtPg" \ 179170101Ssimokawa "\17Rsrvd" \ 180170101Ssimokawa "\16AdvRemFault" \ 181170101Ssimokawa "\15Rsrvd" \ 182170101Ssimokawa "\14AdvAsymPause" \ 183170101Ssimokawa "\13AdvPause" \ 184170101Ssimokawa "\12Adv100T4" \ 185170101Ssimokawa "\11Adv100FD" \ 186170101Ssimokawa "\10Adv100HD" \ 187170101Ssimokawa "\07Adv10FD" \ 188170101Ssimokawa "\06Adv10HD" \ 189170101Ssimokawa "\05Rsrvd" \ 190170101Ssimokawa "\04Rsrvd" \ 191170101Ssimokawa "\03Rsrvd" \ 192170101Ssimokawa "\02Rsrvd" \ 193170101Ssimokawa "\01Adv802.3" 194170101Ssimokawa 195170101Ssimokawa/* MII Autoneg Link Partner Ability Register 0x5 */ 196170101Ssimokawa#define BCE_ANLPAR_PRINTFB \ 197170101Ssimokawa "\020" \ 198170101Ssimokawa "\20CapNxtPg" \ 199170101Ssimokawa "\17Ack" \ 200170101Ssimokawa "\16CapRemFault" \ 201170101Ssimokawa "\15Rsrvd" \ 202170101Ssimokawa "\14CapAsymPause" \ 203170101Ssimokawa "\13CapPause" \ 204170101Ssimokawa "\12Cap100T4" \ 205170101Ssimokawa "\11Cap100FD" \ 206170101Ssimokawa "\10Cap100HD" \ 207170101Ssimokawa "\07Cap10FD" \ 208170101Ssimokawa "\06Cap10HD" \ 209170101Ssimokawa "\05Rsrvd" \ 210170101Ssimokawa "\04Rsrvd" \ 211170101Ssimokawa "\03Rsrvd" \ 212170101Ssimokawa "\02Rsrvd" \ 213170101Ssimokawa "\01Cap802.3" 214170101Ssimokawa 215170101Ssimokawa/* 1000Base-T Control Register 0x09 */ 216170101Ssimokawa#define BCE_1000CTL_PRINTFB \ 217170101Ssimokawa "\020" \ 218170101Ssimokawa "\20Test3" \ 219170101Ssimokawa "\17Test2" \ 220170101Ssimokawa "\16Test1" \ 221170101Ssimokawa "\15MasterSlave" \ 222170101Ssimokawa "\14ForceMaster" \ 223170101Ssimokawa "\13SwitchDev" \ 224170101Ssimokawa "\12Adv1000TFD" \ 225170101Ssimokawa "\11Adv1000THD" \ 226170101Ssimokawa "\10Rsrvd" \ 227170101Ssimokawa "\07Rsrvd" \ 228170101Ssimokawa "\06Rsrvd" \ 229170101Ssimokawa "\05Rsrvd" \ 230170101Ssimokawa "\04Rsrvd" \ 231170101Ssimokawa "\03Rsrvd" \ 232170101Ssimokawa "\02Rsrvd" \ 233170101Ssimokawa "\01Rsrvd" 234170101Ssimokawa 235170101Ssimokawa/* MII 1000Base-T Status Register 0x0a */ 236170101Ssimokawa#define BCE_1000STS_PRINTFB \ 237170101Ssimokawa "\020" \ 238170101Ssimokawa "\20MstrSlvFault" \ 239170101Ssimokawa "\17Master" \ 240170101Ssimokawa "\16LclRcvrOk" \ 241170101Ssimokawa "\15RemRcvrOk" \ 242170101Ssimokawa "\14Cap1000FD" \ 243170101Ssimokawa "\13Cpa1000HD" \ 244170101Ssimokawa "\12Rsrvd" \ 245170101Ssimokawa "\11Rsrvd" 246170101Ssimokawa 247170101Ssimokawa/* MII Extended Status Register 0x0f */ 248170101Ssimokawa#define BCE_EXTSTS_PRINTFB \ 249170101Ssimokawa "\020" \ 250170101Ssimokawa "\20b15" \ 251170101Ssimokawa "\17b14" \ 252170101Ssimokawa "\16b13" \ 253170101Ssimokawa "\15b12" \ 254170101Ssimokawa "\14Rsrvd" \ 255170101Ssimokawa "\13Rsrvd" \ 256170101Ssimokawa "\12Rsrvd" \ 257170101Ssimokawa "\11Rsrvd" \ 258170101Ssimokawa "\10Rsrvd" \ 259170101Ssimokawa "\07Rsrvd" \ 260170101Ssimokawa "\06Rsrvd" \ 261170101Ssimokawa "\05Rsrvd" \ 262170101Ssimokawa "\04Rsrvd" \ 263170101Ssimokawa "\03Rsrvd" \ 264170101Ssimokawa "\02Rsrvd" \ 265170101Ssimokawa "\01Rsrvd" 266170101Ssimokawa 267170101Ssimokawa/* MII Autoneg Link Partner Ability Register 0x19 */ 268170101Ssimokawa#define BCE_AUXSTS_PRINTFB \ 269170101Ssimokawa "\020" \ 270170101Ssimokawa "\20AnegCmpl" \ 271170101Ssimokawa "\17AnegCmplAck" \ 272170101Ssimokawa "\16AnegAckDet" \ 273170101Ssimokawa "\15AnegAblDet" \ 274170101Ssimokawa "\14AnegNextPgWait" \ 275170101Ssimokawa "\13HCD" \ 276170101Ssimokawa "\12HCD" \ 277170101Ssimokawa "\11HCD" \ 278170101Ssimokawa "\10PrlDetFault" \ 279170101Ssimokawa "\07RemFault" \ 280170101Ssimokawa "\06PgRcvd" \ 281170101Ssimokawa "\05LnkPrtnrAnegAbl" \ 282170101Ssimokawa "\04LnkPrtnrNPAbl" \ 283170101Ssimokawa "\03LnkUp" \ 284170101Ssimokawa "\02EnaPauseRcv" \ 285170101Ssimokawa "\01EnaPausXmit" 286170101Ssimokawa 287170101Ssimokawa/* 288170101Ssimokawa * Remove before release: 289170101Ssimokawa * 290170101Ssimokawa * #define BCE_DEBUG 291170101Ssimokawa * #define BCE_NVRAM_WRITE_SUPPORT 292170101Ssimokawa * #define BCE_JUMBO_HDRSPLIT 293170101Ssimokawa */ 294170101Ssimokawa 295170101Ssimokawa/****************************************************************************/ 296170101Ssimokawa/* Debugging macros and definitions. */ 297170101Ssimokawa/****************************************************************************/ 298170101Ssimokawa 299170101Ssimokawa#define BCE_CP_LOAD 0x00000001 300170101Ssimokawa#define BCE_CP_SEND 0x00000002 301170101Ssimokawa#define BCE_CP_RECV 0x00000004 302170101Ssimokawa#define BCE_CP_INTR 0x00000008 303170101Ssimokawa#define BCE_CP_UNLOAD 0x00000010 304170101Ssimokawa#define BCE_CP_RESET 0x00000020 305170101Ssimokawa#define BCE_CP_PHY 0x00000040 306170101Ssimokawa#define BCE_CP_NVRAM 0x00000080 307170101Ssimokawa#define BCE_CP_FIRMWARE 0x00000100 308170101Ssimokawa#define BCE_CP_CTX 0x00000200 309170101Ssimokawa#define BCE_CP_REG 0x00000400 310170101Ssimokawa#define BCE_CP_MISC 0x00400000 311170101Ssimokawa#define BCE_CP_SPECIAL 0x00800000 312170101Ssimokawa#define BCE_CP_ALL 0x00FFFFFF 313170101Ssimokawa 314170101Ssimokawa#define BCE_CP_MASK 0x00FFFFFF 315170101Ssimokawa 316170101Ssimokawa#define BCE_LEVEL_FATAL 0x00000000 317170101Ssimokawa#define BCE_LEVEL_WARN 0x01000000 318170101Ssimokawa#define BCE_LEVEL_INFO 0x02000000 319170101Ssimokawa#define BCE_LEVEL_VERBOSE 0x03000000 320170101Ssimokawa#define BCE_LEVEL_EXTREME 0x04000000 321170101Ssimokawa#define BCE_LEVEL_INSANE 0x05000000 322170101Ssimokawa 323170101Ssimokawa#define BCE_LEVEL_MASK 0xFF000000 324170101Ssimokawa 325170101Ssimokawa#define BCE_WARN_LOAD (BCE_CP_LOAD | BCE_LEVEL_WARN) 326170101Ssimokawa#define BCE_INFO_LOAD (BCE_CP_LOAD | BCE_LEVEL_INFO) 327170101Ssimokawa#define BCE_VERBOSE_LOAD (BCE_CP_LOAD | BCE_LEVEL_VERBOSE) 328170101Ssimokawa#define BCE_EXTREME_LOAD (BCE_CP_LOAD | BCE_LEVEL_EXTREME) 329170101Ssimokawa#define BCE_INSANE_LOAD (BCE_CP_LOAD | BCE_LEVEL_INSANE) 330170101Ssimokawa 331170101Ssimokawa#define BCE_WARN_SEND (BCE_CP_SEND | BCE_LEVEL_WARN) 332170101Ssimokawa#define BCE_INFO_SEND (BCE_CP_SEND | BCE_LEVEL_INFO) 333170101Ssimokawa#define BCE_VERBOSE_SEND (BCE_CP_SEND | BCE_LEVEL_VERBOSE) 334170101Ssimokawa#define BCE_EXTREME_SEND (BCE_CP_SEND | BCE_LEVEL_EXTREME) 335170101Ssimokawa#define BCE_INSANE_SEND (BCE_CP_SEND | BCE_LEVEL_INSANE) 336170101Ssimokawa 337170101Ssimokawa#define BCE_WARN_RECV (BCE_CP_RECV | BCE_LEVEL_WARN) 338170101Ssimokawa#define BCE_INFO_RECV (BCE_CP_RECV | BCE_LEVEL_INFO) 339170101Ssimokawa#define BCE_VERBOSE_RECV (BCE_CP_RECV | BCE_LEVEL_VERBOSE) 340170101Ssimokawa#define BCE_EXTREME_RECV (BCE_CP_RECV | BCE_LEVEL_EXTREME) 341170101Ssimokawa#define BCE_INSANE_RECV (BCE_CP_RECV | BCE_LEVEL_INSANE) 342170101Ssimokawa 343170101Ssimokawa#define BCE_WARN_INTR (BCE_CP_INTR | BCE_LEVEL_WARN) 344170101Ssimokawa#define BCE_INFO_INTR (BCE_CP_INTR | BCE_LEVEL_INFO) 345170101Ssimokawa#define BCE_VERBOSE_INTR (BCE_CP_INTR | BCE_LEVEL_VERBOSE) 346170101Ssimokawa#define BCE_EXTREME_INTR (BCE_CP_INTR | BCE_LEVEL_EXTREME) 347170101Ssimokawa#define BCE_INSANE_INTR (BCE_CP_INTR | BCE_LEVEL_INSANE) 348170101Ssimokawa 349170101Ssimokawa#define BCE_WARN_UNLOAD (BCE_CP_UNLOAD | BCE_LEVEL_WARN) 350170101Ssimokawa#define BCE_INFO_UNLOAD (BCE_CP_UNLOAD | BCE_LEVEL_INFO) 351170101Ssimokawa#define BCE_VERBOSE_UNLOAD (BCE_CP_UNLOAD | BCE_LEVEL_VERBOSE) 352170101Ssimokawa#define BCE_EXTREME_UNLOAD (BCE_CP_UNLOAD | BCE_LEVEL_EXTREME) 353170101Ssimokawa#define BCE_INSANE_UNLOAD (BCE_CP_UNLOAD | BCE_LEVEL_INSANE) 354170101Ssimokawa 355170101Ssimokawa#define BCE_WARN_RESET (BCE_CP_RESET | BCE_LEVEL_WARN) 356170101Ssimokawa#define BCE_INFO_RESET (BCE_CP_RESET | BCE_LEVEL_INFO) 357170101Ssimokawa#define BCE_VERBOSE_RESET (BCE_CP_RESET | BCE_LEVEL_VERBOSE) 358170101Ssimokawa#define BCE_EXTREME_RESET (BCE_CP_RESET | BCE_LEVEL_EXTREME) 359170101Ssimokawa#define BCE_INSANE_RESET (BCE_CP_RESET | BCE_LEVEL_INSANE) 360170101Ssimokawa 361170101Ssimokawa#define BCE_WARN_PHY (BCE_CP_PHY | BCE_LEVEL_WARN) 362170101Ssimokawa#define BCE_INFO_PHY (BCE_CP_PHY | BCE_LEVEL_INFO) 363170101Ssimokawa#define BCE_VERBOSE_PHY (BCE_CP_PHY | BCE_LEVEL_VERBOSE) 364170101Ssimokawa#define BCE_EXTREME_PHY (BCE_CP_PHY | BCE_LEVEL_EXTREME) 365170101Ssimokawa#define BCE_INSANE_PHY (BCE_CP_PHY | BCE_LEVEL_INSANE) 366170101Ssimokawa 367170101Ssimokawa#define BCE_WARN_NVRAM (BCE_CP_NVRAM | BCE_LEVEL_WARN) 368170101Ssimokawa#define BCE_INFO_NVRAM (BCE_CP_NVRAM | BCE_LEVEL_INFO) 369170101Ssimokawa#define BCE_VERBOSE_NVRAM (BCE_CP_NVRAM | BCE_LEVEL_VERBOSE) 370#define BCE_EXTREME_NVRAM (BCE_CP_NVRAM | BCE_LEVEL_EXTREME) 371#define BCE_INSANE_NVRAM (BCE_CP_NVRAM | BCE_LEVEL_INSANE) 372 373#define BCE_WARN_FIRMWARE (BCE_CP_FIRMWARE | BCE_LEVEL_WARN) 374#define BCE_INFO_FIRMWARE (BCE_CP_FIRMWARE | BCE_LEVEL_INFO) 375#define BCE_VERBOSE_FIRMWARE (BCE_CP_FIRMWARE | BCE_LEVEL_VERBOSE) 376#define BCE_EXTREME_FIRMWARE (BCE_CP_FIRMWARE | BCE_LEVEL_EXTREME) 377#define BCE_INSANE_FIRMWARE (BCE_CP_FIRMWARE | BCE_LEVEL_INSANE) 378 379#define BCE_WARN_CTX (BCE_CP_CTX | BCE_LEVEL_WARN) 380#define BCE_INFO_CTX (BCE_CP_CTX | BCE_LEVEL_INFO) 381#define BCE_VERBOSE_CTX (BCE_CP_CTX | BCE_LEVEL_VERBOSE) 382#define BCE_EXTREME_CTX (BCE_CP_CTX | BCE_LEVEL_EXTREME) 383#define BCE_INSANE_CTX (BCE_CP_CTX | BCE_LEVEL_INSANE) 384 385#define BCE_WARN_REG (BCE_CP_REG | BCE_LEVEL_WARN) 386#define BCE_INFO_REG (BCE_CP_REG | BCE_LEVEL_INFO) 387#define BCE_VERBOSE_REG (BCE_CP_REG | BCE_LEVEL_VERBOSE) 388#define BCE_EXTREME_REG (BCE_CP_REG | BCE_LEVEL_EXTREME) 389#define BCE_INSANE_REG (BCE_CP_REG | BCE_LEVEL_INSANE) 390 391#define BCE_WARN_MISC (BCE_CP_MISC | BCE_LEVEL_WARN) 392#define BCE_INFO_MISC (BCE_CP_MISC | BCE_LEVEL_INFO) 393#define BCE_VERBOSE_MISC (BCE_CP_MISC | BCE_LEVEL_VERBOSE) 394#define BCE_EXTREME_MISC (BCE_CP_MISC | BCE_LEVEL_EXTREME) 395#define BCE_INSANE_MISC (BCE_CP_MISC | BCE_LEVEL_INSANE) 396 397#define BCE_WARN_SPECIAL (BCE_CP_SPECIAL | BCE_LEVEL_WARN) 398#define BCE_INFO_SPECIAL (BCE_CP_SPECIAL | BCE_LEVEL_INFO) 399#define BCE_VERBOSE_SPECIAL (BCE_CP_SPECIAL | BCE_LEVEL_VERBOSE) 400#define BCE_EXTREME_SPECIAL (BCE_CP_SPECIAL | BCE_LEVEL_EXTREME) 401#define BCE_INSANE_SPECIAL (BCE_CP_SPECIAL | BCE_LEVEL_INSANE) 402 403#define BCE_FATAL (BCE_CP_ALL | BCE_LEVEL_FATAL) 404#define BCE_WARN (BCE_CP_ALL | BCE_LEVEL_WARN) 405#define BCE_INFO (BCE_CP_ALL | BCE_LEVEL_INFO) 406#define BCE_VERBOSE (BCE_CP_ALL | BCE_LEVEL_VERBOSE) 407#define BCE_EXTREME (BCE_CP_ALL | BCE_LEVEL_EXTREME) 408#define BCE_INSANE (BCE_CP_ALL | BCE_LEVEL_INSANE) 409 410#define BCE_CODE_PATH(cp) ((cp & BCE_CP_MASK) & bce_debug) 411#define BCE_MSG_LEVEL(lv) \ 412 ((lv & BCE_LEVEL_MASK) <= (bce_debug & BCE_LEVEL_MASK)) 413#define BCE_LOG_MSG(m) (BCE_CODE_PATH(m) && BCE_MSG_LEVEL(m)) 414 415#ifdef BCE_DEBUG 416 417/* Print a message based on the logging level and code path. */ 418#define DBPRINT(sc, level, format, args...) \ 419 if (BCE_LOG_MSG(level)) { \ 420 device_printf(sc->bce_dev, format, ## args); \ 421 } 422 423/* Runs a particular command when debugging is enabled. */ 424#define DBRUN(args...) \ 425 do { \ 426 args; \ 427 } while (0) 428 429/* Runs a particular command based on the logging level and code path. */ 430#define DBRUNMSG(msg, args...) \ 431 if (BCE_LOG_MSG(msg)) { \ 432 args; \ 433 } 434 435/* Runs a particular command based on the logging level. */ 436#define DBRUNLV(level, args...) \ 437 if (BCE_MSG_LEVEL(level)) { \ 438 args; \ 439 } 440 441/* Runs a particular command based on the code path. */ 442#define DBRUNCP(cp, args...) \ 443 if (BCE_CODE_PATH(cp)) { \ 444 args; \ 445 } 446 447/* Runs a particular command based on a condition. */ 448#define DBRUNIF(cond, args...) \ 449 if (cond) { \ 450 args; \ 451 } 452 453/* Announces function entry. */ 454#define DBENTER(cond) \ 455 DBPRINT(sc, (cond), "%s(enter)\n", __FUNCTION__) 456 457/* Announces function exit. */ 458#define DBEXIT(cond) \ 459 DBPRINT(sc, (cond), "%s(exit)\n", __FUNCTION__) 460 461/* Temporarily override the debug level. */ 462#define DBPUSH(cond) \ 463 u32 bce_debug_temp = bce_debug; \ 464 bce_debug |= cond; 465 466/* Restore the previously overriden debug level. */ 467#define DBPOP() \ 468 bce_debug = bce_debug_temp; 469 470/* Needed for random() function which is only used in debugging. */ 471#include <sys/random.h> 472 473/* Returns FALSE in "defects" per 2^31 - 1 calls, otherwise returns TRUE. */ 474#define DB_RANDOMFALSE(defects) (random() > defects) 475#define DB_OR_RANDOMFALSE(defects) || (random() > defects) 476#define DB_AND_RANDOMFALSE(defects) && (random() > ddfects) 477 478/* Returns TRUE in "defects" per 2^31 - 1 calls, otherwise returns FALSE. */ 479#define DB_RANDOMTRUE(defects) (random() < defects) 480#define DB_OR_RANDOMTRUE(defects) || (random() < defects) 481#define DB_AND_RANDOMTRUE(defects) && (random() < defects) 482 483#define DB_PRINT_PHY_REG(reg, val) \ 484switch(reg) { \ 485case 0x00: DBPRINT(sc, BCE_INSANE_PHY, \ 486 "%s(): phy = %d, reg = 0x%04X (BMCR ), val = 0x%b\n", \ 487 __FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff, \ 488 BCE_BMCR_PRINTFB); break; \ 489case 0x01: DBPRINT(sc, BCE_INSANE_PHY, \ 490 "%s(): phy = %d, reg = 0x%04X (BMSR ), val = 0x%b\n", \ 491 __FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff, \ 492 BCE_BMSR_PRINTFB); break; \ 493case 0x04: DBPRINT(sc, BCE_INSANE_PHY, \ 494 "%s(): phy = %d, reg = 0x%04X (ANAR ), val = 0x%b\n", \ 495 __FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff, \ 496 BCE_ANAR_PRINTFB); break; \ 497case 0x05: DBPRINT(sc, BCE_INSANE_PHY, \ 498 "%s(): phy = %d, reg = 0x%04X (ANLPAR ), val = 0x%b\n", \ 499 __FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff, \ 500 BCE_ANLPAR_PRINTFB); break; \ 501case 0x09: DBPRINT(sc, BCE_INSANE_PHY, \ 502 "%s(): phy = %d, reg = 0x%04X (1000CTL), val = 0x%b\n", \ 503 __FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff, \ 504 BCE_1000CTL_PRINTFB); break; \ 505case 0x0a: DBPRINT(sc, BCE_INSANE_PHY, \ 506 "%s(): phy = %d, reg = 0x%04X (1000STS), val = 0x%b\n", \ 507 __FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff, \ 508 BCE_1000STS_PRINTFB); break; \ 509case 0x0f: DBPRINT(sc, BCE_INSANE_PHY, \ 510 "%s(): phy = %d, reg = 0x%04X (EXTSTS ), val = 0x%b\n", \ 511 __FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff, \ 512 BCE_EXTSTS_PRINTFB); break; \ 513case 0x19: DBPRINT(sc, BCE_INSANE_PHY, \ 514 "%s(): phy = %d, reg = 0x%04X (AUXSTS ), val = 0x%b\n", \ 515 __FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff, \ 516 BCE_AUXSTS_PRINTFB); break; \ 517default: DBPRINT(sc, BCE_INSANE_PHY, \ 518 "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n", \ 519 __FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff); \ 520 } 521 522#else 523 524#define DBPRINT(level, format, args...) 525#define DBRUN(args...) 526#define DBRUNMSG(msg, args...) 527#define DBRUNLV(level, args...) 528#define DBRUNCP(cp, args...) 529#define DBRUNIF(cond, args...) 530#define DBENTER(cond) 531#define DBEXIT(cond) 532#define DBPUSH(cond) 533#define DBPOP() 534#define DB_RANDOMFALSE(defects) 535#define DB_OR_RANDOMFALSE(percent) 536#define DB_AND_RANDOMFALSE(percent) 537#define DB_RANDOMTRUE(defects) 538#define DB_OR_RANDOMTRUE(percent) 539#define DB_AND_RANDOMTRUE(percent) 540#define DB_PRINT_PHY_REG(reg, val) 541 542#endif /* BCE_DEBUG */ 543 544 545#if __FreeBSD_version < 800054 546#if defined(__i386__) || defined(__amd64__) 547#define mb() __asm volatile("mfence" ::: "memory") 548#define wmb() __asm volatile("sfence" ::: "memory") 549#define rmb() __asm volatile("lfence" ::: "memory") 550#else 551#define mb() 552#define rmb() 553#define wmb() 554#endif 555#endif 556 557/****************************************************************************/ 558/* Device identification definitions. */ 559/****************************************************************************/ 560#define BRCM_VENDORID 0x14E4 561#define BRCM_DEVICEID_BCM5706 0x164A 562#define BRCM_DEVICEID_BCM5706S 0x16AA 563#define BRCM_DEVICEID_BCM5708 0x164C 564#define BRCM_DEVICEID_BCM5708S 0x16AC 565#define BRCM_DEVICEID_BCM5709 0x1639 566#define BRCM_DEVICEID_BCM5709S 0x163A 567#define BRCM_DEVICEID_BCM5716 0x163B 568 569#define HP_VENDORID 0x103C 570 571#define PCI_ANY_ID (u_int16_t) (~0U) 572 573/* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ 574 575#define BCE_CHIP_NUM(sc) (((sc)->bce_chipid) & 0xffff0000) 576#define BCE_CHIP_NUM_5706 0x57060000 577#define BCE_CHIP_NUM_5708 0x57080000 578#define BCE_CHIP_NUM_5709 0x57090000 579#define BCE_CHIP_NUM_5716 0x57160000 580 581#define BCE_CHIP_REV(sc) (((sc)->bce_chipid) & 0x0000f000) 582#define BCE_CHIP_REV_Ax 0x00000000 583#define BCE_CHIP_REV_Bx 0x00001000 584#define BCE_CHIP_REV_Cx 0x00002000 585 586#define BCE_CHIP_METAL(sc) (((sc)->bce_chipid) & 0x00000ff0) 587#define BCE_CHIP_BOND(bp) (((sc)->bce_chipid) & 0x0000000f) 588 589#define BCE_CHIP_ID(sc) (((sc)->bce_chipid) & 0xfffffff0) 590#define BCE_CHIP_ID_5706_A0 0x57060000 591#define BCE_CHIP_ID_5706_A1 0x57060010 592#define BCE_CHIP_ID_5706_A2 0x57060020 593#define BCE_CHIP_ID_5706_A3 0x57060030 594#define BCE_CHIP_ID_5708_A0 0x57080000 595#define BCE_CHIP_ID_5708_B0 0x57081000 596#define BCE_CHIP_ID_5708_B1 0x57081010 597#define BCE_CHIP_ID_5708_B2 0x57081020 598#define BCE_CHIP_ID_5709_A0 0x57090000 599#define BCE_CHIP_ID_5709_A1 0x57090010 600#define BCE_CHIP_ID_5709_B0 0x57091000 601#define BCE_CHIP_ID_5709_B1 0x57091010 602#define BCE_CHIP_ID_5709_B2 0x57091020 603#define BCE_CHIP_ID_5709_C0 0x57092000 604#define BCE_CHIP_ID_5716_C0 0x57162000 605 606#define BCE_CHIP_BOND_ID(sc) (((sc)->bce_chipid) & 0xf) 607 608/* A serdes chip will have the first bit of the bond id set. */ 609#define BCE_CHIP_BOND_ID_SERDES_BIT 0x01 610 611 612/* shorthand one */ 613#define BCE_ASICREV(x) ((x) >> 28) 614#define BCE_ASICREV_BCM5700 0x06 615 616/* chip revisions */ 617#define BCE_CHIPREV(x) ((x) >> 24) 618#define BCE_CHIPREV_5700_AX 0x70 619#define BCE_CHIPREV_5700_BX 0x71 620#define BCE_CHIPREV_5700_CX 0x72 621#define BCE_CHIPREV_5701_AX 0x00 622 623struct bce_type { 624 u_int16_t bce_vid; 625 u_int16_t bce_did; 626 u_int16_t bce_svid; 627 u_int16_t bce_sdid; 628 char *bce_name; 629}; 630 631/****************************************************************************/ 632/* Byte order conversions. */ 633/****************************************************************************/ 634#if __FreeBSD_version >= 500000 635#define bce_htobe16(x) htobe16(x) 636#define bce_htobe32(x) htobe32(x) 637#define bce_htobe64(x) htobe64(x) 638#define bce_htole16(x) htole16(x) 639#define bce_htole32(x) htole32(x) 640#define bce_htole64(x) htole64(x) 641 642#define bce_be16toh(x) be16toh(x) 643#define bce_be32toh(x) be32toh(x) 644#define bce_be64toh(x) be64toh(x) 645#define bce_le16toh(x) le16toh(x) 646#define bce_le32toh(x) le32toh(x) 647#define bce_le64toh(x) le64toh(x) 648#else 649#define bce_htobe16(x) (x) 650#define bce_htobe32(x) (x) 651#define bce_htobe64(x) (x) 652#define bce_htole16(x) (x) 653#define bce_htole32(x) (x) 654#define bce_htole64(x) (x) 655 656#define bce_be16toh(x) (x) 657#define bce_be32toh(x) (x) 658#define bce_be64toh(x) (x) 659#define bce_le16toh(x) (x) 660#define bce_le32toh(x) (x) 661#define bce_le64toh(x) (x) 662#endif 663 664 665/****************************************************************************/ 666/* NVRAM Access */ 667/****************************************************************************/ 668 669/* Buffered flash (Atmel: AT45DB011B) specific information */ 670#define SEEPROM_PAGE_BITS 2 671#define SEEPROM_PHY_PAGE_SIZE (1 << SEEPROM_PAGE_BITS) 672#define SEEPROM_BYTE_ADDR_MASK (SEEPROM_PHY_PAGE_SIZE-1) 673#define SEEPROM_PAGE_SIZE 4 674#define SEEPROM_TOTAL_SIZE 65536 675 676#define BUFFERED_FLASH_PAGE_BITS 9 677#define BUFFERED_FLASH_PHY_PAGE_SIZE (1 << BUFFERED_FLASH_PAGE_BITS) 678#define BUFFERED_FLASH_BYTE_ADDR_MASK (BUFFERED_FLASH_PHY_PAGE_SIZE-1) 679#define BUFFERED_FLASH_PAGE_SIZE 264 680#define BUFFERED_FLASH_TOTAL_SIZE 0x21000 681 682#define SAIFUN_FLASH_PAGE_BITS 8 683#define SAIFUN_FLASH_PHY_PAGE_SIZE (1 << SAIFUN_FLASH_PAGE_BITS) 684#define SAIFUN_FLASH_BYTE_ADDR_MASK (SAIFUN_FLASH_PHY_PAGE_SIZE-1) 685#define SAIFUN_FLASH_PAGE_SIZE 256 686#define SAIFUN_FLASH_BASE_TOTAL_SIZE 65536 687 688#define ST_MICRO_FLASH_PAGE_BITS 8 689#define ST_MICRO_FLASH_PHY_PAGE_SIZE (1 << ST_MICRO_FLASH_PAGE_BITS) 690#define ST_MICRO_FLASH_BYTE_ADDR_MASK (ST_MICRO_FLASH_PHY_PAGE_SIZE-1) 691#define ST_MICRO_FLASH_PAGE_SIZE 256 692#define ST_MICRO_FLASH_BASE_TOTAL_SIZE 65536 693 694#define BCM5709_FLASH_PAGE_BITS 8 695#define BCM5709_FLASH_PHY_PAGE_SIZE (1 << BCM5709_FLASH_PAGE_BITS) 696#define BCM5709_FLASH_BYTE_ADDR_MASK (BCM5709_FLASH_PHY_PAGE_SIZE-1) 697#define BCM5709_FLASH_PAGE_SIZE 256 698 699#define NVRAM_TIMEOUT_COUNT 30000 700#define BCE_FLASHDESC_MAX 64 701 702#define FLASH_STRAP_MASK (BCE_NVM_CFG1_FLASH_MODE | \ 703 BCE_NVM_CFG1_BUFFER_MODE | BCE_NVM_CFG1_PROTECT_MODE | \ 704 BCE_NVM_CFG1_FLASH_SIZE) 705 706#define FLASH_BACKUP_STRAP_MASK (0xf << 26) 707 708struct flash_spec { 709 u32 strapping; 710 u32 config1; 711 u32 config2; 712 u32 config3; 713 u32 write1; 714#define BCE_NV_BUFFERED 0x00000001 715#define BCE_NV_TRANSLATE 0x00000002 716#define BCE_NV_WREN 0x00000004 717 u32 flags; 718 u32 page_bits; 719 u32 page_size; 720 u32 addr_mask; 721 u32 total_size; 722 u8 *name; 723}; 724 725 726/****************************************************************************/ 727/* Shared Memory layout */ 728/* The BCE bootcode will initialize this data area with port configurtion */ 729/* information which can be accessed by the driver. */ 730/****************************************************************************/ 731 732/* 733 * This value (in milliseconds) determines the frequency of the driver 734 * issuing the PULSE message code. The firmware monitors this periodic 735 * pulse to determine when to switch to an OS-absent mode. 736 */ 737#define DRV_PULSE_PERIOD_MS 250 738 739/* 740 * This value (in milliseconds) determines how long the driver should 741 * wait for an acknowledgement from the firmware before timing out. Once 742 * the firmware has timed out, the driver will assume there is no firmware 743 * running and there won't be any firmware-driver synchronization during a 744 * driver reset. 745 */ 746#define FW_ACK_TIME_OUT_MS 1000 747 748 749#define BCE_DRV_RESET_SIGNATURE 0x00000000 750#define BCE_DRV_RESET_SIGNATURE_MAGIC 0x4841564b /* HAVK */ 751 752#define BCE_DRV_MB 0x00000004 753#define BCE_DRV_MSG_CODE 0xff000000 754#define BCE_DRV_MSG_CODE_RESET 0x01000000 755#define BCE_DRV_MSG_CODE_UNLOAD 0x02000000 756#define BCE_DRV_MSG_CODE_SHUTDOWN 0x03000000 757#define BCE_DRV_MSG_CODE_SUSPEND_WOL 0x04000000 758#define BCE_DRV_MSG_CODE_FW_TIMEOUT 0x05000000 759#define BCE_DRV_MSG_CODE_PULSE 0x06000000 760#define BCE_DRV_MSG_CODE_DIAG 0x07000000 761#define BCE_DRV_MSG_CODE_SUSPEND_NO_WOL 0x09000000 762#define BCE_DRV_MSG_CODE_UNLOAD_LNK_DN 0x0b000000 763#define BCE_DRV_MSG_CODE_CMD_SET_LINK 0x10000000 764 765#define BCE_DRV_MSG_DATA 0x00ff0000 766#define BCE_DRV_MSG_DATA_WAIT0 0x00010000 767#define BCE_DRV_MSG_DATA_WAIT1 0x00020000 768#define BCE_DRV_MSG_DATA_WAIT2 0x00030000 769#define BCE_DRV_MSG_DATA_WAIT3 0x00040000 770 771#define BCE_DRV_MSG_SEQ 0x0000ffff 772 773#define BCE_FW_MB 0x00000008 774#define BCE_FW_MSG_ACK 0x0000ffff 775#define BCE_FW_MSG_STATUS_MASK 0x00ff0000 776#define BCE_FW_MSG_STATUS_OK 0x00000000 777#define BCE_FW_MSG_STATUS_INVALID_ARGS 0x00010000 778#define BCE_FW_MSG_STATUS_DRV_PRSNT 0x00020000 779#define BCE_FW_MSG_STATUS_FAILURE 0x00ff0000 780 781#define BCE_LINK_STATUS 0x0000000c 782#define BCE_LINK_STATUS_INIT_VALUE 0xffffffff 783#define BCE_LINK_STATUS_LINK_UP 0x1 784#define BCE_LINK_STATUS_LINK_DOWN 0x0 785#define BCE_LINK_STATUS_SPEED_MASK 0x1e 786#define BCE_LINK_STATUS_AN_INCOMPLETE (0<<1) 787#define BCE_LINK_STATUS_10HALF (1<<1) 788#define BCE_LINK_STATUS_10FULL (2<<1) 789#define BCE_LINK_STATUS_100HALF (3<<1) 790#define BCE_LINK_STATUS_100BASE_T4 (4<<1) 791#define BCE_LINK_STATUS_100FULL (5<<1) 792#define BCE_LINK_STATUS_1000HALF (6<<1) 793#define BCE_LINK_STATUS_1000FULL (7<<1) 794#define BCE_LINK_STATUS_2500HALF (8<<1) 795#define BCE_LINK_STATUS_2500FULL (9<<1) 796#define BCE_LINK_STATUS_AN_ENABLED (1<<5) 797#define BCE_LINK_STATUS_AN_COMPLETE (1<<6) 798#define BCE_LINK_STATUS_PARALLEL_DET (1<<7) 799#define BCE_LINK_STATUS_RESERVED (1<<8) 800#define BCE_LINK_STATUS_PARTNER_AD_1000FULL (1<<9) 801#define BCE_LINK_STATUS_PARTNER_AD_1000HALF (1<<10) 802#define BCE_LINK_STATUS_PARTNER_AD_100BT4 (1<<11) 803#define BCE_LINK_STATUS_PARTNER_AD_100FULL (1<<12) 804#define BCE_LINK_STATUS_PARTNER_AD_100HALF (1<<13) 805#define BCE_LINK_STATUS_PARTNER_AD_10FULL (1<<14) 806#define BCE_LINK_STATUS_PARTNER_AD_10HALF (1<<15) 807#define BCE_LINK_STATUS_TX_FC_ENABLED (1<<16) 808#define BCE_LINK_STATUS_RX_FC_ENABLED (1<<17) 809#define BCE_LINK_STATUS_PARTNER_SYM_PAUSE_CAP (1<<18) 810#define BCE_LINK_STATUS_PARTNER_ASYM_PAUSE_CAP (1<<19) 811#define BCE_LINK_STATUS_SERDES_LINK (1<<20) 812#define BCE_LINK_STATUS_PARTNER_AD_2500FULL (1<<21) 813#define BCE_LINK_STATUS_PARTNER_AD_2500HALF (1<<22) 814 815#define BCE_DRV_PULSE_MB 0x00000010 816#define BCE_DRV_PULSE_SEQ_MASK 0x00007fff 817 818#define BCE_MB_ARGS_0 0x00000014 819#define BCE_MB_ARGS_1 0x00000018 820 821/* Indicate to the firmware not to go into the 822 * OS absent when it is not getting driver pulse. 823 * This is used for debugging. */ 824#define BCE_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE 0x00080000 825 826#define BCE_DEV_INFO_SIGNATURE 0x00000020 827#define BCE_DEV_INFO_SIGNATURE_MAGIC 0x44564900 828#define BCE_DEV_INFO_SIGNATURE_MAGIC_MASK 0xffffff00 829#define BCE_DEV_INFO_FEATURE_CFG_VALID 0x01 830#define BCE_DEV_INFO_SECONDARY_PORT 0x80 831#define BCE_DEV_INFO_DRV_ALWAYS_ALIVE 0x40 832 833#define BCE_SHARED_HW_CFG_PART_NUM 0x00000024 834 835#define BCE_SHARED_HW_CFG_POWER_DISSIPATED 0x00000034 836#define BCE_SHARED_HW_CFG_POWER_STATE_D3_MASK 0xff000000 837#define BCE_SHARED_HW_CFG_POWER_STATE_D2_MASK 0xff0000 838#define BCE_SHARED_HW_CFG_POWER_STATE_D1_MASK 0xff00 839#define BCE_SHARED_HW_CFG_POWER_STATE_D0_MASK 0xff 840 841#define BCE_SHARED_HW_CFG_POWER_CONSUMED 0x00000038 842#define BCE_SHARED_HW_CFG_CONFIG 0x0000003c 843#define BCE_SHARED_HW_CFG_DESIGN_NIC 0 844#define BCE_SHARED_HW_CFG_DESIGN_LOM 0x1 845#define BCE_SHARED_HW_CFG_PHY_COPPER 0 846#define BCE_SHARED_HW_CFG_PHY_FIBER 0x2 847#define BCE_SHARED_HW_CFG_PHY_2_5G 0x20 848#define BCE_SHARED_HW_CFG_PHY_BACKPLANE 0x40 849#define BCE_SHARED_HW_CFG_LED_MODE_SHIFT_BITS 8 850#define BCE_SHARED_HW_CFG_LED_MODE_MASK 0x300 851#define BCE_SHARED_HW_CFG_LED_MODE_MAC 0 852#define BCE_SHARED_HW_CFG_LED_MODE_GPHY1 0x100 853#define BCE_SHARED_HW_CFG_LED_MODE_GPHY2 0x200 854 855#define BCE_SHARED_HW_CFG_CONFIG2 0x00000040 856#define BCE_SHARED_HW_CFG2_NVM_SIZE_MASK 0x00fff000 857 858#define BCE_DEV_INFO_BC_REV 0x0000004c 859 860#define BCE_PORT_HW_CFG_MAC_UPPER 0x00000050 861#define BCE_PORT_HW_CFG_UPPERMAC_MASK 0xffff 862 863#define BCE_PORT_HW_CFG_MAC_LOWER 0x00000054 864#define BCE_PORT_HW_CFG_CONFIG 0x00000058 865#define BCE_PORT_HW_CFG_CFG_TXCTL3_MASK 0x0000ffff 866#define BCE_PORT_HW_CFG_CFG_DFLT_LINK_MASK 0x001f0000 867#define BCE_PORT_HW_CFG_CFG_DFLT_LINK_AN 0x00000000 868#define BCE_PORT_HW_CFG_CFG_DFLT_LINK_1G 0x00030000 869#define BCE_PORT_HW_CFG_CFG_DFLT_LINK_2_5G 0x00040000 870 871#define BCE_PORT_HW_CFG_IMD_MAC_A_UPPER 0x00000068 872#define BCE_PORT_HW_CFG_IMD_MAC_A_LOWER 0x0000006c 873#define BCE_PORT_HW_CFG_IMD_MAC_B_UPPER 0x00000070 874#define BCE_PORT_HW_CFG_IMD_MAC_B_LOWER 0x00000074 875#define BCE_PORT_HW_CFG_ISCSI_MAC_UPPER 0x00000078 876#define BCE_PORT_HW_CFG_ISCSI_MAC_LOWER 0x0000007c 877 878#define BCE_DEV_INFO_PER_PORT_HW_CONFIG2 0x000000b4 879 880#define BCE_DEV_INFO_FORMAT_REV 0x000000c4 881#define BCE_DEV_INFO_FORMAT_REV_MASK 0xff000000 882#define BCE_DEV_INFO_FORMAT_REV_ID ('A' << 24) 883 884#define BCE_SHARED_FEATURE 0x000000c8 885#define BCE_SHARED_FEATURE_MASK 0xffffffff 886 887#define BCE_PORT_FEATURE 0x000000d8 888#define BCE_PORT2_FEATURE 0x00000014c 889#define BCE_PORT_FEATURE_WOL_ENABLED 0x01000000 890#define BCE_PORT_FEATURE_MBA_ENABLED 0x02000000 891#define BCE_PORT_FEATURE_ASF_ENABLED 0x04000000 892#define BCE_PORT_FEATURE_IMD_ENABLED 0x08000000 893#define BCE_PORT_FEATURE_BAR1_SIZE_MASK 0xf 894#define BCE_PORT_FEATURE_BAR1_SIZE_DISABLED 0x0 895#define BCE_PORT_FEATURE_BAR1_SIZE_64K 0x1 896#define BCE_PORT_FEATURE_BAR1_SIZE_128K 0x2 897#define BCE_PORT_FEATURE_BAR1_SIZE_256K 0x3 898#define BCE_PORT_FEATURE_BAR1_SIZE_512K 0x4 899#define BCE_PORT_FEATURE_BAR1_SIZE_1M 0x5 900#define BCE_PORT_FEATURE_BAR1_SIZE_2M 0x6 901#define BCE_PORT_FEATURE_BAR1_SIZE_4M 0x7 902#define BCE_PORT_FEATURE_BAR1_SIZE_8M 0x8 903#define BCE_PORT_FEATURE_BAR1_SIZE_16M 0x9 904#define BCE_PORT_FEATURE_BAR1_SIZE_32M 0xa 905#define BCE_PORT_FEATURE_BAR1_SIZE_64M 0xb 906#define BCE_PORT_FEATURE_BAR1_SIZE_128M 0xc 907#define BCE_PORT_FEATURE_BAR1_SIZE_256M 0xd 908#define BCE_PORT_FEATURE_BAR1_SIZE_512M 0xe 909#define BCE_PORT_FEATURE_BAR1_SIZE_1G 0xf 910 911#define BCE_PORT_FEATURE_WOL 0xdc 912#define BCE_PORT2_FEATURE_WOL 0x150 913#define BCE_PORT_FEATURE_WOL_DEFAULT_SHIFT_BITS 4 914#define BCE_PORT_FEATURE_WOL_DEFAULT_MASK 0x30 915#define BCE_PORT_FEATURE_WOL_DEFAULT_DISABLE 0 916#define BCE_PORT_FEATURE_WOL_DEFAULT_MAGIC 0x10 917#define BCE_PORT_FEATURE_WOL_DEFAULT_ACPI 0x20 918#define BCE_PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI 0x30 919#define BCE_PORT_FEATURE_WOL_LINK_SPEED_MASK 0xf 920#define BCE_PORT_FEATURE_WOL_LINK_SPEED_AUTONEG 0 921#define BCE_PORT_FEATURE_WOL_LINK_SPEED_10HALF 1 922#define BCE_PORT_FEATURE_WOL_LINK_SPEED_10FULL 2 923#define BCE_PORT_FEATURE_WOL_LINK_SPEED_100HALF 3 924#define BCE_PORT_FEATURE_WOL_LINK_SPEED_100FULL 4 925#define BCE_PORT_FEATURE_WOL_LINK_SPEED_1000HALF 5 926#define BCE_PORT_FEATURE_WOL_LINK_SPEED_1000FULL 6 927#define BCE_PORT_FEATURE_WOL_AUTONEG_ADVERTISE_1000 0x40 928#define BCE_PORT_FEATURE_WOL_RESERVED_PAUSE_CAP 0x400 929#define BCE_PORT_FEATURE_WOL_RESERVED_ASYM_PAUSE_CAP 0x800 930 931#define BCE_PORT_FEATURE_MBA 0xe0 932#define BCE_PORT2_FEATURE_MBA 0x154 933#define BCE_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT_BITS 0 934#define BCE_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x3 935#define BCE_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0 936#define BCE_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 1 937#define BCE_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 2 938#define BCE_PORT_FEATURE_MBA_LINK_SPEED_SHIFT_BITS 2 939#define BCE_PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3c 940#define BCE_PORT_FEATURE_MBA_LINK_SPEED_AUTONEG 0 941#define BCE_PORT_FEATURE_MBA_LINK_SPEED_10HALF 0x4 942#define BCE_PORT_FEATURE_MBA_LINK_SPEED_10FULL 0x8 943#define BCE_PORT_FEATURE_MBA_LINK_SPEED_100HALF 0xc 944#define BCE_PORT_FEATURE_MBA_LINK_SPEED_100FULL 0x10 945#define BCE_PORT_FEATURE_MBA_LINK_SPEED_1000HALF 0x14 946#define BCE_PORT_FEATURE_MBA_LINK_SPEED_1000FULL 0x18 947#define BCE_PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x40 948#define BCE_PORT_FEATURE_MBA_HOTKEY_CTRL_S 0 949#define BCE_PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x80 950#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT_BITS 8 951#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0xff00 952#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0 953#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_1K 0x100 954#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x200 955#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x300 956#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x400 957#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x500 958#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x600 959#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x700 960#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x800 961#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x900 962#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0xa00 963#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0xb00 964#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0xc00 965#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0xd00 966#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0xe00 967#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0xf00 968#define BCE_PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT_BITS 16 969#define BCE_PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0xf0000 970#define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT_BITS 20 971#define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x300000 972#define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0 973#define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x100000 974#define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x200000 975#define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x300000 976 977#define BCE_PORT_FEATURE_IMD 0xe4 978#define BCE_PORT2_FEATURE_IMD 0x158 979#define BCE_PORT_FEATURE_IMD_LINK_OVERRIDE_DEFAULT 0 980#define BCE_PORT_FEATURE_IMD_LINK_OVERRIDE_ENABLE 1 981 982#define BCE_PORT_FEATURE_VLAN 0xe8 983#define BCE_PORT2_FEATURE_VLAN 0x15c 984#define BCE_PORT_FEATURE_MBA_VLAN_TAG_MASK 0xffff 985#define BCE_PORT_FEATURE_MBA_VLAN_ENABLE 0x10000 986 987#define BCE_MFW_VER_PTR 0x00000014c 988 989#define BCE_BC_STATE_RESET_TYPE 0x000001c0 990#define BCE_BC_STATE_RESET_TYPE_SIG 0x00005254 991#define BCE_BC_STATE_RESET_TYPE_SIG_MASK 0x0000ffff 992 993#define BCE_BC_STATE_RESET_TYPE_NONE \ 994 (BCE_BC_STATE_RESET_TYPE_SIG | 0x00010000) 995#define BCE_BC_STATE_RESET_TYPE_PCI \ 996 (BCE_BC_STATE_RESET_TYPE_SIG | 0x00020000) 997#define BCE_BC_STATE_RESET_TYPE_VAUX \ 998 (BCE_BC_STATE_RESET_TYPE_SIG | 0x00030000) 999#define BCE_BC_STATE_RESET_TYPE_DRV_MASK DRV_MSG_CODE 1000#define BCE_BC_STATE_RESET_TYPE_DRV_RESET \ 1001 (BCE_BC_STATE_RESET_TYPE_SIG | DRV_MSG_CODE_RESET) 1002#define BCE_BC_STATE_RESET_TYPE_DRV_UNLOAD \ 1003 (BCE_BC_STATE_RESET_TYPE_SIG | DRV_MSG_CODE_UNLOAD) 1004#define BCE_BC_STATE_RESET_TYPE_DRV_SHUTDOWN \ 1005 (BCE_BC_STATE_RESET_TYPE_SIG | DRV_MSG_CODE_SHUTDOWN) 1006#define BCE_BC_STATE_RESET_TYPE_DRV_WOL \ 1007 (BCE_BC_STATE_RESET_TYPE_SIG | DRV_MSG_CODE_WOL) 1008#define BCE_BC_STATE_RESET_TYPE_DRV_DIAG \ 1009 (BCE_BC_STATE_RESET_TYPE_SIG | DRV_MSG_CODE_DIAG) 1010#define BCE_BC_STATE_RESET_TYPE_VALUE(msg) \ 1011 (BCE_BC_STATE_RESET_TYPE_SIG | (msg)) 1012 1013#define BCE_BC_RESET_TYPE 0x000001c0 1014 1015#define BCE_BC_STATE 0x000001c4 1016#define BCE_BC_STATE_ERR_MASK 0x0000ff00 1017#define BCE_BC_STATE_SIGN 0x42530000 1018#define BCE_BC_STATE_SIGN_MASK 0xffff0000 1019#define BCE_BC_STATE_BC1_START (BCE_BC_STATE_SIGN | 0x1) 1020#define BCE_BC_STATE_GET_NVM_CFG1 (BCE_BC_STATE_SIGN | 0x2) 1021#define BCE_BC_STATE_PROG_BAR (BCE_BC_STATE_SIGN | 0x3) 1022#define BCE_BC_STATE_INIT_VID (BCE_BC_STATE_SIGN | 0x4) 1023#define BCE_BC_STATE_GET_NVM_CFG2 (BCE_BC_STATE_SIGN | 0x5) 1024#define BCE_BC_STATE_APPLY_WKARND (BCE_BC_STATE_SIGN | 0x6) 1025#define BCE_BC_STATE_LOAD_BC2 (BCE_BC_STATE_SIGN | 0x7) 1026#define BCE_BC_STATE_GOING_BC2 (BCE_BC_STATE_SIGN | 0x8) 1027#define BCE_BC_STATE_GOING_DIAG (BCE_BC_STATE_SIGN | 0x9) 1028#define BCE_BC_STATE_RT_FINAL_INIT (BCE_BC_STATE_SIGN | 0x81) 1029#define BCE_BC_STATE_RT_WKARND (BCE_BC_STATE_SIGN | 0x82) 1030#define BCE_BC_STATE_RT_DRV_PULSE (BCE_BC_STATE_SIGN | 0x83) 1031#define BCE_BC_STATE_RT_FIOEVTS (BCE_BC_STATE_SIGN | 0x84) 1032#define BCE_BC_STATE_RT_DRV_CMD (BCE_BC_STATE_SIGN | 0x85) 1033#define BCE_BC_STATE_RT_LOW_POWER (BCE_BC_STATE_SIGN | 0x86) 1034#define BCE_BC_STATE_RT_SET_WOL (BCE_BC_STATE_SIGN | 0x87) 1035#define BCE_BC_STATE_RT_OTHER_FW (BCE_BC_STATE_SIGN | 0x88) 1036#define BCE_BC_STATE_RT_GOING_D3 (BCE_BC_STATE_SIGN | 0x89) 1037#define BCE_BC_STATE_ERR_BAD_VERSION (BCE_BC_STATE_SIGN | 0x0100) 1038#define BCE_BC_STATE_ERR_BAD_BC2_CRC (BCE_BC_STATE_SIGN | 0x0200) 1039#define BCE_BC_STATE_ERR_BC1_LOOP (BCE_BC_STATE_SIGN | 0x0300) 1040#define BCE_BC_STATE_ERR_UNKNOWN_CMD (BCE_BC_STATE_SIGN | 0x0400) 1041#define BCE_BC_STATE_ERR_DRV_DEAD (BCE_BC_STATE_SIGN | 0x0500) 1042#define BCE_BC_STATE_ERR_NO_RXP (BCE_BC_STATE_SIGN | 0x0600) 1043#define BCE_BC_STATE_ERR_TOO_MANY_RBUF (BCE_BC_STATE_SIGN | 0x0700) 1044 1045#define BCE_BC_STATE_CONDITION 0x000001c8 1046#define BCE_CONDITION_INIT_POR 0x00000001 1047#define BCE_CONDITION_INIT_VAUX_AVAIL 0x00000002 1048#define BCE_CONDITION_INIT_PCI_AVAIL 0x00000004 1049#define BCE_CONDITION_INIT_PCI_RESET 0x00000008 1050#define BCE_CONDITION_INIT_HD_RESET 0x00000010 /* 5709/16 only */ 1051#define BCE_CONDITION_DRV_PRESENT 0x00000100 1052#define BCE_CONDITION_LOW_POWER_LINK 0x00000200 1053#define BCE_CONDITION_CORE_RST_OCCURRED 0x00000400 /* 5709/16 only */ 1054#define BCE_CONDITION_UNUSED 0x00000800 1055#define BCE_CONDITION_BUSY_EXPROM 0x00001000 /* 5706/08 only */ 1056 1057#define BCE_CONDITION_MFW_RUN_UNKNOWN 0x00000000 1058#define BCE_CONDITION_MFW_RUN_IPMI 0x00002000 1059#define BCE_CONDITION_MFW_RUN_UMP 0x00004000 1060#define BCE_CONDITION_MFW_RUN_NCSI 0x00006000 1061#define BCE_CONDITION_MFW_RUN_NONE 0x0000e000 1062#define BCE_CONDITION_MFW_RUN_MASK 0x0000e000 1063 1064/* 5709/16 only */ 1065#define BCE_CONDITION_PM_STATE_MASK 0x00030000 1066#define BCE_CONDITION_PM_STATE_FULL 0x00030000 1067#define BCE_CONDITION_PM_STATE_PREP 0x00020000 1068#define BCE_CONDITION_PM_STATE_UNPREP 0x00010000 1069#define BCE_CONDITION_PM_RESERVED 0x00000000 1070 1071/* 5709/16 only */ 1072#define BCE_CONDITION_RXMODE_KEEP_VLAN 0x00040000 1073#define BCE_CONDITION_DRV_WOL_ENABLED 0x00080000 1074#define BCE_CONDITION_PORT_DISABLED 0x00100000 1075#define BCE_CONDITION_DRV_MAYBE_OUT 0x00200000 1076#define BCE_CONDITION_DPFW_DEAD 0x00400000 1077 1078#define BCE_BC_STATE_DEBUG_CMD 0x000001dc 1079#define BCE_BC_STATE_BC_DBG_CMD_SIGNATURE 0x42440000 1080#define BCE_BC_STATE_BC_DBG_CMD_SIGNATURE_MASK 0xffff0000 1081#define BCE_BC_STATE_BC_DBG_CMD_LOOP_CNT_MASK 0xffff 1082#define BCE_BC_STATE_BC_DBG_CMD_LOOP_INFINITE 0xffff 1083 1084#define HOST_VIEW_SHMEM_BASE 0x167c00 1085 1086/* 1087 * PCI registers defined in the PCI 2.2 spec. 1088 */ 1089#define BCE_PCI_PCIX_CMD 0x42 1090 1091 1092/****************************************************************************/ 1093/* Convenience definitions. */ 1094/****************************************************************************/ 1095#define BCE_PRINTF(fmt, args...) \ 1096 device_printf(sc->bce_dev, fmt, ##args) 1097 1098#define BCE_LOCK_INIT(_sc, _name) \ 1099 mtx_init(&(_sc)->bce_mtx, _name, MTX_NETWORK_LOCK, MTX_DEF) 1100#define BCE_LOCK(_sc) mtx_lock(&(_sc)->bce_mtx) 1101#define BCE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->bce_mtx, MA_OWNED) 1102#define BCE_UNLOCK(_sc) mtx_unlock(&(_sc)->bce_mtx) 1103#define BCE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->bce_mtx) 1104 1105#ifdef BCE_DEBUG 1106#define REG_WR(sc, offset, val) bce_reg_wr(sc, offset, val) 1107#define REG_WR16(sc, offset, val) bce_reg_wr16(sc, offset, val) 1108#define REG_RD(sc, offset) bce_reg_rd(sc, offset) 1109#else 1110#define REG_WR(sc, offset, val) \ 1111 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, offset, val) 1112#define REG_WR16(sc, offset, val) \ 1113 bus_space_write_2(sc->bce_btag, sc->bce_bhandle, offset, val) 1114#define REG_RD(sc, offset) \ 1115 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, offset) 1116#endif 1117 1118#define REG_RD_IND(sc, offset) bce_reg_rd_ind(sc, offset) 1119#define REG_WR_IND(sc, offset, val) bce_reg_wr_ind(sc, offset, val) 1120#define CTX_WR(sc, cid_addr, offset, val)bce_ctx_wr(sc, cid_addr, offset, val) 1121#define CTX_RD(sc, cid_addr, offset) bce_ctx_rd(sc, cid_addr, offset) 1122 1123#define BCE_SETBIT(sc, reg, x) \ 1124 REG_WR(sc, reg, (REG_RD(sc, reg) | (x))) 1125#define BCE_CLRBIT(sc, reg, x) \ 1126 REG_WR(sc, reg, (REG_RD(sc, reg) & ~(x))) 1127#define PCI_SETBIT(dev, reg, x, s) \ 1128 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | (x)), s) 1129#define PCI_CLRBIT(dev, reg, x, s) \ 1130 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s) 1131 1132#define BCE_STATS(x) (u_long) stats->stat_ ## x ## _lo 1133 1134#if (BUS_SPACE_MAXADDR > 0xFFFFFFFF) 1135#define BCE_ADDR_LO(y) ((u64) (y) & 0xFFFFFFFF) 1136#define BCE_ADDR_HI(y) ((u64) (y) >> 32) 1137#else 1138#define BCE_ADDR_LO(y) ((u32)y) 1139#define BCE_ADDR_HI(y) (0) 1140#endif 1141 1142 1143/****************************************************************************/ 1144/* Do not modify any of the following data structures, they are generated */ 1145/* from RTL code. */ 1146/* */ 1147/* Begin machine generated definitions. */ 1148/****************************************************************************/ 1149 1150/* 1151 * tx_bd definition 1152 */ 1153struct tx_bd { 1154 u32 tx_bd_haddr_hi; 1155 u32 tx_bd_haddr_lo; 1156 u32 tx_bd_mss_nbytes; 1157 u16 tx_bd_flags; 1158#define TX_BD_FLAGS_CONN_FAULT (1<<0) 1159#define TX_BD_FLAGS_TCP_UDP_CKSUM (1<<1) 1160#define TX_BD_FLAGS_IP_CKSUM (1<<2) 1161#define TX_BD_FLAGS_VLAN_TAG (1<<3) 1162#define TX_BD_FLAGS_COAL_NOW (1<<4) 1163#define TX_BD_FLAGS_DONT_GEN_CRC (1<<5) 1164#define TX_BD_FLAGS_END (1<<6) 1165#define TX_BD_FLAGS_START (1<<7) 1166#define TX_BD_FLAGS_SW_OPTION_WORD (0x1f<<8) 1167#define TX_BD_FLAGS_SW_FLAGS (1<<13) 1168#define TX_BD_FLAGS_SW_SNAP (1<<14) 1169#define TX_BD_FLAGS_SW_LSO (1<<15) 1170 u16 tx_bd_vlan_tag; 1171}; 1172 1173 1174/* 1175 * rx_bd definition 1176 */ 1177struct rx_bd { 1178 u32 rx_bd_haddr_hi; 1179 u32 rx_bd_haddr_lo; 1180 u32 rx_bd_len; 1181 u32 rx_bd_flags; 1182#define RX_BD_FLAGS_NOPUSH (1<<0) 1183#define RX_BD_FLAGS_DUMMY (1<<1) 1184#define RX_BD_FLAGS_END (1<<2) 1185#define RX_BD_FLAGS_START (1<<3) 1186}; 1187 1188 1189/* 1190 * status_block definition 1191 */ 1192struct status_block { 1193 u32 status_attn_bits; 1194 #define STATUS_ATTN_BITS_LINK_STATE (1L<<0) 1195 #define STATUS_ATTN_BITS_TX_SCHEDULER_ABORT (1L<<1) 1196 #define STATUS_ATTN_BITS_TX_BD_READ_ABORT (1L<<2) 1197 #define STATUS_ATTN_BITS_TX_BD_CACHE_ABORT (1L<<3) 1198 #define STATUS_ATTN_BITS_TX_PROCESSOR_ABORT (1L<<4) 1199 #define STATUS_ATTN_BITS_TX_DMA_ABORT (1L<<5) 1200 #define STATUS_ATTN_BITS_TX_PATCHUP_ABORT (1L<<6) 1201 #define STATUS_ATTN_BITS_TX_ASSEMBLER_ABORT (1L<<7) 1202 #define STATUS_ATTN_BITS_RX_PARSER_MAC_ABORT (1L<<8) 1203 #define STATUS_ATTN_BITS_RX_PARSER_CATCHUP_ABORT (1L<<9) 1204 #define STATUS_ATTN_BITS_RX_MBUF_ABORT (1L<<10) 1205 #define STATUS_ATTN_BITS_RX_LOOKUP_ABORT (1L<<11) 1206 #define STATUS_ATTN_BITS_RX_PROCESSOR_ABORT (1L<<12) 1207 #define STATUS_ATTN_BITS_RX_V2P_ABORT (1L<<13) 1208 #define STATUS_ATTN_BITS_RX_BD_CACHE_ABORT (1L<<14) 1209 #define STATUS_ATTN_BITS_RX_DMA_ABORT (1L<<15) 1210 #define STATUS_ATTN_BITS_COMPLETION_ABORT (1L<<16) 1211 #define STATUS_ATTN_BITS_HOST_COALESCE_ABORT (1L<<17) 1212 #define STATUS_ATTN_BITS_MAILBOX_QUEUE_ABORT (1L<<18) 1213 #define STATUS_ATTN_BITS_CONTEXT_ABORT (1L<<19) 1214 #define STATUS_ATTN_BITS_CMD_SCHEDULER_ABORT (1L<<20) 1215 #define STATUS_ATTN_BITS_CMD_PROCESSOR_ABORT (1L<<21) 1216 #define STATUS_ATTN_BITS_MGMT_PROCESSOR_ABORT (1L<<22) 1217 #define STATUS_ATTN_BITS_MAC_ABORT (1L<<23) 1218 #define STATUS_ATTN_BITS_TIMER_ABORT (1L<<24) 1219 #define STATUS_ATTN_BITS_DMAE_ABORT (1L<<25) 1220 #define STATUS_ATTN_BITS_FLSH_ABORT (1L<<26) 1221 #define STATUS_ATTN_BITS_GRC_ABORT (1L<<27) 1222 #define STATUS_ATTN_BITS_PARITY_ERROR (1L<<31) 1223 1224 u32 status_attn_bits_ack; 1225#if defined(__BIG_ENDIAN) 1226 u16 status_tx_quick_consumer_index0; 1227 u16 status_tx_quick_consumer_index1; 1228 u16 status_tx_quick_consumer_index2; 1229 u16 status_tx_quick_consumer_index3; 1230 u16 status_rx_quick_consumer_index0; 1231 u16 status_rx_quick_consumer_index1; 1232 u16 status_rx_quick_consumer_index2; 1233 u16 status_rx_quick_consumer_index3; 1234 u16 status_rx_quick_consumer_index4; 1235 u16 status_rx_quick_consumer_index5; 1236 u16 status_rx_quick_consumer_index6; 1237 u16 status_rx_quick_consumer_index7; 1238 u16 status_rx_quick_consumer_index8; 1239 u16 status_rx_quick_consumer_index9; 1240 u16 status_rx_quick_consumer_index10; 1241 u16 status_rx_quick_consumer_index11; 1242 u16 status_rx_quick_consumer_index12; 1243 u16 status_rx_quick_consumer_index13; 1244 u16 status_rx_quick_consumer_index14; 1245 u16 status_rx_quick_consumer_index15; 1246 u16 status_completion_producer_index; 1247 u16 status_cmd_consumer_index; 1248 u16 status_idx; 1249 u16 status_unused; 1250#elif defined(__LITTLE_ENDIAN) 1251 u16 status_tx_quick_consumer_index1; 1252 u16 status_tx_quick_consumer_index0; 1253 u16 status_tx_quick_consumer_index3; 1254 u16 status_tx_quick_consumer_index2; 1255 u16 status_rx_quick_consumer_index1; 1256 u16 status_rx_quick_consumer_index0; 1257 u16 status_rx_quick_consumer_index3; 1258 u16 status_rx_quick_consumer_index2; 1259 u16 status_rx_quick_consumer_index5; 1260 u16 status_rx_quick_consumer_index4; 1261 u16 status_rx_quick_consumer_index7; 1262 u16 status_rx_quick_consumer_index6; 1263 u16 status_rx_quick_consumer_index9; 1264 u16 status_rx_quick_consumer_index8; 1265 u16 status_rx_quick_consumer_index11; 1266 u16 status_rx_quick_consumer_index10; 1267 u16 status_rx_quick_consumer_index13; 1268 u16 status_rx_quick_consumer_index12; 1269 u16 status_rx_quick_consumer_index15; 1270 u16 status_rx_quick_consumer_index14; 1271 u16 status_cmd_consumer_index; 1272 u16 status_completion_producer_index; 1273 u16 status_unused; 1274 u16 status_idx; 1275#endif 1276}; 1277 1278 1279/* 1280 * statistics_block definition 1281 */ 1282struct statistics_block { 1283 u32 stat_IfHCInOctets_hi; 1284 u32 stat_IfHCInOctets_lo; 1285 u32 stat_IfHCInBadOctets_hi; 1286 u32 stat_IfHCInBadOctets_lo; 1287 u32 stat_IfHCOutOctets_hi; 1288 u32 stat_IfHCOutOctets_lo; 1289 u32 stat_IfHCOutBadOctets_hi; 1290 u32 stat_IfHCOutBadOctets_lo; 1291 u32 stat_IfHCInUcastPkts_hi; 1292 u32 stat_IfHCInUcastPkts_lo; 1293 u32 stat_IfHCInMulticastPkts_hi; 1294 u32 stat_IfHCInMulticastPkts_lo; 1295 u32 stat_IfHCInBroadcastPkts_hi; 1296 u32 stat_IfHCInBroadcastPkts_lo; 1297 u32 stat_IfHCOutUcastPkts_hi; 1298 u32 stat_IfHCOutUcastPkts_lo; 1299 u32 stat_IfHCOutMulticastPkts_hi; 1300 u32 stat_IfHCOutMulticastPkts_lo; 1301 u32 stat_IfHCOutBroadcastPkts_hi; 1302 u32 stat_IfHCOutBroadcastPkts_lo; 1303 u32 stat_emac_tx_stat_dot3statsinternalmactransmiterrors; 1304 u32 stat_Dot3StatsCarrierSenseErrors; 1305 u32 stat_Dot3StatsFCSErrors; 1306 u32 stat_Dot3StatsAlignmentErrors; 1307 u32 stat_Dot3StatsSingleCollisionFrames; 1308 u32 stat_Dot3StatsMultipleCollisionFrames; 1309 u32 stat_Dot3StatsDeferredTransmissions; 1310 u32 stat_Dot3StatsExcessiveCollisions; 1311 u32 stat_Dot3StatsLateCollisions; 1312 u32 stat_EtherStatsCollisions; 1313 u32 stat_EtherStatsFragments; 1314 u32 stat_EtherStatsJabbers; 1315 u32 stat_EtherStatsUndersizePkts; 1316 u32 stat_EtherStatsOversizePkts; 1317 u32 stat_EtherStatsPktsRx64Octets; 1318 u32 stat_EtherStatsPktsRx65Octetsto127Octets; 1319 u32 stat_EtherStatsPktsRx128Octetsto255Octets; 1320 u32 stat_EtherStatsPktsRx256Octetsto511Octets; 1321 u32 stat_EtherStatsPktsRx512Octetsto1023Octets; 1322 u32 stat_EtherStatsPktsRx1024Octetsto1522Octets; 1323 u32 stat_EtherStatsPktsRx1523Octetsto9022Octets; 1324 u32 stat_EtherStatsPktsTx64Octets; 1325 u32 stat_EtherStatsPktsTx65Octetsto127Octets; 1326 u32 stat_EtherStatsPktsTx128Octetsto255Octets; 1327 u32 stat_EtherStatsPktsTx256Octetsto511Octets; 1328 u32 stat_EtherStatsPktsTx512Octetsto1023Octets; 1329 u32 stat_EtherStatsPktsTx1024Octetsto1522Octets; 1330 u32 stat_EtherStatsPktsTx1523Octetsto9022Octets; 1331 u32 stat_XonPauseFramesReceived; 1332 u32 stat_XoffPauseFramesReceived; 1333 u32 stat_OutXonSent; 1334 u32 stat_OutXoffSent; 1335 u32 stat_FlowControlDone; 1336 u32 stat_MacControlFramesReceived; 1337 u32 stat_XoffStateEntered; 1338 u32 stat_IfInFramesL2FilterDiscards; 1339 u32 stat_IfInRuleCheckerDiscards; 1340 u32 stat_IfInFTQDiscards; 1341 u32 stat_IfInMBUFDiscards; 1342 u32 stat_IfInRuleCheckerP4Hit; 1343 u32 stat_CatchupInRuleCheckerDiscards; 1344 u32 stat_CatchupInFTQDiscards; 1345 u32 stat_CatchupInMBUFDiscards; 1346 u32 stat_CatchupInRuleCheckerP4Hit; 1347 u32 stat_GenStat00; 1348 u32 stat_GenStat01; 1349 u32 stat_GenStat02; 1350 u32 stat_GenStat03; 1351 u32 stat_GenStat04; 1352 u32 stat_GenStat05; 1353 u32 stat_GenStat06; 1354 u32 stat_GenStat07; 1355 u32 stat_GenStat08; 1356 u32 stat_GenStat09; 1357 u32 stat_GenStat10; 1358 u32 stat_GenStat11; 1359 u32 stat_GenStat12; 1360 u32 stat_GenStat13; 1361 u32 stat_GenStat14; 1362 u32 stat_GenStat15; 1363}; 1364 1365 1366/* 1367 * l2_fhdr definition 1368 */ 1369struct l2_fhdr { 1370 u32 l2_fhdr_status; 1371 #define L2_FHDR_STATUS_RULE_CLASS (0x7<<0) 1372 #define L2_FHDR_STATUS_RULE_P2 (1<<3) 1373 #define L2_FHDR_STATUS_RULE_P3 (1<<4) 1374 #define L2_FHDR_STATUS_RULE_P4 (1<<5) 1375 #define L2_FHDR_STATUS_L2_VLAN_TAG (1<<6) 1376 #define L2_FHDR_STATUS_L2_LLC_SNAP (1<<7) 1377 #define L2_FHDR_STATUS_RSS_HASH (1<<8) 1378 #define L2_FHDR_STATUS_IP_DATAGRAM (1<<13) 1379 #define L2_FHDR_STATUS_TCP_SEGMENT (1<<14) 1380 #define L2_FHDR_STATUS_UDP_DATAGRAM (1<<15) 1381 1382 #define L2_FHDR_STATUS_SPLIT (1<<16) 1383 #define L2_FHDR_ERRORS_BAD_CRC (1<<17) 1384 #define L2_FHDR_ERRORS_PHY_DECODE (1<<18) 1385 #define L2_FHDR_ERRORS_ALIGNMENT (1<<19) 1386 #define L2_FHDR_ERRORS_TOO_SHORT (1<<20) 1387 #define L2_FHDR_ERRORS_GIANT_FRAME (1<<21) 1388 #define L2_FHDR_ERRORS_IPV4_BAD_LEN (1<<22) 1389 #define L2_FHDR_ERRORS_TCP_XSUM (1<<28) 1390 #define L2_FHDR_ERRORS_UDP_XSUM (1<<31) 1391 1392 u32 l2_fhdr_hash; 1393#if defined(__BIG_ENDIAN) 1394 u16 l2_fhdr_pkt_len; 1395 u16 l2_fhdr_vlan_tag; 1396 u16 l2_fhdr_ip_xsum; 1397 u16 l2_fhdr_tcp_udp_xsum; 1398#elif defined(__LITTLE_ENDIAN) 1399 u16 l2_fhdr_vlan_tag; 1400 u16 l2_fhdr_pkt_len; 1401 u16 l2_fhdr_tcp_udp_xsum; 1402 u16 l2_fhdr_ip_xsum; 1403#endif 1404}; 1405 1406#define BCE_L2FHDR_PRINTFB \ 1407 "\20" \ 1408 "\40UDP_XSUM_ERR" \ 1409 "\37b30" \ 1410 "\36b29" \ 1411 "\35TCP_XSUM_ERR" \ 1412 "\34b27" \ 1413 "\33b26" \ 1414 "\32b25" \ 1415 "\31b24" \ 1416 "\30b23" \ 1417 "\27IPv4_BAL_LEN" \ 1418 "\26GIANT_ERR" \ 1419 "\25SHORT_ERR" \ 1420 "\24ALIGN_ERR" \ 1421 "\23PHY_ERR" \ 1422 "\22CRC_ERR" \ 1423 "\21SPLIT" \ 1424 "\20UDP" \ 1425 "\17TCP" \ 1426 "\16IP" \ 1427 "\15SORT_b3" \ 1428 "\14SORT_b2" \ 1429 "\13SORT_b1" \ 1430 "\12SORT_b0" \ 1431 "\11RSS" \ 1432 "\10SNAP" \ 1433 "\07VLAN" \ 1434 "\06P4" \ 1435 "\05P3" \ 1436 "\04P2" \ 1437 "\03RULE_b2" \ 1438 "\02RULE_b1" \ 1439 "\01RULE_b0" 1440 1441 1442/* 1443 * l2_tx_context definition (5706 and 5708) 1444 */ 1445#define BCE_L2CTX_TX_TYPE 0x00000000 1446#define BCE_L2CTX_TX_TYPE_SIZE_L2 ((0xc0/0x20)<<16) 1447#define BCE_L2CTX_TX_TYPE_TYPE (0xf<<28) 1448#define BCE_L2CTX_TX_TYPE_TYPE_EMPTY (0<<28) 1449#define BCE_L2CTX_TX_TYPE_TYPE_L2 (1<<28) 1450 1451#define BCE_L2CTX_TX_HOST_BIDX 0x00000088 1452#define BCE_L2CTX_TX_EST_NBD 0x00000088 1453#define BCE_L2CTX_TX_CMD_TYPE 0x00000088 1454#define BCE_L2CTX_TX_CMD_TYPE_TYPE (0xf<<24) 1455#define BCE_L2CTX_TX_CMD_TYPE_TYPE_L2 (0<<24) 1456#define BCE_L2CTX_TX_CMD_TYPE_TYPE_TCP (1<<24) 1457 1458#define BCE_L2CTX_TX_HOST_BSEQ 0x00000090 1459#define BCE_L2CTX_TX_TSCH_BSEQ 0x00000094 1460#define BCE_L2CTX_TX_TBDR_BSEQ 0x00000098 1461#define BCE_L2CTX_TX_TBDR_BOFF 0x0000009c 1462#define BCE_L2CTX_TX_TBDR_BIDX 0x0000009c 1463#define BCE_L2CTX_TX_TBDR_BHADDR_HI 0x000000a0 1464#define BCE_L2CTX_TX_TBDR_BHADDR_LO 0x000000a4 1465#define BCE_L2CTX_TX_TXP_BOFF 0x000000a8 1466#define BCE_L2CTX_TX_TXP_BIDX 0x000000a8 1467#define BCE_L2CTX_TX_TXP_BSEQ 0x000000ac 1468 1469/* 1470 * l2_tx_context definition (5709 and 5716) 1471 */ 1472#define BCE_L2CTX_TX_TYPE_XI 0x00000080 1473#define BCE_L2CTX_TX_TYPE_SIZE_L2_XI ((0xc0/0x20)<<16) 1474#define BCE_L2CTX_TX_TYPE_TYPE_XI (0xf<<28) 1475#define BCE_L2CTX_TX_TYPE_TYPE_EMPTY_XI (0<<28) 1476#define BCE_L2CTX_TX_TYPE_TYPE_L2_XI (1<<28) 1477 1478#define BCE_L2CTX_TX_CMD_TYPE_XI 0x00000240 1479#define BCE_L2CTX_TX_CMD_TYPE_TYPE_XI (0xf<<24) 1480#define BCE_L2CTX_TX_CMD_TYPE_TYPE_L2_XI (0<<24) 1481#define BCE_L2CTX_TX_CMD_TYPE_TYPE_TCP_XI (1<<24) 1482 1483#define BCE_L2CTX_TX_HOST_BIDX_XI 0x00000240 1484#define BCE_L2CTX_TX_HOST_BSEQ_XI 0x00000248 1485#define BCE_L2CTX_TX_TBDR_BHADDR_HI_XI 0x00000258 1486#define BCE_L2CTX_TX_TBDR_BHADDR_LO_XI 0x0000025c 1487 1488 1489/* 1490 * l2_rx_context definition (5706, 5708, 5709, and 5716) 1491 */ 1492#define BCE_L2CTX_RX_WATER_MARK 0x00000000 1493#define BCE_L2CTX_RX_LO_WATER_MARK_SHIFT 0 1494#define BCE_L2CTX_RX_LO_WATER_MARK_DEFAULT 32 1495#define BCE_L2CTX_RX_LO_WATER_MARK_SCALE 4 1496#define BCE_L2CTX_RX_LO_WATER_MARK_DIS 0 1497#define BCE_L2CTX_RX_HI_WATER_MARK_SHIFT 4 1498#define BCE_L2CTX_RX_HI_WATER_MARK_SCALE 16 1499#define BCE_L2CTX_RX_WATER_MARKS_MSK 0x000000ff 1500 1501#define BCE_L2CTX_RX_BD_PRE_READ 0x00000000 1502#define BCE_L2CTX_RX_BD_PRE_READ_SHIFT 8 1503 1504#define BCE_L2CTX_RX_CTX_SIZE 0x00000000 1505#define BCE_L2CTX_RX_CTX_SIZE_SHIFT 16 1506#define BCE_L2CTX_RX_CTX_TYPE_SIZE_L2 \ 1507 ((0x20/20)<<BCE_L2CTX_RX_CTX_SIZE_SHIFT) 1508 1509#define BCE_L2CTX_RX_CTX_TYPE 0x00000000 1510#define BCE_L2CTX_RX_CTX_TYPE_SHIFT 24 1511 1512#define BCE_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE (0xf<<28) 1513#define BCE_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE_UNDEFINED (0<<28) 1514#define BCE_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE (1<<28) 1515 1516#define BCE_L2CTX_RX_HOST_BDIDX 0x00000004 1517#define BCE_L2CTX_RX_HOST_BSEQ 0x00000008 1518#define BCE_L2CTX_RX_NX_BSEQ 0x0000000c 1519#define BCE_L2CTX_RX_NX_BDHADDR_HI 0x00000010 1520#define BCE_L2CTX_RX_NX_BDHADDR_LO 0x00000014 1521#define BCE_L2CTX_RX_NX_BDIDX 0x00000018 1522 1523#define BCE_L2CTX_RX_HOST_PG_BDIDX 0x00000044 1524#define BCE_L2CTX_RX_PG_BUF_SIZE 0x00000048 1525#define BCE_L2CTX_RX_RBDC_KEY 0x0000004c 1526#define BCE_L2CTX_RX_RBDC_JUMBO_KEY 0x3ffe 1527#define BCE_L2CTX_RX_NX_PG_BDHADDR_HI 0x00000050 1528#define BCE_L2CTX_RX_NX_PG_BDHADDR_LO 0x00000054 1529#define BCE_L2CTX_RX_NX_PG_BDIDX 0x00000058 1530 1531 1532/* 1533 * l2_mq definitions (5706, 5708, 5709, and 5716) 1534 */ 1535 1536#define BCE_L2MQ_RX_HOST_BDIDX 0x00000004 1537#define BCE_L2MQ_RX_HOST_BSEQ 0x00000008 1538#define BCE_L2MQ_RX_HOST_PG_BDIDX 0x00000044 1539 1540#define BCE_L2MQ_TX_HOST_BIDX 0x00000088 1541#define BCE_L2MQ_TX_HOST_BSEQ 0x00000090 1542 1543/* 1544 * pci_config_l definition 1545 * offset: 0000 1546 */ 1547#define BCE_PCICFG_MISC_CONFIG 0x00000068 1548#define BCE_PCICFG_MISC_CONFIG_TARGET_BYTE_SWAP (1L<<2) 1549#define BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP (1L<<3) 1550#define BCE_PCICFG_MISC_CONFIG_CLOCK_CTL_ENA (1L<<5) 1551#define BCE_PCICFG_MISC_CONFIG_TARGET_GRC_WORD_SWAP (1L<<6) 1552#define BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA (1L<<7) 1553#define BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ (1L<<8) 1554#define BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY (1L<<9) 1555#define BCE_PCICFG_MISC_CONFIG_ASIC_METAL_REV (0xffL<<16) 1556#define BCE_PCICFG_MISC_CONFIG_ASIC_BASE_REV (0xfL<<24) 1557#define BCE_PCICFG_MISC_CONFIG_ASIC_ID (0xfL<<28) 1558#define BCE_PCICFG_MISC_CONFIG_ASIC_REV (0xffffL<<16) 1559 1560#define BCE_PCICFG_MISC_STATUS 0x0000006c 1561#define BCE_PCICFG_MISC_STATUS_INTA_VALUE (1L<<0) 1562#define BCE_PCICFG_MISC_STATUS_32BIT_DET (1L<<1) 1563#define BCE_PCICFG_MISC_STATUS_M66EN (1L<<2) 1564#define BCE_PCICFG_MISC_STATUS_PCIX_DET (1L<<3) 1565#define BCE_PCICFG_MISC_STATUS_PCIX_SPEED (0x3L<<4) 1566#define BCE_PCICFG_MISC_STATUS_PCIX_SPEED_66 (0L<<4) 1567#define BCE_PCICFG_MISC_STATUS_PCIX_SPEED_100 (1L<<4) 1568#define BCE_PCICFG_MISC_STATUS_PCIX_SPEED_133 (2L<<4) 1569#define BCE_PCICFG_MISC_STATUS_PCIX_SPEED_PCI_MODE (3L<<4) 1570 1571#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS 0x00000070 1572#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET (0xfL<<0) 1573#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ (0L<<0) 1574#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ (1L<<0) 1575#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ (2L<<0) 1576#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ (3L<<0) 1577#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ (4L<<0) 1578#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ (5L<<0) 1579#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ (6L<<0) 1580#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ (7L<<0) 1581#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW (0xfL<<0) 1582#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE (1L<<6) 1583#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT (1L<<7) 1584#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC (0x7L<<8) 1585#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF (0L<<8) 1586#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12 (1L<<8) 1587#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6 (2L<<8) 1588#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62 (4L<<8) 1589#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PLAY_DEAD (1L<<11) 1590#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED (0xfL<<12) 1591#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100 (0L<<12) 1592#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80 (1L<<12) 1593#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50 (2L<<12) 1594#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40 (4L<<12) 1595#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25 (8L<<12) 1596#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP (1L<<16) 1597#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_PLL_STOP (1L<<17) 1598#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_18 (1L<<18) 1599#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_USE_SPD_DET (1L<<19) 1600#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED (0xfffL<<20) 1601 1602#define BCE_PCICFG_REG_WINDOW_ADDRESS 0x00000078 1603#define BCE_PCICFG_REG_WINDOW 0x00000080 1604#define BCE_PCICFG_INT_ACK_CMD 0x00000084 1605#define BCE_PCICFG_INT_ACK_CMD_INDEX (0xffffL<<0) 1606#define BCE_PCICFG_INT_ACK_CMD_INDEX_VALID (1L<<16) 1607#define BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM (1L<<17) 1608#define BCE_PCICFG_INT_ACK_CMD_MASK_INT (1L<<18) 1609 1610#define BCE_PCICFG_STATUS_BIT_SET_CMD 0x00000088 1611#define BCE_PCICFG_STATUS_BIT_CLEAR_CMD 0x0000008c 1612#define BCE_PCICFG_MAILBOX_QUEUE_ADDR 0x00000090 1613#define BCE_PCICFG_MAILBOX_QUEUE_DATA 0x00000094 1614 1615 1616/* 1617 * pci_reg definition 1618 * offset: 0x400 1619 */ 1620#define BCE_PCI_GRC_WINDOW_ADDR 0x00000400 1621#define BCE_PCI_GRC_WINDOW_ADDR_PCI_GRC_WINDOW_ADDR_VALUE (0x3ffffL<<8) 1622 1623#define BCE_PCI_CONFIG_1 0x00000404 1624#define BCE_PCI_CONFIG_1_READ_BOUNDARY (0x7L<<8) 1625#define BCE_PCI_CONFIG_1_READ_BOUNDARY_OFF (0L<<8) 1626#define BCE_PCI_CONFIG_1_READ_BOUNDARY_16 (1L<<8) 1627#define BCE_PCI_CONFIG_1_READ_BOUNDARY_32 (2L<<8) 1628#define BCE_PCI_CONFIG_1_READ_BOUNDARY_64 (3L<<8) 1629#define BCE_PCI_CONFIG_1_READ_BOUNDARY_128 (4L<<8) 1630#define BCE_PCI_CONFIG_1_READ_BOUNDARY_256 (5L<<8) 1631#define BCE_PCI_CONFIG_1_READ_BOUNDARY_512 (6L<<8) 1632#define BCE_PCI_CONFIG_1_READ_BOUNDARY_1024 (7L<<8) 1633#define BCE_PCI_CONFIG_1_WRITE_BOUNDARY (0x7L<<11) 1634#define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_OFF (0L<<11) 1635#define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_16 (1L<<11) 1636#define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_32 (2L<<11) 1637#define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_64 (3L<<11) 1638#define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_128 (4L<<11) 1639#define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_256 (5L<<11) 1640#define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_512 (6L<<11) 1641#define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_1024 (7L<<11) 1642 1643#define BCE_PCI_CONFIG_2 0x00000408 1644#define BCE_PCI_CONFIG_2_BAR1_SIZE (0xfL<<0) 1645#define BCE_PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0) 1646#define BCE_PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0) 1647#define BCE_PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0) 1648#define BCE_PCI_CONFIG_2_BAR1_SIZE_256K (3L<<0) 1649#define BCE_PCI_CONFIG_2_BAR1_SIZE_512K (4L<<0) 1650#define BCE_PCI_CONFIG_2_BAR1_SIZE_1M (5L<<0) 1651#define BCE_PCI_CONFIG_2_BAR1_SIZE_2M (6L<<0) 1652#define BCE_PCI_CONFIG_2_BAR1_SIZE_4M (7L<<0) 1653#define BCE_PCI_CONFIG_2_BAR1_SIZE_8M (8L<<0) 1654#define BCE_PCI_CONFIG_2_BAR1_SIZE_16M (9L<<0) 1655#define BCE_PCI_CONFIG_2_BAR1_SIZE_32M (10L<<0) 1656#define BCE_PCI_CONFIG_2_BAR1_SIZE_64M (11L<<0) 1657#define BCE_PCI_CONFIG_2_BAR1_SIZE_128M (12L<<0) 1658#define BCE_PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0) 1659#define BCE_PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0) 1660#define BCE_PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0) 1661#define BCE_PCI_CONFIG_2_BAR1_64ENA (1L<<4) 1662#define BCE_PCI_CONFIG_2_EXP_ROM_RETRY (1L<<5) 1663#define BCE_PCI_CONFIG_2_CFG_CYCLE_RETRY (1L<<6) 1664#define BCE_PCI_CONFIG_2_FIRST_CFG_DONE (1L<<7) 1665#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8) 1666#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8) 1667#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_1K (1L<<8) 1668#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_2K (2L<<8) 1669#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_4K (3L<<8) 1670#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_8K (4L<<8) 1671#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_16K (5L<<8) 1672#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_32K (6L<<8) 1673#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_64K (7L<<8) 1674#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_128K (8L<<8) 1675#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_256K (9L<<8) 1676#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_512K (10L<<8) 1677#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_1M (11L<<8) 1678#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_2M (12L<<8) 1679#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_4M (13L<<8) 1680#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_8M (14L<<8) 1681#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_16M (15L<<8) 1682#define BCE_PCI_CONFIG_2_MAX_SPLIT_LIMIT (0x1fL<<16) 1683#define BCE_PCI_CONFIG_2_MAX_READ_LIMIT (0x3L<<21) 1684#define BCE_PCI_CONFIG_2_MAX_READ_LIMIT_512 (0L<<21) 1685#define BCE_PCI_CONFIG_2_MAX_READ_LIMIT_1K (1L<<21) 1686#define BCE_PCI_CONFIG_2_MAX_READ_LIMIT_2K (2L<<21) 1687#define BCE_PCI_CONFIG_2_MAX_READ_LIMIT_4K (3L<<21) 1688#define BCE_PCI_CONFIG_2_FORCE_32_BIT_MSTR (1L<<23) 1689#define BCE_PCI_CONFIG_2_FORCE_32_BIT_TGT (1L<<24) 1690#define BCE_PCI_CONFIG_2_KEEP_REQ_ASSERT (1L<<25) 1691 1692#define BCE_PCI_CONFIG_3 0x0000040c 1693#define BCE_PCI_CONFIG_3_STICKY_BYTE (0xffL<<0) 1694#define BCE_PCI_CONFIG_3_FORCE_PME (1L<<24) 1695#define BCE_PCI_CONFIG_3_PME_STATUS (1L<<25) 1696#define BCE_PCI_CONFIG_3_PME_ENABLE (1L<<26) 1697#define BCE_PCI_CONFIG_3_PM_STATE (0x3L<<27) 1698#define BCE_PCI_CONFIG_3_VAUX_PRESET (1L<<30) 1699#define BCE_PCI_CONFIG_3_PCI_POWER (1L<<31) 1700 1701#define BCE_PCI_PM_DATA_A 0x00000410 1702#define BCE_PCI_PM_DATA_A_PM_DATA_0_PRG (0xffL<<0) 1703#define BCE_PCI_PM_DATA_A_PM_DATA_1_PRG (0xffL<<8) 1704#define BCE_PCI_PM_DATA_A_PM_DATA_2_PRG (0xffL<<16) 1705#define BCE_PCI_PM_DATA_A_PM_DATA_3_PRG (0xffL<<24) 1706 1707#define BCE_PCI_PM_DATA_B 0x00000414 1708#define BCE_PCI_PM_DATA_B_PM_DATA_4_PRG (0xffL<<0) 1709#define BCE_PCI_PM_DATA_B_PM_DATA_5_PRG (0xffL<<8) 1710#define BCE_PCI_PM_DATA_B_PM_DATA_6_PRG (0xffL<<16) 1711#define BCE_PCI_PM_DATA_B_PM_DATA_7_PRG (0xffL<<24) 1712 1713#define BCE_PCI_SWAP_DIAG0 0x00000418 1714#define BCE_PCI_SWAP_DIAG1 0x0000041c 1715#define BCE_PCI_EXP_ROM_ADDR 0x00000420 1716#define BCE_PCI_EXP_ROM_ADDR_ADDRESS (0x3fffffL<<2) 1717#define BCE_PCI_EXP_ROM_ADDR_REQ (1L<<31) 1718 1719#define BCE_PCI_EXP_ROM_DATA 0x00000424 1720#define BCE_PCI_VPD_INTF 0x00000428 1721#define BCE_PCI_VPD_INTF_INTF_REQ (1L<<0) 1722 1723#define BCE_PCI_VPD_ADDR_FLAG 0x0000042c 1724#define BCE_PCI_VPD_ADDR_FLAG_ADDRESS (0x1fff<<2) 1725#define BCE_PCI_VPD_ADDR_FLAG_WR (1<<15) 1726 1727#define BCE_PCI_VPD_DATA 0x00000430 1728#define BCE_PCI_ID_VAL1 0x00000434 1729#define BCE_PCI_ID_VAL1_DEVICE_ID (0xffffL<<0) 1730#define BCE_PCI_ID_VAL1_VENDOR_ID (0xffffL<<16) 1731 1732#define BCE_PCI_ID_VAL2 0x00000438 1733#define BCE_PCI_ID_VAL2_SUBSYSTEM_VENDOR_ID (0xffffL<<0) 1734#define BCE_PCI_ID_VAL2_SUBSYSTEM_ID (0xffffL<<16) 1735 1736#define BCE_PCI_ID_VAL3 0x0000043c 1737#define BCE_PCI_ID_VAL3_CLASS_CODE (0xffffffL<<0) 1738#define BCE_PCI_ID_VAL3_REVISION_ID (0xffL<<24) 1739 1740#define BCE_PCI_ID_VAL4 0x00000440 1741#define BCE_PCI_ID_VAL4_CAP_ENA (0xfL<<0) 1742#define BCE_PCI_ID_VAL4_CAP_ENA_0 (0L<<0) 1743#define BCE_PCI_ID_VAL4_CAP_ENA_1 (1L<<0) 1744#define BCE_PCI_ID_VAL4_CAP_ENA_2 (2L<<0) 1745#define BCE_PCI_ID_VAL4_CAP_ENA_3 (3L<<0) 1746#define BCE_PCI_ID_VAL4_CAP_ENA_4 (4L<<0) 1747#define BCE_PCI_ID_VAL4_CAP_ENA_5 (5L<<0) 1748#define BCE_PCI_ID_VAL4_CAP_ENA_6 (6L<<0) 1749#define BCE_PCI_ID_VAL4_CAP_ENA_7 (7L<<0) 1750#define BCE_PCI_ID_VAL4_CAP_ENA_8 (8L<<0) 1751#define BCE_PCI_ID_VAL4_CAP_ENA_9 (9L<<0) 1752#define BCE_PCI_ID_VAL4_CAP_ENA_10 (10L<<0) 1753#define BCE_PCI_ID_VAL4_CAP_ENA_11 (11L<<0) 1754#define BCE_PCI_ID_VAL4_CAP_ENA_12 (12L<<0) 1755#define BCE_PCI_ID_VAL4_CAP_ENA_13 (13L<<0) 1756#define BCE_PCI_ID_VAL4_CAP_ENA_14 (14L<<0) 1757#define BCE_PCI_ID_VAL4_CAP_ENA_15 (15L<<0) 1758#define BCE_PCI_ID_VAL4_PM_SCALE_PRG (0x3L<<6) 1759#define BCE_PCI_ID_VAL4_PM_SCALE_PRG_0 (0L<<6) 1760#define BCE_PCI_ID_VAL4_PM_SCALE_PRG_1 (1L<<6) 1761#define BCE_PCI_ID_VAL4_PM_SCALE_PRG_2 (2L<<6) 1762#define BCE_PCI_ID_VAL4_PM_SCALE_PRG_3 (3L<<6) 1763#define BCE_PCI_ID_VAL4_MSI_LIMIT (0x7L<<9) 1764#define BCE_PCI_ID_VAL4_MSI_ADVERTIZE (0x7L<<12) 1765#define BCE_PCI_ID_VAL4_MSI_ENABLE (1L<<15) 1766#define BCE_PCI_ID_VAL4_MAX_64_ADVERTIZE (1L<<16) 1767#define BCE_PCI_ID_VAL4_MAX_133_ADVERTIZE (1L<<17) 1768#define BCE_PCI_ID_VAL4_MAX_MEM_READ_SIZE (0x3L<<21) 1769#define BCE_PCI_ID_VAL4_MAX_SPLIT_SIZE (0x7L<<23) 1770#define BCE_PCI_ID_VAL4_MAX_CUMULATIVE_SIZE (0x7L<<26) 1771 1772#define BCE_PCI_ID_VAL5 0x00000444 1773#define BCE_PCI_ID_VAL5_D1_SUPPORT (1L<<0) 1774#define BCE_PCI_ID_VAL5_D2_SUPPORT (1L<<1) 1775#define BCE_PCI_ID_VAL5_PME_IN_D0 (1L<<2) 1776#define BCE_PCI_ID_VAL5_PME_IN_D1 (1L<<3) 1777#define BCE_PCI_ID_VAL5_PME_IN_D2 (1L<<4) 1778#define BCE_PCI_ID_VAL5_PME_IN_D3_HOT (1L<<5) 1779 1780#define BCE_PCI_PCIX_EXTENDED_STATUS 0x00000448 1781#define BCE_PCI_PCIX_EXTENDED_STATUS_NO_SNOOP (1L<<8) 1782#define BCE_PCI_PCIX_EXTENDED_STATUS_LONG_BURST (1L<<9) 1783#define BCE_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_CLASS (0xfL<<16) 1784#define BCE_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_IDX (0xffL<<24) 1785 1786#define BCE_PCI_ID_VAL6 0x0000044c 1787#define BCE_PCI_ID_VAL6_MAX_LAT (0xffL<<0) 1788#define BCE_PCI_ID_VAL6_MIN_GNT (0xffL<<8) 1789#define BCE_PCI_ID_VAL6_BIST (0xffL<<16) 1790 1791#define BCE_PCI_MSI_DATA 0x00000450 1792#define BCE_PCI_MSI_DATA_PCI_MSI_DATA (0xffffL<<0) 1793 1794#define BCE_PCI_MSI_ADDR_H 0x00000454 1795#define BCE_PCI_MSI_ADDR_L 0x00000458 1796 1797 1798/* 1799 * misc_reg definition 1800 * offset: 0x800 1801 */ 1802#define BCE_MISC_COMMAND 0x00000800 1803#define BCE_MISC_COMMAND_ENABLE_ALL (1L<<0) 1804#define BCE_MISC_COMMAND_DISABLE_ALL (1L<<1) 1805#define BCE_MISC_COMMAND_SW_RESET (1L<<4) 1806#define BCE_MISC_COMMAND_POR_RESET (1L<<5) 1807#define BCE_MISC_COMMAND_HD_RESET (1L<<6) 1808#define BCE_MISC_COMMAND_CMN_SW_RESET (1L<<7) 1809#define BCE_MISC_COMMAND_PAR_ERROR (1L<<8) 1810#define BCE_MISC_COMMAND_CS16_ERR (1L<<9) 1811#define BCE_MISC_COMMAND_CS16_ERR_LOC (0xfL<<12) 1812#define BCE_MISC_COMMAND_PAR_ERR_RAM (0x7fL<<16) 1813#define BCE_MISC_COMMAND_POWERDOWN_EVENT (1L<<23) 1814#define BCE_MISC_COMMAND_SW_SHUTDOWN (1L<<24) 1815#define BCE_MISC_COMMAND_SHUTDOWN_EN (1L<<25) 1816#define BCE_MISC_COMMAND_DINTEG_ATTN_EN (1L<<26) 1817#define BCE_MISC_COMMAND_PCIE_LINK_IN_L23 (1L<<27) 1818#define BCE_MISC_COMMAND_PCIE_DIS (1L<<28) 1819 1820#define BCE_MISC_CFG 0x00000804 1821#define BCE_MISC_CFG_GRC_TMOUT (1L<<0) 1822#define BCE_MISC_CFG_NVM_WR_EN (0x3L<<1) 1823#define BCE_MISC_CFG_NVM_WR_EN_PROTECT (0L<<1) 1824#define BCE_MISC_CFG_NVM_WR_EN_PCI (1L<<1) 1825#define BCE_MISC_CFG_NVM_WR_EN_ALLOW (2L<<1) 1826#define BCE_MISC_CFG_NVM_WR_EN_ALLOW2 (3L<<1) 1827#define BCE_MISC_CFG_BIST_EN (1L<<3) 1828#define BCE_MISC_CFG_CK25_OUT_ALT_SRC (1L<<4) 1829#define BCE_MISC_CFG_RESERVED5_TE (1L<<5) 1830#define BCE_MISC_CFG_RESERVED6_TE (1L<<6) 1831#define BCE_MISC_CFG_CLK_CTL_OVERRIDE (1L<<7) 1832#define BCE_MISC_CFG_LEDMODE (0x7L<<8) 1833#define BCE_MISC_CFG_LEDMODE_MAC (0L<<8) 1834#define BCE_MISC_CFG_LEDMODE_PHY1_TE (1L<<8) 1835#define BCE_MISC_CFG_LEDMODE_PHY2_TE (2L<<8) 1836#define BCE_MISC_CFG_LEDMODE_PHY3_TE (3L<<8) 1837#define BCE_MISC_CFG_LEDMODE_PHY4_TE (4L<<8) 1838#define BCE_MISC_CFG_LEDMODE_PHY5_TE (5L<<8) 1839#define BCE_MISC_CFG_LEDMODE_PHY6_TE (6L<<8) 1840#define BCE_MISC_CFG_LEDMODE_PHY7_TE (7L<<8) 1841#define BCE_MISC_CFG_MCP_GRC_TMOUT_TE (1L<<11) 1842#define BCE_MISC_CFG_DBU_GRC_TMOUT_TE (1L<<12) 1843#define BCE_MISC_CFG_LEDMODE_XI (0xfL<<8) 1844#define BCE_MISC_CFG_LEDMODE_MAC_XI (0L<<8) 1845#define BCE_MISC_CFG_LEDMODE_PHY1_XI (1L<<8) 1846#define BCE_MISC_CFG_LEDMODE_PHY2_XI (2L<<8) 1847#define BCE_MISC_CFG_LEDMODE_PHY3_XI (3L<<8) 1848#define BCE_MISC_CFG_LEDMODE_MAC2_XI (4L<<8) 1849#define BCE_MISC_CFG_LEDMODE_PHY4_XI (5L<<8) 1850#define BCE_MISC_CFG_LEDMODE_PHY5_XI (6L<<8) 1851#define BCE_MISC_CFG_LEDMODE_PHY6_XI (7L<<8) 1852#define BCE_MISC_CFG_LEDMODE_MAC3_XI (8L<<8) 1853#define BCE_MISC_CFG_LEDMODE_PHY7_XI (9L<<8) 1854#define BCE_MISC_CFG_LEDMODE_PHY8_XI (10L<<8) 1855#define BCE_MISC_CFG_LEDMODE_PHY9_XI (11L<<8) 1856#define BCE_MISC_CFG_LEDMODE_MAC4_XI (12L<<8) 1857#define BCE_MISC_CFG_LEDMODE_PHY10_XI (13L<<8) 1858#define BCE_MISC_CFG_LEDMODE_PHY11_XI (14L<<8) 1859#define BCE_MISC_CFG_LEDMODE_UNUSED_XI (15L<<8) 1860#define BCE_MISC_CFG_PORT_SELECT_XI (1L<<13) 1861#define BCE_MISC_CFG_PARITY_MODE_XI (1L<<14) 1862 1863#define BCE_MISC_ID 0x00000808 1864#define BCE_MISC_ID_BOND_ID (0xfL<<0) 1865#define BCE_MISC_ID_BOND_ID_X (0L<<0) 1866#define BCE_MISC_ID_BOND_ID_C (3L<<0) 1867#define BCE_MISC_ID_BOND_ID_S (12L<<0) 1868#define BCE_MISC_ID_CHIP_METAL (0xffL<<4) 1869#define BCE_MISC_ID_CHIP_REV (0xfL<<12) 1870#define BCE_MISC_ID_CHIP_NUM (0xffffL<<16) 1871 1872#define BCE_MISC_ENABLE_STATUS_BITS 0x0000080c 1873#define BCE_MISC_ENABLE_STATUS_BITS_TX_SCHEDULER_ENABLE (1L<<0) 1874#define BCE_MISC_ENABLE_STATUS_BITS_TX_BD_READ_ENABLE (1L<<1) 1875#define BCE_MISC_ENABLE_STATUS_BITS_TX_BD_CACHE_ENABLE (1L<<2) 1876#define BCE_MISC_ENABLE_STATUS_BITS_TX_PROCESSOR_ENABLE (1L<<3) 1877#define BCE_MISC_ENABLE_STATUS_BITS_TX_DMA_ENABLE (1L<<4) 1878#define BCE_MISC_ENABLE_STATUS_BITS_TX_PATCHUP_ENABLE (1L<<5) 1879#define BCE_MISC_ENABLE_STATUS_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6) 1880#define BCE_MISC_ENABLE_STATUS_BITS_TX_HEADER_Q_ENABLE (1L<<7) 1881#define BCE_MISC_ENABLE_STATUS_BITS_TX_ASSEMBLER_ENABLE (1L<<8) 1882#define BCE_MISC_ENABLE_STATUS_BITS_EMAC_ENABLE (1L<<9) 1883#define BCE_MISC_ENABLE_STATUS_BITS_RX_PARSER_MAC_ENABLE (1L<<10) 1884#define BCE_MISC_ENABLE_STATUS_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11) 1885#define BCE_MISC_ENABLE_STATUS_BITS_RX_MBUF_ENABLE (1L<<12) 1886#define BCE_MISC_ENABLE_STATUS_BITS_RX_LOOKUP_ENABLE (1L<<13) 1887#define BCE_MISC_ENABLE_STATUS_BITS_RX_PROCESSOR_ENABLE (1L<<14) 1888#define BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE (1L<<15) 1889#define BCE_MISC_ENABLE_STATUS_BITS_RX_BD_CACHE_ENABLE (1L<<16) 1890#define BCE_MISC_ENABLE_STATUS_BITS_RX_DMA_ENABLE (1L<<17) 1891#define BCE_MISC_ENABLE_STATUS_BITS_COMPLETION_ENABLE (1L<<18) 1892#define BCE_MISC_ENABLE_STATUS_BITS_HOST_COALESCE_ENABLE (1L<<19) 1893#define BCE_MISC_ENABLE_STATUS_BITS_MAILBOX_QUEUE_ENABLE (1L<<20) 1894#define BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE (1L<<21) 1895#define BCE_MISC_ENABLE_STATUS_BITS_CMD_SCHEDULER_ENABLE (1L<<22) 1896#define BCE_MISC_ENABLE_STATUS_BITS_CMD_PROCESSOR_ENABLE (1L<<23) 1897#define BCE_MISC_ENABLE_STATUS_BITS_MGMT_PROCESSOR_ENABLE (1L<<24) 1898#define BCE_MISC_ENABLE_STATUS_BITS_TIMER_ENABLE (1L<<25) 1899#define BCE_MISC_ENABLE_STATUS_BITS_DMA_ENGINE_ENABLE (1L<<26) 1900#define BCE_MISC_ENABLE_STATUS_BITS_UMP_ENABLE (1L<<27) 1901#define BCE_MISC_ENABLE_STATUS_BITS_RV2P_CMD_SCHEDULER_ENABLE (1L<<28) 1902#define BCE_MISC_ENABLE_STATUS_BITS_RSVD_FUTURE_ENABLE (0x7L<<29) 1903 1904#define BCE_MISC_ENABLE_SET_BITS 0x00000810 1905#define BCE_MISC_ENABLE_SET_BITS_TX_SCHEDULER_ENABLE (1L<<0) 1906#define BCE_MISC_ENABLE_SET_BITS_TX_BD_READ_ENABLE (1L<<1) 1907#define BCE_MISC_ENABLE_SET_BITS_TX_BD_CACHE_ENABLE (1L<<2) 1908#define BCE_MISC_ENABLE_SET_BITS_TX_PROCESSOR_ENABLE (1L<<3) 1909#define BCE_MISC_ENABLE_SET_BITS_TX_DMA_ENABLE (1L<<4) 1910#define BCE_MISC_ENABLE_SET_BITS_TX_PATCHUP_ENABLE (1L<<5) 1911#define BCE_MISC_ENABLE_SET_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6) 1912#define BCE_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE (1L<<7) 1913#define BCE_MISC_ENABLE_SET_BITS_TX_ASSEMBLER_ENABLE (1L<<8) 1914#define BCE_MISC_ENABLE_SET_BITS_EMAC_ENABLE (1L<<9) 1915#define BCE_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE (1L<<10) 1916#define BCE_MISC_ENABLE_SET_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11) 1917#define BCE_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE (1L<<12) 1918#define BCE_MISC_ENABLE_SET_BITS_RX_LOOKUP_ENABLE (1L<<13) 1919#define BCE_MISC_ENABLE_SET_BITS_RX_PROCESSOR_ENABLE (1L<<14) 1920#define BCE_MISC_ENABLE_SET_BITS_RX_V2P_ENABLE (1L<<15) 1921#define BCE_MISC_ENABLE_SET_BITS_RX_BD_CACHE_ENABLE (1L<<16) 1922#define BCE_MISC_ENABLE_SET_BITS_RX_DMA_ENABLE (1L<<17) 1923#define BCE_MISC_ENABLE_SET_BITS_COMPLETION_ENABLE (1L<<18) 1924#define BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE (1L<<19) 1925#define BCE_MISC_ENABLE_SET_BITS_MAILBOX_QUEUE_ENABLE (1L<<20) 1926#define BCE_MISC_ENABLE_SET_BITS_CONTEXT_ENABLE (1L<<21) 1927#define BCE_MISC_ENABLE_SET_BITS_CMD_SCHEDULER_ENABLE (1L<<22) 1928#define BCE_MISC_ENABLE_SET_BITS_CMD_PROCESSOR_ENABLE (1L<<23) 1929#define BCE_MISC_ENABLE_SET_BITS_MGMT_PROCESSOR_ENABLE (1L<<24) 1930#define BCE_MISC_ENABLE_SET_BITS_TIMER_ENABLE (1L<<25) 1931#define BCE_MISC_ENABLE_SET_BITS_DMA_ENGINE_ENABLE (1L<<26) 1932#define BCE_MISC_ENABLE_SET_BITS_UMP_ENABLE (1L<<27) 1933#define BCE_MISC_ENABLE_SET_BITS_RV2P_CMD_SCHEDULER_ENABLE (1L<<28) 1934#define BCE_MISC_ENABLE_SET_BITS_RSVD_FUTURE_ENABLE (0x7L<<29) 1935 1936#define BCE_MISC_ENABLE_DEFAULT 0x05ffffff 1937#define BCE_MISC_ENABLE_DEFAULT_XI 0x17ffffff 1938 1939#define BCE_MISC_ENABLE_CLR_BITS 0x00000814 1940#define BCE_MISC_ENABLE_CLR_BITS_TX_SCHEDULER_ENABLE (1L<<0) 1941#define BCE_MISC_ENABLE_CLR_BITS_TX_BD_READ_ENABLE (1L<<1) 1942#define BCE_MISC_ENABLE_CLR_BITS_TX_BD_CACHE_ENABLE (1L<<2) 1943#define BCE_MISC_ENABLE_CLR_BITS_TX_PROCESSOR_ENABLE (1L<<3) 1944#define BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE (1L<<4) 1945#define BCE_MISC_ENABLE_CLR_BITS_TX_PATCHUP_ENABLE (1L<<5) 1946#define BCE_MISC_ENABLE_CLR_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6) 1947#define BCE_MISC_ENABLE_CLR_BITS_TX_HEADER_Q_ENABLE (1L<<7) 1948#define BCE_MISC_ENABLE_CLR_BITS_TX_ASSEMBLER_ENABLE (1L<<8) 1949#define BCE_MISC_ENABLE_CLR_BITS_EMAC_ENABLE (1L<<9) 1950#define BCE_MISC_ENABLE_CLR_BITS_RX_PARSER_MAC_ENABLE (1L<<10) 1951#define BCE_MISC_ENABLE_CLR_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11) 1952#define BCE_MISC_ENABLE_CLR_BITS_RX_MBUF_ENABLE (1L<<12) 1953#define BCE_MISC_ENABLE_CLR_BITS_RX_LOOKUP_ENABLE (1L<<13) 1954#define BCE_MISC_ENABLE_CLR_BITS_RX_PROCESSOR_ENABLE (1L<<14) 1955#define BCE_MISC_ENABLE_CLR_BITS_RX_V2P_ENABLE (1L<<15) 1956#define BCE_MISC_ENABLE_CLR_BITS_RX_BD_CACHE_ENABLE (1L<<16) 1957#define BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE (1L<<17) 1958#define BCE_MISC_ENABLE_CLR_BITS_COMPLETION_ENABLE (1L<<18) 1959#define BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE (1L<<19) 1960#define BCE_MISC_ENABLE_CLR_BITS_MAILBOX_QUEUE_ENABLE (1L<<20) 1961#define BCE_MISC_ENABLE_CLR_BITS_CONTEXT_ENABLE (1L<<21) 1962#define BCE_MISC_ENABLE_CLR_BITS_CMD_SCHEDULER_ENABLE (1L<<22) 1963#define BCE_MISC_ENABLE_CLR_BITS_CMD_PROCESSOR_ENABLE (1L<<23) 1964#define BCE_MISC_ENABLE_CLR_BITS_MGMT_PROCESSOR_ENABLE (1L<<24) 1965#define BCE_MISC_ENABLE_CLR_BITS_TIMER_ENABLE (1L<<25) 1966#define BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE (1L<<26) 1967#define BCE_MISC_ENABLE_CLR_BITS_UMP_ENABLE (1L<<27) 1968#define BCE_MISC_ENABLE_CLR_BITS_RV2P_CMD_SCHEDULER_ENABLE (1L<<28) 1969#define BCE_MISC_ENABLE_CLR_BITS_RSVD_FUTURE_ENABLE (0x7L<<29) 1970 1971#define BCE_MISC_ENABLE_CLR_DEFAULT 0x17ffffff 1972 1973#define BCE_MISC_CLOCK_CONTROL_BITS 0x00000818 1974#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET (0xfL<<0) 1975#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ (0L<<0) 1976#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ (1L<<0) 1977#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ (2L<<0) 1978#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ (3L<<0) 1979#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ (4L<<0) 1980#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ (5L<<0) 1981#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ (6L<<0) 1982#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ (7L<<0) 1983#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW (0xfL<<0) 1984#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE (1L<<6) 1985#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT (1L<<7) 1986#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC (0x7L<<8) 1987#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF (0L<<8) 1988#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12 (1L<<8) 1989#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6 (2L<<8) 1990#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62 (4L<<8) 1991#define BCE_MISC_CLOCK_CONTROL_BITS_RESERVED0_XI (0x7L<<8) 1992#define BCE_MISC_CLOCK_CONTROL_BITS_MIN_POWER (1L<<11) 1993#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED (0xfL<<12) 1994#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100 (0L<<12) 1995#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80 (1L<<12) 1996#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50 (2L<<12) 1997#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40 (4L<<12) 1998#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25 (8L<<12) 1999#define BCE_MISC_CLOCK_CONTROL_BITS_RESERVED1_XI (0xfL<<12) 2000#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP (1L<<16) 2001#define BCE_MISC_CLOCK_CONTROL_BITS_RESERVED_17_TE (1L<<17) 2002#define BCE_MISC_CLOCK_CONTROL_BITS_RESERVED_18_TE (1L<<18) 2003#define BCE_MISC_CLOCK_CONTROL_BITS_RESERVED_19_TE (1L<<19) 2004#define BCE_MISC_CLOCK_CONTROL_BITS_RESERVED_TE (0xfffL<<20) 2005#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_MGMT_XI (1L<<17) 2006#define BCE_MISC_CLOCK_CONTROL_BITS_RESERVED2_XI (0x3fL<<18) 2007#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_VCO_XI (0x7L<<24) 2008#define BCE_MISC_CLOCK_CONTROL_BITS_RESERVED3_XI (1L<<27) 2009#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_XI (0xfL<<28) 2010 2011#define BCE_MISC_SPIO 0x0000081c 2012#define BCE_MISC_SPIO_VALUE (0xffL<<0) 2013#define BCE_MISC_SPIO_SET (0xffL<<8) 2014#define BCE_MISC_SPIO_CLR (0xffL<<16) 2015#define BCE_MISC_SPIO_FLOAT (0xffL<<24) 2016 2017#define BCE_MISC_SPIO_INT 0x00000820 2018#define BCE_MISC_SPIO_INT_INT_STATE_TE (0xfL<<0) 2019#define BCE_MISC_SPIO_INT_OLD_VALUE_TE (0xfL<<8) 2020#define BCE_MISC_SPIO_INT_OLD_SET_TE (0xfL<<16) 2021#define BCE_MISC_SPIO_INT_OLD_CLR_TE (0xfL<<24) 2022#define BCE_MISC_SPIO_INT_INT_STATE_XI (0xffL<<0) 2023#define BCE_MISC_SPIO_INT_OLD_VALUE_XI (0xffL<<8) 2024#define BCE_MISC_SPIO_INT_OLD_SET_XI (0xffL<<16) 2025#define BCE_MISC_SPIO_INT_OLD_CLR_XI (0xffL<<24) 2026 2027#define BCE_MISC_CONFIG_LFSR 0x00000824 2028#define BCE_MISC_CONFIG_LFSR_DIV (0xffffL<<0) 2029 2030#define BCE_MISC_LFSR_MASK_BITS 0x00000828 2031#define BCE_MISC_LFSR_MASK_BITS_TX_SCHEDULER_ENABLE (1L<<0) 2032#define BCE_MISC_LFSR_MASK_BITS_TX_BD_READ_ENABLE (1L<<1) 2033#define BCE_MISC_LFSR_MASK_BITS_TX_BD_CACHE_ENABLE (1L<<2) 2034#define BCE_MISC_LFSR_MASK_BITS_TX_PROCESSOR_ENABLE (1L<<3) 2035#define BCE_MISC_LFSR_MASK_BITS_TX_DMA_ENABLE (1L<<4) 2036#define BCE_MISC_LFSR_MASK_BITS_TX_PATCHUP_ENABLE (1L<<5) 2037#define BCE_MISC_LFSR_MASK_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6) 2038#define BCE_MISC_LFSR_MASK_BITS_TX_HEADER_Q_ENABLE (1L<<7) 2039#define BCE_MISC_LFSR_MASK_BITS_TX_ASSEMBLER_ENABLE (1L<<8) 2040#define BCE_MISC_LFSR_MASK_BITS_EMAC_ENABLE (1L<<9) 2041#define BCE_MISC_LFSR_MASK_BITS_RX_PARSER_MAC_ENABLE (1L<<10) 2042#define BCE_MISC_LFSR_MASK_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11) 2043#define BCE_MISC_LFSR_MASK_BITS_RX_MBUF_ENABLE (1L<<12) 2044#define BCE_MISC_LFSR_MASK_BITS_RX_LOOKUP_ENABLE (1L<<13) 2045#define BCE_MISC_LFSR_MASK_BITS_RX_PROCESSOR_ENABLE (1L<<14) 2046#define BCE_MISC_LFSR_MASK_BITS_RX_V2P_ENABLE (1L<<15) 2047#define BCE_MISC_LFSR_MASK_BITS_RX_BD_CACHE_ENABLE (1L<<16) 2048#define BCE_MISC_LFSR_MASK_BITS_RX_DMA_ENABLE (1L<<17) 2049#define BCE_MISC_LFSR_MASK_BITS_COMPLETION_ENABLE (1L<<18) 2050#define BCE_MISC_LFSR_MASK_BITS_HOST_COALESCE_ENABLE (1L<<19) 2051#define BCE_MISC_LFSR_MASK_BITS_MAILBOX_QUEUE_ENABLE (1L<<20) 2052#define BCE_MISC_LFSR_MASK_BITS_CONTEXT_ENABLE (1L<<21) 2053#define BCE_MISC_LFSR_MASK_BITS_CMD_SCHEDULER_ENABLE (1L<<22) 2054#define BCE_MISC_LFSR_MASK_BITS_CMD_PROCESSOR_ENABLE (1L<<23) 2055#define BCE_MISC_LFSR_MASK_BITS_MGMT_PROCESSOR_ENABLE (1L<<24) 2056#define BCE_MISC_LFSR_MASK_BITS_TIMER_ENABLE (1L<<25) 2057#define BCE_MISC_LFSR_MASK_BITS_DMA_ENGINE_ENABLE (1L<<26) 2058#define BCE_MISC_LFSR_MASK_BITS_UMP_ENABLE (1L<<27) 2059#define BCE_MISC_LFSR_MASK_BITS_RV2P_CMD_SCHEDULER_ENABLE (1L<<28) 2060#define BCE_MISC_LFSR_MASK_BITS_RSVD_FUTURE_ENABLE (0x7L<<29) 2061 2062#define BCE_MISC_ARB_REQ0 0x0000082c 2063#define BCE_MISC_ARB_REQ1 0x00000830 2064#define BCE_MISC_ARB_REQ2 0x00000834 2065#define BCE_MISC_ARB_REQ3 0x00000838 2066#define BCE_MISC_ARB_REQ4 0x0000083c 2067#define BCE_MISC_ARB_FREE0 0x00000840 2068#define BCE_MISC_ARB_FREE1 0x00000844 2069#define BCE_MISC_ARB_FREE2 0x00000848 2070#define BCE_MISC_ARB_FREE3 0x0000084c 2071#define BCE_MISC_ARB_FREE4 0x00000850 2072#define BCE_MISC_ARB_REQ_STATUS0 0x00000854 2073#define BCE_MISC_ARB_REQ_STATUS1 0x00000858 2074#define BCE_MISC_ARB_REQ_STATUS2 0x0000085c 2075#define BCE_MISC_ARB_REQ_STATUS3 0x00000860 2076#define BCE_MISC_ARB_REQ_STATUS4 0x00000864 2077#define BCE_MISC_ARB_GNT0 0x00000868 2078#define BCE_MISC_ARB_GNT0_0 (0x7L<<0) 2079#define BCE_MISC_ARB_GNT0_1 (0x7L<<4) 2080#define BCE_MISC_ARB_GNT0_2 (0x7L<<8) 2081#define BCE_MISC_ARB_GNT0_3 (0x7L<<12) 2082#define BCE_MISC_ARB_GNT0_4 (0x7L<<16) 2083#define BCE_MISC_ARB_GNT0_5 (0x7L<<20) 2084#define BCE_MISC_ARB_GNT0_6 (0x7L<<24) 2085#define BCE_MISC_ARB_GNT0_7 (0x7L<<28) 2086 2087#define BCE_MISC_ARB_GNT1 0x0000086c 2088#define BCE_MISC_ARB_GNT1_8 (0x7L<<0) 2089#define BCE_MISC_ARB_GNT1_9 (0x7L<<4) 2090#define BCE_MISC_ARB_GNT1_10 (0x7L<<8) 2091#define BCE_MISC_ARB_GNT1_11 (0x7L<<12) 2092#define BCE_MISC_ARB_GNT1_12 (0x7L<<16) 2093#define BCE_MISC_ARB_GNT1_13 (0x7L<<20) 2094#define BCE_MISC_ARB_GNT1_14 (0x7L<<24) 2095#define BCE_MISC_ARB_GNT1_15 (0x7L<<28) 2096 2097#define BCE_MISC_ARB_GNT2 0x00000870 2098#define BCE_MISC_ARB_GNT2_16 (0x7L<<0) 2099#define BCE_MISC_ARB_GNT2_17 (0x7L<<4) 2100#define BCE_MISC_ARB_GNT2_18 (0x7L<<8) 2101#define BCE_MISC_ARB_GNT2_19 (0x7L<<12) 2102#define BCE_MISC_ARB_GNT2_20 (0x7L<<16) 2103#define BCE_MISC_ARB_GNT2_21 (0x7L<<20) 2104#define BCE_MISC_ARB_GNT2_22 (0x7L<<24) 2105#define BCE_MISC_ARB_GNT2_23 (0x7L<<28) 2106 2107#define BCE_MISC_ARB_GNT3 0x00000874 2108#define BCE_MISC_ARB_GNT3_24 (0x7L<<0) 2109#define BCE_MISC_ARB_GNT3_25 (0x7L<<4) 2110#define BCE_MISC_ARB_GNT3_26 (0x7L<<8) 2111#define BCE_MISC_ARB_GNT3_27 (0x7L<<12) 2112#define BCE_MISC_ARB_GNT3_28 (0x7L<<16) 2113#define BCE_MISC_ARB_GNT3_29 (0x7L<<20) 2114#define BCE_MISC_ARB_GNT3_30 (0x7L<<24) 2115#define BCE_MISC_ARB_GNT3_31 (0x7L<<28) 2116 2117#define BCE_MISC_RESERVED1 0x00000878 2118#define BCE_MISC_RESERVED1_MISC_RESERVED1_VALUE (0x3fL<<0) 2119 2120#define BCE_MISC_RESERVED2 0x0000087c 2121#define BCE_MISC_RESERVED2_PCIE_DIS (1L<<0) 2122#define BCE_MISC_RESERVED2_LINK_IN_L23 (1L<<1) 2123 2124#define BCE_MISC_SM_ASF_CONTROL 0x00000880 2125#define BCE_MISC_SM_ASF_CONTROL_ASF_RST (1L<<0) 2126#define BCE_MISC_SM_ASF_CONTROL_TSC_EN (1L<<1) 2127#define BCE_MISC_SM_ASF_CONTROL_WG_TO (1L<<2) 2128#define BCE_MISC_SM_ASF_CONTROL_HB_TO (1L<<3) 2129#define BCE_MISC_SM_ASF_CONTROL_PA_TO (1L<<4) 2130#define BCE_MISC_SM_ASF_CONTROL_PL_TO (1L<<5) 2131#define BCE_MISC_SM_ASF_CONTROL_RT_TO (1L<<6) 2132#define BCE_MISC_SM_ASF_CONTROL_SMB_EVENT (1L<<7) 2133#define BCE_MISC_SM_ASF_CONTROL_STRETCH_EN (1L<<8) 2134#define BCE_MISC_SM_ASF_CONTROL_STRETCH_PULSE (1L<<9) 2135#define BCE_MISC_SM_ASF_CONTROL_RES (0x3L<<10) 2136#define BCE_MISC_SM_ASF_CONTROL_SMB_EN (1L<<12) 2137#define BCE_MISC_SM_ASF_CONTROL_SMB_BB_EN (1L<<13) 2138#define BCE_MISC_SM_ASF_CONTROL_SMB_NO_ADDR_FILT (1L<<14) 2139#define BCE_MISC_SM_ASF_CONTROL_SMB_AUTOREAD (1L<<15) 2140#define BCE_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR1 (0x7fL<<16) 2141#define BCE_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR2 (0x7fL<<23) 2142#define BCE_MISC_SM_ASF_CONTROL_EN_NIC_SMB_ADDR_0 (1L<<30) 2143#define BCE_MISC_SM_ASF_CONTROL_SMB_EARLY_ATTN (1L<<31) 2144 2145#define BCE_MISC_SMB_IN 0x00000884 2146#define BCE_MISC_SMB_IN_DAT_IN (0xffL<<0) 2147#define BCE_MISC_SMB_IN_RDY (1L<<8) 2148#define BCE_MISC_SMB_IN_DONE (1L<<9) 2149#define BCE_MISC_SMB_IN_FIRSTBYTE (1L<<10) 2150#define BCE_MISC_SMB_IN_STATUS (0x7L<<11) 2151#define BCE_MISC_SMB_IN_STATUS_OK (0x0L<<11) 2152#define BCE_MISC_SMB_IN_STATUS_PEC (0x1L<<11) 2153#define BCE_MISC_SMB_IN_STATUS_OFLOW (0x2L<<11) 2154#define BCE_MISC_SMB_IN_STATUS_STOP (0x3L<<11) 2155#define BCE_MISC_SMB_IN_STATUS_TIMEOUT (0x4L<<11) 2156 2157#define BCE_MISC_SMB_OUT 0x00000888 2158#define BCE_MISC_SMB_OUT_DAT_OUT (0xffL<<0) 2159#define BCE_MISC_SMB_OUT_RDY (1L<<8) 2160#define BCE_MISC_SMB_OUT_START (1L<<9) 2161#define BCE_MISC_SMB_OUT_LAST (1L<<10) 2162#define BCE_MISC_SMB_OUT_ACC_TYPE (1L<<11) 2163#define BCE_MISC_SMB_OUT_ENB_PEC (1L<<12) 2164#define BCE_MISC_SMB_OUT_GET_RX_LEN (1L<<13) 2165#define BCE_MISC_SMB_OUT_SMB_READ_LEN (0x3fL<<14) 2166#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS (0xfL<<20) 2167#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_OK (0L<<20) 2168#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_NACK (1L<<20) 2169#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_UFLOW (2L<<20) 2170#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_STOP (3L<<20) 2171#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_TIMEOUT (4L<<20) 2172#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_LOST (5L<<20) 2173#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_BADACK (6L<<20) 2174#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_NACK (9L<<20) 2175#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_LOST (0xdL<<20) 2176#define BCE_MISC_SMB_OUT_SMB_OUT_SLAVEMODE (1L<<24) 2177#define BCE_MISC_SMB_OUT_SMB_OUT_DAT_EN (1L<<25) 2178#define BCE_MISC_SMB_OUT_SMB_OUT_DAT_IN (1L<<26) 2179#define BCE_MISC_SMB_OUT_SMB_OUT_CLK_EN (1L<<27) 2180#define BCE_MISC_SMB_OUT_SMB_OUT_CLK_IN (1L<<28) 2181 2182#define BCE_MISC_SMB_WATCHDOG 0x0000088c 2183#define BCE_MISC_SMB_WATCHDOG_WATCHDOG (0xffffL<<0) 2184 2185#define BCE_MISC_SMB_HEARTBEAT 0x00000890 2186#define BCE_MISC_SMB_HEARTBEAT_HEARTBEAT (0xffffL<<0) 2187 2188#define BCE_MISC_SMB_POLL_ASF 0x00000894 2189#define BCE_MISC_SMB_POLL_ASF_POLL_ASF (0xffffL<<0) 2190 2191#define BCE_MISC_SMB_POLL_LEGACY 0x00000898 2192#define BCE_MISC_SMB_POLL_LEGACY_POLL_LEGACY (0xffffL<<0) 2193 2194#define BCE_MISC_SMB_RETRAN 0x0000089c 2195#define BCE_MISC_SMB_RETRAN_RETRAN (0xffL<<0) 2196 2197#define BCE_MISC_SMB_TIMESTAMP 0x000008a0 2198#define BCE_MISC_SMB_TIMESTAMP_TIMESTAMP (0xffffffffL<<0) 2199 2200#define BCE_MISC_PERR_ENA0 0x000008a4 2201#define BCE_MISC_PERR_ENA0_COM_MISC_CTXC (1L<<0) 2202#define BCE_MISC_PERR_ENA0_COM_MISC_REGF (1L<<1) 2203#define BCE_MISC_PERR_ENA0_COM_MISC_SCPAD (1L<<2) 2204#define BCE_MISC_PERR_ENA0_CP_MISC_CTXC (1L<<3) 2205#define BCE_MISC_PERR_ENA0_CP_MISC_REGF (1L<<4) 2206#define BCE_MISC_PERR_ENA0_CP_MISC_SCPAD (1L<<5) 2207#define BCE_MISC_PERR_ENA0_CS_MISC_TMEM (1L<<6) 2208#define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM0 (1L<<7) 2209#define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM1 (1L<<8) 2210#define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM2 (1L<<9) 2211#define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM3 (1L<<10) 2212#define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM4 (1L<<11) 2213#define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM5 (1L<<12) 2214#define BCE_MISC_PERR_ENA0_CTX_MISC_PGTBL (1L<<13) 2215#define BCE_MISC_PERR_ENA0_DMAE_MISC_DR0 (1L<<14) 2216#define BCE_MISC_PERR_ENA0_DMAE_MISC_DR1 (1L<<15) 2217#define BCE_MISC_PERR_ENA0_DMAE_MISC_DR2 (1L<<16) 2218#define BCE_MISC_PERR_ENA0_DMAE_MISC_DR3 (1L<<17) 2219#define BCE_MISC_PERR_ENA0_DMAE_MISC_DR4 (1L<<18) 2220#define BCE_MISC_PERR_ENA0_DMAE_MISC_DW0 (1L<<19) 2221#define BCE_MISC_PERR_ENA0_DMAE_MISC_DW1 (1L<<20) 2222#define BCE_MISC_PERR_ENA0_DMAE_MISC_DW2 (1L<<21) 2223#define BCE_MISC_PERR_ENA0_HC_MISC_DMA (1L<<22) 2224#define BCE_MISC_PERR_ENA0_MCP_MISC_REGF (1L<<23) 2225#define BCE_MISC_PERR_ENA0_MCP_MISC_SCPAD (1L<<24) 2226#define BCE_MISC_PERR_ENA0_MQ_MISC_CTX (1L<<25) 2227#define BCE_MISC_PERR_ENA0_RBDC_MISC (1L<<26) 2228#define BCE_MISC_PERR_ENA0_RBUF_MISC_MB (1L<<27) 2229#define BCE_MISC_PERR_ENA0_RBUF_MISC_PTR (1L<<28) 2230#define BCE_MISC_PERR_ENA0_RDE_MISC_RPC (1L<<29) 2231#define BCE_MISC_PERR_ENA0_RDE_MISC_RPM (1L<<30) 2232#define BCE_MISC_PERR_ENA0_RV2P_MISC_CB0REGS (1L<<31) 2233#define BCE_MISC_PERR_ENA0_COM_DMAE_PERR_EN_XI (1L<<0) 2234#define BCE_MISC_PERR_ENA0_CP_DMAE_PERR_EN_XI (1L<<1) 2235#define BCE_MISC_PERR_ENA0_RPM_ACPIBEMEM_PERR_EN_XI (1L<<2) 2236#define BCE_MISC_PERR_ENA0_CTX_USAGE_CNT_PERR_EN_XI (1L<<3) 2237#define BCE_MISC_PERR_ENA0_CTX_PGTBL_PERR_EN_XI (1L<<4) 2238#define BCE_MISC_PERR_ENA0_CTX_CACHE_PERR_EN_XI (1L<<5) 2239#define BCE_MISC_PERR_ENA0_CTX_MIRROR_PERR_EN_XI (1L<<6) 2240#define BCE_MISC_PERR_ENA0_COM_CTXC_PERR_EN_XI (1L<<7) 2241#define BCE_MISC_PERR_ENA0_COM_SCPAD_PERR_EN_XI (1L<<8) 2242#define BCE_MISC_PERR_ENA0_CP_CTXC_PERR_EN_XI (1L<<9) 2243#define BCE_MISC_PERR_ENA0_CP_SCPAD_PERR_EN_XI (1L<<10) 2244#define BCE_MISC_PERR_ENA0_RXP_RBUFC_PERR_EN_XI (1L<<11) 2245#define BCE_MISC_PERR_ENA0_RXP_CTXC_PERR_EN_XI (1L<<12) 2246#define BCE_MISC_PERR_ENA0_RXP_SCPAD_PERR_EN_XI (1L<<13) 2247#define BCE_MISC_PERR_ENA0_TPAT_SCPAD_PERR_EN_XI (1L<<14) 2248#define BCE_MISC_PERR_ENA0_TXP_CTXC_PERR_EN_XI (1L<<15) 2249#define BCE_MISC_PERR_ENA0_TXP_SCPAD_PERR_EN_XI (1L<<16) 2250#define BCE_MISC_PERR_ENA0_CS_TMEM_PERR_EN_XI (1L<<17) 2251#define BCE_MISC_PERR_ENA0_MQ_CTX_PERR_EN_XI (1L<<18) 2252#define BCE_MISC_PERR_ENA0_RPM_DFIFOMEM_PERR_EN_XI (1L<<19) 2253#define BCE_MISC_PERR_ENA0_RPC_DFIFOMEM_PERR_EN_XI (1L<<20) 2254#define BCE_MISC_PERR_ENA0_RBUF_PTRMEM_PERR_EN_XI (1L<<21) 2255#define BCE_MISC_PERR_ENA0_RBUF_DATAMEM_PERR_EN_XI (1L<<22) 2256#define BCE_MISC_PERR_ENA0_RV2P_P2IRAM_PERR_EN_XI (1L<<23) 2257#define BCE_MISC_PERR_ENA0_RV2P_P1IRAM_PERR_EN_XI (1L<<24) 2258#define BCE_MISC_PERR_ENA0_RV2P_CB1REGS_PERR_EN_XI (1L<<25) 2259#define BCE_MISC_PERR_ENA0_RV2P_CB0REGS_PERR_EN_XI (1L<<26) 2260#define BCE_MISC_PERR_ENA0_TPBUF_PERR_EN_XI (1L<<27) 2261#define BCE_MISC_PERR_ENA0_THBUF_PERR_EN_XI (1L<<28) 2262#define BCE_MISC_PERR_ENA0_TDMA_PERR_EN_XI (1L<<29) 2263#define BCE_MISC_PERR_ENA0_TBDC_PERR_EN_XI (1L<<30) 2264#define BCE_MISC_PERR_ENA0_TSCH_LR_PERR_EN_XI (1L<<31) 2265 2266#define BCE_MISC_PERR_ENA1 0x000008a8 2267#define BCE_MISC_PERR_ENA1_RV2P_MISC_CB1REGS (1L<<0) 2268#define BCE_MISC_PERR_ENA1_RV2P_MISC_P1IRAM (1L<<1) 2269#define BCE_MISC_PERR_ENA1_RV2P_MISC_P2IRAM (1L<<2) 2270#define BCE_MISC_PERR_ENA1_RXP_MISC_CTXC (1L<<3) 2271#define BCE_MISC_PERR_ENA1_RXP_MISC_REGF (1L<<4) 2272#define BCE_MISC_PERR_ENA1_RXP_MISC_SCPAD (1L<<5) 2273#define BCE_MISC_PERR_ENA1_RXP_MISC_RBUFC (1L<<6) 2274#define BCE_MISC_PERR_ENA1_TBDC_MISC (1L<<7) 2275#define BCE_MISC_PERR_ENA1_TDMA_MISC (1L<<8) 2276#define BCE_MISC_PERR_ENA1_THBUF_MISC_MB0 (1L<<9) 2277#define BCE_MISC_PERR_ENA1_THBUF_MISC_MB1 (1L<<10) 2278#define BCE_MISC_PERR_ENA1_TPAT_MISC_REGF (1L<<11) 2279#define BCE_MISC_PERR_ENA1_TPAT_MISC_SCPAD (1L<<12) 2280#define BCE_MISC_PERR_ENA1_TPBUF_MISC_MB (1L<<13) 2281#define BCE_MISC_PERR_ENA1_TSCH_MISC_LR (1L<<14) 2282#define BCE_MISC_PERR_ENA1_TXP_MISC_CTXC (1L<<15) 2283#define BCE_MISC_PERR_ENA1_TXP_MISC_REGF (1L<<16) 2284#define BCE_MISC_PERR_ENA1_TXP_MISC_SCPAD (1L<<17) 2285#define BCE_MISC_PERR_ENA1_UMP_MISC_FIORX (1L<<18) 2286#define BCE_MISC_PERR_ENA1_UMP_MISC_FIOTX (1L<<19) 2287#define BCE_MISC_PERR_ENA1_UMP_MISC_RX (1L<<20) 2288#define BCE_MISC_PERR_ENA1_UMP_MISC_TX (1L<<21) 2289#define BCE_MISC_PERR_ENA1_RDMAQ_MISC (1L<<22) 2290#define BCE_MISC_PERR_ENA1_CSQ_MISC (1L<<23) 2291#define BCE_MISC_PERR_ENA1_CPQ_MISC (1L<<24) 2292#define BCE_MISC_PERR_ENA1_MCPQ_MISC (1L<<25) 2293#define BCE_MISC_PERR_ENA1_RV2PMQ_MISC (1L<<26) 2294#define BCE_MISC_PERR_ENA1_RV2PPQ_MISC (1L<<27) 2295#define BCE_MISC_PERR_ENA1_RV2PTQ_MISC (1L<<28) 2296#define BCE_MISC_PERR_ENA1_RXPQ_MISC (1L<<29) 2297#define BCE_MISC_PERR_ENA1_RXPCQ_MISC (1L<<30) 2298#define BCE_MISC_PERR_ENA1_RLUPQ_MISC (1L<<31) 2299#define BCE_MISC_PERR_ENA1_RBDC_PERR_EN_XI (1L<<0) 2300#define BCE_MISC_PERR_ENA1_RDMA_DFIFO_PERR_EN_XI (1L<<2) 2301#define BCE_MISC_PERR_ENA1_HC_STATS_PERR_EN_XI (1L<<3) 2302#define BCE_MISC_PERR_ENA1_HC_MSIX_PERR_EN_XI (1L<<4) 2303#define BCE_MISC_PERR_ENA1_HC_PRODUCSTB_PERR_EN_XI (1L<<5) 2304#define BCE_MISC_PERR_ENA1_HC_CONSUMSTB_PERR_EN_XI (1L<<6) 2305#define BCE_MISC_PERR_ENA1_TPATQ_PERR_EN_XI (1L<<7) 2306#define BCE_MISC_PERR_ENA1_MCPQ_PERR_EN_XI (1L<<8) 2307#define BCE_MISC_PERR_ENA1_TDMAQ_PERR_EN_XI (1L<<9) 2308#define BCE_MISC_PERR_ENA1_TXPQ_PERR_EN_XI (1L<<10) 2309#define BCE_MISC_PERR_ENA1_COMTQ_PERR_EN_XI (1L<<11) 2310#define BCE_MISC_PERR_ENA1_COMQ_PERR_EN_XI (1L<<12) 2311#define BCE_MISC_PERR_ENA1_RLUPQ_PERR_EN_XI (1L<<13) 2312#define BCE_MISC_PERR_ENA1_RXPQ_PERR_EN_XI (1L<<14) 2313#define BCE_MISC_PERR_ENA1_RV2PPQ_PERR_EN_XI (1L<<15) 2314#define BCE_MISC_PERR_ENA1_RDMAQ_PERR_EN_XI (1L<<16) 2315#define BCE_MISC_PERR_ENA1_TASQ_PERR_EN_XI (1L<<17) 2316#define BCE_MISC_PERR_ENA1_TBDRQ_PERR_EN_XI (1L<<18) 2317#define BCE_MISC_PERR_ENA1_TSCHQ_PERR_EN_XI (1L<<19) 2318#define BCE_MISC_PERR_ENA1_COMXQ_PERR_EN_XI (1L<<20) 2319#define BCE_MISC_PERR_ENA1_RXPCQ_PERR_EN_XI (1L<<21) 2320#define BCE_MISC_PERR_ENA1_RV2PTQ_PERR_EN_XI (1L<<22) 2321#define BCE_MISC_PERR_ENA1_RV2PMQ_PERR_EN_XI (1L<<23) 2322#define BCE_MISC_PERR_ENA1_CPQ_PERR_EN_XI (1L<<24) 2323#define BCE_MISC_PERR_ENA1_CSQ_PERR_EN_XI (1L<<25) 2324#define BCE_MISC_PERR_ENA1_RLUP_CID_PERR_EN_XI (1L<<26) 2325#define BCE_MISC_PERR_ENA1_RV2PCS_TMEM_PERR_EN_XI (1L<<27) 2326#define BCE_MISC_PERR_ENA1_RV2PCSQ_PERR_EN_XI (1L<<28) 2327#define BCE_MISC_PERR_ENA1_MQ_IDX_PERR_EN_XI (1L<<29) 2328 2329#define BCE_MISC_PERR_ENA2 0x000008ac 2330#define BCE_MISC_PERR_ENA2_COMQ_MISC (1L<<0) 2331#define BCE_MISC_PERR_ENA2_COMXQ_MISC (1L<<1) 2332#define BCE_MISC_PERR_ENA2_COMTQ_MISC (1L<<2) 2333#define BCE_MISC_PERR_ENA2_TSCHQ_MISC (1L<<3) 2334#define BCE_MISC_PERR_ENA2_TBDRQ_MISC (1L<<4) 2335#define BCE_MISC_PERR_ENA2_TXPQ_MISC (1L<<5) 2336#define BCE_MISC_PERR_ENA2_TDMAQ_MISC (1L<<6) 2337#define BCE_MISC_PERR_ENA2_TPATQ_MISC (1L<<7) 2338#define BCE_MISC_PERR_ENA2_TASQ_MISC (1L<<8) 2339#define BCE_MISC_PERR_ENA2_TGT_FIFO_PERR_EN_XI (1L<<0) 2340#define BCE_MISC_PERR_ENA2_UMP_TX_PERR_EN_XI (1L<<1) 2341#define BCE_MISC_PERR_ENA2_UMP_RX_PERR_EN_XI (1L<<2) 2342#define BCE_MISC_PERR_ENA2_MCP_ROM_PERR_EN_XI (1L<<3) 2343#define BCE_MISC_PERR_ENA2_MCP_SCPAD_PERR_EN_XI (1L<<4) 2344#define BCE_MISC_PERR_ENA2_HB_MEM_PERR_EN_XI (1L<<5) 2345#define BCE_MISC_PERR_ENA2_PCIE_REPLAY_PERR_EN_XI (1L<<6) 2346 2347#define BCE_MISC_DEBUG_VECTOR_SEL 0x000008b0 2348#define BCE_MISC_DEBUG_VECTOR_SEL_0 (0xfffL<<0) 2349#define BCE_MISC_DEBUG_VECTOR_SEL_1 (0xfffL<<12) 2350#define BCE_MISC_DEBUG_VECTOR_SEL_1_XI (0xfffL<<15) 2351 2352#define BCE_MISC_VREG_CONTROL 0x000008b4 2353#define BCE_MISC_VREG_CONTROL_1_2 (0xfL<<0) 2354#define BCE_MISC_VREG_CONTROL_1_0_MAIN_XI (0xfL<<0) 2355#define BCE_MISC_VREG_CONTROL_1_0_MAIN_PLUS14_XI (0L<<0) 2356#define BCE_MISC_VREG_CONTROL_1_0_MAIN_PLUS12_XI (1L<<0) 2357#define BCE_MISC_VREG_CONTROL_1_0_MAIN_PLUS10_XI (2L<<0) 2358#define BCE_MISC_VREG_CONTROL_1_0_MAIN_PLUS8_XI (3L<<0) 2359#define BCE_MISC_VREG_CONTROL_1_0_MAIN_PLUS6_XI (4L<<0) 2360#define BCE_MISC_VREG_CONTROL_1_0_MAIN_PLUS4_XI (5L<<0) 2361#define BCE_MISC_VREG_CONTROL_1_0_MAIN_PLUS2_XI (6L<<0) 2362#define BCE_MISC_VREG_CONTROL_1_0_MAIN_NOM_XI (7L<<0) 2363#define BCE_MISC_VREG_CONTROL_1_0_MAIN_MINUS2_XI (8L<<0) 2364#define BCE_MISC_VREG_CONTROL_1_0_MAIN_MINUS4_XI (9L<<0) 2365#define BCE_MISC_VREG_CONTROL_1_0_MAIN_MINUS6_XI (10L<<0) 2366#define BCE_MISC_VREG_CONTROL_1_0_MAIN_MINUS8_XI (11L<<0) 2367#define BCE_MISC_VREG_CONTROL_1_0_MAIN_MINUS10_XI (12L<<0) 2368#define BCE_MISC_VREG_CONTROL_1_0_MAIN_MINUS12_XI (13L<<0) 2369#define BCE_MISC_VREG_CONTROL_1_0_MAIN_MINUS14_XI (14L<<0) 2370#define BCE_MISC_VREG_CONTROL_1_0_MAIN_MINUS16_XI (15L<<0) 2371#define BCE_MISC_VREG_CONTROL_2_5 (0xfL<<4) 2372#define BCE_MISC_VREG_CONTROL_2_5_PLUS14 (0L<<4) 2373#define BCE_MISC_VREG_CONTROL_2_5_PLUS12 (1L<<4) 2374#define BCE_MISC_VREG_CONTROL_2_5_PLUS10 (2L<<4) 2375#define BCE_MISC_VREG_CONTROL_2_5_PLUS8 (3L<<4) 2376#define BCE_MISC_VREG_CONTROL_2_5_PLUS6 (4L<<4) 2377#define BCE_MISC_VREG_CONTROL_2_5_PLUS4 (5L<<4) 2378#define BCE_MISC_VREG_CONTROL_2_5_PLUS2 (6L<<4) 2379#define BCE_MISC_VREG_CONTROL_2_5_NOM (7L<<4) 2380#define BCE_MISC_VREG_CONTROL_2_5_MINUS2 (8L<<4) 2381#define BCE_MISC_VREG_CONTROL_2_5_MINUS4 (9L<<4) 2382#define BCE_MISC_VREG_CONTROL_2_5_MINUS6 (10L<<4) 2383#define BCE_MISC_VREG_CONTROL_2_5_MINUS8 (11L<<4) 2384#define BCE_MISC_VREG_CONTROL_2_5_MINUS10 (12L<<4) 2385#define BCE_MISC_VREG_CONTROL_2_5_MINUS12 (13L<<4) 2386#define BCE_MISC_VREG_CONTROL_2_5_MINUS14 (14L<<4) 2387#define BCE_MISC_VREG_CONTROL_2_5_MINUS16 (15L<<4) 2388#define BCE_MISC_VREG_CONTROL_1_0_MGMT (0xfL<<8) 2389#define BCE_MISC_VREG_CONTROL_1_0_MGMT_PLUS14 (0L<<8) 2390#define BCE_MISC_VREG_CONTROL_1_0_MGMT_PLUS12 (1L<<8) 2391#define BCE_MISC_VREG_CONTROL_1_0_MGMT_PLUS10 (2L<<8) 2392#define BCE_MISC_VREG_CONTROL_1_0_MGMT_PLUS8 (3L<<8) 2393#define BCE_MISC_VREG_CONTROL_1_0_MGMT_PLUS6 (4L<<8) 2394#define BCE_MISC_VREG_CONTROL_1_0_MGMT_PLUS4 (5L<<8) 2395#define BCE_MISC_VREG_CONTROL_1_0_MGMT_PLUS2 (6L<<8) 2396#define BCE_MISC_VREG_CONTROL_1_0_MGMT_NOM (7L<<8) 2397#define BCE_MISC_VREG_CONTROL_1_0_MGMT_MINUS2 (8L<<8) 2398#define BCE_MISC_VREG_CONTROL_1_0_MGMT_MINUS4 (9L<<8) 2399#define BCE_MISC_VREG_CONTROL_1_0_MGMT_MINUS6 (10L<<8) 2400#define BCE_MISC_VREG_CONTROL_1_0_MGMT_MINUS8 (11L<<8) 2401#define BCE_MISC_VREG_CONTROL_1_0_MGMT_MINUS10 (12L<<8) 2402#define BCE_MISC_VREG_CONTROL_1_0_MGMT_MINUS12 (13L<<8) 2403#define BCE_MISC_VREG_CONTROL_1_0_MGMT_MINUS14 (14L<<8) 2404#define BCE_MISC_VREG_CONTROL_1_0_MGMT_MINUS16 (15L<<8) 2405 2406#define BCE_MISC_FINAL_CLK_CTL_VAL 0x000008b8 2407#define BCE_MISC_FINAL_CLK_CTL_VAL_MISC_FINAL_CLK_CTL_VAL (0x3ffffffL<<6) 2408 2409#define BCE_MISC_GP_HW_CTL0 0x000008bc 2410#define BCE_MISC_GP_HW_CTL0_TX_DRIVE (1L<<0) 2411#define BCE_MISC_GP_HW_CTL0_RMII_MODE (1L<<1) 2412#define BCE_MISC_GP_HW_CTL0_RMII_CRSDV_SEL (1L<<2) 2413#define BCE_MISC_GP_HW_CTL0_RVMII_MODE (1L<<3) 2414#define BCE_MISC_GP_HW_CTL0_FLASH_SAMP_SCLK_NEGEDGE_TE (1L<<4) 2415#define BCE_MISC_GP_HW_CTL0_HIDDEN_REVISION_ID_TE (1L<<5) 2416#define BCE_MISC_GP_HW_CTL0_HC_CNTL_TMOUT_CTR_RST_TE (1L<<6) 2417#define BCE_MISC_GP_HW_CTL0_RESERVED1_XI (0x7L<<4) 2418#define BCE_MISC_GP_HW_CTL0_ENA_CORE_RST_ON_MAIN_PWR_GOING_AWAY (1L<<7) 2419#define BCE_MISC_GP_HW_CTL0_ENA_SEL_VAUX_B_IN_L2_TE (1L<<8) 2420#define BCE_MISC_GP_HW_CTL0_GRC_BNK_FREE_FIX_TE (1L<<9) 2421#define BCE_MISC_GP_HW_CTL0_LED_ACT_SEL_TE (1L<<10) 2422#define BCE_MISC_GP_HW_CTL0_RESERVED2_XI (0x7L<<8) 2423#define BCE_MISC_GP_HW_CTL0_UP1_DEF0 (1L<<11) 2424#define BCE_MISC_GP_HW_CTL0_FIBER_MODE_DIS_DEF (1L<<12) 2425#define BCE_MISC_GP_HW_CTL0_FORCE2500_DEF (1L<<13) 2426#define BCE_MISC_GP_HW_CTL0_AUTODETECT_DIS_DEF (1L<<14) 2427#define BCE_MISC_GP_HW_CTL0_PARALLEL_DETECT_DEF (1L<<15) 2428#define BCE_MISC_GP_HW_CTL0_OSCCTRL_DAI (0xfL<<16) 2429#define BCE_MISC_GP_HW_CTL0_OSCCTRL_DAI_3MA (0L<<16) 2430#define BCE_MISC_GP_HW_CTL0_OSCCTRL_DAI_2P5MA (1L<<16) 2431#define BCE_MISC_GP_HW_CTL0_OSCCTRL_DAI_2P0MA (3L<<16) 2432#define BCE_MISC_GP_HW_CTL0_OSCCTRL_DAI_1P5MA (5L<<16) 2433#define BCE_MISC_GP_HW_CTL0_OSCCTRL_DAI_1P0MA (7L<<16) 2434#define BCE_MISC_GP_HW_CTL0_OSCCTRL_DAI_PWRDN (15L<<16) 2435#define BCE_MISC_GP_HW_CTL0_OSCCTRL_PRE2DIS (1L<<20) 2436#define BCE_MISC_GP_HW_CTL0_OSCCTRL_PRE1DIS (1L<<21) 2437#define BCE_MISC_GP_HW_CTL0_OSCCTRL_CTAT (0x3L<<22) 2438#define BCE_MISC_GP_HW_CTL0_OSCCTRL_CTAT_M6P (0L<<22) 2439#define BCE_MISC_GP_HW_CTL0_OSCCTRL_CTAT_M0P (1L<<22) 2440#define BCE_MISC_GP_HW_CTL0_OSCCTRL_CTAT_P0P (2L<<22) 2441#define BCE_MISC_GP_HW_CTL0_OSCCTRL_CTAT_P6P (3L<<22) 2442#define BCE_MISC_GP_HW_CTL0_OSCCTRL_PTAT (0x3L<<24) 2443#define BCE_MISC_GP_HW_CTL0_OSCCTRL_PTAT_M6P (0L<<24) 2444#define BCE_MISC_GP_HW_CTL0_OSCCTRL_PTAT_M0P (1L<<24) 2445#define BCE_MISC_GP_HW_CTL0_OSCCTRL_PTAT_P0P (2L<<24) 2446#define BCE_MISC_GP_HW_CTL0_OSCCTRL_PTAT_P6P (3L<<24) 2447#define BCE_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ (0x3L<<26) 2448#define BCE_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_240UA (0L<<26) 2449#define BCE_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_160UA (1L<<26) 2450#define BCE_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_400UA (2L<<26) 2451#define BCE_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_320UA (3L<<26) 2452#define BCE_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ (0x3L<<28) 2453#define BCE_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_240UA (0L<<28) 2454#define BCE_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_160UA (1L<<28) 2455#define BCE_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_400UA (2L<<28) 2456#define BCE_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_320UA (3L<<28) 2457#define BCE_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ (0x3L<<30) 2458#define BCE_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P57 (0L<<30) 2459#define BCE_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P45 (1L<<30) 2460#define BCE_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P62 (2L<<30) 2461#define BCE_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P66 (3L<<30) 2462 2463#define BCE_MISC_GP_HW_CTL1 0x000008c0 2464#define BCE_MISC_GP_HW_CTL1_1_ATTN_BTN_PRSNT_TE (1L<<0) 2465#define BCE_MISC_GP_HW_CTL1_1_ATTN_IND_PRSNT_TE (1L<<1) 2466#define BCE_MISC_GP_HW_CTL1_1_PWR_IND_PRSNT_TE (1L<<2) 2467#define BCE_MISC_GP_HW_CTL1_0_PCIE_LOOPBACK_TE (1L<<3) 2468#define BCE_MISC_GP_HW_CTL1_RESERVED_SOFT_XI (0xffffL<<0) 2469#define BCE_MISC_GP_HW_CTL1_RESERVED_HARD_XI (0xffffL<<16) 2470 2471#define BCE_MISC_NEW_HW_CTL 0x000008c4 2472#define BCE_MISC_NEW_HW_CTL_MAIN_POR_BYPASS (1L<<0) 2473#define BCE_MISC_NEW_HW_CTL_RINGOSC_ENABLE (1L<<1) 2474#define BCE_MISC_NEW_HW_CTL_RINGOSC_SEL0 (1L<<2) 2475#define BCE_MISC_NEW_HW_CTL_RINGOSC_SEL1 (1L<<3) 2476#define BCE_MISC_NEW_HW_CTL_RESERVED_SHARED (0xfffL<<4) 2477#define BCE_MISC_NEW_HW_CTL_RESERVED_SPLIT (0xffffL<<16) 2478 2479#define BCE_MISC_NEW_CORE_CTL 0x000008c8 2480#define BCE_MISC_NEW_CORE_CTL_LINK_HOLDOFF_SUCCESS (1L<<0) 2481#define BCE_MISC_NEW_CORE_CTL_LINK_HOLDOFF_REQ (1L<<1) 2482#define BCE_MISC_NEW_CORE_CTL_DMA_ENABLE (1L<<16) 2483#define BCE_MISC_NEW_CORE_CTL_RESERVED_CMN (0x3fffL<<2) 2484#define BCE_MISC_NEW_CORE_CTL_RESERVED_TC (0xffffL<<16) 2485 2486#define BCE_MISC_ECO_HW_CTL 0x000008cc 2487#define BCE_MISC_ECO_HW_CTL_LARGE_GRC_TMOUT_EN (1L<<0) 2488#define BCE_MISC_ECO_HW_CTL_RESERVED_SOFT (0x7fffL<<1) 2489#define BCE_MISC_ECO_HW_CTL_RESERVED_HARD (0xffffL<<16) 2490 2491#define BCE_MISC_ECO_CORE_CTL 0x000008d0 2492#define BCE_MISC_ECO_CORE_CTL_RESERVED_SOFT (0xffffL<<0) 2493#define BCE_MISC_ECO_CORE_CTL_RESERVED_HARD (0xffffL<<16) 2494 2495#define BCE_MISC_PPIO 0x000008d4 2496#define BCE_MISC_PPIO_VALUE (0xfL<<0) 2497#define BCE_MISC_PPIO_SET (0xfL<<8) 2498#define BCE_MISC_PPIO_CLR (0xfL<<16) 2499#define BCE_MISC_PPIO_FLOAT (0xfL<<24) 2500 2501#define BCE_MISC_PPIO_INT 0x000008d8 2502#define BCE_MISC_PPIO_INT_INT_STATE (0xfL<<0) 2503#define BCE_MISC_PPIO_INT_OLD_VALUE (0xfL<<8) 2504#define BCE_MISC_PPIO_INT_OLD_SET (0xfL<<16) 2505#define BCE_MISC_PPIO_INT_OLD_CLR (0xfL<<24) 2506 2507#define BCE_MISC_RESET_NUMS 0x000008dc 2508#define BCE_MISC_RESET_NUMS_NUM_HARD_RESETS (0x7L<<0) 2509#define BCE_MISC_RESET_NUMS_NUM_PCIE_RESETS (0x7L<<4) 2510#define BCE_MISC_RESET_NUMS_NUM_PERSTB_RESETS (0x7L<<8) 2511#define BCE_MISC_RESET_NUMS_NUM_CMN_RESETS (0x7L<<12) 2512#define BCE_MISC_RESET_NUMS_NUM_PORT_RESETS (0x7L<<16) 2513 2514#define BCE_MISC_CS16_ERR 0x000008e0 2515#define BCE_MISC_CS16_ERR_ENA_PCI (1L<<0) 2516#define BCE_MISC_CS16_ERR_ENA_RDMA (1L<<1) 2517#define BCE_MISC_CS16_ERR_ENA_TDMA (1L<<2) 2518#define BCE_MISC_CS16_ERR_ENA_EMAC (1L<<3) 2519#define BCE_MISC_CS16_ERR_ENA_CTX (1L<<4) 2520#define BCE_MISC_CS16_ERR_ENA_TBDR (1L<<5) 2521#define BCE_MISC_CS16_ERR_ENA_RBDC (1L<<6) 2522#define BCE_MISC_CS16_ERR_ENA_COM (1L<<7) 2523#define BCE_MISC_CS16_ERR_ENA_CP (1L<<8) 2524#define BCE_MISC_CS16_ERR_STA_PCI (1L<<16) 2525#define BCE_MISC_CS16_ERR_STA_RDMA (1L<<17) 2526#define BCE_MISC_CS16_ERR_STA_TDMA (1L<<18) 2527#define BCE_MISC_CS16_ERR_STA_EMAC (1L<<19) 2528#define BCE_MISC_CS16_ERR_STA_CTX (1L<<20) 2529#define BCE_MISC_CS16_ERR_STA_TBDR (1L<<21) 2530#define BCE_MISC_CS16_ERR_STA_RBDC (1L<<22) 2531#define BCE_MISC_CS16_ERR_STA_COM (1L<<23) 2532#define BCE_MISC_CS16_ERR_STA_CP (1L<<24) 2533 2534#define BCE_MISC_SPIO_EVENT 0x000008e4 2535#define BCE_MISC_SPIO_EVENT_ENABLE (0xffL<<0) 2536 2537#define BCE_MISC_PPIO_EVENT 0x000008e8 2538#define BCE_MISC_PPIO_EVENT_ENABLE (0xfL<<0) 2539 2540#define BCE_MISC_DUAL_MEDIA_CTRL 0x000008ec 2541#define BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID (0xffL<<0) 2542#define BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_X (0L<<0) 2543#define BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_C (3L<<0) 2544#define BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_S (12L<<0) 2545#define BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP (0x7L<<8) 2546#define BCE_MISC_DUAL_MEDIA_CTRL_PORT_SWAP_PIN (1L<<11) 2547#define BCE_MISC_DUAL_MEDIA_CTRL_SERDES1_SIGDET (1L<<12) 2548#define BCE_MISC_DUAL_MEDIA_CTRL_SERDES0_SIGDET (1L<<13) 2549#define BCE_MISC_DUAL_MEDIA_CTRL_PHY1_SIGDET (1L<<14) 2550#define BCE_MISC_DUAL_MEDIA_CTRL_PHY0_SIGDET (1L<<15) 2551#define BCE_MISC_DUAL_MEDIA_CTRL_LCPLL_RST (1L<<16) 2552#define BCE_MISC_DUAL_MEDIA_CTRL_SERDES1_RST (1L<<17) 2553#define BCE_MISC_DUAL_MEDIA_CTRL_SERDES0_RST (1L<<18) 2554#define BCE_MISC_DUAL_MEDIA_CTRL_PHY1_RST (1L<<19) 2555#define BCE_MISC_DUAL_MEDIA_CTRL_PHY0_RST (1L<<20) 2556#define BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL (0x7L<<21) 2557#define BCE_MISC_DUAL_MEDIA_CTRL_PORT_SWAP (1L<<24) 2558#define BCE_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE (1L<<25) 2559#define BCE_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ (0xfL<<26) 2560#define BCE_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_SER1_IDDQ (1L<<26) 2561#define BCE_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_SER0_IDDQ (2L<<26) 2562#define BCE_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_PHY1_IDDQ (4L<<26) 2563#define BCE_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_PHY0_IDDQ (8L<<26) 2564 2565#define BCE_MISC_OTP_CMD1 0x000008f0 2566#define BCE_MISC_OTP_CMD1_FMODE (0x7L<<0) 2567#define BCE_MISC_OTP_CMD1_FMODE_IDLE (0L<<0) 2568#define BCE_MISC_OTP_CMD1_FMODE_WRITE (1L<<0) 2569#define BCE_MISC_OTP_CMD1_FMODE_INIT (2L<<0) 2570#define BCE_MISC_OTP_CMD1_FMODE_SET (3L<<0) 2571#define BCE_MISC_OTP_CMD1_FMODE_RST (4L<<0) 2572#define BCE_MISC_OTP_CMD1_FMODE_VERIFY (5L<<0) 2573#define BCE_MISC_OTP_CMD1_FMODE_RESERVED0 (6L<<0) 2574#define BCE_MISC_OTP_CMD1_FMODE_RESERVED1 (7L<<0) 2575#define BCE_MISC_OTP_CMD1_USEPINS (1L<<8) 2576#define BCE_MISC_OTP_CMD1_PROGSEL (1L<<9) 2577#define BCE_MISC_OTP_CMD1_PROGSTART (1L<<10) 2578#define BCE_MISC_OTP_CMD1_PCOUNT (0x7L<<16) 2579#define BCE_MISC_OTP_CMD1_PBYP (1L<<19) 2580#define BCE_MISC_OTP_CMD1_VSEL (0xfL<<20) 2581#define BCE_MISC_OTP_CMD1_TM (0x7L<<27) 2582#define BCE_MISC_OTP_CMD1_SADBYP (1L<<30) 2583#define BCE_MISC_OTP_CMD1_DEBUG (1L<<31) 2584 2585#define BCE_MISC_OTP_CMD2 0x000008f4 2586#define BCE_MISC_OTP_CMD2_OTP_ROM_ADDR (0x3ffL<<0) 2587#define BCE_MISC_OTP_CMD2_DOSEL (0x7fL<<16) 2588#define BCE_MISC_OTP_CMD2_DOSEL_0 (0L<<16) 2589#define BCE_MISC_OTP_CMD2_DOSEL_1 (1L<<16) 2590#define BCE_MISC_OTP_CMD2_DOSEL_127 (127L<<16) 2591 2592#define BCE_MISC_OTP_STATUS 0x000008f8 2593#define BCE_MISC_OTP_STATUS_DATA (0xffL<<0) 2594#define BCE_MISC_OTP_STATUS_VALID (1L<<8) 2595#define BCE_MISC_OTP_STATUS_BUSY (1L<<9) 2596#define BCE_MISC_OTP_STATUS_BUSYSM (1L<<10) 2597#define BCE_MISC_OTP_STATUS_DONE (1L<<11) 2598 2599#define BCE_MISC_OTP_SHIFT1_CMD 0x000008fc 2600#define BCE_MISC_OTP_SHIFT1_CMD_RESET_MODE_N (1L<<0) 2601#define BCE_MISC_OTP_SHIFT1_CMD_SHIFT_DONE (1L<<1) 2602#define BCE_MISC_OTP_SHIFT1_CMD_SHIFT_START (1L<<2) 2603#define BCE_MISC_OTP_SHIFT1_CMD_LOAD_DATA (1L<<3) 2604#define BCE_MISC_OTP_SHIFT1_CMD_SHIFT_SELECT (0x1fL<<8) 2605 2606#define BCE_MISC_OTP_SHIFT1_DATA 0x00000900 2607#define BCE_MISC_OTP_SHIFT2_CMD 0x00000904 2608#define BCE_MISC_OTP_SHIFT2_CMD_RESET_MODE_N (1L<<0) 2609#define BCE_MISC_OTP_SHIFT2_CMD_SHIFT_DONE (1L<<1) 2610#define BCE_MISC_OTP_SHIFT2_CMD_SHIFT_START (1L<<2) 2611#define BCE_MISC_OTP_SHIFT2_CMD_LOAD_DATA (1L<<3) 2612#define BCE_MISC_OTP_SHIFT2_CMD_SHIFT_SELECT (0x1fL<<8) 2613 2614#define BCE_MISC_OTP_SHIFT2_DATA 0x00000908 2615#define BCE_MISC_BIST_CS0 0x0000090c 2616#define BCE_MISC_BIST_CS0_MBIST_EN (1L<<0) 2617#define BCE_MISC_BIST_CS0_BIST_SETUP (0x3L<<1) 2618#define BCE_MISC_BIST_CS0_MBIST_ASYNC_RESET (1L<<3) 2619#define BCE_MISC_BIST_CS0_MBIST_DONE (1L<<8) 2620#define BCE_MISC_BIST_CS0_MBIST_GO (1L<<9) 2621#define BCE_MISC_BIST_CS0_BIST_OVERRIDE (1L<<31) 2622 2623#define BCE_MISC_BIST_MEMSTATUS0 0x00000910 2624#define BCE_MISC_BIST_CS1 0x00000914 2625#define BCE_MISC_BIST_CS1_MBIST_EN (1L<<0) 2626#define BCE_MISC_BIST_CS1_BIST_SETUP (0x3L<<1) 2627#define BCE_MISC_BIST_CS1_MBIST_ASYNC_RESET (1L<<3) 2628#define BCE_MISC_BIST_CS1_MBIST_DONE (1L<<8) 2629#define BCE_MISC_BIST_CS1_MBIST_GO (1L<<9) 2630 2631#define BCE_MISC_BIST_MEMSTATUS1 0x00000918 2632#define BCE_MISC_BIST_CS2 0x0000091c 2633#define BCE_MISC_BIST_CS2_MBIST_EN (1L<<0) 2634#define BCE_MISC_BIST_CS2_BIST_SETUP (0x3L<<1) 2635#define BCE_MISC_BIST_CS2_MBIST_ASYNC_RESET (1L<<3) 2636#define BCE_MISC_BIST_CS2_MBIST_DONE (1L<<8) 2637#define BCE_MISC_BIST_CS2_MBIST_GO (1L<<9) 2638 2639#define BCE_MISC_BIST_MEMSTATUS2 0x00000920 2640#define BCE_MISC_BIST_CS3 0x00000924 2641#define BCE_MISC_BIST_CS3_MBIST_EN (1L<<0) 2642#define BCE_MISC_BIST_CS3_BIST_SETUP (0x3L<<1) 2643#define BCE_MISC_BIST_CS3_MBIST_ASYNC_RESET (1L<<3) 2644#define BCE_MISC_BIST_CS3_MBIST_DONE (1L<<8) 2645#define BCE_MISC_BIST_CS3_MBIST_GO (1L<<9) 2646 2647#define BCE_MISC_BIST_MEMSTATUS3 0x00000928 2648#define BCE_MISC_BIST_CS4 0x0000092c 2649#define BCE_MISC_BIST_CS4_MBIST_EN (1L<<0) 2650#define BCE_MISC_BIST_CS4_BIST_SETUP (0x3L<<1) 2651#define BCE_MISC_BIST_CS4_MBIST_ASYNC_RESET (1L<<3) 2652#define BCE_MISC_BIST_CS4_MBIST_DONE (1L<<8) 2653#define BCE_MISC_BIST_CS4_MBIST_GO (1L<<9) 2654 2655#define BCE_MISC_BIST_MEMSTATUS4 0x00000930 2656#define BCE_MISC_BIST_CS5 0x00000934 2657#define BCE_MISC_BIST_CS5_MBIST_EN (1L<<0) 2658#define BCE_MISC_BIST_CS5_BIST_SETUP (0x3L<<1) 2659#define BCE_MISC_BIST_CS5_MBIST_ASYNC_RESET (1L<<3) 2660#define BCE_MISC_BIST_CS5_MBIST_DONE (1L<<8) 2661#define BCE_MISC_BIST_CS5_MBIST_GO (1L<<9) 2662 2663#define BCE_MISC_BIST_MEMSTATUS5 0x00000938 2664#define BCE_MISC_MEM_TM0 0x0000093c 2665#define BCE_MISC_MEM_TM0_PCIE_REPLAY_TM (0xfL<<0) 2666#define BCE_MISC_MEM_TM0_MCP_SCPAD (0xfL<<8) 2667#define BCE_MISC_MEM_TM0_UMP_TM (0xffL<<16) 2668#define BCE_MISC_MEM_TM0_HB_MEM_TM (0xfL<<24) 2669 2670#define BCE_MISC_USPLL_CTRL 0x00000940 2671#define BCE_MISC_USPLL_CTRL_PH_DET_DIS (1L<<0) 2672#define BCE_MISC_USPLL_CTRL_FREQ_DET_DIS (1L<<1) 2673#define BCE_MISC_USPLL_CTRL_LCPX (0x3fL<<2) 2674#define BCE_MISC_USPLL_CTRL_RX (0x3L<<8) 2675#define BCE_MISC_USPLL_CTRL_VC_EN (1L<<10) 2676#define BCE_MISC_USPLL_CTRL_VCO_MG (0x3L<<11) 2677#define BCE_MISC_USPLL_CTRL_KVCO_XF (0x7L<<13) 2678#define BCE_MISC_USPLL_CTRL_KVCO_XS (0x7L<<16) 2679#define BCE_MISC_USPLL_CTRL_TESTD_EN (1L<<19) 2680#define BCE_MISC_USPLL_CTRL_TESTD_SEL (0x7L<<20) 2681#define BCE_MISC_USPLL_CTRL_TESTA_EN (1L<<23) 2682#define BCE_MISC_USPLL_CTRL_TESTA_SEL (0x3L<<24) 2683#define BCE_MISC_USPLL_CTRL_ATTEN_FREF (1L<<26) 2684#define BCE_MISC_USPLL_CTRL_DIGITAL_RST (1L<<27) 2685#define BCE_MISC_USPLL_CTRL_ANALOG_RST (1L<<28) 2686#define BCE_MISC_USPLL_CTRL_LOCK (1L<<29) 2687 2688#define BCE_MISC_PERR_STATUS0 0x00000944 2689#define BCE_MISC_PERR_STATUS0_COM_DMAE_PERR (1L<<0) 2690#define BCE_MISC_PERR_STATUS0_CP_DMAE_PERR (1L<<1) 2691#define BCE_MISC_PERR_STATUS0_RPM_ACPIBEMEM_PERR (1L<<2) 2692#define BCE_MISC_PERR_STATUS0_CTX_USAGE_CNT_PERR (1L<<3) 2693#define BCE_MISC_PERR_STATUS0_CTX_PGTBL_PERR (1L<<4) 2694#define BCE_MISC_PERR_STATUS0_CTX_CACHE_PERR (1L<<5) 2695#define BCE_MISC_PERR_STATUS0_CTX_MIRROR_PERR (1L<<6) 2696#define BCE_MISC_PERR_STATUS0_COM_CTXC_PERR (1L<<7) 2697#define BCE_MISC_PERR_STATUS0_COM_SCPAD_PERR (1L<<8) 2698#define BCE_MISC_PERR_STATUS0_CP_CTXC_PERR (1L<<9) 2699#define BCE_MISC_PERR_STATUS0_CP_SCPAD_PERR (1L<<10) 2700#define BCE_MISC_PERR_STATUS0_RXP_RBUFC_PERR (1L<<11) 2701#define BCE_MISC_PERR_STATUS0_RXP_CTXC_PERR (1L<<12) 2702#define BCE_MISC_PERR_STATUS0_RXP_SCPAD_PERR (1L<<13) 2703#define BCE_MISC_PERR_STATUS0_TPAT_SCPAD_PERR (1L<<14) 2704#define BCE_MISC_PERR_STATUS0_TXP_CTXC_PERR (1L<<15) 2705#define BCE_MISC_PERR_STATUS0_TXP_SCPAD_PERR (1L<<16) 2706#define BCE_MISC_PERR_STATUS0_CS_TMEM_PERR (1L<<17) 2707#define BCE_MISC_PERR_STATUS0_MQ_CTX_PERR (1L<<18) 2708#define BCE_MISC_PERR_STATUS0_RPM_DFIFOMEM_PERR (1L<<19) 2709#define BCE_MISC_PERR_STATUS0_RPC_DFIFOMEM_PERR (1L<<20) 2710#define BCE_MISC_PERR_STATUS0_RBUF_PTRMEM_PERR (1L<<21) 2711#define BCE_MISC_PERR_STATUS0_RBUF_DATAMEM_PERR (1L<<22) 2712#define BCE_MISC_PERR_STATUS0_RV2P_P2IRAM_PERR (1L<<23) 2713#define BCE_MISC_PERR_STATUS0_RV2P_P1IRAM_PERR (1L<<24) 2714#define BCE_MISC_PERR_STATUS0_RV2P_CB1REGS_PERR (1L<<25) 2715#define BCE_MISC_PERR_STATUS0_RV2P_CB0REGS_PERR (1L<<26) 2716#define BCE_MISC_PERR_STATUS0_TPBUF_PERR (1L<<27) 2717#define BCE_MISC_PERR_STATUS0_THBUF_PERR (1L<<28) 2718#define BCE_MISC_PERR_STATUS0_TDMA_PERR (1L<<29) 2719#define BCE_MISC_PERR_STATUS0_TBDC_PERR (1L<<30) 2720#define BCE_MISC_PERR_STATUS0_TSCH_LR_PERR (1L<<31) 2721 2722#define BCE_MISC_PERR_STATUS1 0x00000948 2723#define BCE_MISC_PERR_STATUS1_RBDC_PERR (1L<<0) 2724#define BCE_MISC_PERR_STATUS1_RDMA_DFIFO_PERR (1L<<2) 2725#define BCE_MISC_PERR_STATUS1_HC_STATS_PERR (1L<<3) 2726#define BCE_MISC_PERR_STATUS1_HC_MSIX_PERR (1L<<4) 2727#define BCE_MISC_PERR_STATUS1_HC_PRODUCSTB_PERR (1L<<5) 2728#define BCE_MISC_PERR_STATUS1_HC_CONSUMSTB_PERR (1L<<6) 2729#define BCE_MISC_PERR_STATUS1_TPATQ_PERR (1L<<7) 2730#define BCE_MISC_PERR_STATUS1_MCPQ_PERR (1L<<8) 2731#define BCE_MISC_PERR_STATUS1_TDMAQ_PERR (1L<<9) 2732#define BCE_MISC_PERR_STATUS1_TXPQ_PERR (1L<<10) 2733#define BCE_MISC_PERR_STATUS1_COMTQ_PERR (1L<<11) 2734#define BCE_MISC_PERR_STATUS1_COMQ_PERR (1L<<12) 2735#define BCE_MISC_PERR_STATUS1_RLUPQ_PERR (1L<<13) 2736#define BCE_MISC_PERR_STATUS1_RXPQ_PERR (1L<<14) 2737#define BCE_MISC_PERR_STATUS1_RV2PPQ_PERR (1L<<15) 2738#define BCE_MISC_PERR_STATUS1_RDMAQ_PERR (1L<<16) 2739#define BCE_MISC_PERR_STATUS1_TASQ_PERR (1L<<17) 2740#define BCE_MISC_PERR_STATUS1_TBDRQ_PERR (1L<<18) 2741#define BCE_MISC_PERR_STATUS1_TSCHQ_PERR (1L<<19) 2742#define BCE_MISC_PERR_STATUS1_COMXQ_PERR (1L<<20) 2743#define BCE_MISC_PERR_STATUS1_RXPCQ_PERR (1L<<21) 2744#define BCE_MISC_PERR_STATUS1_RV2PTQ_PERR (1L<<22) 2745#define BCE_MISC_PERR_STATUS1_RV2PMQ_PERR (1L<<23) 2746#define BCE_MISC_PERR_STATUS1_CPQ_PERR (1L<<24) 2747#define BCE_MISC_PERR_STATUS1_CSQ_PERR (1L<<25) 2748#define BCE_MISC_PERR_STATUS1_RLUP_CID_PERR (1L<<26) 2749#define BCE_MISC_PERR_STATUS1_RV2PCS_TMEM_PERR (1L<<27) 2750#define BCE_MISC_PERR_STATUS1_RV2PCSQ_PERR (1L<<28) 2751#define BCE_MISC_PERR_STATUS1_MQ_IDX_PERR (1L<<29) 2752 2753#define BCE_MISC_PERR_STATUS2 0x0000094c 2754#define BCE_MISC_PERR_STATUS2_TGT_FIFO_PERR (1L<<0) 2755#define BCE_MISC_PERR_STATUS2_UMP_TX_PERR (1L<<1) 2756#define BCE_MISC_PERR_STATUS2_UMP_RX_PERR (1L<<2) 2757#define BCE_MISC_PERR_STATUS2_MCP_ROM_PERR (1L<<3) 2758#define BCE_MISC_PERR_STATUS2_MCP_SCPAD_PERR (1L<<4) 2759#define BCE_MISC_PERR_STATUS2_HB_MEM_PERR (1L<<5) 2760#define BCE_MISC_PERR_STATUS2_PCIE_REPLAY_PERR (1L<<6) 2761 2762#define BCE_MISC_LCPLL_CTRL0 0x00000950 2763#define BCE_MISC_LCPLL_CTRL0_OAC (0x7L<<0) 2764#define BCE_MISC_LCPLL_CTRL0_OAC_NEGTWENTY (0L<<0) 2765#define BCE_MISC_LCPLL_CTRL0_OAC_ZERO (1L<<0) 2766#define BCE_MISC_LCPLL_CTRL0_OAC_TWENTY (3L<<0) 2767#define BCE_MISC_LCPLL_CTRL0_OAC_FORTY (7L<<0) 2768#define BCE_MISC_LCPLL_CTRL0_ICP_CTRL (0x7L<<3) 2769#define BCE_MISC_LCPLL_CTRL0_ICP_CTRL_360 (0L<<3) 2770#define BCE_MISC_LCPLL_CTRL0_ICP_CTRL_480 (1L<<3) 2771#define BCE_MISC_LCPLL_CTRL0_ICP_CTRL_600 (3L<<3) 2772#define BCE_MISC_LCPLL_CTRL0_ICP_CTRL_720 (7L<<3) 2773#define BCE_MISC_LCPLL_CTRL0_BIAS_CTRL (0x3L<<6) 2774#define BCE_MISC_LCPLL_CTRL0_PLL_OBSERVE (0x7L<<8) 2775#define BCE_MISC_LCPLL_CTRL0_VTH_CTRL (0x3L<<11) 2776#define BCE_MISC_LCPLL_CTRL0_VTH_CTRL_0 (0L<<11) 2777#define BCE_MISC_LCPLL_CTRL0_VTH_CTRL_1 (1L<<11) 2778#define BCE_MISC_LCPLL_CTRL0_VTH_CTRL_2 (2L<<11) 2779#define BCE_MISC_LCPLL_CTRL0_PLLSEQSTART (1L<<13) 2780#define BCE_MISC_LCPLL_CTRL0_RESERVED (1L<<14) 2781#define BCE_MISC_LCPLL_CTRL0_CAPRETRY_EN (1L<<15) 2782#define BCE_MISC_LCPLL_CTRL0_FREQMONITOR_EN (1L<<16) 2783#define BCE_MISC_LCPLL_CTRL0_FREQDETRESTART_EN (1L<<17) 2784#define BCE_MISC_LCPLL_CTRL0_FREQDETRETRY_EN (1L<<18) 2785#define BCE_MISC_LCPLL_CTRL0_PLLFORCEFDONE_EN (1L<<19) 2786#define BCE_MISC_LCPLL_CTRL0_PLLFORCEFDONE (1L<<20) 2787#define BCE_MISC_LCPLL_CTRL0_PLLFORCEFPASS (1L<<21) 2788#define BCE_MISC_LCPLL_CTRL0_PLLFORCECAPDONE_EN (1L<<22) 2789#define BCE_MISC_LCPLL_CTRL0_PLLFORCECAPDONE (1L<<23) 2790#define BCE_MISC_LCPLL_CTRL0_PLLFORCECAPPASS_EN (1L<<24) 2791#define BCE_MISC_LCPLL_CTRL0_PLLFORCECAPPASS (1L<<25) 2792#define BCE_MISC_LCPLL_CTRL0_CAPRESTART (1L<<26) 2793#define BCE_MISC_LCPLL_CTRL0_CAPSELECTM_EN (1L<<27) 2794 2795#define BCE_MISC_LCPLL_CTRL1 0x00000954 2796#define BCE_MISC_LCPLL_CTRL1_CAPSELECTM (0x1fL<<0) 2797#define BCE_MISC_LCPLL_CTRL1_CAPFORCESLOWDOWN_EN (1L<<5) 2798#define BCE_MISC_LCPLL_CTRL1_CAPFORCESLOWDOWN (1L<<6) 2799#define BCE_MISC_LCPLL_CTRL1_SLOWDN_XOR (1L<<7) 2800 2801#define BCE_MISC_LCPLL_STATUS 0x00000958 2802#define BCE_MISC_LCPLL_STATUS_FREQDONE_SM (1L<<0) 2803#define BCE_MISC_LCPLL_STATUS_FREQPASS_SM (1L<<1) 2804#define BCE_MISC_LCPLL_STATUS_PLLSEQDONE (1L<<2) 2805#define BCE_MISC_LCPLL_STATUS_PLLSEQPASS (1L<<3) 2806#define BCE_MISC_LCPLL_STATUS_PLLSTATE (0x7L<<4) 2807#define BCE_MISC_LCPLL_STATUS_CAPSTATE (0x7L<<7) 2808#define BCE_MISC_LCPLL_STATUS_CAPSELECT (0x1fL<<10) 2809#define BCE_MISC_LCPLL_STATUS_SLOWDN_INDICATOR (1L<<15) 2810#define BCE_MISC_LCPLL_STATUS_SLOWDN_INDICATOR_0 (0L<<15) 2811#define BCE_MISC_LCPLL_STATUS_SLOWDN_INDICATOR_1 (1L<<15) 2812 2813#define BCE_MISC_OSCFUNDS_CTRL 0x0000095c 2814#define BCE_MISC_OSCFUNDS_CTRL_FREQ_MON (1L<<5) 2815#define BCE_MISC_OSCFUNDS_CTRL_FREQ_MON_OFF (0L<<5) 2816#define BCE_MISC_OSCFUNDS_CTRL_FREQ_MON_ON (1L<<5) 2817#define BCE_MISC_OSCFUNDS_CTRL_XTAL_ADJCM (0x3L<<6) 2818#define BCE_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_0 (0L<<6) 2819#define BCE_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_1 (1L<<6) 2820#define BCE_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_2 (2L<<6) 2821#define BCE_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_3 (3L<<6) 2822#define BCE_MISC_OSCFUNDS_CTRL_ICBUF_ADJ (0x3L<<8) 2823#define BCE_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_0 (0L<<8) 2824#define BCE_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_1 (1L<<8) 2825#define BCE_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_2 (2L<<8) 2826#define BCE_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_3 (3L<<8) 2827#define BCE_MISC_OSCFUNDS_CTRL_IAMP_ADJ (0x3L<<10) 2828#define BCE_MISC_OSCFUNDS_CTRL_IAMP_ADJ_0 (0L<<10) 2829#define BCE_MISC_OSCFUNDS_CTRL_IAMP_ADJ_1 (1L<<10) 2830#define BCE_MISC_OSCFUNDS_CTRL_IAMP_ADJ_2 (2L<<10) 2831#define BCE_MISC_OSCFUNDS_CTRL_IAMP_ADJ_3 (3L<<10) 2832 2833 2834/* 2835 * dma_reg definition 2836 * offset: 0xc00 2837 */ 2838#define BCE_DMA_COMMAND 0x00000c00 2839#define BCE_DMA_COMMAND_ENABLE (1L<<0) 2840 2841#define BCE_DMA_STATUS 0x00000c04 2842#define BCE_DMA_STATUS_PAR_ERROR_STATE (1L<<0) 2843#define BCE_DMA_STATUS_READ_TRANSFERS_STAT (1L<<16) 2844#define BCE_DMA_STATUS_READ_DELAY_PCI_CLKS_STAT (1L<<17) 2845#define BCE_DMA_STATUS_BIG_READ_TRANSFERS_STAT (1L<<18) 2846#define BCE_DMA_STATUS_BIG_READ_DELAY_PCI_CLKS_STAT (1L<<19) 2847#define BCE_DMA_STATUS_BIG_READ_RETRY_AFTER_DATA_STAT (1L<<20) 2848#define BCE_DMA_STATUS_WRITE_TRANSFERS_STAT (1L<<21) 2849#define BCE_DMA_STATUS_WRITE_DELAY_PCI_CLKS_STAT (1L<<22) 2850#define BCE_DMA_STATUS_BIG_WRITE_TRANSFERS_STAT (1L<<23) 2851#define BCE_DMA_STATUS_BIG_WRITE_DELAY_PCI_CLKS_STAT (1L<<24) 2852#define BCE_DMA_STATUS_BIG_WRITE_RETRY_AFTER_DATA_STAT (1L<<25) 2853 2854#define BCE_DMA_CONFIG 0x00000c08 2855#define BCE_DMA_CONFIG_DATA_BYTE_SWAP (1L<<0) 2856#define BCE_DMA_CONFIG_DATA_WORD_SWAP (1L<<1) 2857#define BCE_DMA_CONFIG_CNTL_BYTE_SWAP (1L<<4) 2858#define BCE_DMA_CONFIG_CNTL_WORD_SWAP (1L<<5) 2859#define BCE_DMA_CONFIG_ONE_DMA (1L<<6) 2860#define BCE_DMA_CONFIG_CNTL_TWO_DMA (1L<<7) 2861#define BCE_DMA_CONFIG_CNTL_FPGA_MODE (1L<<8) 2862#define BCE_DMA_CONFIG_CNTL_PING_PONG_DMA (1L<<10) 2863#define BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY (1L<<11) 2864#define BCE_DMA_CONFIG_NO_RCHANS_IN_USE (0xfL<<12) 2865#define BCE_DMA_CONFIG_NO_WCHANS_IN_USE (0xfL<<16) 2866#define BCE_DMA_CONFIG_PCI_CLK_CMP_BITS (0x7L<<20) 2867#define BCE_DMA_CONFIG_PCI_FAST_CLK_CMP (1L<<23) 2868#define BCE_DMA_CONFIG_BIG_SIZE (0xfL<<24) 2869#define BCE_DMA_CONFIG_BIG_SIZE_NONE (0x0L<<24) 2870#define BCE_DMA_CONFIG_BIG_SIZE_64 (0x1L<<24) 2871#define BCE_DMA_CONFIG_BIG_SIZE_128 (0x2L<<24) 2872#define BCE_DMA_CONFIG_BIG_SIZE_256 (0x4L<<24) 2873#define BCE_DMA_CONFIG_BIG_SIZE_512 (0x8L<<24) 2874 2875#define BCE_DMA_BLACKOUT 0x00000c0c 2876#define BCE_DMA_BLACKOUT_RD_RETRY_BLACKOUT (0xffL<<0) 2877#define BCE_DMA_BLACKOUT_2ND_RD_RETRY_BLACKOUT (0xffL<<8) 2878#define BCE_DMA_BLACKOUT_WR_RETRY_BLACKOUT (0xffL<<16) 2879 2880#define BCE_DMA_RCHAN_STAT 0x00000c30 2881#define BCE_DMA_RCHAN_STAT_COMP_CODE_0 (0x7L<<0) 2882#define BCE_DMA_RCHAN_STAT_PAR_ERR_0 (1L<<3) 2883#define BCE_DMA_RCHAN_STAT_COMP_CODE_1 (0x7L<<4) 2884#define BCE_DMA_RCHAN_STAT_PAR_ERR_1 (1L<<7) 2885#define BCE_DMA_RCHAN_STAT_COMP_CODE_2 (0x7L<<8) 2886#define BCE_DMA_RCHAN_STAT_PAR_ERR_2 (1L<<11) 2887#define BCE_DMA_RCHAN_STAT_COMP_CODE_3 (0x7L<<12) 2888#define BCE_DMA_RCHAN_STAT_PAR_ERR_3 (1L<<15) 2889#define BCE_DMA_RCHAN_STAT_COMP_CODE_4 (0x7L<<16) 2890#define BCE_DMA_RCHAN_STAT_PAR_ERR_4 (1L<<19) 2891#define BCE_DMA_RCHAN_STAT_COMP_CODE_5 (0x7L<<20) 2892#define BCE_DMA_RCHAN_STAT_PAR_ERR_5 (1L<<23) 2893#define BCE_DMA_RCHAN_STAT_COMP_CODE_6 (0x7L<<24) 2894#define BCE_DMA_RCHAN_STAT_PAR_ERR_6 (1L<<27) 2895#define BCE_DMA_RCHAN_STAT_COMP_CODE_7 (0x7L<<28) 2896#define BCE_DMA_RCHAN_STAT_PAR_ERR_7 (1L<<31) 2897 2898#define BCE_DMA_WCHAN_STAT 0x00000c34 2899#define BCE_DMA_WCHAN_STAT_COMP_CODE_0 (0x7L<<0) 2900#define BCE_DMA_WCHAN_STAT_PAR_ERR_0 (1L<<3) 2901#define BCE_DMA_WCHAN_STAT_COMP_CODE_1 (0x7L<<4) 2902#define BCE_DMA_WCHAN_STAT_PAR_ERR_1 (1L<<7) 2903#define BCE_DMA_WCHAN_STAT_COMP_CODE_2 (0x7L<<8) 2904#define BCE_DMA_WCHAN_STAT_PAR_ERR_2 (1L<<11) 2905#define BCE_DMA_WCHAN_STAT_COMP_CODE_3 (0x7L<<12) 2906#define BCE_DMA_WCHAN_STAT_PAR_ERR_3 (1L<<15) 2907#define BCE_DMA_WCHAN_STAT_COMP_CODE_4 (0x7L<<16) 2908#define BCE_DMA_WCHAN_STAT_PAR_ERR_4 (1L<<19) 2909#define BCE_DMA_WCHAN_STAT_COMP_CODE_5 (0x7L<<20) 2910#define BCE_DMA_WCHAN_STAT_PAR_ERR_5 (1L<<23) 2911#define BCE_DMA_WCHAN_STAT_COMP_CODE_6 (0x7L<<24) 2912#define BCE_DMA_WCHAN_STAT_PAR_ERR_6 (1L<<27) 2913#define BCE_DMA_WCHAN_STAT_COMP_CODE_7 (0x7L<<28) 2914#define BCE_DMA_WCHAN_STAT_PAR_ERR_7 (1L<<31) 2915 2916#define BCE_DMA_RCHAN_ASSIGNMENT 0x00000c38 2917#define BCE_DMA_RCHAN_ASSIGNMENT_0 (0xfL<<0) 2918#define BCE_DMA_RCHAN_ASSIGNMENT_1 (0xfL<<4) 2919#define BCE_DMA_RCHAN_ASSIGNMENT_2 (0xfL<<8) 2920#define BCE_DMA_RCHAN_ASSIGNMENT_3 (0xfL<<12) 2921#define BCE_DMA_RCHAN_ASSIGNMENT_4 (0xfL<<16) 2922#define BCE_DMA_RCHAN_ASSIGNMENT_5 (0xfL<<20) 2923#define BCE_DMA_RCHAN_ASSIGNMENT_6 (0xfL<<24) 2924#define BCE_DMA_RCHAN_ASSIGNMENT_7 (0xfL<<28) 2925 2926#define BCE_DMA_WCHAN_ASSIGNMENT 0x00000c3c 2927#define BCE_DMA_WCHAN_ASSIGNMENT_0 (0xfL<<0) 2928#define BCE_DMA_WCHAN_ASSIGNMENT_1 (0xfL<<4) 2929#define BCE_DMA_WCHAN_ASSIGNMENT_2 (0xfL<<8) 2930#define BCE_DMA_WCHAN_ASSIGNMENT_3 (0xfL<<12) 2931#define BCE_DMA_WCHAN_ASSIGNMENT_4 (0xfL<<16) 2932#define BCE_DMA_WCHAN_ASSIGNMENT_5 (0xfL<<20) 2933#define BCE_DMA_WCHAN_ASSIGNMENT_6 (0xfL<<24) 2934#define BCE_DMA_WCHAN_ASSIGNMENT_7 (0xfL<<28) 2935 2936#define BCE_DMA_RCHAN_STAT_00 0x00000c40 2937#define BCE_DMA_RCHAN_STAT_00_RCHAN_STA_HOST_ADDR_LOW (0xffffffffL<<0) 2938 2939#define BCE_DMA_RCHAN_STAT_01 0x00000c44 2940#define BCE_DMA_RCHAN_STAT_01_RCHAN_STA_HOST_ADDR_HIGH (0xffffffffL<<0) 2941 2942#define BCE_DMA_RCHAN_STAT_02 0x00000c48 2943#define BCE_DMA_RCHAN_STAT_02_LENGTH (0xffffL<<0) 2944#define BCE_DMA_RCHAN_STAT_02_WORD_SWAP (1L<<16) 2945#define BCE_DMA_RCHAN_STAT_02_BYTE_SWAP (1L<<17) 2946#define BCE_DMA_RCHAN_STAT_02_PRIORITY_LVL (1L<<18) 2947 2948#define BCE_DMA_RCHAN_STAT_10 0x00000c4c 2949#define BCE_DMA_RCHAN_STAT_11 0x00000c50 2950#define BCE_DMA_RCHAN_STAT_12 0x00000c54 2951#define BCE_DMA_RCHAN_STAT_20 0x00000c58 2952#define BCE_DMA_RCHAN_STAT_21 0x00000c5c 2953#define BCE_DMA_RCHAN_STAT_22 0x00000c60 2954#define BCE_DMA_RCHAN_STAT_30 0x00000c64 2955#define BCE_DMA_RCHAN_STAT_31 0x00000c68 2956#define BCE_DMA_RCHAN_STAT_32 0x00000c6c 2957#define BCE_DMA_RCHAN_STAT_40 0x00000c70 2958#define BCE_DMA_RCHAN_STAT_41 0x00000c74 2959#define BCE_DMA_RCHAN_STAT_42 0x00000c78 2960#define BCE_DMA_RCHAN_STAT_50 0x00000c7c 2961#define BCE_DMA_RCHAN_STAT_51 0x00000c80 2962#define BCE_DMA_RCHAN_STAT_52 0x00000c84 2963#define BCE_DMA_RCHAN_STAT_60 0x00000c88 2964#define BCE_DMA_RCHAN_STAT_61 0x00000c8c 2965#define BCE_DMA_RCHAN_STAT_62 0x00000c90 2966#define BCE_DMA_RCHAN_STAT_70 0x00000c94 2967#define BCE_DMA_RCHAN_STAT_71 0x00000c98 2968#define BCE_DMA_RCHAN_STAT_72 0x00000c9c 2969#define BCE_DMA_WCHAN_STAT_00 0x00000ca0 2970#define BCE_DMA_WCHAN_STAT_00_WCHAN_STA_HOST_ADDR_LOW (0xffffffffL<<0) 2971 2972#define BCE_DMA_WCHAN_STAT_01 0x00000ca4 2973#define BCE_DMA_WCHAN_STAT_01_WCHAN_STA_HOST_ADDR_HIGH (0xffffffffL<<0) 2974 2975#define BCE_DMA_WCHAN_STAT_02 0x00000ca8 2976#define BCE_DMA_WCHAN_STAT_02_LENGTH (0xffffL<<0) 2977#define BCE_DMA_WCHAN_STAT_02_WORD_SWAP (1L<<16) 2978#define BCE_DMA_WCHAN_STAT_02_BYTE_SWAP (1L<<17) 2979#define BCE_DMA_WCHAN_STAT_02_PRIORITY_LVL (1L<<18) 2980 2981#define BCE_DMA_WCHAN_STAT_10 0x00000cac 2982#define BCE_DMA_WCHAN_STAT_11 0x00000cb0 2983#define BCE_DMA_WCHAN_STAT_12 0x00000cb4 2984#define BCE_DMA_WCHAN_STAT_20 0x00000cb8 2985#define BCE_DMA_WCHAN_STAT_21 0x00000cbc 2986#define BCE_DMA_WCHAN_STAT_22 0x00000cc0 2987#define BCE_DMA_WCHAN_STAT_30 0x00000cc4 2988#define BCE_DMA_WCHAN_STAT_31 0x00000cc8 2989#define BCE_DMA_WCHAN_STAT_32 0x00000ccc 2990#define BCE_DMA_WCHAN_STAT_40 0x00000cd0 2991#define BCE_DMA_WCHAN_STAT_41 0x00000cd4 2992#define BCE_DMA_WCHAN_STAT_42 0x00000cd8 2993#define BCE_DMA_WCHAN_STAT_50 0x00000cdc 2994#define BCE_DMA_WCHAN_STAT_51 0x00000ce0 2995#define BCE_DMA_WCHAN_STAT_52 0x00000ce4 2996#define BCE_DMA_WCHAN_STAT_60 0x00000ce8 2997#define BCE_DMA_WCHAN_STAT_61 0x00000cec 2998#define BCE_DMA_WCHAN_STAT_62 0x00000cf0 2999#define BCE_DMA_WCHAN_STAT_70 0x00000cf4 3000#define BCE_DMA_WCHAN_STAT_71 0x00000cf8 3001#define BCE_DMA_WCHAN_STAT_72 0x00000cfc 3002#define BCE_DMA_ARB_STAT_00 0x00000d00 3003#define BCE_DMA_ARB_STAT_00_MASTER (0xffffL<<0) 3004#define BCE_DMA_ARB_STAT_00_MASTER_ENC (0xffL<<16) 3005#define BCE_DMA_ARB_STAT_00_CUR_BINMSTR (0xffL<<24) 3006 3007#define BCE_DMA_ARB_STAT_01 0x00000d04 3008#define BCE_DMA_ARB_STAT_01_LPR_RPTR (0xfL<<0) 3009#define BCE_DMA_ARB_STAT_01_LPR_WPTR (0xfL<<4) 3010#define BCE_DMA_ARB_STAT_01_LPB_RPTR (0xfL<<8) 3011#define BCE_DMA_ARB_STAT_01_LPB_WPTR (0xfL<<12) 3012#define BCE_DMA_ARB_STAT_01_HPR_RPTR (0xfL<<16) 3013#define BCE_DMA_ARB_STAT_01_HPR_WPTR (0xfL<<20) 3014#define BCE_DMA_ARB_STAT_01_HPB_RPTR (0xfL<<24) 3015#define BCE_DMA_ARB_STAT_01_HPB_WPTR (0xfL<<28) 3016 3017#define BCE_DMA_FUSE_CTRL0_CMD 0x00000f00 3018#define BCE_DMA_FUSE_CTRL0_CMD_PWRUP_DONE (1L<<0) 3019#define BCE_DMA_FUSE_CTRL0_CMD_SHIFT_DONE (1L<<1) 3020#define BCE_DMA_FUSE_CTRL0_CMD_SHIFT (1L<<2) 3021#define BCE_DMA_FUSE_CTRL0_CMD_LOAD (1L<<3) 3022#define BCE_DMA_FUSE_CTRL0_CMD_SEL (0xfL<<8) 3023 3024#define BCE_DMA_FUSE_CTRL0_DATA 0x00000f04 3025#define BCE_DMA_FUSE_CTRL1_CMD 0x00000f08 3026#define BCE_DMA_FUSE_CTRL1_CMD_PWRUP_DONE (1L<<0) 3027#define BCE_DMA_FUSE_CTRL1_CMD_SHIFT_DONE (1L<<1) 3028#define BCE_DMA_FUSE_CTRL1_CMD_SHIFT (1L<<2) 3029#define BCE_DMA_FUSE_CTRL1_CMD_LOAD (1L<<3) 3030#define BCE_DMA_FUSE_CTRL1_CMD_SEL (0xfL<<8) 3031 3032#define BCE_DMA_FUSE_CTRL1_DATA 0x00000f0c 3033#define BCE_DMA_FUSE_CTRL2_CMD 0x00000f10 3034#define BCE_DMA_FUSE_CTRL2_CMD_PWRUP_DONE (1L<<0) 3035#define BCE_DMA_FUSE_CTRL2_CMD_SHIFT_DONE (1L<<1) 3036#define BCE_DMA_FUSE_CTRL2_CMD_SHIFT (1L<<2) 3037#define BCE_DMA_FUSE_CTRL2_CMD_LOAD (1L<<3) 3038#define BCE_DMA_FUSE_CTRL2_CMD_SEL (0xfL<<8) 3039 3040#define BCE_DMA_FUSE_CTRL2_DATA 0x00000f14 3041 3042 3043/* 3044 * context_reg definition 3045 * offset: 0x1000 3046 */ 3047#define BCE_CTX_COMMAND 0x00001000 3048#define BCE_CTX_COMMAND_ENABLED (1L<<0) 3049#define BCE_CTX_COMMAND_DISABLE_USAGE_CNT (1L<<1) 3050#define BCE_CTX_COMMAND_DISABLE_PLRU (1L<<2) 3051#define BCE_CTX_COMMAND_DISABLE_COMBINE_READ (1L<<3) 3052#define BCE_CTX_COMMAND_FLUSH_AHEAD (0x1fL<<8) 3053#define BCE_CTX_COMMAND_MEM_INIT (1L<<13) 3054#define BCE_CTX_COMMAND_PAGE_SIZE (0xfL<<16) 3055#define BCE_CTX_COMMAND_PAGE_SIZE_256 (0L<<16) 3056#define BCE_CTX_COMMAND_PAGE_SIZE_512 (1L<<16) 3057#define BCE_CTX_COMMAND_PAGE_SIZE_1K (2L<<16) 3058#define BCE_CTX_COMMAND_PAGE_SIZE_2K (3L<<16) 3059#define BCE_CTX_COMMAND_PAGE_SIZE_4K (4L<<16) 3060#define BCE_CTX_COMMAND_PAGE_SIZE_8K (5L<<16) 3061#define BCE_CTX_COMMAND_PAGE_SIZE_16K (6L<<16) 3062#define BCE_CTX_COMMAND_PAGE_SIZE_32K (7L<<16) 3063#define BCE_CTX_COMMAND_PAGE_SIZE_64K (8L<<16) 3064#define BCE_CTX_COMMAND_PAGE_SIZE_128K (9L<<16) 3065#define BCE_CTX_COMMAND_PAGE_SIZE_256K (10L<<16) 3066#define BCE_CTX_COMMAND_PAGE_SIZE_512K (11L<<16) 3067#define BCE_CTX_COMMAND_PAGE_SIZE_1M (12L<<16) 3068 3069#define BCE_CTX_STATUS 0x00001004 3070#define BCE_CTX_STATUS_LOCK_WAIT (1L<<0) 3071#define BCE_CTX_STATUS_READ_STAT (1L<<16) 3072#define BCE_CTX_STATUS_WRITE_STAT (1L<<17) 3073#define BCE_CTX_STATUS_ACC_STALL_STAT (1L<<18) 3074#define BCE_CTX_STATUS_LOCK_STALL_STAT (1L<<19) 3075#define BCE_CTX_STATUS_EXT_READ_STAT (1L<<20) 3076#define BCE_CTX_STATUS_EXT_WRITE_STAT (1L<<21) 3077#define BCE_CTX_STATUS_MISS_STAT (1L<<22) 3078#define BCE_CTX_STATUS_HIT_STAT (1L<<23) 3079#define BCE_CTX_STATUS_DEAD_LOCK (1L<<24) 3080#define BCE_CTX_STATUS_USAGE_CNT_ERR (1L<<25) 3081#define BCE_CTX_STATUS_INVALID_PAGE (1L<<26) 3082 3083#define BCE_CTX_VIRT_ADDR 0x00001008 3084#define BCE_CTX_VIRT_ADDR_VIRT_ADDR (0x7fffL<<6) 3085 3086#define BCE_CTX_PAGE_TBL 0x0000100c 3087#define BCE_CTX_PAGE_TBL_PAGE_TBL (0x3fffL<<6) 3088 3089#define BCE_CTX_DATA_ADR 0x00001010 3090#define BCE_CTX_DATA_ADR_DATA_ADR (0x7ffffL<<2) 3091 3092#define BCE_CTX_DATA 0x00001014 3093#define BCE_CTX_LOCK 0x00001018 3094#define BCE_CTX_LOCK_TYPE (0x7L<<0) 3095#define BCE_CTX_LOCK_TYPE_LOCK_TYPE_VOID (0x0L<<0) 3096#define BCE_CTX_LOCK_TYPE_LOCK_TYPE_PROTOCOL (0x1L<<0) 3097#define BCE_CTX_LOCK_TYPE_LOCK_TYPE_TX (0x2L<<0) 3098#define BCE_CTX_LOCK_TYPE_LOCK_TYPE_TIMER (0x4L<<0) 3099#define BCE_CTX_LOCK_TYPE_LOCK_TYPE_COMPLETE (0x7L<<0) 3100#define BCE_CTX_LOCK_TYPE_VOID_XI (0L<<0) 3101#define BCE_CTX_LOCK_TYPE_PROTOCOL_XI (1L<<0) 3102#define BCE_CTX_LOCK_TYPE_TX_XI (2L<<0) 3103#define BCE_CTX_LOCK_TYPE_TIMER_XI (4L<<0) 3104#define BCE_CTX_LOCK_TYPE_COMPLETE_XI (7L<<0) 3105#define BCE_CTX_LOCK_CID_VALUE (0x3fffL<<7) 3106#define BCE_CTX_LOCK_GRANTED (1L<<26) 3107#define BCE_CTX_LOCK_MODE (0x7L<<27) 3108#define BCE_CTX_LOCK_MODE_UNLOCK (0x0L<<27) 3109#define BCE_CTX_LOCK_MODE_IMMEDIATE (0x1L<<27) 3110#define BCE_CTX_LOCK_MODE_SURE (0x2L<<27) 3111#define BCE_CTX_LOCK_STATUS (1L<<30) 3112#define BCE_CTX_LOCK_REQ (1L<<31) 3113 3114#define BCE_CTX_CTX_CTRL 0x0000101c 3115#define BCE_CTX_CTX_CTRL_CTX_ADDR (0x7ffffL<<2) 3116#define BCE_CTX_CTX_CTRL_MOD_USAGE_CNT (0x3L<<21) 3117#define BCE_CTX_CTX_CTRL_NO_RAM_ACC (1L<<23) 3118#define BCE_CTX_CTX_CTRL_PREFETCH_SIZE (0x3L<<24) 3119#define BCE_CTX_CTX_CTRL_ATTR (1L<<26) 3120#define BCE_CTX_CTX_CTRL_WRITE_REQ (1L<<30) 3121#define BCE_CTX_CTX_CTRL_READ_REQ (1L<<31) 3122 3123#define BCE_CTX_CTX_DATA 0x00001020 3124#define BCE_CTX_ACCESS_STATUS 0x00001040 3125#define BCE_CTX_ACCESS_STATUS_MASTERENCODED (0xfL<<0) 3126#define BCE_CTX_ACCESS_STATUS_ACCESSMEMORYSM (0x3L<<10) 3127#define BCE_CTX_ACCESS_STATUS_PAGETABLEINITSM (0x3L<<12) 3128#define BCE_CTX_ACCESS_STATUS_ACCESSMEMORYINITSM (0x3L<<14) 3129#define BCE_CTX_ACCESS_STATUS_QUALIFIED_REQUEST (0x7ffL<<17) 3130#define BCE_CTX_ACCESS_STATUS_CAMMASTERENCODED_XI (0x1fL<<0) 3131#define BCE_CTX_ACCESS_STATUS_CACHEMASTERENCODED_XI (0x1fL<<5) 3132#define BCE_CTX_ACCESS_STATUS_REQUEST_XI (0x3fffffL<<10) 3133 3134#define BCE_CTX_DBG_LOCK_STATUS 0x00001044 3135#define BCE_CTX_DBG_LOCK_STATUS_SM (0x3ffL<<0) 3136#define BCE_CTX_DBG_LOCK_STATUS_MATCH (0x3ffL<<22) 3137 3138#define BCE_CTX_CACHE_CTRL_STATUS 0x00001048 3139#define BCE_CTX_CACHE_CTRL_STATUS_RFIFO_OVERFLOW (1L<<0) 3140#define BCE_CTX_CACHE_CTRL_STATUS_INVALID_READ_COMP (1L<<1) 3141#define BCE_CTX_CACHE_CTRL_STATUS_FLUSH_START (1L<<6) 3142#define BCE_CTX_CACHE_CTRL_STATUS_FREE_ENTRY_CNT (0x3fL<<7) 3143#define BCE_CTX_CACHE_CTRL_STATUS_CACHE_ENTRY_NEEDED (0x3fL<<13) 3144#define BCE_CTX_CACHE_CTRL_STATUS_RD_CHAN0_ACTIVE (1L<<19) 3145#define BCE_CTX_CACHE_CTRL_STATUS_RD_CHAN1_ACTIVE (1L<<20) 3146#define BCE_CTX_CACHE_CTRL_STATUS_RD_CHAN2_ACTIVE (1L<<21) 3147#define BCE_CTX_CACHE_CTRL_STATUS_RD_CHAN3_ACTIVE (1L<<22) 3148#define BCE_CTX_CACHE_CTRL_STATUS_RD_CHAN4_ACTIVE (1L<<23) 3149#define BCE_CTX_CACHE_CTRL_STATUS_RD_CHAN5_ACTIVE (1L<<24) 3150#define BCE_CTX_CACHE_CTRL_STATUS_RD_CHAN6_ACTIVE (1L<<25) 3151#define BCE_CTX_CACHE_CTRL_STATUS_RD_CHAN7_ACTIVE (1L<<26) 3152#define BCE_CTX_CACHE_CTRL_STATUS_RD_CHAN8_ACTIVE (1L<<27) 3153#define BCE_CTX_CACHE_CTRL_STATUS_RD_CHAN9_ACTIVE (1L<<28) 3154#define BCE_CTX_CACHE_CTRL_STATUS_RD_CHAN10_ACTIVE (1L<<29) 3155 3156#define BCE_CTX_CACHE_CTRL_SM_STATUS 0x0000104c 3157#define BCE_CTX_CACHE_CTRL_SM_STATUS_CS_DWC (0x7L<<0) 3158#define BCE_CTX_CACHE_CTRL_SM_STATUS_CS_WFIFOC (0x7L<<3) 3159#define BCE_CTX_CACHE_CTRL_SM_STATUS_CS_RTAGC (0x7L<<6) 3160#define BCE_CTX_CACHE_CTRL_SM_STATUS_CS_RFIFOC (0x7L<<9) 3161#define BCE_CTX_CACHE_CTRL_SM_STATUS_INVALID_BLK_ADDR (0x7fffL<<16) 3162 3163#define BCE_CTX_CACHE_STATUS 0x00001050 3164#define BCE_CTX_CACHE_STATUS_HELD_ENTRIES (0x3ffL<<0) 3165#define BCE_CTX_CACHE_STATUS_MAX_HELD_ENTRIES (0x3ffL<<16) 3166 3167#define BCE_CTX_DMA_STATUS 0x00001054 3168#define BCE_CTX_DMA_STATUS_RD_CHAN0_STATUS (0x3L<<0) 3169#define BCE_CTX_DMA_STATUS_RD_CHAN1_STATUS (0x3L<<2) 3170#define BCE_CTX_DMA_STATUS_RD_CHAN2_STATUS (0x3L<<4) 3171#define BCE_CTX_DMA_STATUS_RD_CHAN3_STATUS (0x3L<<6) 3172#define BCE_CTX_DMA_STATUS_RD_CHAN4_STATUS (0x3L<<8) 3173#define BCE_CTX_DMA_STATUS_RD_CHAN5_STATUS (0x3L<<10) 3174#define BCE_CTX_DMA_STATUS_RD_CHAN6_STATUS (0x3L<<12) 3175#define BCE_CTX_DMA_STATUS_RD_CHAN7_STATUS (0x3L<<14) 3176#define BCE_CTX_DMA_STATUS_RD_CHAN8_STATUS (0x3L<<16) 3177#define BCE_CTX_DMA_STATUS_RD_CHAN9_STATUS (0x3L<<18) 3178#define BCE_CTX_DMA_STATUS_RD_CHAN10_STATUS (0x3L<<20) 3179 3180#define BCE_CTX_REP_STATUS 0x00001058 3181#define BCE_CTX_REP_STATUS_ERROR_ENTRY (0x3ffL<<0) 3182#define BCE_CTX_REP_STATUS_ERROR_CLIENT_ID (0x1fL<<10) 3183#define BCE_CTX_REP_STATUS_USAGE_CNT_MAX_ERR (1L<<16) 3184#define BCE_CTX_REP_STATUS_USAGE_CNT_MIN_ERR (1L<<17) 3185#define BCE_CTX_REP_STATUS_USAGE_CNT_MISS_ERR (1L<<18) 3186 3187#define BCE_CTX_CKSUM_ERROR_STATUS 0x0000105c 3188#define BCE_CTX_CKSUM_ERROR_STATUS_CALCULATED (0xffffL<<0) 3189#define BCE_CTX_CKSUM_ERROR_STATUS_EXPECTED (0xffffL<<16) 3190 3191#define BCE_CTX_CHNL_LOCK_STATUS_0 0x00001080 3192#define BCE_CTX_CHNL_LOCK_STATUS_0_CID (0x3fffL<<0) 3193#define BCE_CTX_CHNL_LOCK_STATUS_0_TYPE (0x3L<<14) 3194#define BCE_CTX_CHNL_LOCK_STATUS_0_MODE (1L<<16) 3195#define BCE_CTX_CHNL_LOCK_STATUS_0_MODE_XI (1L<<14) 3196#define BCE_CTX_CHNL_LOCK_STATUS_0_TYPE_XI (0x7L<<15) 3197 3198#define BCE_CTX_CHNL_LOCK_STATUS_1 0x00001084 3199#define BCE_CTX_CHNL_LOCK_STATUS_2 0x00001088 3200#define BCE_CTX_CHNL_LOCK_STATUS_3 0x0000108c 3201#define BCE_CTX_CHNL_LOCK_STATUS_4 0x00001090 3202#define BCE_CTX_CHNL_LOCK_STATUS_5 0x00001094 3203#define BCE_CTX_CHNL_LOCK_STATUS_6 0x00001098 3204#define BCE_CTX_CHNL_LOCK_STATUS_7 0x0000109c 3205#define BCE_CTX_CHNL_LOCK_STATUS_8 0x000010a0 3206#define BCE_CTX_CHNL_LOCK_STATUS_9 0x000010a4 3207 3208#define BCE_CTX_CACHE_DATA 0x000010c4 3209#define BCE_CTX_HOST_PAGE_TBL_CTRL 0x000010c8 3210#define BCE_CTX_HOST_PAGE_TBL_CTRL_PAGE_TBL_ADDR (0x1ffL<<0) 3211#define BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ (1L<<30) 3212#define BCE_CTX_HOST_PAGE_TBL_CTRL_READ_REQ (1L<<31) 3213 3214#define BCE_CTX_HOST_PAGE_TBL_DATA0 0x000010cc 3215#define BCE_CTX_HOST_PAGE_TBL_DATA0_VALID (1L<<0) 3216#define BCE_CTX_HOST_PAGE_TBL_DATA0_VALUE (0xffffffL<<8) 3217 3218#define BCE_CTX_HOST_PAGE_TBL_DATA1 0x000010d0 3219#define BCE_CTX_CAM_CTRL 0x000010d4 3220#define BCE_CTX_CAM_CTRL_CAM_ADDR (0x3ffL<<0) 3221#define BCE_CTX_CAM_CTRL_RESET (1L<<27) 3222#define BCE_CTX_CAM_CTRL_INVALIDATE (1L<<28) 3223#define BCE_CTX_CAM_CTRL_SEARCH (1L<<29) 3224#define BCE_CTX_CAM_CTRL_WRITE_REQ (1L<<30) 3225#define BCE_CTX_CAM_CTRL_READ_REQ (1L<<31) 3226 3227 3228/* 3229 * emac_reg definition 3230 * offset: 0x1400 3231 */ 3232#define BCE_EMAC_MODE 0x00001400 3233#define BCE_EMAC_MODE_RESET (1L<<0) 3234#define BCE_EMAC_MODE_HALF_DUPLEX (1L<<1) 3235#define BCE_EMAC_MODE_PORT (0x3L<<2) 3236#define BCE_EMAC_MODE_PORT_NONE (0L<<2) 3237#define BCE_EMAC_MODE_PORT_MII (1L<<2) 3238#define BCE_EMAC_MODE_PORT_GMII (2L<<2) 3239#define BCE_EMAC_MODE_PORT_MII_10 (3L<<2) 3240#define BCE_EMAC_MODE_MAC_LOOP (1L<<4) 3241#define BCE_EMAC_MODE_25G (1L<<5) 3242#define BCE_EMAC_MODE_TAGGED_MAC_CTL (1L<<7) 3243#define BCE_EMAC_MODE_TX_BURST (1L<<8) 3244#define BCE_EMAC_MODE_MAX_DEFER_DROP_ENA (1L<<9) 3245#define BCE_EMAC_MODE_EXT_LINK_POL (1L<<10) 3246#define BCE_EMAC_MODE_FORCE_LINK (1L<<11) 3247#define BCE_EMAC_MODE_MPKT (1L<<18) 3248#define BCE_EMAC_MODE_MPKT_RCVD (1L<<19) 3249#define BCE_EMAC_MODE_ACPI_RCVD (1L<<20) 3250 3251#define BCE_EMAC_STATUS 0x00001404 3252#define BCE_EMAC_STATUS_LINK (1L<<11) 3253#define BCE_EMAC_STATUS_LINK_CHANGE (1L<<12) 3254#define BCE_EMAC_STATUS_MI_COMPLETE (1L<<22) 3255#define BCE_EMAC_STATUS_MI_INT (1L<<23) 3256#define BCE_EMAC_STATUS_AP_ERROR (1L<<24) 3257#define BCE_EMAC_STATUS_PARITY_ERROR_STATE (1L<<31) 3258 3259#define BCE_EMAC_ATTENTION_ENA 0x00001408 3260#define BCE_EMAC_ATTENTION_ENA_LINK (1L<<11) 3261#define BCE_EMAC_ATTENTION_ENA_MI_COMPLETE (1L<<22) 3262#define BCE_EMAC_ATTENTION_ENA_MI_INT (1L<<23) 3263#define BCE_EMAC_ATTENTION_ENA_AP_ERROR (1L<<24) 3264 3265#define BCE_EMAC_LED 0x0000140c 3266#define BCE_EMAC_LED_OVERRIDE (1L<<0) 3267#define BCE_EMAC_LED_1000MB_OVERRIDE (1L<<1) 3268#define BCE_EMAC_LED_100MB_OVERRIDE (1L<<2) 3269#define BCE_EMAC_LED_10MB_OVERRIDE (1L<<3) 3270#define BCE_EMAC_LED_TRAFFIC_OVERRIDE (1L<<4) 3271#define BCE_EMAC_LED_BLNK_TRAFFIC (1L<<5) 3272#define BCE_EMAC_LED_TRAFFIC (1L<<6) 3273#define BCE_EMAC_LED_1000MB (1L<<7) 3274#define BCE_EMAC_LED_100MB (1L<<8) 3275#define BCE_EMAC_LED_10MB (1L<<9) 3276#define BCE_EMAC_LED_TRAFFIC_STAT (1L<<10) 3277#define BCE_EMAC_LED_BLNK_RATE (0xfffL<<19) 3278#define BCE_EMAC_LED_BLNK_RATE_ENA (1L<<31) 3279 3280#define BCE_EMAC_MAC_MATCH0 0x00001410 3281#define BCE_EMAC_MAC_MATCH1 0x00001414 3282#define BCE_EMAC_MAC_MATCH2 0x00001418 3283#define BCE_EMAC_MAC_MATCH3 0x0000141c 3284#define BCE_EMAC_MAC_MATCH4 0x00001420 3285#define BCE_EMAC_MAC_MATCH5 0x00001424 3286#define BCE_EMAC_MAC_MATCH6 0x00001428 3287#define BCE_EMAC_MAC_MATCH7 0x0000142c 3288#define BCE_EMAC_MAC_MATCH8 0x00001430 3289#define BCE_EMAC_MAC_MATCH9 0x00001434 3290#define BCE_EMAC_MAC_MATCH10 0x00001438 3291#define BCE_EMAC_MAC_MATCH11 0x0000143c 3292#define BCE_EMAC_MAC_MATCH12 0x00001440 3293#define BCE_EMAC_MAC_MATCH13 0x00001444 3294#define BCE_EMAC_MAC_MATCH14 0x00001448 3295#define BCE_EMAC_MAC_MATCH15 0x0000144c 3296#define BCE_EMAC_MAC_MATCH16 0x00001450 3297#define BCE_EMAC_MAC_MATCH17 0x00001454 3298#define BCE_EMAC_MAC_MATCH18 0x00001458 3299#define BCE_EMAC_MAC_MATCH19 0x0000145c 3300#define BCE_EMAC_MAC_MATCH20 0x00001460 3301#define BCE_EMAC_MAC_MATCH21 0x00001464 3302#define BCE_EMAC_MAC_MATCH22 0x00001468 3303#define BCE_EMAC_MAC_MATCH23 0x0000146c 3304#define BCE_EMAC_MAC_MATCH24 0x00001470 3305#define BCE_EMAC_MAC_MATCH25 0x00001474 3306#define BCE_EMAC_MAC_MATCH26 0x00001478 3307#define BCE_EMAC_MAC_MATCH27 0x0000147c 3308#define BCE_EMAC_MAC_MATCH28 0x00001480 3309#define BCE_EMAC_MAC_MATCH29 0x00001484 3310#define BCE_EMAC_MAC_MATCH30 0x00001488 3311#define BCE_EMAC_MAC_MATCH31 0x0000148c 3312#define BCE_EMAC_BACKOFF_SEED 0x00001498 3313#define BCE_EMAC_BACKOFF_SEED_EMAC_BACKOFF_SEED (0x3ffL<<0) 3314 3315#define BCE_EMAC_RX_MTU_SIZE 0x0000149c 3316#define BCE_EMAC_RX_MTU_SIZE_MTU_SIZE (0xffffL<<0) 3317#define BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31) 3318 3319#define BCE_EMAC_SERDES_CNTL 0x000014a4 3320#define BCE_EMAC_SERDES_CNTL_RXR (0x7L<<0) 3321#define BCE_EMAC_SERDES_CNTL_RXG (0x3L<<3) 3322#define BCE_EMAC_SERDES_CNTL_RXCKSEL (1L<<6) 3323#define BCE_EMAC_SERDES_CNTL_TXBIAS (0x7L<<7) 3324#define BCE_EMAC_SERDES_CNTL_BGMAX (1L<<10) 3325#define BCE_EMAC_SERDES_CNTL_BGMIN (1L<<11) 3326#define BCE_EMAC_SERDES_CNTL_TXMODE (1L<<12) 3327#define BCE_EMAC_SERDES_CNTL_TXEDGE (1L<<13) 3328#define BCE_EMAC_SERDES_CNTL_SERDES_MODE (1L<<14) 3329#define BCE_EMAC_SERDES_CNTL_PLLTEST (1L<<15) 3330#define BCE_EMAC_SERDES_CNTL_CDET_EN (1L<<16) 3331#define BCE_EMAC_SERDES_CNTL_TBI_LBK (1L<<17) 3332#define BCE_EMAC_SERDES_CNTL_REMOTE_LBK (1L<<18) 3333#define BCE_EMAC_SERDES_CNTL_REV_PHASE (1L<<19) 3334#define BCE_EMAC_SERDES_CNTL_REGCTL12 (0x3L<<20) 3335#define BCE_EMAC_SERDES_CNTL_REGCTL25 (0x3L<<22) 3336 3337#define BCE_EMAC_SERDES_STATUS 0x000014a8 3338#define BCE_EMAC_SERDES_STATUS_RX_STAT (0xffL<<0) 3339#define BCE_EMAC_SERDES_STATUS_COMMA_DET (1L<<8) 3340 3341#define BCE_EMAC_MDIO_COMM 0x000014ac 3342#define BCE_EMAC_MDIO_COMM_DATA (0xffffL<<0) 3343#define BCE_EMAC_MDIO_COMM_REG_ADDR (0x1fL<<16) 3344#define BCE_EMAC_MDIO_COMM_PHY_ADDR (0x1fL<<21) 3345#define BCE_EMAC_MDIO_COMM_COMMAND (0x3L<<26) 3346#define BCE_EMAC_MDIO_COMM_COMMAND_UNDEFINED_0 (0L<<26) 3347#define BCE_EMAC_MDIO_COMM_COMMAND_WRITE (1L<<26) 3348#define BCE_EMAC_MDIO_COMM_COMMAND_READ (2L<<26) 3349#define BCE_EMAC_MDIO_COMM_COMMAND_UNDEFINED_3 (3L<<26) 3350#define BCE_EMAC_MDIO_COMM_FAIL (1L<<28) 3351#define BCE_EMAC_MDIO_COMM_START_BUSY (1L<<29) 3352#define BCE_EMAC_MDIO_COMM_DISEXT (1L<<30) 3353 3354#define BCE_EMAC_MDIO_STATUS 0x000014b0 3355#define BCE_EMAC_MDIO_STATUS_LINK (1L<<0) 3356#define BCE_EMAC_MDIO_STATUS_10MB (1L<<1) 3357 3358#define BCE_EMAC_MDIO_MODE 0x000014b4 3359#define BCE_EMAC_MDIO_MODE_SHORT_PREAMBLE (1L<<1) 3360#define BCE_EMAC_MDIO_MODE_AUTO_POLL (1L<<4) 3361#define BCE_EMAC_MDIO_MODE_BIT_BANG (1L<<8) 3362#define BCE_EMAC_MDIO_MODE_MDIO (1L<<9) 3363#define BCE_EMAC_MDIO_MODE_MDIO_OE (1L<<10) 3364#define BCE_EMAC_MDIO_MODE_MDC (1L<<11) 3365#define BCE_EMAC_MDIO_MODE_MDINT (1L<<12) 3366#define BCE_EMAC_MDIO_MODE_CLOCK_CNT (0x1fL<<16) 3367 3368#define BCE_EMAC_MDIO_AUTO_STATUS 0x000014b8 3369#define BCE_EMAC_MDIO_AUTO_STATUS_AUTO_ERR (1L<<0) 3370 3371#define BCE_EMAC_TX_MODE 0x000014bc 3372#define BCE_EMAC_TX_MODE_RESET (1L<<0) 3373#define BCE_EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3) 3374#define BCE_EMAC_TX_MODE_FLOW_EN (1L<<4) 3375#define BCE_EMAC_TX_MODE_BIG_BACKOFF (1L<<5) 3376#define BCE_EMAC_TX_MODE_LONG_PAUSE (1L<<6) 3377#define BCE_EMAC_TX_MODE_LINK_AWARE (1L<<7) 3378 3379#define BCE_EMAC_TX_STATUS 0x000014c0 3380#define BCE_EMAC_TX_STATUS_XOFFED (1L<<0) 3381#define BCE_EMAC_TX_STATUS_XOFF_SENT (1L<<1) 3382#define BCE_EMAC_TX_STATUS_XON_SENT (1L<<2) 3383#define BCE_EMAC_TX_STATUS_LINK_UP (1L<<3) 3384#define BCE_EMAC_TX_STATUS_UNDERRUN (1L<<4) 3385 3386#define BCE_EMAC_TX_LENGTHS 0x000014c4 3387#define BCE_EMAC_TX_LENGTHS_SLOT (0xffL<<0) 3388#define BCE_EMAC_TX_LENGTHS_IPG (0xfL<<8) 3389#define BCE_EMAC_TX_LENGTHS_IPG_CRS (0x3L<<12) 3390 3391#define BCE_EMAC_RX_MODE 0x000014c8 3392#define BCE_EMAC_RX_MODE_RESET (1L<<0) 3393#define BCE_EMAC_RX_MODE_FLOW_EN (1L<<2) 3394#define BCE_EMAC_RX_MODE_KEEP_MAC_CONTROL (1L<<3) 3395#define BCE_EMAC_RX_MODE_KEEP_PAUSE (1L<<4) 3396#define BCE_EMAC_RX_MODE_ACCEPT_OVERSIZE (1L<<5) 3397#define BCE_EMAC_RX_MODE_ACCEPT_RUNTS (1L<<6) 3398#define BCE_EMAC_RX_MODE_LLC_CHK (1L<<7) 3399#define BCE_EMAC_RX_MODE_PROMISCUOUS (1L<<8) 3400#define BCE_EMAC_RX_MODE_NO_CRC_CHK (1L<<9) 3401#define BCE_EMAC_RX_MODE_KEEP_VLAN_TAG (1L<<10) 3402#define BCE_EMAC_RX_MODE_FILT_BROADCAST (1L<<11) 3403#define BCE_EMAC_RX_MODE_SORT_MODE (1L<<12) 3404 3405#define BCE_EMAC_RX_STATUS 0x000014cc 3406#define BCE_EMAC_RX_STATUS_FFED (1L<<0) 3407#define BCE_EMAC_RX_STATUS_FF_RECEIVED (1L<<1) 3408#define BCE_EMAC_RX_STATUS_N_RECEIVED (1L<<2) 3409 3410#define BCE_EMAC_MULTICAST_HASH0 0x000014d0 3411#define BCE_EMAC_MULTICAST_HASH1 0x000014d4 3412#define BCE_EMAC_MULTICAST_HASH2 0x000014d8 3413#define BCE_EMAC_MULTICAST_HASH3 0x000014dc 3414#define BCE_EMAC_MULTICAST_HASH4 0x000014e0 3415#define BCE_EMAC_MULTICAST_HASH5 0x000014e4 3416#define BCE_EMAC_MULTICAST_HASH6 0x000014e8 3417#define BCE_EMAC_MULTICAST_HASH7 0x000014ec 3418#define BCE_EMAC_RX_STAT_IFHCINOCTETS 0x00001500 3419#define BCE_EMAC_RX_STAT_IFHCINBADOCTETS 0x00001504 3420#define BCE_EMAC_RX_STAT_ETHERSTATSFRAGMENTS 0x00001508 3421#define BCE_EMAC_RX_STAT_IFHCINUCASTPKTS 0x0000150c 3422#define BCE_EMAC_RX_STAT_IFHCINMULTICASTPKTS 0x00001510 3423#define BCE_EMAC_RX_STAT_IFHCINBROADCASTPKTS 0x00001514 3424#define BCE_EMAC_RX_STAT_DOT3STATSFCSERRORS 0x00001518 3425#define BCE_EMAC_RX_STAT_DOT3STATSALIGNMENTERRORS 0x0000151c 3426#define BCE_EMAC_RX_STAT_DOT3STATSCARRIERSENSEERRORS 0x00001520 3427#define BCE_EMAC_RX_STAT_XONPAUSEFRAMESRECEIVED 0x00001524 3428#define BCE_EMAC_RX_STAT_XOFFPAUSEFRAMESRECEIVED 0x00001528 3429#define BCE_EMAC_RX_STAT_MACCONTROLFRAMESRECEIVED 0x0000152c 3430#define BCE_EMAC_RX_STAT_XOFFSTATEENTERED 0x00001530 3431#define BCE_EMAC_RX_STAT_DOT3STATSFRAMESTOOLONG 0x00001534 3432#define BCE_EMAC_RX_STAT_ETHERSTATSJABBERS 0x00001538 3433#define BCE_EMAC_RX_STAT_ETHERSTATSUNDERSIZEPKTS 0x0000153c 3434#define BCE_EMAC_RX_STAT_ETHERSTATSPKTS64OCTETS 0x00001540 3435#define BCE_EMAC_RX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS 0x00001544 3436#define BCE_EMAC_RX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS 0x00001548 3437#define BCE_EMAC_RX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS 0x0000154c 3438#define BCE_EMAC_RX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS 0x00001550 3439#define BCE_EMAC_RX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS 0x00001554 3440#define BCE_EMAC_RX_STAT_ETHERSTATSPKTS1523OCTETSTO9022OCTETS 0x00001558 3441#define BCE_EMAC_RXMAC_DEBUG0 0x0000155c 3442#define BCE_EMAC_RXMAC_DEBUG1 0x00001560 3443#define BCE_EMAC_RXMAC_DEBUG1_LENGTH_NE_BYTE_COUNT (1L<<0) 3444#define BCE_EMAC_RXMAC_DEBUG1_LENGTH_OUT_RANGE (1L<<1) 3445#define BCE_EMAC_RXMAC_DEBUG1_BAD_CRC (1L<<2) 3446#define BCE_EMAC_RXMAC_DEBUG1_RX_ERROR (1L<<3) 3447#define BCE_EMAC_RXMAC_DEBUG1_ALIGN_ERROR (1L<<4) 3448#define BCE_EMAC_RXMAC_DEBUG1_LAST_DATA (1L<<5) 3449#define BCE_EMAC_RXMAC_DEBUG1_ODD_BYTE_START (1L<<6) 3450#define BCE_EMAC_RXMAC_DEBUG1_BYTE_COUNT (0xffffL<<7) 3451#define BCE_EMAC_RXMAC_DEBUG1_SLOT_TIME (0xffL<<23) 3452 3453#define BCE_EMAC_RXMAC_DEBUG2 0x00001564 3454#define BCE_EMAC_RXMAC_DEBUG2_SM_STATE (0x7L<<0) 3455#define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_IDLE (0x0L<<0) 3456#define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_SFD (0x1L<<0) 3457#define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_DATA (0x2L<<0) 3458#define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_SKEEP (0x3L<<0) 3459#define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_EXT (0x4L<<0) 3460#define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_DROP (0x5L<<0) 3461#define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_SDROP (0x6L<<0) 3462#define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_FC (0x7L<<0) 3463#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE (0xfL<<3) 3464#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_IDLE (0x0L<<3) 3465#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA0 (0x1L<<3) 3466#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA1 (0x2L<<3) 3467#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA2 (0x3L<<3) 3468#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA3 (0x4L<<3) 3469#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_ABORT (0x5L<<3) 3470#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_WAIT (0x6L<<3) 3471#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_STATUS (0x7L<<3) 3472#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_LAST (0x8L<<3) 3473#define BCE_EMAC_RXMAC_DEBUG2_BYTE_IN (0xffL<<7) 3474#define BCE_EMAC_RXMAC_DEBUG2_FALSEC (1L<<15) 3475#define BCE_EMAC_RXMAC_DEBUG2_TAGGED (1L<<16) 3476#define BCE_EMAC_RXMAC_DEBUG2_PAUSE_STATE (1L<<18) 3477#define BCE_EMAC_RXMAC_DEBUG2_PAUSE_STATE_IDLE (0L<<18) 3478#define BCE_EMAC_RXMAC_DEBUG2_PAUSE_STATE_PAUSED (1L<<18) 3479#define BCE_EMAC_RXMAC_DEBUG2_SE_COUNTER (0xfL<<19) 3480#define BCE_EMAC_RXMAC_DEBUG2_QUANTA (0x1fL<<23) 3481 3482#define BCE_EMAC_RXMAC_DEBUG3 0x00001568 3483#define BCE_EMAC_RXMAC_DEBUG3_PAUSE_CTR (0xffffL<<0) 3484#define BCE_EMAC_RXMAC_DEBUG3_TMP_PAUSE_CTR (0xffffL<<16) 3485 3486#define BCE_EMAC_RXMAC_DEBUG4 0x0000156c 3487#define BCE_EMAC_RXMAC_DEBUG4_TYPE_FIELD (0xffffL<<0) 3488#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE (0x3fL<<16) 3489#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_IDLE (0x0L<<16) 3490#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC2 (0x1L<<16) 3491#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC3 (0x2L<<16) 3492#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UNI (0x3L<<16) 3493#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC2 (0x7L<<16) 3494#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC3 (0x5L<<16) 3495#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA1 (0x6L<<16) 3496#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA2 (0x7L<<16) 3497#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA3 (0x8L<<16) 3498#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MC2 (0x9L<<16) 3499#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MC3 (0xaL<<16) 3500#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT1 (0xeL<<16) 3501#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT2 (0xfL<<16) 3502#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MCHECK (0x10L<<16) 3503#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MC (0x11L<<16) 3504#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BC2 (0x12L<<16) 3505#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BC3 (0x13L<<16) 3506#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA1 (0x14L<<16) 3507#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA2 (0x15L<<16) 3508#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA3 (0x16L<<16) 3509#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BTYPE (0x17L<<16) 3510#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BC (0x18L<<16) 3511#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_PTYPE (0x19L<<16) 3512#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_CMD (0x1aL<<16) 3513#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MAC (0x1bL<<16) 3514#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_LATCH (0x1cL<<16) 3515#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_XOFF (0x1dL<<16) 3516#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_XON (0x1eL<<16) 3517#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_PAUSED (0x1fL<<16) 3518#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_NPAUSED (0x20L<<16) 3519#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_TTYPE (0x21L<<16) 3520#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_TVAL (0x22L<<16) 3521#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_USA1 (0x23L<<16) 3522#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_USA2 (0x24L<<16) 3523#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_USA3 (0x25L<<16) 3524#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UTYPE (0x26L<<16) 3525#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UTTYPE (0x27L<<16) 3526#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UTVAL (0x28L<<16) 3527#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MTYPE (0x29L<<16) 3528#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_DROP (0x2aL<<16) 3529#define BCE_EMAC_RXMAC_DEBUG4_DROP_PKT (1L<<22) 3530#define BCE_EMAC_RXMAC_DEBUG4_SLOT_FILLED (1L<<23) 3531#define BCE_EMAC_RXMAC_DEBUG4_FALSE_CARRIER (1L<<24) 3532#define BCE_EMAC_RXMAC_DEBUG4_LAST_DATA (1L<<25) 3533#define BCE_EMAC_RXMAC_DEBUG4_sfd_FOUND (1L<<26) 3534#define BCE_EMAC_RXMAC_DEBUG4_ADVANCE (1L<<27) 3535#define BCE_EMAC_RXMAC_DEBUG4_START (1L<<28) 3536 3537#define BCE_EMAC_RXMAC_DEBUG5 0x00001570 3538#define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM (0x7L<<0) 3539#define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_IDLE (0L<<0) 3540#define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_EOF (1L<<0) 3541#define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_STAT (2L<<0) 3542#define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4FCRC (3L<<0) 3543#define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4RDE (4L<<0) 3544#define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4ALL (5L<<0) 3545#define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_1WD_WAIT_STAT (6L<<0) 3546#define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1 (0x7L<<4) 3547#define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_VDW (0x0L<<4) 3548#define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_STAT (0x1L<<4) 3549#define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_AEOF (0x2L<<4) 3550#define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_NEOF (0x3L<<4) 3551#define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SOF (0x4L<<4) 3552#define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SAEOF (0x6L<<4) 3553#define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SNEOF (0x7L<<4) 3554#define BCE_EMAC_RXMAC_DEBUG5_EOF_DETECTED (1L<<7) 3555#define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF0 (0x7L<<8) 3556#define BCE_EMAC_RXMAC_DEBUG5_RPM_IDI_FIFO_FULL (1L<<11) 3557#define BCE_EMAC_RXMAC_DEBUG5_LOAD_CCODE (1L<<12) 3558#define BCE_EMAC_RXMAC_DEBUG5_LOAD_DATA (1L<<13) 3559#define BCE_EMAC_RXMAC_DEBUG5_LOAD_STAT (1L<<14) 3560#define BCE_EMAC_RXMAC_DEBUG5_CLR_STAT (1L<<15) 3561#define BCE_EMAC_RXMAC_DEBUG5_IDI_RPM_CCODE (0x3L<<16) 3562#define BCE_EMAC_RXMAC_DEBUG5_IDI_RPM_ACCEPT (1L<<19) 3563#define BCE_EMAC_RXMAC_DEBUG5_FMLEN (0xfffL<<20) 3564 3565#define BCE_EMAC_RX_STAT_AC0 0x00001580 3566#define BCE_EMAC_RX_STAT_AC1 0x00001584 3567#define BCE_EMAC_RX_STAT_AC2 0x00001588 3568#define BCE_EMAC_RX_STAT_AC3 0x0000158c 3569#define BCE_EMAC_RX_STAT_AC4 0x00001590 3570#define BCE_EMAC_RX_STAT_AC5 0x00001594 3571#define BCE_EMAC_RX_STAT_AC6 0x00001598 3572#define BCE_EMAC_RX_STAT_AC7 0x0000159c 3573#define BCE_EMAC_RX_STAT_AC8 0x000015a0 3574#define BCE_EMAC_RX_STAT_AC9 0x000015a4 3575#define BCE_EMAC_RX_STAT_AC10 0x000015a8 3576#define BCE_EMAC_RX_STAT_AC11 0x000015ac 3577#define BCE_EMAC_RX_STAT_AC12 0x000015b0 3578#define BCE_EMAC_RX_STAT_AC13 0x000015b4 3579#define BCE_EMAC_RX_STAT_AC14 0x000015b8 3580#define BCE_EMAC_RX_STAT_AC15 0x000015bc 3581#define BCE_EMAC_RX_STAT_AC16 0x000015c0 3582#define BCE_EMAC_RX_STAT_AC17 0x000015c4 3583#define BCE_EMAC_RX_STAT_AC18 0x000015c8 3584#define BCE_EMAC_RX_STAT_AC19 0x000015cc 3585#define BCE_EMAC_RX_STAT_AC20 0x000015d0 3586#define BCE_EMAC_RX_STAT_AC21 0x000015d4 3587#define BCE_EMAC_RX_STAT_AC22 0x000015d8 3588#define BCE_EMAC_RXMAC_SUC_DBG_OVERRUNVEC 0x000015dc 3589#define BCE_EMAC_TX_STAT_IFHCOUTOCTETS 0x00001600 3590#define BCE_EMAC_TX_STAT_IFHCOUTBADOCTETS 0x00001604 3591#define BCE_EMAC_TX_STAT_ETHERSTATSCOLLISIONS 0x00001608 3592#define BCE_EMAC_TX_STAT_OUTXONSENT 0x0000160c 3593#define BCE_EMAC_TX_STAT_OUTXOFFSENT 0x00001610 3594#define BCE_EMAC_TX_STAT_FLOWCONTROLDONE 0x00001614 3595#define BCE_EMAC_TX_STAT_DOT3STATSSINGLECOLLISIONFRAMES 0x00001618 3596#define BCE_EMAC_TX_STAT_DOT3STATSMULTIPLECOLLISIONFRAMES 0x0000161c 3597#define BCE_EMAC_TX_STAT_DOT3STATSDEFERREDTRANSMISSIONS 0x00001620 3598#define BCE_EMAC_TX_STAT_DOT3STATSEXCESSIVECOLLISIONS 0x00001624 3599#define BCE_EMAC_TX_STAT_DOT3STATSLATECOLLISIONS 0x00001628 3600#define BCE_EMAC_TX_STAT_IFHCOUTUCASTPKTS 0x0000162c 3601#define BCE_EMAC_TX_STAT_IFHCOUTMULTICASTPKTS 0x00001630 3602#define BCE_EMAC_TX_STAT_IFHCOUTBROADCASTPKTS 0x00001634 3603#define BCE_EMAC_TX_STAT_ETHERSTATSPKTS64OCTETS 0x00001638 3604#define BCE_EMAC_TX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS 0x0000163c 3605#define BCE_EMAC_TX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS 0x00001640 3606#define BCE_EMAC_TX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS 0x00001644 3607#define BCE_EMAC_TX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS 0x00001648 3608#define BCE_EMAC_TX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS 0x0000164c 3609#define BCE_EMAC_TX_STAT_ETHERSTATSPKTS1523OCTETSTO9022OCTETS 0x00001650 3610#define BCE_EMAC_TX_STAT_DOT3STATSINTERNALMACTRANSMITERRORS 0x00001654 3611#define BCE_EMAC_TXMAC_DEBUG0 0x00001658 3612#define BCE_EMAC_TXMAC_DEBUG1 0x0000165c 3613#define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE (0xfL<<0) 3614#define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_IDLE (0x0L<<0) 3615#define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_START0 (0x1L<<0) 3616#define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA0 (0x4L<<0) 3617#define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA1 (0x5L<<0) 3618#define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA2 (0x6L<<0) 3619#define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA3 (0x7L<<0) 3620#define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT0 (0x8L<<0) 3621#define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT1 (0x9L<<0) 3622#define BCE_EMAC_TXMAC_DEBUG1_CRS_ENABLE (1L<<4) 3623#define BCE_EMAC_TXMAC_DEBUG1_BAD_CRC (1L<<5) 3624#define BCE_EMAC_TXMAC_DEBUG1_SE_COUNTER (0xfL<<6) 3625#define BCE_EMAC_TXMAC_DEBUG1_SEND_PAUSE (1L<<10) 3626#define BCE_EMAC_TXMAC_DEBUG1_LATE_COLLISION (1L<<11) 3627#define BCE_EMAC_TXMAC_DEBUG1_MAX_DEFER (1L<<12) 3628#define BCE_EMAC_TXMAC_DEBUG1_DEFERRED (1L<<13) 3629#define BCE_EMAC_TXMAC_DEBUG1_ONE_BYTE (1L<<14) 3630#define BCE_EMAC_TXMAC_DEBUG1_IPG_TIME (0xfL<<15) 3631#define BCE_EMAC_TXMAC_DEBUG1_SLOT_TIME (0xffL<<19) 3632 3633#define BCE_EMAC_TXMAC_DEBUG2 0x00001660 3634#define BCE_EMAC_TXMAC_DEBUG2_BACK_OFF (0x3ffL<<0) 3635#define BCE_EMAC_TXMAC_DEBUG2_BYTE_COUNT (0xffffL<<10) 3636#define BCE_EMAC_TXMAC_DEBUG2_COL_COUNT (0x1fL<<26) 3637#define BCE_EMAC_TXMAC_DEBUG2_COL_BIT (1L<<31) 3638 3639#define BCE_EMAC_TXMAC_DEBUG3 0x00001664 3640#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE (0xfL<<0) 3641#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_IDLE (0x0L<<0) 3642#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_PRE1 (0x1L<<0) 3643#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_PRE2 (0x2L<<0) 3644#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_SFD (0x3L<<0) 3645#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_DATA (0x4L<<0) 3646#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_CRC1 (0x5L<<0) 3647#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_CRC2 (0x6L<<0) 3648#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_EXT (0x7L<<0) 3649#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_STATB (0x8L<<0) 3650#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_STATG (0x9L<<0) 3651#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_JAM (0xaL<<0) 3652#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_EJAM (0xbL<<0) 3653#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_BJAM (0xcL<<0) 3654#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_SWAIT (0xdL<<0) 3655#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_BACKOFF (0xeL<<0) 3656#define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE (0x7L<<4) 3657#define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_IDLE (0x0L<<4) 3658#define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_WAIT (0x1L<<4) 3659#define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_UNI (0x2L<<4) 3660#define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_MC (0x3L<<4) 3661#define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_BC2 (0x4L<<4) 3662#define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_BC3 (0x5L<<4) 3663#define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_BC (0x6L<<4) 3664#define BCE_EMAC_TXMAC_DEBUG3_CRS_DONE (1L<<7) 3665#define BCE_EMAC_TXMAC_DEBUG3_XOFF (1L<<8) 3666#define BCE_EMAC_TXMAC_DEBUG3_SE_COUNTER (0xfL<<9) 3667#define BCE_EMAC_TXMAC_DEBUG3_QUANTA_COUNTER (0x1fL<<13) 3668 3669#define BCE_EMAC_TXMAC_DEBUG4 0x00001668 3670#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_COUNTER (0xffffL<<0) 3671#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE (0xfL<<16) 3672#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_IDLE (0x0L<<16) 3673#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA1 (0x2L<<16) 3674#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA2 (0x3L<<16) 3675#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA3 (0x6L<<16) 3676#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC1 (0x7L<<16) 3677#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC2 (0x5L<<16) 3678#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC3 (0x4L<<16) 3679#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TYPE (0xcL<<16) 3680#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CMD (0xeL<<16) 3681#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TIME (0xaL<<16) 3682#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC1 (0x8L<<16) 3683#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC2 (0x9L<<16) 3684#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_WAIT (0xdL<<16) 3685#define BCE_EMAC_TXMAC_DEBUG4_STATS0_VALID (1L<<20) 3686#define BCE_EMAC_TXMAC_DEBUG4_APPEND_CRC (1L<<21) 3687#define BCE_EMAC_TXMAC_DEBUG4_SLOT_FILLED (1L<<22) 3688#define BCE_EMAC_TXMAC_DEBUG4_MAX_DEFER (1L<<23) 3689#define BCE_EMAC_TXMAC_DEBUG4_SEND_EXTEND (1L<<24) 3690#define BCE_EMAC_TXMAC_DEBUG4_SEND_PADDING (1L<<25) 3691#define BCE_EMAC_TXMAC_DEBUG4_EOF_LOC (1L<<26) 3692#define BCE_EMAC_TXMAC_DEBUG4_COLLIDING (1L<<27) 3693#define BCE_EMAC_TXMAC_DEBUG4_COL_IN (1L<<28) 3694#define BCE_EMAC_TXMAC_DEBUG4_BURSTING (1L<<29) 3695#define BCE_EMAC_TXMAC_DEBUG4_ADVANCE (1L<<30) 3696#define BCE_EMAC_TXMAC_DEBUG4_GO (1L<<31) 3697 3698#define BCE_EMAC_TX_STAT_AC0 0x00001680 3699#define BCE_EMAC_TX_STAT_AC1 0x00001684 3700#define BCE_EMAC_TX_STAT_AC2 0x00001688 3701#define BCE_EMAC_TX_STAT_AC3 0x0000168c 3702#define BCE_EMAC_TX_STAT_AC4 0x00001690 3703#define BCE_EMAC_TX_STAT_AC5 0x00001694 3704#define BCE_EMAC_TX_STAT_AC6 0x00001698 3705#define BCE_EMAC_TX_STAT_AC7 0x0000169c 3706#define BCE_EMAC_TX_STAT_AC8 0x000016a0 3707#define BCE_EMAC_TX_STAT_AC9 0x000016a4 3708#define BCE_EMAC_TX_STAT_AC10 0x000016a8 3709#define BCE_EMAC_TX_STAT_AC11 0x000016ac 3710#define BCE_EMAC_TX_STAT_AC12 0x000016b0 3711#define BCE_EMAC_TX_STAT_AC13 0x000016b4 3712#define BCE_EMAC_TX_STAT_AC14 0x000016b8 3713#define BCE_EMAC_TX_STAT_AC15 0x000016bc 3714#define BCE_EMAC_TX_STAT_AC16 0x000016c0 3715#define BCE_EMAC_TX_STAT_AC17 0x000016c4 3716#define BCE_EMAC_TX_STAT_AC18 0x000016c8 3717#define BCE_EMAC_TX_STAT_AC19 0x000016cc 3718#define BCE_EMAC_TX_STAT_AC20 0x000016d0 3719#define BCE_EMAC_TX_STAT_AC21 0x000016d4 3720#define BCE_EMAC_TXMAC_SUC_DBG_OVERRUNVEC 0x000016d8 3721 3722 3723/* 3724 * rpm_reg definition 3725 * offset: 0x1800 3726 */ 3727#define BCE_RPM_COMMAND 0x00001800 3728#define BCE_RPM_COMMAND_ENABLED (1L<<0) 3729#define BCE_RPM_COMMAND_OVERRUN_ABORT (1L<<4) 3730 3731#define BCE_RPM_STATUS 0x00001804 3732#define BCE_RPM_STATUS_MBUF_WAIT (1L<<0) 3733#define BCE_RPM_STATUS_FREE_WAIT (1L<<1) 3734 3735#define BCE_RPM_CONFIG 0x00001808 3736#define BCE_RPM_CONFIG_NO_PSD_HDR_CKSUM (1L<<0) 3737#define BCE_RPM_CONFIG_ACPI_ENA (1L<<1) 3738#define BCE_RPM_CONFIG_ACPI_KEEP (1L<<2) 3739#define BCE_RPM_CONFIG_MP_KEEP (1L<<3) 3740#define BCE_RPM_CONFIG_SORT_VECT_VAL (0xfL<<4) 3741#define BCE_RPM_CONFIG_IGNORE_VLAN (1L<<31) 3742 3743#define BCE_RPM_MGMT_PKT_CTRL 0x0000180c 3744#define BCE_RPM_MGMT_PKT_CTRL_MGMT_DISCARD_EN (1L<<30) 3745#define BCE_RPM_MGMT_PKT_CTRL_MGMT_EN (1L<<31) 3746 3747#define BCE_RPM_VLAN_MATCH0 0x00001810 3748#define BCE_RPM_VLAN_MATCH0_RPM_VLAN_MTCH0_VALUE (0xfffL<<0) 3749 3750#define BCE_RPM_VLAN_MATCH1 0x00001814 3751#define BCE_RPM_VLAN_MATCH1_RPM_VLAN_MTCH1_VALUE (0xfffL<<0) 3752 3753#define BCE_RPM_VLAN_MATCH2 0x00001818 3754#define BCE_RPM_VLAN_MATCH2_RPM_VLAN_MTCH2_VALUE (0xfffL<<0) 3755 3756#define BCE_RPM_VLAN_MATCH3 0x0000181c 3757#define BCE_RPM_VLAN_MATCH3_RPM_VLAN_MTCH3_VALUE (0xfffL<<0) 3758 3759#define BCE_RPM_SORT_USER0 0x00001820 3760#define BCE_RPM_SORT_USER0_PM_EN (0xffffL<<0) 3761#define BCE_RPM_SORT_USER0_BC_EN (1L<<16) 3762#define BCE_RPM_SORT_USER0_MC_EN (1L<<17) 3763#define BCE_RPM_SORT_USER0_MC_HSH_EN (1L<<18) 3764#define BCE_RPM_SORT_USER0_PROM_EN (1L<<19) 3765#define BCE_RPM_SORT_USER0_VLAN_EN (0xfL<<20) 3766#define BCE_RPM_SORT_USER0_PROM_VLAN (1L<<24) 3767#define BCE_RPM_SORT_USER0_ENA (1L<<31) 3768 3769#define BCE_RPM_SORT_USER1 0x00001824 3770#define BCE_RPM_SORT_USER1_PM_EN (0xffffL<<0) 3771#define BCE_RPM_SORT_USER1_BC_EN (1L<<16) 3772#define BCE_RPM_SORT_USER1_MC_EN (1L<<17) 3773#define BCE_RPM_SORT_USER1_MC_HSH_EN (1L<<18) 3774#define BCE_RPM_SORT_USER1_PROM_EN (1L<<19) 3775#define BCE_RPM_SORT_USER1_VLAN_EN (0xfL<<20) 3776#define BCE_RPM_SORT_USER1_PROM_VLAN (1L<<24) 3777#define BCE_RPM_SORT_USER1_ENA (1L<<31) 3778 3779#define BCE_RPM_SORT_USER2 0x00001828 3780#define BCE_RPM_SORT_USER2_PM_EN (0xffffL<<0) 3781#define BCE_RPM_SORT_USER2_BC_EN (1L<<16) 3782#define BCE_RPM_SORT_USER2_MC_EN (1L<<17) 3783#define BCE_RPM_SORT_USER2_MC_HSH_EN (1L<<18) 3784#define BCE_RPM_SORT_USER2_PROM_EN (1L<<19) 3785#define BCE_RPM_SORT_USER2_VLAN_EN (0xfL<<20) 3786#define BCE_RPM_SORT_USER2_PROM_VLAN (1L<<24) 3787#define BCE_RPM_SORT_USER2_ENA (1L<<31) 3788 3789#define BCE_RPM_SORT_USER3 0x0000182c 3790#define BCE_RPM_SORT_USER3_PM_EN (0xffffL<<0) 3791#define BCE_RPM_SORT_USER3_BC_EN (1L<<16) 3792#define BCE_RPM_SORT_USER3_MC_EN (1L<<17) 3793#define BCE_RPM_SORT_USER3_MC_HSH_EN (1L<<18) 3794#define BCE_RPM_SORT_USER3_PROM_EN (1L<<19) 3795#define BCE_RPM_SORT_USER3_VLAN_EN (0xfL<<20) 3796#define BCE_RPM_SORT_USER3_PROM_VLAN (1L<<24) 3797#define BCE_RPM_SORT_USER3_ENA (1L<<31) 3798 3799#define BCE_RPM_STAT_L2_FILTER_DISCARDS 0x00001840 3800#define BCE_RPM_STAT_RULE_CHECKER_DISCARDS 0x00001844 3801#define BCE_RPM_STAT_IFINFTQDISCARDS 0x00001848 3802#define BCE_RPM_STAT_IFINMBUFDISCARD 0x0000184c 3803#define BCE_RPM_STAT_RULE_CHECKER_P4_HIT 0x00001850 3804#define BCE_RPM_STAT_AC0 0x00001880 3805#define BCE_RPM_STAT_AC1 0x00001884 3806#define BCE_RPM_STAT_AC2 0x00001888 3807#define BCE_RPM_STAT_AC3 0x0000188c 3808#define BCE_RPM_STAT_AC4 0x00001890 3809#define BCE_RPM_RC_CNTL_0 0x00001900 3810#define BCE_RPM_RC_CNTL_0_OFFSET (0xffL<<0) 3811#define BCE_RPM_RC_CNTL_0_CLASS (0x7L<<8) 3812#define BCE_RPM_RC_CNTL_0_PRIORITY (1L<<11) 3813#define BCE_RPM_RC_CNTL_0_P4 (1L<<12) 3814#define BCE_RPM_RC_CNTL_0_HDR_TYPE (0x7L<<13) 3815#define BCE_RPM_RC_CNTL_0_HDR_TYPE_START (0L<<13) 3816#define BCE_RPM_RC_CNTL_0_HDR_TYPE_IP (1L<<13) 3817#define BCE_RPM_RC_CNTL_0_HDR_TYPE_TCP (2L<<13) 3818#define BCE_RPM_RC_CNTL_0_HDR_TYPE_UDP (3L<<13) 3819#define BCE_RPM_RC_CNTL_0_HDR_TYPE_DATA (4L<<13) 3820#define BCE_RPM_RC_CNTL_0_COMP (0x3L<<16) 3821#define BCE_RPM_RC_CNTL_0_COMP_EQUAL (0L<<16) 3822#define BCE_RPM_RC_CNTL_0_COMP_NEQUAL (1L<<16) 3823#define BCE_RPM_RC_CNTL_0_COMP_GREATER (2L<<16) 3824#define BCE_RPM_RC_CNTL_0_COMP_LESS (3L<<16) 3825#define BCE_RPM_RC_CNTL_0_SBIT (1L<<19) 3826#define BCE_RPM_RC_CNTL_0_CMDSEL (0xfL<<20) 3827#define BCE_RPM_RC_CNTL_0_MAP (1L<<24) 3828#define BCE_RPM_RC_CNTL_0_DISCARD (1L<<25) 3829#define BCE_RPM_RC_CNTL_0_MASK (1L<<26) 3830#define BCE_RPM_RC_CNTL_0_P1 (1L<<27) 3831#define BCE_RPM_RC_CNTL_0_P2 (1L<<28) 3832#define BCE_RPM_RC_CNTL_0_P3 (1L<<29) 3833#define BCE_RPM_RC_CNTL_0_NBIT (1L<<30) 3834 3835#define BCE_RPM_RC_VALUE_MASK_0 0x00001904 3836#define BCE_RPM_RC_VALUE_MASK_0_VALUE (0xffffL<<0) 3837#define BCE_RPM_RC_VALUE_MASK_0_MASK (0xffffL<<16) 3838 3839#define BCE_RPM_RC_CNTL_1 0x00001908 3840#define BCE_RPM_RC_CNTL_1_A (0x3ffffL<<0) 3841#define BCE_RPM_RC_CNTL_1_B (0xfffL<<19) 3842 3843#define BCE_RPM_RC_VALUE_MASK_1 0x0000190c 3844#define BCE_RPM_RC_CNTL_2 0x00001910 3845#define BCE_RPM_RC_CNTL_2_A (0x3ffffL<<0) 3846#define BCE_RPM_RC_CNTL_2_B (0xfffL<<19) 3847 3848#define BCE_RPM_RC_VALUE_MASK_2 0x00001914 3849#define BCE_RPM_RC_CNTL_3 0x00001918 3850#define BCE_RPM_RC_CNTL_3_A (0x3ffffL<<0) 3851#define BCE_RPM_RC_CNTL_3_B (0xfffL<<19) 3852 3853#define BCE_RPM_RC_VALUE_MASK_3 0x0000191c 3854#define BCE_RPM_RC_CNTL_4 0x00001920 3855#define BCE_RPM_RC_CNTL_4_A (0x3ffffL<<0) 3856#define BCE_RPM_RC_CNTL_4_B (0xfffL<<19) 3857 3858#define BCE_RPM_RC_VALUE_MASK_4 0x00001924 3859#define BCE_RPM_RC_CNTL_5 0x00001928 3860#define BCE_RPM_RC_CNTL_5_A (0x3ffffL<<0) 3861#define BCE_RPM_RC_CNTL_5_B (0xfffL<<19) 3862 3863#define BCE_RPM_RC_VALUE_MASK_5 0x0000192c 3864#define BCE_RPM_RC_CNTL_6 0x00001930 3865#define BCE_RPM_RC_CNTL_6_A (0x3ffffL<<0) 3866#define BCE_RPM_RC_CNTL_6_B (0xfffL<<19) 3867 3868#define BCE_RPM_RC_VALUE_MASK_6 0x00001934 3869#define BCE_RPM_RC_CNTL_7 0x00001938 3870#define BCE_RPM_RC_CNTL_7_A (0x3ffffL<<0) 3871#define BCE_RPM_RC_CNTL_7_B (0xfffL<<19) 3872 3873#define BCE_RPM_RC_VALUE_MASK_7 0x0000193c 3874#define BCE_RPM_RC_CNTL_8 0x00001940 3875#define BCE_RPM_RC_CNTL_8_A (0x3ffffL<<0) 3876#define BCE_RPM_RC_CNTL_8_B (0xfffL<<19) 3877 3878#define BCE_RPM_RC_VALUE_MASK_8 0x00001944 3879#define BCE_RPM_RC_CNTL_9 0x00001948 3880#define BCE_RPM_RC_CNTL_9_A (0x3ffffL<<0) 3881#define BCE_RPM_RC_CNTL_9_B (0xfffL<<19) 3882 3883#define BCE_RPM_RC_VALUE_MASK_9 0x0000194c 3884#define BCE_RPM_RC_CNTL_10 0x00001950 3885#define BCE_RPM_RC_CNTL_10_A (0x3ffffL<<0) 3886#define BCE_RPM_RC_CNTL_10_B (0xfffL<<19) 3887 3888#define BCE_RPM_RC_VALUE_MASK_10 0x00001954 3889#define BCE_RPM_RC_CNTL_11 0x00001958 3890#define BCE_RPM_RC_CNTL_11_A (0x3ffffL<<0) 3891#define BCE_RPM_RC_CNTL_11_B (0xfffL<<19) 3892 3893#define BCE_RPM_RC_VALUE_MASK_11 0x0000195c 3894#define BCE_RPM_RC_CNTL_12 0x00001960 3895#define BCE_RPM_RC_CNTL_12_A (0x3ffffL<<0) 3896#define BCE_RPM_RC_CNTL_12_B (0xfffL<<19) 3897 3898#define BCE_RPM_RC_VALUE_MASK_12 0x00001964 3899#define BCE_RPM_RC_CNTL_13 0x00001968 3900#define BCE_RPM_RC_CNTL_13_A (0x3ffffL<<0) 3901#define BCE_RPM_RC_CNTL_13_B (0xfffL<<19) 3902 3903#define BCE_RPM_RC_VALUE_MASK_13 0x0000196c 3904#define BCE_RPM_RC_CNTL_14 0x00001970 3905#define BCE_RPM_RC_CNTL_14_A (0x3ffffL<<0) 3906#define BCE_RPM_RC_CNTL_14_B (0xfffL<<19) 3907 3908#define BCE_RPM_RC_VALUE_MASK_14 0x00001974 3909#define BCE_RPM_RC_CNTL_15 0x00001978 3910#define BCE_RPM_RC_CNTL_15_A (0x3ffffL<<0) 3911#define BCE_RPM_RC_CNTL_15_B (0xfffL<<19) 3912 3913#define BCE_RPM_RC_VALUE_MASK_15 0x0000197c 3914#define BCE_RPM_RC_CONFIG 0x00001980 3915#define BCE_RPM_RC_CONFIG_RULE_ENABLE (0xffffL<<0) 3916#define BCE_RPM_RC_CONFIG_DEF_CLASS (0x7L<<24) 3917 3918#define BCE_RPM_DEBUG0 0x00001984 3919#define BCE_RPM_DEBUG0_FM_BCNT (0xffffL<<0) 3920#define BCE_RPM_DEBUG0_T_DATA_OFST_VLD (1L<<16) 3921#define BCE_RPM_DEBUG0_T_UDP_OFST_VLD (1L<<17) 3922#define BCE_RPM_DEBUG0_T_TCP_OFST_VLD (1L<<18) 3923#define BCE_RPM_DEBUG0_T_IP_OFST_VLD (1L<<19) 3924#define BCE_RPM_DEBUG0_IP_MORE_FRGMT (1L<<20) 3925#define BCE_RPM_DEBUG0_T_IP_NO_TCP_UDP_HDR (1L<<21) 3926#define BCE_RPM_DEBUG0_LLC_SNAP (1L<<22) 3927#define BCE_RPM_DEBUG0_FM_STARTED (1L<<23) 3928#define BCE_RPM_DEBUG0_DONE (1L<<24) 3929#define BCE_RPM_DEBUG0_WAIT_4_DONE (1L<<25) 3930#define BCE_RPM_DEBUG0_USE_TPBUF_CKSUM (1L<<26) 3931#define BCE_RPM_DEBUG0_RX_NO_PSD_HDR_CKSUM (1L<<27) 3932#define BCE_RPM_DEBUG0_IGNORE_VLAN (1L<<28) 3933#define BCE_RPM_DEBUG0_RP_ENA_ACTIVE (1L<<31) 3934 3935#define BCE_RPM_DEBUG1 0x00001988 3936#define BCE_RPM_DEBUG1_FSM_CUR_ST (0xffffL<<0) 3937#define BCE_RPM_DEBUG1_FSM_CUR_ST_IDLE (0L<<0) 3938#define BCE_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_ALL (1L<<0) 3939#define BCE_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IPLLC (2L<<0) 3940#define BCE_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_IP (4L<<0) 3941#define BCE_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IP (8L<<0) 3942#define BCE_RPM_DEBUG1_FSM_CUR_ST_IP_START (16L<<0) 3943#define BCE_RPM_DEBUG1_FSM_CUR_ST_IP (32L<<0) 3944#define BCE_RPM_DEBUG1_FSM_CUR_ST_TCP (64L<<0) 3945#define BCE_RPM_DEBUG1_FSM_CUR_ST_UDP (128L<<0) 3946#define BCE_RPM_DEBUG1_FSM_CUR_ST_AH (256L<<0) 3947#define BCE_RPM_DEBUG1_FSM_CUR_ST_ESP (512L<<0) 3948#define BCE_RPM_DEBUG1_FSM_CUR_ST_ESP_PAYLOAD (1024L<<0) 3949#define BCE_RPM_DEBUG1_FSM_CUR_ST_DATA (2048L<<0) 3950#define BCE_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRY (0x2000L<<0) 3951#define BCE_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRYOUT (0x4000L<<0) 3952#define BCE_RPM_DEBUG1_FSM_CUR_ST_LATCH_RESULT (0x8000L<<0) 3953#define BCE_RPM_DEBUG1_HDR_BCNT (0x7ffL<<16) 3954#define BCE_RPM_DEBUG1_UNKNOWN_ETYPE_D (1L<<28) 3955#define BCE_RPM_DEBUG1_VLAN_REMOVED_D2 (1L<<29) 3956#define BCE_RPM_DEBUG1_VLAN_REMOVED_D1 (1L<<30) 3957#define BCE_RPM_DEBUG1_EOF_0XTRA_WD (1L<<31) 3958 3959#define BCE_RPM_DEBUG2 0x0000198c 3960#define BCE_RPM_DEBUG2_CMD_HIT_VEC (0xffffL<<0) 3961#define BCE_RPM_DEBUG2_IP_BCNT (0xffL<<16) 3962#define BCE_RPM_DEBUG2_THIS_CMD_M4 (1L<<24) 3963#define BCE_RPM_DEBUG2_THIS_CMD_M3 (1L<<25) 3964#define BCE_RPM_DEBUG2_THIS_CMD_M2 (1L<<26) 3965#define BCE_RPM_DEBUG2_THIS_CMD_M1 (1L<<27) 3966#define BCE_RPM_DEBUG2_IPIPE_EMPTY (1L<<28) 3967#define BCE_RPM_DEBUG2_FM_DISCARD (1L<<29) 3968#define BCE_RPM_DEBUG2_LAST_RULE_IN_FM_D2 (1L<<30) 3969#define BCE_RPM_DEBUG2_LAST_RULE_IN_FM_D1 (1L<<31) 3970 3971#define BCE_RPM_DEBUG3 0x00001990 3972#define BCE_RPM_DEBUG3_AVAIL_MBUF_PTR (0x1ffL<<0) 3973#define BCE_RPM_DEBUG3_RDE_RLUPQ_WR_REQ_INT (1L<<9) 3974#define BCE_RPM_DEBUG3_RDE_RBUF_WR_LAST_INT (1L<<10) 3975#define BCE_RPM_DEBUG3_RDE_RBUF_WR_REQ_INT (1L<<11) 3976#define BCE_RPM_DEBUG3_RDE_RBUF_FREE_REQ (1L<<12) 3977#define BCE_RPM_DEBUG3_RDE_RBUF_ALLOC_REQ (1L<<13) 3978#define BCE_RPM_DEBUG3_DFSM_MBUF_NOTAVAIL (1L<<14) 3979#define BCE_RPM_DEBUG3_RBUF_RDE_SOF_DROP (1L<<15) 3980#define BCE_RPM_DEBUG3_DFIFO_VLD_ENTRY_CT (0xfL<<16) 3981#define BCE_RPM_DEBUG3_RDE_SRC_FIFO_ALMFULL (1L<<21) 3982#define BCE_RPM_DEBUG3_DROP_NXT_VLD (1L<<22) 3983#define BCE_RPM_DEBUG3_DROP_NXT (1L<<23) 3984#define BCE_RPM_DEBUG3_FTQ_FSM (0x3L<<24) 3985#define BCE_RPM_DEBUG3_FTQ_FSM_IDLE (0x0L<<24) 3986#define BCE_RPM_DEBUG3_FTQ_FSM_WAIT_ACK (0x1L<<24) 3987#define BCE_RPM_DEBUG3_FTQ_FSM_WAIT_FREE (0x2L<<24) 3988#define BCE_RPM_DEBUG3_MBWRITE_FSM (0x3L<<26) 3989#define BCE_RPM_DEBUG3_MBWRITE_FSM_WAIT_SOF (0x0L<<26) 3990#define BCE_RPM_DEBUG3_MBWRITE_FSM_GET_MBUF (0x1L<<26) 3991#define BCE_RPM_DEBUG3_MBWRITE_FSM_DMA_DATA (0x2L<<26) 3992#define BCE_RPM_DEBUG3_MBWRITE_FSM_WAIT_DATA (0x3L<<26) 3993#define BCE_RPM_DEBUG3_MBWRITE_FSM_WAIT_EOF (0x4L<<26) 3994#define BCE_RPM_DEBUG3_MBWRITE_FSM_WAIT_MF_ACK (0x5L<<26) 3995#define BCE_RPM_DEBUG3_MBWRITE_FSM_WAIT_DROP_NXT_VLD (0x6L<<26) 3996#define BCE_RPM_DEBUG3_MBWRITE_FSM_DONE (0x7L<<26) 3997#define BCE_RPM_DEBUG3_MBFREE_FSM (1L<<29) 3998#define BCE_RPM_DEBUG3_MBFREE_FSM_IDLE (0L<<29) 3999#define BCE_RPM_DEBUG3_MBFREE_FSM_WAIT_ACK (1L<<29) 4000#define BCE_RPM_DEBUG3_MBALLOC_FSM (1L<<30) 4001#define BCE_RPM_DEBUG3_MBALLOC_FSM_ET_MBUF (0x0L<<30) 4002#define BCE_RPM_DEBUG3_MBALLOC_FSM_IVE_MBUF (0x1L<<30) 4003#define BCE_RPM_DEBUG3_CCODE_EOF_ERROR (1L<<31) 4004 4005#define BCE_RPM_DEBUG4 0x00001994 4006#define BCE_RPM_DEBUG4_DFSM_MBUF_CLUSTER (0x1ffffffL<<0) 4007#define BCE_RPM_DEBUG4_DFIFO_CUR_CCODE (0x7L<<25) 4008#define BCE_RPM_DEBUG4_MBWRITE_FSM (0x7L<<28) 4009#define BCE_RPM_DEBUG4_DFIFO_EMPTY (1L<<31) 4010 4011#define BCE_RPM_DEBUG5 0x00001998 4012#define BCE_RPM_DEBUG5_RDROP_WPTR (0x1fL<<0) 4013#define BCE_RPM_DEBUG5_RDROP_ACPI_RPTR (0x1fL<<5) 4014#define BCE_RPM_DEBUG5_RDROP_MC_RPTR (0x1fL<<10) 4015#define BCE_RPM_DEBUG5_RDROP_RC_RPTR (0x1fL<<15) 4016#define BCE_RPM_DEBUG5_RDROP_ACPI_EMPTY (1L<<20) 4017#define BCE_RPM_DEBUG5_RDROP_MC_EMPTY (1L<<21) 4018#define BCE_RPM_DEBUG5_RDROP_AEOF_VEC_AT_RDROP_MC_RPTR (1L<<22) 4019#define BCE_RPM_DEBUG5_HOLDREG_WOL_DROP_INT (1L<<23) 4020#define BCE_RPM_DEBUG5_HOLDREG_DISCARD (1L<<24) 4021#define BCE_RPM_DEBUG5_HOLDREG_MBUF_NOTAVAIL (1L<<25) 4022#define BCE_RPM_DEBUG5_HOLDREG_MC_EMPTY (1L<<26) 4023#define BCE_RPM_DEBUG5_HOLDREG_RC_EMPTY (1L<<27) 4024#define BCE_RPM_DEBUG5_HOLDREG_FC_EMPTY (1L<<28) 4025#define BCE_RPM_DEBUG5_HOLDREG_ACPI_EMPTY (1L<<29) 4026#define BCE_RPM_DEBUG5_HOLDREG_FULL_T (1L<<30) 4027#define BCE_RPM_DEBUG5_HOLDREG_RD (1L<<31) 4028 4029#define BCE_RPM_DEBUG6 0x0000199c 4030#define BCE_RPM_DEBUG6_ACPI_VEC (0xffffL<<0) 4031#define BCE_RPM_DEBUG6_VEC (0xffffL<<16) 4032 4033#define BCE_RPM_DEBUG7 0x000019a0 4034#define BCE_RPM_DEBUG7_RPM_DBG7_LAST_CRC (0xffffffffL<<0) 4035 4036#define BCE_RPM_DEBUG8 0x000019a4 4037#define BCE_RPM_DEBUG8_PS_ACPI_FSM (0xfL<<0) 4038#define BCE_RPM_DEBUG8_PS_ACPI_FSM_IDLE (0L<<0) 4039#define BCE_RPM_DEBUG8_PS_ACPI_FSM_SOF_W1_ADDR (1L<<0) 4040#define BCE_RPM_DEBUG8_PS_ACPI_FSM_SOF_W2_ADDR (2L<<0) 4041#define BCE_RPM_DEBUG8_PS_ACPI_FSM_SOF_W3_ADDR (3L<<0) 4042#define BCE_RPM_DEBUG8_PS_ACPI_FSM_SOF_WAIT_THBUF (4L<<0) 4043#define BCE_RPM_DEBUG8_PS_ACPI_FSM_W3_DATA (5L<<0) 4044#define BCE_RPM_DEBUG8_PS_ACPI_FSM_W0_ADDR (6L<<0) 4045#define BCE_RPM_DEBUG8_PS_ACPI_FSM_W1_ADDR (7L<<0) 4046#define BCE_RPM_DEBUG8_PS_ACPI_FSM_W2_ADDR (8L<<0) 4047#define BCE_RPM_DEBUG8_PS_ACPI_FSM_W3_ADDR (9L<<0) 4048#define BCE_RPM_DEBUG8_PS_ACPI_FSM_WAIT_THBUF (10L<<0) 4049#define BCE_RPM_DEBUG8_COMPARE_AT_W0 (1L<<4) 4050#define BCE_RPM_DEBUG8_COMPARE_AT_W3_DATA (1L<<5) 4051#define BCE_RPM_DEBUG8_COMPARE_AT_SOF_WAIT (1L<<6) 4052#define BCE_RPM_DEBUG8_COMPARE_AT_SOF_W3 (1L<<7) 4053#define BCE_RPM_DEBUG8_COMPARE_AT_SOF_W2 (1L<<8) 4054#define BCE_RPM_DEBUG8_EOF_W_LTEQ6_VLDBYTES (1L<<9) 4055#define BCE_RPM_DEBUG8_EOF_W_LTEQ4_VLDBYTES (1L<<10) 4056#define BCE_RPM_DEBUG8_NXT_EOF_W_12_VLDBYTES (1L<<11) 4057#define BCE_RPM_DEBUG8_EOF_DET (1L<<12) 4058#define BCE_RPM_DEBUG8_SOF_DET (1L<<13) 4059#define BCE_RPM_DEBUG8_WAIT_4_SOF (1L<<14) 4060#define BCE_RPM_DEBUG8_ALL_DONE (1L<<15) 4061#define BCE_RPM_DEBUG8_THBUF_ADDR (0x7fL<<16) 4062#define BCE_RPM_DEBUG8_BYTE_CTR (0xffL<<24) 4063 4064#define BCE_RPM_DEBUG9 0x000019a8 4065#define BCE_RPM_DEBUG9_OUTFIFO_COUNT (0x7L<<0) 4066#define BCE_RPM_DEBUG9_RDE_ACPI_RDY (1L<<3) 4067#define BCE_RPM_DEBUG9_VLD_RD_ENTRY_CT (0x7L<<4) 4068#define BCE_RPM_DEBUG9_OUTFIFO_OVERRUN_OCCURRED (1L<<28) 4069#define BCE_RPM_DEBUG9_INFIFO_OVERRUN_OCCURRED (1L<<29) 4070#define BCE_RPM_DEBUG9_ACPI_MATCH_INT (1L<<30) 4071#define BCE_RPM_DEBUG9_ACPI_ENABLE_SYN (1L<<31) 4072 4073#define BCE_RPM_ACPI_DBG_BUF_W00 0x000019c0 4074#define BCE_RPM_ACPI_DBG_BUF_W01 0x000019c4 4075#define BCE_RPM_ACPI_DBG_BUF_W02 0x000019c8 4076#define BCE_RPM_ACPI_DBG_BUF_W03 0x000019cc 4077#define BCE_RPM_ACPI_DBG_BUF_W10 0x000019d0 4078#define BCE_RPM_ACPI_DBG_BUF_W11 0x000019d4 4079#define BCE_RPM_ACPI_DBG_BUF_W12 0x000019d8 4080#define BCE_RPM_ACPI_DBG_BUF_W13 0x000019dc 4081#define BCE_RPM_ACPI_DBG_BUF_W20 0x000019e0 4082#define BCE_RPM_ACPI_DBG_BUF_W21 0x000019e4 4083#define BCE_RPM_ACPI_DBG_BUF_W22 0x000019e8 4084#define BCE_RPM_ACPI_DBG_BUF_W23 0x000019ec 4085#define BCE_RPM_ACPI_DBG_BUF_W30 0x000019f0 4086#define BCE_RPM_ACPI_DBG_BUF_W31 0x000019f4 4087#define BCE_RPM_ACPI_DBG_BUF_W32 0x000019f8 4088#define BCE_RPM_ACPI_DBG_BUF_W33 0x000019fc 4089 4090 4091/* 4092 * rlup_reg definition 4093 * offset: 0x2000 4094 */ 4095#define BCE_RLUP_FTQ_CMD 0x000023f8 4096#define BCE_RLUP_FTQ_CTL 0x000023fc 4097#define BCE_RLUP_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 4098#define BCE_RLUP_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 4099 4100 4101/* 4102 * rv2pcsr_reg definition 4103 * offset: 0x2400 4104 */ 4105#define BCE_RV2PCSR_FTQ_CMD 0x000027f8 4106#define BCE_RV2PCSR_FTQ_CTL 0x000027fc 4107#define BCE_RV2PCSR_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 4108#define BCE_RV2PCSR_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 4109 4110 4111/* 4112 * rdma_reg definition 4113 * offset: 0x2c00 4114 */ 4115#define BCE_RDMA_FTQ_CMD 0x00002ff8 4116#define BCE_RDMA_FTQ_CTL 0x00002ffc 4117#define BCE_RDMA_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 4118#define BCE_RDMA_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 4119 4120 4121 4122/* 4123 * timer_reg definition 4124 * offset: 0x4400 4125 */ 4126 4127#define BCE_TIMER_COMMAND 0x00004400 4128#define BCE_TIMER_COMMAND_ENABLED (1L<<0) 4129 4130#define BCE_TIMER_STATUS 0x00004404 4131#define BCE_TIMER_STATUS_CMP_FTQ_WAIT (1L<<0) 4132#define BCE_TIMER_STATUS_POLL_PASS_CNT (1L<<8) 4133#define BCE_TIMER_STATUS_TMR1_CNT (1L<<9) 4134#define BCE_TIMER_STATUS_TMR2_CNT (1L<<10) 4135#define BCE_TIMER_STATUS_TMR3_CNT (1L<<11) 4136#define BCE_TIMER_STATUS_TMR4_CNT (1L<<12) 4137#define BCE_TIMER_STATUS_TMR5_CNT (1L<<13) 4138 4139#define BCE_TIMER_25MHZ_FREE_RUN 0x00004448 4140 4141 4142/* 4143 * tsch_reg definition 4144 * offset: 0x4c00 4145 */ 4146 4147#define BCE_TSCH_FTQ_CMD 0x00004ff8 4148#define BCE_TSCH_FTQ_CTL 0x00004ffc 4149#define BCE_TSCH_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 4150#define BCE_TSCH_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 4151 4152 4153 4154/* 4155 * rbuf_reg definition 4156 * offset: 0x200000 4157 */ 4158#define BCE_RBUF_COMMAND 0x00200000 4159#define BCE_RBUF_COMMAND_ENABLED (1L<<0) 4160#define BCE_RBUF_COMMAND_FREE_INIT (1L<<1) 4161#define BCE_RBUF_COMMAND_RAM_INIT (1L<<2) 4162#define BCE_RBUF_COMMAND_OVER_FREE (1L<<4) 4163#define BCE_RBUF_COMMAND_ALLOC_REQ (1L<<5) 4164 4165#define BCE_RBUF_STATUS1 0x00200004 4166#define BCE_RBUF_STATUS1_FREE_COUNT (0x3ffL<<0) 4167 4168#define BCE_RBUF_STATUS2 0x00200008 4169#define BCE_RBUF_STATUS2_FREE_TAIL (0x3ffL<<0) 4170#define BCE_RBUF_STATUS2_FREE_HEAD (0x3ffL<<16) 4171 4172#define BCE_RBUF_CONFIG 0x0020000c 4173#define BCE_RBUF_CONFIG_XOFF_TRIP (0x3ffL<<0) 4174#define BCE_RBUF_CONFIG_XON_TRIP (0x3ffL<<16) 4175 4176#define BCE_RBUF_FW_BUF_ALLOC 0x00200010 4177#define BCE_RBUF_FW_BUF_ALLOC_VALUE (0x1ffL<<7) 4178 4179#define BCE_RBUF_FW_BUF_FREE 0x00200014 4180#define BCE_RBUF_FW_BUF_FREE_COUNT (0x7fL<<0) 4181#define BCE_RBUF_FW_BUF_FREE_TAIL (0x1ffL<<7) 4182#define BCE_RBUF_FW_BUF_FREE_HEAD (0x1ffL<<16) 4183 4184#define BCE_RBUF_FW_BUF_SEL 0x00200018 4185#define BCE_RBUF_FW_BUF_SEL_COUNT (0x7fL<<0) 4186#define BCE_RBUF_FW_BUF_SEL_TAIL (0x1ffL<<7) 4187#define BCE_RBUF_FW_BUF_SEL_HEAD (0x1ffL<<16) 4188 4189#define BCE_RBUF_CONFIG2 0x0020001c 4190#define BCE_RBUF_CONFIG2_MAC_DROP_TRIP (0x3ffL<<0) 4191#define BCE_RBUF_CONFIG2_MAC_KEEP_TRIP (0x3ffL<<16) 4192 4193#define BCE_RBUF_CONFIG3 0x00200020 4194#define BCE_RBUF_CONFIG3_CU_DROP_TRIP (0x3ffL<<0) 4195#define BCE_RBUF_CONFIG3_CU_KEEP_TRIP (0x3ffL<<16) 4196 4197#define BCE_RBUF_PKT_DATA 0x00208000 4198#define BCE_RBUF_CLIST_DATA 0x00210000 4199#define BCE_RBUF_BUF_DATA 0x00220000 4200 4201 4202/* 4203 * rv2p_reg definition 4204 * offset: 0x2800 4205 */ 4206#define BCE_RV2P_COMMAND 0x00002800 4207#define BCE_RV2P_COMMAND_ENABLED (1L<<0) 4208#define BCE_RV2P_COMMAND_PROC1_INTRPT (1L<<1) 4209#define BCE_RV2P_COMMAND_PROC2_INTRPT (1L<<2) 4210#define BCE_RV2P_COMMAND_ABORT0 (1L<<4) 4211#define BCE_RV2P_COMMAND_ABORT1 (1L<<5) 4212#define BCE_RV2P_COMMAND_ABORT2 (1L<<6) 4213#define BCE_RV2P_COMMAND_ABORT3 (1L<<7) 4214#define BCE_RV2P_COMMAND_ABORT4 (1L<<8) 4215#define BCE_RV2P_COMMAND_ABORT5 (1L<<9) 4216#define BCE_RV2P_COMMAND_PROC1_RESET (1L<<16) 4217#define BCE_RV2P_COMMAND_PROC2_RESET (1L<<17) 4218#define BCE_RV2P_COMMAND_CTXIF_RESET (1L<<18) 4219 4220#define BCE_RV2P_STATUS 0x00002804 4221#define BCE_RV2P_STATUS_ALWAYS_0 (1L<<0) 4222#define BCE_RV2P_STATUS_RV2P_GEN_STAT0_CNT (1L<<8) 4223#define BCE_RV2P_STATUS_RV2P_GEN_STAT1_CNT (1L<<9) 4224#define BCE_RV2P_STATUS_RV2P_GEN_STAT2_CNT (1L<<10) 4225#define BCE_RV2P_STATUS_RV2P_GEN_STAT3_CNT (1L<<11) 4226#define BCE_RV2P_STATUS_RV2P_GEN_STAT4_CNT (1L<<12) 4227#define BCE_RV2P_STATUS_RV2P_GEN_STAT5_CNT (1L<<13) 4228 4229#define BCE_RV2P_CONFIG 0x00002808 4230#define BCE_RV2P_CONFIG_STALL_PROC1 (1L<<0) 4231#define BCE_RV2P_CONFIG_STALL_PROC2 (1L<<1) 4232#define BCE_RV2P_CONFIG_PROC1_STALL_ON_ABORT0 (1L<<8) 4233#define BCE_RV2P_CONFIG_PROC1_STALL_ON_ABORT1 (1L<<9) 4234#define BCE_RV2P_CONFIG_PROC1_STALL_ON_ABORT2 (1L<<10) 4235#define BCE_RV2P_CONFIG_PROC1_STALL_ON_ABORT3 (1L<<11) 4236#define BCE_RV2P_CONFIG_PROC1_STALL_ON_ABORT4 (1L<<12) 4237#define BCE_RV2P_CONFIG_PROC1_STALL_ON_ABORT5 (1L<<13) 4238#define BCE_RV2P_CONFIG_PROC2_STALL_ON_ABORT0 (1L<<16) 4239#define BCE_RV2P_CONFIG_PROC2_STALL_ON_ABORT1 (1L<<17) 4240#define BCE_RV2P_CONFIG_PROC2_STALL_ON_ABORT2 (1L<<18) 4241#define BCE_RV2P_CONFIG_PROC2_STALL_ON_ABORT3 (1L<<19) 4242#define BCE_RV2P_CONFIG_PROC2_STALL_ON_ABORT4 (1L<<20) 4243#define BCE_RV2P_CONFIG_PROC2_STALL_ON_ABORT5 (1L<<21) 4244#define BCE_RV2P_CONFIG_PAGE_SIZE (0xfL<<24) 4245#define BCE_RV2P_CONFIG_PAGE_SIZE_256 (0L<<24) 4246#define BCE_RV2P_CONFIG_PAGE_SIZE_512 (1L<<24) 4247#define BCE_RV2P_CONFIG_PAGE_SIZE_1K (2L<<24) 4248#define BCE_RV2P_CONFIG_PAGE_SIZE_2K (3L<<24) 4249#define BCE_RV2P_CONFIG_PAGE_SIZE_4K (4L<<24) 4250#define BCE_RV2P_CONFIG_PAGE_SIZE_8K (5L<<24) 4251#define BCE_RV2P_CONFIG_PAGE_SIZE_16K (6L<<24) 4252#define BCE_RV2P_CONFIG_PAGE_SIZE_32K (7L<<24) 4253#define BCE_RV2P_CONFIG_PAGE_SIZE_64K (8L<<24) 4254#define BCE_RV2P_CONFIG_PAGE_SIZE_128K (9L<<24) 4255#define BCE_RV2P_CONFIG_PAGE_SIZE_256K (10L<<24) 4256#define BCE_RV2P_CONFIG_PAGE_SIZE_512K (11L<<24) 4257#define BCE_RV2P_CONFIG_PAGE_SIZE_1M (12L<<24) 4258 4259#define BCE_RV2P_GEN_BFR_ADDR_0 0x00002810 4260#define BCE_RV2P_GEN_BFR_ADDR_0_VALUE (0xffffL<<16) 4261 4262#define BCE_RV2P_GEN_BFR_ADDR_1 0x00002814 4263#define BCE_RV2P_GEN_BFR_ADDR_1_VALUE (0xffffL<<16) 4264 4265#define BCE_RV2P_GEN_BFR_ADDR_2 0x00002818 4266#define BCE_RV2P_GEN_BFR_ADDR_2_VALUE (0xffffL<<16) 4267 4268#define BCE_RV2P_GEN_BFR_ADDR_3 0x0000281c 4269#define BCE_RV2P_GEN_BFR_ADDR_3_VALUE (0xffffL<<16) 4270 4271#define BCE_RV2P_INSTR_HIGH 0x00002830 4272#define BCE_RV2P_INSTR_HIGH_HIGH (0x1fL<<0) 4273 4274#define BCE_RV2P_INSTR_LOW 0x00002834 4275#define BCE_RV2P_PROC1_ADDR_CMD 0x00002838 4276#define BCE_RV2P_PROC1_ADDR_CMD_ADD (0x3ffL<<0) 4277#define BCE_RV2P_PROC1_ADDR_CMD_RDWR (1L<<31) 4278 4279#define BCE_RV2P_PROC2_ADDR_CMD 0x0000283c 4280#define BCE_RV2P_PROC2_ADDR_CMD_ADD (0x3ffL<<0) 4281#define BCE_RV2P_PROC2_ADDR_CMD_RDWR (1L<<31) 4282 4283#define BCE_RV2P_PROC1_GRC_DEBUG 0x00002840 4284#define BCE_RV2P_PROC2_GRC_DEBUG 0x00002844 4285#define BCE_RV2P_GRC_PROC_DEBUG 0x00002848 4286#define BCE_RV2P_DEBUG_VECT_PEEK 0x0000284c 4287#define BCE_RV2P_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) 4288#define BCE_RV2P_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) 4289#define BCE_RV2P_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) 4290#define BCE_RV2P_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) 4291#define BCE_RV2P_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) 4292#define BCE_RV2P_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) 4293 4294#define BCE_RV2P_PFTQ_DATA 0x00002b40 4295#define BCE_RV2P_PFTQ_CMD 0x00002b78 4296#define BCE_RV2P_PFTQ_CMD_OFFSET (0x3ffL<<0) 4297#define BCE_RV2P_PFTQ_CMD_WR_TOP (1L<<10) 4298#define BCE_RV2P_PFTQ_CMD_WR_TOP_0 (0L<<10) 4299#define BCE_RV2P_PFTQ_CMD_WR_TOP_1 (1L<<10) 4300#define BCE_RV2P_PFTQ_CMD_SFT_RESET (1L<<25) 4301#define BCE_RV2P_PFTQ_CMD_RD_DATA (1L<<26) 4302#define BCE_RV2P_PFTQ_CMD_ADD_INTERVEN (1L<<27) 4303#define BCE_RV2P_PFTQ_CMD_ADD_DATA (1L<<28) 4304#define BCE_RV2P_PFTQ_CMD_INTERVENE_CLR (1L<<29) 4305#define BCE_RV2P_PFTQ_CMD_POP (1L<<30) 4306#define BCE_RV2P_PFTQ_CMD_BUSY (1L<<31) 4307 4308#define BCE_RV2P_PFTQ_CTL 0x00002b7c 4309#define BCE_RV2P_PFTQ_CTL_INTERVENE (1L<<0) 4310#define BCE_RV2P_PFTQ_CTL_OVERFLOW (1L<<1) 4311#define BCE_RV2P_PFTQ_CTL_FORCE_INTERVENE (1L<<2) 4312#define BCE_RV2P_PFTQ_CTL_MAX_DEPTH (0x3ffL<<12) 4313#define BCE_RV2P_PFTQ_CTL_CUR_DEPTH (0x3ffL<<22) 4314 4315#define BCE_RV2P_TFTQ_DATA 0x00002b80 4316#define BCE_RV2P_TFTQ_CMD 0x00002bb8 4317#define BCE_RV2P_TFTQ_CMD_OFFSET (0x3ffL<<0) 4318#define BCE_RV2P_TFTQ_CMD_WR_TOP (1L<<10) 4319#define BCE_RV2P_TFTQ_CMD_WR_TOP_0 (0L<<10) 4320#define BCE_RV2P_TFTQ_CMD_WR_TOP_1 (1L<<10) 4321#define BCE_RV2P_TFTQ_CMD_SFT_RESET (1L<<25) 4322#define BCE_RV2P_TFTQ_CMD_RD_DATA (1L<<26) 4323#define BCE_RV2P_TFTQ_CMD_ADD_INTERVEN (1L<<27) 4324#define BCE_RV2P_TFTQ_CMD_ADD_DATA (1L<<28) 4325#define BCE_RV2P_TFTQ_CMD_INTERVENE_CLR (1L<<29) 4326#define BCE_RV2P_TFTQ_CMD_POP (1L<<30) 4327#define BCE_RV2P_TFTQ_CMD_BUSY (1L<<31) 4328 4329#define BCE_RV2P_TFTQ_CTL 0x00002bbc 4330#define BCE_RV2P_TFTQ_CTL_INTERVENE (1L<<0) 4331#define BCE_RV2P_TFTQ_CTL_OVERFLOW (1L<<1) 4332#define BCE_RV2P_TFTQ_CTL_FORCE_INTERVENE (1L<<2) 4333#define BCE_RV2P_TFTQ_CTL_MAX_DEPTH (0x3ffL<<12) 4334#define BCE_RV2P_TFTQ_CTL_CUR_DEPTH (0x3ffL<<22) 4335 4336#define BCE_RV2P_MFTQ_DATA 0x00002bc0 4337#define BCE_RV2P_MFTQ_CMD 0x00002bf8 4338#define BCE_RV2P_MFTQ_CMD_OFFSET (0x3ffL<<0) 4339#define BCE_RV2P_MFTQ_CMD_WR_TOP (1L<<10) 4340#define BCE_RV2P_MFTQ_CMD_WR_TOP_0 (0L<<10) 4341#define BCE_RV2P_MFTQ_CMD_WR_TOP_1 (1L<<10) 4342#define BCE_RV2P_MFTQ_CMD_SFT_RESET (1L<<25) 4343#define BCE_RV2P_MFTQ_CMD_RD_DATA (1L<<26) 4344#define BCE_RV2P_MFTQ_CMD_ADD_INTERVEN (1L<<27) 4345#define BCE_RV2P_MFTQ_CMD_ADD_DATA (1L<<28) 4346#define BCE_RV2P_MFTQ_CMD_INTERVENE_CLR (1L<<29) 4347#define BCE_RV2P_MFTQ_CMD_POP (1L<<30) 4348#define BCE_RV2P_MFTQ_CMD_BUSY (1L<<31) 4349 4350#define BCE_RV2P_MFTQ_CTL 0x00002bfc 4351#define BCE_RV2P_MFTQ_CTL_INTERVENE (1L<<0) 4352#define BCE_RV2P_MFTQ_CTL_OVERFLOW (1L<<1) 4353#define BCE_RV2P_MFTQ_CTL_FORCE_INTERVENE (1L<<2) 4354#define BCE_RV2P_MFTQ_CTL_MAX_DEPTH (0x3ffL<<12) 4355#define BCE_RV2P_MFTQ_CTL_CUR_DEPTH (0x3ffL<<22) 4356 4357 4358/* 4359 * mq_reg definition 4360 * offset: 0x3c00 4361 */ 4362#define BCE_MQ_COMMAND 0x00003c00 4363#define BCE_MQ_COMMAND_ENABLED (1L<<0) 4364#define BCE_MQ_COMMAND_INIT (1L<<1) 4365#define BCE_MQ_COMMAND_OVERFLOW (1L<<4) 4366#define BCE_MQ_COMMAND_WR_ERROR (1L<<5) 4367#define BCE_MQ_COMMAND_RD_ERROR (1L<<6) 4368#define BCE_MQ_COMMAND_IDB_CFG_ERROR (1L<<7) 4369#define BCE_MQ_COMMAND_IDB_OVERFLOW (1L<<10) 4370#define BCE_MQ_COMMAND_NO_BIN_ERROR (1L<<11) 4371#define BCE_MQ_COMMAND_NO_MAP_ERROR (1L<<12) 4372 4373#define BCE_MQ_STATUS 0x00003c04 4374#define BCE_MQ_STATUS_CTX_ACCESS_STAT (1L<<16) 4375#define BCE_MQ_STATUS_CTX_ACCESS64_STAT (1L<<17) 4376#define BCE_MQ_STATUS_PCI_STALL_STAT (1L<<18) 4377#define BCE_MQ_STATUS_IDB_OFLOW_STAT (1L<<19) 4378 4379#define BCE_MQ_CONFIG 0x00003c08 4380#define BCE_MQ_CONFIG_TX_HIGH_PRI (1L<<0) 4381#define BCE_MQ_CONFIG_HALT_DIS (1L<<1) 4382#define BCE_MQ_CONFIG_BIN_MQ_MODE (1L<<2) 4383#define BCE_MQ_CONFIG_DIS_IDB_DROP (1L<<3) 4384#define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE (0x7L<<4) 4385#define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256 (0L<<4) 4386#define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_512 (1L<<4) 4387#define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_1K (2L<<4) 4388#define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_2K (3L<<4) 4389#define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_4K (4L<<4) 4390#define BCE_MQ_CONFIG_MAX_DEPTH (0x7fL<<8) 4391#define BCE_MQ_CONFIG_CUR_DEPTH (0x7fL<<20) 4392 4393#define BCE_MQ_ENQUEUE1 0x00003c0c 4394#define BCE_MQ_ENQUEUE1_OFFSET (0x3fL<<2) 4395#define BCE_MQ_ENQUEUE1_CID (0x3fffL<<8) 4396#define BCE_MQ_ENQUEUE1_BYTE_MASK (0xfL<<24) 4397#define BCE_MQ_ENQUEUE1_KNL_MODE (1L<<28) 4398 4399#define BCE_MQ_ENQUEUE2 0x00003c10 4400#define BCE_MQ_BAD_WR_ADDR 0x00003c14 4401#define BCE_MQ_BAD_RD_ADDR 0x00003c18 4402#define BCE_MQ_KNL_BYP_WIND_START 0x00003c1c 4403#define BCE_MQ_KNL_BYP_WIND_START_VALUE (0xfffffL<<12) 4404 4405#define BCE_MQ_KNL_WIND_END 0x00003c20 4406#define BCE_MQ_KNL_WIND_END_VALUE (0xffffffL<<8) 4407 4408#define BCE_MQ_KNL_WRITE_MASK1 0x00003c24 4409#define BCE_MQ_KNL_TX_MASK1 0x00003c28 4410#define BCE_MQ_KNL_CMD_MASK1 0x00003c2c 4411#define BCE_MQ_KNL_COND_ENQUEUE_MASK1 0x00003c30 4412#define BCE_MQ_KNL_RX_V2P_MASK1 0x00003c34 4413#define BCE_MQ_KNL_WRITE_MASK2 0x00003c38 4414#define BCE_MQ_KNL_TX_MASK2 0x00003c3c 4415#define BCE_MQ_KNL_CMD_MASK2 0x00003c40 4416#define BCE_MQ_KNL_COND_ENQUEUE_MASK2 0x00003c44 4417#define BCE_MQ_KNL_RX_V2P_MASK2 0x00003c48 4418#define BCE_MQ_KNL_BYP_WRITE_MASK1 0x00003c4c 4419#define BCE_MQ_KNL_BYP_TX_MASK1 0x00003c50 4420#define BCE_MQ_KNL_BYP_CMD_MASK1 0x00003c54 4421#define BCE_MQ_KNL_BYP_COND_ENQUEUE_MASK1 0x00003c58 4422#define BCE_MQ_KNL_BYP_RX_V2P_MASK1 0x00003c5c 4423#define BCE_MQ_KNL_BYP_WRITE_MASK2 0x00003c60 4424#define BCE_MQ_KNL_BYP_TX_MASK2 0x00003c64 4425#define BCE_MQ_KNL_BYP_CMD_MASK2 0x00003c68 4426#define BCE_MQ_KNL_BYP_COND_ENQUEUE_MASK2 0x00003c6c 4427#define BCE_MQ_KNL_BYP_RX_V2P_MASK2 0x00003c70 4428#define BCE_MQ_MEM_WR_ADDR 0x00003c74 4429#define BCE_MQ_MEM_WR_ADDR_VALUE (0x3fL<<0) 4430 4431#define BCE_MQ_MEM_WR_DATA0 0x00003c78 4432#define BCE_MQ_MEM_WR_DATA0_VALUE (0xffffffffL<<0) 4433 4434#define BCE_MQ_MEM_WR_DATA1 0x00003c7c 4435#define BCE_MQ_MEM_WR_DATA1_VALUE (0xffffffffL<<0) 4436 4437#define BCE_MQ_MEM_WR_DATA2 0x00003c80 4438#define BCE_MQ_MEM_WR_DATA2_VALUE (0x3fffffffL<<0) 4439#define BCE_MQ_MEM_WR_DATA2_VALUE_XI (0x7fffffffL<<0) 4440 4441#define BCE_MQ_MEM_RD_ADDR 0x00003c84 4442#define BCE_MQ_MEM_RD_ADDR_VALUE (0x3fL<<0) 4443 4444#define BCE_MQ_MEM_RD_DATA0 0x00003c88 4445#define BCE_MQ_MEM_RD_DATA0_VALUE (0xffffffffL<<0) 4446 4447#define BCE_MQ_MEM_RD_DATA1 0x00003c8c 4448#define BCE_MQ_MEM_RD_DATA1_VALUE (0xffffffffL<<0) 4449 4450#define BCE_MQ_MEM_RD_DATA2 0x00003c90 4451#define BCE_MQ_MEM_RD_DATA2_VALUE (0x3fffffffL<<0) 4452#define BCE_MQ_MEM_RD_DATA2_VALUE_XI (0x7fffffffL<<0) 4453 4454#define BCE_MQ_CONFIG2 0x00003d00 4455#define BCE_MQ_CONFIG2_CONT_SZ (0x7L<<4) 4456#define BCE_MQ_CONFIG2_FIRST_L4L5 (0x1fL<<8) 4457 4458#define BCE_MQ_MAP_L2_3 0x00003d2c 4459#define BCE_MQ_MAP_L2_3_MQ_OFFSET (0xffL<<0) 4460#define BCE_MQ_MAP_L2_3_SZ (0x3L<<8) 4461#define BCE_MQ_MAP_L2_3_CTX_OFFSET (0x2ffL<<10) 4462#define BCE_MQ_MAP_L2_3_BIN_OFFSET (0x7L<<23) 4463#define BCE_MQ_MAP_L2_3_ARM (0x3L<<26) 4464#define BCE_MQ_MAP_L2_3_ENA (0x1L<<31) 4465#define BCE_MQ_MAP_L2_3_DEFAULT 0x82004646 4466 4467#define BCE_MQ_MAP_L2_5 0x00003d34 4468#define BCE_MQ_MAP_L2_5_MQ_OFFSET (0xffL<<0) 4469#define BCE_MQ_MAP_L2_5_SZ (0x3L<<8) 4470#define BCE_MQ_MAP_L2_5_CTX_OFFSET (0x2ffL<<10) 4471#define BCE_MQ_MAP_L2_5_BIN_OFFSET (0x7L<<23) 4472#define BCE_MQ_MAP_L2_5_ARM (0x3L<<26) 4473#define BCE_MQ_MAP_L2_5_ENA (0x1L<<31) 4474#define BCE_MQ_MAP_L2_5_DEFAULT 0x83000b08 4475 4476 4477/* 4478 * csch_reg definition 4479 * offset: 0x4000 4480 */ 4481#define BCE_CSCH_COMMAND 0x00004000 4482#define BCE_CSCH_CH_FTQ_CMD 0x000043f8 4483#define BCE_CSCH_CH_FTQ_CTL 0x000043fc 4484#define BCE_CSCH_CH_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 4485#define BCE_CSCH_CH_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 4486 4487 4488/* 4489 * tbdr_reg definition 4490 * offset: 0x5000 4491 */ 4492#define BCE_TBDR_COMMAND 0x00005000 4493#define BCE_TBDR_COMMAND_ENABLE (1L<<0) 4494#define BCE_TBDR_COMMAND_SOFT_RST (1L<<1) 4495#define BCE_TBDR_COMMAND_MSTR_ABORT (1L<<4) 4496 4497#define BCE_TBDR_STATUS 0x00005004 4498#define BCE_TBDR_STATUS_DMA_WAIT (1L<<0) 4499#define BCE_TBDR_STATUS_FTQ_WAIT (1L<<1) 4500#define BCE_TBDR_STATUS_FIFO_OVERFLOW (1L<<2) 4501#define BCE_TBDR_STATUS_FIFO_UNDERFLOW (1L<<3) 4502#define BCE_TBDR_STATUS_SEARCHMISS_ERROR (1L<<4) 4503#define BCE_TBDR_STATUS_FTQ_ENTRY_CNT (1L<<5) 4504#define BCE_TBDR_STATUS_BURST_CNT (1L<<6) 4505 4506#define BCE_TBDR_CONFIG 0x00005008 4507#define BCE_TBDR_CONFIG_MAX_BDS (0xffL<<0) 4508#define BCE_TBDR_CONFIG_SWAP_MODE (1L<<8) 4509#define BCE_TBDR_CONFIG_PRIORITY (1L<<9) 4510#define BCE_TBDR_CONFIG_CACHE_NEXT_PAGE_PTRS (1L<<10) 4511#define BCE_TBDR_CONFIG_PAGE_SIZE (0xfL<<24) 4512#define BCE_TBDR_CONFIG_PAGE_SIZE_256 (0L<<24) 4513#define BCE_TBDR_CONFIG_PAGE_SIZE_512 (1L<<24) 4514#define BCE_TBDR_CONFIG_PAGE_SIZE_1K (2L<<24) 4515#define BCE_TBDR_CONFIG_PAGE_SIZE_2K (3L<<24) 4516#define BCE_TBDR_CONFIG_PAGE_SIZE_4K (4L<<24) 4517#define BCE_TBDR_CONFIG_PAGE_SIZE_8K (5L<<24) 4518#define BCE_TBDR_CONFIG_PAGE_SIZE_16K (6L<<24) 4519#define BCE_TBDR_CONFIG_PAGE_SIZE_32K (7L<<24) 4520#define BCE_TBDR_CONFIG_PAGE_SIZE_64K (8L<<24) 4521#define BCE_TBDR_CONFIG_PAGE_SIZE_128K (9L<<24) 4522#define BCE_TBDR_CONFIG_PAGE_SIZE_256K (10L<<24) 4523#define BCE_TBDR_CONFIG_PAGE_SIZE_512K (11L<<24) 4524#define BCE_TBDR_CONFIG_PAGE_SIZE_1M (12L<<24) 4525 4526#define BCE_TBDR_DEBUG_VECT_PEEK 0x0000500c 4527#define BCE_TBDR_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) 4528#define BCE_TBDR_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) 4529#define BCE_TBDR_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) 4530#define BCE_TBDR_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) 4531#define BCE_TBDR_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) 4532#define BCE_TBDR_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) 4533 4534#define BCE_TBDR_FTQ_DATA 0x000053c0 4535#define BCE_TBDR_FTQ_CMD 0x000053f8 4536#define BCE_TBDR_FTQ_CMD_OFFSET (0x3ffL<<0) 4537#define BCE_TBDR_FTQ_CMD_WR_TOP (1L<<10) 4538#define BCE_TBDR_FTQ_CMD_WR_TOP_0 (0L<<10) 4539#define BCE_TBDR_FTQ_CMD_WR_TOP_1 (1L<<10) 4540#define BCE_TBDR_FTQ_CMD_SFT_RESET (1L<<25) 4541#define BCE_TBDR_FTQ_CMD_RD_DATA (1L<<26) 4542#define BCE_TBDR_FTQ_CMD_ADD_INTERVEN (1L<<27) 4543#define BCE_TBDR_FTQ_CMD_ADD_DATA (1L<<28) 4544#define BCE_TBDR_FTQ_CMD_INTERVENE_CLR (1L<<29) 4545#define BCE_TBDR_FTQ_CMD_POP (1L<<30) 4546#define BCE_TBDR_FTQ_CMD_BUSY (1L<<31) 4547 4548#define BCE_TBDR_FTQ_CTL 0x000053fc 4549#define BCE_TBDR_FTQ_CTL_INTERVENE (1L<<0) 4550#define BCE_TBDR_FTQ_CTL_OVERFLOW (1L<<1) 4551#define BCE_TBDR_FTQ_CTL_FORCE_INTERVENE (1L<<2) 4552#define BCE_TBDR_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 4553#define BCE_TBDR_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 4554 4555 4556/* 4557 * tdma_reg definition 4558 * offset: 0x5c00 4559 */ 4560#define BCE_TDMA_COMMAND 0x00005c00 4561#define BCE_TDMA_COMMAND_ENABLED (1L<<0) 4562#define BCE_TDMA_COMMAND_MASTER_ABORT (1L<<4) 4563#define BCE_TDMA_COMMAND_BAD_L2_LENGTH_ABORT (1L<<7) 4564 4565#define BCE_TDMA_STATUS 0x00005c04 4566#define BCE_TDMA_STATUS_DMA_WAIT (1L<<0) 4567#define BCE_TDMA_STATUS_PAYLOAD_WAIT (1L<<1) 4568#define BCE_TDMA_STATUS_PATCH_FTQ_WAIT (1L<<2) 4569#define BCE_TDMA_STATUS_LOCK_WAIT (1L<<3) 4570#define BCE_TDMA_STATUS_FTQ_ENTRY_CNT (1L<<16) 4571#define BCE_TDMA_STATUS_BURST_CNT (1L<<17) 4572 4573#define BCE_TDMA_CONFIG 0x00005c08 4574#define BCE_TDMA_CONFIG_ONE_DMA (1L<<0) 4575#define BCE_TDMA_CONFIG_ONE_RECORD (1L<<1) 4576#define BCE_TDMA_CONFIG_LIMIT_SZ (0xfL<<4) 4577#define BCE_TDMA_CONFIG_LIMIT_SZ_64 (0L<<4) 4578#define BCE_TDMA_CONFIG_LIMIT_SZ_128 (0x4L<<4) 4579#define BCE_TDMA_CONFIG_LIMIT_SZ_256 (0x6L<<4) 4580#define BCE_TDMA_CONFIG_LIMIT_SZ_512 (0x8L<<4) 4581#define BCE_TDMA_CONFIG_LINE_SZ (0xfL<<8) 4582#define BCE_TDMA_CONFIG_LINE_SZ_64 (0L<<8) 4583#define BCE_TDMA_CONFIG_LINE_SZ_128 (4L<<8) 4584#define BCE_TDMA_CONFIG_LINE_SZ_256 (6L<<8) 4585#define BCE_TDMA_CONFIG_LINE_SZ_512 (8L<<8) 4586#define BCE_TDMA_CONFIG_ALIGN_ENA (1L<<15) 4587#define BCE_TDMA_CONFIG_CHK_L2_BD (1L<<16) 4588#define BCE_TDMA_CONFIG_FIFO_CMP (0xfL<<20) 4589 4590#define BCE_TDMA_PAYLOAD_PROD 0x00005c0c 4591#define BCE_TDMA_PAYLOAD_PROD_VALUE (0x1fffL<<3) 4592 4593#define BCE_TDMA_DBG_WATCHDOG 0x00005c10 4594#define BCE_TDMA_DBG_TRIGGER 0x00005c14 4595#define BCE_TDMA_DMAD_FSM 0x00005c80 4596#define BCE_TDMA_DMAD_FSM_BD_INVLD (1L<<0) 4597#define BCE_TDMA_DMAD_FSM_PUSH (0xfL<<4) 4598#define BCE_TDMA_DMAD_FSM_ARB_TBDC (0x3L<<8) 4599#define BCE_TDMA_DMAD_FSM_ARB_CTX (1L<<12) 4600#define BCE_TDMA_DMAD_FSM_DR_INTF (1L<<16) 4601#define BCE_TDMA_DMAD_FSM_DMAD (0x7L<<20) 4602#define BCE_TDMA_DMAD_FSM_BD (0xfL<<24) 4603 4604#define BCE_TDMA_DMAD_STATUS 0x00005c84 4605#define BCE_TDMA_DMAD_STATUS_RHOLD_PUSH_ENTRY (0x3L<<0) 4606#define BCE_TDMA_DMAD_STATUS_RHOLD_DMAD_ENTRY (0x3L<<4) 4607#define BCE_TDMA_DMAD_STATUS_RHOLD_BD_ENTRY (0x3L<<8) 4608#define BCE_TDMA_DMAD_STATUS_IFTQ_ENUM (0xfL<<12) 4609 4610#define BCE_TDMA_DR_INTF_FSM 0x00005c88 4611#define BCE_TDMA_DR_INTF_FSM_L2_COMP (0x3L<<0) 4612#define BCE_TDMA_DR_INTF_FSM_TPATQ (0x7L<<4) 4613#define BCE_TDMA_DR_INTF_FSM_TPBUF (0x3L<<8) 4614#define BCE_TDMA_DR_INTF_FSM_DR_BUF (0x7L<<12) 4615#define BCE_TDMA_DR_INTF_FSM_DMAD (0x7L<<16) 4616 4617#define BCE_TDMA_DR_INTF_STATUS 0x00005c8c 4618#define BCE_TDMA_DR_INTF_STATUS_HOLE_PHASE (0x7L<<0) 4619#define BCE_TDMA_DR_INTF_STATUS_DATA_AVAIL (0x3L<<4) 4620#define BCE_TDMA_DR_INTF_STATUS_SHIFT_ADDR (0x7L<<8) 4621#define BCE_TDMA_DR_INTF_STATUS_NXT_PNTR (0xfL<<12) 4622#define BCE_TDMA_DR_INTF_STATUS_BYTE_COUNT (0x7L<<16) 4623 4624#define BCE_TDMA_FTQ_DATA 0x00005fc0 4625#define BCE_TDMA_FTQ_CMD 0x00005ff8 4626#define BCE_TDMA_FTQ_CMD_OFFSET (0x3ffL<<0) 4627#define BCE_TDMA_FTQ_CMD_WR_TOP (1L<<10) 4628#define BCE_TDMA_FTQ_CMD_WR_TOP_0 (0L<<10) 4629#define BCE_TDMA_FTQ_CMD_WR_TOP_1 (1L<<10) 4630#define BCE_TDMA_FTQ_CMD_SFT_RESET (1L<<25) 4631#define BCE_TDMA_FTQ_CMD_RD_DATA (1L<<26) 4632#define BCE_TDMA_FTQ_CMD_ADD_INTERVEN (1L<<27) 4633#define BCE_TDMA_FTQ_CMD_ADD_DATA (1L<<28) 4634#define BCE_TDMA_FTQ_CMD_INTERVENE_CLR (1L<<29) 4635#define BCE_TDMA_FTQ_CMD_POP (1L<<30) 4636#define BCE_TDMA_FTQ_CMD_BUSY (1L<<31) 4637 4638#define BCE_TDMA_FTQ_CTL 0x00005ffc 4639#define BCE_TDMA_FTQ_CTL_INTERVENE (1L<<0) 4640#define BCE_TDMA_FTQ_CTL_OVERFLOW (1L<<1) 4641#define BCE_TDMA_FTQ_CTL_FORCE_INTERVENE (1L<<2) 4642#define BCE_TDMA_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 4643#define BCE_TDMA_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 4644 4645 4646/* 4647 * nvm_reg definition 4648 * offset: 0x6400 4649 */ 4650#define BCE_NVM_COMMAND 0x00006400 4651#define BCE_NVM_COMMAND_RST (1L<<0) 4652#define BCE_NVM_COMMAND_DONE (1L<<3) 4653#define BCE_NVM_COMMAND_DOIT (1L<<4) 4654#define BCE_NVM_COMMAND_WR (1L<<5) 4655#define BCE_NVM_COMMAND_ERASE (1L<<6) 4656#define BCE_NVM_COMMAND_FIRST (1L<<7) 4657#define BCE_NVM_COMMAND_LAST (1L<<8) 4658#define BCE_NVM_COMMAND_WREN (1L<<16) 4659#define BCE_NVM_COMMAND_WRDI (1L<<17) 4660#define BCE_NVM_COMMAND_EWSR (1L<<18) 4661#define BCE_NVM_COMMAND_WRSR (1L<<19) 4662 4663#define BCE_NVM_STATUS 0x00006404 4664#define BCE_NVM_STATUS_PI_FSM_STATE (0xfL<<0) 4665#define BCE_NVM_STATUS_EE_FSM_STATE (0xfL<<4) 4666#define BCE_NVM_STATUS_EQ_FSM_STATE (0xfL<<8) 4667 4668#define BCE_NVM_WRITE 0x00006408 4669#define BCE_NVM_WRITE_NVM_WRITE_VALUE (0xffffffffL<<0) 4670#define BCE_NVM_WRITE_NVM_WRITE_VALUE_BIT_BANG (0L<<0) 4671#define BCE_NVM_WRITE_NVM_WRITE_VALUE_EECLK (1L<<0) 4672#define BCE_NVM_WRITE_NVM_WRITE_VALUE_EEDATA (2L<<0) 4673#define BCE_NVM_WRITE_NVM_WRITE_VALUE_SCLK (4L<<0) 4674#define BCE_NVM_WRITE_NVM_WRITE_VALUE_CS_B (8L<<0) 4675#define BCE_NVM_WRITE_NVM_WRITE_VALUE_SO (16L<<0) 4676#define BCE_NVM_WRITE_NVM_WRITE_VALUE_SI (32L<<0) 4677 4678#define BCE_NVM_ADDR 0x0000640c 4679#define BCE_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL<<0) 4680#define BCE_NVM_ADDR_NVM_ADDR_VALUE_BIT_BANG (0L<<0) 4681#define BCE_NVM_ADDR_NVM_ADDR_VALUE_EECLK (1L<<0) 4682#define BCE_NVM_ADDR_NVM_ADDR_VALUE_EEDATA (2L<<0) 4683#define BCE_NVM_ADDR_NVM_ADDR_VALUE_SCLK (4L<<0) 4684#define BCE_NVM_ADDR_NVM_ADDR_VALUE_CS_B (8L<<0) 4685#define BCE_NVM_ADDR_NVM_ADDR_VALUE_SO (16L<<0) 4686#define BCE_NVM_ADDR_NVM_ADDR_VALUE_SI (32L<<0) 4687 4688#define BCE_NVM_READ 0x00006410 4689#define BCE_NVM_READ_NVM_READ_VALUE (0xffffffffL<<0) 4690#define BCE_NVM_READ_NVM_READ_VALUE_BIT_BANG (0L<<0) 4691#define BCE_NVM_READ_NVM_READ_VALUE_EECLK (1L<<0) 4692#define BCE_NVM_READ_NVM_READ_VALUE_EEDATA (2L<<0) 4693#define BCE_NVM_READ_NVM_READ_VALUE_SCLK (4L<<0) 4694#define BCE_NVM_READ_NVM_READ_VALUE_CS_B (8L<<0) 4695#define BCE_NVM_READ_NVM_READ_VALUE_SO (16L<<0) 4696#define BCE_NVM_READ_NVM_READ_VALUE_SI (32L<<0) 4697 4698#define BCE_NVM_CFG1 0x00006414 4699#define BCE_NVM_CFG1_FLASH_MODE (1L<<0) 4700#define BCE_NVM_CFG1_BUFFER_MODE (1L<<1) 4701#define BCE_NVM_CFG1_PASS_MODE (1L<<2) 4702#define BCE_NVM_CFG1_BITBANG_MODE (1L<<3) 4703#define BCE_NVM_CFG1_STATUS_BIT (0x7L<<4) 4704#define BCE_NVM_CFG1_STATUS_BIT_FLASH_RDY (0L<<4) 4705#define BCE_NVM_CFG1_STATUS_BIT_BUFFER_RDY (7L<<4) 4706#define BCE_NVM_CFG1_SPI_CLK_DIV (0xfL<<7) 4707#define BCE_NVM_CFG1_SEE_CLK_DIV (0x7ffL<<11) 4708#define BCE_NVM_CFG1_PROTECT_MODE (1L<<24) 4709#define BCE_NVM_CFG1_FLASH_SIZE (1L<<25) 4710#define BCE_NVM_CFG1_COMPAT_BYPASSS (1L<<31) 4711 4712#define BCE_NVM_CFG2 0x00006418 4713#define BCE_NVM_CFG2_ERASE_CMD (0xffL<<0) 4714#define BCE_NVM_CFG2_DUMMY (0xffL<<8) 4715#define BCE_NVM_CFG2_STATUS_CMD (0xffL<<16) 4716 4717#define BCE_NVM_CFG3 0x0000641c 4718#define BCE_NVM_CFG3_BUFFER_RD_CMD (0xffL<<0) 4719#define BCE_NVM_CFG3_WRITE_CMD (0xffL<<8) 4720#define BCE_NVM_CFG3_BUFFER_WRITE_CMD (0xffL<<16) 4721#define BCE_NVM_CFG3_READ_CMD (0xffL<<24) 4722 4723#define BCE_NVM_SW_ARB 0x00006420 4724#define BCE_NVM_SW_ARB_ARB_REQ_SET0 (1L<<0) 4725#define BCE_NVM_SW_ARB_ARB_REQ_SET1 (1L<<1) 4726#define BCE_NVM_SW_ARB_ARB_REQ_SET2 (1L<<2) 4727#define BCE_NVM_SW_ARB_ARB_REQ_SET3 (1L<<3) 4728#define BCE_NVM_SW_ARB_ARB_REQ_CLR0 (1L<<4) 4729#define BCE_NVM_SW_ARB_ARB_REQ_CLR1 (1L<<5) 4730#define BCE_NVM_SW_ARB_ARB_REQ_CLR2 (1L<<6) 4731#define BCE_NVM_SW_ARB_ARB_REQ_CLR3 (1L<<7) 4732#define BCE_NVM_SW_ARB_ARB_ARB0 (1L<<8) 4733#define BCE_NVM_SW_ARB_ARB_ARB1 (1L<<9) 4734#define BCE_NVM_SW_ARB_ARB_ARB2 (1L<<10) 4735#define BCE_NVM_SW_ARB_ARB_ARB3 (1L<<11) 4736#define BCE_NVM_SW_ARB_REQ0 (1L<<12) 4737#define BCE_NVM_SW_ARB_REQ1 (1L<<13) 4738#define BCE_NVM_SW_ARB_REQ2 (1L<<14) 4739#define BCE_NVM_SW_ARB_REQ3 (1L<<15) 4740 4741#define BCE_NVM_ACCESS_ENABLE 0x00006424 4742#define BCE_NVM_ACCESS_ENABLE_EN (1L<<0) 4743#define BCE_NVM_ACCESS_ENABLE_WR_EN (1L<<1) 4744 4745#define BCE_NVM_WRITE1 0x00006428 4746#define BCE_NVM_WRITE1_WREN_CMD (0xffL<<0) 4747#define BCE_NVM_WRITE1_WRDI_CMD (0xffL<<8) 4748#define BCE_NVM_WRITE1_SR_DATA (0xffL<<16) 4749 4750 4751/* 4752 * hc_reg definition 4753 * offset: 0x6800 4754 */ 4755#define BCE_HC_COMMAND 0x00006800 4756#define BCE_HC_COMMAND_ENABLE (1L<<0) 4757#define BCE_HC_COMMAND_SKIP_ABORT (1L<<4) 4758#define BCE_HC_COMMAND_COAL_NOW (1L<<16) 4759#define BCE_HC_COMMAND_COAL_NOW_WO_INT (1L<<17) 4760#define BCE_HC_COMMAND_STATS_NOW (1L<<18) 4761#define BCE_HC_COMMAND_FORCE_INT (0x3L<<19) 4762#define BCE_HC_COMMAND_FORCE_INT_NULL (0L<<19) 4763#define BCE_HC_COMMAND_FORCE_INT_HIGH (1L<<19) 4764#define BCE_HC_COMMAND_FORCE_INT_LOW (2L<<19) 4765#define BCE_HC_COMMAND_FORCE_INT_FREE (3L<<19) 4766#define BCE_HC_COMMAND_CLR_STAT_NOW (1L<<21) 4767#define BCE_HC_COMMAND_MAIN_PWR_INT (1L<<22) 4768#define BCE_HC_COMMAND_COAL_ON_NEXT_EVENT (1L<<27) 4769 4770#define BCE_HC_STATUS 0x00006804 4771#define BCE_HC_STATUS_MASTER_ABORT (1L<<0) 4772#define BCE_HC_STATUS_PARITY_ERROR_STATE (1L<<1) 4773#define BCE_HC_STATUS_PCI_CLK_CNT_STAT (1L<<16) 4774#define BCE_HC_STATUS_CORE_CLK_CNT_STAT (1L<<17) 4775#define BCE_HC_STATUS_NUM_STATUS_BLOCKS_STAT (1L<<18) 4776#define BCE_HC_STATUS_NUM_INT_GEN_STAT (1L<<19) 4777#define BCE_HC_STATUS_NUM_INT_MBOX_WR_STAT (1L<<20) 4778#define BCE_HC_STATUS_CORE_CLKS_TO_HW_INTACK_STAT (1L<<23) 4779#define BCE_HC_STATUS_CORE_CLKS_TO_SW_INTACK_STAT (1L<<24) 4780#define BCE_HC_STATUS_CORE_CLKS_DURING_SW_INTACK_STAT (1L<<25) 4781 4782#define BCE_HC_CONFIG 0x00006808 4783#define BCE_HC_CONFIG_COLLECT_STATS (1L<<0) 4784#define BCE_HC_CONFIG_RX_TMR_MODE (1L<<1) 4785#define BCE_HC_CONFIG_TX_TMR_MODE (1L<<2) 4786#define BCE_HC_CONFIG_COM_TMR_MODE (1L<<3) 4787#define BCE_HC_CONFIG_CMD_TMR_MODE (1L<<4) 4788#define BCE_HC_CONFIG_STATISTIC_PRIORITY (1L<<5) 4789#define BCE_HC_CONFIG_STATUS_PRIORITY (1L<<6) 4790#define BCE_HC_CONFIG_STAT_MEM_ADDR (0xffL<<8) 4791#define BCE_HC_CONFIG_PER_MODE (1L<<16) 4792#define BCE_HC_CONFIG_ONE_SHOT (1L<<17) 4793#define BCE_HC_CONFIG_USE_INT_PARAM (1L<<18) 4794#define BCE_HC_CONFIG_SET_MASK_AT_RD (1L<<19) 4795#define BCE_HC_CONFIG_PER_COLLECT_LIMIT (0xfL<<20) 4796#define BCE_HC_CONFIG_SB_ADDR_INC (0x7L<<24) 4797#define BCE_HC_CONFIG_SB_ADDR_INC_64B (0L<<24) 4798#define BCE_HC_CONFIG_SB_ADDR_INC_128B (1L<<24) 4799#define BCE_HC_CONFIG_SB_ADDR_INC_256B (2L<<24) 4800#define BCE_HC_CONFIG_SB_ADDR_INC_512B (3L<<24) 4801#define BCE_HC_CONFIG_SB_ADDR_INC_1024B (4L<<24) 4802#define BCE_HC_CONFIG_SB_ADDR_INC_2048B (5L<<24) 4803#define BCE_HC_CONFIG_SB_ADDR_INC_4096B (6L<<24) 4804#define BCE_HC_CONFIG_SB_ADDR_INC_8192B (7L<<24) 4805#define BCE_HC_CONFIG_GEN_STAT_AVG_INTR (1L<<29) 4806#define BCE_HC_CONFIG_UNMASK_ALL (1L<<30) 4807#define BCE_HC_CONFIG_TX_SEL (1L<<31) 4808 4809#define BCE_HC_ATTN_BITS_ENABLE 0x0000680c 4810#define BCE_HC_STATUS_ADDR_L 0x00006810 4811#define BCE_HC_STATUS_ADDR_H 0x00006814 4812#define BCE_HC_STATISTICS_ADDR_L 0x00006818 4813#define BCE_HC_STATISTICS_ADDR_H 0x0000681c 4814#define BCE_HC_TX_QUICK_CONS_TRIP 0x00006820 4815#define BCE_HC_TX_QUICK_CONS_TRIP_VALUE (0xffL<<0) 4816#define BCE_HC_TX_QUICK_CONS_TRIP_INT (0xffL<<16) 4817 4818#define BCE_HC_COMP_PROD_TRIP 0x00006824 4819#define BCE_HC_COMP_PROD_TRIP_VALUE (0xffL<<0) 4820#define BCE_HC_COMP_PROD_TRIP_INT (0xffL<<16) 4821 4822#define BCE_HC_RX_QUICK_CONS_TRIP 0x00006828 4823#define BCE_HC_RX_QUICK_CONS_TRIP_VALUE (0xffL<<0) 4824#define BCE_HC_RX_QUICK_CONS_TRIP_INT (0xffL<<16) 4825 4826#define BCE_HC_RX_TICKS 0x0000682c 4827#define BCE_HC_RX_TICKS_VALUE (0x3ffL<<0) 4828#define BCE_HC_RX_TICKS_INT (0x3ffL<<16) 4829 4830#define BCE_HC_TX_TICKS 0x00006830 4831#define BCE_HC_TX_TICKS_VALUE (0x3ffL<<0) 4832#define BCE_HC_TX_TICKS_INT (0x3ffL<<16) 4833 4834#define BCE_HC_COM_TICKS 0x00006834 4835#define BCE_HC_COM_TICKS_VALUE (0x3ffL<<0) 4836#define BCE_HC_COM_TICKS_INT (0x3ffL<<16) 4837 4838#define BCE_HC_CMD_TICKS 0x00006838 4839#define BCE_HC_CMD_TICKS_VALUE (0x3ffL<<0) 4840#define BCE_HC_CMD_TICKS_INT (0x3ffL<<16) 4841 4842#define BCE_HC_PERIODIC_TICKS 0x0000683c 4843#define BCE_HC_PERIODIC_TICKS_HC_PERIODIC_TICKS (0xffffL<<0) 4844#define BCE_HC_PERIODIC_TICKS_HC_INT_PERIODIC_TICKS (0xffffL<<16) 4845 4846#define BCE_HC_STAT_COLLECT_TICKS 0x00006840 4847#define BCE_HC_STAT_COLLECT_TICKS_HC_STAT_COLL_TICKS (0xffL<<4) 4848 4849#define BCE_HC_STATS_TICKS 0x00006844 4850#define BCE_HC_STATS_TICKS_HC_STAT_TICKS (0xffffL<<8) 4851 4852#define BCE_HC_STATS_INTERRUPT_STATUS 0x00006848 4853#define BCE_HC_STATS_INTERRUPT_STATUS_SB_STATUS (0x1ffL<<0) 4854#define BCE_HC_STATS_INTERRUPT_STATUS_INT_STATUS (0x1ffL<<16) 4855 4856#define BCE_HC_STAT_MEM_DATA 0x0000684c 4857#define BCE_HC_STAT_GEN_SEL_0 0x00006850 4858#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0 (0x7fL<<0) 4859#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT0 (0L<<0) 4860#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT1 (1L<<0) 4861#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT2 (2L<<0) 4862#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT3 (3L<<0) 4863#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT4 (4L<<0) 4864#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT5 (5L<<0) 4865#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT6 (6L<<0) 4866#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT7 (7L<<0) 4867#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT8 (8L<<0) 4868#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT9 (9L<<0) 4869#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT10 (10L<<0) 4870#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT11 (11L<<0) 4871#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT0 (12L<<0) 4872#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT1 (13L<<0) 4873#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT2 (14L<<0) 4874#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT3 (15L<<0) 4875#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT4 (16L<<0) 4876#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT5 (17L<<0) 4877#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT6 (18L<<0) 4878#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT7 (19L<<0) 4879#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT0 (20L<<0) 4880#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT1 (21L<<0) 4881#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT2 (22L<<0) 4882#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT3 (23L<<0) 4883#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT4 (24L<<0) 4884#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT5 (25L<<0) 4885#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT6 (26L<<0) 4886#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT7 (27L<<0) 4887#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT8 (28L<<0) 4888#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT9 (29L<<0) 4889#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT10 (30L<<0) 4890#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT11 (31L<<0) 4891#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT0 (32L<<0) 4892#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT1 (33L<<0) 4893#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT2 (34L<<0) 4894#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT3 (35L<<0) 4895#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT0 (36L<<0) 4896#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT1 (37L<<0) 4897#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT2 (38L<<0) 4898#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT3 (39L<<0) 4899#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT4 (40L<<0) 4900#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT5 (41L<<0) 4901#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT6 (42L<<0) 4902#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT7 (43L<<0) 4903#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT0 (44L<<0) 4904#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT1 (45L<<0) 4905#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT2 (46L<<0) 4906#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT3 (47L<<0) 4907#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT4 (48L<<0) 4908#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT5 (49L<<0) 4909#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT6 (50L<<0) 4910#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT7 (51L<<0) 4911#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_PCI_CLK_CNT (52L<<0) 4912#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CORE_CLK_CNT (53L<<0) 4913#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS (54L<<0) 4914#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN (55L<<0) 4915#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR (56L<<0) 4916#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK (59L<<0) 4917#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK (60L<<0) 4918#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK (61L<<0) 4919#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_CMD_CNT (62L<<0) 4920#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_SLOT_CNT (63L<<0) 4921#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_CMD_CNT (64L<<0) 4922#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_SLOT_CNT (65L<<0) 4923#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT (66L<<0) 4924#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT (67L<<0) 4925#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT (68L<<0) 4926#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT (69L<<0) 4927#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT (70L<<0) 4928#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT (71L<<0) 4929#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT (72L<<0) 4930#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT (73L<<0) 4931#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT (74L<<0) 4932#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT (75L<<0) 4933#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT (76L<<0) 4934#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT (77L<<0) 4935#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT (78L<<0) 4936#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT (79L<<0) 4937#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT (80L<<0) 4938#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT (81L<<0) 4939#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT (82L<<0) 4940#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT (83L<<0) 4941#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT (84L<<0) 4942#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_TRANSFERS_CNT (85L<<0) 4943#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_DELAY_PCI_CLKS_CNT (86L<<0) 4944#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_TRANSFERS_CNT (87L<<0) 4945#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_DELAY_PCI_CLKS_CNT (88L<<0) 4946#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_RETRY_AFTER_DATA_CNT (89L<<0) 4947#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_TRANSFERS_CNT (90L<<0) 4948#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_DELAY_PCI_CLKS_CNT (91L<<0) 4949#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_TRANSFERS_CNT (92L<<0) 4950#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_DELAY_PCI_CLKS_CNT (93L<<0) 4951#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_RETRY_AFTER_DATA_CNT (94L<<0) 4952#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_WR_CNT64 (95L<<0) 4953#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_RD_CNT64 (96L<<0) 4954#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_ACC_STALL_CLKS (97L<<0) 4955#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_LOCK_STALL_CLKS (98L<<0) 4956#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS_STAT (99L<<0) 4957#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS64_STAT (100L<<0) 4958#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_PCI_STALL_STAT (101L<<0) 4959#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_FTQ_ENTRY_CNT (102L<<0) 4960#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_BURST_CNT (103L<<0) 4961#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_FTQ_ENTRY_CNT (104L<<0) 4962#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_BURST_CNT (105L<<0) 4963#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_FTQ_ENTRY_CNT (106L<<0) 4964#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_BURST_CNT (107L<<0) 4965#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUP_MATCH_CNT (108L<<0) 4966#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_POLL_PASS_CNT (109L<<0) 4967#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR1_CNT (110L<<0) 4968#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR2_CNT (111L<<0) 4969#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR3_CNT (112L<<0) 4970#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR4_CNT (113L<<0) 4971#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR5_CNT (114L<<0) 4972#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT0 (115L<<0) 4973#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT1 (116L<<0) 4974#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT2 (117L<<0) 4975#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT3 (118L<<0) 4976#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT4 (119L<<0) 4977#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT5 (120L<<0) 4978#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC1_MISS (121L<<0) 4979#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC2_MISS (122L<<0) 4980#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_BURST_CNT (127L<<0) 4981#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_1 (0x7fL<<8) 4982#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_2 (0x7fL<<16) 4983#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_3 (0x7fL<<24) 4984#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_XI (0xffL<<0) 4985#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_UMP_RX_FRAME_DROP_XI (52L<<0) 4986#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S0_XI (57L<<0) 4987#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S1_XI (58L<<0) 4988#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S2_XI (85L<<0) 4989#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S3_XI (86L<<0) 4990#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S4_XI (87L<<0) 4991#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S5_XI (88L<<0) 4992#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S6_XI (89L<<0) 4993#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S7_XI (90L<<0) 4994#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S8_XI (91L<<0) 4995#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S9_XI (92L<<0) 4996#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S10_XI (93L<<0) 4997#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MQ_IDB_OFLOW_XI (94L<<0) 4998#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_BLK_RD_CNT_XI (123L<<0) 4999#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_BLK_WR_CNT_XI (124L<<0) 5000#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_HITS_XI (125L<<0) 5001#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_MISSES_XI (126L<<0) 5002#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC1_XI (128L<<0) 5003#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC1_XI (129L<<0) 5004#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC1_XI (130L<<0) 5005#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC1_XI (131L<<0) 5006#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC1_XI (132L<<0) 5007#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC1_XI (133L<<0) 5008#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC2_XI (134L<<0) 5009#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC2_XI (135L<<0) 5010#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC2_XI (136L<<0) 5011#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC2_XI (137L<<0) 5012#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC2_XI (138L<<0) 5013#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC2_XI (139L<<0) 5014#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC3_XI (140L<<0) 5015#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC3_XI (141L<<0) 5016#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC3_XI (142L<<0) 5017#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC3_XI (143L<<0) 5018#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC3_XI (144L<<0) 5019#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC3_XI (145L<<0) 5020#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC4_XI (146L<<0) 5021#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC4_XI (147L<<0) 5022#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC4_XI (148L<<0) 5023#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC4_XI (149L<<0) 5024#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC4_XI (150L<<0) 5025#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC4_XI (151L<<0) 5026#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC5_XI (152L<<0) 5027#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC5_XI (153L<<0) 5028#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC5_XI (154L<<0) 5029#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC5_XI (155L<<0) 5030#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC5_XI (156L<<0) 5031#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC5_XI (157L<<0) 5032#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC6_XI (158L<<0) 5033#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC6_XI (159L<<0) 5034#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC6_XI (160L<<0) 5035#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC6_XI (161L<<0) 5036#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC6_XI (162L<<0) 5037#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC6_XI (163L<<0) 5038#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC7_XI (164L<<0) 5039#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC7_XI (165L<<0) 5040#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC7_XI (166L<<0) 5041#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC7_XI (167L<<0) 5042#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC7_XI (168L<<0) 5043#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC7_XI (169L<<0) 5044#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC8_XI (170L<<0) 5045#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC8_XI (171L<<0) 5046#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC8_XI (172L<<0) 5047#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC8_XI (173L<<0) 5048#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC8_XI (174L<<0) 5049#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC8_XI (175L<<0) 5050#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCS_CMD_CNT_XI (176L<<0) 5051#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCS_SLOT_CNT_XI (177L<<0) 5052#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCSQ_VALID_CNT_XI (178L<<0) 5053#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_1_XI (0xffL<<8) 5054#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_2_XI (0xffL<<16) 5055#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_3_XI (0xffL<<24) 5056 5057#define BCE_HC_STAT_GEN_SEL_1 0x00006854 5058#define BCE_HC_STAT_GEN_SEL_1_GEN_SEL_4 (0x7fL<<0) 5059#define BCE_HC_STAT_GEN_SEL_1_GEN_SEL_5 (0x7fL<<8) 5060#define BCE_HC_STAT_GEN_SEL_1_GEN_SEL_6 (0x7fL<<16) 5061#define BCE_HC_STAT_GEN_SEL_1_GEN_SEL_7 (0x7fL<<24) 5062#define BCE_HC_STAT_GEN_SEL_1_GEN_SEL_4_XI (0xffL<<0) 5063#define BCE_HC_STAT_GEN_SEL_1_GEN_SEL_5_XI (0xffL<<8) 5064#define BCE_HC_STAT_GEN_SEL_1_GEN_SEL_6_XI (0xffL<<16) 5065#define BCE_HC_STAT_GEN_SEL_1_GEN_SEL_7_XI (0xffL<<24) 5066 5067#define BCE_HC_STAT_GEN_SEL_2 0x00006858 5068#define BCE_HC_STAT_GEN_SEL_2_GEN_SEL_8 (0x7fL<<0) 5069#define BCE_HC_STAT_GEN_SEL_2_GEN_SEL_9 (0x7fL<<8) 5070#define BCE_HC_STAT_GEN_SEL_2_GEN_SEL_10 (0x7fL<<16) 5071#define BCE_HC_STAT_GEN_SEL_2_GEN_SEL_11 (0x7fL<<24) 5072#define BCE_HC_STAT_GEN_SEL_2_GEN_SEL_8_XI (0xffL<<0) 5073#define BCE_HC_STAT_GEN_SEL_2_GEN_SEL_9_XI (0xffL<<8) 5074#define BCE_HC_STAT_GEN_SEL_2_GEN_SEL_10_XI (0xffL<<16) 5075#define BCE_HC_STAT_GEN_SEL_2_GEN_SEL_11_XI (0xffL<<24) 5076 5077#define BCE_HC_STAT_GEN_SEL_3 0x0000685c 5078#define BCE_HC_STAT_GEN_SEL_3_GEN_SEL_12 (0x7fL<<0) 5079#define BCE_HC_STAT_GEN_SEL_3_GEN_SEL_13 (0x7fL<<8) 5080#define BCE_HC_STAT_GEN_SEL_3_GEN_SEL_14 (0x7fL<<16) 5081#define BCE_HC_STAT_GEN_SEL_3_GEN_SEL_15 (0x7fL<<24) 5082#define BCE_HC_STAT_GEN_SEL_3_GEN_SEL_12_XI (0xffL<<0) 5083#define BCE_HC_STAT_GEN_SEL_3_GEN_SEL_13_XI (0xffL<<8) 5084#define BCE_HC_STAT_GEN_SEL_3_GEN_SEL_14_XI (0xffL<<16) 5085#define BCE_HC_STAT_GEN_SEL_3_GEN_SEL_15_XI (0xffL<<24) 5086 5087#define BCE_HC_STAT_GEN_STAT0 0x00006888 5088#define BCE_HC_STAT_GEN_STAT1 0x0000688c 5089#define BCE_HC_STAT_GEN_STAT2 0x00006890 5090#define BCE_HC_STAT_GEN_STAT3 0x00006894 5091#define BCE_HC_STAT_GEN_STAT4 0x00006898 5092#define BCE_HC_STAT_GEN_STAT5 0x0000689c 5093#define BCE_HC_STAT_GEN_STAT6 0x000068a0 5094#define BCE_HC_STAT_GEN_STAT7 0x000068a4 5095#define BCE_HC_STAT_GEN_STAT8 0x000068a8 5096#define BCE_HC_STAT_GEN_STAT9 0x000068ac 5097#define BCE_HC_STAT_GEN_STAT10 0x000068b0 5098#define BCE_HC_STAT_GEN_STAT11 0x000068b4 5099#define BCE_HC_STAT_GEN_STAT12 0x000068b8 5100#define BCE_HC_STAT_GEN_STAT13 0x000068bc 5101#define BCE_HC_STAT_GEN_STAT14 0x000068c0 5102#define BCE_HC_STAT_GEN_STAT15 0x000068c4 5103#define BCE_HC_STAT_GEN_STAT_AC0 0x000068c8 5104#define BCE_HC_STAT_GEN_STAT_AC1 0x000068cc 5105#define BCE_HC_STAT_GEN_STAT_AC2 0x000068d0 5106#define BCE_HC_STAT_GEN_STAT_AC3 0x000068d4 5107#define BCE_HC_STAT_GEN_STAT_AC4 0x000068d8 5108#define BCE_HC_STAT_GEN_STAT_AC5 0x000068dc 5109#define BCE_HC_STAT_GEN_STAT_AC6 0x000068e0 5110#define BCE_HC_STAT_GEN_STAT_AC7 0x000068e4 5111#define BCE_HC_STAT_GEN_STAT_AC8 0x000068e8 5112#define BCE_HC_STAT_GEN_STAT_AC9 0x000068ec 5113#define BCE_HC_STAT_GEN_STAT_AC10 0x000068f0 5114#define BCE_HC_STAT_GEN_STAT_AC11 0x000068f4 5115#define BCE_HC_STAT_GEN_STAT_AC12 0x000068f8 5116#define BCE_HC_STAT_GEN_STAT_AC13 0x000068fc 5117#define BCE_HC_STAT_GEN_STAT_AC14 0x00006900 5118#define BCE_HC_STAT_GEN_STAT_AC15 0x00006904 5119#define BCE_HC_STAT_GEN_STAT_AC 0x000068c8 5120#define BCE_HC_VIS 0x00006908 5121#define BCE_HC_VIS_STAT_BUILD_STATE (0xfL<<0) 5122#define BCE_HC_VIS_STAT_BUILD_STATE_IDLE (0L<<0) 5123#define BCE_HC_VIS_STAT_BUILD_STATE_START (1L<<0) 5124#define BCE_HC_VIS_STAT_BUILD_STATE_REQUEST (2L<<0) 5125#define BCE_HC_VIS_STAT_BUILD_STATE_UPDATE64 (3L<<0) 5126#define BCE_HC_VIS_STAT_BUILD_STATE_UPDATE32 (4L<<0) 5127#define BCE_HC_VIS_STAT_BUILD_STATE_UPDATE_DONE (5L<<0) 5128#define BCE_HC_VIS_STAT_BUILD_STATE_DMA (6L<<0) 5129#define BCE_HC_VIS_STAT_BUILD_STATE_MSI_CONTROL (7L<<0) 5130#define BCE_HC_VIS_STAT_BUILD_STATE_MSI_LOW (8L<<0) 5131#define BCE_HC_VIS_STAT_BUILD_STATE_MSI_HIGH (9L<<0) 5132#define BCE_HC_VIS_STAT_BUILD_STATE_MSI_DATA (10L<<0) 5133#define BCE_HC_VIS_DMA_STAT_STATE (0xfL<<8) 5134#define BCE_HC_VIS_DMA_STAT_STATE_IDLE (0L<<8) 5135#define BCE_HC_VIS_DMA_STAT_STATE_STATUS_PARAM (1L<<8) 5136#define BCE_HC_VIS_DMA_STAT_STATE_STATUS_DMA (2L<<8) 5137#define BCE_HC_VIS_DMA_STAT_STATE_WRITE_COMP (3L<<8) 5138#define BCE_HC_VIS_DMA_STAT_STATE_COMP (4L<<8) 5139#define BCE_HC_VIS_DMA_STAT_STATE_STATISTIC_PARAM (5L<<8) 5140#define BCE_HC_VIS_DMA_STAT_STATE_STATISTIC_DMA (6L<<8) 5141#define BCE_HC_VIS_DMA_STAT_STATE_WRITE_COMP_1 (7L<<8) 5142#define BCE_HC_VIS_DMA_STAT_STATE_WRITE_COMP_2 (8L<<8) 5143#define BCE_HC_VIS_DMA_STAT_STATE_WAIT (9L<<8) 5144#define BCE_HC_VIS_DMA_STAT_STATE_ABORT (15L<<8) 5145#define BCE_HC_VIS_DMA_MSI_STATE (0x7L<<12) 5146#define BCE_HC_VIS_STATISTIC_DMA_EN_STATE (0x3L<<15) 5147#define BCE_HC_VIS_STATISTIC_DMA_EN_STATE_IDLE (0L<<15) 5148#define BCE_HC_VIS_STATISTIC_DMA_EN_STATE_COUNT (1L<<15) 5149#define BCE_HC_VIS_STATISTIC_DMA_EN_STATE_START (2L<<15) 5150 5151#define BCE_HC_VIS_1 0x0000690c 5152#define BCE_HC_VIS_1_HW_INTACK_STATE (1L<<4) 5153#define BCE_HC_VIS_1_HW_INTACK_STATE_IDLE (0L<<4) 5154#define BCE_HC_VIS_1_HW_INTACK_STATE_COUNT (1L<<4) 5155#define BCE_HC_VIS_1_SW_INTACK_STATE (1L<<5) 5156#define BCE_HC_VIS_1_SW_INTACK_STATE_IDLE (0L<<5) 5157#define BCE_HC_VIS_1_SW_INTACK_STATE_COUNT (1L<<5) 5158#define BCE_HC_VIS_1_DURING_SW_INTACK_STATE (1L<<6) 5159#define BCE_HC_VIS_1_DURING_SW_INTACK_STATE_IDLE (0L<<6) 5160#define BCE_HC_VIS_1_DURING_SW_INTACK_STATE_COUNT (1L<<6) 5161#define BCE_HC_VIS_1_MAILBOX_COUNT_STATE (1L<<7) 5162#define BCE_HC_VIS_1_MAILBOX_COUNT_STATE_IDLE (0L<<7) 5163#define BCE_HC_VIS_1_MAILBOX_COUNT_STATE_COUNT (1L<<7) 5164#define BCE_HC_VIS_1_RAM_RD_ARB_STATE (0xfL<<17) 5165#define BCE_HC_VIS_1_RAM_RD_ARB_STATE_IDLE (0L<<17) 5166#define BCE_HC_VIS_1_RAM_RD_ARB_STATE_DMA (1L<<17) 5167#define BCE_HC_VIS_1_RAM_RD_ARB_STATE_UPDATE (2L<<17) 5168#define BCE_HC_VIS_1_RAM_RD_ARB_STATE_ASSIGN (3L<<17) 5169#define BCE_HC_VIS_1_RAM_RD_ARB_STATE_WAIT (4L<<17) 5170#define BCE_HC_VIS_1_RAM_RD_ARB_STATE_REG_UPDATE (5L<<17) 5171#define BCE_HC_VIS_1_RAM_RD_ARB_STATE_REG_ASSIGN (6L<<17) 5172#define BCE_HC_VIS_1_RAM_RD_ARB_STATE_REG_WAIT (7L<<17) 5173#define BCE_HC_VIS_1_RAM_WR_ARB_STATE (0x3L<<21) 5174#define BCE_HC_VIS_1_RAM_WR_ARB_STATE_NORMAL (0L<<21) 5175#define BCE_HC_VIS_1_RAM_WR_ARB_STATE_CLEAR (1L<<21) 5176#define BCE_HC_VIS_1_INT_GEN_STATE (1L<<23) 5177#define BCE_HC_VIS_1_INT_GEN_STATE_DLE (0L<<23) 5178#define BCE_HC_VIS_1_INT_GEN_STATE_NTERRUPT (1L<<23) 5179#define BCE_HC_VIS_1_STAT_CHAN_ID (0x7L<<24) 5180#define BCE_HC_VIS_1_INT_B (1L<<27) 5181 5182#define BCE_HC_DEBUG_VECT_PEEK 0x00006910 5183#define BCE_HC_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) 5184#define BCE_HC_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) 5185#define BCE_HC_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) 5186#define BCE_HC_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) 5187#define BCE_HC_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) 5188#define BCE_HC_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) 5189 5190#define BCE_HC_COALESCE_NOW 0x00006914 5191#define BCE_HC_COALESCE_NOW_COAL_NOW (0x1ffL<<1) 5192#define BCE_HC_COALESCE_NOW_COAL_NOW_WO_INT (0x1ffL<<11) 5193#define BCE_HC_COALESCE_NOW_COAL_ON_NXT_EVENT (0x1ffL<<21) 5194 5195#define BCE_HC_MSIX_BIT_VECTOR 0x00006918 5196#define BCE_HC_MSIX_BIT_VECTOR_VAL (0x1ffL<<0) 5197 5198#define BCE_HC_SB_CONFIG_1 0x00006a00 5199#define BCE_HC_SB_CONFIG_1_RX_TMR_MODE (1L<<1) 5200#define BCE_HC_SB_CONFIG_1_TX_TMR_MODE (1L<<2) 5201#define BCE_HC_SB_CONFIG_1_COM_TMR_MODE (1L<<3) 5202#define BCE_HC_SB_CONFIG_1_CMD_TMR_MODE (1L<<4) 5203#define BCE_HC_SB_CONFIG_1_PER_MODE (1L<<16) 5204#define BCE_HC_SB_CONFIG_1_ONE_SHOT (1L<<17) 5205#define BCE_HC_SB_CONFIG_1_USE_INT_PARAM (1L<<18) 5206#define BCE_HC_SB_CONFIG_1_PER_COLLECT_LIMIT (0xfL<<20) 5207 5208#define BCE_HC_TX_QUICK_CONS_TRIP_1 0x00006a04 5209#define BCE_HC_TX_QUICK_CONS_TRIP_1_VALUE (0xffL<<0) 5210#define BCE_HC_TX_QUICK_CONS_TRIP_1_INT (0xffL<<16) 5211 5212#define BCE_HC_COMP_PROD_TRIP_1 0x00006a08 5213#define BCE_HC_COMP_PROD_TRIP_1_VALUE (0xffL<<0) 5214#define BCE_HC_COMP_PROD_TRIP_1_INT (0xffL<<16) 5215 5216#define BCE_HC_RX_QUICK_CONS_TRIP_1 0x00006a0c 5217#define BCE_HC_RX_QUICK_CONS_TRIP_1_VALUE (0xffL<<0) 5218#define BCE_HC_RX_QUICK_CONS_TRIP_1_INT (0xffL<<16) 5219 5220#define BCE_HC_RX_TICKS_1 0x00006a10 5221#define BCE_HC_RX_TICKS_1_VALUE (0x3ffL<<0) 5222#define BCE_HC_RX_TICKS_1_INT (0x3ffL<<16) 5223 5224#define BCE_HC_TX_TICKS_1 0x00006a14 5225#define BCE_HC_TX_TICKS_1_VALUE (0x3ffL<<0) 5226#define BCE_HC_TX_TICKS_1_INT (0x3ffL<<16) 5227 5228#define BCE_HC_COM_TICKS_1 0x00006a18 5229#define BCE_HC_COM_TICKS_1_VALUE (0x3ffL<<0) 5230#define BCE_HC_COM_TICKS_1_INT (0x3ffL<<16) 5231 5232#define BCE_HC_CMD_TICKS_1 0x00006a1c 5233#define BCE_HC_CMD_TICKS_1_VALUE (0x3ffL<<0) 5234#define BCE_HC_CMD_TICKS_1_INT (0x3ffL<<16) 5235 5236#define BCE_HC_PERIODIC_TICKS_1 0x00006a20 5237#define BCE_HC_PERIODIC_TICKS_1_HC_PERIODIC_TICKS (0xffffL<<0) 5238#define BCE_HC_PERIODIC_TICKS_1_HC_INT_PERIODIC_TICKS (0xffffL<<16) 5239 5240#define BCE_HC_SB_CONFIG_2 0x00006a24 5241#define BCE_HC_SB_CONFIG_2_RX_TMR_MODE (1L<<1) 5242#define BCE_HC_SB_CONFIG_2_TX_TMR_MODE (1L<<2) 5243#define BCE_HC_SB_CONFIG_2_COM_TMR_MODE (1L<<3) 5244#define BCE_HC_SB_CONFIG_2_CMD_TMR_MODE (1L<<4) 5245#define BCE_HC_SB_CONFIG_2_PER_MODE (1L<<16) 5246#define BCE_HC_SB_CONFIG_2_ONE_SHOT (1L<<17) 5247#define BCE_HC_SB_CONFIG_2_USE_INT_PARAM (1L<<18) 5248#define BCE_HC_SB_CONFIG_2_PER_COLLECT_LIMIT (0xfL<<20) 5249 5250#define BCE_HC_TX_QUICK_CONS_TRIP_2 0x00006a28 5251#define BCE_HC_TX_QUICK_CONS_TRIP_2_VALUE (0xffL<<0) 5252#define BCE_HC_TX_QUICK_CONS_TRIP_2_INT (0xffL<<16) 5253 5254#define BCE_HC_COMP_PROD_TRIP_2 0x00006a2c 5255#define BCE_HC_COMP_PROD_TRIP_2_VALUE (0xffL<<0) 5256#define BCE_HC_COMP_PROD_TRIP_2_INT (0xffL<<16) 5257 5258#define BCE_HC_RX_QUICK_CONS_TRIP_2 0x00006a30 5259#define BCE_HC_RX_QUICK_CONS_TRIP_2_VALUE (0xffL<<0) 5260#define BCE_HC_RX_QUICK_CONS_TRIP_2_INT (0xffL<<16) 5261 5262#define BCE_HC_RX_TICKS_2 0x00006a34 5263#define BCE_HC_RX_TICKS_2_VALUE (0x3ffL<<0) 5264#define BCE_HC_RX_TICKS_2_INT (0x3ffL<<16) 5265 5266#define BCE_HC_TX_TICKS_2 0x00006a38 5267#define BCE_HC_TX_TICKS_2_VALUE (0x3ffL<<0) 5268#define BCE_HC_TX_TICKS_2_INT (0x3ffL<<16) 5269 5270#define BCE_HC_COM_TICKS_2 0x00006a3c 5271#define BCE_HC_COM_TICKS_2_VALUE (0x3ffL<<0) 5272#define BCE_HC_COM_TICKS_2_INT (0x3ffL<<16) 5273 5274#define BCE_HC_CMD_TICKS_2 0x00006a40 5275#define BCE_HC_CMD_TICKS_2_VALUE (0x3ffL<<0) 5276#define BCE_HC_CMD_TICKS_2_INT (0x3ffL<<16) 5277 5278#define BCE_HC_PERIODIC_TICKS_2 0x00006a44 5279#define BCE_HC_PERIODIC_TICKS_2_HC_PERIODIC_TICKS (0xffffL<<0) 5280#define BCE_HC_PERIODIC_TICKS_2_HC_INT_PERIODIC_TICKS (0xffffL<<16) 5281 5282#define BCE_HC_SB_CONFIG_3 0x00006a48 5283#define BCE_HC_SB_CONFIG_3_RX_TMR_MODE (1L<<1) 5284#define BCE_HC_SB_CONFIG_3_TX_TMR_MODE (1L<<2) 5285#define BCE_HC_SB_CONFIG_3_COM_TMR_MODE (1L<<3) 5286#define BCE_HC_SB_CONFIG_3_CMD_TMR_MODE (1L<<4) 5287#define BCE_HC_SB_CONFIG_3_PER_MODE (1L<<16) 5288#define BCE_HC_SB_CONFIG_3_ONE_SHOT (1L<<17) 5289#define BCE_HC_SB_CONFIG_3_USE_INT_PARAM (1L<<18) 5290#define BCE_HC_SB_CONFIG_3_PER_COLLECT_LIMIT (0xfL<<20) 5291 5292#define BCE_HC_TX_QUICK_CONS_TRIP_3 0x00006a4c 5293#define BCE_HC_TX_QUICK_CONS_TRIP_3_VALUE (0xffL<<0) 5294#define BCE_HC_TX_QUICK_CONS_TRIP_3_INT (0xffL<<16) 5295 5296#define BCE_HC_COMP_PROD_TRIP_3 0x00006a50 5297#define BCE_HC_COMP_PROD_TRIP_3_VALUE (0xffL<<0) 5298#define BCE_HC_COMP_PROD_TRIP_3_INT (0xffL<<16) 5299 5300#define BCE_HC_RX_QUICK_CONS_TRIP_3 0x00006a54 5301#define BCE_HC_RX_QUICK_CONS_TRIP_3_VALUE (0xffL<<0) 5302#define BCE_HC_RX_QUICK_CONS_TRIP_3_INT (0xffL<<16) 5303 5304#define BCE_HC_RX_TICKS_3 0x00006a58 5305#define BCE_HC_RX_TICKS_3_VALUE (0x3ffL<<0) 5306#define BCE_HC_RX_TICKS_3_INT (0x3ffL<<16) 5307 5308#define BCE_HC_TX_TICKS_3 0x00006a5c 5309#define BCE_HC_TX_TICKS_3_VALUE (0x3ffL<<0) 5310#define BCE_HC_TX_TICKS_3_INT (0x3ffL<<16) 5311 5312#define BCE_HC_COM_TICKS_3 0x00006a60 5313#define BCE_HC_COM_TICKS_3_VALUE (0x3ffL<<0) 5314#define BCE_HC_COM_TICKS_3_INT (0x3ffL<<16) 5315 5316#define BCE_HC_CMD_TICKS_3 0x00006a64 5317#define BCE_HC_CMD_TICKS_3_VALUE (0x3ffL<<0) 5318#define BCE_HC_CMD_TICKS_3_INT (0x3ffL<<16) 5319 5320#define BCE_HC_PERIODIC_TICKS_3 0x00006a68 5321#define BCE_HC_PERIODIC_TICKS_3_HC_PERIODIC_TICKS (0xffffL<<0) 5322#define BCE_HC_PERIODIC_TICKS_3_HC_INT_PERIODIC_TICKS (0xffffL<<16) 5323 5324#define BCE_HC_SB_CONFIG_4 0x00006a6c 5325#define BCE_HC_SB_CONFIG_4_RX_TMR_MODE (1L<<1) 5326#define BCE_HC_SB_CONFIG_4_TX_TMR_MODE (1L<<2) 5327#define BCE_HC_SB_CONFIG_4_COM_TMR_MODE (1L<<3) 5328#define BCE_HC_SB_CONFIG_4_CMD_TMR_MODE (1L<<4) 5329#define BCE_HC_SB_CONFIG_4_PER_MODE (1L<<16) 5330#define BCE_HC_SB_CONFIG_4_ONE_SHOT (1L<<17) 5331#define BCE_HC_SB_CONFIG_4_USE_INT_PARAM (1L<<18) 5332#define BCE_HC_SB_CONFIG_4_PER_COLLECT_LIMIT (0xfL<<20) 5333 5334#define BCE_HC_TX_QUICK_CONS_TRIP_4 0x00006a70 5335#define BCE_HC_TX_QUICK_CONS_TRIP_4_VALUE (0xffL<<0) 5336#define BCE_HC_TX_QUICK_CONS_TRIP_4_INT (0xffL<<16) 5337 5338#define BCE_HC_COMP_PROD_TRIP_4 0x00006a74 5339#define BCE_HC_COMP_PROD_TRIP_4_VALUE (0xffL<<0) 5340#define BCE_HC_COMP_PROD_TRIP_4_INT (0xffL<<16) 5341 5342#define BCE_HC_RX_QUICK_CONS_TRIP_4 0x00006a78 5343#define BCE_HC_RX_QUICK_CONS_TRIP_4_VALUE (0xffL<<0) 5344#define BCE_HC_RX_QUICK_CONS_TRIP_4_INT (0xffL<<16) 5345 5346#define BCE_HC_RX_TICKS_4 0x00006a7c 5347#define BCE_HC_RX_TICKS_4_VALUE (0x3ffL<<0) 5348#define BCE_HC_RX_TICKS_4_INT (0x3ffL<<16) 5349 5350#define BCE_HC_TX_TICKS_4 0x00006a80 5351#define BCE_HC_TX_TICKS_4_VALUE (0x3ffL<<0) 5352#define BCE_HC_TX_TICKS_4_INT (0x3ffL<<16) 5353 5354#define BCE_HC_COM_TICKS_4 0x00006a84 5355#define BCE_HC_COM_TICKS_4_VALUE (0x3ffL<<0) 5356#define BCE_HC_COM_TICKS_4_INT (0x3ffL<<16) 5357 5358#define BCE_HC_CMD_TICKS_4 0x00006a88 5359#define BCE_HC_CMD_TICKS_4_VALUE (0x3ffL<<0) 5360#define BCE_HC_CMD_TICKS_4_INT (0x3ffL<<16) 5361 5362#define BCE_HC_PERIODIC_TICKS_4 0x00006a8c 5363#define BCE_HC_PERIODIC_TICKS_4_HC_PERIODIC_TICKS (0xffffL<<0) 5364#define BCE_HC_PERIODIC_TICKS_4_HC_INT_PERIODIC_TICKS (0xffffL<<16) 5365 5366#define BCE_HC_SB_CONFIG_5 0x00006a90 5367#define BCE_HC_SB_CONFIG_5_RX_TMR_MODE (1L<<1) 5368#define BCE_HC_SB_CONFIG_5_TX_TMR_MODE (1L<<2) 5369#define BCE_HC_SB_CONFIG_5_COM_TMR_MODE (1L<<3) 5370#define BCE_HC_SB_CONFIG_5_CMD_TMR_MODE (1L<<4) 5371#define BCE_HC_SB_CONFIG_5_PER_MODE (1L<<16) 5372#define BCE_HC_SB_CONFIG_5_ONE_SHOT (1L<<17) 5373#define BCE_HC_SB_CONFIG_5_USE_INT_PARAM (1L<<18) 5374#define BCE_HC_SB_CONFIG_5_PER_COLLECT_LIMIT (0xfL<<20) 5375 5376#define BCE_HC_TX_QUICK_CONS_TRIP_5 0x00006a94 5377#define BCE_HC_TX_QUICK_CONS_TRIP_5_VALUE (0xffL<<0) 5378#define BCE_HC_TX_QUICK_CONS_TRIP_5_INT (0xffL<<16) 5379 5380#define BCE_HC_COMP_PROD_TRIP_5 0x00006a98 5381#define BCE_HC_COMP_PROD_TRIP_5_VALUE (0xffL<<0) 5382#define BCE_HC_COMP_PROD_TRIP_5_INT (0xffL<<16) 5383 5384#define BCE_HC_RX_QUICK_CONS_TRIP_5 0x00006a9c 5385#define BCE_HC_RX_QUICK_CONS_TRIP_5_VALUE (0xffL<<0) 5386#define BCE_HC_RX_QUICK_CONS_TRIP_5_INT (0xffL<<16) 5387 5388#define BCE_HC_RX_TICKS_5 0x00006aa0 5389#define BCE_HC_RX_TICKS_5_VALUE (0x3ffL<<0) 5390#define BCE_HC_RX_TICKS_5_INT (0x3ffL<<16) 5391 5392#define BCE_HC_TX_TICKS_5 0x00006aa4 5393#define BCE_HC_TX_TICKS_5_VALUE (0x3ffL<<0) 5394#define BCE_HC_TX_TICKS_5_INT (0x3ffL<<16) 5395 5396#define BCE_HC_COM_TICKS_5 0x00006aa8 5397#define BCE_HC_COM_TICKS_5_VALUE (0x3ffL<<0) 5398#define BCE_HC_COM_TICKS_5_INT (0x3ffL<<16) 5399 5400#define BCE_HC_CMD_TICKS_5 0x00006aac 5401#define BCE_HC_CMD_TICKS_5_VALUE (0x3ffL<<0) 5402#define BCE_HC_CMD_TICKS_5_INT (0x3ffL<<16) 5403 5404#define BCE_HC_PERIODIC_TICKS_5 0x00006ab0 5405#define BCE_HC_PERIODIC_TICKS_5_HC_PERIODIC_TICKS (0xffffL<<0) 5406#define BCE_HC_PERIODIC_TICKS_5_HC_INT_PERIODIC_TICKS (0xffffL<<16) 5407 5408#define BCE_HC_SB_CONFIG_6 0x00006ab4 5409#define BCE_HC_SB_CONFIG_6_RX_TMR_MODE (1L<<1) 5410#define BCE_HC_SB_CONFIG_6_TX_TMR_MODE (1L<<2) 5411#define BCE_HC_SB_CONFIG_6_COM_TMR_MODE (1L<<3) 5412#define BCE_HC_SB_CONFIG_6_CMD_TMR_MODE (1L<<4) 5413#define BCE_HC_SB_CONFIG_6_PER_MODE (1L<<16) 5414#define BCE_HC_SB_CONFIG_6_ONE_SHOT (1L<<17) 5415#define BCE_HC_SB_CONFIG_6_USE_INT_PARAM (1L<<18) 5416#define BCE_HC_SB_CONFIG_6_PER_COLLECT_LIMIT (0xfL<<20) 5417 5418#define BCE_HC_TX_QUICK_CONS_TRIP_6 0x00006ab8 5419#define BCE_HC_TX_QUICK_CONS_TRIP_6_VALUE (0xffL<<0) 5420#define BCE_HC_TX_QUICK_CONS_TRIP_6_INT (0xffL<<16) 5421 5422#define BCE_HC_COMP_PROD_TRIP_6 0x00006abc 5423#define BCE_HC_COMP_PROD_TRIP_6_VALUE (0xffL<<0) 5424#define BCE_HC_COMP_PROD_TRIP_6_INT (0xffL<<16) 5425 5426#define BCE_HC_RX_QUICK_CONS_TRIP_6 0x00006ac0 5427#define BCE_HC_RX_QUICK_CONS_TRIP_6_VALUE (0xffL<<0) 5428#define BCE_HC_RX_QUICK_CONS_TRIP_6_INT (0xffL<<16) 5429 5430#define BCE_HC_RX_TICKS_6 0x00006ac4 5431#define BCE_HC_RX_TICKS_6_VALUE (0x3ffL<<0) 5432#define BCE_HC_RX_TICKS_6_INT (0x3ffL<<16) 5433 5434#define BCE_HC_TX_TICKS_6 0x00006ac8 5435#define BCE_HC_TX_TICKS_6_VALUE (0x3ffL<<0) 5436#define BCE_HC_TX_TICKS_6_INT (0x3ffL<<16) 5437 5438#define BCE_HC_COM_TICKS_6 0x00006acc 5439#define BCE_HC_COM_TICKS_6_VALUE (0x3ffL<<0) 5440#define BCE_HC_COM_TICKS_6_INT (0x3ffL<<16) 5441 5442#define BCE_HC_CMD_TICKS_6 0x00006ad0 5443#define BCE_HC_CMD_TICKS_6_VALUE (0x3ffL<<0) 5444#define BCE_HC_CMD_TICKS_6_INT (0x3ffL<<16) 5445 5446#define BCE_HC_PERIODIC_TICKS_6 0x00006ad4 5447#define BCE_HC_PERIODIC_TICKS_6_HC_PERIODIC_TICKS (0xffffL<<0) 5448#define BCE_HC_PERIODIC_TICKS_6_HC_INT_PERIODIC_TICKS (0xffffL<<16) 5449 5450#define BCE_HC_SB_CONFIG_7 0x00006ad8 5451#define BCE_HC_SB_CONFIG_7_RX_TMR_MODE (1L<<1) 5452#define BCE_HC_SB_CONFIG_7_TX_TMR_MODE (1L<<2) 5453#define BCE_HC_SB_CONFIG_7_COM_TMR_MODE (1L<<3) 5454#define BCE_HC_SB_CONFIG_7_CMD_TMR_MODE (1L<<4) 5455#define BCE_HC_SB_CONFIG_7_PER_MODE (1L<<16) 5456#define BCE_HC_SB_CONFIG_7_ONE_SHOT (1L<<17) 5457#define BCE_HC_SB_CONFIG_7_USE_INT_PARAM (1L<<18) 5458#define BCE_HC_SB_CONFIG_7_PER_COLLECT_LIMIT (0xfL<<20) 5459 5460#define BCE_HC_TX_QUICK_CONS_TRIP_7 0x00006adc 5461#define BCE_HC_TX_QUICK_CONS_TRIP_7_VALUE (0xffL<<0) 5462#define BCE_HC_TX_QUICK_CONS_TRIP_7_INT (0xffL<<16) 5463 5464#define BCE_HC_COMP_PROD_TRIP_7 0x00006ae0 5465#define BCE_HC_COMP_PROD_TRIP_7_VALUE (0xffL<<0) 5466#define BCE_HC_COMP_PROD_TRIP_7_INT (0xffL<<16) 5467 5468#define BCE_HC_RX_QUICK_CONS_TRIP_7 0x00006ae4 5469#define BCE_HC_RX_QUICK_CONS_TRIP_7_VALUE (0xffL<<0) 5470#define BCE_HC_RX_QUICK_CONS_TRIP_7_INT (0xffL<<16) 5471 5472#define BCE_HC_RX_TICKS_7 0x00006ae8 5473#define BCE_HC_RX_TICKS_7_VALUE (0x3ffL<<0) 5474#define BCE_HC_RX_TICKS_7_INT (0x3ffL<<16) 5475 5476#define BCE_HC_TX_TICKS_7 0x00006aec 5477#define BCE_HC_TX_TICKS_7_VALUE (0x3ffL<<0) 5478#define BCE_HC_TX_TICKS_7_INT (0x3ffL<<16) 5479 5480#define BCE_HC_COM_TICKS_7 0x00006af0 5481#define BCE_HC_COM_TICKS_7_VALUE (0x3ffL<<0) 5482#define BCE_HC_COM_TICKS_7_INT (0x3ffL<<16) 5483 5484#define BCE_HC_CMD_TICKS_7 0x00006af4 5485#define BCE_HC_CMD_TICKS_7_VALUE (0x3ffL<<0) 5486#define BCE_HC_CMD_TICKS_7_INT (0x3ffL<<16) 5487 5488#define BCE_HC_PERIODIC_TICKS_7 0x00006af8 5489#define BCE_HC_PERIODIC_TICKS_7_HC_PERIODIC_TICKS (0xffffL<<0) 5490#define BCE_HC_PERIODIC_TICKS_7_HC_INT_PERIODIC_TICKS (0xffffL<<16) 5491 5492#define BCE_HC_SB_CONFIG_8 0x00006afc 5493#define BCE_HC_SB_CONFIG_8_RX_TMR_MODE (1L<<1) 5494#define BCE_HC_SB_CONFIG_8_TX_TMR_MODE (1L<<2) 5495#define BCE_HC_SB_CONFIG_8_COM_TMR_MODE (1L<<3) 5496#define BCE_HC_SB_CONFIG_8_CMD_TMR_MODE (1L<<4) 5497#define BCE_HC_SB_CONFIG_8_PER_MODE (1L<<16) 5498#define BCE_HC_SB_CONFIG_8_ONE_SHOT (1L<<17) 5499#define BCE_HC_SB_CONFIG_8_USE_INT_PARAM (1L<<18) 5500#define BCE_HC_SB_CONFIG_8_PER_COLLECT_LIMIT (0xfL<<20) 5501 5502#define BCE_HC_TX_QUICK_CONS_TRIP_8 0x00006b00 5503#define BCE_HC_TX_QUICK_CONS_TRIP_8_VALUE (0xffL<<0) 5504#define BCE_HC_TX_QUICK_CONS_TRIP_8_INT (0xffL<<16) 5505 5506#define BCE_HC_COMP_PROD_TRIP_8 0x00006b04 5507#define BCE_HC_COMP_PROD_TRIP_8_VALUE (0xffL<<0) 5508#define BCE_HC_COMP_PROD_TRIP_8_INT (0xffL<<16) 5509 5510#define BCE_HC_RX_QUICK_CONS_TRIP_8 0x00006b08 5511#define BCE_HC_RX_QUICK_CONS_TRIP_8_VALUE (0xffL<<0) 5512#define BCE_HC_RX_QUICK_CONS_TRIP_8_INT (0xffL<<16) 5513 5514#define BCE_HC_RX_TICKS_8 0x00006b0c 5515#define BCE_HC_RX_TICKS_8_VALUE (0x3ffL<<0) 5516#define BCE_HC_RX_TICKS_8_INT (0x3ffL<<16) 5517 5518#define BCE_HC_TX_TICKS_8 0x00006b10 5519#define BCE_HC_TX_TICKS_8_VALUE (0x3ffL<<0) 5520#define BCE_HC_TX_TICKS_8_INT (0x3ffL<<16) 5521 5522#define BCE_HC_COM_TICKS_8 0x00006b14 5523#define BCE_HC_COM_TICKS_8_VALUE (0x3ffL<<0) 5524#define BCE_HC_COM_TICKS_8_INT (0x3ffL<<16) 5525 5526#define BCE_HC_CMD_TICKS_8 0x00006b18 5527#define BCE_HC_CMD_TICKS_8_VALUE (0x3ffL<<0) 5528#define BCE_HC_CMD_TICKS_8_INT (0x3ffL<<16) 5529 5530#define BCE_HC_PERIODIC_TICKS_8 0x00006b1c 5531#define BCE_HC_PERIODIC_TICKS_8_HC_PERIODIC_TICKS (0xffffL<<0) 5532#define BCE_HC_PERIODIC_TICKS_8_HC_INT_PERIODIC_TICKS (0xffffL<<16) 5533 5534 5535/* 5536 * txp_reg definition 5537 * offset: 0x40000 5538 */ 5539#define BCE_TXP_CPU_MODE 0x00045000 5540#define BCE_TXP_CPU_MODE_LOCAL_RST (1L<<0) 5541#define BCE_TXP_CPU_MODE_STEP_ENA (1L<<1) 5542#define BCE_TXP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2) 5543#define BCE_TXP_CPU_MODE_PAGE_0_INST_ENA (1L<<3) 5544#define BCE_TXP_CPU_MODE_MSG_BIT1 (1L<<6) 5545#define BCE_TXP_CPU_MODE_INTERRUPT_ENA (1L<<7) 5546#define BCE_TXP_CPU_MODE_SOFT_HALT (1L<<10) 5547#define BCE_TXP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11) 5548#define BCE_TXP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12) 5549#define BCE_TXP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13) 5550#define BCE_TXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15) 5551 5552#define BCE_TXP_CPU_STATE 0x00045004 5553#define BCE_TXP_CPU_STATE_BREAKPOINT (1L<<0) 5554#define BCE_TXP_CPU_STATE_BAD_INST_HALTED (1L<<2) 5555#define BCE_TXP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) 5556#define BCE_TXP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) 5557#define BCE_TXP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) 5558#define BCE_TXP_CPU_STATE_BAD_pc_HALTED (1L<<6) 5559#define BCE_TXP_CPU_STATE_ALIGN_HALTED (1L<<7) 5560#define BCE_TXP_CPU_STATE_FIO_ABORT_HALTED (1L<<8) 5561#define BCE_TXP_CPU_STATE_SOFT_HALTED (1L<<10) 5562#define BCE_TXP_CPU_STATE_SPAD_UNDERFLOW (1L<<11) 5563#define BCE_TXP_CPU_STATE_INTERRRUPT (1L<<12) 5564#define BCE_TXP_CPU_STATE_DATA_ACCESS_STALL (1L<<14) 5565#define BCE_TXP_CPU_STATE_INST_FETCH_STALL (1L<<15) 5566#define BCE_TXP_CPU_STATE_BLOCKED_READ (1L<<31) 5567 5568#define BCE_TXP_CPU_EVENT_MASK 0x00045008 5569#define BCE_TXP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) 5570#define BCE_TXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2) 5571#define BCE_TXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3) 5572#define BCE_TXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4) 5573#define BCE_TXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5) 5574#define BCE_TXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6) 5575#define BCE_TXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7) 5576#define BCE_TXP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8) 5577#define BCE_TXP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10) 5578#define BCE_TXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11) 5579#define BCE_TXP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12) 5580 5581#define BCE_TXP_CPU_PROGRAM_COUNTER 0x0004501c 5582#define BCE_TXP_CPU_INSTRUCTION 0x00045020 5583#define BCE_TXP_CPU_DATA_ACCESS 0x00045024 5584#define BCE_TXP_CPU_INTERRUPT_ENABLE 0x00045028 5585#define BCE_TXP_CPU_INTERRUPT_VECTOR 0x0004502c 5586#define BCE_TXP_CPU_INTERRUPT_SAVED_PC 0x00045030 5587#define BCE_TXP_CPU_HW_BREAKPOINT 0x00045034 5588#define BCE_TXP_CPU_HW_BREAKPOINT_DISABLE (1L<<0) 5589#define BCE_TXP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2) 5590 5591#define BCE_TXP_CPU_REG_FILE 0x00045200 5592#define BCE_TXP_FTQ_DATA 0x000453c0 5593#define BCE_TXP_FTQ_CMD 0x000453f8 5594#define BCE_TXP_FTQ_CMD_OFFSET (0x3ffL<<0) 5595#define BCE_TXP_FTQ_CMD_WR_TOP (1L<<10) 5596#define BCE_TXP_FTQ_CMD_WR_TOP_0 (0L<<10) 5597#define BCE_TXP_FTQ_CMD_WR_TOP_1 (1L<<10) 5598#define BCE_TXP_FTQ_CMD_SFT_RESET (1L<<25) 5599#define BCE_TXP_FTQ_CMD_RD_DATA (1L<<26) 5600#define BCE_TXP_FTQ_CMD_ADD_INTERVEN (1L<<27) 5601#define BCE_TXP_FTQ_CMD_ADD_DATA (1L<<28) 5602#define BCE_TXP_FTQ_CMD_INTERVENE_CLR (1L<<29) 5603#define BCE_TXP_FTQ_CMD_POP (1L<<30) 5604#define BCE_TXP_FTQ_CMD_BUSY (1L<<31) 5605 5606#define BCE_TXP_FTQ_CTL 0x000453fc 5607#define BCE_TXP_FTQ_CTL_INTERVENE (1L<<0) 5608#define BCE_TXP_FTQ_CTL_OVERFLOW (1L<<1) 5609#define BCE_TXP_FTQ_CTL_FORCE_INTERVENE (1L<<2) 5610#define BCE_TXP_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 5611#define BCE_TXP_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 5612 5613#define BCE_TXP_SCRATCH 0x00060000 5614 5615 5616/* 5617 * tpat_reg definition 5618 * offset: 0x80000 5619 */ 5620#define BCE_TPAT_CPU_MODE 0x00085000 5621#define BCE_TPAT_CPU_MODE_LOCAL_RST (1L<<0) 5622#define BCE_TPAT_CPU_MODE_STEP_ENA (1L<<1) 5623#define BCE_TPAT_CPU_MODE_PAGE_0_DATA_ENA (1L<<2) 5624#define BCE_TPAT_CPU_MODE_PAGE_0_INST_ENA (1L<<3) 5625#define BCE_TPAT_CPU_MODE_MSG_BIT1 (1L<<6) 5626#define BCE_TPAT_CPU_MODE_INTERRUPT_ENA (1L<<7) 5627#define BCE_TPAT_CPU_MODE_SOFT_HALT (1L<<10) 5628#define BCE_TPAT_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11) 5629#define BCE_TPAT_CPU_MODE_BAD_INST_HALT_ENA (1L<<12) 5630#define BCE_TPAT_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13) 5631#define BCE_TPAT_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15) 5632 5633#define BCE_TPAT_CPU_STATE 0x00085004 5634#define BCE_TPAT_CPU_STATE_BREAKPOINT (1L<<0) 5635#define BCE_TPAT_CPU_STATE_BAD_INST_HALTED (1L<<2) 5636#define BCE_TPAT_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) 5637#define BCE_TPAT_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) 5638#define BCE_TPAT_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) 5639#define BCE_TPAT_CPU_STATE_BAD_pc_HALTED (1L<<6) 5640#define BCE_TPAT_CPU_STATE_ALIGN_HALTED (1L<<7) 5641#define BCE_TPAT_CPU_STATE_FIO_ABORT_HALTED (1L<<8) 5642#define BCE_TPAT_CPU_STATE_SOFT_HALTED (1L<<10) 5643#define BCE_TPAT_CPU_STATE_SPAD_UNDERFLOW (1L<<11) 5644#define BCE_TPAT_CPU_STATE_INTERRRUPT (1L<<12) 5645#define BCE_TPAT_CPU_STATE_DATA_ACCESS_STALL (1L<<14) 5646#define BCE_TPAT_CPU_STATE_INST_FETCH_STALL (1L<<15) 5647#define BCE_TPAT_CPU_STATE_BLOCKED_READ (1L<<31) 5648 5649#define BCE_TPAT_CPU_EVENT_MASK 0x00085008 5650#define BCE_TPAT_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) 5651#define BCE_TPAT_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2) 5652#define BCE_TPAT_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3) 5653#define BCE_TPAT_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4) 5654#define BCE_TPAT_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5) 5655#define BCE_TPAT_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6) 5656#define BCE_TPAT_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7) 5657#define BCE_TPAT_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8) 5658#define BCE_TPAT_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10) 5659#define BCE_TPAT_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11) 5660#define BCE_TPAT_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12) 5661 5662#define BCE_TPAT_CPU_PROGRAM_COUNTER 0x0008501c 5663#define BCE_TPAT_CPU_INSTRUCTION 0x00085020 5664#define BCE_TPAT_CPU_DATA_ACCESS 0x00085024 5665#define BCE_TPAT_CPU_INTERRUPT_ENABLE 0x00085028 5666#define BCE_TPAT_CPU_INTERRUPT_VECTOR 0x0008502c 5667#define BCE_TPAT_CPU_INTERRUPT_SAVED_PC 0x00085030 5668#define BCE_TPAT_CPU_HW_BREAKPOINT 0x00085034 5669#define BCE_TPAT_CPU_HW_BREAKPOINT_DISABLE (1L<<0) 5670#define BCE_TPAT_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2) 5671#define BCE_TPAT_CPU_REG_FILE 0x00085200 5672#define BCE_TPAT_FTQ_DATA 0x000853c0 5673#define BCE_TPAT_FTQ_CMD 0x000853f8 5674#define BCE_TPAT_FTQ_CMD_OFFSET (0x3ffL<<0) 5675#define BCE_TPAT_FTQ_CMD_WR_TOP (1L<<10) 5676#define BCE_TPAT_FTQ_CMD_WR_TOP_0 (0L<<10) 5677#define BCE_TPAT_FTQ_CMD_WR_TOP_1 (1L<<10) 5678#define BCE_TPAT_FTQ_CMD_SFT_RESET (1L<<25) 5679#define BCE_TPAT_FTQ_CMD_RD_DATA (1L<<26) 5680#define BCE_TPAT_FTQ_CMD_ADD_INTERVEN (1L<<27) 5681#define BCE_TPAT_FTQ_CMD_ADD_DATA (1L<<28) 5682#define BCE_TPAT_FTQ_CMD_INTERVENE_CLR (1L<<29) 5683#define BCE_TPAT_FTQ_CMD_POP (1L<<30) 5684#define BCE_TPAT_FTQ_CMD_BUSY (1L<<31) 5685 5686#define BCE_TPAT_FTQ_CTL 0x000853fc 5687#define BCE_TPAT_FTQ_CTL_INTERVENE (1L<<0) 5688#define BCE_TPAT_FTQ_CTL_OVERFLOW (1L<<1) 5689#define BCE_TPAT_FTQ_CTL_FORCE_INTERVENE (1L<<2) 5690#define BCE_TPAT_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 5691#define BCE_TPAT_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 5692 5693#define BCE_TPAT_SCRATCH 0x000a0000 5694 5695 5696/* 5697 * rxp_reg definition 5698 * offset: 0xc0000 5699 */ 5700#define BCE_RXP_CPU_MODE 0x000c5000 5701#define BCE_RXP_CPU_MODE_LOCAL_RST (1L<<0) 5702#define BCE_RXP_CPU_MODE_STEP_ENA (1L<<1) 5703#define BCE_RXP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2) 5704#define BCE_RXP_CPU_MODE_PAGE_0_INST_ENA (1L<<3) 5705#define BCE_RXP_CPU_MODE_MSG_BIT1 (1L<<6) 5706#define BCE_RXP_CPU_MODE_INTERRUPT_ENA (1L<<7) 5707#define BCE_RXP_CPU_MODE_SOFT_HALT (1L<<10) 5708#define BCE_RXP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11) 5709#define BCE_RXP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12) 5710#define BCE_RXP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13) 5711#define BCE_RXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15) 5712 5713#define BCE_RXP_CPU_STATE 0x000c5004 5714#define BCE_RXP_CPU_STATE_BREAKPOINT (1L<<0) 5715#define BCE_RXP_CPU_STATE_BAD_INST_HALTED (1L<<2) 5716#define BCE_RXP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) 5717#define BCE_RXP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) 5718#define BCE_RXP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) 5719#define BCE_RXP_CPU_STATE_BAD_pc_HALTED (1L<<6) 5720#define BCE_RXP_CPU_STATE_ALIGN_HALTED (1L<<7) 5721#define BCE_RXP_CPU_STATE_FIO_ABORT_HALTED (1L<<8) 5722#define BCE_RXP_CPU_STATE_SOFT_HALTED (1L<<10) 5723#define BCE_RXP_CPU_STATE_SPAD_UNDERFLOW (1L<<11) 5724#define BCE_RXP_CPU_STATE_INTERRRUPT (1L<<12) 5725#define BCE_RXP_CPU_STATE_DATA_ACCESS_STALL (1L<<14) 5726#define BCE_RXP_CPU_STATE_INST_FETCH_STALL (1L<<15) 5727#define BCE_RXP_CPU_STATE_BLOCKED_READ (1L<<31) 5728 5729#define BCE_RXP_CPU_EVENT_MASK 0x000c5008 5730#define BCE_RXP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) 5731#define BCE_RXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2) 5732#define BCE_RXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3) 5733#define BCE_RXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4) 5734#define BCE_RXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5) 5735#define BCE_RXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6) 5736#define BCE_RXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7) 5737#define BCE_RXP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8) 5738#define BCE_RXP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10) 5739#define BCE_RXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11) 5740#define BCE_RXP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12) 5741 5742#define BCE_RXP_CPU_PROGRAM_COUNTER 0x000c501c 5743#define BCE_RXP_CPU_INSTRUCTION 0x000c5020 5744#define BCE_RXP_CPU_DATA_ACCESS 0x000c5024 5745#define BCE_RXP_CPU_INTERRUPT_ENABLE 0x000c5028 5746#define BCE_RXP_CPU_INTERRUPT_VECTOR 0x000c502c 5747#define BCE_RXP_CPU_INTERRUPT_SAVED_PC 0x000c5030 5748#define BCE_RXP_CPU_HW_BREAKPOINT 0x000c5034 5749#define BCE_RXP_CPU_HW_BREAKPOINT_DISABLE (1L<<0) 5750#define BCE_RXP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2) 5751 5752#define BCE_RXP_CPU_REG_FILE 0x000c5200 5753#define BCE_RXP_CFTQ_DATA 0x000c5380 5754#define BCE_RXP_CFTQ_CMD 0x000c53b8 5755#define BCE_RXP_CFTQ_CMD_OFFSET (0x3ffL<<0) 5756#define BCE_RXP_CFTQ_CMD_WR_TOP (1L<<10) 5757#define BCE_RXP_CFTQ_CMD_WR_TOP_0 (0L<<10) 5758#define BCE_RXP_CFTQ_CMD_WR_TOP_1 (1L<<10) 5759#define BCE_RXP_CFTQ_CMD_SFT_RESET (1L<<25) 5760#define BCE_RXP_CFTQ_CMD_RD_DATA (1L<<26) 5761#define BCE_RXP_CFTQ_CMD_ADD_INTERVEN (1L<<27) 5762#define BCE_RXP_CFTQ_CMD_ADD_DATA (1L<<28) 5763#define BCE_RXP_CFTQ_CMD_INTERVENE_CLR (1L<<29) 5764#define BCE_RXP_CFTQ_CMD_POP (1L<<30) 5765#define BCE_RXP_CFTQ_CMD_BUSY (1L<<31) 5766 5767#define BCE_RXP_CFTQ_CTL 0x000c53bc 5768#define BCE_RXP_CFTQ_CTL_INTERVENE (1L<<0) 5769#define BCE_RXP_CFTQ_CTL_OVERFLOW (1L<<1) 5770#define BCE_RXP_CFTQ_CTL_FORCE_INTERVENE (1L<<2) 5771#define BCE_RXP_CFTQ_CTL_MAX_DEPTH (0x3ffL<<12) 5772#define BCE_RXP_CFTQ_CTL_CUR_DEPTH (0x3ffL<<22) 5773 5774#define BCE_RXP_FTQ_DATA 0x000c53c0 5775#define BCE_RXP_FTQ_CMD 0x000c53f8 5776#define BCE_RXP_FTQ_CMD_OFFSET (0x3ffL<<0) 5777#define BCE_RXP_FTQ_CMD_WR_TOP (1L<<10) 5778#define BCE_RXP_FTQ_CMD_WR_TOP_0 (0L<<10) 5779#define BCE_RXP_FTQ_CMD_WR_TOP_1 (1L<<10) 5780#define BCE_RXP_FTQ_CMD_SFT_RESET (1L<<25) 5781#define BCE_RXP_FTQ_CMD_RD_DATA (1L<<26) 5782#define BCE_RXP_FTQ_CMD_ADD_INTERVEN (1L<<27) 5783#define BCE_RXP_FTQ_CMD_ADD_DATA (1L<<28) 5784#define BCE_RXP_FTQ_CMD_INTERVENE_CLR (1L<<29) 5785#define BCE_RXP_FTQ_CMD_POP (1L<<30) 5786#define BCE_RXP_FTQ_CMD_BUSY (1L<<31) 5787 5788#define BCE_RXP_FTQ_CTL 0x000c53fc 5789#define BCE_RXP_FTQ_CTL_INTERVENE (1L<<0) 5790#define BCE_RXP_FTQ_CTL_OVERFLOW (1L<<1) 5791#define BCE_RXP_FTQ_CTL_FORCE_INTERVENE (1L<<2) 5792#define BCE_RXP_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 5793#define BCE_RXP_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 5794 5795#define BCE_RXP_SCRATCH 0x000e0000 5796 5797 5798/* 5799 * com_reg definition 5800 * offset: 0x100000 5801 */ 5802#define BCE_COM_CPU_MODE 0x00105000 5803#define BCE_COM_CPU_MODE_LOCAL_RST (1L<<0) 5804#define BCE_COM_CPU_MODE_STEP_ENA (1L<<1) 5805#define BCE_COM_CPU_MODE_PAGE_0_DATA_ENA (1L<<2) 5806#define BCE_COM_CPU_MODE_PAGE_0_INST_ENA (1L<<3) 5807#define BCE_COM_CPU_MODE_MSG_BIT1 (1L<<6) 5808#define BCE_COM_CPU_MODE_INTERRUPT_ENA (1L<<7) 5809#define BCE_COM_CPU_MODE_SOFT_HALT (1L<<10) 5810#define BCE_COM_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11) 5811#define BCE_COM_CPU_MODE_BAD_INST_HALT_ENA (1L<<12) 5812#define BCE_COM_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13) 5813#define BCE_COM_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15) 5814 5815#define BCE_COM_CPU_STATE 0x00105004 5816#define BCE_COM_CPU_STATE_BREAKPOINT (1L<<0) 5817#define BCE_COM_CPU_STATE_BAD_INST_HALTED (1L<<2) 5818#define BCE_COM_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) 5819#define BCE_COM_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) 5820#define BCE_COM_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) 5821#define BCE_COM_CPU_STATE_BAD_pc_HALTED (1L<<6) 5822#define BCE_COM_CPU_STATE_ALIGN_HALTED (1L<<7) 5823#define BCE_COM_CPU_STATE_FIO_ABORT_HALTED (1L<<8) 5824#define BCE_COM_CPU_STATE_SOFT_HALTED (1L<<10) 5825#define BCE_COM_CPU_STATE_SPAD_UNDERFLOW (1L<<11) 5826#define BCE_COM_CPU_STATE_INTERRRUPT (1L<<12) 5827#define BCE_COM_CPU_STATE_DATA_ACCESS_STALL (1L<<14) 5828#define BCE_COM_CPU_STATE_INST_FETCH_STALL (1L<<15) 5829#define BCE_COM_CPU_STATE_BLOCKED_READ (1L<<31) 5830 5831#define BCE_COM_CPU_EVENT_MASK 0x00105008 5832#define BCE_COM_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) 5833#define BCE_COM_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2) 5834#define BCE_COM_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3) 5835#define BCE_COM_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4) 5836#define BCE_COM_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5) 5837#define BCE_COM_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6) 5838#define BCE_COM_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7) 5839#define BCE_COM_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8) 5840#define BCE_COM_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10) 5841#define BCE_COM_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11) 5842#define BCE_COM_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12) 5843 5844#define BCE_COM_CPU_PROGRAM_COUNTER 0x0010501c 5845#define BCE_COM_CPU_INSTRUCTION 0x00105020 5846#define BCE_COM_CPU_DATA_ACCESS 0x00105024 5847#define BCE_COM_CPU_INTERRUPT_ENABLE 0x00105028 5848#define BCE_COM_CPU_INTERRUPT_VECTOR 0x0010502c 5849#define BCE_COM_CPU_INTERRUPT_SAVED_PC 0x00105030 5850#define BCE_COM_CPU_HW_BREAKPOINT 0x00105034 5851#define BCE_COM_CPU_HW_BREAKPOINT_DISABLE (1L<<0) 5852#define BCE_COM_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2) 5853 5854#define BCE_COM_CPU_REG_FILE 0x00105200 5855#define BCE_COM_COMXQ_FTQ_DATA 0x00105340 5856#define BCE_COM_COMXQ_FTQ_CMD 0x00105378 5857#define BCE_COM_COMXQ_FTQ_CMD_OFFSET (0x3ffL<<0) 5858#define BCE_COM_COMXQ_FTQ_CMD_WR_TOP (1L<<10) 5859#define BCE_COM_COMXQ_FTQ_CMD_WR_TOP_0 (0L<<10) 5860#define BCE_COM_COMXQ_FTQ_CMD_WR_TOP_1 (1L<<10) 5861#define BCE_COM_COMXQ_FTQ_CMD_SFT_RESET (1L<<25) 5862#define BCE_COM_COMXQ_FTQ_CMD_RD_DATA (1L<<26) 5863#define BCE_COM_COMXQ_FTQ_CMD_ADD_INTERVEN (1L<<27) 5864#define BCE_COM_COMXQ_FTQ_CMD_ADD_DATA (1L<<28) 5865#define BCE_COM_COMXQ_FTQ_CMD_INTERVENE_CLR (1L<<29) 5866#define BCE_COM_COMXQ_FTQ_CMD_POP (1L<<30) 5867#define BCE_COM_COMXQ_FTQ_CMD_BUSY (1L<<31) 5868 5869#define BCE_COM_COMXQ_FTQ_CTL 0x0010537c 5870#define BCE_COM_COMXQ_FTQ_CTL_INTERVENE (1L<<0) 5871#define BCE_COM_COMXQ_FTQ_CTL_OVERFLOW (1L<<1) 5872#define BCE_COM_COMXQ_FTQ_CTL_FORCE_INTERVENE (1L<<2) 5873#define BCE_COM_COMXQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 5874#define BCE_COM_COMXQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 5875 5876#define BCE_COM_COMTQ_FTQ_DATA 0x00105380 5877#define BCE_COM_COMTQ_FTQ_CMD 0x001053b8 5878#define BCE_COM_COMTQ_FTQ_CMD_OFFSET (0x3ffL<<0) 5879#define BCE_COM_COMTQ_FTQ_CMD_WR_TOP (1L<<10) 5880#define BCE_COM_COMTQ_FTQ_CMD_WR_TOP_0 (0L<<10) 5881#define BCE_COM_COMTQ_FTQ_CMD_WR_TOP_1 (1L<<10) 5882#define BCE_COM_COMTQ_FTQ_CMD_SFT_RESET (1L<<25) 5883#define BCE_COM_COMTQ_FTQ_CMD_RD_DATA (1L<<26) 5884#define BCE_COM_COMTQ_FTQ_CMD_ADD_INTERVEN (1L<<27) 5885#define BCE_COM_COMTQ_FTQ_CMD_ADD_DATA (1L<<28) 5886#define BCE_COM_COMTQ_FTQ_CMD_INTERVENE_CLR (1L<<29) 5887#define BCE_COM_COMTQ_FTQ_CMD_POP (1L<<30) 5888#define BCE_COM_COMTQ_FTQ_CMD_BUSY (1L<<31) 5889 5890#define BCE_COM_COMTQ_FTQ_CTL 0x001053bc 5891#define BCE_COM_COMTQ_FTQ_CTL_INTERVENE (1L<<0) 5892#define BCE_COM_COMTQ_FTQ_CTL_OVERFLOW (1L<<1) 5893#define BCE_COM_COMTQ_FTQ_CTL_FORCE_INTERVENE (1L<<2) 5894#define BCE_COM_COMTQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 5895#define BCE_COM_COMTQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 5896 5897#define BCE_COM_COMQ_FTQ_DATA 0x001053c0 5898#define BCE_COM_COMQ_FTQ_CMD 0x001053f8 5899#define BCE_COM_COMQ_FTQ_CMD_OFFSET (0x3ffL<<0) 5900#define BCE_COM_COMQ_FTQ_CMD_WR_TOP (1L<<10) 5901#define BCE_COM_COMQ_FTQ_CMD_WR_TOP_0 (0L<<10) 5902#define BCE_COM_COMQ_FTQ_CMD_WR_TOP_1 (1L<<10) 5903#define BCE_COM_COMQ_FTQ_CMD_SFT_RESET (1L<<25) 5904#define BCE_COM_COMQ_FTQ_CMD_RD_DATA (1L<<26) 5905#define BCE_COM_COMQ_FTQ_CMD_ADD_INTERVEN (1L<<27) 5906#define BCE_COM_COMQ_FTQ_CMD_ADD_DATA (1L<<28) 5907#define BCE_COM_COMQ_FTQ_CMD_INTERVENE_CLR (1L<<29) 5908#define BCE_COM_COMQ_FTQ_CMD_POP (1L<<30) 5909#define BCE_COM_COMQ_FTQ_CMD_BUSY (1L<<31) 5910 5911#define BCE_COM_COMQ_FTQ_CTL 0x001053fc 5912#define BCE_COM_COMQ_FTQ_CTL_INTERVENE (1L<<0) 5913#define BCE_COM_COMQ_FTQ_CTL_OVERFLOW (1L<<1) 5914#define BCE_COM_COMQ_FTQ_CTL_FORCE_INTERVENE (1L<<2) 5915#define BCE_COM_COMQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 5916#define BCE_COM_COMQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 5917 5918#define BCE_COM_SCRATCH 0x00120000 5919 5920 5921/* 5922 * cp_reg definition 5923 * offset: 0x180000 5924 */ 5925#define BCE_CP_CPU_MODE 0x00185000 5926#define BCE_CP_CPU_MODE_LOCAL_RST (1L<<0) 5927#define BCE_CP_CPU_MODE_STEP_ENA (1L<<1) 5928#define BCE_CP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2) 5929#define BCE_CP_CPU_MODE_PAGE_0_INST_ENA (1L<<3) 5930#define BCE_CP_CPU_MODE_MSG_BIT1 (1L<<6) 5931#define BCE_CP_CPU_MODE_INTERRUPT_ENA (1L<<7) 5932#define BCE_CP_CPU_MODE_SOFT_HALT (1L<<10) 5933#define BCE_CP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11) 5934#define BCE_CP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12) 5935#define BCE_CP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13) 5936#define BCE_CP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15) 5937 5938#define BCE_CP_CPU_STATE 0x00185004 5939#define BCE_CP_CPU_STATE_BREAKPOINT (1L<<0) 5940#define BCE_CP_CPU_STATE_BAD_INST_HALTED (1L<<2) 5941#define BCE_CP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) 5942#define BCE_CP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) 5943#define BCE_CP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) 5944#define BCE_CP_CPU_STATE_BAD_pc_HALTED (1L<<6) 5945#define BCE_CP_CPU_STATE_ALIGN_HALTED (1L<<7) 5946#define BCE_CP_CPU_STATE_FIO_ABORT_HALTED (1L<<8) 5947#define BCE_CP_CPU_STATE_SOFT_HALTED (1L<<10) 5948#define BCE_CP_CPU_STATE_SPAD_UNDERFLOW (1L<<11) 5949#define BCE_CP_CPU_STATE_INTERRRUPT (1L<<12) 5950#define BCE_CP_CPU_STATE_DATA_ACCESS_STALL (1L<<14) 5951#define BCE_CP_CPU_STATE_INST_FETCH_STALL (1L<<15) 5952#define BCE_CP_CPU_STATE_BLOCKED_READ (1L<<31) 5953 5954#define BCE_CP_CPU_EVENT_MASK 0x00185008 5955#define BCE_CP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) 5956#define BCE_CP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2) 5957#define BCE_CP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3) 5958#define BCE_CP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4) 5959#define BCE_CP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5) 5960#define BCE_CP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6) 5961#define BCE_CP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7) 5962#define BCE_CP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8) 5963#define BCE_CP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10) 5964#define BCE_CP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11) 5965#define BCE_CP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12) 5966 5967#define BCE_CP_CPU_PROGRAM_COUNTER 0x0018501c 5968#define BCE_CP_CPU_INSTRUCTION 0x00185020 5969#define BCE_CP_CPU_DATA_ACCESS 0x00185024 5970#define BCE_CP_CPU_INTERRUPT_ENABLE 0x00185028 5971#define BCE_CP_CPU_INTERRUPT_VECTOR 0x0018502c 5972#define BCE_CP_CPU_INTERRUPT_SAVED_PC 0x00185030 5973#define BCE_CP_CPU_HW_BREAKPOINT 0x00185034 5974#define BCE_CP_CPU_HW_BREAKPOINT_DISABLE (1L<<0) 5975#define BCE_CP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2) 5976 5977#define BCE_CP_CPU_REG_FILE 0x00185200 5978#define BCE_CP_CPQ_FTQ_DATA 0x001853c0 5979#define BCE_CP_CPQ_FTQ_CMD 0x001853f8 5980#define BCE_CP_CPQ_FTQ_CMD_OFFSET (0x3ffL<<0) 5981#define BCE_CP_CPQ_FTQ_CMD_WR_TOP (1L<<10) 5982#define BCE_CP_CPQ_FTQ_CMD_WR_TOP_0 (0L<<10) 5983#define BCE_CP_CPQ_FTQ_CMD_WR_TOP_1 (1L<<10) 5984#define BCE_CP_CPQ_FTQ_CMD_SFT_RESET (1L<<25) 5985#define BCE_CP_CPQ_FTQ_CMD_RD_DATA (1L<<26) 5986#define BCE_CP_CPQ_FTQ_CMD_ADD_INTERVEN (1L<<27) 5987#define BCE_CP_CPQ_FTQ_CMD_ADD_DATA (1L<<28) 5988#define BCE_CP_CPQ_FTQ_CMD_INTERVENE_CLR (1L<<29) 5989#define BCE_CP_CPQ_FTQ_CMD_POP (1L<<30) 5990#define BCE_CP_CPQ_FTQ_CMD_BUSY (1L<<31) 5991 5992#define BCE_CP_CPQ_FTQ_CTL 0x001853fc 5993#define BCE_CP_CPQ_FTQ_CTL_INTERVENE (1L<<0) 5994#define BCE_CP_CPQ_FTQ_CTL_OVERFLOW (1L<<1) 5995#define BCE_CP_CPQ_FTQ_CTL_FORCE_INTERVENE (1L<<2) 5996#define BCE_CP_CPQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 5997#define BCE_CP_CPQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 5998 5999#define BCE_CP_SCRATCH 0x001a0000 6000 6001 6002/* 6003 * tas_reg definition 6004 * offset: 0x1c0000 6005 */ 6006#define BCE_TAS_FTQ_CMD 0x001c03f8 6007#define BCE_TAS_FTQ_CTL 0x001c03fc 6008#define BCE_TAS_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 6009#define BCE_TAS_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 6010 6011 6012/* 6013 * mcp_reg definition 6014 * offset: 0x140000 6015 */ 6016#define BCE_MCP_CPU_MODE 0x00145000 6017#define BCE_MCP_CPU_MODE_LOCAL_RST (1L<<0) 6018#define BCE_MCP_CPU_MODE_STEP_ENA (1L<<1) 6019#define BCE_MCP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2) 6020#define BCE_MCP_CPU_MODE_PAGE_0_INST_ENA (1L<<3) 6021#define BCE_MCP_CPU_MODE_MSG_BIT1 (1L<<6) 6022#define BCE_MCP_CPU_MODE_INTERRUPT_ENA (1L<<7) 6023#define BCE_MCP_CPU_MODE_SOFT_HALT (1L<<10) 6024#define BCE_MCP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11) 6025#define BCE_MCP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12) 6026#define BCE_MCP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13) 6027#define BCE_MCP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15) 6028 6029#define BCE_MCP_CPU_STATE 0x00145004 6030#define BCE_MCP_CPU_STATE_BREAKPOINT (1L<<0) 6031#define BCE_MCP_CPU_STATE_BAD_INST_HALTED (1L<<2) 6032#define BCE_MCP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) 6033#define BCE_MCP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) 6034#define BCE_MCP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) 6035#define BCE_MCP_CPU_STATE_BAD_pc_HALTED (1L<<6) 6036#define BCE_MCP_CPU_STATE_ALIGN_HALTED (1L<<7) 6037#define BCE_MCP_CPU_STATE_FIO_ABORT_HALTED (1L<<8) 6038#define BCE_MCP_CPU_STATE_SOFT_HALTED (1L<<10) 6039#define BCE_MCP_CPU_STATE_SPAD_UNDERFLOW (1L<<11) 6040#define BCE_MCP_CPU_STATE_INTERRRUPT (1L<<12) 6041#define BCE_MCP_CPU_STATE_DATA_ACCESS_STALL (1L<<14) 6042#define BCE_MCP_CPU_STATE_INST_FETCH_STALL (1L<<15) 6043#define BCE_MCP_CPU_STATE_BLOCKED_READ (1L<<31) 6044 6045#define BCE_MCP_CPU_EVENT_MASK 0x00145008 6046#define BCE_MCP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) 6047#define BCE_MCP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2) 6048#define BCE_MCP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3) 6049#define BCE_MCP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4) 6050#define BCE_MCP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5) 6051#define BCE_MCP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6) 6052#define BCE_MCP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7) 6053#define BCE_MCP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8) 6054#define BCE_MCP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10) 6055#define BCE_MCP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11) 6056#define BCE_MCP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12) 6057 6058#define BCE_MCP_CPU_PROGRAM_COUNTER 0x0014501c 6059#define BCE_MCP_CPU_INSTRUCTION 0x00145020 6060#define BCE_MCP_CPU_DATA_ACCESS 0x00145024 6061#define BCE_MCP_CPU_INTERRUPT_ENABLE 0x00145028 6062#define BCE_MCP_CPU_INTERRUPT_VECTOR 0x0014502c 6063#define BCE_MCP_CPU_INTERRUPT_SAVED_PC 0x00145030 6064#define BCE_MCP_CPU_HW_BREAKPOINT 0x00145034 6065#define BCE_MCP_CPU_HW_BREAKPOINT_DISABLE (1L<<0) 6066#define BCE_MCP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2) 6067 6068#define BCE_MCP_CPU_REG_FILE 0x00145200 6069#define BCE_MCP_MCPQ_FTQ_DATA 0x001453c0 6070#define BCE_MCP_MCPQ_FTQ_CMD 0x001453f8 6071#define BCE_MCP_MCPQ_FTQ_CMD_OFFSET (0x3ffL<<0) 6072#define BCE_MCP_MCPQ_FTQ_CMD_WR_TOP (1L<<10) 6073#define BCE_MCP_MCPQ_FTQ_CMD_WR_TOP_0 (0L<<10) 6074#define BCE_MCP_MCPQ_FTQ_CMD_WR_TOP_1 (1L<<10) 6075#define BCE_MCP_MCPQ_FTQ_CMD_SFT_RESET (1L<<25) 6076#define BCE_MCP_MCPQ_FTQ_CMD_RD_DATA (1L<<26) 6077#define BCE_MCP_MCPQ_FTQ_CMD_ADD_INTERVEN (1L<<27) 6078#define BCE_MCP_MCPQ_FTQ_CMD_ADD_DATA (1L<<28) 6079#define BCE_MCP_MCPQ_FTQ_CMD_INTERVENE_CLR (1L<<29) 6080#define BCE_MCP_MCPQ_FTQ_CMD_POP (1L<<30) 6081#define BCE_MCP_MCPQ_FTQ_CMD_BUSY (1L<<31) 6082 6083#define BCE_MCP_MCPQ_FTQ_CTL 0x001453fc 6084#define BCE_MCP_MCPQ_FTQ_CTL_INTERVENE (1L<<0) 6085#define BCE_MCP_MCPQ_FTQ_CTL_OVERFLOW (1L<<1) 6086#define BCE_MCP_MCPQ_FTQ_CTL_FORCE_INTERVENE (1L<<2) 6087#define BCE_MCP_MCPQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 6088#define BCE_MCP_MCPQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 6089 6090#define BCE_MCP_ROM 0x00150000 6091#define BCE_MCP_SCRATCH 0x00160000 6092 6093#define BCE_SHM_HDR_SIGNATURE BCE_MCP_SCRATCH 6094#define BCE_SHM_HDR_SIGNATURE_SIG_MASK 0xffff0000 6095#define BCE_SHM_HDR_SIGNATURE_SIG 0x53530000 6096#define BCE_SHM_HDR_SIGNATURE_VER_MASK 0x000000ff 6097#define BCE_SHM_HDR_SIGNATURE_VER_ONE 0x00000001 6098 6099#define BCE_SHM_HDR_ADDR_0 BCE_MCP_SCRATCH + 4 6100#define BCE_SHM_HDR_ADDR_1 BCE_MCP_SCRATCH + 8 6101 6102/****************************************************************************/ 6103/* End machine generated definitions. */ 6104/****************************************************************************/ 6105 6106/****************************************************************************/ 6107/* Begin firmware definitions. */ 6108/****************************************************************************/ 6109/* The following definitions refer to pre-defined locations in processor */ 6110/* memory space which allows the driver to enable particular functionality */ 6111/* within the firmware or read specfic information about the running */ 6112/* firmware. */ 6113/****************************************************************************/ 6114 6115/* 6116 * Perfect match control register. 6117 * 0 = Default. All received unicst packets matching MAC address 6118 * BCE_EMAC_MAC_MATCH[0:1,8:9,10:11,12:13,14:15] are sent to receive queue 6119 * 0, all other perfect match registers are reserved. 6120 * 1 = All received unicast packets matching MAC address 6121 * BCE_EMAC_MAC_MATCH[0:1] are mapped to receive queue 0, 6122 * BCE_EMAC_MAC_MATCH[2:3] is mapped to receive queue 1, etc. 6123 * 2 = All received unicast packets matching any BCE_EMAC_MAC_MATCH[] register 6124 * are sent to receive queue 0. 6125 */ 6126#define BCE_RXP_PM_CTRL 0x0e00d0 6127 6128/* 6129 * This firmware statistic records the number of frames that 6130 * were dropped because there were no buffers available in the 6131 * receive chain. 6132 */ 6133#define BCE_COM_NO_BUFFERS 0x120084 6134/****************************************************************************/ 6135/* End firmware definitions. */ 6136/****************************************************************************/ 6137 6138#define NUM_MC_HASH_REGISTERS 8 6139 6140#define DMA_READ_CHANS 5 6141#define DMA_WRITE_CHANS 3 6142 6143/* Use the natural page size of the host CPU. */ 6144/* XXX: This has only been tested on amd64/i386 systems using 4KB pages. */ 6145#define BCM_PAGE_BITS PAGE_SHIFT 6146#define BCM_PAGE_SIZE PAGE_SIZE 6147#define BCM_PAGE_MASK (BCM_PAGE_SIZE - 1) 6148#define BCM_PAGES(x) ((((x) + BCM_PAGE_SIZE - 1) & \ 6149 BCM_PAGE_MASK) >> BCM_PAGE_BITS) 6150 6151/* 6152 * Page count must remain a power of 2 for all 6153 * of the math to work correctly. 6154 */ 6155#define DEFAULT_TX_PAGES 2 6156#define MAX_TX_PAGES 8 6157#define TOTAL_TX_BD_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct tx_bd)) 6158#define USABLE_TX_BD_PER_PAGE (TOTAL_TX_BD_PER_PAGE - 1) 6159#define MAX_TX_BD_AVAIL (MAX_TX_PAGES * TOTAL_TX_BD_PER_PAGE) 6160#define TOTAL_TX_BD_ALLOC (TOTAL_TX_BD_PER_PAGE * sc->tx_pages) 6161#define USABLE_TX_BD_ALLOC (USABLE_TX_BD_PER_PAGE * sc->tx_pages) 6162#define MAX_TX_BD_ALLOC (TOTAL_TX_BD_ALLOC - 1) 6163 6164/* Advance to the next tx_bd, skipping any next page pointers. */ 6165#define NEXT_TX_BD(x) (((x) & USABLE_TX_BD_PER_PAGE) == \ 6166 (USABLE_TX_BD_PER_PAGE - 1)) ? (x) + 2 : (x) + 1 6167 6168#define TX_CHAIN_IDX(x) ((x) & MAX_TX_BD_ALLOC) 6169 6170#define TX_PAGE(x) (((x) & ~USABLE_TX_BD_PER_PAGE) >> (BCM_PAGE_BITS - 4)) 6171#define TX_IDX(x) ((x) & USABLE_TX_BD_PER_PAGE) 6172 6173/* 6174 * Page count must remain a power of 2 for all 6175 * of the math to work correctly. 6176 */ 6177#define DEFAULT_RX_PAGES 2 6178#define MAX_RX_PAGES 8 6179#define TOTAL_RX_BD_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct rx_bd)) 6180#define USABLE_RX_BD_PER_PAGE (TOTAL_RX_BD_PER_PAGE - 1) 6181#define MAX_RX_BD_AVAIL (MAX_RX_PAGES * TOTAL_RX_BD_PER_PAGE) 6182#define TOTAL_RX_BD_ALLOC (TOTAL_RX_BD_PER_PAGE * sc->rx_pages) 6183#define USABLE_RX_BD_ALLOC (USABLE_RX_BD_PER_PAGE * sc->rx_pages) 6184#define MAX_RX_BD_ALLOC (TOTAL_RX_BD_ALLOC - 1) 6185 6186/* Advance to the next rx_bd, skipping any next page pointers. */ 6187#define NEXT_RX_BD(x) (((x) & USABLE_RX_BD_PER_PAGE) == \ 6188 (USABLE_RX_BD_PER_PAGE - 1)) ? (x) + 2 : (x) + 1 6189 6190#define RX_CHAIN_IDX(x) ((x) & MAX_RX_BD_ALLOC) 6191 6192#define RX_PAGE(x) (((x) & ~USABLE_RX_BD_PER_PAGE) >> (BCM_PAGE_BITS - 4)) 6193#define RX_IDX(x) ((x) & USABLE_RX_BD_PER_PAGE) 6194 6195/* 6196 * To accomodate jumbo frames, the page chain should 6197 * be 4 times larger than the receive chain. 6198 */ 6199#define DEFAULT_PG_PAGES (DEFAULT_RX_PAGES * 4) 6200#define MAX_PG_PAGES (MAX_RX_PAGES * 4) 6201#define TOTAL_PG_BD_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct rx_bd)) 6202#define USABLE_PG_BD_PER_PAGE (TOTAL_PG_BD_PER_PAGE - 1) 6203#define MAX_PG_BD_AVAIL (MAX_PG_PAGES * TOTAL_PG_BD_PER_PAGE) 6204#define TOTAL_PG_BD_ALLOC (TOTAL_PG_BD_PER_PAGE * sc->pg_pages) 6205#define USABLE_PG_BD_ALLOC (USABLE_PG_BD_PER_PAGE * sc->pg_pages) 6206#define MAX_PG_BD_ALLOC (TOTAL_PG_BD_ALLOC - 1) 6207 6208/* Advance to the next pg_bd, skipping any next page pointers. */ 6209#define NEXT_PG_BD(x) (((x) & USABLE_PG_BD_PER_PAGE) == \ 6210 (USABLE_PG_BD_PER_PAGE - 1)) ? (x) + 2 : (x) + 1 6211 6212#define PG_CHAIN_IDX(x) ((x) & MAX_PG_BD_ALLOC) 6213 6214#define PG_PAGE(x) (((x) & ~USABLE_PG_BD_PER_PAGE) >> (BCM_PAGE_BITS - 4)) 6215#define PG_IDX(x) ((x) & USABLE_PG_BD_PER_PAGE) 6216 6217#define CTX_INIT_RETRY_COUNT 10 6218 6219/* Context size. */ 6220#define CTX_SHIFT 7 6221#define CTX_SIZE (1 << CTX_SHIFT) 6222#define CTX_MASK (CTX_SIZE - 1) 6223#define GET_CID_ADDR(_cid) ((_cid) << CTX_SHIFT) 6224#define GET_CID(_cid_addr) ((_cid_addr) >> CTX_SHIFT) 6225 6226#define PHY_CTX_SHIFT 6 6227#define PHY_CTX_SIZE (1 << PHY_CTX_SHIFT) 6228#define PHY_CTX_MASK (PHY_CTX_SIZE - 1) 6229#define GET_PCID_ADDR(_pcid) ((_pcid) << PHY_CTX_SHIFT) 6230#define GET_PCID(_pcid_addr) ((_pcid_addr) >> PHY_CTX_SHIFT) 6231 6232#define MB_KERNEL_CTX_SHIFT 8 6233#define MB_KERNEL_CTX_SIZE (1 << MB_KERNEL_CTX_SHIFT) 6234#define MB_KERNEL_CTX_MASK (MB_KERNEL_CTX_SIZE - 1) 6235#define MB_GET_CID_ADDR(_cid) (0x10000 + ((_cid) << MB_KERNEL_CTX_SHIFT)) 6236 6237#define MAX_CID_CNT 0x4000 6238#define MAX_CID_ADDR (GET_CID_ADDR(MAX_CID_CNT)) 6239#define INVALID_CID_ADDR 0xffffffff 6240 6241#define TX_CID 16 6242#define RX_CID 0 6243 6244#define DEFAULT_TX_QUICK_CONS_TRIP_INT 20 6245#define DEFAULT_TX_QUICK_CONS_TRIP 20 6246#define DEFAULT_TX_TICKS_INT 80 6247#define DEFAULT_TX_TICKS 80 6248#define DEFAULT_RX_QUICK_CONS_TRIP_INT 6 6249#define DEFAULT_RX_QUICK_CONS_TRIP 6 6250#define DEFAULT_RX_TICKS_INT 18 6251#define DEFAULT_RX_TICKS 18 6252 6253/****************************************************************************/ 6254/* BCE Processor Firmwware Load Definitions */ 6255/****************************************************************************/ 6256 6257struct cpu_reg { 6258 u32 mode; 6259 u32 mode_value_halt; 6260 u32 mode_value_sstep; 6261 6262 u32 state; 6263 u32 state_value_clear; 6264 6265 u32 gpr0; 6266 u32 evmask; 6267 u32 pc; 6268 u32 inst; 6269 u32 bp; 6270 6271 u32 spad_base; 6272 6273 u32 mips_view_base; 6274}; 6275 6276struct fw_info { 6277 u32 ver_major; 6278 u32 ver_minor; 6279 u32 ver_fix; 6280 6281 u32 start_addr; 6282 6283 /* Text section. */ 6284 u32 text_addr; 6285 u32 text_len; 6286 u32 text_index; 6287 u32 *text; 6288 6289 /* Data section. */ 6290 u32 data_addr; 6291 u32 data_len; 6292 u32 data_index; 6293 u32 *data; 6294 6295 /* SBSS section. */ 6296 u32 sbss_addr; 6297 u32 sbss_len; 6298 u32 sbss_index; 6299 u32 *sbss; 6300 6301 /* BSS section. */ 6302 u32 bss_addr; 6303 u32 bss_len; 6304 u32 bss_index; 6305 u32 *bss; 6306 6307 /* Read-only section. */ 6308 u32 rodata_addr; 6309 u32 rodata_len; 6310 u32 rodata_index; 6311 u32 *rodata; 6312}; 6313 6314#define RV2P_PROC1 0 6315#define RV2P_PROC2 1 6316 6317#define BCE_MIREG(x) ((x & 0x1F) << 16) 6318#define BCE_MIPHY(x) ((x & 0x1F) << 21) 6319#define BCE_PHY_TIMEOUT 50 6320 6321#define BCE_NVRAM_SIZE 0x200 6322#define BCE_NVRAM_MAGIC 0x669955aa 6323#define BCE_CRC32_RESIDUAL 0xdebb20e3 6324 6325#define BCE_TX_TIMEOUT 5 6326 6327#define BCE_MAX_SEGMENTS 32 6328#define BCE_TSO_MAX_SIZE 65536 6329#define BCE_TSO_MAX_SEG_SIZE 4096 6330 6331#define BCE_DMA_ALIGN 8 6332#define BCE_DMA_BOUNDARY 0 6333#define BCE_RX_BUF_ALIGN 16 6334 6335#define BCE_MAX_CONTEXT 4 6336 6337/* The BCM5708 has a problem with addresses greater that 40bits. */ 6338/* Handle the sizing issue in an architecture agnostic fashion. */ 6339#if (BUS_SPACE_MAXADDR < 0xFFFFFFFFFF) 6340#define BCE_BUS_SPACE_MAXADDR BUS_SPACE_MAXADDR 6341#else 6342#define BCE_BUS_SPACE_MAXADDR 0xFFFFFFFFFF 6343#endif 6344 6345/* 6346 * XXX Checksum offload involving IP fragments seems to cause problems on 6347 * transmit. Disable it for now, hopefully there will be a more elegant 6348 * solution later. 6349 */ 6350#ifdef BCE_IP_CSUM 6351#define BCE_IF_HWASSIST (CSUM_IP | CSUM_TCP | CSUM_UDP) 6352#else 6353#define BCE_IF_HWASSIST (CSUM_TCP | CSUM_UDP) 6354#endif 6355 6356#if __FreeBSD_version < 700000 6357#define BCE_IF_CAPABILITIES (IFCAP_VLAN_MTU | \ 6358 IFCAP_VLAN_HWTAGGING | IFCAP_HWCSUM | IFCAP_JUMBO_MTU) 6359#else 6360#define BCE_IF_CAPABILITIES (IFCAP_VLAN_MTU | \ 6361 IFCAP_VLAN_HWTAGGING | IFCAP_HWCSUM | \ 6362 IFCAP_JUMBO_MTU | IFCAP_VLAN_HWCSUM) 6363#endif 6364 6365#define BCE_MIN_MTU 60 6366#define BCE_MIN_ETHER_MTU 64 6367 6368#define BCE_MAX_STD_MTU 1500 6369#define BCE_MAX_STD_ETHER_MTU 1518 6370#define BCE_MAX_STD_ETHER_MTU_VLAN 1522 6371 6372#define BCE_MAX_JUMBO_MTU 9000 6373#define BCE_MAX_JUMBO_ETHER_MTU 9018 6374#define BCE_MAX_JUMBO_ETHER_MTU_VLAN 9022 6375 6376// #define BCE_MAX_MTU ETHER_MAX_LEN_JUMBO + ETHER_VLAN_ENCAP_LEN /* 9022 */ 6377 6378/****************************************************************************/ 6379/* BCE Device State Data Structure */ 6380/****************************************************************************/ 6381 6382#define BCE_STATUS_BLK_SZ sizeof(struct status_block) 6383#define BCE_STATS_BLK_SZ sizeof(struct statistics_block) 6384#define BCE_TX_CHAIN_PAGE_SZ BCM_PAGE_SIZE 6385#define BCE_RX_CHAIN_PAGE_SZ BCM_PAGE_SIZE 6386#define BCE_PG_CHAIN_PAGE_SZ BCM_PAGE_SIZE 6387 6388struct bce_softc 6389{ 6390 /* Interface info. Must be first!! */ 6391 struct ifnet *bce_ifp; 6392 6393 /* Parent device handle */ 6394 device_t bce_dev; 6395 6396 /* Interface number */ 6397 u_int8_t bce_unit; 6398 6399 /* Device resource handle */ 6400 struct resource *bce_res_mem; 6401 6402 /* TBI media info */ 6403 struct ifmedia bce_ifmedia; 6404 6405 /* Device bus tag */ 6406 bus_space_tag_t bce_btag; 6407 6408 /* Device bus handle */ 6409 bus_space_handle_t bce_bhandle; 6410 6411 /* Device virtual memory handle */ 6412 vm_offset_t bce_vhandle; 6413 6414 /* IRQ Resource Handle */ 6415 struct resource *bce_res_irq; 6416 6417 struct mtx bce_mtx; 6418 6419 /* Interrupt handler. */ 6420 driver_intr_t *bce_intr; 6421 void *bce_intrhand; 6422 int bce_irq_rid; 6423 int bce_msi_count; 6424 6425 /* ASIC Chip ID. */ 6426 u32 bce_chipid; 6427 6428 /* General controller flags. */ 6429 u32 bce_flags; 6430#define BCE_PCIX_FLAG 0x00000001 6431#define BCE_PCI_32BIT_FLAG 0x00000002 6432#define BCE_RESERVED_FLAG 0x00000004 6433#define BCE_NO_WOL_FLAG 0x00000008 6434#define BCE_USING_DAC_FLAG 0x00000010 6435#define BCE_USING_MSI_FLAG 0x00000020 6436#define BCE_MFW_ENABLE_FLAG 0x00000040 6437#define BCE_ONE_SHOT_MSI_FLAG 0x00000080 6438#define BCE_USING_MSIX_FLAG 0x00000100 6439#define BCE_PCIE_FLAG 0x00000200 6440#define BCE_USING_TX_FLOW_CONTROL 0x00000400 6441 6442 /* Controller capability flags. */ 6443 u32 bce_cap_flags; 6444#define BCE_MSI_CAPABLE_FLAG 0x00000001 6445#define BCE_MSIX_CAPABLE_FLAG 0x00000002 6446#define BCE_PCIE_CAPABLE_FLAG 0x00000004 6447#define BCE_PCIX_CAPABLE_FLAG 0x00000008 6448 6449 /* PHY specific flags. */ 6450 u32 bce_phy_flags; 6451#define BCE_PHY_SERDES_FLAG 0x00000001 6452#define BCE_PHY_CRC_FIX_FLAG 0x00000002 6453#define BCE_PHY_PARALLEL_DETECT_FLAG 0x00000004 6454#define BCE_PHY_2_5G_CAPABLE_FLAG 0x00000008 6455#define BCE_PHY_INT_MODE_MASK_FLAG 0x00000300 6456#define BCE_PHY_INT_MODE_AUTO_POLLING_FLAG 0x00000100 6457#define BCE_PHY_INT_MODE_LINK_READY_FLAG 0x00000200 6458#define BCE_PHY_IEEE_CLAUSE_45_FLAG 0x00000400 6459 6460 /* Values that need to be shared with the PHY driver. */ 6461 u32 bce_shared_hw_cfg; 6462 u32 bce_port_hw_cfg; 6463 6464 bus_addr_t max_bus_addr; 6465 6466 /* PCI bus speed */ 6467 u16 bus_speed_mhz; 6468 6469 /* PCIe link width */ 6470 u16 link_width; 6471 6472 /* PCIe link speed */ 6473 u16 link_speed; 6474 6475 /* Flash NVRAM settings */ 6476 struct flash_spec *bce_flash_info; 6477 6478 /* Flash NVRAM size */ 6479 u32 bce_flash_size; 6480 6481 /* Shared Memory base address */ 6482 u32 bce_shmem_base; 6483 6484 /* Name string */ 6485 char *bce_name; 6486 6487 /* Tracks the version of bootcode firmware. */ 6488 char bce_bc_ver[32]; 6489 6490 /* Tracks the version of management firmware. */ 6491 char bce_mfw_ver[32]; 6492 6493 /* 6494 * Tracks the state of the firmware. 0 = Running while any 6495 * other value indicates that the firmware is not responding. 6496 */ 6497 u16 bce_fw_timed_out; 6498 6499 /* 6500 * An incrementing sequence used to coordinate messages passed 6501 * from the driver to the firmware. 6502 */ 6503 u16 bce_fw_wr_seq; 6504 6505 /* 6506 * An incrementing sequence used to let the firmware know that 6507 * the driver is still operating. Without the pulse, management 6508 * firmware such as IPMI or UMP will operate in OS absent state. 6509 */ 6510 u16 bce_fw_drv_pulse_wr_seq; 6511 6512 /* Tracks whether firmware has lost the driver's pulse. */ 6513 u16 bce_drv_cardiac_arrest; 6514 6515 /* Ethernet MAC address. */ 6516 u_char eaddr[6]; 6517 6518 /* 6519 * These setting are used by the host coalescing (HC) block to 6520 * to control how often the status block, statistics block and 6521 * interrupts are generated. 6522 */ 6523 u16 bce_tx_quick_cons_trip_int; 6524 u16 bce_tx_quick_cons_trip; 6525 u16 bce_rx_quick_cons_trip_int; 6526 u16 bce_rx_quick_cons_trip; 6527 u16 bce_tx_ticks_int; 6528 u16 bce_tx_ticks; 6529 u16 bce_rx_ticks_int; 6530 u16 bce_rx_ticks; 6531 u32 bce_stats_ticks; 6532 6533 /* ToDo: Can these be removed? */ 6534 u16 bce_comp_prod_trip_int; 6535 u16 bce_comp_prod_trip; 6536 u16 bce_com_ticks_int; 6537 u16 bce_com_ticks; 6538 u16 bce_cmd_ticks_int; 6539 u16 bce_cmd_ticks; 6540 6541 /* The address of the integrated PHY on the MII bus. */ 6542 int bce_phy_addr; 6543 6544 /* The device handle for the MII bus child device. */ 6545 device_t bce_miibus; 6546 6547 /* Driver maintained RX chain pointers and byte counter. */ 6548 u16 rx_prod; 6549 u16 rx_cons; 6550 6551 /* Counts the bytes used in the RX chain. */ 6552 u32 rx_prod_bseq; 6553 6554 /* Driver maintained TX chain pointers and byte counter. */ 6555 u16 tx_prod; 6556 u16 tx_cons; 6557 6558 /* Counts the bytes used in the TX chain. */ 6559 u32 tx_prod_bseq; 6560 6561 /* Driver maintained PG chain pointers. */ 6562 u16 pg_prod; 6563 u16 pg_cons; 6564 6565 int bce_link_up; 6566 struct callout bce_tick_callout; 6567 struct callout bce_pulse_callout; 6568 6569 /* Ticks until chip reset */ 6570 int watchdog_timer; 6571 6572 /* Frame size and mbuf allocation size for RX frames. */ 6573 u32 max_frame_size; 6574 int rx_bd_mbuf_alloc_size; 6575 int rx_bd_mbuf_data_len; 6576 int rx_bd_mbuf_align_pad; 6577 int pg_bd_mbuf_alloc_size; 6578 6579 /* Receive mode settings (i.e promiscuous, multicast, etc.). */ 6580 u32 rx_mode; 6581 6582 /* Bus tag for the bce controller. */ 6583 bus_dma_tag_t parent_tag; 6584 6585 /* H/W maintained TX buffer descriptor chain structure. */ 6586 int tx_pages; 6587 bus_dma_tag_t tx_bd_chain_tag; 6588 bus_dmamap_t tx_bd_chain_map[MAX_TX_PAGES]; 6589 struct tx_bd *tx_bd_chain[MAX_TX_PAGES]; 6590 bus_addr_t tx_bd_chain_paddr[MAX_TX_PAGES]; 6591 6592 /* H/W maintained RX buffer descriptor chain structure. */ 6593 int rx_pages; 6594 bus_dma_tag_t rx_bd_chain_tag; 6595 bus_dmamap_t rx_bd_chain_map[MAX_RX_PAGES]; 6596 struct rx_bd *rx_bd_chain[MAX_RX_PAGES]; 6597 bus_addr_t rx_bd_chain_paddr[MAX_RX_PAGES]; 6598 6599 /* H/W maintained page buffer descriptor chain structure. */ 6600 int pg_pages; 6601 bus_dma_tag_t pg_bd_chain_tag; 6602 bus_dmamap_t pg_bd_chain_map[MAX_PG_PAGES]; 6603 struct rx_bd *pg_bd_chain[MAX_PG_PAGES]; 6604 bus_addr_t pg_bd_chain_paddr[MAX_PG_PAGES]; 6605 6606 /* H/W maintained status block. */ 6607 bus_dma_tag_t status_tag; 6608 bus_dmamap_t status_map; 6609 struct status_block *status_block; 6610 bus_addr_t status_block_paddr; 6611 6612 /* Driver maintained status block values. */ 6613 u16 last_status_idx; 6614 u16 hw_rx_cons; 6615 u16 hw_tx_cons; 6616 6617 /* H/W maintained statistics block. */ 6618 bus_dma_tag_t stats_tag; 6619 bus_dmamap_t stats_map; 6620 struct statistics_block *stats_block; 6621 bus_addr_t stats_block_paddr; 6622 6623 /* H/W maintained context block. */ 6624 int ctx_pages; 6625 bus_dma_tag_t ctx_tag; 6626 6627 /* BCM5709/16 use host memory for context. */ 6628 bus_dmamap_t ctx_map[BCE_MAX_CONTEXT]; 6629 void *ctx_block[BCE_MAX_CONTEXT]; 6630 bus_addr_t ctx_paddr[BCE_MAX_CONTEXT]; 6631 6632 /* Bus tag for RX/TX mbufs. */ 6633 bus_dma_tag_t rx_mbuf_tag; 6634 bus_dma_tag_t tx_mbuf_tag; 6635 bus_dma_tag_t pg_mbuf_tag; 6636 6637 /* S/W maintained mbuf TX chain structure. */ 6638 bus_dmamap_t tx_mbuf_map[MAX_TX_BD_AVAIL]; 6639 struct mbuf *tx_mbuf_ptr[MAX_TX_BD_AVAIL]; 6640 6641 /* S/W maintained mbuf RX chain structure. */ 6642 bus_dmamap_t rx_mbuf_map[MAX_RX_BD_AVAIL]; 6643 struct mbuf *rx_mbuf_ptr[MAX_RX_BD_AVAIL]; 6644 6645 /* S/W maintained mbuf page chain structure. */ 6646 bus_dmamap_t pg_mbuf_map[MAX_PG_BD_AVAIL]; 6647 struct mbuf *pg_mbuf_ptr[MAX_PG_BD_AVAIL]; 6648 6649 /* Track the number of buffer descriptors in use. */ 6650 u16 free_rx_bd; 6651 u16 max_rx_bd; 6652 u16 used_tx_bd; 6653 u16 max_tx_bd; 6654 u16 free_pg_bd; 6655 u16 max_pg_bd; 6656 6657 /* Provides access to hardware statistics through sysctl. */ 6658 u64 stat_IfHCInOctets; 6659 u64 stat_IfHCInBadOctets; 6660 u64 stat_IfHCOutOctets; 6661 u64 stat_IfHCOutBadOctets; 6662 u64 stat_IfHCInUcastPkts; 6663 u64 stat_IfHCInMulticastPkts; 6664 u64 stat_IfHCInBroadcastPkts; 6665 u64 stat_IfHCOutUcastPkts; 6666 u64 stat_IfHCOutMulticastPkts; 6667 u64 stat_IfHCOutBroadcastPkts; 6668 6669 u32 stat_emac_tx_stat_dot3statsinternalmactransmiterrors; 6670 u32 stat_Dot3StatsCarrierSenseErrors; 6671 u32 stat_Dot3StatsFCSErrors; 6672 u32 stat_Dot3StatsAlignmentErrors; 6673 u32 stat_Dot3StatsSingleCollisionFrames; 6674 u32 stat_Dot3StatsMultipleCollisionFrames; 6675 u32 stat_Dot3StatsDeferredTransmissions; 6676 u32 stat_Dot3StatsExcessiveCollisions; 6677 u32 stat_Dot3StatsLateCollisions; 6678 u32 stat_EtherStatsCollisions; 6679 u32 stat_EtherStatsFragments; 6680 u32 stat_EtherStatsJabbers; 6681 u32 stat_EtherStatsUndersizePkts; 6682 u32 stat_EtherStatsOversizePkts; 6683 u32 stat_EtherStatsPktsRx64Octets; 6684 u32 stat_EtherStatsPktsRx65Octetsto127Octets; 6685 u32 stat_EtherStatsPktsRx128Octetsto255Octets; 6686 u32 stat_EtherStatsPktsRx256Octetsto511Octets; 6687 u32 stat_EtherStatsPktsRx512Octetsto1023Octets; 6688 u32 stat_EtherStatsPktsRx1024Octetsto1522Octets; 6689 u32 stat_EtherStatsPktsRx1523Octetsto9022Octets; 6690 u32 stat_EtherStatsPktsTx64Octets; 6691 u32 stat_EtherStatsPktsTx65Octetsto127Octets; 6692 u32 stat_EtherStatsPktsTx128Octetsto255Octets; 6693 u32 stat_EtherStatsPktsTx256Octetsto511Octets; 6694 u32 stat_EtherStatsPktsTx512Octetsto1023Octets; 6695 u32 stat_EtherStatsPktsTx1024Octetsto1522Octets; 6696 u32 stat_EtherStatsPktsTx1523Octetsto9022Octets; 6697 u32 stat_XonPauseFramesReceived; 6698 u32 stat_XoffPauseFramesReceived; 6699 u32 stat_OutXonSent; 6700 u32 stat_OutXoffSent; 6701 u32 stat_FlowControlDone; 6702 u32 stat_MacControlFramesReceived; 6703 u32 stat_XoffStateEntered; 6704 u32 stat_IfInFramesL2FilterDiscards; 6705 u32 stat_IfInRuleCheckerDiscards; 6706 u32 stat_IfInFTQDiscards; 6707 u32 stat_IfInMBUFDiscards; 6708 u32 stat_IfInRuleCheckerP4Hit; 6709 u32 stat_CatchupInRuleCheckerDiscards; 6710 u32 stat_CatchupInFTQDiscards; 6711 u32 stat_CatchupInMBUFDiscards; 6712 u32 stat_CatchupInRuleCheckerP4Hit; 6713 6714 /* Provides access to certain firmware statistics. */ 6715 u32 com_no_buffers; 6716 6717 /* Recoverable failure counters. */ 6718 u32 mbuf_alloc_failed_count; 6719 u32 mbuf_frag_count; 6720 u32 unexpected_attention_count; 6721 u32 l2fhdr_error_count; 6722 u32 dma_map_addr_tx_failed_count; 6723 u32 dma_map_addr_rx_failed_count; 6724 6725 /* Host coalescing block command register */ 6726 u32 hc_command; 6727 6728 /* Bootcode state */ 6729 u32 bc_state; 6730 6731#ifdef BCE_DEBUG 6732 /* Simulated recoverable failure counters. */ 6733 u32 mbuf_alloc_failed_sim_count; 6734 u32 unexpected_attention_sim_count; 6735 u32 l2fhdr_error_sim_count; 6736 u32 dma_map_addr_failed_sim_count; 6737 6738 /* Track the number of enqueued mbufs. */ 6739 int debug_tx_mbuf_alloc; 6740 int debug_rx_mbuf_alloc; 6741 int debug_pg_mbuf_alloc; 6742 6743 /* Track how many and what type of interrupts are generated. */ 6744 u64 interrupts_generated; 6745 u64 interrupts_handled; 6746 u64 interrupts_rx; 6747 u64 interrupts_tx; 6748 u64 phy_interrupts; 6749 6750 /* Lowest number of rx_bd's free. */ 6751 u16 rx_low_watermark; 6752 6753 /* Number of times the RX chain was empty. */ 6754 u64 rx_empty_count; 6755 6756 /* Lowest number of pages free. */ 6757 u16 pg_low_watermark; 6758 6759 /* Number of times the page chain was empty. */ 6760 u64 pg_empty_count; 6761 6762 /* Greatest number of tx_bd's used. */ 6763 u16 tx_hi_watermark; 6764 6765 /* Number of times the TX chain was full. */ 6766 u64 tx_full_count; 6767 6768 /* Number of TSO frames requested. */ 6769 u64 tso_frames_requested; 6770 6771 /* Number of TSO frames completed. */ 6772 u64 tso_frames_completed; 6773 6774 /* Number of TSO frames failed. */ 6775 u64 tso_frames_failed; 6776 6777 /* Number of IP checksum offload frames.*/ 6778 u64 csum_offload_ip; 6779 6780 /* Number of TCP/UDP checksum offload frames.*/ 6781 u64 csum_offload_tcp_udp; 6782 6783 /* Number of VLAN tagged frames received. */ 6784 u64 vlan_tagged_frames_rcvd; 6785 6786 /* Number of VLAN tagged frames stripped. */ 6787 u64 vlan_tagged_frames_stripped; 6788 6789 /* Number of split header frames received. */ 6790 u64 split_header_frames_rcvd; 6791 6792 /* Number of split header TCP frames received. */ 6793 u64 split_header_tcp_frames_rcvd; 6794#endif /* BCE_DEBUG */ 6795 6796 uint8_t *nvram_buf; 6797}; 6798 6799#endif /* __BCEREG_H_DEFINED */ 6800 6801