if_bcereg.h revision 170810
1/*- 2 * Copyright (c) 2006-2007 Broadcom Corporation 3 * David Christensen <davidch@broadcom.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. Neither the name of Broadcom Corporation nor the name of its contributors 14 * may be used to endorse or promote products derived from this software 15 * without specific prior written consent. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 18 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * $FreeBSD: head/sys/dev/bce/if_bcereg.h 170810 2007-06-16 02:27:03Z davidch $ 30 */ 31 32#ifndef _BCE_H_DEFINED 33#define _BCE_H_DEFINED 34 35#ifdef HAVE_KERNEL_OPTION_HEADERS 36#include "opt_device_polling.h" 37#endif 38 39#include <sys/param.h> 40#include <sys/endian.h> 41#include <sys/systm.h> 42#include <sys/sockio.h> 43#include <sys/mbuf.h> 44#include <sys/malloc.h> 45#include <sys/kernel.h> 46#include <sys/module.h> 47#include <sys/socket.h> 48#include <sys/sysctl.h> 49#include <sys/queue.h> 50 51#include <net/bpf.h> 52#include <net/ethernet.h> 53#include <net/if.h> 54#include <net/if_arp.h> 55#include <net/if_dl.h> 56#include <net/if_media.h> 57 58#include <net/if_types.h> 59#include <net/if_vlan_var.h> 60 61#include <netinet/in_systm.h> 62#include <netinet/in.h> 63#include <netinet/if_ether.h> 64#include <netinet/ip.h> 65#include <netinet/ip6.h> 66#include <netinet/tcp.h> 67#include <netinet/udp.h> 68 69#include <machine/bus.h> 70#include <machine/resource.h> 71#include <sys/bus.h> 72#include <sys/rman.h> 73 74#include <dev/mii/mii.h> 75#include <dev/mii/miivar.h> 76#include "miidevs.h" 77#include <dev/mii/brgphyreg.h> 78 79#include <dev/pci/pcireg.h> 80#include <dev/pci/pcivar.h> 81 82#include "miibus_if.h" 83 84/****************************************************************************/ 85/* Conversion to FreeBSD type definitions. */ 86/****************************************************************************/ 87#define u64 uint64_t 88#define u32 uint32_t 89#define u16 uint16_t 90#define u8 uint8_t 91 92#if BYTE_ORDER == BIG_ENDIAN 93#define __BIG_ENDIAN 1 94#undef __LITTLE_ENDIAN 95#else 96#undef __BIG_ENDIAN 97#define __LITTLE_ENDIAN 1 98#endif 99 100/****************************************************************************/ 101/* Debugging macros and definitions. */ 102/****************************************************************************/ 103#define BCE_CP_LOAD 0x00000001 104#define BCE_CP_SEND 0x00000002 105#define BCE_CP_RECV 0x00000004 106#define BCE_CP_INTR 0x00000008 107#define BCE_CP_UNLOAD 0x00000010 108#define BCE_CP_RESET 0x00000020 109#define BCE_CP_PHY 0x00000040 110#define BCE_CP_NVRAM 0x00000080 111#define BCE_CP_FIRMWARE 0x00000100 112#define BCE_CP_MISC 0x00400000 113#define BCE_CP_SPECIAL 0x00800000 114#define BCE_CP_ALL 0x00FFFFFF 115 116#define BCE_CP_MASK 0x00FFFFFF 117 118#define BCE_LEVEL_FATAL 0x00000000 119#define BCE_LEVEL_WARN 0x01000000 120#define BCE_LEVEL_INFO 0x02000000 121#define BCE_LEVEL_VERBOSE 0x03000000 122#define BCE_LEVEL_EXCESSIVE 0x04000000 123 124#define BCE_LEVEL_MASK 0xFF000000 125 126#define BCE_WARN_LOAD (BCE_CP_LOAD | BCE_LEVEL_WARN) 127#define BCE_INFO_LOAD (BCE_CP_LOAD | BCE_LEVEL_INFO) 128#define BCE_VERBOSE_LOAD (BCE_CP_LOAD | BCE_LEVEL_VERBOSE) 129#define BCE_EXCESSIVE_LOAD (BCE_CP_LOAD | BCE_LEVEL_EXCESSIVE) 130 131#define BCE_WARN_SEND (BCE_CP_SEND | BCE_LEVEL_WARN) 132#define BCE_INFO_SEND (BCE_CP_SEND | BCE_LEVEL_INFO) 133#define BCE_VERBOSE_SEND (BCE_CP_SEND | BCE_LEVEL_VERBOSE) 134#define BCE_EXCESSIVE_SEND (BCE_CP_SEND | BCE_LEVEL_EXCESSIVE) 135 136#define BCE_WARN_RECV (BCE_CP_RECV | BCE_LEVEL_WARN) 137#define BCE_INFO_RECV (BCE_CP_RECV | BCE_LEVEL_INFO) 138#define BCE_VERBOSE_RECV (BCE_CP_RECV | BCE_LEVEL_VERBOSE) 139#define BCE_EXCESSIVE_RECV (BCE_CP_RECV | BCE_LEVEL_EXCESSIVE) 140 141#define BCE_WARN_INTR (BCE_CP_INTR | BCE_LEVEL_WARN) 142#define BCE_INFO_INTR (BCE_CP_INTR | BCE_LEVEL_INFO) 143#define BCE_VERBOSE_INTR (BCE_CP_INTR | BCE_LEVEL_VERBOSE) 144#define BCE_EXCESSIVE_INTR (BCE_CP_INTR | BCE_LEVEL_EXCESSIVE) 145 146#define BCE_WARN_UNLOAD (BCE_CP_UNLOAD | BCE_LEVEL_WARN) 147#define BCE_INFO_UNLOAD (BCE_CP_UNLOAD | BCE_LEVEL_INFO) 148#define BCE_VERBOSE_UNLOAD (BCE_CP_UNLOAD | BCE_LEVEL_VERBOSE) 149#define BCE_EXCESSIVE_UNLOAD (BCE_CP_UNLOAD | BCE_LEVEL_EXCESSIVE) 150 151#define BCE_WARN_RESET (BCE_CP_RESET | BCE_LEVEL_WARN) 152#define BCE_INFO_RESET (BCE_CP_RESET | BCE_LEVEL_INFO) 153#define BCE_VERBOSE_RESET (BCE_CP_RESET | BCE_LEVEL_VERBOSE) 154#define BCE_EXCESSIVE_RESET (BCE_CP_RESET | BCE_LEVEL_EXCESSIVE) 155 156#define BCE_WARN_PHY (BCE_CP_PHY | BCE_LEVEL_WARN) 157#define BCE_INFO_PHY (BCE_CP_PHY | BCE_LEVEL_INFO) 158#define BCE_VERBOSE_PHY (BCE_CP_PHY | BCE_LEVEL_VERBOSE) 159#define BCE_EXCESSIVE_PHY (BCE_CP_PHY | BCE_LEVEL_EXCESSIVE) 160 161#define BCE_WARN_NVRAM (BCE_CP_NVRAM | BCE_LEVEL_WARN) 162#define BCE_INFO_NVRAM (BCE_CP_NVRAM | BCE_LEVEL_INFO) 163#define BCE_VERBOSE_NVRAM (BCE_CP_NVRAM | BCE_LEVEL_VERBOSE) 164#define BCE_EXCESSIVE_NVRAM (BCE_CP_NVRAM | BCE_LEVEL_EXCESSIVE) 165 166#define BCE_WARN_FIRMWARE (BCE_CP_FIRMWARE | BCE_LEVEL_WARN) 167#define BCE_INFO_FIRMWARE (BCE_CP_FIRMWARE | BCE_LEVEL_INFO) 168#define BCE_VERBOSE_FIRMWARE (BCE_CP_FIRMWARE | BCE_LEVEL_VERBOSE) 169#define BCE_EXCESSIVE_FIRMWARE (BCE_CP_FIRMWARE | BCE_LEVEL_EXCESSIVE) 170 171#define BCE_WARN_MISC (BCE_CP_MISC | BCE_LEVEL_WARN) 172#define BCE_INFO_MISC (BCE_CP_MISC | BCE_LEVEL_INFO) 173#define BCE_VERBOSE_MISC (BCE_CP_MISC | BCE_LEVEL_VERBOSE) 174#define BCE_EXCESSIVE_MISC (BCE_CP_MISC | BCE_LEVEL_EXCESSIVE) 175 176#define BCE_WARN_SPECIAL (BCE_CP_SPECIAL | BCE_LEVEL_WARN) 177#define BCE_INFO_SPECIAL (BCE_CP_SPECIAL | BCE_LEVEL_INFO) 178#define BCE_VERBOSE_SPECIAL (BCE_CP_SPECIAL | BCE_LEVEL_VERBOSE) 179#define BCE_EXCESSIVE_SPECIAL (BCE_CP_SPECIAL | BCE_LEVEL_EXCESSIVE) 180 181#define BCE_FATAL (BCE_CP_ALL | BCE_LEVEL_FATAL) 182#define BCE_WARN (BCE_CP_ALL | BCE_LEVEL_WARN) 183#define BCE_INFO (BCE_CP_ALL | BCE_LEVEL_INFO) 184#define BCE_VERBOSE (BCE_CP_ALL | BCE_LEVEL_VERBOSE) 185#define BCE_EXCESSIVE (BCE_CP_ALL | BCE_LEVEL_EXCESSIVE) 186 187#define BCE_CODE_PATH(cp) ((cp & BCE_CP_MASK) & bce_debug) 188#define BCE_MSG_LEVEL(lv) ((lv & BCE_LEVEL_MASK) <= (bce_debug & BCE_LEVEL_MASK)) 189#define BCE_LOG_MSG(m) (BCE_CODE_PATH(m) && BCE_MSG_LEVEL(m)) 190 191#ifdef BCE_DEBUG 192 193/* Print a message based on the logging level and code path. */ 194#define DBPRINT(sc, level, format, args...) \ 195 if (BCE_LOG_MSG(level)) { \ 196 device_printf(sc->bce_dev, format, ## args); \ 197 } 198 199/* Runs a particular command based on the logging level and code path. */ 200#define DBRUN(m, args...) \ 201 if (BCE_LOG_MSG(m)) { \ 202 args; \ 203 } 204 205/* Runs a particular command based on the logging level. */ 206#define DBRUNLV(level, args...) \ 207 if (BCE_MSG_LEVEL(level)) { \ 208 args; \ 209 } 210 211/* Runs a particular command based on the code path. */ 212#define DBRUNCP(cp, args...) \ 213 if (BCE_CODE_PATH(cp)) { \ 214 args; \ 215 } 216 217/* Runs a particular command based on a condition. */ 218#define DBRUNIF(cond, args...) \ 219 if (cond) { \ 220 args; \ 221 } 222 223/* Needed for random() function which is only used in debugging. */ 224#include <sys/random.h> 225 226/* Returns FALSE in "defects" per 2^31 - 1 calls, otherwise returns TRUE. */ 227#define DB_RANDOMFALSE(defects) (random() > defects) 228#define DB_OR_RANDOMFALSE(defects) || (random() > defects) 229#define DB_AND_RANDOMFALSE(defects) && (random() > ddfects) 230 231/* Returns TRUE in "defects" per 2^31 - 1 calls, otherwise returns FALSE. */ 232#define DB_RANDOMTRUE(defects) (random() < defects) 233#define DB_OR_RANDOMTRUE(defects) || (random() < defects) 234#define DB_AND_RANDOMTRUE(defects) && (random() < defects) 235 236#else 237 238#define DBPRINT(level, format, args...) 239#define DBRUN(m, args...) 240#define DBRUNLV(level, args...) 241#define DBRUNCP(cp, args...) 242#define DBRUNIF(cond, args...) 243#define DB_RANDOMFALSE(defects) 244#define DB_OR_RANDOMFALSE(percent) 245#define DB_AND_RANDOMFALSE(percent) 246#define DB_RANDOMTRUE(defects) 247#define DB_OR_RANDOMTRUE(percent) 248#define DB_AND_RANDOMTRUE(percent) 249 250#endif /* BCE_DEBUG */ 251 252 253/****************************************************************************/ 254/* Device identification definitions. */ 255/****************************************************************************/ 256#define BRCM_VENDORID 0x14E4 257#define BRCM_DEVICEID_BCM5706 0x164A 258#define BRCM_DEVICEID_BCM5706S 0x16AA 259#define BRCM_DEVICEID_BCM5708 0x164C 260#define BRCM_DEVICEID_BCM5708S 0x16AC 261 262#define HP_VENDORID 0x103C 263 264#define PCI_ANY_ID (u_int16_t) (~0U) 265 266/* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ 267 268#define BCE_CHIP_NUM(sc) (((sc)->bce_chipid) & 0xffff0000) 269#define BCE_CHIP_NUM_5706 0x57060000 270#define BCE_CHIP_NUM_5708 0x57080000 271 272#define BCE_CHIP_REV(sc) (((sc)->bce_chipid) & 0x0000f000) 273#define BCE_CHIP_REV_Ax 0x00000000 274#define BCE_CHIP_REV_Bx 0x00001000 275#define BCE_CHIP_REV_Cx 0x00002000 276 277#define BCE_CHIP_METAL(sc) (((sc)->bce_chipid) & 0x00000ff0) 278#define BCE_CHIP_BOND(bp) (((sc)->bce_chipid) & 0x0000000f) 279 280#define BCE_CHIP_ID(sc) (((sc)->bce_chipid) & 0xfffffff0) 281#define BCE_CHIP_ID_5706_A0 0x57060000 282#define BCE_CHIP_ID_5706_A1 0x57060010 283#define BCE_CHIP_ID_5706_A2 0x57060020 284#define BCE_CHIP_ID_5706_A3 0x57060030 285#define BCE_CHIP_ID_5708_A0 0x57080000 286#define BCE_CHIP_ID_5708_B0 0x57081000 287#define BCE_CHIP_ID_5708_B1 0x57081010 288#define BCE_CHIP_ID_5708_B2 0x57081020 289 290#define BCE_CHIP_BOND_ID(sc) (((sc)->bce_chipid) & 0xf) 291 292/* A serdes chip will have the first bit of the bond id set. */ 293#define BCE_CHIP_BOND_ID_SERDES_BIT 0x01 294 295 296/* shorthand one */ 297#define BCE_ASICREV(x) ((x) >> 28) 298#define BCE_ASICREV_BCM5700 0x06 299 300/* chip revisions */ 301#define BCE_CHIPREV(x) ((x) >> 24) 302#define BCE_CHIPREV_5700_AX 0x70 303#define BCE_CHIPREV_5700_BX 0x71 304#define BCE_CHIPREV_5700_CX 0x72 305#define BCE_CHIPREV_5701_AX 0x00 306 307struct bce_type { 308 u_int16_t bce_vid; 309 u_int16_t bce_did; 310 u_int16_t bce_svid; 311 u_int16_t bce_sdid; 312 char *bce_name; 313}; 314 315/****************************************************************************/ 316/* Byte order conversions. */ 317/****************************************************************************/ 318#if __FreeBSD_version >= 500000 319#define bce_htobe16(x) htobe16(x) 320#define bce_htobe32(x) htobe32(x) 321#define bce_htobe64(x) htobe64(x) 322#define bce_htole16(x) htole16(x) 323#define bce_htole32(x) htole32(x) 324#define bce_htole64(x) htole64(x) 325 326#define bce_be16toh(x) be16toh(x) 327#define bce_be32toh(x) be32toh(x) 328#define bce_be64toh(x) be64toh(x) 329#define bce_le16toh(x) le16toh(x) 330#define bce_le32toh(x) le32toh(x) 331#define bce_le64toh(x) le64toh(x) 332#else 333#define bce_htobe16(x) (x) 334#define bce_htobe32(x) (x) 335#define bce_htobe64(x) (x) 336#define bce_htole16(x) (x) 337#define bce_htole32(x) (x) 338#define bce_htole64(x) (x) 339 340#define bce_be16toh(x) (x) 341#define bce_be32toh(x) (x) 342#define bce_be64toh(x) (x) 343#define bce_le16toh(x) (x) 344#define bce_le32toh(x) (x) 345#define bce_le64toh(x) (x) 346#endif 347 348 349/****************************************************************************/ 350/* NVRAM Access */ 351/****************************************************************************/ 352 353/* Buffered flash (Atmel: AT45DB011B) specific information */ 354#define SEEPROM_PAGE_BITS 2 355#define SEEPROM_PHY_PAGE_SIZE (1 << SEEPROM_PAGE_BITS) 356#define SEEPROM_BYTE_ADDR_MASK (SEEPROM_PHY_PAGE_SIZE-1) 357#define SEEPROM_PAGE_SIZE 4 358#define SEEPROM_TOTAL_SIZE 65536 359 360#define BUFFERED_FLASH_PAGE_BITS 9 361#define BUFFERED_FLASH_PHY_PAGE_SIZE (1 << BUFFERED_FLASH_PAGE_BITS) 362#define BUFFERED_FLASH_BYTE_ADDR_MASK (BUFFERED_FLASH_PHY_PAGE_SIZE-1) 363#define BUFFERED_FLASH_PAGE_SIZE 264 364#define BUFFERED_FLASH_TOTAL_SIZE 0x21000 365 366#define SAIFUN_FLASH_PAGE_BITS 8 367#define SAIFUN_FLASH_PHY_PAGE_SIZE (1 << SAIFUN_FLASH_PAGE_BITS) 368#define SAIFUN_FLASH_BYTE_ADDR_MASK (SAIFUN_FLASH_PHY_PAGE_SIZE-1) 369#define SAIFUN_FLASH_PAGE_SIZE 256 370#define SAIFUN_FLASH_BASE_TOTAL_SIZE 65536 371 372#define ST_MICRO_FLASH_PAGE_BITS 8 373#define ST_MICRO_FLASH_PHY_PAGE_SIZE (1 << ST_MICRO_FLASH_PAGE_BITS) 374#define ST_MICRO_FLASH_BYTE_ADDR_MASK (ST_MICRO_FLASH_PHY_PAGE_SIZE-1) 375#define ST_MICRO_FLASH_PAGE_SIZE 256 376#define ST_MICRO_FLASH_BASE_TOTAL_SIZE 65536 377 378#define NVRAM_TIMEOUT_COUNT 30000 379#define BCE_FLASHDESC_MAX 64 380 381#define FLASH_STRAP_MASK (BCE_NVM_CFG1_FLASH_MODE | \ 382 BCE_NVM_CFG1_BUFFER_MODE | \ 383 BCE_NVM_CFG1_PROTECT_MODE | \ 384 BCE_NVM_CFG1_FLASH_SIZE) 385 386#define FLASH_BACKUP_STRAP_MASK (0xf << 26) 387 388struct flash_spec { 389 u32 strapping; 390 u32 config1; 391 u32 config2; 392 u32 config3; 393 u32 write1; 394 u32 buffered; 395 u32 page_bits; 396 u32 page_size; 397 u32 addr_mask; 398 u32 total_size; 399 u8 *name; 400}; 401 402 403/****************************************************************************/ 404/* Shared Memory layout */ 405/* The BCE bootcode will initialize this data area with port configurtion */ 406/* information which can be accessed by the driver. */ 407/****************************************************************************/ 408 409/* 410 * This value (in milliseconds) determines the frequency of the driver 411 * issuing the PULSE message code. The firmware monitors this periodic 412 * pulse to determine when to switch to an OS-absent mode. 413 */ 414#define DRV_PULSE_PERIOD_MS 250 415 416/* 417 * This value (in milliseconds) determines how long the driver should 418 * wait for an acknowledgement from the firmware before timing out. Once 419 * the firmware has timed out, the driver will assume there is no firmware 420 * running and there won't be any firmware-driver synchronization during a 421 * driver reset. 422 */ 423#define FW_ACK_TIME_OUT_MS 100 424 425 426#define BCE_DRV_RESET_SIGNATURE 0x00000000 427#define BCE_DRV_RESET_SIGNATURE_MAGIC 0x4841564b /* HAVK */ 428 429#define BCE_DRV_MB 0x00000004 430#define BCE_DRV_MSG_CODE 0xff000000 431#define BCE_DRV_MSG_CODE_RESET 0x01000000 432#define BCE_DRV_MSG_CODE_UNLOAD 0x02000000 433#define BCE_DRV_MSG_CODE_SHUTDOWN 0x03000000 434#define BCE_DRV_MSG_CODE_SUSPEND_WOL 0x04000000 435#define BCE_DRV_MSG_CODE_FW_TIMEOUT 0x05000000 436#define BCE_DRV_MSG_CODE_PULSE 0x06000000 437#define BCE_DRV_MSG_CODE_DIAG 0x07000000 438#define BCE_DRV_MSG_CODE_SUSPEND_NO_WOL 0x09000000 439#define BCE_DRV_MSG_CODE_UNLOAD_LNK_DN 0x0b000000 440#define BCE_DRV_MSG_CODE_CMD_SET_LINK 0x10000000 441 442#define BCE_DRV_MSG_DATA 0x00ff0000 443#define BCE_DRV_MSG_DATA_WAIT0 0x00010000 444#define BCE_DRV_MSG_DATA_WAIT1 0x00020000 445#define BCE_DRV_MSG_DATA_WAIT2 0x00030000 446#define BCE_DRV_MSG_DATA_WAIT3 0x00040000 447 448#define BCE_DRV_MSG_SEQ 0x0000ffff 449 450#define BCE_FW_MB 0x00000008 451#define BCE_FW_MSG_ACK 0x0000ffff 452#define BCE_FW_MSG_STATUS_MASK 0x00ff0000 453#define BCE_FW_MSG_STATUS_OK 0x00000000 454#define BCE_FW_MSG_STATUS_FAILURE 0x00ff0000 455 456#define BCE_LINK_STATUS 0x0000000c 457#define BCE_LINK_STATUS_INIT_VALUE 0xffffffff 458#define BCE_LINK_STATUS_LINK_UP 0x1 459#define BCE_LINK_STATUS_LINK_DOWN 0x0 460#define BCE_LINK_STATUS_SPEED_MASK 0x1e 461#define BCE_LINK_STATUS_AN_INCOMPLETE (0<<1) 462#define BCE_LINK_STATUS_10HALF (1<<1) 463#define BCE_LINK_STATUS_10FULL (2<<1) 464#define BCE_LINK_STATUS_100HALF (3<<1) 465#define BCE_LINK_STATUS_100BASE_T4 (4<<1) 466#define BCE_LINK_STATUS_100FULL (5<<1) 467#define BCE_LINK_STATUS_1000HALF (6<<1) 468#define BCE_LINK_STATUS_1000FULL (7<<1) 469#define BCE_LINK_STATUS_2500HALF (8<<1) 470#define BCE_LINK_STATUS_2500FULL (9<<1) 471#define BCE_LINK_STATUS_AN_ENABLED (1<<5) 472#define BCE_LINK_STATUS_AN_COMPLETE (1<<6) 473#define BCE_LINK_STATUS_PARALLEL_DET (1<<7) 474#define BCE_LINK_STATUS_RESERVED (1<<8) 475#define BCE_LINK_STATUS_PARTNER_AD_1000FULL (1<<9) 476#define BCE_LINK_STATUS_PARTNER_AD_1000HALF (1<<10) 477#define BCE_LINK_STATUS_PARTNER_AD_100BT4 (1<<11) 478#define BCE_LINK_STATUS_PARTNER_AD_100FULL (1<<12) 479#define BCE_LINK_STATUS_PARTNER_AD_100HALF (1<<13) 480#define BCE_LINK_STATUS_PARTNER_AD_10FULL (1<<14) 481#define BCE_LINK_STATUS_PARTNER_AD_10HALF (1<<15) 482#define BCE_LINK_STATUS_TX_FC_ENABLED (1<<16) 483#define BCE_LINK_STATUS_RX_FC_ENABLED (1<<17) 484#define BCE_LINK_STATUS_PARTNER_SYM_PAUSE_CAP (1<<18) 485#define BCE_LINK_STATUS_PARTNER_ASYM_PAUSE_CAP (1<<19) 486#define BCE_LINK_STATUS_SERDES_LINK (1<<20) 487#define BCE_LINK_STATUS_PARTNER_AD_2500FULL (1<<21) 488#define BCE_LINK_STATUS_PARTNER_AD_2500HALF (1<<22) 489 490#define BCE_DRV_PULSE_MB 0x00000010 491#define BCE_DRV_PULSE_SEQ_MASK 0x00007fff 492 493/* Indicate to the firmware not to go into the 494 * OS absent when it is not getting driver pulse. 495 * This is used for debugging. */ 496#define BCE_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE 0x00080000 497 498#define BCE_DEV_INFO_SIGNATURE 0x00000020 499#define BCE_DEV_INFO_SIGNATURE_MAGIC 0x44564900 500#define BCE_DEV_INFO_SIGNATURE_MAGIC_MASK 0xffffff00 501#define BCE_DEV_INFO_FEATURE_CFG_VALID 0x01 502#define BCE_DEV_INFO_SECONDARY_PORT 0x80 503#define BCE_DEV_INFO_DRV_ALWAYS_ALIVE 0x40 504 505#define BCE_SHARED_HW_CFG_PART_NUM 0x00000024 506 507#define BCE_SHARED_HW_CFG_POWER_DISSIPATED 0x00000034 508#define BCE_SHARED_HW_CFG_POWER_STATE_D3_MASK 0xff000000 509#define BCE_SHARED_HW_CFG_POWER_STATE_D2_MASK 0xff0000 510#define BCE_SHARED_HW_CFG_POWER_STATE_D1_MASK 0xff00 511#define BCE_SHARED_HW_CFG_POWER_STATE_D0_MASK 0xff 512 513#define BCE_SHARED_HW_CFG_POWER_CONSUMED 0x00000038 514#define BCE_SHARED_HW_CFG_CONFIG 0x0000003c 515#define BCE_SHARED_HW_CFG_DESIGN_NIC 0 516#define BCE_SHARED_HW_CFG_DESIGN_LOM 0x1 517#define BCE_SHARED_HW_CFG_PHY_COPPER 0 518#define BCE_SHARED_HW_CFG_PHY_FIBER 0x2 519#define BCE_SHARED_HW_CFG_PHY_2_5G 0x20 520#define BCE_SHARED_HW_CFG_PHY_BACKPLANE 0x40 521#define BCE_SHARED_HW_CFG_LED_MODE_SHIFT_BITS 8 522#define BCE_SHARED_HW_CFG_LED_MODE_MASK 0x300 523#define BCE_SHARED_HW_CFG_LED_MODE_MAC 0 524#define BCE_SHARED_HW_CFG_LED_MODE_GPHY1 0x100 525#define BCE_SHARED_HW_CFG_LED_MODE_GPHY2 0x200 526 527#define BCE_SHARED_HW_CFG_CONFIG2 0x00000040 528#define BCE_SHARED_HW_CFG2_NVM_SIZE_MASK 0x00fff000 529 530#define BCE_DEV_INFO_BC_REV 0x0000004c 531 532#define BCE_PORT_HW_CFG_MAC_UPPER 0x00000050 533#define BCE_PORT_HW_CFG_UPPERMAC_MASK 0xffff 534 535#define BCE_PORT_HW_CFG_MAC_LOWER 0x00000054 536#define BCE_PORT_HW_CFG_CONFIG 0x00000058 537#define BCE_PORT_HW_CFG_CFG_TXCTL3_MASK 0x0000ffff 538#define BCE_PORT_HW_CFG_CFG_DFLT_LINK_MASK 0x001f0000 539#define BCE_PORT_HW_CFG_CFG_DFLT_LINK_AN 0x00000000 540#define BCE_PORT_HW_CFG_CFG_DFLT_LINK_1G 0x00030000 541#define BCE_PORT_HW_CFG_CFG_DFLT_LINK_2_5G 0x00040000 542 543#define BCE_PORT_HW_CFG_IMD_MAC_A_UPPER 0x00000068 544#define BCE_PORT_HW_CFG_IMD_MAC_A_LOWER 0x0000006c 545#define BCE_PORT_HW_CFG_IMD_MAC_B_UPPER 0x00000070 546#define BCE_PORT_HW_CFG_IMD_MAC_B_LOWER 0x00000074 547#define BCE_PORT_HW_CFG_ISCSI_MAC_UPPER 0x00000078 548#define BCE_PORT_HW_CFG_ISCSI_MAC_LOWER 0x0000007c 549 550#define BCE_DEV_INFO_PER_PORT_HW_CONFIG2 0x000000b4 551 552#define BCE_DEV_INFO_FORMAT_REV 0x000000c4 553#define BCE_DEV_INFO_FORMAT_REV_MASK 0xff000000 554#define BCE_DEV_INFO_FORMAT_REV_ID ('A' << 24) 555 556#define BCE_SHARED_FEATURE 0x000000c8 557#define BCE_SHARED_FEATURE_MASK 0xffffffff 558 559#define BCE_PORT_FEATURE 0x000000d8 560#define BCE_PORT2_FEATURE 0x00000014c 561#define BCE_PORT_FEATURE_WOL_ENABLED 0x01000000 562#define BCE_PORT_FEATURE_MBA_ENABLED 0x02000000 563#define BCE_PORT_FEATURE_ASF_ENABLED 0x04000000 564#define BCE_PORT_FEATURE_IMD_ENABLED 0x08000000 565#define BCE_PORT_FEATURE_BAR1_SIZE_MASK 0xf 566#define BCE_PORT_FEATURE_BAR1_SIZE_DISABLED 0x0 567#define BCE_PORT_FEATURE_BAR1_SIZE_64K 0x1 568#define BCE_PORT_FEATURE_BAR1_SIZE_128K 0x2 569#define BCE_PORT_FEATURE_BAR1_SIZE_256K 0x3 570#define BCE_PORT_FEATURE_BAR1_SIZE_512K 0x4 571#define BCE_PORT_FEATURE_BAR1_SIZE_1M 0x5 572#define BCE_PORT_FEATURE_BAR1_SIZE_2M 0x6 573#define BCE_PORT_FEATURE_BAR1_SIZE_4M 0x7 574#define BCE_PORT_FEATURE_BAR1_SIZE_8M 0x8 575#define BCE_PORT_FEATURE_BAR1_SIZE_16M 0x9 576#define BCE_PORT_FEATURE_BAR1_SIZE_32M 0xa 577#define BCE_PORT_FEATURE_BAR1_SIZE_64M 0xb 578#define BCE_PORT_FEATURE_BAR1_SIZE_128M 0xc 579#define BCE_PORT_FEATURE_BAR1_SIZE_256M 0xd 580#define BCE_PORT_FEATURE_BAR1_SIZE_512M 0xe 581#define BCE_PORT_FEATURE_BAR1_SIZE_1G 0xf 582 583#define BCE_PORT_FEATURE_WOL 0xdc 584#define BCE_PORT2_FEATURE_WOL 0x150 585#define BCE_PORT_FEATURE_WOL_DEFAULT_SHIFT_BITS 4 586#define BCE_PORT_FEATURE_WOL_DEFAULT_MASK 0x30 587#define BCE_PORT_FEATURE_WOL_DEFAULT_DISABLE 0 588#define BCE_PORT_FEATURE_WOL_DEFAULT_MAGIC 0x10 589#define BCE_PORT_FEATURE_WOL_DEFAULT_ACPI 0x20 590#define BCE_PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI 0x30 591#define BCE_PORT_FEATURE_WOL_LINK_SPEED_MASK 0xf 592#define BCE_PORT_FEATURE_WOL_LINK_SPEED_AUTONEG 0 593#define BCE_PORT_FEATURE_WOL_LINK_SPEED_10HALF 1 594#define BCE_PORT_FEATURE_WOL_LINK_SPEED_10FULL 2 595#define BCE_PORT_FEATURE_WOL_LINK_SPEED_100HALF 3 596#define BCE_PORT_FEATURE_WOL_LINK_SPEED_100FULL 4 597#define BCE_PORT_FEATURE_WOL_LINK_SPEED_1000HALF 5 598#define BCE_PORT_FEATURE_WOL_LINK_SPEED_1000FULL 6 599#define BCE_PORT_FEATURE_WOL_AUTONEG_ADVERTISE_1000 0x40 600#define BCE_PORT_FEATURE_WOL_RESERVED_PAUSE_CAP 0x400 601#define BCE_PORT_FEATURE_WOL_RESERVED_ASYM_PAUSE_CAP 0x800 602 603#define BCE_PORT_FEATURE_MBA 0xe0 604#define BCE_PORT2_FEATURE_MBA 0x154 605#define BCE_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT_BITS 0 606#define BCE_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x3 607#define BCE_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0 608#define BCE_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 1 609#define BCE_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 2 610#define BCE_PORT_FEATURE_MBA_LINK_SPEED_SHIFT_BITS 2 611#define BCE_PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3c 612#define BCE_PORT_FEATURE_MBA_LINK_SPEED_AUTONEG 0 613#define BCE_PORT_FEATURE_MBA_LINK_SPEED_10HALF 0x4 614#define BCE_PORT_FEATURE_MBA_LINK_SPEED_10FULL 0x8 615#define BCE_PORT_FEATURE_MBA_LINK_SPEED_100HALF 0xc 616#define BCE_PORT_FEATURE_MBA_LINK_SPEED_100FULL 0x10 617#define BCE_PORT_FEATURE_MBA_LINK_SPEED_1000HALF 0x14 618#define BCE_PORT_FEATURE_MBA_LINK_SPEED_1000FULL 0x18 619#define BCE_PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x40 620#define BCE_PORT_FEATURE_MBA_HOTKEY_CTRL_S 0 621#define BCE_PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x80 622#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT_BITS 8 623#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0xff00 624#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0 625#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_1K 0x100 626#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x200 627#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x300 628#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x400 629#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x500 630#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x600 631#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x700 632#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x800 633#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x900 634#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0xa00 635#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0xb00 636#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0xc00 637#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0xd00 638#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0xe00 639#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0xf00 640#define BCE_PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT_BITS 16 641#define BCE_PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0xf0000 642#define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT_BITS 20 643#define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x300000 644#define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0 645#define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x100000 646#define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x200000 647#define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x300000 648 649#define BCE_PORT_FEATURE_IMD 0xe4 650#define BCE_PORT2_FEATURE_IMD 0x158 651#define BCE_PORT_FEATURE_IMD_LINK_OVERRIDE_DEFAULT 0 652#define BCE_PORT_FEATURE_IMD_LINK_OVERRIDE_ENABLE 1 653 654#define BCE_PORT_FEATURE_VLAN 0xe8 655#define BCE_PORT2_FEATURE_VLAN 0x15c 656#define BCE_PORT_FEATURE_MBA_VLAN_TAG_MASK 0xffff 657#define BCE_PORT_FEATURE_MBA_VLAN_ENABLE 0x10000 658 659#define BCE_BC_STATE_RESET_TYPE 0x000001c0 660#define BCE_BC_STATE_RESET_TYPE_SIG 0x00005254 661#define BCE_BC_STATE_RESET_TYPE_SIG_MASK 0x0000ffff 662#define BCE_BC_STATE_RESET_TYPE_NONE (BCE_BC_STATE_RESET_TYPE_SIG | \ 663 0x00010000) 664#define BCE_BC_STATE_RESET_TYPE_PCI (BCE_BC_STATE_RESET_TYPE_SIG | \ 665 0x00020000) 666#define BCE_BC_STATE_RESET_TYPE_VAUX (BCE_BC_STATE_RESET_TYPE_SIG | \ 667 0x00030000) 668#define BCE_BC_STATE_RESET_TYPE_DRV_MASK DRV_MSG_CODE 669#define BCE_BC_STATE_RESET_TYPE_DRV_RESET (BCE_BC_STATE_RESET_TYPE_SIG | \ 670 DRV_MSG_CODE_RESET) 671#define BCE_BC_STATE_RESET_TYPE_DRV_UNLOAD (BCE_BC_STATE_RESET_TYPE_SIG | \ 672 DRV_MSG_CODE_UNLOAD) 673#define BCE_BC_STATE_RESET_TYPE_DRV_SHUTDOWN (BCE_BC_STATE_RESET_TYPE_SIG | \ 674 DRV_MSG_CODE_SHUTDOWN) 675#define BCE_BC_STATE_RESET_TYPE_DRV_WOL (BCE_BC_STATE_RESET_TYPE_SIG | \ 676 DRV_MSG_CODE_WOL) 677#define BCE_BC_STATE_RESET_TYPE_DRV_DIAG (BCE_BC_STATE_RESET_TYPE_SIG | \ 678 DRV_MSG_CODE_DIAG) 679#define BCE_BC_STATE_RESET_TYPE_VALUE(msg) (BCE_BC_STATE_RESET_TYPE_SIG | \ 680 (msg)) 681 682#define BCE_BC_RESET_TYPE 0x000001c0 683 684#define BCE_BC_STATE 0x000001c4 685#define BCE_BC_STATE_ERR_MASK 0x0000ff00 686#define BCE_BC_STATE_SIGN 0x42530000 687#define BCE_BC_STATE_SIGN_MASK 0xffff0000 688#define BCE_BC_STATE_BC1_START (BCE_BC_STATE_SIGN | 0x1) 689#define BCE_BC_STATE_GET_NVM_CFG1 (BCE_BC_STATE_SIGN | 0x2) 690#define BCE_BC_STATE_PROG_BAR (BCE_BC_STATE_SIGN | 0x3) 691#define BCE_BC_STATE_INIT_VID (BCE_BC_STATE_SIGN | 0x4) 692#define BCE_BC_STATE_GET_NVM_CFG2 (BCE_BC_STATE_SIGN | 0x5) 693#define BCE_BC_STATE_APPLY_WKARND (BCE_BC_STATE_SIGN | 0x6) 694#define BCE_BC_STATE_LOAD_BC2 (BCE_BC_STATE_SIGN | 0x7) 695#define BCE_BC_STATE_GOING_BC2 (BCE_BC_STATE_SIGN | 0x8) 696#define BCE_BC_STATE_GOING_DIAG (BCE_BC_STATE_SIGN | 0x9) 697#define BCE_BC_STATE_RT_FINAL_INIT (BCE_BC_STATE_SIGN | 0x81) 698#define BCE_BC_STATE_RT_WKARND (BCE_BC_STATE_SIGN | 0x82) 699#define BCE_BC_STATE_RT_DRV_PULSE (BCE_BC_STATE_SIGN | 0x83) 700#define BCE_BC_STATE_RT_FIOEVTS (BCE_BC_STATE_SIGN | 0x84) 701#define BCE_BC_STATE_RT_DRV_CMD (BCE_BC_STATE_SIGN | 0x85) 702#define BCE_BC_STATE_RT_LOW_POWER (BCE_BC_STATE_SIGN | 0x86) 703#define BCE_BC_STATE_RT_SET_WOL (BCE_BC_STATE_SIGN | 0x87) 704#define BCE_BC_STATE_RT_OTHER_FW (BCE_BC_STATE_SIGN | 0x88) 705#define BCE_BC_STATE_RT_GOING_D3 (BCE_BC_STATE_SIGN | 0x89) 706#define BCE_BC_STATE_ERR_BAD_VERSION (BCE_BC_STATE_SIGN | 0x0100) 707#define BCE_BC_STATE_ERR_BAD_BC2_CRC (BCE_BC_STATE_SIGN | 0x0200) 708#define BCE_BC_STATE_ERR_BC1_LOOP (BCE_BC_STATE_SIGN | 0x0300) 709#define BCE_BC_STATE_ERR_UNKNOWN_CMD (BCE_BC_STATE_SIGN | 0x0400) 710#define BCE_BC_STATE_ERR_DRV_DEAD (BCE_BC_STATE_SIGN | 0x0500) 711#define BCE_BC_STATE_ERR_NO_RXP (BCE_BC_STATE_SIGN | 0x0600) 712#define BCE_BC_STATE_ERR_TOO_MANY_RBUF (BCE_BC_STATE_SIGN | 0x0700) 713 714#define BCE_BC_CONDITION 0x000001c8 715 716#define BCE_BC_STATE_DEBUG_CMD 0x1dc 717#define BCE_BC_STATE_BC_DBG_CMD_SIGNATURE 0x42440000 718#define BCE_BC_STATE_BC_DBG_CMD_SIGNATURE_MASK 0xffff0000 719#define BCE_BC_STATE_BC_DBG_CMD_LOOP_CNT_MASK 0xffff 720#define BCE_BC_STATE_BC_DBG_CMD_LOOP_INFINITE 0xffff 721 722#define HOST_VIEW_SHMEM_BASE 0x167c00 723 724/* 725 * PCI registers defined in the PCI 2.2 spec. 726 */ 727#define BCE_PCI_PCIX_CMD 0x42 728 729 730/****************************************************************************/ 731/* Convenience definitions. */ 732/****************************************************************************/ 733#define BCE_PRINTF(fmt, args...) device_printf(sc->bce_dev, fmt, ##args) 734 735#define BCE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->bce_mtx, _name, MTX_NETWORK_LOCK, MTX_DEF) 736#define BCE_LOCK(_sc) mtx_lock(&(_sc)->bce_mtx) 737#define BCE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->bce_mtx, MA_OWNED) 738#define BCE_UNLOCK(_sc) mtx_unlock(&(_sc)->bce_mtx) 739#define BCE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->bce_mtx) 740 741#define REG_WR(sc, reg, val) bus_space_write_4(sc->bce_btag, sc->bce_bhandle, reg, val) 742#define REG_WR16(sc, reg, val) bus_space_write_2(sc->bce_btag, sc->bce_bhandle, reg, val) 743#define REG_RD(sc, reg) bus_space_read_4(sc->bce_btag, sc->bce_bhandle, reg) 744#define REG_RD_IND(sc, offset) bce_reg_rd_ind(sc, offset) 745#define REG_WR_IND(sc, offset, val) bce_reg_wr_ind(sc, offset, val) 746#define CTX_WR(sc, cid_addr, offset, val) bce_ctx_wr(sc, cid_addr, offset, val) 747#define BCE_SETBIT(sc, reg, x) REG_WR(sc, reg, (REG_RD(sc, reg) | (x))) 748#define BCE_CLRBIT(sc, reg, x) REG_WR(sc, reg, (REG_RD(sc, reg) & ~(x))) 749#define PCI_SETBIT(dev, reg, x, s) pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | (x)), s) 750#define PCI_CLRBIT(dev, reg, x, s) pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s) 751 752#define BCE_STATS(x) (u_long) stats->stat_ ## x ## _lo 753#if (BUS_SPACE_MAXADDR > 0xFFFFFFFF) 754#define BCE_ADDR_LO(y) ((u64) (y) & 0xFFFFFFFF) 755#define BCE_ADDR_HI(y) ((u64) (y) >> 32) 756#else 757#define BCE_ADDR_LO(y) ((u32)y) 758#define BCE_ADDR_HI(y) (0) 759#endif 760 761 762/* 763 * The following data structures are generated from RTL code. 764 * Do not modify any values below this line. 765 */ 766 767/****************************************************************************/ 768/* Do not modify any of the following data structures, they are generated */ 769/* from RTL code. */ 770/* */ 771/* Begin machine generated definitions. */ 772/****************************************************************************/ 773 774/* 775 * tx_bd definition 776 */ 777struct tx_bd { 778 u32 tx_bd_haddr_hi; 779 u32 tx_bd_haddr_lo; 780 u32 tx_bd_mss_nbytes; 781 u16 tx_bd_flags; 782 u16 tx_bd_vlan_tag; 783 #define TX_BD_FLAGS_CONN_FAULT (1<<0) 784 #define TX_BD_FLAGS_TCP_UDP_CKSUM (1<<1) 785 #define TX_BD_FLAGS_IP_CKSUM (1<<2) 786 #define TX_BD_FLAGS_VLAN_TAG (1<<3) 787 #define TX_BD_FLAGS_COAL_NOW (1<<4) 788 #define TX_BD_FLAGS_DONT_GEN_CRC (1<<5) 789 #define TX_BD_FLAGS_END (1<<6) 790 #define TX_BD_FLAGS_START (1<<7) 791 #define TX_BD_FLAGS_SW_OPTION_WORD (0x1f<<8) 792 #define TX_BD_FLAGS_SW_FLAGS (1<<13) 793 #define TX_BD_FLAGS_SW_SNAP (1<<14) 794 #define TX_BD_FLAGS_SW_LSO (1<<15) 795 796}; 797 798 799/* 800 * rx_bd definition 801 */ 802struct rx_bd { 803 u32 rx_bd_haddr_hi; 804 u32 rx_bd_haddr_lo; 805 u32 rx_bd_len; 806 u32 rx_bd_flags; 807 #define RX_BD_FLAGS_NOPUSH (1<<0) 808 #define RX_BD_FLAGS_DUMMY (1<<1) 809 #define RX_BD_FLAGS_END (1<<2) 810 #define RX_BD_FLAGS_START (1<<3) 811 812}; 813 814 815/* 816 * status_block definition 817 */ 818struct status_block { 819 u32 status_attn_bits; 820 #define STATUS_ATTN_BITS_LINK_STATE (1L<<0) 821 #define STATUS_ATTN_BITS_TX_SCHEDULER_ABORT (1L<<1) 822 #define STATUS_ATTN_BITS_TX_BD_READ_ABORT (1L<<2) 823 #define STATUS_ATTN_BITS_TX_BD_CACHE_ABORT (1L<<3) 824 #define STATUS_ATTN_BITS_TX_PROCESSOR_ABORT (1L<<4) 825 #define STATUS_ATTN_BITS_TX_DMA_ABORT (1L<<5) 826 #define STATUS_ATTN_BITS_TX_PATCHUP_ABORT (1L<<6) 827 #define STATUS_ATTN_BITS_TX_ASSEMBLER_ABORT (1L<<7) 828 #define STATUS_ATTN_BITS_RX_PARSER_MAC_ABORT (1L<<8) 829 #define STATUS_ATTN_BITS_RX_PARSER_CATCHUP_ABORT (1L<<9) 830 #define STATUS_ATTN_BITS_RX_MBUF_ABORT (1L<<10) 831 #define STATUS_ATTN_BITS_RX_LOOKUP_ABORT (1L<<11) 832 #define STATUS_ATTN_BITS_RX_PROCESSOR_ABORT (1L<<12) 833 #define STATUS_ATTN_BITS_RX_V2P_ABORT (1L<<13) 834 #define STATUS_ATTN_BITS_RX_BD_CACHE_ABORT (1L<<14) 835 #define STATUS_ATTN_BITS_RX_DMA_ABORT (1L<<15) 836 #define STATUS_ATTN_BITS_COMPLETION_ABORT (1L<<16) 837 #define STATUS_ATTN_BITS_HOST_COALESCE_ABORT (1L<<17) 838 #define STATUS_ATTN_BITS_MAILBOX_QUEUE_ABORT (1L<<18) 839 #define STATUS_ATTN_BITS_CONTEXT_ABORT (1L<<19) 840 #define STATUS_ATTN_BITS_CMD_SCHEDULER_ABORT (1L<<20) 841 #define STATUS_ATTN_BITS_CMD_PROCESSOR_ABORT (1L<<21) 842 #define STATUS_ATTN_BITS_MGMT_PROCESSOR_ABORT (1L<<22) 843 #define STATUS_ATTN_BITS_MAC_ABORT (1L<<23) 844 #define STATUS_ATTN_BITS_TIMER_ABORT (1L<<24) 845 #define STATUS_ATTN_BITS_DMAE_ABORT (1L<<25) 846 #define STATUS_ATTN_BITS_FLSH_ABORT (1L<<26) 847 #define STATUS_ATTN_BITS_GRC_ABORT (1L<<27) 848 #define STATUS_ATTN_BITS_PARITY_ERROR (1L<<31) 849 850 u32 status_attn_bits_ack; 851#if defined(__BIG_ENDIAN) 852 u16 status_tx_quick_consumer_index0; 853 u16 status_tx_quick_consumer_index1; 854 u16 status_tx_quick_consumer_index2; 855 u16 status_tx_quick_consumer_index3; 856 u16 status_rx_quick_consumer_index0; 857 u16 status_rx_quick_consumer_index1; 858 u16 status_rx_quick_consumer_index2; 859 u16 status_rx_quick_consumer_index3; 860 u16 status_rx_quick_consumer_index4; 861 u16 status_rx_quick_consumer_index5; 862 u16 status_rx_quick_consumer_index6; 863 u16 status_rx_quick_consumer_index7; 864 u16 status_rx_quick_consumer_index8; 865 u16 status_rx_quick_consumer_index9; 866 u16 status_rx_quick_consumer_index10; 867 u16 status_rx_quick_consumer_index11; 868 u16 status_rx_quick_consumer_index12; 869 u16 status_rx_quick_consumer_index13; 870 u16 status_rx_quick_consumer_index14; 871 u16 status_rx_quick_consumer_index15; 872 u16 status_completion_producer_index; 873 u16 status_cmd_consumer_index; 874 u16 status_idx; 875 u16 status_unused; 876#elif defined(__LITTLE_ENDIAN) 877 u16 status_tx_quick_consumer_index1; 878 u16 status_tx_quick_consumer_index0; 879 u16 status_tx_quick_consumer_index3; 880 u16 status_tx_quick_consumer_index2; 881 u16 status_rx_quick_consumer_index1; 882 u16 status_rx_quick_consumer_index0; 883 u16 status_rx_quick_consumer_index3; 884 u16 status_rx_quick_consumer_index2; 885 u16 status_rx_quick_consumer_index5; 886 u16 status_rx_quick_consumer_index4; 887 u16 status_rx_quick_consumer_index7; 888 u16 status_rx_quick_consumer_index6; 889 u16 status_rx_quick_consumer_index9; 890 u16 status_rx_quick_consumer_index8; 891 u16 status_rx_quick_consumer_index11; 892 u16 status_rx_quick_consumer_index10; 893 u16 status_rx_quick_consumer_index13; 894 u16 status_rx_quick_consumer_index12; 895 u16 status_rx_quick_consumer_index15; 896 u16 status_rx_quick_consumer_index14; 897 u16 status_cmd_consumer_index; 898 u16 status_completion_producer_index; 899 u16 status_unused; 900 u16 status_idx; 901#endif 902}; 903 904 905/* 906 * statistics_block definition 907 */ 908struct statistics_block { 909 u32 stat_IfHCInOctets_hi; 910 u32 stat_IfHCInOctets_lo; 911 u32 stat_IfHCInBadOctets_hi; 912 u32 stat_IfHCInBadOctets_lo; 913 u32 stat_IfHCOutOctets_hi; 914 u32 stat_IfHCOutOctets_lo; 915 u32 stat_IfHCOutBadOctets_hi; 916 u32 stat_IfHCOutBadOctets_lo; 917 u32 stat_IfHCInUcastPkts_hi; 918 u32 stat_IfHCInUcastPkts_lo; 919 u32 stat_IfHCInMulticastPkts_hi; 920 u32 stat_IfHCInMulticastPkts_lo; 921 u32 stat_IfHCInBroadcastPkts_hi; 922 u32 stat_IfHCInBroadcastPkts_lo; 923 u32 stat_IfHCOutUcastPkts_hi; 924 u32 stat_IfHCOutUcastPkts_lo; 925 u32 stat_IfHCOutMulticastPkts_hi; 926 u32 stat_IfHCOutMulticastPkts_lo; 927 u32 stat_IfHCOutBroadcastPkts_hi; 928 u32 stat_IfHCOutBroadcastPkts_lo; 929 u32 stat_emac_tx_stat_dot3statsinternalmactransmiterrors; 930 u32 stat_Dot3StatsCarrierSenseErrors; 931 u32 stat_Dot3StatsFCSErrors; 932 u32 stat_Dot3StatsAlignmentErrors; 933 u32 stat_Dot3StatsSingleCollisionFrames; 934 u32 stat_Dot3StatsMultipleCollisionFrames; 935 u32 stat_Dot3StatsDeferredTransmissions; 936 u32 stat_Dot3StatsExcessiveCollisions; 937 u32 stat_Dot3StatsLateCollisions; 938 u32 stat_EtherStatsCollisions; 939 u32 stat_EtherStatsFragments; 940 u32 stat_EtherStatsJabbers; 941 u32 stat_EtherStatsUndersizePkts; 942 u32 stat_EtherStatsOverrsizePkts; 943 u32 stat_EtherStatsPktsRx64Octets; 944 u32 stat_EtherStatsPktsRx65Octetsto127Octets; 945 u32 stat_EtherStatsPktsRx128Octetsto255Octets; 946 u32 stat_EtherStatsPktsRx256Octetsto511Octets; 947 u32 stat_EtherStatsPktsRx512Octetsto1023Octets; 948 u32 stat_EtherStatsPktsRx1024Octetsto1522Octets; 949 u32 stat_EtherStatsPktsRx1523Octetsto9022Octets; 950 u32 stat_EtherStatsPktsTx64Octets; 951 u32 stat_EtherStatsPktsTx65Octetsto127Octets; 952 u32 stat_EtherStatsPktsTx128Octetsto255Octets; 953 u32 stat_EtherStatsPktsTx256Octetsto511Octets; 954 u32 stat_EtherStatsPktsTx512Octetsto1023Octets; 955 u32 stat_EtherStatsPktsTx1024Octetsto1522Octets; 956 u32 stat_EtherStatsPktsTx1523Octetsto9022Octets; 957 u32 stat_XonPauseFramesReceived; 958 u32 stat_XoffPauseFramesReceived; 959 u32 stat_OutXonSent; 960 u32 stat_OutXoffSent; 961 u32 stat_FlowControlDone; 962 u32 stat_MacControlFramesReceived; 963 u32 stat_XoffStateEntered; 964 u32 stat_IfInFramesL2FilterDiscards; 965 u32 stat_IfInRuleCheckerDiscards; 966 u32 stat_IfInFTQDiscards; 967 u32 stat_IfInMBUFDiscards; 968 u32 stat_IfInRuleCheckerP4Hit; 969 u32 stat_CatchupInRuleCheckerDiscards; 970 u32 stat_CatchupInFTQDiscards; 971 u32 stat_CatchupInMBUFDiscards; 972 u32 stat_CatchupInRuleCheckerP4Hit; 973 u32 stat_GenStat00; 974 u32 stat_GenStat01; 975 u32 stat_GenStat02; 976 u32 stat_GenStat03; 977 u32 stat_GenStat04; 978 u32 stat_GenStat05; 979 u32 stat_GenStat06; 980 u32 stat_GenStat07; 981 u32 stat_GenStat08; 982 u32 stat_GenStat09; 983 u32 stat_GenStat10; 984 u32 stat_GenStat11; 985 u32 stat_GenStat12; 986 u32 stat_GenStat13; 987 u32 stat_GenStat14; 988 u32 stat_GenStat15; 989}; 990 991 992/* 993 * l2_fhdr definition 994 */ 995struct l2_fhdr { 996 u32 l2_fhdr_status; 997 #define L2_FHDR_STATUS_RULE_CLASS (0x7<<0) 998 #define L2_FHDR_STATUS_RULE_P2 (1<<3) 999 #define L2_FHDR_STATUS_RULE_P3 (1<<4) 1000 #define L2_FHDR_STATUS_RULE_P4 (1<<5) 1001 #define L2_FHDR_STATUS_L2_VLAN_TAG (1<<6) 1002 #define L2_FHDR_STATUS_L2_LLC_SNAP (1<<7) 1003 #define L2_FHDR_STATUS_RSS_HASH (1<<8) 1004 #define L2_FHDR_STATUS_IP_DATAGRAM (1<<13) 1005 #define L2_FHDR_STATUS_TCP_SEGMENT (1<<14) 1006 #define L2_FHDR_STATUS_UDP_DATAGRAM (1<<15) 1007 1008 #define L2_FHDR_ERRORS_BAD_CRC (1<<17) 1009 #define L2_FHDR_ERRORS_PHY_DECODE (1<<18) 1010 #define L2_FHDR_ERRORS_ALIGNMENT (1<<19) 1011 #define L2_FHDR_ERRORS_TOO_SHORT (1<<20) 1012 #define L2_FHDR_ERRORS_GIANT_FRAME (1<<21) 1013 #define L2_FHDR_ERRORS_TCP_XSUM (1<<28) 1014 #define L2_FHDR_ERRORS_UDP_XSUM (1<<31) 1015 1016 u32 l2_fhdr_hash; 1017#if defined(__BIG_ENDIAN) 1018 u16 l2_fhdr_pkt_len; 1019 u16 l2_fhdr_vlan_tag; 1020 u16 l2_fhdr_ip_xsum; 1021 u16 l2_fhdr_tcp_udp_xsum; 1022#elif defined(__LITTLE_ENDIAN) 1023 u16 l2_fhdr_vlan_tag; 1024 u16 l2_fhdr_pkt_len; 1025 u16 l2_fhdr_tcp_udp_xsum; 1026 u16 l2_fhdr_ip_xsum; 1027#endif 1028}; 1029 1030 1031/* 1032 * l2_context definition 1033 */ 1034#define BCE_L2CTX_TYPE 0x00000000 1035#define BCE_L2CTX_TYPE_SIZE_L2 ((0xc0/0x20)<<16) 1036#define BCE_L2CTX_TYPE_TYPE (0xf<<28) 1037#define BCE_L2CTX_TYPE_TYPE_EMPTY (0<<28) 1038#define BCE_L2CTX_TYPE_TYPE_L2 (1<<28) 1039 1040#define BCE_L2CTX_TX_HOST_BIDX 0x00000088 1041#define BCE_L2CTX_EST_NBD 0x00000088 1042#define BCE_L2CTX_CMD_TYPE 0x00000088 1043#define BCE_L2CTX_CMD_TYPE_TYPE (0xf<<24) 1044#define BCE_L2CTX_CMD_TYPE_TYPE_L2 (0<<24) 1045#define BCE_L2CTX_CMD_TYPE_TYPE_TCP (1<<24) 1046 1047#define BCE_L2CTX_TX_HOST_BSEQ 0x00000090 1048#define BCE_L2CTX_TSCH_BSEQ 0x00000094 1049#define BCE_L2CTX_TBDR_BSEQ 0x00000098 1050#define BCE_L2CTX_TBDR_BOFF 0x0000009c 1051#define BCE_L2CTX_TBDR_BIDX 0x0000009c 1052#define BCE_L2CTX_TBDR_BHADDR_HI 0x000000a0 1053#define BCE_L2CTX_TBDR_BHADDR_LO 0x000000a4 1054#define BCE_L2CTX_TXP_BOFF 0x000000a8 1055#define BCE_L2CTX_TXP_BIDX 0x000000a8 1056#define BCE_L2CTX_TXP_BSEQ 0x000000ac 1057 1058 1059/* 1060 * l2_bd_chain_context definition 1061 */ 1062#define BCE_L2CTX_BD_PRE_READ 0x00000000 1063#define BCE_L2CTX_CTX_SIZE 0x00000000 1064#define BCE_L2CTX_CTX_TYPE 0x00000000 1065#define BCE_L2CTX_CTX_TYPE_SIZE_L2 ((0x20/20)<<16) 1066#define BCE_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE (0xf<<28) 1067#define BCE_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_UNDEFINED (0<<28) 1068#define BCE_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE (1<<28) 1069 1070#define BCE_L2CTX_HOST_BDIDX 0x00000004 1071#define BCE_L2CTX_HOST_BSEQ 0x00000008 1072#define BCE_L2CTX_NX_BSEQ 0x0000000c 1073#define BCE_L2CTX_NX_BDHADDR_HI 0x00000010 1074#define BCE_L2CTX_NX_BDHADDR_LO 0x00000014 1075#define BCE_L2CTX_NX_BDIDX 0x00000018 1076 1077 1078/* 1079 * pci_config_l definition 1080 * offset: 0000 1081 */ 1082#define BCE_PCICFG_MISC_CONFIG 0x00000068 1083#define BCE_PCICFG_MISC_CONFIG_TARGET_BYTE_SWAP (1L<<2) 1084#define BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP (1L<<3) 1085#define BCE_PCICFG_MISC_CONFIG_CLOCK_CTL_ENA (1L<<5) 1086#define BCE_PCICFG_MISC_CONFIG_TARGET_GRC_WORD_SWAP (1L<<6) 1087#define BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA (1L<<7) 1088#define BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ (1L<<8) 1089#define BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY (1L<<9) 1090#define BCE_PCICFG_MISC_CONFIG_ASIC_METAL_REV (0xffL<<16) 1091#define BCE_PCICFG_MISC_CONFIG_ASIC_BASE_REV (0xfL<<24) 1092#define BCE_PCICFG_MISC_CONFIG_ASIC_ID (0xfL<<28) 1093#define BCE_PCICFG_MISC_CONFIG_ASIC_REV (0xffffL<<16) 1094 1095#define BCE_PCICFG_MISC_STATUS 0x0000006c 1096#define BCE_PCICFG_MISC_STATUS_INTA_VALUE (1L<<0) 1097#define BCE_PCICFG_MISC_STATUS_32BIT_DET (1L<<1) 1098#define BCE_PCICFG_MISC_STATUS_M66EN (1L<<2) 1099#define BCE_PCICFG_MISC_STATUS_PCIX_DET (1L<<3) 1100#define BCE_PCICFG_MISC_STATUS_PCIX_SPEED (0x3L<<4) 1101#define BCE_PCICFG_MISC_STATUS_PCIX_SPEED_66 (0L<<4) 1102#define BCE_PCICFG_MISC_STATUS_PCIX_SPEED_100 (1L<<4) 1103#define BCE_PCICFG_MISC_STATUS_PCIX_SPEED_133 (2L<<4) 1104#define BCE_PCICFG_MISC_STATUS_PCIX_SPEED_PCI_MODE (3L<<4) 1105 1106#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS 0x00000070 1107#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET (0xfL<<0) 1108#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ (0L<<0) 1109#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ (1L<<0) 1110#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ (2L<<0) 1111#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ (3L<<0) 1112#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ (4L<<0) 1113#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ (5L<<0) 1114#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ (6L<<0) 1115#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ (7L<<0) 1116#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW (0xfL<<0) 1117#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE (1L<<6) 1118#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT (1L<<7) 1119#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC (0x7L<<8) 1120#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF (0L<<8) 1121#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12 (1L<<8) 1122#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6 (2L<<8) 1123#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62 (4L<<8) 1124#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PLAY_DEAD (1L<<11) 1125#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED (0xfL<<12) 1126#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100 (0L<<12) 1127#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80 (1L<<12) 1128#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50 (2L<<12) 1129#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40 (4L<<12) 1130#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25 (8L<<12) 1131#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP (1L<<16) 1132#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_PLL_STOP (1L<<17) 1133#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_18 (1L<<18) 1134#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_USE_SPD_DET (1L<<19) 1135#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED (0xfffL<<20) 1136 1137#define BCE_PCICFG_REG_WINDOW_ADDRESS 0x00000078 1138#define BCE_PCICFG_REG_WINDOW 0x00000080 1139#define BCE_PCICFG_INT_ACK_CMD 0x00000084 1140#define BCE_PCICFG_INT_ACK_CMD_INDEX (0xffffL<<0) 1141#define BCE_PCICFG_INT_ACK_CMD_INDEX_VALID (1L<<16) 1142#define BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM (1L<<17) 1143#define BCE_PCICFG_INT_ACK_CMD_MASK_INT (1L<<18) 1144 1145#define BCE_PCICFG_STATUS_BIT_SET_CMD 0x00000088 1146#define BCE_PCICFG_STATUS_BIT_CLEAR_CMD 0x0000008c 1147#define BCE_PCICFG_MAILBOX_QUEUE_ADDR 0x00000090 1148#define BCE_PCICFG_MAILBOX_QUEUE_DATA 0x00000094 1149 1150 1151/* 1152 * pci_reg definition 1153 * offset: 0x400 1154 */ 1155#define BCE_PCI_GRC_WINDOW_ADDR 0x00000400 1156#define BCE_PCI_GRC_WINDOW_ADDR_PCI_GRC_WINDOW_ADDR_VALUE (0x3ffffL<<8) 1157 1158#define BCE_PCI_CONFIG_1 0x00000404 1159#define BCE_PCI_CONFIG_1_READ_BOUNDARY (0x7L<<8) 1160#define BCE_PCI_CONFIG_1_READ_BOUNDARY_OFF (0L<<8) 1161#define BCE_PCI_CONFIG_1_READ_BOUNDARY_16 (1L<<8) 1162#define BCE_PCI_CONFIG_1_READ_BOUNDARY_32 (2L<<8) 1163#define BCE_PCI_CONFIG_1_READ_BOUNDARY_64 (3L<<8) 1164#define BCE_PCI_CONFIG_1_READ_BOUNDARY_128 (4L<<8) 1165#define BCE_PCI_CONFIG_1_READ_BOUNDARY_256 (5L<<8) 1166#define BCE_PCI_CONFIG_1_READ_BOUNDARY_512 (6L<<8) 1167#define BCE_PCI_CONFIG_1_READ_BOUNDARY_1024 (7L<<8) 1168#define BCE_PCI_CONFIG_1_WRITE_BOUNDARY (0x7L<<11) 1169#define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_OFF (0L<<11) 1170#define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_16 (1L<<11) 1171#define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_32 (2L<<11) 1172#define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_64 (3L<<11) 1173#define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_128 (4L<<11) 1174#define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_256 (5L<<11) 1175#define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_512 (6L<<11) 1176#define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_1024 (7L<<11) 1177 1178#define BCE_PCI_CONFIG_2 0x00000408 1179#define BCE_PCI_CONFIG_2_BAR1_SIZE (0xfL<<0) 1180#define BCE_PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0) 1181#define BCE_PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0) 1182#define BCE_PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0) 1183#define BCE_PCI_CONFIG_2_BAR1_SIZE_256K (3L<<0) 1184#define BCE_PCI_CONFIG_2_BAR1_SIZE_512K (4L<<0) 1185#define BCE_PCI_CONFIG_2_BAR1_SIZE_1M (5L<<0) 1186#define BCE_PCI_CONFIG_2_BAR1_SIZE_2M (6L<<0) 1187#define BCE_PCI_CONFIG_2_BAR1_SIZE_4M (7L<<0) 1188#define BCE_PCI_CONFIG_2_BAR1_SIZE_8M (8L<<0) 1189#define BCE_PCI_CONFIG_2_BAR1_SIZE_16M (9L<<0) 1190#define BCE_PCI_CONFIG_2_BAR1_SIZE_32M (10L<<0) 1191#define BCE_PCI_CONFIG_2_BAR1_SIZE_64M (11L<<0) 1192#define BCE_PCI_CONFIG_2_BAR1_SIZE_128M (12L<<0) 1193#define BCE_PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0) 1194#define BCE_PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0) 1195#define BCE_PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0) 1196#define BCE_PCI_CONFIG_2_BAR1_64ENA (1L<<4) 1197#define BCE_PCI_CONFIG_2_EXP_ROM_RETRY (1L<<5) 1198#define BCE_PCI_CONFIG_2_CFG_CYCLE_RETRY (1L<<6) 1199#define BCE_PCI_CONFIG_2_FIRST_CFG_DONE (1L<<7) 1200#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8) 1201#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8) 1202#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_1K (1L<<8) 1203#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_2K (2L<<8) 1204#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_4K (3L<<8) 1205#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_8K (4L<<8) 1206#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_16K (5L<<8) 1207#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_32K (6L<<8) 1208#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_64K (7L<<8) 1209#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_128K (8L<<8) 1210#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_256K (9L<<8) 1211#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_512K (10L<<8) 1212#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_1M (11L<<8) 1213#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_2M (12L<<8) 1214#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_4M (13L<<8) 1215#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_8M (14L<<8) 1216#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_16M (15L<<8) 1217#define BCE_PCI_CONFIG_2_MAX_SPLIT_LIMIT (0x1fL<<16) 1218#define BCE_PCI_CONFIG_2_MAX_READ_LIMIT (0x3L<<21) 1219#define BCE_PCI_CONFIG_2_MAX_READ_LIMIT_512 (0L<<21) 1220#define BCE_PCI_CONFIG_2_MAX_READ_LIMIT_1K (1L<<21) 1221#define BCE_PCI_CONFIG_2_MAX_READ_LIMIT_2K (2L<<21) 1222#define BCE_PCI_CONFIG_2_MAX_READ_LIMIT_4K (3L<<21) 1223#define BCE_PCI_CONFIG_2_FORCE_32_BIT_MSTR (1L<<23) 1224#define BCE_PCI_CONFIG_2_FORCE_32_BIT_TGT (1L<<24) 1225#define BCE_PCI_CONFIG_2_KEEP_REQ_ASSERT (1L<<25) 1226 1227#define BCE_PCI_CONFIG_3 0x0000040c 1228#define BCE_PCI_CONFIG_3_STICKY_BYTE (0xffL<<0) 1229#define BCE_PCI_CONFIG_3_FORCE_PME (1L<<24) 1230#define BCE_PCI_CONFIG_3_PME_STATUS (1L<<25) 1231#define BCE_PCI_CONFIG_3_PME_ENABLE (1L<<26) 1232#define BCE_PCI_CONFIG_3_PM_STATE (0x3L<<27) 1233#define BCE_PCI_CONFIG_3_VAUX_PRESET (1L<<30) 1234#define BCE_PCI_CONFIG_3_PCI_POWER (1L<<31) 1235 1236#define BCE_PCI_PM_DATA_A 0x00000410 1237#define BCE_PCI_PM_DATA_A_PM_DATA_0_PRG (0xffL<<0) 1238#define BCE_PCI_PM_DATA_A_PM_DATA_1_PRG (0xffL<<8) 1239#define BCE_PCI_PM_DATA_A_PM_DATA_2_PRG (0xffL<<16) 1240#define BCE_PCI_PM_DATA_A_PM_DATA_3_PRG (0xffL<<24) 1241 1242#define BCE_PCI_PM_DATA_B 0x00000414 1243#define BCE_PCI_PM_DATA_B_PM_DATA_4_PRG (0xffL<<0) 1244#define BCE_PCI_PM_DATA_B_PM_DATA_5_PRG (0xffL<<8) 1245#define BCE_PCI_PM_DATA_B_PM_DATA_6_PRG (0xffL<<16) 1246#define BCE_PCI_PM_DATA_B_PM_DATA_7_PRG (0xffL<<24) 1247 1248#define BCE_PCI_SWAP_DIAG0 0x00000418 1249#define BCE_PCI_SWAP_DIAG1 0x0000041c 1250#define BCE_PCI_EXP_ROM_ADDR 0x00000420 1251#define BCE_PCI_EXP_ROM_ADDR_ADDRESS (0x3fffffL<<2) 1252#define BCE_PCI_EXP_ROM_ADDR_REQ (1L<<31) 1253 1254#define BCE_PCI_EXP_ROM_DATA 0x00000424 1255#define BCE_PCI_VPD_INTF 0x00000428 1256#define BCE_PCI_VPD_INTF_INTF_REQ (1L<<0) 1257 1258#define BCE_PCI_VPD_ADDR_FLAG 0x0000042c 1259#define BCE_PCI_VPD_ADDR_FLAG_ADDRESS (0x1fff<<2) 1260#define BCE_PCI_VPD_ADDR_FLAG_WR (1<<15) 1261 1262#define BCE_PCI_VPD_DATA 0x00000430 1263#define BCE_PCI_ID_VAL1 0x00000434 1264#define BCE_PCI_ID_VAL1_DEVICE_ID (0xffffL<<0) 1265#define BCE_PCI_ID_VAL1_VENDOR_ID (0xffffL<<16) 1266 1267#define BCE_PCI_ID_VAL2 0x00000438 1268#define BCE_PCI_ID_VAL2_SUBSYSTEM_VENDOR_ID (0xffffL<<0) 1269#define BCE_PCI_ID_VAL2_SUBSYSTEM_ID (0xffffL<<16) 1270 1271#define BCE_PCI_ID_VAL3 0x0000043c 1272#define BCE_PCI_ID_VAL3_CLASS_CODE (0xffffffL<<0) 1273#define BCE_PCI_ID_VAL3_REVISION_ID (0xffL<<24) 1274 1275#define BCE_PCI_ID_VAL4 0x00000440 1276#define BCE_PCI_ID_VAL4_CAP_ENA (0xfL<<0) 1277#define BCE_PCI_ID_VAL4_CAP_ENA_0 (0L<<0) 1278#define BCE_PCI_ID_VAL4_CAP_ENA_1 (1L<<0) 1279#define BCE_PCI_ID_VAL4_CAP_ENA_2 (2L<<0) 1280#define BCE_PCI_ID_VAL4_CAP_ENA_3 (3L<<0) 1281#define BCE_PCI_ID_VAL4_CAP_ENA_4 (4L<<0) 1282#define BCE_PCI_ID_VAL4_CAP_ENA_5 (5L<<0) 1283#define BCE_PCI_ID_VAL4_CAP_ENA_6 (6L<<0) 1284#define BCE_PCI_ID_VAL4_CAP_ENA_7 (7L<<0) 1285#define BCE_PCI_ID_VAL4_CAP_ENA_8 (8L<<0) 1286#define BCE_PCI_ID_VAL4_CAP_ENA_9 (9L<<0) 1287#define BCE_PCI_ID_VAL4_CAP_ENA_10 (10L<<0) 1288#define BCE_PCI_ID_VAL4_CAP_ENA_11 (11L<<0) 1289#define BCE_PCI_ID_VAL4_CAP_ENA_12 (12L<<0) 1290#define BCE_PCI_ID_VAL4_CAP_ENA_13 (13L<<0) 1291#define BCE_PCI_ID_VAL4_CAP_ENA_14 (14L<<0) 1292#define BCE_PCI_ID_VAL4_CAP_ENA_15 (15L<<0) 1293#define BCE_PCI_ID_VAL4_PM_SCALE_PRG (0x3L<<6) 1294#define BCE_PCI_ID_VAL4_PM_SCALE_PRG_0 (0L<<6) 1295#define BCE_PCI_ID_VAL4_PM_SCALE_PRG_1 (1L<<6) 1296#define BCE_PCI_ID_VAL4_PM_SCALE_PRG_2 (2L<<6) 1297#define BCE_PCI_ID_VAL4_PM_SCALE_PRG_3 (3L<<6) 1298#define BCE_PCI_ID_VAL4_MSI_LIMIT (0x7L<<9) 1299#define BCE_PCI_ID_VAL4_MSI_ADVERTIZE (0x7L<<12) 1300#define BCE_PCI_ID_VAL4_MSI_ENABLE (1L<<15) 1301#define BCE_PCI_ID_VAL4_MAX_64_ADVERTIZE (1L<<16) 1302#define BCE_PCI_ID_VAL4_MAX_133_ADVERTIZE (1L<<17) 1303#define BCE_PCI_ID_VAL4_MAX_MEM_READ_SIZE (0x3L<<21) 1304#define BCE_PCI_ID_VAL4_MAX_SPLIT_SIZE (0x7L<<23) 1305#define BCE_PCI_ID_VAL4_MAX_CUMULATIVE_SIZE (0x7L<<26) 1306 1307#define BCE_PCI_ID_VAL5 0x00000444 1308#define BCE_PCI_ID_VAL5_D1_SUPPORT (1L<<0) 1309#define BCE_PCI_ID_VAL5_D2_SUPPORT (1L<<1) 1310#define BCE_PCI_ID_VAL5_PME_IN_D0 (1L<<2) 1311#define BCE_PCI_ID_VAL5_PME_IN_D1 (1L<<3) 1312#define BCE_PCI_ID_VAL5_PME_IN_D2 (1L<<4) 1313#define BCE_PCI_ID_VAL5_PME_IN_D3_HOT (1L<<5) 1314 1315#define BCE_PCI_PCIX_EXTENDED_STATUS 0x00000448 1316#define BCE_PCI_PCIX_EXTENDED_STATUS_NO_SNOOP (1L<<8) 1317#define BCE_PCI_PCIX_EXTENDED_STATUS_LONG_BURST (1L<<9) 1318#define BCE_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_CLASS (0xfL<<16) 1319#define BCE_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_IDX (0xffL<<24) 1320 1321#define BCE_PCI_ID_VAL6 0x0000044c 1322#define BCE_PCI_ID_VAL6_MAX_LAT (0xffL<<0) 1323#define BCE_PCI_ID_VAL6_MIN_GNT (0xffL<<8) 1324#define BCE_PCI_ID_VAL6_BIST (0xffL<<16) 1325 1326#define BCE_PCI_MSI_DATA 0x00000450 1327#define BCE_PCI_MSI_DATA_PCI_MSI_DATA (0xffffL<<0) 1328 1329#define BCE_PCI_MSI_ADDR_H 0x00000454 1330#define BCE_PCI_MSI_ADDR_L 0x00000458 1331 1332 1333/* 1334 * misc_reg definition 1335 * offset: 0x800 1336 */ 1337#define BCE_MISC_COMMAND 0x00000800 1338#define BCE_MISC_COMMAND_ENABLE_ALL (1L<<0) 1339#define BCE_MISC_COMMAND_DISABLE_ALL (1L<<1) 1340#define BCE_MISC_COMMAND_CORE_RESET (1L<<4) 1341#define BCE_MISC_COMMAND_HARD_RESET (1L<<5) 1342#define BCE_MISC_COMMAND_PAR_ERROR (1L<<8) 1343#define BCE_MISC_COMMAND_PAR_ERR_RAM (0x7fL<<16) 1344 1345#define BCE_MISC_CFG 0x00000804 1346#define BCE_MISC_CFG_PCI_GRC_TMOUT (1L<<0) 1347#define BCE_MISC_CFG_NVM_WR_EN (0x3L<<1) 1348#define BCE_MISC_CFG_NVM_WR_EN_PROTECT (0L<<1) 1349#define BCE_MISC_CFG_NVM_WR_EN_PCI (1L<<1) 1350#define BCE_MISC_CFG_NVM_WR_EN_ALLOW (2L<<1) 1351#define BCE_MISC_CFG_NVM_WR_EN_ALLOW2 (3L<<1) 1352#define BCE_MISC_CFG_BIST_EN (1L<<3) 1353#define BCE_MISC_CFG_CK25_OUT_ALT_SRC (1L<<4) 1354#define BCE_MISC_CFG_BYPASS_BSCAN (1L<<5) 1355#define BCE_MISC_CFG_BYPASS_EJTAG (1L<<6) 1356#define BCE_MISC_CFG_CLK_CTL_OVERRIDE (1L<<7) 1357#define BCE_MISC_CFG_LEDMODE (0x3L<<8) 1358#define BCE_MISC_CFG_LEDMODE_MAC (0L<<8) 1359#define BCE_MISC_CFG_LEDMODE_GPHY1 (1L<<8) 1360#define BCE_MISC_CFG_LEDMODE_GPHY2 (2L<<8) 1361 1362#define BCE_MISC_ID 0x00000808 1363#define BCE_MISC_ID_BOND_ID (0xfL<<0) 1364#define BCE_MISC_ID_CHIP_METAL (0xffL<<4) 1365#define BCE_MISC_ID_CHIP_REV (0xfL<<12) 1366#define BCE_MISC_ID_CHIP_NUM (0xffffL<<16) 1367 1368#define BCE_MISC_ENABLE_STATUS_BITS 0x0000080c 1369#define BCE_MISC_ENABLE_STATUS_BITS_TX_SCHEDULER_ENABLE (1L<<0) 1370#define BCE_MISC_ENABLE_STATUS_BITS_TX_BD_READ_ENABLE (1L<<1) 1371#define BCE_MISC_ENABLE_STATUS_BITS_TX_BD_CACHE_ENABLE (1L<<2) 1372#define BCE_MISC_ENABLE_STATUS_BITS_TX_PROCESSOR_ENABLE (1L<<3) 1373#define BCE_MISC_ENABLE_STATUS_BITS_TX_DMA_ENABLE (1L<<4) 1374#define BCE_MISC_ENABLE_STATUS_BITS_TX_PATCHUP_ENABLE (1L<<5) 1375#define BCE_MISC_ENABLE_STATUS_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6) 1376#define BCE_MISC_ENABLE_STATUS_BITS_TX_HEADER_Q_ENABLE (1L<<7) 1377#define BCE_MISC_ENABLE_STATUS_BITS_TX_ASSEMBLER_ENABLE (1L<<8) 1378#define BCE_MISC_ENABLE_STATUS_BITS_EMAC_ENABLE (1L<<9) 1379#define BCE_MISC_ENABLE_STATUS_BITS_RX_PARSER_MAC_ENABLE (1L<<10) 1380#define BCE_MISC_ENABLE_STATUS_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11) 1381#define BCE_MISC_ENABLE_STATUS_BITS_RX_MBUF_ENABLE (1L<<12) 1382#define BCE_MISC_ENABLE_STATUS_BITS_RX_LOOKUP_ENABLE (1L<<13) 1383#define BCE_MISC_ENABLE_STATUS_BITS_RX_PROCESSOR_ENABLE (1L<<14) 1384#define BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE (1L<<15) 1385#define BCE_MISC_ENABLE_STATUS_BITS_RX_BD_CACHE_ENABLE (1L<<16) 1386#define BCE_MISC_ENABLE_STATUS_BITS_RX_DMA_ENABLE (1L<<17) 1387#define BCE_MISC_ENABLE_STATUS_BITS_COMPLETION_ENABLE (1L<<18) 1388#define BCE_MISC_ENABLE_STATUS_BITS_HOST_COALESCE_ENABLE (1L<<19) 1389#define BCE_MISC_ENABLE_STATUS_BITS_MAILBOX_QUEUE_ENABLE (1L<<20) 1390#define BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE (1L<<21) 1391#define BCE_MISC_ENABLE_STATUS_BITS_CMD_SCHEDULER_ENABLE (1L<<22) 1392#define BCE_MISC_ENABLE_STATUS_BITS_CMD_PROCESSOR_ENABLE (1L<<23) 1393#define BCE_MISC_ENABLE_STATUS_BITS_MGMT_PROCESSOR_ENABLE (1L<<24) 1394#define BCE_MISC_ENABLE_STATUS_BITS_TIMER_ENABLE (1L<<25) 1395#define BCE_MISC_ENABLE_STATUS_BITS_DMA_ENGINE_ENABLE (1L<<26) 1396#define BCE_MISC_ENABLE_STATUS_BITS_UMP_ENABLE (1L<<27) 1397 1398#define BCE_MISC_ENABLE_SET_BITS 0x00000810 1399#define BCE_MISC_ENABLE_SET_BITS_TX_SCHEDULER_ENABLE (1L<<0) 1400#define BCE_MISC_ENABLE_SET_BITS_TX_BD_READ_ENABLE (1L<<1) 1401#define BCE_MISC_ENABLE_SET_BITS_TX_BD_CACHE_ENABLE (1L<<2) 1402#define BCE_MISC_ENABLE_SET_BITS_TX_PROCESSOR_ENABLE (1L<<3) 1403#define BCE_MISC_ENABLE_SET_BITS_TX_DMA_ENABLE (1L<<4) 1404#define BCE_MISC_ENABLE_SET_BITS_TX_PATCHUP_ENABLE (1L<<5) 1405#define BCE_MISC_ENABLE_SET_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6) 1406#define BCE_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE (1L<<7) 1407#define BCE_MISC_ENABLE_SET_BITS_TX_ASSEMBLER_ENABLE (1L<<8) 1408#define BCE_MISC_ENABLE_SET_BITS_EMAC_ENABLE (1L<<9) 1409#define BCE_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE (1L<<10) 1410#define BCE_MISC_ENABLE_SET_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11) 1411#define BCE_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE (1L<<12) 1412#define BCE_MISC_ENABLE_SET_BITS_RX_LOOKUP_ENABLE (1L<<13) 1413#define BCE_MISC_ENABLE_SET_BITS_RX_PROCESSOR_ENABLE (1L<<14) 1414#define BCE_MISC_ENABLE_SET_BITS_RX_V2P_ENABLE (1L<<15) 1415#define BCE_MISC_ENABLE_SET_BITS_RX_BD_CACHE_ENABLE (1L<<16) 1416#define BCE_MISC_ENABLE_SET_BITS_RX_DMA_ENABLE (1L<<17) 1417#define BCE_MISC_ENABLE_SET_BITS_COMPLETION_ENABLE (1L<<18) 1418#define BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE (1L<<19) 1419#define BCE_MISC_ENABLE_SET_BITS_MAILBOX_QUEUE_ENABLE (1L<<20) 1420#define BCE_MISC_ENABLE_SET_BITS_CONTEXT_ENABLE (1L<<21) 1421#define BCE_MISC_ENABLE_SET_BITS_CMD_SCHEDULER_ENABLE (1L<<22) 1422#define BCE_MISC_ENABLE_SET_BITS_CMD_PROCESSOR_ENABLE (1L<<23) 1423#define BCE_MISC_ENABLE_SET_BITS_MGMT_PROCESSOR_ENABLE (1L<<24) 1424#define BCE_MISC_ENABLE_SET_BITS_TIMER_ENABLE (1L<<25) 1425#define BCE_MISC_ENABLE_SET_BITS_DMA_ENGINE_ENABLE (1L<<26) 1426#define BCE_MISC_ENABLE_SET_BITS_UMP_ENABLE (1L<<27) 1427 1428#define BCE_MISC_ENABLE_CLR_BITS 0x00000814 1429#define BCE_MISC_ENABLE_CLR_BITS_TX_SCHEDULER_ENABLE (1L<<0) 1430#define BCE_MISC_ENABLE_CLR_BITS_TX_BD_READ_ENABLE (1L<<1) 1431#define BCE_MISC_ENABLE_CLR_BITS_TX_BD_CACHE_ENABLE (1L<<2) 1432#define BCE_MISC_ENABLE_CLR_BITS_TX_PROCESSOR_ENABLE (1L<<3) 1433#define BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE (1L<<4) 1434#define BCE_MISC_ENABLE_CLR_BITS_TX_PATCHUP_ENABLE (1L<<5) 1435#define BCE_MISC_ENABLE_CLR_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6) 1436#define BCE_MISC_ENABLE_CLR_BITS_TX_HEADER_Q_ENABLE (1L<<7) 1437#define BCE_MISC_ENABLE_CLR_BITS_TX_ASSEMBLER_ENABLE (1L<<8) 1438#define BCE_MISC_ENABLE_CLR_BITS_EMAC_ENABLE (1L<<9) 1439#define BCE_MISC_ENABLE_CLR_BITS_RX_PARSER_MAC_ENABLE (1L<<10) 1440#define BCE_MISC_ENABLE_CLR_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11) 1441#define BCE_MISC_ENABLE_CLR_BITS_RX_MBUF_ENABLE (1L<<12) 1442#define BCE_MISC_ENABLE_CLR_BITS_RX_LOOKUP_ENABLE (1L<<13) 1443#define BCE_MISC_ENABLE_CLR_BITS_RX_PROCESSOR_ENABLE (1L<<14) 1444#define BCE_MISC_ENABLE_CLR_BITS_RX_V2P_ENABLE (1L<<15) 1445#define BCE_MISC_ENABLE_CLR_BITS_RX_BD_CACHE_ENABLE (1L<<16) 1446#define BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE (1L<<17) 1447#define BCE_MISC_ENABLE_CLR_BITS_COMPLETION_ENABLE (1L<<18) 1448#define BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE (1L<<19) 1449#define BCE_MISC_ENABLE_CLR_BITS_MAILBOX_QUEUE_ENABLE (1L<<20) 1450#define BCE_MISC_ENABLE_CLR_BITS_CONTEXT_ENABLE (1L<<21) 1451#define BCE_MISC_ENABLE_CLR_BITS_CMD_SCHEDULER_ENABLE (1L<<22) 1452#define BCE_MISC_ENABLE_CLR_BITS_CMD_PROCESSOR_ENABLE (1L<<23) 1453#define BCE_MISC_ENABLE_CLR_BITS_MGMT_PROCESSOR_ENABLE (1L<<24) 1454#define BCE_MISC_ENABLE_CLR_BITS_TIMER_ENABLE (1L<<25) 1455#define BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE (1L<<26) 1456#define BCE_MISC_ENABLE_CLR_BITS_UMP_ENABLE (1L<<27) 1457 1458#define BCE_MISC_CLOCK_CONTROL_BITS 0x00000818 1459#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET (0xfL<<0) 1460#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ (0L<<0) 1461#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ (1L<<0) 1462#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ (2L<<0) 1463#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ (3L<<0) 1464#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ (4L<<0) 1465#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ (5L<<0) 1466#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ (6L<<0) 1467#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ (7L<<0) 1468#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW (0xfL<<0) 1469#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE (1L<<6) 1470#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT (1L<<7) 1471#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC (0x7L<<8) 1472#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF (0L<<8) 1473#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12 (1L<<8) 1474#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6 (2L<<8) 1475#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62 (4L<<8) 1476#define BCE_MISC_CLOCK_CONTROL_BITS_PLAY_DEAD (1L<<11) 1477#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED (0xfL<<12) 1478#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100 (0L<<12) 1479#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80 (1L<<12) 1480#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50 (2L<<12) 1481#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40 (4L<<12) 1482#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25 (8L<<12) 1483#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP (1L<<16) 1484#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_PLL_STOP (1L<<17) 1485#define BCE_MISC_CLOCK_CONTROL_BITS_RESERVED_18 (1L<<18) 1486#define BCE_MISC_CLOCK_CONTROL_BITS_USE_SPD_DET (1L<<19) 1487#define BCE_MISC_CLOCK_CONTROL_BITS_RESERVED (0xfffL<<20) 1488 1489#define BCE_MISC_GPIO 0x0000081c 1490#define BCE_MISC_GPIO_VALUE (0xffL<<0) 1491#define BCE_MISC_GPIO_SET (0xffL<<8) 1492#define BCE_MISC_GPIO_CLR (0xffL<<16) 1493#define BCE_MISC_GPIO_FLOAT (0xffL<<24) 1494 1495#define BCE_MISC_GPIO_INT 0x00000820 1496#define BCE_MISC_GPIO_INT_INT_STATE (0xfL<<0) 1497#define BCE_MISC_GPIO_INT_OLD_VALUE (0xfL<<8) 1498#define BCE_MISC_GPIO_INT_OLD_SET (0xfL<<16) 1499#define BCE_MISC_GPIO_INT_OLD_CLR (0xfL<<24) 1500 1501#define BCE_MISC_CONFIG_LFSR 0x00000824 1502#define BCE_MISC_CONFIG_LFSR_DIV (0xffffL<<0) 1503 1504#define BCE_MISC_LFSR_MASK_BITS 0x00000828 1505#define BCE_MISC_LFSR_MASK_BITS_TX_SCHEDULER_ENABLE (1L<<0) 1506#define BCE_MISC_LFSR_MASK_BITS_TX_BD_READ_ENABLE (1L<<1) 1507#define BCE_MISC_LFSR_MASK_BITS_TX_BD_CACHE_ENABLE (1L<<2) 1508#define BCE_MISC_LFSR_MASK_BITS_TX_PROCESSOR_ENABLE (1L<<3) 1509#define BCE_MISC_LFSR_MASK_BITS_TX_DMA_ENABLE (1L<<4) 1510#define BCE_MISC_LFSR_MASK_BITS_TX_PATCHUP_ENABLE (1L<<5) 1511#define BCE_MISC_LFSR_MASK_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6) 1512#define BCE_MISC_LFSR_MASK_BITS_TX_HEADER_Q_ENABLE (1L<<7) 1513#define BCE_MISC_LFSR_MASK_BITS_TX_ASSEMBLER_ENABLE (1L<<8) 1514#define BCE_MISC_LFSR_MASK_BITS_EMAC_ENABLE (1L<<9) 1515#define BCE_MISC_LFSR_MASK_BITS_RX_PARSER_MAC_ENABLE (1L<<10) 1516#define BCE_MISC_LFSR_MASK_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11) 1517#define BCE_MISC_LFSR_MASK_BITS_RX_MBUF_ENABLE (1L<<12) 1518#define BCE_MISC_LFSR_MASK_BITS_RX_LOOKUP_ENABLE (1L<<13) 1519#define BCE_MISC_LFSR_MASK_BITS_RX_PROCESSOR_ENABLE (1L<<14) 1520#define BCE_MISC_LFSR_MASK_BITS_RX_V2P_ENABLE (1L<<15) 1521#define BCE_MISC_LFSR_MASK_BITS_RX_BD_CACHE_ENABLE (1L<<16) 1522#define BCE_MISC_LFSR_MASK_BITS_RX_DMA_ENABLE (1L<<17) 1523#define BCE_MISC_LFSR_MASK_BITS_COMPLETION_ENABLE (1L<<18) 1524#define BCE_MISC_LFSR_MASK_BITS_HOST_COALESCE_ENABLE (1L<<19) 1525#define BCE_MISC_LFSR_MASK_BITS_MAILBOX_QUEUE_ENABLE (1L<<20) 1526#define BCE_MISC_LFSR_MASK_BITS_CONTEXT_ENABLE (1L<<21) 1527#define BCE_MISC_LFSR_MASK_BITS_CMD_SCHEDULER_ENABLE (1L<<22) 1528#define BCE_MISC_LFSR_MASK_BITS_CMD_PROCESSOR_ENABLE (1L<<23) 1529#define BCE_MISC_LFSR_MASK_BITS_MGMT_PROCESSOR_ENABLE (1L<<24) 1530#define BCE_MISC_LFSR_MASK_BITS_TIMER_ENABLE (1L<<25) 1531#define BCE_MISC_LFSR_MASK_BITS_DMA_ENGINE_ENABLE (1L<<26) 1532#define BCE_MISC_LFSR_MASK_BITS_UMP_ENABLE (1L<<27) 1533 1534#define BCE_MISC_ARB_REQ0 0x0000082c 1535#define BCE_MISC_ARB_REQ1 0x00000830 1536#define BCE_MISC_ARB_REQ2 0x00000834 1537#define BCE_MISC_ARB_REQ3 0x00000838 1538#define BCE_MISC_ARB_REQ4 0x0000083c 1539#define BCE_MISC_ARB_FREE0 0x00000840 1540#define BCE_MISC_ARB_FREE1 0x00000844 1541#define BCE_MISC_ARB_FREE2 0x00000848 1542#define BCE_MISC_ARB_FREE3 0x0000084c 1543#define BCE_MISC_ARB_FREE4 0x00000850 1544#define BCE_MISC_ARB_REQ_STATUS0 0x00000854 1545#define BCE_MISC_ARB_REQ_STATUS1 0x00000858 1546#define BCE_MISC_ARB_REQ_STATUS2 0x0000085c 1547#define BCE_MISC_ARB_REQ_STATUS3 0x00000860 1548#define BCE_MISC_ARB_REQ_STATUS4 0x00000864 1549#define BCE_MISC_ARB_GNT0 0x00000868 1550#define BCE_MISC_ARB_GNT0_0 (0x7L<<0) 1551#define BCE_MISC_ARB_GNT0_1 (0x7L<<4) 1552#define BCE_MISC_ARB_GNT0_2 (0x7L<<8) 1553#define BCE_MISC_ARB_GNT0_3 (0x7L<<12) 1554#define BCE_MISC_ARB_GNT0_4 (0x7L<<16) 1555#define BCE_MISC_ARB_GNT0_5 (0x7L<<20) 1556#define BCE_MISC_ARB_GNT0_6 (0x7L<<24) 1557#define BCE_MISC_ARB_GNT0_7 (0x7L<<28) 1558 1559#define BCE_MISC_ARB_GNT1 0x0000086c 1560#define BCE_MISC_ARB_GNT1_8 (0x7L<<0) 1561#define BCE_MISC_ARB_GNT1_9 (0x7L<<4) 1562#define BCE_MISC_ARB_GNT1_10 (0x7L<<8) 1563#define BCE_MISC_ARB_GNT1_11 (0x7L<<12) 1564#define BCE_MISC_ARB_GNT1_12 (0x7L<<16) 1565#define BCE_MISC_ARB_GNT1_13 (0x7L<<20) 1566#define BCE_MISC_ARB_GNT1_14 (0x7L<<24) 1567#define BCE_MISC_ARB_GNT1_15 (0x7L<<28) 1568 1569#define BCE_MISC_ARB_GNT2 0x00000870 1570#define BCE_MISC_ARB_GNT2_16 (0x7L<<0) 1571#define BCE_MISC_ARB_GNT2_17 (0x7L<<4) 1572#define BCE_MISC_ARB_GNT2_18 (0x7L<<8) 1573#define BCE_MISC_ARB_GNT2_19 (0x7L<<12) 1574#define BCE_MISC_ARB_GNT2_20 (0x7L<<16) 1575#define BCE_MISC_ARB_GNT2_21 (0x7L<<20) 1576#define BCE_MISC_ARB_GNT2_22 (0x7L<<24) 1577#define BCE_MISC_ARB_GNT2_23 (0x7L<<28) 1578 1579#define BCE_MISC_ARB_GNT3 0x00000874 1580#define BCE_MISC_ARB_GNT3_24 (0x7L<<0) 1581#define BCE_MISC_ARB_GNT3_25 (0x7L<<4) 1582#define BCE_MISC_ARB_GNT3_26 (0x7L<<8) 1583#define BCE_MISC_ARB_GNT3_27 (0x7L<<12) 1584#define BCE_MISC_ARB_GNT3_28 (0x7L<<16) 1585#define BCE_MISC_ARB_GNT3_29 (0x7L<<20) 1586#define BCE_MISC_ARB_GNT3_30 (0x7L<<24) 1587#define BCE_MISC_ARB_GNT3_31 (0x7L<<28) 1588 1589#define BCE_MISC_PRBS_CONTROL 0x00000878 1590#define BCE_MISC_PRBS_CONTROL_EN (1L<<0) 1591#define BCE_MISC_PRBS_CONTROL_RSTB (1L<<1) 1592#define BCE_MISC_PRBS_CONTROL_INV (1L<<2) 1593#define BCE_MISC_PRBS_CONTROL_ERR_CLR (1L<<3) 1594#define BCE_MISC_PRBS_CONTROL_ORDER (0x3L<<4) 1595#define BCE_MISC_PRBS_CONTROL_ORDER_7TH (0L<<4) 1596#define BCE_MISC_PRBS_CONTROL_ORDER_15TH (1L<<4) 1597#define BCE_MISC_PRBS_CONTROL_ORDER_23RD (2L<<4) 1598#define BCE_MISC_PRBS_CONTROL_ORDER_31ST (3L<<4) 1599 1600#define BCE_MISC_PRBS_STATUS 0x0000087c 1601#define BCE_MISC_PRBS_STATUS_LOCK (1L<<0) 1602#define BCE_MISC_PRBS_STATUS_STKY (1L<<1) 1603#define BCE_MISC_PRBS_STATUS_ERRORS (0x3fffL<<2) 1604#define BCE_MISC_PRBS_STATUS_STATE (0xfL<<16) 1605 1606#define BCE_MISC_SM_ASF_CONTROL 0x00000880 1607#define BCE_MISC_SM_ASF_CONTROL_ASF_RST (1L<<0) 1608#define BCE_MISC_SM_ASF_CONTROL_TSC_EN (1L<<1) 1609#define BCE_MISC_SM_ASF_CONTROL_WG_TO (1L<<2) 1610#define BCE_MISC_SM_ASF_CONTROL_HB_TO (1L<<3) 1611#define BCE_MISC_SM_ASF_CONTROL_PA_TO (1L<<4) 1612#define BCE_MISC_SM_ASF_CONTROL_PL_TO (1L<<5) 1613#define BCE_MISC_SM_ASF_CONTROL_RT_TO (1L<<6) 1614#define BCE_MISC_SM_ASF_CONTROL_SMB_EVENT (1L<<7) 1615#define BCE_MISC_SM_ASF_CONTROL_RES (0xfL<<8) 1616#define BCE_MISC_SM_ASF_CONTROL_SMB_EN (1L<<12) 1617#define BCE_MISC_SM_ASF_CONTROL_SMB_BB_EN (1L<<13) 1618#define BCE_MISC_SM_ASF_CONTROL_SMB_NO_ADDR_FILT (1L<<14) 1619#define BCE_MISC_SM_ASF_CONTROL_SMB_AUTOREAD (1L<<15) 1620#define BCE_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR1 (0x3fL<<16) 1621#define BCE_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR2 (0x3fL<<24) 1622#define BCE_MISC_SM_ASF_CONTROL_EN_NIC_SMB_ADDR_0 (1L<<30) 1623#define BCE_MISC_SM_ASF_CONTROL_SMB_EARLY_ATTN (1L<<31) 1624 1625#define BCE_MISC_SMB_IN 0x00000884 1626#define BCE_MISC_SMB_IN_DAT_IN (0xffL<<0) 1627#define BCE_MISC_SMB_IN_RDY (1L<<8) 1628#define BCE_MISC_SMB_IN_DONE (1L<<9) 1629#define BCE_MISC_SMB_IN_FIRSTBYTE (1L<<10) 1630#define BCE_MISC_SMB_IN_STATUS (0x7L<<11) 1631#define BCE_MISC_SMB_IN_STATUS_OK (0x0L<<11) 1632#define BCE_MISC_SMB_IN_STATUS_PEC (0x1L<<11) 1633#define BCE_MISC_SMB_IN_STATUS_OFLOW (0x2L<<11) 1634#define BCE_MISC_SMB_IN_STATUS_STOP (0x3L<<11) 1635#define BCE_MISC_SMB_IN_STATUS_TIMEOUT (0x4L<<11) 1636 1637#define BCE_MISC_SMB_OUT 0x00000888 1638#define BCE_MISC_SMB_OUT_DAT_OUT (0xffL<<0) 1639#define BCE_MISC_SMB_OUT_RDY (1L<<8) 1640#define BCE_MISC_SMB_OUT_START (1L<<9) 1641#define BCE_MISC_SMB_OUT_LAST (1L<<10) 1642#define BCE_MISC_SMB_OUT_ACC_TYPE (1L<<11) 1643#define BCE_MISC_SMB_OUT_ENB_PEC (1L<<12) 1644#define BCE_MISC_SMB_OUT_GET_RX_LEN (1L<<13) 1645#define BCE_MISC_SMB_OUT_SMB_READ_LEN (0x3fL<<14) 1646#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS (0xfL<<20) 1647#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_OK (0L<<20) 1648#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_NACK (1L<<20) 1649#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_NACK (9L<<20) 1650#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_UFLOW (2L<<20) 1651#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_STOP (3L<<20) 1652#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_TIMEOUT (4L<<20) 1653#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_LOST (5L<<20) 1654#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_LOST (0xdL<<20) 1655#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_BADACK (0x6L<<20) 1656#define BCE_MISC_SMB_OUT_SMB_OUT_SLAVEMODE (1L<<24) 1657#define BCE_MISC_SMB_OUT_SMB_OUT_DAT_EN (1L<<25) 1658#define BCE_MISC_SMB_OUT_SMB_OUT_DAT_IN (1L<<26) 1659#define BCE_MISC_SMB_OUT_SMB_OUT_CLK_EN (1L<<27) 1660#define BCE_MISC_SMB_OUT_SMB_OUT_CLK_IN (1L<<28) 1661 1662#define BCE_MISC_SMB_WATCHDOG 0x0000088c 1663#define BCE_MISC_SMB_WATCHDOG_WATCHDOG (0xffffL<<0) 1664 1665#define BCE_MISC_SMB_HEARTBEAT 0x00000890 1666#define BCE_MISC_SMB_HEARTBEAT_HEARTBEAT (0xffffL<<0) 1667 1668#define BCE_MISC_SMB_POLL_ASF 0x00000894 1669#define BCE_MISC_SMB_POLL_ASF_POLL_ASF (0xffffL<<0) 1670 1671#define BCE_MISC_SMB_POLL_LEGACY 0x00000898 1672#define BCE_MISC_SMB_POLL_LEGACY_POLL_LEGACY (0xffffL<<0) 1673 1674#define BCE_MISC_SMB_RETRAN 0x0000089c 1675#define BCE_MISC_SMB_RETRAN_RETRAN (0xffL<<0) 1676 1677#define BCE_MISC_SMB_TIMESTAMP 0x000008a0 1678#define BCE_MISC_SMB_TIMESTAMP_TIMESTAMP (0xffffffffL<<0) 1679 1680#define BCE_MISC_PERR_ENA0 0x000008a4 1681#define BCE_MISC_PERR_ENA0_COM_MISC_CTXC (1L<<0) 1682#define BCE_MISC_PERR_ENA0_COM_MISC_REGF (1L<<1) 1683#define BCE_MISC_PERR_ENA0_COM_MISC_SCPAD (1L<<2) 1684#define BCE_MISC_PERR_ENA0_CP_MISC_CTXC (1L<<3) 1685#define BCE_MISC_PERR_ENA0_CP_MISC_REGF (1L<<4) 1686#define BCE_MISC_PERR_ENA0_CP_MISC_SCPAD (1L<<5) 1687#define BCE_MISC_PERR_ENA0_CS_MISC_TMEM (1L<<6) 1688#define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM0 (1L<<7) 1689#define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM1 (1L<<8) 1690#define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM2 (1L<<9) 1691#define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM3 (1L<<10) 1692#define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM4 (1L<<11) 1693#define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM5 (1L<<12) 1694#define BCE_MISC_PERR_ENA0_CTX_MISC_PGTBL (1L<<13) 1695#define BCE_MISC_PERR_ENA0_DMAE_MISC_DR0 (1L<<14) 1696#define BCE_MISC_PERR_ENA0_DMAE_MISC_DR1 (1L<<15) 1697#define BCE_MISC_PERR_ENA0_DMAE_MISC_DR2 (1L<<16) 1698#define BCE_MISC_PERR_ENA0_DMAE_MISC_DR3 (1L<<17) 1699#define BCE_MISC_PERR_ENA0_DMAE_MISC_DR4 (1L<<18) 1700#define BCE_MISC_PERR_ENA0_DMAE_MISC_DW0 (1L<<19) 1701#define BCE_MISC_PERR_ENA0_DMAE_MISC_DW1 (1L<<20) 1702#define BCE_MISC_PERR_ENA0_DMAE_MISC_DW2 (1L<<21) 1703#define BCE_MISC_PERR_ENA0_HC_MISC_DMA (1L<<22) 1704#define BCE_MISC_PERR_ENA0_MCP_MISC_REGF (1L<<23) 1705#define BCE_MISC_PERR_ENA0_MCP_MISC_SCPAD (1L<<24) 1706#define BCE_MISC_PERR_ENA0_MQ_MISC_CTX (1L<<25) 1707#define BCE_MISC_PERR_ENA0_RBDC_MISC (1L<<26) 1708#define BCE_MISC_PERR_ENA0_RBUF_MISC_MB (1L<<27) 1709#define BCE_MISC_PERR_ENA0_RBUF_MISC_PTR (1L<<28) 1710#define BCE_MISC_PERR_ENA0_RDE_MISC_RPC (1L<<29) 1711#define BCE_MISC_PERR_ENA0_RDE_MISC_RPM (1L<<30) 1712#define BCE_MISC_PERR_ENA0_RV2P_MISC_CB0REGS (1L<<31) 1713 1714#define BCE_MISC_PERR_ENA1 0x000008a8 1715#define BCE_MISC_PERR_ENA1_RV2P_MISC_CB1REGS (1L<<0) 1716#define BCE_MISC_PERR_ENA1_RV2P_MISC_P1IRAM (1L<<1) 1717#define BCE_MISC_PERR_ENA1_RV2P_MISC_P2IRAM (1L<<2) 1718#define BCE_MISC_PERR_ENA1_RXP_MISC_CTXC (1L<<3) 1719#define BCE_MISC_PERR_ENA1_RXP_MISC_REGF (1L<<4) 1720#define BCE_MISC_PERR_ENA1_RXP_MISC_SCPAD (1L<<5) 1721#define BCE_MISC_PERR_ENA1_RXP_MISC_RBUFC (1L<<6) 1722#define BCE_MISC_PERR_ENA1_TBDC_MISC (1L<<7) 1723#define BCE_MISC_PERR_ENA1_TDMA_MISC (1L<<8) 1724#define BCE_MISC_PERR_ENA1_THBUF_MISC_MB0 (1L<<9) 1725#define BCE_MISC_PERR_ENA1_THBUF_MISC_MB1 (1L<<10) 1726#define BCE_MISC_PERR_ENA1_TPAT_MISC_REGF (1L<<11) 1727#define BCE_MISC_PERR_ENA1_TPAT_MISC_SCPAD (1L<<12) 1728#define BCE_MISC_PERR_ENA1_TPBUF_MISC_MB (1L<<13) 1729#define BCE_MISC_PERR_ENA1_TSCH_MISC_LR (1L<<14) 1730#define BCE_MISC_PERR_ENA1_TXP_MISC_CTXC (1L<<15) 1731#define BCE_MISC_PERR_ENA1_TXP_MISC_REGF (1L<<16) 1732#define BCE_MISC_PERR_ENA1_TXP_MISC_SCPAD (1L<<17) 1733#define BCE_MISC_PERR_ENA1_UMP_MISC_FIORX (1L<<18) 1734#define BCE_MISC_PERR_ENA1_UMP_MISC_FIOTX (1L<<19) 1735#define BCE_MISC_PERR_ENA1_UMP_MISC_RX (1L<<20) 1736#define BCE_MISC_PERR_ENA1_UMP_MISC_TX (1L<<21) 1737#define BCE_MISC_PERR_ENA1_RDMAQ_MISC (1L<<22) 1738#define BCE_MISC_PERR_ENA1_CSQ_MISC (1L<<23) 1739#define BCE_MISC_PERR_ENA1_CPQ_MISC (1L<<24) 1740#define BCE_MISC_PERR_ENA1_MCPQ_MISC (1L<<25) 1741#define BCE_MISC_PERR_ENA1_RV2PMQ_MISC (1L<<26) 1742#define BCE_MISC_PERR_ENA1_RV2PPQ_MISC (1L<<27) 1743#define BCE_MISC_PERR_ENA1_RV2PTQ_MISC (1L<<28) 1744#define BCE_MISC_PERR_ENA1_RXPQ_MISC (1L<<29) 1745#define BCE_MISC_PERR_ENA1_RXPCQ_MISC (1L<<30) 1746#define BCE_MISC_PERR_ENA1_RLUPQ_MISC (1L<<31) 1747 1748#define BCE_MISC_PERR_ENA2 0x000008ac 1749#define BCE_MISC_PERR_ENA2_COMQ_MISC (1L<<0) 1750#define BCE_MISC_PERR_ENA2_COMXQ_MISC (1L<<1) 1751#define BCE_MISC_PERR_ENA2_COMTQ_MISC (1L<<2) 1752#define BCE_MISC_PERR_ENA2_TSCHQ_MISC (1L<<3) 1753#define BCE_MISC_PERR_ENA2_TBDRQ_MISC (1L<<4) 1754#define BCE_MISC_PERR_ENA2_TXPQ_MISC (1L<<5) 1755#define BCE_MISC_PERR_ENA2_TDMAQ_MISC (1L<<6) 1756#define BCE_MISC_PERR_ENA2_TPATQ_MISC (1L<<7) 1757#define BCE_MISC_PERR_ENA2_TASQ_MISC (1L<<8) 1758 1759#define BCE_MISC_DEBUG_VECTOR_SEL 0x000008b0 1760#define BCE_MISC_DEBUG_VECTOR_SEL_0 (0xfffL<<0) 1761#define BCE_MISC_DEBUG_VECTOR_SEL_1 (0xfffL<<12) 1762 1763#define BCE_MISC_VREG_CONTROL 0x000008b4 1764#define BCE_MISC_VREG_CONTROL_1_2 (0xfL<<0) 1765#define BCE_MISC_VREG_CONTROL_2_5 (0xfL<<4) 1766 1767#define BCE_MISC_FINAL_CLK_CTL_VAL 0x000008b8 1768#define BCE_MISC_FINAL_CLK_CTL_VAL_MISC_FINAL_CLK_CTL_VAL (0x3ffffffL<<6) 1769 1770#define BCE_MISC_UNUSED0 0x000008bc 1771 1772 1773/* 1774 * nvm_reg definition 1775 * offset: 0x6400 1776 */ 1777#define BCE_NVM_COMMAND 0x00006400 1778#define BCE_NVM_COMMAND_RST (1L<<0) 1779#define BCE_NVM_COMMAND_DONE (1L<<3) 1780#define BCE_NVM_COMMAND_DOIT (1L<<4) 1781#define BCE_NVM_COMMAND_WR (1L<<5) 1782#define BCE_NVM_COMMAND_ERASE (1L<<6) 1783#define BCE_NVM_COMMAND_FIRST (1L<<7) 1784#define BCE_NVM_COMMAND_LAST (1L<<8) 1785#define BCE_NVM_COMMAND_WREN (1L<<16) 1786#define BCE_NVM_COMMAND_WRDI (1L<<17) 1787#define BCE_NVM_COMMAND_EWSR (1L<<18) 1788#define BCE_NVM_COMMAND_WRSR (1L<<19) 1789 1790#define BCE_NVM_STATUS 0x00006404 1791#define BCE_NVM_STATUS_PI_FSM_STATE (0xfL<<0) 1792#define BCE_NVM_STATUS_EE_FSM_STATE (0xfL<<4) 1793#define BCE_NVM_STATUS_EQ_FSM_STATE (0xfL<<8) 1794 1795#define BCE_NVM_WRITE 0x00006408 1796#define BCE_NVM_WRITE_NVM_WRITE_VALUE (0xffffffffL<<0) 1797#define BCE_NVM_WRITE_NVM_WRITE_VALUE_BIT_BANG (0L<<0) 1798#define BCE_NVM_WRITE_NVM_WRITE_VALUE_EECLK (1L<<0) 1799#define BCE_NVM_WRITE_NVM_WRITE_VALUE_EEDATA (2L<<0) 1800#define BCE_NVM_WRITE_NVM_WRITE_VALUE_SCLK (4L<<0) 1801#define BCE_NVM_WRITE_NVM_WRITE_VALUE_CS_B (8L<<0) 1802#define BCE_NVM_WRITE_NVM_WRITE_VALUE_SO (16L<<0) 1803#define BCE_NVM_WRITE_NVM_WRITE_VALUE_SI (32L<<0) 1804 1805#define BCE_NVM_ADDR 0x0000640c 1806#define BCE_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL<<0) 1807#define BCE_NVM_ADDR_NVM_ADDR_VALUE_BIT_BANG (0L<<0) 1808#define BCE_NVM_ADDR_NVM_ADDR_VALUE_EECLK (1L<<0) 1809#define BCE_NVM_ADDR_NVM_ADDR_VALUE_EEDATA (2L<<0) 1810#define BCE_NVM_ADDR_NVM_ADDR_VALUE_SCLK (4L<<0) 1811#define BCE_NVM_ADDR_NVM_ADDR_VALUE_CS_B (8L<<0) 1812#define BCE_NVM_ADDR_NVM_ADDR_VALUE_SO (16L<<0) 1813#define BCE_NVM_ADDR_NVM_ADDR_VALUE_SI (32L<<0) 1814 1815#define BCE_NVM_READ 0x00006410 1816#define BCE_NVM_READ_NVM_READ_VALUE (0xffffffffL<<0) 1817#define BCE_NVM_READ_NVM_READ_VALUE_BIT_BANG (0L<<0) 1818#define BCE_NVM_READ_NVM_READ_VALUE_EECLK (1L<<0) 1819#define BCE_NVM_READ_NVM_READ_VALUE_EEDATA (2L<<0) 1820#define BCE_NVM_READ_NVM_READ_VALUE_SCLK (4L<<0) 1821#define BCE_NVM_READ_NVM_READ_VALUE_CS_B (8L<<0) 1822#define BCE_NVM_READ_NVM_READ_VALUE_SO (16L<<0) 1823#define BCE_NVM_READ_NVM_READ_VALUE_SI (32L<<0) 1824 1825#define BCE_NVM_CFG1 0x00006414 1826#define BCE_NVM_CFG1_FLASH_MODE (1L<<0) 1827#define BCE_NVM_CFG1_BUFFER_MODE (1L<<1) 1828#define BCE_NVM_CFG1_PASS_MODE (1L<<2) 1829#define BCE_NVM_CFG1_BITBANG_MODE (1L<<3) 1830#define BCE_NVM_CFG1_STATUS_BIT (0x7L<<4) 1831#define BCE_NVM_CFG1_STATUS_BIT_FLASH_RDY (0L<<4) 1832#define BCE_NVM_CFG1_STATUS_BIT_BUFFER_RDY (7L<<4) 1833#define BCE_NVM_CFG1_SPI_CLK_DIV (0xfL<<7) 1834#define BCE_NVM_CFG1_SEE_CLK_DIV (0x7ffL<<11) 1835#define BCE_NVM_CFG1_PROTECT_MODE (1L<<24) 1836#define BCE_NVM_CFG1_FLASH_SIZE (1L<<25) 1837#define BCE_NVM_CFG1_COMPAT_BYPASSS (1L<<31) 1838 1839#define BCE_NVM_CFG2 0x00006418 1840#define BCE_NVM_CFG2_ERASE_CMD (0xffL<<0) 1841#define BCE_NVM_CFG2_DUMMY (0xffL<<8) 1842#define BCE_NVM_CFG2_STATUS_CMD (0xffL<<16) 1843 1844#define BCE_NVM_CFG3 0x0000641c 1845#define BCE_NVM_CFG3_BUFFER_RD_CMD (0xffL<<0) 1846#define BCE_NVM_CFG3_WRITE_CMD (0xffL<<8) 1847#define BCE_NVM_CFG3_BUFFER_WRITE_CMD (0xffL<<16) 1848#define BCE_NVM_CFG3_READ_CMD (0xffL<<24) 1849 1850#define BCE_NVM_SW_ARB 0x00006420 1851#define BCE_NVM_SW_ARB_ARB_REQ_SET0 (1L<<0) 1852#define BCE_NVM_SW_ARB_ARB_REQ_SET1 (1L<<1) 1853#define BCE_NVM_SW_ARB_ARB_REQ_SET2 (1L<<2) 1854#define BCE_NVM_SW_ARB_ARB_REQ_SET3 (1L<<3) 1855#define BCE_NVM_SW_ARB_ARB_REQ_CLR0 (1L<<4) 1856#define BCE_NVM_SW_ARB_ARB_REQ_CLR1 (1L<<5) 1857#define BCE_NVM_SW_ARB_ARB_REQ_CLR2 (1L<<6) 1858#define BCE_NVM_SW_ARB_ARB_REQ_CLR3 (1L<<7) 1859#define BCE_NVM_SW_ARB_ARB_ARB0 (1L<<8) 1860#define BCE_NVM_SW_ARB_ARB_ARB1 (1L<<9) 1861#define BCE_NVM_SW_ARB_ARB_ARB2 (1L<<10) 1862#define BCE_NVM_SW_ARB_ARB_ARB3 (1L<<11) 1863#define BCE_NVM_SW_ARB_REQ0 (1L<<12) 1864#define BCE_NVM_SW_ARB_REQ1 (1L<<13) 1865#define BCE_NVM_SW_ARB_REQ2 (1L<<14) 1866#define BCE_NVM_SW_ARB_REQ3 (1L<<15) 1867 1868#define BCE_NVM_ACCESS_ENABLE 0x00006424 1869#define BCE_NVM_ACCESS_ENABLE_EN (1L<<0) 1870#define BCE_NVM_ACCESS_ENABLE_WR_EN (1L<<1) 1871 1872#define BCE_NVM_WRITE1 0x00006428 1873#define BCE_NVM_WRITE1_WREN_CMD (0xffL<<0) 1874#define BCE_NVM_WRITE1_WRDI_CMD (0xffL<<8) 1875#define BCE_NVM_WRITE1_SR_DATA (0xffL<<16) 1876 1877 1878 1879/* 1880 * dma_reg definition 1881 * offset: 0xc00 1882 */ 1883#define BCE_DMA_COMMAND 0x00000c00 1884#define BCE_DMA_COMMAND_ENABLE (1L<<0) 1885 1886#define BCE_DMA_STATUS 0x00000c04 1887#define BCE_DMA_STATUS_PAR_ERROR_STATE (1L<<0) 1888#define BCE_DMA_STATUS_READ_TRANSFERS_STAT (1L<<16) 1889#define BCE_DMA_STATUS_READ_DELAY_PCI_CLKS_STAT (1L<<17) 1890#define BCE_DMA_STATUS_BIG_READ_TRANSFERS_STAT (1L<<18) 1891#define BCE_DMA_STATUS_BIG_READ_DELAY_PCI_CLKS_STAT (1L<<19) 1892#define BCE_DMA_STATUS_BIG_READ_RETRY_AFTER_DATA_STAT (1L<<20) 1893#define BCE_DMA_STATUS_WRITE_TRANSFERS_STAT (1L<<21) 1894#define BCE_DMA_STATUS_WRITE_DELAY_PCI_CLKS_STAT (1L<<22) 1895#define BCE_DMA_STATUS_BIG_WRITE_TRANSFERS_STAT (1L<<23) 1896#define BCE_DMA_STATUS_BIG_WRITE_DELAY_PCI_CLKS_STAT (1L<<24) 1897#define BCE_DMA_STATUS_BIG_WRITE_RETRY_AFTER_DATA_STAT (1L<<25) 1898 1899#define BCE_DMA_CONFIG 0x00000c08 1900#define BCE_DMA_CONFIG_DATA_BYTE_SWAP (1L<<0) 1901#define BCE_DMA_CONFIG_DATA_WORD_SWAP (1L<<1) 1902#define BCE_DMA_CONFIG_CNTL_BYTE_SWAP (1L<<4) 1903#define BCE_DMA_CONFIG_CNTL_WORD_SWAP (1L<<5) 1904#define BCE_DMA_CONFIG_ONE_DMA (1L<<6) 1905#define BCE_DMA_CONFIG_CNTL_TWO_DMA (1L<<7) 1906#define BCE_DMA_CONFIG_CNTL_FPGA_MODE (1L<<8) 1907#define BCE_DMA_CONFIG_CNTL_PING_PONG_DMA (1L<<10) 1908#define BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY (1L<<11) 1909#define BCE_DMA_CONFIG_NO_RCHANS_IN_USE (0xfL<<12) 1910#define BCE_DMA_CONFIG_NO_WCHANS_IN_USE (0xfL<<16) 1911#define BCE_DMA_CONFIG_PCI_CLK_CMP_BITS (0x7L<<20) 1912#define BCE_DMA_CONFIG_PCI_FAST_CLK_CMP (1L<<23) 1913#define BCE_DMA_CONFIG_BIG_SIZE (0xfL<<24) 1914#define BCE_DMA_CONFIG_BIG_SIZE_NONE (0x0L<<24) 1915#define BCE_DMA_CONFIG_BIG_SIZE_64 (0x1L<<24) 1916#define BCE_DMA_CONFIG_BIG_SIZE_128 (0x2L<<24) 1917#define BCE_DMA_CONFIG_BIG_SIZE_256 (0x4L<<24) 1918#define BCE_DMA_CONFIG_BIG_SIZE_512 (0x8L<<24) 1919 1920#define BCE_DMA_BLACKOUT 0x00000c0c 1921#define BCE_DMA_BLACKOUT_RD_RETRY_BLACKOUT (0xffL<<0) 1922#define BCE_DMA_BLACKOUT_2ND_RD_RETRY_BLACKOUT (0xffL<<8) 1923#define BCE_DMA_BLACKOUT_WR_RETRY_BLACKOUT (0xffL<<16) 1924 1925#define BCE_DMA_RCHAN_STAT 0x00000c30 1926#define BCE_DMA_RCHAN_STAT_COMP_CODE_0 (0x7L<<0) 1927#define BCE_DMA_RCHAN_STAT_PAR_ERR_0 (1L<<3) 1928#define BCE_DMA_RCHAN_STAT_COMP_CODE_1 (0x7L<<4) 1929#define BCE_DMA_RCHAN_STAT_PAR_ERR_1 (1L<<7) 1930#define BCE_DMA_RCHAN_STAT_COMP_CODE_2 (0x7L<<8) 1931#define BCE_DMA_RCHAN_STAT_PAR_ERR_2 (1L<<11) 1932#define BCE_DMA_RCHAN_STAT_COMP_CODE_3 (0x7L<<12) 1933#define BCE_DMA_RCHAN_STAT_PAR_ERR_3 (1L<<15) 1934#define BCE_DMA_RCHAN_STAT_COMP_CODE_4 (0x7L<<16) 1935#define BCE_DMA_RCHAN_STAT_PAR_ERR_4 (1L<<19) 1936#define BCE_DMA_RCHAN_STAT_COMP_CODE_5 (0x7L<<20) 1937#define BCE_DMA_RCHAN_STAT_PAR_ERR_5 (1L<<23) 1938#define BCE_DMA_RCHAN_STAT_COMP_CODE_6 (0x7L<<24) 1939#define BCE_DMA_RCHAN_STAT_PAR_ERR_6 (1L<<27) 1940#define BCE_DMA_RCHAN_STAT_COMP_CODE_7 (0x7L<<28) 1941#define BCE_DMA_RCHAN_STAT_PAR_ERR_7 (1L<<31) 1942 1943#define BCE_DMA_WCHAN_STAT 0x00000c34 1944#define BCE_DMA_WCHAN_STAT_COMP_CODE_0 (0x7L<<0) 1945#define BCE_DMA_WCHAN_STAT_PAR_ERR_0 (1L<<3) 1946#define BCE_DMA_WCHAN_STAT_COMP_CODE_1 (0x7L<<4) 1947#define BCE_DMA_WCHAN_STAT_PAR_ERR_1 (1L<<7) 1948#define BCE_DMA_WCHAN_STAT_COMP_CODE_2 (0x7L<<8) 1949#define BCE_DMA_WCHAN_STAT_PAR_ERR_2 (1L<<11) 1950#define BCE_DMA_WCHAN_STAT_COMP_CODE_3 (0x7L<<12) 1951#define BCE_DMA_WCHAN_STAT_PAR_ERR_3 (1L<<15) 1952#define BCE_DMA_WCHAN_STAT_COMP_CODE_4 (0x7L<<16) 1953#define BCE_DMA_WCHAN_STAT_PAR_ERR_4 (1L<<19) 1954#define BCE_DMA_WCHAN_STAT_COMP_CODE_5 (0x7L<<20) 1955#define BCE_DMA_WCHAN_STAT_PAR_ERR_5 (1L<<23) 1956#define BCE_DMA_WCHAN_STAT_COMP_CODE_6 (0x7L<<24) 1957#define BCE_DMA_WCHAN_STAT_PAR_ERR_6 (1L<<27) 1958#define BCE_DMA_WCHAN_STAT_COMP_CODE_7 (0x7L<<28) 1959#define BCE_DMA_WCHAN_STAT_PAR_ERR_7 (1L<<31) 1960 1961#define BCE_DMA_RCHAN_ASSIGNMENT 0x00000c38 1962#define BCE_DMA_RCHAN_ASSIGNMENT_0 (0xfL<<0) 1963#define BCE_DMA_RCHAN_ASSIGNMENT_1 (0xfL<<4) 1964#define BCE_DMA_RCHAN_ASSIGNMENT_2 (0xfL<<8) 1965#define BCE_DMA_RCHAN_ASSIGNMENT_3 (0xfL<<12) 1966#define BCE_DMA_RCHAN_ASSIGNMENT_4 (0xfL<<16) 1967#define BCE_DMA_RCHAN_ASSIGNMENT_5 (0xfL<<20) 1968#define BCE_DMA_RCHAN_ASSIGNMENT_6 (0xfL<<24) 1969#define BCE_DMA_RCHAN_ASSIGNMENT_7 (0xfL<<28) 1970 1971#define BCE_DMA_WCHAN_ASSIGNMENT 0x00000c3c 1972#define BCE_DMA_WCHAN_ASSIGNMENT_0 (0xfL<<0) 1973#define BCE_DMA_WCHAN_ASSIGNMENT_1 (0xfL<<4) 1974#define BCE_DMA_WCHAN_ASSIGNMENT_2 (0xfL<<8) 1975#define BCE_DMA_WCHAN_ASSIGNMENT_3 (0xfL<<12) 1976#define BCE_DMA_WCHAN_ASSIGNMENT_4 (0xfL<<16) 1977#define BCE_DMA_WCHAN_ASSIGNMENT_5 (0xfL<<20) 1978#define BCE_DMA_WCHAN_ASSIGNMENT_6 (0xfL<<24) 1979#define BCE_DMA_WCHAN_ASSIGNMENT_7 (0xfL<<28) 1980 1981#define BCE_DMA_RCHAN_STAT_00 0x00000c40 1982#define BCE_DMA_RCHAN_STAT_00_RCHAN_STA_HOST_ADDR_LOW (0xffffffffL<<0) 1983 1984#define BCE_DMA_RCHAN_STAT_01 0x00000c44 1985#define BCE_DMA_RCHAN_STAT_01_RCHAN_STA_HOST_ADDR_HIGH (0xffffffffL<<0) 1986 1987#define BCE_DMA_RCHAN_STAT_02 0x00000c48 1988#define BCE_DMA_RCHAN_STAT_02_LENGTH (0xffffL<<0) 1989#define BCE_DMA_RCHAN_STAT_02_WORD_SWAP (1L<<16) 1990#define BCE_DMA_RCHAN_STAT_02_BYTE_SWAP (1L<<17) 1991#define BCE_DMA_RCHAN_STAT_02_PRIORITY_LVL (1L<<18) 1992 1993#define BCE_DMA_RCHAN_STAT_10 0x00000c4c 1994#define BCE_DMA_RCHAN_STAT_11 0x00000c50 1995#define BCE_DMA_RCHAN_STAT_12 0x00000c54 1996#define BCE_DMA_RCHAN_STAT_20 0x00000c58 1997#define BCE_DMA_RCHAN_STAT_21 0x00000c5c 1998#define BCE_DMA_RCHAN_STAT_22 0x00000c60 1999#define BCE_DMA_RCHAN_STAT_30 0x00000c64 2000#define BCE_DMA_RCHAN_STAT_31 0x00000c68 2001#define BCE_DMA_RCHAN_STAT_32 0x00000c6c 2002#define BCE_DMA_RCHAN_STAT_40 0x00000c70 2003#define BCE_DMA_RCHAN_STAT_41 0x00000c74 2004#define BCE_DMA_RCHAN_STAT_42 0x00000c78 2005#define BCE_DMA_RCHAN_STAT_50 0x00000c7c 2006#define BCE_DMA_RCHAN_STAT_51 0x00000c80 2007#define BCE_DMA_RCHAN_STAT_52 0x00000c84 2008#define BCE_DMA_RCHAN_STAT_60 0x00000c88 2009#define BCE_DMA_RCHAN_STAT_61 0x00000c8c 2010#define BCE_DMA_RCHAN_STAT_62 0x00000c90 2011#define BCE_DMA_RCHAN_STAT_70 0x00000c94 2012#define BCE_DMA_RCHAN_STAT_71 0x00000c98 2013#define BCE_DMA_RCHAN_STAT_72 0x00000c9c 2014#define BCE_DMA_WCHAN_STAT_00 0x00000ca0 2015#define BCE_DMA_WCHAN_STAT_00_WCHAN_STA_HOST_ADDR_LOW (0xffffffffL<<0) 2016 2017#define BCE_DMA_WCHAN_STAT_01 0x00000ca4 2018#define BCE_DMA_WCHAN_STAT_01_WCHAN_STA_HOST_ADDR_HIGH (0xffffffffL<<0) 2019 2020#define BCE_DMA_WCHAN_STAT_02 0x00000ca8 2021#define BCE_DMA_WCHAN_STAT_02_LENGTH (0xffffL<<0) 2022#define BCE_DMA_WCHAN_STAT_02_WORD_SWAP (1L<<16) 2023#define BCE_DMA_WCHAN_STAT_02_BYTE_SWAP (1L<<17) 2024#define BCE_DMA_WCHAN_STAT_02_PRIORITY_LVL (1L<<18) 2025 2026#define BCE_DMA_WCHAN_STAT_10 0x00000cac 2027#define BCE_DMA_WCHAN_STAT_11 0x00000cb0 2028#define BCE_DMA_WCHAN_STAT_12 0x00000cb4 2029#define BCE_DMA_WCHAN_STAT_20 0x00000cb8 2030#define BCE_DMA_WCHAN_STAT_21 0x00000cbc 2031#define BCE_DMA_WCHAN_STAT_22 0x00000cc0 2032#define BCE_DMA_WCHAN_STAT_30 0x00000cc4 2033#define BCE_DMA_WCHAN_STAT_31 0x00000cc8 2034#define BCE_DMA_WCHAN_STAT_32 0x00000ccc 2035#define BCE_DMA_WCHAN_STAT_40 0x00000cd0 2036#define BCE_DMA_WCHAN_STAT_41 0x00000cd4 2037#define BCE_DMA_WCHAN_STAT_42 0x00000cd8 2038#define BCE_DMA_WCHAN_STAT_50 0x00000cdc 2039#define BCE_DMA_WCHAN_STAT_51 0x00000ce0 2040#define BCE_DMA_WCHAN_STAT_52 0x00000ce4 2041#define BCE_DMA_WCHAN_STAT_60 0x00000ce8 2042#define BCE_DMA_WCHAN_STAT_61 0x00000cec 2043#define BCE_DMA_WCHAN_STAT_62 0x00000cf0 2044#define BCE_DMA_WCHAN_STAT_70 0x00000cf4 2045#define BCE_DMA_WCHAN_STAT_71 0x00000cf8 2046#define BCE_DMA_WCHAN_STAT_72 0x00000cfc 2047#define BCE_DMA_ARB_STAT_00 0x00000d00 2048#define BCE_DMA_ARB_STAT_00_MASTER (0xffffL<<0) 2049#define BCE_DMA_ARB_STAT_00_MASTER_ENC (0xffL<<16) 2050#define BCE_DMA_ARB_STAT_00_CUR_BINMSTR (0xffL<<24) 2051 2052#define BCE_DMA_ARB_STAT_01 0x00000d04 2053#define BCE_DMA_ARB_STAT_01_LPR_RPTR (0xfL<<0) 2054#define BCE_DMA_ARB_STAT_01_LPR_WPTR (0xfL<<4) 2055#define BCE_DMA_ARB_STAT_01_LPB_RPTR (0xfL<<8) 2056#define BCE_DMA_ARB_STAT_01_LPB_WPTR (0xfL<<12) 2057#define BCE_DMA_ARB_STAT_01_HPR_RPTR (0xfL<<16) 2058#define BCE_DMA_ARB_STAT_01_HPR_WPTR (0xfL<<20) 2059#define BCE_DMA_ARB_STAT_01_HPB_RPTR (0xfL<<24) 2060#define BCE_DMA_ARB_STAT_01_HPB_WPTR (0xfL<<28) 2061 2062#define BCE_DMA_FUSE_CTRL0_CMD 0x00000f00 2063#define BCE_DMA_FUSE_CTRL0_CMD_PWRUP_DONE (1L<<0) 2064#define BCE_DMA_FUSE_CTRL0_CMD_SHIFT_DONE (1L<<1) 2065#define BCE_DMA_FUSE_CTRL0_CMD_SHIFT (1L<<2) 2066#define BCE_DMA_FUSE_CTRL0_CMD_LOAD (1L<<3) 2067#define BCE_DMA_FUSE_CTRL0_CMD_SEL (0xfL<<8) 2068 2069#define BCE_DMA_FUSE_CTRL0_DATA 0x00000f04 2070#define BCE_DMA_FUSE_CTRL1_CMD 0x00000f08 2071#define BCE_DMA_FUSE_CTRL1_CMD_PWRUP_DONE (1L<<0) 2072#define BCE_DMA_FUSE_CTRL1_CMD_SHIFT_DONE (1L<<1) 2073#define BCE_DMA_FUSE_CTRL1_CMD_SHIFT (1L<<2) 2074#define BCE_DMA_FUSE_CTRL1_CMD_LOAD (1L<<3) 2075#define BCE_DMA_FUSE_CTRL1_CMD_SEL (0xfL<<8) 2076 2077#define BCE_DMA_FUSE_CTRL1_DATA 0x00000f0c 2078#define BCE_DMA_FUSE_CTRL2_CMD 0x00000f10 2079#define BCE_DMA_FUSE_CTRL2_CMD_PWRUP_DONE (1L<<0) 2080#define BCE_DMA_FUSE_CTRL2_CMD_SHIFT_DONE (1L<<1) 2081#define BCE_DMA_FUSE_CTRL2_CMD_SHIFT (1L<<2) 2082#define BCE_DMA_FUSE_CTRL2_CMD_LOAD (1L<<3) 2083#define BCE_DMA_FUSE_CTRL2_CMD_SEL (0xfL<<8) 2084 2085#define BCE_DMA_FUSE_CTRL2_DATA 0x00000f14 2086 2087 2088/* 2089 * context_reg definition 2090 * offset: 0x1000 2091 */ 2092#define BCE_CTX_COMMAND 0x00001000 2093#define BCE_CTX_COMMAND_ENABLED (1L<<0) 2094 2095#define BCE_CTX_STATUS 0x00001004 2096#define BCE_CTX_STATUS_LOCK_WAIT (1L<<0) 2097#define BCE_CTX_STATUS_READ_STAT (1L<<16) 2098#define BCE_CTX_STATUS_WRITE_STAT (1L<<17) 2099#define BCE_CTX_STATUS_ACC_STALL_STAT (1L<<18) 2100#define BCE_CTX_STATUS_LOCK_STALL_STAT (1L<<19) 2101 2102#define BCE_CTX_VIRT_ADDR 0x00001008 2103#define BCE_CTX_VIRT_ADDR_VIRT_ADDR (0x7fffL<<6) 2104 2105#define BCE_CTX_PAGE_TBL 0x0000100c 2106#define BCE_CTX_PAGE_TBL_PAGE_TBL (0x3fffL<<6) 2107 2108#define BCE_CTX_DATA_ADR 0x00001010 2109#define BCE_CTX_DATA_ADR_DATA_ADR (0x7ffffL<<2) 2110 2111#define BCE_CTX_DATA 0x00001014 2112#define BCE_CTX_LOCK 0x00001018 2113#define BCE_CTX_LOCK_TYPE (0x7L<<0) 2114#define BCE_CTX_LOCK_TYPE_LOCK_TYPE_VOID (0x0L<<0) 2115#define BCE_CTX_LOCK_TYPE_LOCK_TYPE_COMPLETE (0x7L<<0) 2116#define BCE_CTX_LOCK_TYPE_LOCK_TYPE_PROTOCOL (0x1L<<0) 2117#define BCE_CTX_LOCK_TYPE_LOCK_TYPE_TX (0x2L<<0) 2118#define BCE_CTX_LOCK_TYPE_LOCK_TYPE_TIMER (0x4L<<0) 2119#define BCE_CTX_LOCK_CID_VALUE (0x3fffL<<7) 2120#define BCE_CTX_LOCK_GRANTED (1L<<26) 2121#define BCE_CTX_LOCK_MODE (0x7L<<27) 2122#define BCE_CTX_LOCK_MODE_UNLOCK (0x0L<<27) 2123#define BCE_CTX_LOCK_MODE_IMMEDIATE (0x1L<<27) 2124#define BCE_CTX_LOCK_MODE_SURE (0x2L<<27) 2125#define BCE_CTX_LOCK_STATUS (1L<<30) 2126#define BCE_CTX_LOCK_REQ (1L<<31) 2127 2128#define BCE_CTX_ACCESS_STATUS 0x00001040 2129#define BCE_CTX_ACCESS_STATUS_MASTERENCODED (0xfL<<0) 2130#define BCE_CTX_ACCESS_STATUS_ACCESSMEMORYSM (0x3L<<10) 2131#define BCE_CTX_ACCESS_STATUS_PAGETABLEINITSM (0x3L<<12) 2132#define BCE_CTX_ACCESS_STATUS_ACCESSMEMORYINITSM (0x3L<<14) 2133#define BCE_CTX_ACCESS_STATUS_QUALIFIED_REQUEST (0x7ffL<<17) 2134 2135#define BCE_CTX_DBG_LOCK_STATUS 0x00001044 2136#define BCE_CTX_DBG_LOCK_STATUS_SM (0x3ffL<<0) 2137#define BCE_CTX_DBG_LOCK_STATUS_MATCH (0x3ffL<<22) 2138 2139#define BCE_CTX_CHNL_LOCK_STATUS_0 0x00001080 2140#define BCE_CTX_CHNL_LOCK_STATUS_0_CID (0x3fffL<<0) 2141#define BCE_CTX_CHNL_LOCK_STATUS_0_TYPE (0x3L<<14) 2142#define BCE_CTX_CHNL_LOCK_STATUS_0_MODE (1L<<16) 2143 2144#define BCE_CTX_CHNL_LOCK_STATUS_1 0x00001084 2145#define BCE_CTX_CHNL_LOCK_STATUS_2 0x00001088 2146#define BCE_CTX_CHNL_LOCK_STATUS_3 0x0000108c 2147#define BCE_CTX_CHNL_LOCK_STATUS_4 0x00001090 2148#define BCE_CTX_CHNL_LOCK_STATUS_5 0x00001094 2149#define BCE_CTX_CHNL_LOCK_STATUS_6 0x00001098 2150#define BCE_CTX_CHNL_LOCK_STATUS_7 0x0000109c 2151#define BCE_CTX_CHNL_LOCK_STATUS_8 0x000010a0 2152 2153 2154/* 2155 * emac_reg definition 2156 * offset: 0x1400 2157 */ 2158#define BCE_EMAC_MODE 0x00001400 2159#define BCE_EMAC_MODE_RESET (1L<<0) 2160#define BCE_EMAC_MODE_HALF_DUPLEX (1L<<1) 2161#define BCE_EMAC_MODE_PORT (0x3L<<2) 2162#define BCE_EMAC_MODE_PORT_NONE (0L<<2) 2163#define BCE_EMAC_MODE_PORT_MII (1L<<2) 2164#define BCE_EMAC_MODE_PORT_GMII (2L<<2) 2165#define BCE_EMAC_MODE_PORT_MII_10 (3L<<2) 2166#define BCE_EMAC_MODE_MAC_LOOP (1L<<4) 2167#define BCE_EMAC_MODE_25G (1L<<5) 2168#define BCE_EMAC_MODE_TAGGED_MAC_CTL (1L<<7) 2169#define BCE_EMAC_MODE_TX_BURST (1L<<8) 2170#define BCE_EMAC_MODE_MAX_DEFER_DROP_ENA (1L<<9) 2171#define BCE_EMAC_MODE_EXT_LINK_POL (1L<<10) 2172#define BCE_EMAC_MODE_FORCE_LINK (1L<<11) 2173#define BCE_EMAC_MODE_MPKT (1L<<18) 2174#define BCE_EMAC_MODE_MPKT_RCVD (1L<<19) 2175#define BCE_EMAC_MODE_ACPI_RCVD (1L<<20) 2176 2177#define BCE_EMAC_STATUS 0x00001404 2178#define BCE_EMAC_STATUS_LINK (1L<<11) 2179#define BCE_EMAC_STATUS_LINK_CHANGE (1L<<12) 2180#define BCE_EMAC_STATUS_MI_COMPLETE (1L<<22) 2181#define BCE_EMAC_STATUS_MI_INT (1L<<23) 2182#define BCE_EMAC_STATUS_AP_ERROR (1L<<24) 2183#define BCE_EMAC_STATUS_PARITY_ERROR_STATE (1L<<31) 2184 2185#define BCE_EMAC_ATTENTION_ENA 0x00001408 2186#define BCE_EMAC_ATTENTION_ENA_LINK (1L<<11) 2187#define BCE_EMAC_ATTENTION_ENA_MI_COMPLETE (1L<<22) 2188#define BCE_EMAC_ATTENTION_ENA_MI_INT (1L<<23) 2189#define BCE_EMAC_ATTENTION_ENA_AP_ERROR (1L<<24) 2190 2191#define BCE_EMAC_LED 0x0000140c 2192#define BCE_EMAC_LED_OVERRIDE (1L<<0) 2193#define BCE_EMAC_LED_1000MB_OVERRIDE (1L<<1) 2194#define BCE_EMAC_LED_100MB_OVERRIDE (1L<<2) 2195#define BCE_EMAC_LED_10MB_OVERRIDE (1L<<3) 2196#define BCE_EMAC_LED_TRAFFIC_OVERRIDE (1L<<4) 2197#define BCE_EMAC_LED_BLNK_TRAFFIC (1L<<5) 2198#define BCE_EMAC_LED_TRAFFIC (1L<<6) 2199#define BCE_EMAC_LED_1000MB (1L<<7) 2200#define BCE_EMAC_LED_100MB (1L<<8) 2201#define BCE_EMAC_LED_10MB (1L<<9) 2202#define BCE_EMAC_LED_TRAFFIC_STAT (1L<<10) 2203#define BCE_EMAC_LED_BLNK_RATE (0xfffL<<19) 2204#define BCE_EMAC_LED_BLNK_RATE_ENA (1L<<31) 2205 2206#define BCE_EMAC_MAC_MATCH0 0x00001410 2207#define BCE_EMAC_MAC_MATCH1 0x00001414 2208#define BCE_EMAC_MAC_MATCH2 0x00001418 2209#define BCE_EMAC_MAC_MATCH3 0x0000141c 2210#define BCE_EMAC_MAC_MATCH4 0x00001420 2211#define BCE_EMAC_MAC_MATCH5 0x00001424 2212#define BCE_EMAC_MAC_MATCH6 0x00001428 2213#define BCE_EMAC_MAC_MATCH7 0x0000142c 2214#define BCE_EMAC_MAC_MATCH8 0x00001430 2215#define BCE_EMAC_MAC_MATCH9 0x00001434 2216#define BCE_EMAC_MAC_MATCH10 0x00001438 2217#define BCE_EMAC_MAC_MATCH11 0x0000143c 2218#define BCE_EMAC_MAC_MATCH12 0x00001440 2219#define BCE_EMAC_MAC_MATCH13 0x00001444 2220#define BCE_EMAC_MAC_MATCH14 0x00001448 2221#define BCE_EMAC_MAC_MATCH15 0x0000144c 2222#define BCE_EMAC_MAC_MATCH16 0x00001450 2223#define BCE_EMAC_MAC_MATCH17 0x00001454 2224#define BCE_EMAC_MAC_MATCH18 0x00001458 2225#define BCE_EMAC_MAC_MATCH19 0x0000145c 2226#define BCE_EMAC_MAC_MATCH20 0x00001460 2227#define BCE_EMAC_MAC_MATCH21 0x00001464 2228#define BCE_EMAC_MAC_MATCH22 0x00001468 2229#define BCE_EMAC_MAC_MATCH23 0x0000146c 2230#define BCE_EMAC_MAC_MATCH24 0x00001470 2231#define BCE_EMAC_MAC_MATCH25 0x00001474 2232#define BCE_EMAC_MAC_MATCH26 0x00001478 2233#define BCE_EMAC_MAC_MATCH27 0x0000147c 2234#define BCE_EMAC_MAC_MATCH28 0x00001480 2235#define BCE_EMAC_MAC_MATCH29 0x00001484 2236#define BCE_EMAC_MAC_MATCH30 0x00001488 2237#define BCE_EMAC_MAC_MATCH31 0x0000148c 2238#define BCE_EMAC_BACKOFF_SEED 0x00001498 2239#define BCE_EMAC_BACKOFF_SEED_EMAC_BACKOFF_SEED (0x3ffL<<0) 2240 2241#define BCE_EMAC_RX_MTU_SIZE 0x0000149c 2242#define BCE_EMAC_RX_MTU_SIZE_MTU_SIZE (0xffffL<<0) 2243#define BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31) 2244 2245#define BCE_EMAC_SERDES_CNTL 0x000014a4 2246#define BCE_EMAC_SERDES_CNTL_RXR (0x7L<<0) 2247#define BCE_EMAC_SERDES_CNTL_RXG (0x3L<<3) 2248#define BCE_EMAC_SERDES_CNTL_RXCKSEL (1L<<6) 2249#define BCE_EMAC_SERDES_CNTL_TXBIAS (0x7L<<7) 2250#define BCE_EMAC_SERDES_CNTL_BGMAX (1L<<10) 2251#define BCE_EMAC_SERDES_CNTL_BGMIN (1L<<11) 2252#define BCE_EMAC_SERDES_CNTL_TXMODE (1L<<12) 2253#define BCE_EMAC_SERDES_CNTL_TXEDGE (1L<<13) 2254#define BCE_EMAC_SERDES_CNTL_SERDES_MODE (1L<<14) 2255#define BCE_EMAC_SERDES_CNTL_PLLTEST (1L<<15) 2256#define BCE_EMAC_SERDES_CNTL_CDET_EN (1L<<16) 2257#define BCE_EMAC_SERDES_CNTL_TBI_LBK (1L<<17) 2258#define BCE_EMAC_SERDES_CNTL_REMOTE_LBK (1L<<18) 2259#define BCE_EMAC_SERDES_CNTL_REV_PHASE (1L<<19) 2260#define BCE_EMAC_SERDES_CNTL_REGCTL12 (0x3L<<20) 2261#define BCE_EMAC_SERDES_CNTL_REGCTL25 (0x3L<<22) 2262 2263#define BCE_EMAC_SERDES_STATUS 0x000014a8 2264#define BCE_EMAC_SERDES_STATUS_RX_STAT (0xffL<<0) 2265#define BCE_EMAC_SERDES_STATUS_COMMA_DET (1L<<8) 2266 2267#define BCE_EMAC_MDIO_COMM 0x000014ac 2268#define BCE_EMAC_MDIO_COMM_DATA (0xffffL<<0) 2269#define BCE_EMAC_MDIO_COMM_REG_ADDR (0x1fL<<16) 2270#define BCE_EMAC_MDIO_COMM_PHY_ADDR (0x1fL<<21) 2271#define BCE_EMAC_MDIO_COMM_COMMAND (0x3L<<26) 2272#define BCE_EMAC_MDIO_COMM_COMMAND_UNDEFINED_0 (0L<<26) 2273#define BCE_EMAC_MDIO_COMM_COMMAND_WRITE (1L<<26) 2274#define BCE_EMAC_MDIO_COMM_COMMAND_READ (2L<<26) 2275#define BCE_EMAC_MDIO_COMM_COMMAND_UNDEFINED_3 (3L<<26) 2276#define BCE_EMAC_MDIO_COMM_FAIL (1L<<28) 2277#define BCE_EMAC_MDIO_COMM_START_BUSY (1L<<29) 2278#define BCE_EMAC_MDIO_COMM_DISEXT (1L<<30) 2279 2280#define BCE_EMAC_MDIO_STATUS 0x000014b0 2281#define BCE_EMAC_MDIO_STATUS_LINK (1L<<0) 2282#define BCE_EMAC_MDIO_STATUS_10MB (1L<<1) 2283 2284#define BCE_EMAC_MDIO_MODE 0x000014b4 2285#define BCE_EMAC_MDIO_MODE_SHORT_PREAMBLE (1L<<1) 2286#define BCE_EMAC_MDIO_MODE_AUTO_POLL (1L<<4) 2287#define BCE_EMAC_MDIO_MODE_BIT_BANG (1L<<8) 2288#define BCE_EMAC_MDIO_MODE_MDIO (1L<<9) 2289#define BCE_EMAC_MDIO_MODE_MDIO_OE (1L<<10) 2290#define BCE_EMAC_MDIO_MODE_MDC (1L<<11) 2291#define BCE_EMAC_MDIO_MODE_MDINT (1L<<12) 2292#define BCE_EMAC_MDIO_MODE_CLOCK_CNT (0x1fL<<16) 2293 2294#define BCE_EMAC_MDIO_AUTO_STATUS 0x000014b8 2295#define BCE_EMAC_MDIO_AUTO_STATUS_AUTO_ERR (1L<<0) 2296 2297#define BCE_EMAC_TX_MODE 0x000014bc 2298#define BCE_EMAC_TX_MODE_RESET (1L<<0) 2299#define BCE_EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3) 2300#define BCE_EMAC_TX_MODE_FLOW_EN (1L<<4) 2301#define BCE_EMAC_TX_MODE_BIG_BACKOFF (1L<<5) 2302#define BCE_EMAC_TX_MODE_LONG_PAUSE (1L<<6) 2303#define BCE_EMAC_TX_MODE_LINK_AWARE (1L<<7) 2304 2305#define BCE_EMAC_TX_STATUS 0x000014c0 2306#define BCE_EMAC_TX_STATUS_XOFFED (1L<<0) 2307#define BCE_EMAC_TX_STATUS_XOFF_SENT (1L<<1) 2308#define BCE_EMAC_TX_STATUS_XON_SENT (1L<<2) 2309#define BCE_EMAC_TX_STATUS_LINK_UP (1L<<3) 2310#define BCE_EMAC_TX_STATUS_UNDERRUN (1L<<4) 2311 2312#define BCE_EMAC_TX_LENGTHS 0x000014c4 2313#define BCE_EMAC_TX_LENGTHS_SLOT (0xffL<<0) 2314#define BCE_EMAC_TX_LENGTHS_IPG (0xfL<<8) 2315#define BCE_EMAC_TX_LENGTHS_IPG_CRS (0x3L<<12) 2316 2317#define BCE_EMAC_RX_MODE 0x000014c8 2318#define BCE_EMAC_RX_MODE_RESET (1L<<0) 2319#define BCE_EMAC_RX_MODE_FLOW_EN (1L<<2) 2320#define BCE_EMAC_RX_MODE_KEEP_MAC_CONTROL (1L<<3) 2321#define BCE_EMAC_RX_MODE_KEEP_PAUSE (1L<<4) 2322#define BCE_EMAC_RX_MODE_ACCEPT_OVERSIZE (1L<<5) 2323#define BCE_EMAC_RX_MODE_ACCEPT_RUNTS (1L<<6) 2324#define BCE_EMAC_RX_MODE_LLC_CHK (1L<<7) 2325#define BCE_EMAC_RX_MODE_PROMISCUOUS (1L<<8) 2326#define BCE_EMAC_RX_MODE_NO_CRC_CHK (1L<<9) 2327#define BCE_EMAC_RX_MODE_KEEP_VLAN_TAG (1L<<10) 2328#define BCE_EMAC_RX_MODE_FILT_BROADCAST (1L<<11) 2329#define BCE_EMAC_RX_MODE_SORT_MODE (1L<<12) 2330 2331#define BCE_EMAC_RX_STATUS 0x000014cc 2332#define BCE_EMAC_RX_STATUS_FFED (1L<<0) 2333#define BCE_EMAC_RX_STATUS_FF_RECEIVED (1L<<1) 2334#define BCE_EMAC_RX_STATUS_N_RECEIVED (1L<<2) 2335 2336#define BCE_EMAC_MULTICAST_HASH0 0x000014d0 2337#define BCE_EMAC_MULTICAST_HASH1 0x000014d4 2338#define BCE_EMAC_MULTICAST_HASH2 0x000014d8 2339#define BCE_EMAC_MULTICAST_HASH3 0x000014dc 2340#define BCE_EMAC_MULTICAST_HASH4 0x000014e0 2341#define BCE_EMAC_MULTICAST_HASH5 0x000014e4 2342#define BCE_EMAC_MULTICAST_HASH6 0x000014e8 2343#define BCE_EMAC_MULTICAST_HASH7 0x000014ec 2344#define BCE_EMAC_RX_STAT_IFHCINOCTETS 0x00001500 2345#define BCE_EMAC_RX_STAT_IFHCINBADOCTETS 0x00001504 2346#define BCE_EMAC_RX_STAT_ETHERSTATSFRAGMENTS 0x00001508 2347#define BCE_EMAC_RX_STAT_IFHCINUCASTPKTS 0x0000150c 2348#define BCE_EMAC_RX_STAT_IFHCINMULTICASTPKTS 0x00001510 2349#define BCE_EMAC_RX_STAT_IFHCINBROADCASTPKTS 0x00001514 2350#define BCE_EMAC_RX_STAT_DOT3STATSFCSERRORS 0x00001518 2351#define BCE_EMAC_RX_STAT_DOT3STATSALIGNMENTERRORS 0x0000151c 2352#define BCE_EMAC_RX_STAT_DOT3STATSCARRIERSENSEERRORS 0x00001520 2353#define BCE_EMAC_RX_STAT_XONPAUSEFRAMESRECEIVED 0x00001524 2354#define BCE_EMAC_RX_STAT_XOFFPAUSEFRAMESRECEIVED 0x00001528 2355#define BCE_EMAC_RX_STAT_MACCONTROLFRAMESRECEIVED 0x0000152c 2356#define BCE_EMAC_RX_STAT_XOFFSTATEENTERED 0x00001530 2357#define BCE_EMAC_RX_STAT_DOT3STATSFRAMESTOOLONG 0x00001534 2358#define BCE_EMAC_RX_STAT_ETHERSTATSJABBERS 0x00001538 2359#define BCE_EMAC_RX_STAT_ETHERSTATSUNDERSIZEPKTS 0x0000153c 2360#define BCE_EMAC_RX_STAT_ETHERSTATSPKTS64OCTETS 0x00001540 2361#define BCE_EMAC_RX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS 0x00001544 2362#define BCE_EMAC_RX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS 0x00001548 2363#define BCE_EMAC_RX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS 0x0000154c 2364#define BCE_EMAC_RX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS 0x00001550 2365#define BCE_EMAC_RX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS 0x00001554 2366#define BCE_EMAC_RX_STAT_ETHERSTATSPKTS1523OCTETSTO9022OCTETS 0x00001558 2367#define BCE_EMAC_RXMAC_DEBUG0 0x0000155c 2368#define BCE_EMAC_RXMAC_DEBUG1 0x00001560 2369#define BCE_EMAC_RXMAC_DEBUG1_LENGTH_NE_BYTE_COUNT (1L<<0) 2370#define BCE_EMAC_RXMAC_DEBUG1_LENGTH_OUT_RANGE (1L<<1) 2371#define BCE_EMAC_RXMAC_DEBUG1_BAD_CRC (1L<<2) 2372#define BCE_EMAC_RXMAC_DEBUG1_RX_ERROR (1L<<3) 2373#define BCE_EMAC_RXMAC_DEBUG1_ALIGN_ERROR (1L<<4) 2374#define BCE_EMAC_RXMAC_DEBUG1_LAST_DATA (1L<<5) 2375#define BCE_EMAC_RXMAC_DEBUG1_ODD_BYTE_START (1L<<6) 2376#define BCE_EMAC_RXMAC_DEBUG1_BYTE_COUNT (0xffffL<<7) 2377#define BCE_EMAC_RXMAC_DEBUG1_SLOT_TIME (0xffL<<23) 2378 2379#define BCE_EMAC_RXMAC_DEBUG2 0x00001564 2380#define BCE_EMAC_RXMAC_DEBUG2_SM_STATE (0x7L<<0) 2381#define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_IDLE (0x0L<<0) 2382#define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_SFD (0x1L<<0) 2383#define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_DATA (0x2L<<0) 2384#define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_SKEEP (0x3L<<0) 2385#define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_EXT (0x4L<<0) 2386#define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_DROP (0x5L<<0) 2387#define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_SDROP (0x6L<<0) 2388#define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_FC (0x7L<<0) 2389#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE (0xfL<<3) 2390#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_IDLE (0x0L<<3) 2391#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA0 (0x1L<<3) 2392#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA1 (0x2L<<3) 2393#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA2 (0x3L<<3) 2394#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA3 (0x4L<<3) 2395#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_ABORT (0x5L<<3) 2396#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_WAIT (0x6L<<3) 2397#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_STATUS (0x7L<<3) 2398#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_LAST (0x8L<<3) 2399#define BCE_EMAC_RXMAC_DEBUG2_BYTE_IN (0xffL<<7) 2400#define BCE_EMAC_RXMAC_DEBUG2_FALSEC (1L<<15) 2401#define BCE_EMAC_RXMAC_DEBUG2_TAGGED (1L<<16) 2402#define BCE_EMAC_RXMAC_DEBUG2_PAUSE_STATE (1L<<18) 2403#define BCE_EMAC_RXMAC_DEBUG2_PAUSE_STATE_IDLE (0L<<18) 2404#define BCE_EMAC_RXMAC_DEBUG2_PAUSE_STATE_PAUSED (1L<<18) 2405#define BCE_EMAC_RXMAC_DEBUG2_SE_COUNTER (0xfL<<19) 2406#define BCE_EMAC_RXMAC_DEBUG2_QUANTA (0x1fL<<23) 2407 2408#define BCE_EMAC_RXMAC_DEBUG3 0x00001568 2409#define BCE_EMAC_RXMAC_DEBUG3_PAUSE_CTR (0xffffL<<0) 2410#define BCE_EMAC_RXMAC_DEBUG3_TMP_PAUSE_CTR (0xffffL<<16) 2411 2412#define BCE_EMAC_RXMAC_DEBUG4 0x0000156c 2413#define BCE_EMAC_RXMAC_DEBUG4_TYPE_FIELD (0xffffL<<0) 2414#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE (0x3fL<<16) 2415#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_IDLE (0x0L<<16) 2416#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC2 (0x1L<<16) 2417#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC3 (0x2L<<16) 2418#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UNI (0x3L<<16) 2419#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC2 (0x7L<<16) 2420#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC3 (0x5L<<16) 2421#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA1 (0x6L<<16) 2422#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA2 (0x7L<<16) 2423#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA3 (0x8L<<16) 2424#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MC2 (0x9L<<16) 2425#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MC3 (0xaL<<16) 2426#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT1 (0xeL<<16) 2427#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT2 (0xfL<<16) 2428#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MCHECK (0x10L<<16) 2429#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MC (0x11L<<16) 2430#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BC2 (0x12L<<16) 2431#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BC3 (0x13L<<16) 2432#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA1 (0x14L<<16) 2433#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA2 (0x15L<<16) 2434#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA3 (0x16L<<16) 2435#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BTYPE (0x17L<<16) 2436#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BC (0x18L<<16) 2437#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_PTYPE (0x19L<<16) 2438#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_CMD (0x1aL<<16) 2439#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MAC (0x1bL<<16) 2440#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_LATCH (0x1cL<<16) 2441#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_XOFF (0x1dL<<16) 2442#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_XON (0x1eL<<16) 2443#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_PAUSED (0x1fL<<16) 2444#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_NPAUSED (0x20L<<16) 2445#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_TTYPE (0x21L<<16) 2446#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_TVAL (0x22L<<16) 2447#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_USA1 (0x23L<<16) 2448#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_USA2 (0x24L<<16) 2449#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_USA3 (0x25L<<16) 2450#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UTYPE (0x26L<<16) 2451#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UTTYPE (0x27L<<16) 2452#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UTVAL (0x28L<<16) 2453#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MTYPE (0x29L<<16) 2454#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_DROP (0x2aL<<16) 2455#define BCE_EMAC_RXMAC_DEBUG4_DROP_PKT (1L<<22) 2456#define BCE_EMAC_RXMAC_DEBUG4_SLOT_FILLED (1L<<23) 2457#define BCE_EMAC_RXMAC_DEBUG4_FALSE_CARRIER (1L<<24) 2458#define BCE_EMAC_RXMAC_DEBUG4_LAST_DATA (1L<<25) 2459#define BCE_EMAC_RXMAC_DEBUG4_sfd_FOUND (1L<<26) 2460#define BCE_EMAC_RXMAC_DEBUG4_ADVANCE (1L<<27) 2461#define BCE_EMAC_RXMAC_DEBUG4_START (1L<<28) 2462 2463#define BCE_EMAC_RXMAC_DEBUG5 0x00001570 2464#define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM (0x7L<<0) 2465#define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_IDLE (0L<<0) 2466#define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_EOF (1L<<0) 2467#define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_STAT (2L<<0) 2468#define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4FCRC (3L<<0) 2469#define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4RDE (4L<<0) 2470#define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4ALL (5L<<0) 2471#define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_1WD_WAIT_STAT (6L<<0) 2472#define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1 (0x7L<<4) 2473#define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_VDW (0x0L<<4) 2474#define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_STAT (0x1L<<4) 2475#define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_AEOF (0x2L<<4) 2476#define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_NEOF (0x3L<<4) 2477#define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SOF (0x4L<<4) 2478#define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SAEOF (0x6L<<4) 2479#define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SNEOF (0x7L<<4) 2480#define BCE_EMAC_RXMAC_DEBUG5_EOF_DETECTED (1L<<7) 2481#define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF0 (0x7L<<8) 2482#define BCE_EMAC_RXMAC_DEBUG5_RPM_IDI_FIFO_FULL (1L<<11) 2483#define BCE_EMAC_RXMAC_DEBUG5_LOAD_CCODE (1L<<12) 2484#define BCE_EMAC_RXMAC_DEBUG5_LOAD_DATA (1L<<13) 2485#define BCE_EMAC_RXMAC_DEBUG5_LOAD_STAT (1L<<14) 2486#define BCE_EMAC_RXMAC_DEBUG5_CLR_STAT (1L<<15) 2487#define BCE_EMAC_RXMAC_DEBUG5_IDI_RPM_CCODE (0x3L<<16) 2488#define BCE_EMAC_RXMAC_DEBUG5_IDI_RPM_ACCEPT (1L<<19) 2489#define BCE_EMAC_RXMAC_DEBUG5_FMLEN (0xfffL<<20) 2490 2491#define BCE_EMAC_RX_STAT_AC0 0x00001580 2492#define BCE_EMAC_RX_STAT_AC1 0x00001584 2493#define BCE_EMAC_RX_STAT_AC2 0x00001588 2494#define BCE_EMAC_RX_STAT_AC3 0x0000158c 2495#define BCE_EMAC_RX_STAT_AC4 0x00001590 2496#define BCE_EMAC_RX_STAT_AC5 0x00001594 2497#define BCE_EMAC_RX_STAT_AC6 0x00001598 2498#define BCE_EMAC_RX_STAT_AC7 0x0000159c 2499#define BCE_EMAC_RX_STAT_AC8 0x000015a0 2500#define BCE_EMAC_RX_STAT_AC9 0x000015a4 2501#define BCE_EMAC_RX_STAT_AC10 0x000015a8 2502#define BCE_EMAC_RX_STAT_AC11 0x000015ac 2503#define BCE_EMAC_RX_STAT_AC12 0x000015b0 2504#define BCE_EMAC_RX_STAT_AC13 0x000015b4 2505#define BCE_EMAC_RX_STAT_AC14 0x000015b8 2506#define BCE_EMAC_RX_STAT_AC15 0x000015bc 2507#define BCE_EMAC_RX_STAT_AC16 0x000015c0 2508#define BCE_EMAC_RX_STAT_AC17 0x000015c4 2509#define BCE_EMAC_RX_STAT_AC18 0x000015c8 2510#define BCE_EMAC_RX_STAT_AC19 0x000015cc 2511#define BCE_EMAC_RX_STAT_AC20 0x000015d0 2512#define BCE_EMAC_RX_STAT_AC21 0x000015d4 2513#define BCE_EMAC_RX_STAT_AC22 0x000015d8 2514#define BCE_EMAC_RXMAC_SUC_DBG_OVERRUNVEC 0x000015dc 2515#define BCE_EMAC_TX_STAT_IFHCOUTOCTETS 0x00001600 2516#define BCE_EMAC_TX_STAT_IFHCOUTBADOCTETS 0x00001604 2517#define BCE_EMAC_TX_STAT_ETHERSTATSCOLLISIONS 0x00001608 2518#define BCE_EMAC_TX_STAT_OUTXONSENT 0x0000160c 2519#define BCE_EMAC_TX_STAT_OUTXOFFSENT 0x00001610 2520#define BCE_EMAC_TX_STAT_FLOWCONTROLDONE 0x00001614 2521#define BCE_EMAC_TX_STAT_DOT3STATSSINGLECOLLISIONFRAMES 0x00001618 2522#define BCE_EMAC_TX_STAT_DOT3STATSMULTIPLECOLLISIONFRAMES 0x0000161c 2523#define BCE_EMAC_TX_STAT_DOT3STATSDEFERREDTRANSMISSIONS 0x00001620 2524#define BCE_EMAC_TX_STAT_DOT3STATSEXCESSIVECOLLISIONS 0x00001624 2525#define BCE_EMAC_TX_STAT_DOT3STATSLATECOLLISIONS 0x00001628 2526#define BCE_EMAC_TX_STAT_IFHCOUTUCASTPKTS 0x0000162c 2527#define BCE_EMAC_TX_STAT_IFHCOUTMULTICASTPKTS 0x00001630 2528#define BCE_EMAC_TX_STAT_IFHCOUTBROADCASTPKTS 0x00001634 2529#define BCE_EMAC_TX_STAT_ETHERSTATSPKTS64OCTETS 0x00001638 2530#define BCE_EMAC_TX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS 0x0000163c 2531#define BCE_EMAC_TX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS 0x00001640 2532#define BCE_EMAC_TX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS 0x00001644 2533#define BCE_EMAC_TX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS 0x00001648 2534#define BCE_EMAC_TX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS 0x0000164c 2535#define BCE_EMAC_TX_STAT_ETHERSTATSPKTS1523OCTETSTO9022OCTETS 0x00001650 2536#define BCE_EMAC_TX_STAT_DOT3STATSINTERNALMACTRANSMITERRORS 0x00001654 2537#define BCE_EMAC_TXMAC_DEBUG0 0x00001658 2538#define BCE_EMAC_TXMAC_DEBUG1 0x0000165c 2539#define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE (0xfL<<0) 2540#define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_IDLE (0x0L<<0) 2541#define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_START0 (0x1L<<0) 2542#define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA0 (0x4L<<0) 2543#define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA1 (0x5L<<0) 2544#define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA2 (0x6L<<0) 2545#define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA3 (0x7L<<0) 2546#define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT0 (0x8L<<0) 2547#define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT1 (0x9L<<0) 2548#define BCE_EMAC_TXMAC_DEBUG1_CRS_ENABLE (1L<<4) 2549#define BCE_EMAC_TXMAC_DEBUG1_BAD_CRC (1L<<5) 2550#define BCE_EMAC_TXMAC_DEBUG1_SE_COUNTER (0xfL<<6) 2551#define BCE_EMAC_TXMAC_DEBUG1_SEND_PAUSE (1L<<10) 2552#define BCE_EMAC_TXMAC_DEBUG1_LATE_COLLISION (1L<<11) 2553#define BCE_EMAC_TXMAC_DEBUG1_MAX_DEFER (1L<<12) 2554#define BCE_EMAC_TXMAC_DEBUG1_DEFERRED (1L<<13) 2555#define BCE_EMAC_TXMAC_DEBUG1_ONE_BYTE (1L<<14) 2556#define BCE_EMAC_TXMAC_DEBUG1_IPG_TIME (0xfL<<15) 2557#define BCE_EMAC_TXMAC_DEBUG1_SLOT_TIME (0xffL<<19) 2558 2559#define BCE_EMAC_TXMAC_DEBUG2 0x00001660 2560#define BCE_EMAC_TXMAC_DEBUG2_BACK_OFF (0x3ffL<<0) 2561#define BCE_EMAC_TXMAC_DEBUG2_BYTE_COUNT (0xffffL<<10) 2562#define BCE_EMAC_TXMAC_DEBUG2_COL_COUNT (0x1fL<<26) 2563#define BCE_EMAC_TXMAC_DEBUG2_COL_BIT (1L<<31) 2564 2565#define BCE_EMAC_TXMAC_DEBUG3 0x00001664 2566#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE (0xfL<<0) 2567#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_IDLE (0x0L<<0) 2568#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_PRE1 (0x1L<<0) 2569#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_PRE2 (0x2L<<0) 2570#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_SFD (0x3L<<0) 2571#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_DATA (0x4L<<0) 2572#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_CRC1 (0x5L<<0) 2573#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_CRC2 (0x6L<<0) 2574#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_EXT (0x7L<<0) 2575#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_STATB (0x8L<<0) 2576#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_STATG (0x9L<<0) 2577#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_JAM (0xaL<<0) 2578#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_EJAM (0xbL<<0) 2579#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_BJAM (0xcL<<0) 2580#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_SWAIT (0xdL<<0) 2581#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_BACKOFF (0xeL<<0) 2582#define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE (0x7L<<4) 2583#define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_IDLE (0x0L<<4) 2584#define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_WAIT (0x1L<<4) 2585#define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_UNI (0x2L<<4) 2586#define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_MC (0x3L<<4) 2587#define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_BC2 (0x4L<<4) 2588#define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_BC3 (0x5L<<4) 2589#define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_BC (0x6L<<4) 2590#define BCE_EMAC_TXMAC_DEBUG3_CRS_DONE (1L<<7) 2591#define BCE_EMAC_TXMAC_DEBUG3_XOFF (1L<<8) 2592#define BCE_EMAC_TXMAC_DEBUG3_SE_COUNTER (0xfL<<9) 2593#define BCE_EMAC_TXMAC_DEBUG3_QUANTA_COUNTER (0x1fL<<13) 2594 2595#define BCE_EMAC_TXMAC_DEBUG4 0x00001668 2596#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_COUNTER (0xffffL<<0) 2597#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE (0xfL<<16) 2598#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_IDLE (0x0L<<16) 2599#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA1 (0x2L<<16) 2600#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA2 (0x3L<<16) 2601#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA3 (0x6L<<16) 2602#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC1 (0x7L<<16) 2603#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC2 (0x5L<<16) 2604#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC3 (0x4L<<16) 2605#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TYPE (0xcL<<16) 2606#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CMD (0xeL<<16) 2607#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TIME (0xaL<<16) 2608#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC1 (0x8L<<16) 2609#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC2 (0x9L<<16) 2610#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_WAIT (0xdL<<16) 2611#define BCE_EMAC_TXMAC_DEBUG4_STATS0_VALID (1L<<20) 2612#define BCE_EMAC_TXMAC_DEBUG4_APPEND_CRC (1L<<21) 2613#define BCE_EMAC_TXMAC_DEBUG4_SLOT_FILLED (1L<<22) 2614#define BCE_EMAC_TXMAC_DEBUG4_MAX_DEFER (1L<<23) 2615#define BCE_EMAC_TXMAC_DEBUG4_SEND_EXTEND (1L<<24) 2616#define BCE_EMAC_TXMAC_DEBUG4_SEND_PADDING (1L<<25) 2617#define BCE_EMAC_TXMAC_DEBUG4_EOF_LOC (1L<<26) 2618#define BCE_EMAC_TXMAC_DEBUG4_COLLIDING (1L<<27) 2619#define BCE_EMAC_TXMAC_DEBUG4_COL_IN (1L<<28) 2620#define BCE_EMAC_TXMAC_DEBUG4_BURSTING (1L<<29) 2621#define BCE_EMAC_TXMAC_DEBUG4_ADVANCE (1L<<30) 2622#define BCE_EMAC_TXMAC_DEBUG4_GO (1L<<31) 2623 2624#define BCE_EMAC_TX_STAT_AC0 0x00001680 2625#define BCE_EMAC_TX_STAT_AC1 0x00001684 2626#define BCE_EMAC_TX_STAT_AC2 0x00001688 2627#define BCE_EMAC_TX_STAT_AC3 0x0000168c 2628#define BCE_EMAC_TX_STAT_AC4 0x00001690 2629#define BCE_EMAC_TX_STAT_AC5 0x00001694 2630#define BCE_EMAC_TX_STAT_AC6 0x00001698 2631#define BCE_EMAC_TX_STAT_AC7 0x0000169c 2632#define BCE_EMAC_TX_STAT_AC8 0x000016a0 2633#define BCE_EMAC_TX_STAT_AC9 0x000016a4 2634#define BCE_EMAC_TX_STAT_AC10 0x000016a8 2635#define BCE_EMAC_TX_STAT_AC11 0x000016ac 2636#define BCE_EMAC_TX_STAT_AC12 0x000016b0 2637#define BCE_EMAC_TX_STAT_AC13 0x000016b4 2638#define BCE_EMAC_TX_STAT_AC14 0x000016b8 2639#define BCE_EMAC_TX_STAT_AC15 0x000016bc 2640#define BCE_EMAC_TX_STAT_AC16 0x000016c0 2641#define BCE_EMAC_TX_STAT_AC17 0x000016c4 2642#define BCE_EMAC_TX_STAT_AC18 0x000016c8 2643#define BCE_EMAC_TX_STAT_AC19 0x000016cc 2644#define BCE_EMAC_TX_STAT_AC20 0x000016d0 2645#define BCE_EMAC_TX_STAT_AC21 0x000016d4 2646#define BCE_EMAC_TXMAC_SUC_DBG_OVERRUNVEC 0x000016d8 2647 2648 2649/* 2650 * rpm_reg definition 2651 * offset: 0x1800 2652 */ 2653#define BCE_RPM_COMMAND 0x00001800 2654#define BCE_RPM_COMMAND_ENABLED (1L<<0) 2655#define BCE_RPM_COMMAND_OVERRUN_ABORT (1L<<4) 2656 2657#define BCE_RPM_STATUS 0x00001804 2658#define BCE_RPM_STATUS_MBUF_WAIT (1L<<0) 2659#define BCE_RPM_STATUS_FREE_WAIT (1L<<1) 2660 2661#define BCE_RPM_CONFIG 0x00001808 2662#define BCE_RPM_CONFIG_NO_PSD_HDR_CKSUM (1L<<0) 2663#define BCE_RPM_CONFIG_ACPI_ENA (1L<<1) 2664#define BCE_RPM_CONFIG_ACPI_KEEP (1L<<2) 2665#define BCE_RPM_CONFIG_MP_KEEP (1L<<3) 2666#define BCE_RPM_CONFIG_SORT_VECT_VAL (0xfL<<4) 2667#define BCE_RPM_CONFIG_IGNORE_VLAN (1L<<31) 2668 2669#define BCE_RPM_VLAN_MATCH0 0x00001810 2670#define BCE_RPM_VLAN_MATCH0_RPM_VLAN_MTCH0_VALUE (0xfffL<<0) 2671 2672#define BCE_RPM_VLAN_MATCH1 0x00001814 2673#define BCE_RPM_VLAN_MATCH1_RPM_VLAN_MTCH1_VALUE (0xfffL<<0) 2674 2675#define BCE_RPM_VLAN_MATCH2 0x00001818 2676#define BCE_RPM_VLAN_MATCH2_RPM_VLAN_MTCH2_VALUE (0xfffL<<0) 2677 2678#define BCE_RPM_VLAN_MATCH3 0x0000181c 2679#define BCE_RPM_VLAN_MATCH3_RPM_VLAN_MTCH3_VALUE (0xfffL<<0) 2680 2681#define BCE_RPM_SORT_USER0 0x00001820 2682#define BCE_RPM_SORT_USER0_PM_EN (0xffffL<<0) 2683#define BCE_RPM_SORT_USER0_BC_EN (1L<<16) 2684#define BCE_RPM_SORT_USER0_MC_EN (1L<<17) 2685#define BCE_RPM_SORT_USER0_MC_HSH_EN (1L<<18) 2686#define BCE_RPM_SORT_USER0_PROM_EN (1L<<19) 2687#define BCE_RPM_SORT_USER0_VLAN_EN (0xfL<<20) 2688#define BCE_RPM_SORT_USER0_PROM_VLAN (1L<<24) 2689#define BCE_RPM_SORT_USER0_ENA (1L<<31) 2690 2691#define BCE_RPM_SORT_USER1 0x00001824 2692#define BCE_RPM_SORT_USER1_PM_EN (0xffffL<<0) 2693#define BCE_RPM_SORT_USER1_BC_EN (1L<<16) 2694#define BCE_RPM_SORT_USER1_MC_EN (1L<<17) 2695#define BCE_RPM_SORT_USER1_MC_HSH_EN (1L<<18) 2696#define BCE_RPM_SORT_USER1_PROM_EN (1L<<19) 2697#define BCE_RPM_SORT_USER1_VLAN_EN (0xfL<<20) 2698#define BCE_RPM_SORT_USER1_PROM_VLAN (1L<<24) 2699#define BCE_RPM_SORT_USER1_ENA (1L<<31) 2700 2701#define BCE_RPM_SORT_USER2 0x00001828 2702#define BCE_RPM_SORT_USER2_PM_EN (0xffffL<<0) 2703#define BCE_RPM_SORT_USER2_BC_EN (1L<<16) 2704#define BCE_RPM_SORT_USER2_MC_EN (1L<<17) 2705#define BCE_RPM_SORT_USER2_MC_HSH_EN (1L<<18) 2706#define BCE_RPM_SORT_USER2_PROM_EN (1L<<19) 2707#define BCE_RPM_SORT_USER2_VLAN_EN (0xfL<<20) 2708#define BCE_RPM_SORT_USER2_PROM_VLAN (1L<<24) 2709#define BCE_RPM_SORT_USER2_ENA (1L<<31) 2710 2711#define BCE_RPM_SORT_USER3 0x0000182c 2712#define BCE_RPM_SORT_USER3_PM_EN (0xffffL<<0) 2713#define BCE_RPM_SORT_USER3_BC_EN (1L<<16) 2714#define BCE_RPM_SORT_USER3_MC_EN (1L<<17) 2715#define BCE_RPM_SORT_USER3_MC_HSH_EN (1L<<18) 2716#define BCE_RPM_SORT_USER3_PROM_EN (1L<<19) 2717#define BCE_RPM_SORT_USER3_VLAN_EN (0xfL<<20) 2718#define BCE_RPM_SORT_USER3_PROM_VLAN (1L<<24) 2719#define BCE_RPM_SORT_USER3_ENA (1L<<31) 2720 2721#define BCE_RPM_STAT_L2_FILTER_DISCARDS 0x00001840 2722#define BCE_RPM_STAT_RULE_CHECKER_DISCARDS 0x00001844 2723#define BCE_RPM_STAT_IFINFTQDISCARDS 0x00001848 2724#define BCE_RPM_STAT_IFINMBUFDISCARD 0x0000184c 2725#define BCE_RPM_STAT_RULE_CHECKER_P4_HIT 0x00001850 2726#define BCE_RPM_STAT_AC0 0x00001880 2727#define BCE_RPM_STAT_AC1 0x00001884 2728#define BCE_RPM_STAT_AC2 0x00001888 2729#define BCE_RPM_STAT_AC3 0x0000188c 2730#define BCE_RPM_STAT_AC4 0x00001890 2731#define BCE_RPM_RC_CNTL_0 0x00001900 2732#define BCE_RPM_RC_CNTL_0_OFFSET (0xffL<<0) 2733#define BCE_RPM_RC_CNTL_0_CLASS (0x7L<<8) 2734#define BCE_RPM_RC_CNTL_0_PRIORITY (1L<<11) 2735#define BCE_RPM_RC_CNTL_0_P4 (1L<<12) 2736#define BCE_RPM_RC_CNTL_0_HDR_TYPE (0x7L<<13) 2737#define BCE_RPM_RC_CNTL_0_HDR_TYPE_START (0L<<13) 2738#define BCE_RPM_RC_CNTL_0_HDR_TYPE_IP (1L<<13) 2739#define BCE_RPM_RC_CNTL_0_HDR_TYPE_TCP (2L<<13) 2740#define BCE_RPM_RC_CNTL_0_HDR_TYPE_UDP (3L<<13) 2741#define BCE_RPM_RC_CNTL_0_HDR_TYPE_DATA (4L<<13) 2742#define BCE_RPM_RC_CNTL_0_COMP (0x3L<<16) 2743#define BCE_RPM_RC_CNTL_0_COMP_EQUAL (0L<<16) 2744#define BCE_RPM_RC_CNTL_0_COMP_NEQUAL (1L<<16) 2745#define BCE_RPM_RC_CNTL_0_COMP_GREATER (2L<<16) 2746#define BCE_RPM_RC_CNTL_0_COMP_LESS (3L<<16) 2747#define BCE_RPM_RC_CNTL_0_SBIT (1L<<19) 2748#define BCE_RPM_RC_CNTL_0_CMDSEL (0xfL<<20) 2749#define BCE_RPM_RC_CNTL_0_MAP (1L<<24) 2750#define BCE_RPM_RC_CNTL_0_DISCARD (1L<<25) 2751#define BCE_RPM_RC_CNTL_0_MASK (1L<<26) 2752#define BCE_RPM_RC_CNTL_0_P1 (1L<<27) 2753#define BCE_RPM_RC_CNTL_0_P2 (1L<<28) 2754#define BCE_RPM_RC_CNTL_0_P3 (1L<<29) 2755#define BCE_RPM_RC_CNTL_0_NBIT (1L<<30) 2756 2757#define BCE_RPM_RC_VALUE_MASK_0 0x00001904 2758#define BCE_RPM_RC_VALUE_MASK_0_VALUE (0xffffL<<0) 2759#define BCE_RPM_RC_VALUE_MASK_0_MASK (0xffffL<<16) 2760 2761#define BCE_RPM_RC_CNTL_1 0x00001908 2762#define BCE_RPM_RC_CNTL_1_A (0x3ffffL<<0) 2763#define BCE_RPM_RC_CNTL_1_B (0xfffL<<19) 2764 2765#define BCE_RPM_RC_VALUE_MASK_1 0x0000190c 2766#define BCE_RPM_RC_CNTL_2 0x00001910 2767#define BCE_RPM_RC_CNTL_2_A (0x3ffffL<<0) 2768#define BCE_RPM_RC_CNTL_2_B (0xfffL<<19) 2769 2770#define BCE_RPM_RC_VALUE_MASK_2 0x00001914 2771#define BCE_RPM_RC_CNTL_3 0x00001918 2772#define BCE_RPM_RC_CNTL_3_A (0x3ffffL<<0) 2773#define BCE_RPM_RC_CNTL_3_B (0xfffL<<19) 2774 2775#define BCE_RPM_RC_VALUE_MASK_3 0x0000191c 2776#define BCE_RPM_RC_CNTL_4 0x00001920 2777#define BCE_RPM_RC_CNTL_4_A (0x3ffffL<<0) 2778#define BCE_RPM_RC_CNTL_4_B (0xfffL<<19) 2779 2780#define BCE_RPM_RC_VALUE_MASK_4 0x00001924 2781#define BCE_RPM_RC_CNTL_5 0x00001928 2782#define BCE_RPM_RC_CNTL_5_A (0x3ffffL<<0) 2783#define BCE_RPM_RC_CNTL_5_B (0xfffL<<19) 2784 2785#define BCE_RPM_RC_VALUE_MASK_5 0x0000192c 2786#define BCE_RPM_RC_CNTL_6 0x00001930 2787#define BCE_RPM_RC_CNTL_6_A (0x3ffffL<<0) 2788#define BCE_RPM_RC_CNTL_6_B (0xfffL<<19) 2789 2790#define BCE_RPM_RC_VALUE_MASK_6 0x00001934 2791#define BCE_RPM_RC_CNTL_7 0x00001938 2792#define BCE_RPM_RC_CNTL_7_A (0x3ffffL<<0) 2793#define BCE_RPM_RC_CNTL_7_B (0xfffL<<19) 2794 2795#define BCE_RPM_RC_VALUE_MASK_7 0x0000193c 2796#define BCE_RPM_RC_CNTL_8 0x00001940 2797#define BCE_RPM_RC_CNTL_8_A (0x3ffffL<<0) 2798#define BCE_RPM_RC_CNTL_8_B (0xfffL<<19) 2799 2800#define BCE_RPM_RC_VALUE_MASK_8 0x00001944 2801#define BCE_RPM_RC_CNTL_9 0x00001948 2802#define BCE_RPM_RC_CNTL_9_A (0x3ffffL<<0) 2803#define BCE_RPM_RC_CNTL_9_B (0xfffL<<19) 2804 2805#define BCE_RPM_RC_VALUE_MASK_9 0x0000194c 2806#define BCE_RPM_RC_CNTL_10 0x00001950 2807#define BCE_RPM_RC_CNTL_10_A (0x3ffffL<<0) 2808#define BCE_RPM_RC_CNTL_10_B (0xfffL<<19) 2809 2810#define BCE_RPM_RC_VALUE_MASK_10 0x00001954 2811#define BCE_RPM_RC_CNTL_11 0x00001958 2812#define BCE_RPM_RC_CNTL_11_A (0x3ffffL<<0) 2813#define BCE_RPM_RC_CNTL_11_B (0xfffL<<19) 2814 2815#define BCE_RPM_RC_VALUE_MASK_11 0x0000195c 2816#define BCE_RPM_RC_CNTL_12 0x00001960 2817#define BCE_RPM_RC_CNTL_12_A (0x3ffffL<<0) 2818#define BCE_RPM_RC_CNTL_12_B (0xfffL<<19) 2819 2820#define BCE_RPM_RC_VALUE_MASK_12 0x00001964 2821#define BCE_RPM_RC_CNTL_13 0x00001968 2822#define BCE_RPM_RC_CNTL_13_A (0x3ffffL<<0) 2823#define BCE_RPM_RC_CNTL_13_B (0xfffL<<19) 2824 2825#define BCE_RPM_RC_VALUE_MASK_13 0x0000196c 2826#define BCE_RPM_RC_CNTL_14 0x00001970 2827#define BCE_RPM_RC_CNTL_14_A (0x3ffffL<<0) 2828#define BCE_RPM_RC_CNTL_14_B (0xfffL<<19) 2829 2830#define BCE_RPM_RC_VALUE_MASK_14 0x00001974 2831#define BCE_RPM_RC_CNTL_15 0x00001978 2832#define BCE_RPM_RC_CNTL_15_A (0x3ffffL<<0) 2833#define BCE_RPM_RC_CNTL_15_B (0xfffL<<19) 2834 2835#define BCE_RPM_RC_VALUE_MASK_15 0x0000197c 2836#define BCE_RPM_RC_CONFIG 0x00001980 2837#define BCE_RPM_RC_CONFIG_RULE_ENABLE (0xffffL<<0) 2838#define BCE_RPM_RC_CONFIG_DEF_CLASS (0x7L<<24) 2839 2840#define BCE_RPM_DEBUG0 0x00001984 2841#define BCE_RPM_DEBUG0_FM_BCNT (0xffffL<<0) 2842#define BCE_RPM_DEBUG0_T_DATA_OFST_VLD (1L<<16) 2843#define BCE_RPM_DEBUG0_T_UDP_OFST_VLD (1L<<17) 2844#define BCE_RPM_DEBUG0_T_TCP_OFST_VLD (1L<<18) 2845#define BCE_RPM_DEBUG0_T_IP_OFST_VLD (1L<<19) 2846#define BCE_RPM_DEBUG0_IP_MORE_FRGMT (1L<<20) 2847#define BCE_RPM_DEBUG0_T_IP_NO_TCP_UDP_HDR (1L<<21) 2848#define BCE_RPM_DEBUG0_LLC_SNAP (1L<<22) 2849#define BCE_RPM_DEBUG0_FM_STARTED (1L<<23) 2850#define BCE_RPM_DEBUG0_DONE (1L<<24) 2851#define BCE_RPM_DEBUG0_WAIT_4_DONE (1L<<25) 2852#define BCE_RPM_DEBUG0_USE_TPBUF_CKSUM (1L<<26) 2853#define BCE_RPM_DEBUG0_RX_NO_PSD_HDR_CKSUM (1L<<27) 2854#define BCE_RPM_DEBUG0_IGNORE_VLAN (1L<<28) 2855#define BCE_RPM_DEBUG0_RP_ENA_ACTIVE (1L<<31) 2856 2857#define BCE_RPM_DEBUG1 0x00001988 2858#define BCE_RPM_DEBUG1_FSM_CUR_ST (0xffffL<<0) 2859#define BCE_RPM_DEBUG1_FSM_CUR_ST_IDLE (0L<<0) 2860#define BCE_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_ALL (1L<<0) 2861#define BCE_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IPLLC (2L<<0) 2862#define BCE_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_IP (4L<<0) 2863#define BCE_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IP (8L<<0) 2864#define BCE_RPM_DEBUG1_FSM_CUR_ST_IP_START (16L<<0) 2865#define BCE_RPM_DEBUG1_FSM_CUR_ST_IP (32L<<0) 2866#define BCE_RPM_DEBUG1_FSM_CUR_ST_TCP (64L<<0) 2867#define BCE_RPM_DEBUG1_FSM_CUR_ST_UDP (128L<<0) 2868#define BCE_RPM_DEBUG1_FSM_CUR_ST_AH (256L<<0) 2869#define BCE_RPM_DEBUG1_FSM_CUR_ST_ESP (512L<<0) 2870#define BCE_RPM_DEBUG1_FSM_CUR_ST_ESP_PAYLOAD (1024L<<0) 2871#define BCE_RPM_DEBUG1_FSM_CUR_ST_DATA (2048L<<0) 2872#define BCE_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRY (0x2000L<<0) 2873#define BCE_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRYOUT (0x4000L<<0) 2874#define BCE_RPM_DEBUG1_FSM_CUR_ST_LATCH_RESULT (0x8000L<<0) 2875#define BCE_RPM_DEBUG1_HDR_BCNT (0x7ffL<<16) 2876#define BCE_RPM_DEBUG1_UNKNOWN_ETYPE_D (1L<<28) 2877#define BCE_RPM_DEBUG1_VLAN_REMOVED_D2 (1L<<29) 2878#define BCE_RPM_DEBUG1_VLAN_REMOVED_D1 (1L<<30) 2879#define BCE_RPM_DEBUG1_EOF_0XTRA_WD (1L<<31) 2880 2881#define BCE_RPM_DEBUG2 0x0000198c 2882#define BCE_RPM_DEBUG2_CMD_HIT_VEC (0xffffL<<0) 2883#define BCE_RPM_DEBUG2_IP_BCNT (0xffL<<16) 2884#define BCE_RPM_DEBUG2_THIS_CMD_M4 (1L<<24) 2885#define BCE_RPM_DEBUG2_THIS_CMD_M3 (1L<<25) 2886#define BCE_RPM_DEBUG2_THIS_CMD_M2 (1L<<26) 2887#define BCE_RPM_DEBUG2_THIS_CMD_M1 (1L<<27) 2888#define BCE_RPM_DEBUG2_IPIPE_EMPTY (1L<<28) 2889#define BCE_RPM_DEBUG2_FM_DISCARD (1L<<29) 2890#define BCE_RPM_DEBUG2_LAST_RULE_IN_FM_D2 (1L<<30) 2891#define BCE_RPM_DEBUG2_LAST_RULE_IN_FM_D1 (1L<<31) 2892 2893#define BCE_RPM_DEBUG3 0x00001990 2894#define BCE_RPM_DEBUG3_AVAIL_MBUF_PTR (0x1ffL<<0) 2895#define BCE_RPM_DEBUG3_RDE_RLUPQ_WR_REQ_INT (1L<<9) 2896#define BCE_RPM_DEBUG3_RDE_RBUF_WR_LAST_INT (1L<<10) 2897#define BCE_RPM_DEBUG3_RDE_RBUF_WR_REQ_INT (1L<<11) 2898#define BCE_RPM_DEBUG3_RDE_RBUF_FREE_REQ (1L<<12) 2899#define BCE_RPM_DEBUG3_RDE_RBUF_ALLOC_REQ (1L<<13) 2900#define BCE_RPM_DEBUG3_DFSM_MBUF_NOTAVAIL (1L<<14) 2901#define BCE_RPM_DEBUG3_RBUF_RDE_SOF_DROP (1L<<15) 2902#define BCE_RPM_DEBUG3_DFIFO_VLD_ENTRY_CT (0xfL<<16) 2903#define BCE_RPM_DEBUG3_RDE_SRC_FIFO_ALMFULL (1L<<21) 2904#define BCE_RPM_DEBUG3_DROP_NXT_VLD (1L<<22) 2905#define BCE_RPM_DEBUG3_DROP_NXT (1L<<23) 2906#define BCE_RPM_DEBUG3_FTQ_FSM (0x3L<<24) 2907#define BCE_RPM_DEBUG3_FTQ_FSM_IDLE (0x0L<<24) 2908#define BCE_RPM_DEBUG3_FTQ_FSM_WAIT_ACK (0x1L<<24) 2909#define BCE_RPM_DEBUG3_FTQ_FSM_WAIT_FREE (0x2L<<24) 2910#define BCE_RPM_DEBUG3_MBWRITE_FSM (0x3L<<26) 2911#define BCE_RPM_DEBUG3_MBWRITE_FSM_WAIT_SOF (0x0L<<26) 2912#define BCE_RPM_DEBUG3_MBWRITE_FSM_GET_MBUF (0x1L<<26) 2913#define BCE_RPM_DEBUG3_MBWRITE_FSM_DMA_DATA (0x2L<<26) 2914#define BCE_RPM_DEBUG3_MBWRITE_FSM_WAIT_DATA (0x3L<<26) 2915#define BCE_RPM_DEBUG3_MBWRITE_FSM_WAIT_EOF (0x4L<<26) 2916#define BCE_RPM_DEBUG3_MBWRITE_FSM_WAIT_MF_ACK (0x5L<<26) 2917#define BCE_RPM_DEBUG3_MBWRITE_FSM_WAIT_DROP_NXT_VLD (0x6L<<26) 2918#define BCE_RPM_DEBUG3_MBWRITE_FSM_DONE (0x7L<<26) 2919#define BCE_RPM_DEBUG3_MBFREE_FSM (1L<<29) 2920#define BCE_RPM_DEBUG3_MBFREE_FSM_IDLE (0L<<29) 2921#define BCE_RPM_DEBUG3_MBFREE_FSM_WAIT_ACK (1L<<29) 2922#define BCE_RPM_DEBUG3_MBALLOC_FSM (1L<<30) 2923#define BCE_RPM_DEBUG3_MBALLOC_FSM_ET_MBUF (0x0L<<30) 2924#define BCE_RPM_DEBUG3_MBALLOC_FSM_IVE_MBUF (0x1L<<30) 2925#define BCE_RPM_DEBUG3_CCODE_EOF_ERROR (1L<<31) 2926 2927#define BCE_RPM_DEBUG4 0x00001994 2928#define BCE_RPM_DEBUG4_DFSM_MBUF_CLUSTER (0x1ffffffL<<0) 2929#define BCE_RPM_DEBUG4_DFIFO_CUR_CCODE (0x7L<<25) 2930#define BCE_RPM_DEBUG4_MBWRITE_FSM (0x7L<<28) 2931#define BCE_RPM_DEBUG4_DFIFO_EMPTY (1L<<31) 2932 2933#define BCE_RPM_DEBUG5 0x00001998 2934#define BCE_RPM_DEBUG5_RDROP_WPTR (0x1fL<<0) 2935#define BCE_RPM_DEBUG5_RDROP_ACPI_RPTR (0x1fL<<5) 2936#define BCE_RPM_DEBUG5_RDROP_MC_RPTR (0x1fL<<10) 2937#define BCE_RPM_DEBUG5_RDROP_RC_RPTR (0x1fL<<15) 2938#define BCE_RPM_DEBUG5_RDROP_ACPI_EMPTY (1L<<20) 2939#define BCE_RPM_DEBUG5_RDROP_MC_EMPTY (1L<<21) 2940#define BCE_RPM_DEBUG5_RDROP_AEOF_VEC_AT_RDROP_MC_RPTR (1L<<22) 2941#define BCE_RPM_DEBUG5_HOLDREG_WOL_DROP_INT (1L<<23) 2942#define BCE_RPM_DEBUG5_HOLDREG_DISCARD (1L<<24) 2943#define BCE_RPM_DEBUG5_HOLDREG_MBUF_NOTAVAIL (1L<<25) 2944#define BCE_RPM_DEBUG5_HOLDREG_MC_EMPTY (1L<<26) 2945#define BCE_RPM_DEBUG5_HOLDREG_RC_EMPTY (1L<<27) 2946#define BCE_RPM_DEBUG5_HOLDREG_FC_EMPTY (1L<<28) 2947#define BCE_RPM_DEBUG5_HOLDREG_ACPI_EMPTY (1L<<29) 2948#define BCE_RPM_DEBUG5_HOLDREG_FULL_T (1L<<30) 2949#define BCE_RPM_DEBUG5_HOLDREG_RD (1L<<31) 2950 2951#define BCE_RPM_DEBUG6 0x0000199c 2952#define BCE_RPM_DEBUG6_ACPI_VEC (0xffffL<<0) 2953#define BCE_RPM_DEBUG6_VEC (0xffffL<<16) 2954 2955#define BCE_RPM_DEBUG7 0x000019a0 2956#define BCE_RPM_DEBUG7_RPM_DBG7_LAST_CRC (0xffffffffL<<0) 2957 2958#define BCE_RPM_DEBUG8 0x000019a4 2959#define BCE_RPM_DEBUG8_PS_ACPI_FSM (0xfL<<0) 2960#define BCE_RPM_DEBUG8_PS_ACPI_FSM_IDLE (0L<<0) 2961#define BCE_RPM_DEBUG8_PS_ACPI_FSM_SOF_W1_ADDR (1L<<0) 2962#define BCE_RPM_DEBUG8_PS_ACPI_FSM_SOF_W2_ADDR (2L<<0) 2963#define BCE_RPM_DEBUG8_PS_ACPI_FSM_SOF_W3_ADDR (3L<<0) 2964#define BCE_RPM_DEBUG8_PS_ACPI_FSM_SOF_WAIT_THBUF (4L<<0) 2965#define BCE_RPM_DEBUG8_PS_ACPI_FSM_W3_DATA (5L<<0) 2966#define BCE_RPM_DEBUG8_PS_ACPI_FSM_W0_ADDR (6L<<0) 2967#define BCE_RPM_DEBUG8_PS_ACPI_FSM_W1_ADDR (7L<<0) 2968#define BCE_RPM_DEBUG8_PS_ACPI_FSM_W2_ADDR (8L<<0) 2969#define BCE_RPM_DEBUG8_PS_ACPI_FSM_W3_ADDR (9L<<0) 2970#define BCE_RPM_DEBUG8_PS_ACPI_FSM_WAIT_THBUF (10L<<0) 2971#define BCE_RPM_DEBUG8_COMPARE_AT_W0 (1L<<4) 2972#define BCE_RPM_DEBUG8_COMPARE_AT_W3_DATA (1L<<5) 2973#define BCE_RPM_DEBUG8_COMPARE_AT_SOF_WAIT (1L<<6) 2974#define BCE_RPM_DEBUG8_COMPARE_AT_SOF_W3 (1L<<7) 2975#define BCE_RPM_DEBUG8_COMPARE_AT_SOF_W2 (1L<<8) 2976#define BCE_RPM_DEBUG8_EOF_W_LTEQ6_VLDBYTES (1L<<9) 2977#define BCE_RPM_DEBUG8_EOF_W_LTEQ4_VLDBYTES (1L<<10) 2978#define BCE_RPM_DEBUG8_NXT_EOF_W_12_VLDBYTES (1L<<11) 2979#define BCE_RPM_DEBUG8_EOF_DET (1L<<12) 2980#define BCE_RPM_DEBUG8_SOF_DET (1L<<13) 2981#define BCE_RPM_DEBUG8_WAIT_4_SOF (1L<<14) 2982#define BCE_RPM_DEBUG8_ALL_DONE (1L<<15) 2983#define BCE_RPM_DEBUG8_THBUF_ADDR (0x7fL<<16) 2984#define BCE_RPM_DEBUG8_BYTE_CTR (0xffL<<24) 2985 2986#define BCE_RPM_DEBUG9 0x000019a8 2987#define BCE_RPM_DEBUG9_OUTFIFO_COUNT (0x7L<<0) 2988#define BCE_RPM_DEBUG9_RDE_ACPI_RDY (1L<<3) 2989#define BCE_RPM_DEBUG9_VLD_RD_ENTRY_CT (0x7L<<4) 2990#define BCE_RPM_DEBUG9_OUTFIFO_OVERRUN_OCCURRED (1L<<28) 2991#define BCE_RPM_DEBUG9_INFIFO_OVERRUN_OCCURRED (1L<<29) 2992#define BCE_RPM_DEBUG9_ACPI_MATCH_INT (1L<<30) 2993#define BCE_RPM_DEBUG9_ACPI_ENABLE_SYN (1L<<31) 2994 2995#define BCE_RPM_ACPI_DBG_BUF_W00 0x000019c0 2996#define BCE_RPM_ACPI_DBG_BUF_W01 0x000019c4 2997#define BCE_RPM_ACPI_DBG_BUF_W02 0x000019c8 2998#define BCE_RPM_ACPI_DBG_BUF_W03 0x000019cc 2999#define BCE_RPM_ACPI_DBG_BUF_W10 0x000019d0 3000#define BCE_RPM_ACPI_DBG_BUF_W11 0x000019d4 3001#define BCE_RPM_ACPI_DBG_BUF_W12 0x000019d8 3002#define BCE_RPM_ACPI_DBG_BUF_W13 0x000019dc 3003#define BCE_RPM_ACPI_DBG_BUF_W20 0x000019e0 3004#define BCE_RPM_ACPI_DBG_BUF_W21 0x000019e4 3005#define BCE_RPM_ACPI_DBG_BUF_W22 0x000019e8 3006#define BCE_RPM_ACPI_DBG_BUF_W23 0x000019ec 3007#define BCE_RPM_ACPI_DBG_BUF_W30 0x000019f0 3008#define BCE_RPM_ACPI_DBG_BUF_W31 0x000019f4 3009#define BCE_RPM_ACPI_DBG_BUF_W32 0x000019f8 3010#define BCE_RPM_ACPI_DBG_BUF_W33 0x000019fc 3011 3012 3013/* 3014 * rbuf_reg definition 3015 * offset: 0x200000 3016 */ 3017#define BCE_RBUF_COMMAND 0x00200000 3018#define BCE_RBUF_COMMAND_ENABLED (1L<<0) 3019#define BCE_RBUF_COMMAND_FREE_INIT (1L<<1) 3020#define BCE_RBUF_COMMAND_RAM_INIT (1L<<2) 3021#define BCE_RBUF_COMMAND_OVER_FREE (1L<<4) 3022#define BCE_RBUF_COMMAND_ALLOC_REQ (1L<<5) 3023 3024#define BCE_RBUF_STATUS1 0x00200004 3025#define BCE_RBUF_STATUS1_FREE_COUNT (0x3ffL<<0) 3026 3027#define BCE_RBUF_STATUS2 0x00200008 3028#define BCE_RBUF_STATUS2_FREE_TAIL (0x3ffL<<0) 3029#define BCE_RBUF_STATUS2_FREE_HEAD (0x3ffL<<16) 3030 3031#define BCE_RBUF_CONFIG 0x0020000c 3032#define BCE_RBUF_CONFIG_XOFF_TRIP (0x3ffL<<0) 3033#define BCE_RBUF_CONFIG_XON_TRIP (0x3ffL<<16) 3034 3035#define BCE_RBUF_FW_BUF_ALLOC 0x00200010 3036#define BCE_RBUF_FW_BUF_ALLOC_VALUE (0x1ffL<<7) 3037 3038#define BCE_RBUF_FW_BUF_FREE 0x00200014 3039#define BCE_RBUF_FW_BUF_FREE_COUNT (0x7fL<<0) 3040#define BCE_RBUF_FW_BUF_FREE_TAIL (0x1ffL<<7) 3041#define BCE_RBUF_FW_BUF_FREE_HEAD (0x1ffL<<16) 3042 3043#define BCE_RBUF_FW_BUF_SEL 0x00200018 3044#define BCE_RBUF_FW_BUF_SEL_COUNT (0x7fL<<0) 3045#define BCE_RBUF_FW_BUF_SEL_TAIL (0x1ffL<<7) 3046#define BCE_RBUF_FW_BUF_SEL_HEAD (0x1ffL<<16) 3047 3048#define BCE_RBUF_CONFIG2 0x0020001c 3049#define BCE_RBUF_CONFIG2_MAC_DROP_TRIP (0x3ffL<<0) 3050#define BCE_RBUF_CONFIG2_MAC_KEEP_TRIP (0x3ffL<<16) 3051 3052#define BCE_RBUF_CONFIG3 0x00200020 3053#define BCE_RBUF_CONFIG3_CU_DROP_TRIP (0x3ffL<<0) 3054#define BCE_RBUF_CONFIG3_CU_KEEP_TRIP (0x3ffL<<16) 3055 3056#define BCE_RBUF_PKT_DATA 0x00208000 3057#define BCE_RBUF_CLIST_DATA 0x00210000 3058#define BCE_RBUF_BUF_DATA 0x00220000 3059 3060 3061/* 3062 * rv2p_reg definition 3063 * offset: 0x2800 3064 */ 3065#define BCE_RV2P_COMMAND 0x00002800 3066#define BCE_RV2P_COMMAND_ENABLED (1L<<0) 3067#define BCE_RV2P_COMMAND_PROC1_INTRPT (1L<<1) 3068#define BCE_RV2P_COMMAND_PROC2_INTRPT (1L<<2) 3069#define BCE_RV2P_COMMAND_ABORT0 (1L<<4) 3070#define BCE_RV2P_COMMAND_ABORT1 (1L<<5) 3071#define BCE_RV2P_COMMAND_ABORT2 (1L<<6) 3072#define BCE_RV2P_COMMAND_ABORT3 (1L<<7) 3073#define BCE_RV2P_COMMAND_ABORT4 (1L<<8) 3074#define BCE_RV2P_COMMAND_ABORT5 (1L<<9) 3075#define BCE_RV2P_COMMAND_PROC1_RESET (1L<<16) 3076#define BCE_RV2P_COMMAND_PROC2_RESET (1L<<17) 3077#define BCE_RV2P_COMMAND_CTXIF_RESET (1L<<18) 3078 3079#define BCE_RV2P_STATUS 0x00002804 3080#define BCE_RV2P_STATUS_ALWAYS_0 (1L<<0) 3081#define BCE_RV2P_STATUS_RV2P_GEN_STAT0_CNT (1L<<8) 3082#define BCE_RV2P_STATUS_RV2P_GEN_STAT1_CNT (1L<<9) 3083#define BCE_RV2P_STATUS_RV2P_GEN_STAT2_CNT (1L<<10) 3084#define BCE_RV2P_STATUS_RV2P_GEN_STAT3_CNT (1L<<11) 3085#define BCE_RV2P_STATUS_RV2P_GEN_STAT4_CNT (1L<<12) 3086#define BCE_RV2P_STATUS_RV2P_GEN_STAT5_CNT (1L<<13) 3087 3088#define BCE_RV2P_CONFIG 0x00002808 3089#define BCE_RV2P_CONFIG_STALL_PROC1 (1L<<0) 3090#define BCE_RV2P_CONFIG_STALL_PROC2 (1L<<1) 3091#define BCE_RV2P_CONFIG_PROC1_STALL_ON_ABORT0 (1L<<8) 3092#define BCE_RV2P_CONFIG_PROC1_STALL_ON_ABORT1 (1L<<9) 3093#define BCE_RV2P_CONFIG_PROC1_STALL_ON_ABORT2 (1L<<10) 3094#define BCE_RV2P_CONFIG_PROC1_STALL_ON_ABORT3 (1L<<11) 3095#define BCE_RV2P_CONFIG_PROC1_STALL_ON_ABORT4 (1L<<12) 3096#define BCE_RV2P_CONFIG_PROC1_STALL_ON_ABORT5 (1L<<13) 3097#define BCE_RV2P_CONFIG_PROC2_STALL_ON_ABORT0 (1L<<16) 3098#define BCE_RV2P_CONFIG_PROC2_STALL_ON_ABORT1 (1L<<17) 3099#define BCE_RV2P_CONFIG_PROC2_STALL_ON_ABORT2 (1L<<18) 3100#define BCE_RV2P_CONFIG_PROC2_STALL_ON_ABORT3 (1L<<19) 3101#define BCE_RV2P_CONFIG_PROC2_STALL_ON_ABORT4 (1L<<20) 3102#define BCE_RV2P_CONFIG_PROC2_STALL_ON_ABORT5 (1L<<21) 3103#define BCE_RV2P_CONFIG_PAGE_SIZE (0xfL<<24) 3104#define BCE_RV2P_CONFIG_PAGE_SIZE_256 (0L<<24) 3105#define BCE_RV2P_CONFIG_PAGE_SIZE_512 (1L<<24) 3106#define BCE_RV2P_CONFIG_PAGE_SIZE_1K (2L<<24) 3107#define BCE_RV2P_CONFIG_PAGE_SIZE_2K (3L<<24) 3108#define BCE_RV2P_CONFIG_PAGE_SIZE_4K (4L<<24) 3109#define BCE_RV2P_CONFIG_PAGE_SIZE_8K (5L<<24) 3110#define BCE_RV2P_CONFIG_PAGE_SIZE_16K (6L<<24) 3111#define BCE_RV2P_CONFIG_PAGE_SIZE_32K (7L<<24) 3112#define BCE_RV2P_CONFIG_PAGE_SIZE_64K (8L<<24) 3113#define BCE_RV2P_CONFIG_PAGE_SIZE_128K (9L<<24) 3114#define BCE_RV2P_CONFIG_PAGE_SIZE_256K (10L<<24) 3115#define BCE_RV2P_CONFIG_PAGE_SIZE_512K (11L<<24) 3116#define BCE_RV2P_CONFIG_PAGE_SIZE_1M (12L<<24) 3117 3118#define BCE_RV2P_GEN_BFR_ADDR_0 0x00002810 3119#define BCE_RV2P_GEN_BFR_ADDR_0_VALUE (0xffffL<<16) 3120 3121#define BCE_RV2P_GEN_BFR_ADDR_1 0x00002814 3122#define BCE_RV2P_GEN_BFR_ADDR_1_VALUE (0xffffL<<16) 3123 3124#define BCE_RV2P_GEN_BFR_ADDR_2 0x00002818 3125#define BCE_RV2P_GEN_BFR_ADDR_2_VALUE (0xffffL<<16) 3126 3127#define BCE_RV2P_GEN_BFR_ADDR_3 0x0000281c 3128#define BCE_RV2P_GEN_BFR_ADDR_3_VALUE (0xffffL<<16) 3129 3130#define BCE_RV2P_INSTR_HIGH 0x00002830 3131#define BCE_RV2P_INSTR_HIGH_HIGH (0x1fL<<0) 3132 3133#define BCE_RV2P_INSTR_LOW 0x00002834 3134#define BCE_RV2P_PROC1_ADDR_CMD 0x00002838 3135#define BCE_RV2P_PROC1_ADDR_CMD_ADD (0x3ffL<<0) 3136#define BCE_RV2P_PROC1_ADDR_CMD_RDWR (1L<<31) 3137 3138#define BCE_RV2P_PROC2_ADDR_CMD 0x0000283c 3139#define BCE_RV2P_PROC2_ADDR_CMD_ADD (0x3ffL<<0) 3140#define BCE_RV2P_PROC2_ADDR_CMD_RDWR (1L<<31) 3141 3142#define BCE_RV2P_PROC1_GRC_DEBUG 0x00002840 3143#define BCE_RV2P_PROC2_GRC_DEBUG 0x00002844 3144#define BCE_RV2P_GRC_PROC_DEBUG 0x00002848 3145#define BCE_RV2P_DEBUG_VECT_PEEK 0x0000284c 3146#define BCE_RV2P_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) 3147#define BCE_RV2P_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) 3148#define BCE_RV2P_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) 3149#define BCE_RV2P_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) 3150#define BCE_RV2P_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) 3151#define BCE_RV2P_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) 3152 3153#define BCE_RV2P_PFTQ_DATA 0x00002b40 3154#define BCE_RV2P_PFTQ_CMD 0x00002b78 3155#define BCE_RV2P_PFTQ_CMD_OFFSET (0x3ffL<<0) 3156#define BCE_RV2P_PFTQ_CMD_WR_TOP (1L<<10) 3157#define BCE_RV2P_PFTQ_CMD_WR_TOP_0 (0L<<10) 3158#define BCE_RV2P_PFTQ_CMD_WR_TOP_1 (1L<<10) 3159#define BCE_RV2P_PFTQ_CMD_SFT_RESET (1L<<25) 3160#define BCE_RV2P_PFTQ_CMD_RD_DATA (1L<<26) 3161#define BCE_RV2P_PFTQ_CMD_ADD_INTERVEN (1L<<27) 3162#define BCE_RV2P_PFTQ_CMD_ADD_DATA (1L<<28) 3163#define BCE_RV2P_PFTQ_CMD_INTERVENE_CLR (1L<<29) 3164#define BCE_RV2P_PFTQ_CMD_POP (1L<<30) 3165#define BCE_RV2P_PFTQ_CMD_BUSY (1L<<31) 3166 3167#define BCE_RV2P_PFTQ_CTL 0x00002b7c 3168#define BCE_RV2P_PFTQ_CTL_INTERVENE (1L<<0) 3169#define BCE_RV2P_PFTQ_CTL_OVERFLOW (1L<<1) 3170#define BCE_RV2P_PFTQ_CTL_FORCE_INTERVENE (1L<<2) 3171#define BCE_RV2P_PFTQ_CTL_MAX_DEPTH (0x3ffL<<12) 3172#define BCE_RV2P_PFTQ_CTL_CUR_DEPTH (0x3ffL<<22) 3173 3174#define BCE_RV2P_TFTQ_DATA 0x00002b80 3175#define BCE_RV2P_TFTQ_CMD 0x00002bb8 3176#define BCE_RV2P_TFTQ_CMD_OFFSET (0x3ffL<<0) 3177#define BCE_RV2P_TFTQ_CMD_WR_TOP (1L<<10) 3178#define BCE_RV2P_TFTQ_CMD_WR_TOP_0 (0L<<10) 3179#define BCE_RV2P_TFTQ_CMD_WR_TOP_1 (1L<<10) 3180#define BCE_RV2P_TFTQ_CMD_SFT_RESET (1L<<25) 3181#define BCE_RV2P_TFTQ_CMD_RD_DATA (1L<<26) 3182#define BCE_RV2P_TFTQ_CMD_ADD_INTERVEN (1L<<27) 3183#define BCE_RV2P_TFTQ_CMD_ADD_DATA (1L<<28) 3184#define BCE_RV2P_TFTQ_CMD_INTERVENE_CLR (1L<<29) 3185#define BCE_RV2P_TFTQ_CMD_POP (1L<<30) 3186#define BCE_RV2P_TFTQ_CMD_BUSY (1L<<31) 3187 3188#define BCE_RV2P_TFTQ_CTL 0x00002bbc 3189#define BCE_RV2P_TFTQ_CTL_INTERVENE (1L<<0) 3190#define BCE_RV2P_TFTQ_CTL_OVERFLOW (1L<<1) 3191#define BCE_RV2P_TFTQ_CTL_FORCE_INTERVENE (1L<<2) 3192#define BCE_RV2P_TFTQ_CTL_MAX_DEPTH (0x3ffL<<12) 3193#define BCE_RV2P_TFTQ_CTL_CUR_DEPTH (0x3ffL<<22) 3194 3195#define BCE_RV2P_MFTQ_DATA 0x00002bc0 3196#define BCE_RV2P_MFTQ_CMD 0x00002bf8 3197#define BCE_RV2P_MFTQ_CMD_OFFSET (0x3ffL<<0) 3198#define BCE_RV2P_MFTQ_CMD_WR_TOP (1L<<10) 3199#define BCE_RV2P_MFTQ_CMD_WR_TOP_0 (0L<<10) 3200#define BCE_RV2P_MFTQ_CMD_WR_TOP_1 (1L<<10) 3201#define BCE_RV2P_MFTQ_CMD_SFT_RESET (1L<<25) 3202#define BCE_RV2P_MFTQ_CMD_RD_DATA (1L<<26) 3203#define BCE_RV2P_MFTQ_CMD_ADD_INTERVEN (1L<<27) 3204#define BCE_RV2P_MFTQ_CMD_ADD_DATA (1L<<28) 3205#define BCE_RV2P_MFTQ_CMD_INTERVENE_CLR (1L<<29) 3206#define BCE_RV2P_MFTQ_CMD_POP (1L<<30) 3207#define BCE_RV2P_MFTQ_CMD_BUSY (1L<<31) 3208 3209#define BCE_RV2P_MFTQ_CTL 0x00002bfc 3210#define BCE_RV2P_MFTQ_CTL_INTERVENE (1L<<0) 3211#define BCE_RV2P_MFTQ_CTL_OVERFLOW (1L<<1) 3212#define BCE_RV2P_MFTQ_CTL_FORCE_INTERVENE (1L<<2) 3213#define BCE_RV2P_MFTQ_CTL_MAX_DEPTH (0x3ffL<<12) 3214#define BCE_RV2P_MFTQ_CTL_CUR_DEPTH (0x3ffL<<22) 3215 3216 3217 3218/* 3219 * mq_reg definition 3220 * offset: 0x3c00 3221 */ 3222#define BCE_MQ_COMMAND 0x00003c00 3223#define BCE_MQ_COMMAND_ENABLED (1L<<0) 3224#define BCE_MQ_COMMAND_OVERFLOW (1L<<4) 3225#define BCE_MQ_COMMAND_WR_ERROR (1L<<5) 3226#define BCE_MQ_COMMAND_RD_ERROR (1L<<6) 3227 3228#define BCE_MQ_STATUS 0x00003c04 3229#define BCE_MQ_STATUS_CTX_ACCESS_STAT (1L<<16) 3230#define BCE_MQ_STATUS_CTX_ACCESS64_STAT (1L<<17) 3231#define BCE_MQ_STATUS_PCI_STALL_STAT (1L<<18) 3232 3233#define BCE_MQ_CONFIG 0x00003c08 3234#define BCE_MQ_CONFIG_TX_HIGH_PRI (1L<<0) 3235#define BCE_MQ_CONFIG_HALT_DIS (1L<<1) 3236#define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE (0x7L<<4) 3237#define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256 (0L<<4) 3238#define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_512 (1L<<4) 3239#define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_1K (2L<<4) 3240#define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_2K (3L<<4) 3241#define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_4K (4L<<4) 3242#define BCE_MQ_CONFIG_MAX_DEPTH (0x7fL<<8) 3243#define BCE_MQ_CONFIG_CUR_DEPTH (0x7fL<<20) 3244 3245#define BCE_MQ_ENQUEUE1 0x00003c0c 3246#define BCE_MQ_ENQUEUE1_OFFSET (0x3fL<<2) 3247#define BCE_MQ_ENQUEUE1_CID (0x3fffL<<8) 3248#define BCE_MQ_ENQUEUE1_BYTE_MASK (0xfL<<24) 3249#define BCE_MQ_ENQUEUE1_KNL_MODE (1L<<28) 3250 3251#define BCE_MQ_ENQUEUE2 0x00003c10 3252#define BCE_MQ_BAD_WR_ADDR 0x00003c14 3253#define BCE_MQ_BAD_RD_ADDR 0x00003c18 3254#define BCE_MQ_KNL_BYP_WIND_START 0x00003c1c 3255#define BCE_MQ_KNL_BYP_WIND_START_VALUE (0xfffffL<<12) 3256 3257#define BCE_MQ_KNL_WIND_END 0x00003c20 3258#define BCE_MQ_KNL_WIND_END_VALUE (0xffffffL<<8) 3259 3260#define BCE_MQ_KNL_WRITE_MASK1 0x00003c24 3261#define BCE_MQ_KNL_TX_MASK1 0x00003c28 3262#define BCE_MQ_KNL_CMD_MASK1 0x00003c2c 3263#define BCE_MQ_KNL_COND_ENQUEUE_MASK1 0x00003c30 3264#define BCE_MQ_KNL_RX_V2P_MASK1 0x00003c34 3265#define BCE_MQ_KNL_WRITE_MASK2 0x00003c38 3266#define BCE_MQ_KNL_TX_MASK2 0x00003c3c 3267#define BCE_MQ_KNL_CMD_MASK2 0x00003c40 3268#define BCE_MQ_KNL_COND_ENQUEUE_MASK2 0x00003c44 3269#define BCE_MQ_KNL_RX_V2P_MASK2 0x00003c48 3270#define BCE_MQ_KNL_BYP_WRITE_MASK1 0x00003c4c 3271#define BCE_MQ_KNL_BYP_TX_MASK1 0x00003c50 3272#define BCE_MQ_KNL_BYP_CMD_MASK1 0x00003c54 3273#define BCE_MQ_KNL_BYP_COND_ENQUEUE_MASK1 0x00003c58 3274#define BCE_MQ_KNL_BYP_RX_V2P_MASK1 0x00003c5c 3275#define BCE_MQ_KNL_BYP_WRITE_MASK2 0x00003c60 3276#define BCE_MQ_KNL_BYP_TX_MASK2 0x00003c64 3277#define BCE_MQ_KNL_BYP_CMD_MASK2 0x00003c68 3278#define BCE_MQ_KNL_BYP_COND_ENQUEUE_MASK2 0x00003c6c 3279#define BCE_MQ_KNL_BYP_RX_V2P_MASK2 0x00003c70 3280#define BCE_MQ_MEM_WR_ADDR 0x00003c74 3281#define BCE_MQ_MEM_WR_ADDR_VALUE (0x3fL<<0) 3282 3283#define BCE_MQ_MEM_WR_DATA0 0x00003c78 3284#define BCE_MQ_MEM_WR_DATA0_VALUE (0xffffffffL<<0) 3285 3286#define BCE_MQ_MEM_WR_DATA1 0x00003c7c 3287#define BCE_MQ_MEM_WR_DATA1_VALUE (0xffffffffL<<0) 3288 3289#define BCE_MQ_MEM_WR_DATA2 0x00003c80 3290#define BCE_MQ_MEM_WR_DATA2_VALUE (0x3fffffffL<<0) 3291 3292#define BCE_MQ_MEM_RD_ADDR 0x00003c84 3293#define BCE_MQ_MEM_RD_ADDR_VALUE (0x3fL<<0) 3294 3295#define BCE_MQ_MEM_RD_DATA0 0x00003c88 3296#define BCE_MQ_MEM_RD_DATA0_VALUE (0xffffffffL<<0) 3297 3298#define BCE_MQ_MEM_RD_DATA1 0x00003c8c 3299#define BCE_MQ_MEM_RD_DATA1_VALUE (0xffffffffL<<0) 3300 3301#define BCE_MQ_MEM_RD_DATA2 0x00003c90 3302#define BCE_MQ_MEM_RD_DATA2_VALUE (0x3fffffffL<<0) 3303 3304 3305 3306/* 3307 * tbdr_reg definition 3308 * offset: 0x5000 3309 */ 3310#define BCE_TBDR_COMMAND 0x00005000 3311#define BCE_TBDR_COMMAND_ENABLE (1L<<0) 3312#define BCE_TBDR_COMMAND_SOFT_RST (1L<<1) 3313#define BCE_TBDR_COMMAND_MSTR_ABORT (1L<<4) 3314 3315#define BCE_TBDR_STATUS 0x00005004 3316#define BCE_TBDR_STATUS_DMA_WAIT (1L<<0) 3317#define BCE_TBDR_STATUS_FTQ_WAIT (1L<<1) 3318#define BCE_TBDR_STATUS_FIFO_OVERFLOW (1L<<2) 3319#define BCE_TBDR_STATUS_FIFO_UNDERFLOW (1L<<3) 3320#define BCE_TBDR_STATUS_SEARCHMISS_ERROR (1L<<4) 3321#define BCE_TBDR_STATUS_FTQ_ENTRY_CNT (1L<<5) 3322#define BCE_TBDR_STATUS_BURST_CNT (1L<<6) 3323 3324#define BCE_TBDR_CONFIG 0x00005008 3325#define BCE_TBDR_CONFIG_MAX_BDS (0xffL<<0) 3326#define BCE_TBDR_CONFIG_SWAP_MODE (1L<<8) 3327#define BCE_TBDR_CONFIG_PRIORITY (1L<<9) 3328#define BCE_TBDR_CONFIG_CACHE_NEXT_PAGE_PTRS (1L<<10) 3329#define BCE_TBDR_CONFIG_PAGE_SIZE (0xfL<<24) 3330#define BCE_TBDR_CONFIG_PAGE_SIZE_256 (0L<<24) 3331#define BCE_TBDR_CONFIG_PAGE_SIZE_512 (1L<<24) 3332#define BCE_TBDR_CONFIG_PAGE_SIZE_1K (2L<<24) 3333#define BCE_TBDR_CONFIG_PAGE_SIZE_2K (3L<<24) 3334#define BCE_TBDR_CONFIG_PAGE_SIZE_4K (4L<<24) 3335#define BCE_TBDR_CONFIG_PAGE_SIZE_8K (5L<<24) 3336#define BCE_TBDR_CONFIG_PAGE_SIZE_16K (6L<<24) 3337#define BCE_TBDR_CONFIG_PAGE_SIZE_32K (7L<<24) 3338#define BCE_TBDR_CONFIG_PAGE_SIZE_64K (8L<<24) 3339#define BCE_TBDR_CONFIG_PAGE_SIZE_128K (9L<<24) 3340#define BCE_TBDR_CONFIG_PAGE_SIZE_256K (10L<<24) 3341#define BCE_TBDR_CONFIG_PAGE_SIZE_512K (11L<<24) 3342#define BCE_TBDR_CONFIG_PAGE_SIZE_1M (12L<<24) 3343 3344#define BCE_TBDR_DEBUG_VECT_PEEK 0x0000500c 3345#define BCE_TBDR_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) 3346#define BCE_TBDR_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) 3347#define BCE_TBDR_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) 3348#define BCE_TBDR_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) 3349#define BCE_TBDR_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) 3350#define BCE_TBDR_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) 3351 3352#define BCE_TBDR_FTQ_DATA 0x000053c0 3353#define BCE_TBDR_FTQ_CMD 0x000053f8 3354#define BCE_TBDR_FTQ_CMD_OFFSET (0x3ffL<<0) 3355#define BCE_TBDR_FTQ_CMD_WR_TOP (1L<<10) 3356#define BCE_TBDR_FTQ_CMD_WR_TOP_0 (0L<<10) 3357#define BCE_TBDR_FTQ_CMD_WR_TOP_1 (1L<<10) 3358#define BCE_TBDR_FTQ_CMD_SFT_RESET (1L<<25) 3359#define BCE_TBDR_FTQ_CMD_RD_DATA (1L<<26) 3360#define BCE_TBDR_FTQ_CMD_ADD_INTERVEN (1L<<27) 3361#define BCE_TBDR_FTQ_CMD_ADD_DATA (1L<<28) 3362#define BCE_TBDR_FTQ_CMD_INTERVENE_CLR (1L<<29) 3363#define BCE_TBDR_FTQ_CMD_POP (1L<<30) 3364#define BCE_TBDR_FTQ_CMD_BUSY (1L<<31) 3365 3366#define BCE_TBDR_FTQ_CTL 0x000053fc 3367#define BCE_TBDR_FTQ_CTL_INTERVENE (1L<<0) 3368#define BCE_TBDR_FTQ_CTL_OVERFLOW (1L<<1) 3369#define BCE_TBDR_FTQ_CTL_FORCE_INTERVENE (1L<<2) 3370#define BCE_TBDR_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 3371#define BCE_TBDR_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 3372 3373 3374 3375/* 3376 * tdma_reg definition 3377 * offset: 0x5c00 3378 */ 3379#define BCE_TDMA_COMMAND 0x00005c00 3380#define BCE_TDMA_COMMAND_ENABLED (1L<<0) 3381#define BCE_TDMA_COMMAND_MASTER_ABORT (1L<<4) 3382#define BCE_TDMA_COMMAND_BAD_L2_LENGTH_ABORT (1L<<7) 3383 3384#define BCE_TDMA_STATUS 0x00005c04 3385#define BCE_TDMA_STATUS_DMA_WAIT (1L<<0) 3386#define BCE_TDMA_STATUS_PAYLOAD_WAIT (1L<<1) 3387#define BCE_TDMA_STATUS_PATCH_FTQ_WAIT (1L<<2) 3388#define BCE_TDMA_STATUS_LOCK_WAIT (1L<<3) 3389#define BCE_TDMA_STATUS_FTQ_ENTRY_CNT (1L<<16) 3390#define BCE_TDMA_STATUS_BURST_CNT (1L<<17) 3391 3392#define BCE_TDMA_CONFIG 0x00005c08 3393#define BCE_TDMA_CONFIG_ONE_DMA (1L<<0) 3394#define BCE_TDMA_CONFIG_ONE_RECORD (1L<<1) 3395#define BCE_TDMA_CONFIG_LIMIT_SZ (0xfL<<4) 3396#define BCE_TDMA_CONFIG_LIMIT_SZ_64 (0L<<4) 3397#define BCE_TDMA_CONFIG_LIMIT_SZ_128 (0x4L<<4) 3398#define BCE_TDMA_CONFIG_LIMIT_SZ_256 (0x6L<<4) 3399#define BCE_TDMA_CONFIG_LIMIT_SZ_512 (0x8L<<4) 3400#define BCE_TDMA_CONFIG_LINE_SZ (0xfL<<8) 3401#define BCE_TDMA_CONFIG_LINE_SZ_64 (0L<<8) 3402#define BCE_TDMA_CONFIG_LINE_SZ_128 (4L<<8) 3403#define BCE_TDMA_CONFIG_LINE_SZ_256 (6L<<8) 3404#define BCE_TDMA_CONFIG_LINE_SZ_512 (8L<<8) 3405#define BCE_TDMA_CONFIG_ALIGN_ENA (1L<<15) 3406#define BCE_TDMA_CONFIG_CHK_L2_BD (1L<<16) 3407#define BCE_TDMA_CONFIG_FIFO_CMP (0xfL<<20) 3408 3409#define BCE_TDMA_PAYLOAD_PROD 0x00005c0c 3410#define BCE_TDMA_PAYLOAD_PROD_VALUE (0x1fffL<<3) 3411 3412#define BCE_TDMA_DBG_WATCHDOG 0x00005c10 3413#define BCE_TDMA_DBG_TRIGGER 0x00005c14 3414#define BCE_TDMA_DMAD_FSM 0x00005c80 3415#define BCE_TDMA_DMAD_FSM_BD_INVLD (1L<<0) 3416#define BCE_TDMA_DMAD_FSM_PUSH (0xfL<<4) 3417#define BCE_TDMA_DMAD_FSM_ARB_TBDC (0x3L<<8) 3418#define BCE_TDMA_DMAD_FSM_ARB_CTX (1L<<12) 3419#define BCE_TDMA_DMAD_FSM_DR_INTF (1L<<16) 3420#define BCE_TDMA_DMAD_FSM_DMAD (0x7L<<20) 3421#define BCE_TDMA_DMAD_FSM_BD (0xfL<<24) 3422 3423#define BCE_TDMA_DMAD_STATUS 0x00005c84 3424#define BCE_TDMA_DMAD_STATUS_RHOLD_PUSH_ENTRY (0x3L<<0) 3425#define BCE_TDMA_DMAD_STATUS_RHOLD_DMAD_ENTRY (0x3L<<4) 3426#define BCE_TDMA_DMAD_STATUS_RHOLD_BD_ENTRY (0x3L<<8) 3427#define BCE_TDMA_DMAD_STATUS_IFTQ_ENUM (0xfL<<12) 3428 3429#define BCE_TDMA_DR_INTF_FSM 0x00005c88 3430#define BCE_TDMA_DR_INTF_FSM_L2_COMP (0x3L<<0) 3431#define BCE_TDMA_DR_INTF_FSM_TPATQ (0x7L<<4) 3432#define BCE_TDMA_DR_INTF_FSM_TPBUF (0x3L<<8) 3433#define BCE_TDMA_DR_INTF_FSM_DR_BUF (0x7L<<12) 3434#define BCE_TDMA_DR_INTF_FSM_DMAD (0x7L<<16) 3435 3436#define BCE_TDMA_DR_INTF_STATUS 0x00005c8c 3437#define BCE_TDMA_DR_INTF_STATUS_HOLE_PHASE (0x7L<<0) 3438#define BCE_TDMA_DR_INTF_STATUS_DATA_AVAIL (0x3L<<4) 3439#define BCE_TDMA_DR_INTF_STATUS_SHIFT_ADDR (0x7L<<8) 3440#define BCE_TDMA_DR_INTF_STATUS_NXT_PNTR (0xfL<<12) 3441#define BCE_TDMA_DR_INTF_STATUS_BYTE_COUNT (0x7L<<16) 3442 3443#define BCE_TDMA_FTQ_DATA 0x00005fc0 3444#define BCE_TDMA_FTQ_CMD 0x00005ff8 3445#define BCE_TDMA_FTQ_CMD_OFFSET (0x3ffL<<0) 3446#define BCE_TDMA_FTQ_CMD_WR_TOP (1L<<10) 3447#define BCE_TDMA_FTQ_CMD_WR_TOP_0 (0L<<10) 3448#define BCE_TDMA_FTQ_CMD_WR_TOP_1 (1L<<10) 3449#define BCE_TDMA_FTQ_CMD_SFT_RESET (1L<<25) 3450#define BCE_TDMA_FTQ_CMD_RD_DATA (1L<<26) 3451#define BCE_TDMA_FTQ_CMD_ADD_INTERVEN (1L<<27) 3452#define BCE_TDMA_FTQ_CMD_ADD_DATA (1L<<28) 3453#define BCE_TDMA_FTQ_CMD_INTERVENE_CLR (1L<<29) 3454#define BCE_TDMA_FTQ_CMD_POP (1L<<30) 3455#define BCE_TDMA_FTQ_CMD_BUSY (1L<<31) 3456 3457#define BCE_TDMA_FTQ_CTL 0x00005ffc 3458#define BCE_TDMA_FTQ_CTL_INTERVENE (1L<<0) 3459#define BCE_TDMA_FTQ_CTL_OVERFLOW (1L<<1) 3460#define BCE_TDMA_FTQ_CTL_FORCE_INTERVENE (1L<<2) 3461#define BCE_TDMA_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 3462#define BCE_TDMA_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 3463 3464 3465 3466/* 3467 * hc_reg definition 3468 * offset: 0x6800 3469 */ 3470#define BCE_HC_COMMAND 0x00006800 3471#define BCE_HC_COMMAND_ENABLE (1L<<0) 3472#define BCE_HC_COMMAND_SKIP_ABORT (1L<<4) 3473#define BCE_HC_COMMAND_COAL_NOW (1L<<16) 3474#define BCE_HC_COMMAND_COAL_NOW_WO_INT (1L<<17) 3475#define BCE_HC_COMMAND_STATS_NOW (1L<<18) 3476#define BCE_HC_COMMAND_FORCE_INT (0x3L<<19) 3477#define BCE_HC_COMMAND_FORCE_INT_NULL (0L<<19) 3478#define BCE_HC_COMMAND_FORCE_INT_HIGH (1L<<19) 3479#define BCE_HC_COMMAND_FORCE_INT_LOW (2L<<19) 3480#define BCE_HC_COMMAND_FORCE_INT_FREE (3L<<19) 3481#define BCE_HC_COMMAND_CLR_STAT_NOW (1L<<21) 3482 3483#define BCE_HC_STATUS 0x00006804 3484#define BCE_HC_STATUS_MASTER_ABORT (1L<<0) 3485#define BCE_HC_STATUS_PARITY_ERROR_STATE (1L<<1) 3486#define BCE_HC_STATUS_PCI_CLK_CNT_STAT (1L<<16) 3487#define BCE_HC_STATUS_CORE_CLK_CNT_STAT (1L<<17) 3488#define BCE_HC_STATUS_NUM_STATUS_BLOCKS_STAT (1L<<18) 3489#define BCE_HC_STATUS_NUM_INT_GEN_STAT (1L<<19) 3490#define BCE_HC_STATUS_NUM_INT_MBOX_WR_STAT (1L<<20) 3491#define BCE_HC_STATUS_CORE_CLKS_TO_HW_INTACK_STAT (1L<<23) 3492#define BCE_HC_STATUS_CORE_CLKS_TO_SW_INTACK_STAT (1L<<24) 3493#define BCE_HC_STATUS_CORE_CLKS_DURING_SW_INTACK_STAT (1L<<25) 3494 3495#define BCE_HC_CONFIG 0x00006808 3496#define BCE_HC_CONFIG_COLLECT_STATS (1L<<0) 3497#define BCE_HC_CONFIG_RX_TMR_MODE (1L<<1) 3498#define BCE_HC_CONFIG_TX_TMR_MODE (1L<<2) 3499#define BCE_HC_CONFIG_COM_TMR_MODE (1L<<3) 3500#define BCE_HC_CONFIG_CMD_TMR_MODE (1L<<4) 3501#define BCE_HC_CONFIG_STATISTIC_PRIORITY (1L<<5) 3502#define BCE_HC_CONFIG_STATUS_PRIORITY (1L<<6) 3503#define BCE_HC_CONFIG_STAT_MEM_ADDR (0xffL<<8) 3504 3505#define BCE_HC_ATTN_BITS_ENABLE 0x0000680c 3506#define BCE_HC_STATUS_ADDR_L 0x00006810 3507#define BCE_HC_STATUS_ADDR_H 0x00006814 3508#define BCE_HC_STATISTICS_ADDR_L 0x00006818 3509#define BCE_HC_STATISTICS_ADDR_H 0x0000681c 3510#define BCE_HC_TX_QUICK_CONS_TRIP 0x00006820 3511#define BCE_HC_TX_QUICK_CONS_TRIP_VALUE (0xffL<<0) 3512#define BCE_HC_TX_QUICK_CONS_TRIP_INT (0xffL<<16) 3513 3514#define BCE_HC_COMP_PROD_TRIP 0x00006824 3515#define BCE_HC_COMP_PROD_TRIP_VALUE (0xffL<<0) 3516#define BCE_HC_COMP_PROD_TRIP_INT (0xffL<<16) 3517 3518#define BCE_HC_RX_QUICK_CONS_TRIP 0x00006828 3519#define BCE_HC_RX_QUICK_CONS_TRIP_VALUE (0xffL<<0) 3520#define BCE_HC_RX_QUICK_CONS_TRIP_INT (0xffL<<16) 3521 3522#define BCE_HC_RX_TICKS 0x0000682c 3523#define BCE_HC_RX_TICKS_VALUE (0x3ffL<<0) 3524#define BCE_HC_RX_TICKS_INT (0x3ffL<<16) 3525 3526#define BCE_HC_TX_TICKS 0x00006830 3527#define BCE_HC_TX_TICKS_VALUE (0x3ffL<<0) 3528#define BCE_HC_TX_TICKS_INT (0x3ffL<<16) 3529 3530#define BCE_HC_COM_TICKS 0x00006834 3531#define BCE_HC_COM_TICKS_VALUE (0x3ffL<<0) 3532#define BCE_HC_COM_TICKS_INT (0x3ffL<<16) 3533 3534#define BCE_HC_CMD_TICKS 0x00006838 3535#define BCE_HC_CMD_TICKS_VALUE (0x3ffL<<0) 3536#define BCE_HC_CMD_TICKS_INT (0x3ffL<<16) 3537 3538#define BCE_HC_PERIODIC_TICKS 0x0000683c 3539#define BCE_HC_PERIODIC_TICKS_HC_PERIODIC_TICKS (0xffffL<<0) 3540 3541#define BCE_HC_STAT_COLLECT_TICKS 0x00006840 3542#define BCE_HC_STAT_COLLECT_TICKS_HC_STAT_COLL_TICKS (0xffL<<4) 3543 3544#define BCE_HC_STATS_TICKS 0x00006844 3545#define BCE_HC_STATS_TICKS_HC_STAT_TICKS (0xffffL<<8) 3546 3547#define BCE_HC_STAT_MEM_DATA 0x0000684c 3548#define BCE_HC_STAT_GEN_SEL_0 0x00006850 3549#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0 (0x7fL<<0) 3550#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT0 (0L<<0) 3551#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT1 (1L<<0) 3552#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT2 (2L<<0) 3553#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT3 (3L<<0) 3554#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT4 (4L<<0) 3555#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT5 (5L<<0) 3556#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT6 (6L<<0) 3557#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT7 (7L<<0) 3558#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT8 (8L<<0) 3559#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT9 (9L<<0) 3560#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT10 (10L<<0) 3561#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT11 (11L<<0) 3562#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT0 (12L<<0) 3563#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT1 (13L<<0) 3564#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT2 (14L<<0) 3565#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT3 (15L<<0) 3566#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT4 (16L<<0) 3567#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT5 (17L<<0) 3568#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT6 (18L<<0) 3569#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT7 (19L<<0) 3570#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT0 (20L<<0) 3571#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT1 (21L<<0) 3572#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT2 (22L<<0) 3573#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT3 (23L<<0) 3574#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT4 (24L<<0) 3575#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT5 (25L<<0) 3576#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT6 (26L<<0) 3577#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT7 (27L<<0) 3578#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT8 (28L<<0) 3579#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT9 (29L<<0) 3580#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT10 (30L<<0) 3581#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT11 (31L<<0) 3582#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT0 (32L<<0) 3583#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT1 (33L<<0) 3584#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT2 (34L<<0) 3585#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT3 (35L<<0) 3586#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT0 (36L<<0) 3587#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT1 (37L<<0) 3588#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT2 (38L<<0) 3589#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT3 (39L<<0) 3590#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT4 (40L<<0) 3591#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT5 (41L<<0) 3592#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT6 (42L<<0) 3593#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT7 (43L<<0) 3594#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT0 (44L<<0) 3595#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT1 (45L<<0) 3596#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT2 (46L<<0) 3597#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT3 (47L<<0) 3598#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT4 (48L<<0) 3599#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT5 (49L<<0) 3600#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT6 (50L<<0) 3601#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT7 (51L<<0) 3602#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_PCI_CLK_CNT (52L<<0) 3603#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CORE_CLK_CNT (53L<<0) 3604#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS (54L<<0) 3605#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN (55L<<0) 3606#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR (56L<<0) 3607#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK (59L<<0) 3608#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK (60L<<0) 3609#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK (61L<<0) 3610#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_CMD_CNT (62L<<0) 3611#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_SLOT_CNT (63L<<0) 3612#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_CMD_CNT (64L<<0) 3613#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_SLOT_CNT (65L<<0) 3614#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT (66L<<0) 3615#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT (67L<<0) 3616#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT (68L<<0) 3617#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT (69L<<0) 3618#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT (70L<<0) 3619#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT (71L<<0) 3620#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT (72L<<0) 3621#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT (73L<<0) 3622#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT (74L<<0) 3623#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT (75L<<0) 3624#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT (76L<<0) 3625#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT (77L<<0) 3626#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT (78L<<0) 3627#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT (79L<<0) 3628#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT (80L<<0) 3629#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT (81L<<0) 3630#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT (82L<<0) 3631#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT (83L<<0) 3632#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT (84L<<0) 3633#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_TRANSFERS_CNT (85L<<0) 3634#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_DELAY_PCI_CLKS_CNT (86L<<0) 3635#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_TRANSFERS_CNT (87L<<0) 3636#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_DELAY_PCI_CLKS_CNT (88L<<0) 3637#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_RETRY_AFTER_DATA_CNT (89L<<0) 3638#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_TRANSFERS_CNT (90L<<0) 3639#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_DELAY_PCI_CLKS_CNT (91L<<0) 3640#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_TRANSFERS_CNT (92L<<0) 3641#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_DELAY_PCI_CLKS_CNT (93L<<0) 3642#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_RETRY_AFTER_DATA_CNT (94L<<0) 3643#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_WR_CNT64 (95L<<0) 3644#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_RD_CNT64 (96L<<0) 3645#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_ACC_STALL_CLKS (97L<<0) 3646#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_LOCK_STALL_CLKS (98L<<0) 3647#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS_STAT (99L<<0) 3648#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS64_STAT (100L<<0) 3649#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_PCI_STALL_STAT (101L<<0) 3650#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_FTQ_ENTRY_CNT (102L<<0) 3651#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_BURST_CNT (103L<<0) 3652#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_FTQ_ENTRY_CNT (104L<<0) 3653#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_BURST_CNT (105L<<0) 3654#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_FTQ_ENTRY_CNT (106L<<0) 3655#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_BURST_CNT (107L<<0) 3656#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUP_MATCH_CNT (108L<<0) 3657#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_POLL_PASS_CNT (109L<<0) 3658#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR1_CNT (110L<<0) 3659#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR2_CNT (111L<<0) 3660#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR3_CNT (112L<<0) 3661#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR4_CNT (113L<<0) 3662#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR5_CNT (114L<<0) 3663#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT0 (115L<<0) 3664#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT1 (116L<<0) 3665#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT2 (117L<<0) 3666#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT3 (118L<<0) 3667#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT4 (119L<<0) 3668#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT5 (120L<<0) 3669#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC1_MISS (121L<<0) 3670#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC2_MISS (122L<<0) 3671#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_BURST_CNT (127L<<0) 3672#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_1 (0x7fL<<8) 3673#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_2 (0x7fL<<16) 3674#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_3 (0x7fL<<24) 3675 3676#define BCE_HC_STAT_GEN_SEL_1 0x00006854 3677#define BCE_HC_STAT_GEN_SEL_1_GEN_SEL_4 (0x7fL<<0) 3678#define BCE_HC_STAT_GEN_SEL_1_GEN_SEL_5 (0x7fL<<8) 3679#define BCE_HC_STAT_GEN_SEL_1_GEN_SEL_6 (0x7fL<<16) 3680#define BCE_HC_STAT_GEN_SEL_1_GEN_SEL_7 (0x7fL<<24) 3681 3682#define BCE_HC_STAT_GEN_SEL_2 0x00006858 3683#define BCE_HC_STAT_GEN_SEL_2_GEN_SEL_8 (0x7fL<<0) 3684#define BCE_HC_STAT_GEN_SEL_2_GEN_SEL_9 (0x7fL<<8) 3685#define BCE_HC_STAT_GEN_SEL_2_GEN_SEL_10 (0x7fL<<16) 3686#define BCE_HC_STAT_GEN_SEL_2_GEN_SEL_11 (0x7fL<<24) 3687 3688#define BCE_HC_STAT_GEN_SEL_3 0x0000685c 3689#define BCE_HC_STAT_GEN_SEL_3_GEN_SEL_12 (0x7fL<<0) 3690#define BCE_HC_STAT_GEN_SEL_3_GEN_SEL_13 (0x7fL<<8) 3691#define BCE_HC_STAT_GEN_SEL_3_GEN_SEL_14 (0x7fL<<16) 3692#define BCE_HC_STAT_GEN_SEL_3_GEN_SEL_15 (0x7fL<<24) 3693 3694#define BCE_HC_STAT_GEN_STAT0 0x00006888 3695#define BCE_HC_STAT_GEN_STAT1 0x0000688c 3696#define BCE_HC_STAT_GEN_STAT2 0x00006890 3697#define BCE_HC_STAT_GEN_STAT3 0x00006894 3698#define BCE_HC_STAT_GEN_STAT4 0x00006898 3699#define BCE_HC_STAT_GEN_STAT5 0x0000689c 3700#define BCE_HC_STAT_GEN_STAT6 0x000068a0 3701#define BCE_HC_STAT_GEN_STAT7 0x000068a4 3702#define BCE_HC_STAT_GEN_STAT8 0x000068a8 3703#define BCE_HC_STAT_GEN_STAT9 0x000068ac 3704#define BCE_HC_STAT_GEN_STAT10 0x000068b0 3705#define BCE_HC_STAT_GEN_STAT11 0x000068b4 3706#define BCE_HC_STAT_GEN_STAT12 0x000068b8 3707#define BCE_HC_STAT_GEN_STAT13 0x000068bc 3708#define BCE_HC_STAT_GEN_STAT14 0x000068c0 3709#define BCE_HC_STAT_GEN_STAT15 0x000068c4 3710#define BCE_HC_STAT_GEN_STAT_AC0 0x000068c8 3711#define BCE_HC_STAT_GEN_STAT_AC1 0x000068cc 3712#define BCE_HC_STAT_GEN_STAT_AC2 0x000068d0 3713#define BCE_HC_STAT_GEN_STAT_AC3 0x000068d4 3714#define BCE_HC_STAT_GEN_STAT_AC4 0x000068d8 3715#define BCE_HC_STAT_GEN_STAT_AC5 0x000068dc 3716#define BCE_HC_STAT_GEN_STAT_AC6 0x000068e0 3717#define BCE_HC_STAT_GEN_STAT_AC7 0x000068e4 3718#define BCE_HC_STAT_GEN_STAT_AC8 0x000068e8 3719#define BCE_HC_STAT_GEN_STAT_AC9 0x000068ec 3720#define BCE_HC_STAT_GEN_STAT_AC10 0x000068f0 3721#define BCE_HC_STAT_GEN_STAT_AC11 0x000068f4 3722#define BCE_HC_STAT_GEN_STAT_AC12 0x000068f8 3723#define BCE_HC_STAT_GEN_STAT_AC13 0x000068fc 3724#define BCE_HC_STAT_GEN_STAT_AC14 0x00006900 3725#define BCE_HC_STAT_GEN_STAT_AC15 0x00006904 3726#define BCE_HC_VIS 0x00006908 3727#define BCE_HC_VIS_STAT_BUILD_STATE (0xfL<<0) 3728#define BCE_HC_VIS_STAT_BUILD_STATE_IDLE (0L<<0) 3729#define BCE_HC_VIS_STAT_BUILD_STATE_START (1L<<0) 3730#define BCE_HC_VIS_STAT_BUILD_STATE_REQUEST (2L<<0) 3731#define BCE_HC_VIS_STAT_BUILD_STATE_UPDATE64 (3L<<0) 3732#define BCE_HC_VIS_STAT_BUILD_STATE_UPDATE32 (4L<<0) 3733#define BCE_HC_VIS_STAT_BUILD_STATE_UPDATE_DONE (5L<<0) 3734#define BCE_HC_VIS_STAT_BUILD_STATE_DMA (6L<<0) 3735#define BCE_HC_VIS_STAT_BUILD_STATE_MSI_CONTROL (7L<<0) 3736#define BCE_HC_VIS_STAT_BUILD_STATE_MSI_LOW (8L<<0) 3737#define BCE_HC_VIS_STAT_BUILD_STATE_MSI_HIGH (9L<<0) 3738#define BCE_HC_VIS_STAT_BUILD_STATE_MSI_DATA (10L<<0) 3739#define BCE_HC_VIS_DMA_STAT_STATE (0xfL<<8) 3740#define BCE_HC_VIS_DMA_STAT_STATE_IDLE (0L<<8) 3741#define BCE_HC_VIS_DMA_STAT_STATE_STATUS_PARAM (1L<<8) 3742#define BCE_HC_VIS_DMA_STAT_STATE_STATUS_DMA (2L<<8) 3743#define BCE_HC_VIS_DMA_STAT_STATE_WRITE_COMP (3L<<8) 3744#define BCE_HC_VIS_DMA_STAT_STATE_COMP (4L<<8) 3745#define BCE_HC_VIS_DMA_STAT_STATE_STATISTIC_PARAM (5L<<8) 3746#define BCE_HC_VIS_DMA_STAT_STATE_STATISTIC_DMA (6L<<8) 3747#define BCE_HC_VIS_DMA_STAT_STATE_WRITE_COMP_1 (7L<<8) 3748#define BCE_HC_VIS_DMA_STAT_STATE_WRITE_COMP_2 (8L<<8) 3749#define BCE_HC_VIS_DMA_STAT_STATE_WAIT (9L<<8) 3750#define BCE_HC_VIS_DMA_STAT_STATE_ABORT (15L<<8) 3751#define BCE_HC_VIS_DMA_MSI_STATE (0x7L<<12) 3752#define BCE_HC_VIS_STATISTIC_DMA_EN_STATE (0x3L<<15) 3753#define BCE_HC_VIS_STATISTIC_DMA_EN_STATE_IDLE (0L<<15) 3754#define BCE_HC_VIS_STATISTIC_DMA_EN_STATE_COUNT (1L<<15) 3755#define BCE_HC_VIS_STATISTIC_DMA_EN_STATE_START (2L<<15) 3756 3757#define BCE_HC_VIS_1 0x0000690c 3758#define BCE_HC_VIS_1_HW_INTACK_STATE (1L<<4) 3759#define BCE_HC_VIS_1_HW_INTACK_STATE_IDLE (0L<<4) 3760#define BCE_HC_VIS_1_HW_INTACK_STATE_COUNT (1L<<4) 3761#define BCE_HC_VIS_1_SW_INTACK_STATE (1L<<5) 3762#define BCE_HC_VIS_1_SW_INTACK_STATE_IDLE (0L<<5) 3763#define BCE_HC_VIS_1_SW_INTACK_STATE_COUNT (1L<<5) 3764#define BCE_HC_VIS_1_DURING_SW_INTACK_STATE (1L<<6) 3765#define BCE_HC_VIS_1_DURING_SW_INTACK_STATE_IDLE (0L<<6) 3766#define BCE_HC_VIS_1_DURING_SW_INTACK_STATE_COUNT (1L<<6) 3767#define BCE_HC_VIS_1_MAILBOX_COUNT_STATE (1L<<7) 3768#define BCE_HC_VIS_1_MAILBOX_COUNT_STATE_IDLE (0L<<7) 3769#define BCE_HC_VIS_1_MAILBOX_COUNT_STATE_COUNT (1L<<7) 3770#define BCE_HC_VIS_1_RAM_RD_ARB_STATE (0xfL<<17) 3771#define BCE_HC_VIS_1_RAM_RD_ARB_STATE_IDLE (0L<<17) 3772#define BCE_HC_VIS_1_RAM_RD_ARB_STATE_DMA (1L<<17) 3773#define BCE_HC_VIS_1_RAM_RD_ARB_STATE_UPDATE (2L<<17) 3774#define BCE_HC_VIS_1_RAM_RD_ARB_STATE_ASSIGN (3L<<17) 3775#define BCE_HC_VIS_1_RAM_RD_ARB_STATE_WAIT (4L<<17) 3776#define BCE_HC_VIS_1_RAM_RD_ARB_STATE_REG_UPDATE (5L<<17) 3777#define BCE_HC_VIS_1_RAM_RD_ARB_STATE_REG_ASSIGN (6L<<17) 3778#define BCE_HC_VIS_1_RAM_RD_ARB_STATE_REG_WAIT (7L<<17) 3779#define BCE_HC_VIS_1_RAM_WR_ARB_STATE (0x3L<<21) 3780#define BCE_HC_VIS_1_RAM_WR_ARB_STATE_NORMAL (0L<<21) 3781#define BCE_HC_VIS_1_RAM_WR_ARB_STATE_CLEAR (1L<<21) 3782#define BCE_HC_VIS_1_INT_GEN_STATE (1L<<23) 3783#define BCE_HC_VIS_1_INT_GEN_STATE_DLE (0L<<23) 3784#define BCE_HC_VIS_1_INT_GEN_STATE_NTERRUPT (1L<<23) 3785#define BCE_HC_VIS_1_STAT_CHAN_ID (0x7L<<24) 3786#define BCE_HC_VIS_1_INT_B (1L<<27) 3787 3788#define BCE_HC_DEBUG_VECT_PEEK 0x00006910 3789#define BCE_HC_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) 3790#define BCE_HC_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) 3791#define BCE_HC_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) 3792#define BCE_HC_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) 3793#define BCE_HC_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) 3794#define BCE_HC_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) 3795 3796 3797 3798/* 3799 * txp_reg definition 3800 * offset: 0x40000 3801 */ 3802#define BCE_TXP_CPU_MODE 0x00045000 3803#define BCE_TXP_CPU_MODE_LOCAL_RST (1L<<0) 3804#define BCE_TXP_CPU_MODE_STEP_ENA (1L<<1) 3805#define BCE_TXP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2) 3806#define BCE_TXP_CPU_MODE_PAGE_0_INST_ENA (1L<<3) 3807#define BCE_TXP_CPU_MODE_MSG_BIT1 (1L<<6) 3808#define BCE_TXP_CPU_MODE_INTERRUPT_ENA (1L<<7) 3809#define BCE_TXP_CPU_MODE_SOFT_HALT (1L<<10) 3810#define BCE_TXP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11) 3811#define BCE_TXP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12) 3812#define BCE_TXP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13) 3813#define BCE_TXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15) 3814 3815#define BCE_TXP_CPU_STATE 0x00045004 3816#define BCE_TXP_CPU_STATE_BREAKPOINT (1L<<0) 3817#define BCE_TXP_CPU_STATE_BAD_INST_HALTED (1L<<2) 3818#define BCE_TXP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) 3819#define BCE_TXP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) 3820#define BCE_TXP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) 3821#define BCE_TXP_CPU_STATE_BAD_pc_HALTED (1L<<6) 3822#define BCE_TXP_CPU_STATE_ALIGN_HALTED (1L<<7) 3823#define BCE_TXP_CPU_STATE_FIO_ABORT_HALTED (1L<<8) 3824#define BCE_TXP_CPU_STATE_SOFT_HALTED (1L<<10) 3825#define BCE_TXP_CPU_STATE_SPAD_UNDERFLOW (1L<<11) 3826#define BCE_TXP_CPU_STATE_INTERRRUPT (1L<<12) 3827#define BCE_TXP_CPU_STATE_DATA_ACCESS_STALL (1L<<14) 3828#define BCE_TXP_CPU_STATE_INST_FETCH_STALL (1L<<15) 3829#define BCE_TXP_CPU_STATE_BLOCKED_READ (1L<<31) 3830 3831#define BCE_TXP_CPU_EVENT_MASK 0x00045008 3832#define BCE_TXP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) 3833#define BCE_TXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2) 3834#define BCE_TXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3) 3835#define BCE_TXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4) 3836#define BCE_TXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5) 3837#define BCE_TXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6) 3838#define BCE_TXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7) 3839#define BCE_TXP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8) 3840#define BCE_TXP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10) 3841#define BCE_TXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11) 3842#define BCE_TXP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12) 3843 3844#define BCE_TXP_CPU_PROGRAM_COUNTER 0x0004501c 3845#define BCE_TXP_CPU_INSTRUCTION 0x00045020 3846#define BCE_TXP_CPU_DATA_ACCESS 0x00045024 3847#define BCE_TXP_CPU_INTERRUPT_ENABLE 0x00045028 3848#define BCE_TXP_CPU_INTERRUPT_VECTOR 0x0004502c 3849#define BCE_TXP_CPU_INTERRUPT_SAVED_PC 0x00045030 3850#define BCE_TXP_CPU_HW_BREAKPOINT 0x00045034 3851#define BCE_TXP_CPU_HW_BREAKPOINT_DISABLE (1L<<0) 3852#define BCE_TXP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2) 3853 3854#define BCE_TXP_CPU_DEBUG_VECT_PEEK 0x00045038 3855#define BCE_TXP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) 3856#define BCE_TXP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) 3857#define BCE_TXP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) 3858#define BCE_TXP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) 3859#define BCE_TXP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) 3860#define BCE_TXP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) 3861 3862#define BCE_TXP_CPU_LAST_BRANCH_ADDR 0x00045048 3863#define BCE_TXP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1) 3864#define BCE_TXP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1) 3865#define BCE_TXP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1) 3866#define BCE_TXP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2) 3867 3868#define BCE_TXP_CPU_REG_FILE 0x00045200 3869#define BCE_TXP_FTQ_DATA 0x000453c0 3870#define BCE_TXP_FTQ_CMD 0x000453f8 3871#define BCE_TXP_FTQ_CMD_OFFSET (0x3ffL<<0) 3872#define BCE_TXP_FTQ_CMD_WR_TOP (1L<<10) 3873#define BCE_TXP_FTQ_CMD_WR_TOP_0 (0L<<10) 3874#define BCE_TXP_FTQ_CMD_WR_TOP_1 (1L<<10) 3875#define BCE_TXP_FTQ_CMD_SFT_RESET (1L<<25) 3876#define BCE_TXP_FTQ_CMD_RD_DATA (1L<<26) 3877#define BCE_TXP_FTQ_CMD_ADD_INTERVEN (1L<<27) 3878#define BCE_TXP_FTQ_CMD_ADD_DATA (1L<<28) 3879#define BCE_TXP_FTQ_CMD_INTERVENE_CLR (1L<<29) 3880#define BCE_TXP_FTQ_CMD_POP (1L<<30) 3881#define BCE_TXP_FTQ_CMD_BUSY (1L<<31) 3882 3883#define BCE_TXP_FTQ_CTL 0x000453fc 3884#define BCE_TXP_FTQ_CTL_INTERVENE (1L<<0) 3885#define BCE_TXP_FTQ_CTL_OVERFLOW (1L<<1) 3886#define BCE_TXP_FTQ_CTL_FORCE_INTERVENE (1L<<2) 3887#define BCE_TXP_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 3888#define BCE_TXP_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 3889 3890#define BCE_TXP_SCRATCH 0x00060000 3891 3892 3893/* 3894 * tpat_reg definition 3895 * offset: 0x80000 3896 */ 3897#define BCE_TPAT_CPU_MODE 0x00085000 3898#define BCE_TPAT_CPU_MODE_LOCAL_RST (1L<<0) 3899#define BCE_TPAT_CPU_MODE_STEP_ENA (1L<<1) 3900#define BCE_TPAT_CPU_MODE_PAGE_0_DATA_ENA (1L<<2) 3901#define BCE_TPAT_CPU_MODE_PAGE_0_INST_ENA (1L<<3) 3902#define BCE_TPAT_CPU_MODE_MSG_BIT1 (1L<<6) 3903#define BCE_TPAT_CPU_MODE_INTERRUPT_ENA (1L<<7) 3904#define BCE_TPAT_CPU_MODE_SOFT_HALT (1L<<10) 3905#define BCE_TPAT_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11) 3906#define BCE_TPAT_CPU_MODE_BAD_INST_HALT_ENA (1L<<12) 3907#define BCE_TPAT_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13) 3908#define BCE_TPAT_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15) 3909 3910#define BCE_TPAT_CPU_STATE 0x00085004 3911#define BCE_TPAT_CPU_STATE_BREAKPOINT (1L<<0) 3912#define BCE_TPAT_CPU_STATE_BAD_INST_HALTED (1L<<2) 3913#define BCE_TPAT_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) 3914#define BCE_TPAT_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) 3915#define BCE_TPAT_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) 3916#define BCE_TPAT_CPU_STATE_BAD_pc_HALTED (1L<<6) 3917#define BCE_TPAT_CPU_STATE_ALIGN_HALTED (1L<<7) 3918#define BCE_TPAT_CPU_STATE_FIO_ABORT_HALTED (1L<<8) 3919#define BCE_TPAT_CPU_STATE_SOFT_HALTED (1L<<10) 3920#define BCE_TPAT_CPU_STATE_SPAD_UNDERFLOW (1L<<11) 3921#define BCE_TPAT_CPU_STATE_INTERRRUPT (1L<<12) 3922#define BCE_TPAT_CPU_STATE_DATA_ACCESS_STALL (1L<<14) 3923#define BCE_TPAT_CPU_STATE_INST_FETCH_STALL (1L<<15) 3924#define BCE_TPAT_CPU_STATE_BLOCKED_READ (1L<<31) 3925 3926#define BCE_TPAT_CPU_EVENT_MASK 0x00085008 3927#define BCE_TPAT_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) 3928#define BCE_TPAT_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2) 3929#define BCE_TPAT_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3) 3930#define BCE_TPAT_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4) 3931#define BCE_TPAT_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5) 3932#define BCE_TPAT_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6) 3933#define BCE_TPAT_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7) 3934#define BCE_TPAT_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8) 3935#define BCE_TPAT_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10) 3936#define BCE_TPAT_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11) 3937#define BCE_TPAT_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12) 3938 3939#define BCE_TPAT_CPU_PROGRAM_COUNTER 0x0008501c 3940#define BCE_TPAT_CPU_INSTRUCTION 0x00085020 3941#define BCE_TPAT_CPU_DATA_ACCESS 0x00085024 3942#define BCE_TPAT_CPU_INTERRUPT_ENABLE 0x00085028 3943#define BCE_TPAT_CPU_INTERRUPT_VECTOR 0x0008502c 3944#define BCE_TPAT_CPU_INTERRUPT_SAVED_PC 0x00085030 3945#define BCE_TPAT_CPU_HW_BREAKPOINT 0x00085034 3946#define BCE_TPAT_CPU_HW_BREAKPOINT_DISABLE (1L<<0) 3947#define BCE_TPAT_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2) 3948 3949#define BCE_TPAT_CPU_DEBUG_VECT_PEEK 0x00085038 3950#define BCE_TPAT_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) 3951#define BCE_TPAT_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) 3952#define BCE_TPAT_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) 3953#define BCE_TPAT_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) 3954#define BCE_TPAT_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) 3955#define BCE_TPAT_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) 3956 3957#define BCE_TPAT_CPU_LAST_BRANCH_ADDR 0x00085048 3958#define BCE_TPAT_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1) 3959#define BCE_TPAT_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1) 3960#define BCE_TPAT_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1) 3961#define BCE_TPAT_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2) 3962 3963#define BCE_TPAT_CPU_REG_FILE 0x00085200 3964#define BCE_TPAT_FTQ_DATA 0x000853c0 3965#define BCE_TPAT_FTQ_CMD 0x000853f8 3966#define BCE_TPAT_FTQ_CMD_OFFSET (0x3ffL<<0) 3967#define BCE_TPAT_FTQ_CMD_WR_TOP (1L<<10) 3968#define BCE_TPAT_FTQ_CMD_WR_TOP_0 (0L<<10) 3969#define BCE_TPAT_FTQ_CMD_WR_TOP_1 (1L<<10) 3970#define BCE_TPAT_FTQ_CMD_SFT_RESET (1L<<25) 3971#define BCE_TPAT_FTQ_CMD_RD_DATA (1L<<26) 3972#define BCE_TPAT_FTQ_CMD_ADD_INTERVEN (1L<<27) 3973#define BCE_TPAT_FTQ_CMD_ADD_DATA (1L<<28) 3974#define BCE_TPAT_FTQ_CMD_INTERVENE_CLR (1L<<29) 3975#define BCE_TPAT_FTQ_CMD_POP (1L<<30) 3976#define BCE_TPAT_FTQ_CMD_BUSY (1L<<31) 3977 3978#define BCE_TPAT_FTQ_CTL 0x000853fc 3979#define BCE_TPAT_FTQ_CTL_INTERVENE (1L<<0) 3980#define BCE_TPAT_FTQ_CTL_OVERFLOW (1L<<1) 3981#define BCE_TPAT_FTQ_CTL_FORCE_INTERVENE (1L<<2) 3982#define BCE_TPAT_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 3983#define BCE_TPAT_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 3984 3985#define BCE_TPAT_SCRATCH 0x000a0000 3986 3987 3988/* 3989 * rxp_reg definition 3990 * offset: 0xc0000 3991 */ 3992#define BCE_RXP_CPU_MODE 0x000c5000 3993#define BCE_RXP_CPU_MODE_LOCAL_RST (1L<<0) 3994#define BCE_RXP_CPU_MODE_STEP_ENA (1L<<1) 3995#define BCE_RXP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2) 3996#define BCE_RXP_CPU_MODE_PAGE_0_INST_ENA (1L<<3) 3997#define BCE_RXP_CPU_MODE_MSG_BIT1 (1L<<6) 3998#define BCE_RXP_CPU_MODE_INTERRUPT_ENA (1L<<7) 3999#define BCE_RXP_CPU_MODE_SOFT_HALT (1L<<10) 4000#define BCE_RXP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11) 4001#define BCE_RXP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12) 4002#define BCE_RXP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13) 4003#define BCE_RXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15) 4004 4005#define BCE_RXP_CPU_STATE 0x000c5004 4006#define BCE_RXP_CPU_STATE_BREAKPOINT (1L<<0) 4007#define BCE_RXP_CPU_STATE_BAD_INST_HALTED (1L<<2) 4008#define BCE_RXP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) 4009#define BCE_RXP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) 4010#define BCE_RXP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) 4011#define BCE_RXP_CPU_STATE_BAD_pc_HALTED (1L<<6) 4012#define BCE_RXP_CPU_STATE_ALIGN_HALTED (1L<<7) 4013#define BCE_RXP_CPU_STATE_FIO_ABORT_HALTED (1L<<8) 4014#define BCE_RXP_CPU_STATE_SOFT_HALTED (1L<<10) 4015#define BCE_RXP_CPU_STATE_SPAD_UNDERFLOW (1L<<11) 4016#define BCE_RXP_CPU_STATE_INTERRRUPT (1L<<12) 4017#define BCE_RXP_CPU_STATE_DATA_ACCESS_STALL (1L<<14) 4018#define BCE_RXP_CPU_STATE_INST_FETCH_STALL (1L<<15) 4019#define BCE_RXP_CPU_STATE_BLOCKED_READ (1L<<31) 4020 4021#define BCE_RXP_CPU_EVENT_MASK 0x000c5008 4022#define BCE_RXP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) 4023#define BCE_RXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2) 4024#define BCE_RXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3) 4025#define BCE_RXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4) 4026#define BCE_RXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5) 4027#define BCE_RXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6) 4028#define BCE_RXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7) 4029#define BCE_RXP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8) 4030#define BCE_RXP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10) 4031#define BCE_RXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11) 4032#define BCE_RXP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12) 4033 4034#define BCE_RXP_CPU_PROGRAM_COUNTER 0x000c501c 4035#define BCE_RXP_CPU_INSTRUCTION 0x000c5020 4036#define BCE_RXP_CPU_DATA_ACCESS 0x000c5024 4037#define BCE_RXP_CPU_INTERRUPT_ENABLE 0x000c5028 4038#define BCE_RXP_CPU_INTERRUPT_VECTOR 0x000c502c 4039#define BCE_RXP_CPU_INTERRUPT_SAVED_PC 0x000c5030 4040#define BCE_RXP_CPU_HW_BREAKPOINT 0x000c5034 4041#define BCE_RXP_CPU_HW_BREAKPOINT_DISABLE (1L<<0) 4042#define BCE_RXP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2) 4043 4044#define BCE_RXP_CPU_DEBUG_VECT_PEEK 0x000c5038 4045#define BCE_RXP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) 4046#define BCE_RXP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) 4047#define BCE_RXP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) 4048#define BCE_RXP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) 4049#define BCE_RXP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) 4050#define BCE_RXP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) 4051 4052#define BCE_RXP_CPU_LAST_BRANCH_ADDR 0x000c5048 4053#define BCE_RXP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1) 4054#define BCE_RXP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1) 4055#define BCE_RXP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1) 4056#define BCE_RXP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2) 4057 4058#define BCE_RXP_CPU_REG_FILE 0x000c5200 4059#define BCE_RXP_CFTQ_DATA 0x000c5380 4060#define BCE_RXP_CFTQ_CMD 0x000c53b8 4061#define BCE_RXP_CFTQ_CMD_OFFSET (0x3ffL<<0) 4062#define BCE_RXP_CFTQ_CMD_WR_TOP (1L<<10) 4063#define BCE_RXP_CFTQ_CMD_WR_TOP_0 (0L<<10) 4064#define BCE_RXP_CFTQ_CMD_WR_TOP_1 (1L<<10) 4065#define BCE_RXP_CFTQ_CMD_SFT_RESET (1L<<25) 4066#define BCE_RXP_CFTQ_CMD_RD_DATA (1L<<26) 4067#define BCE_RXP_CFTQ_CMD_ADD_INTERVEN (1L<<27) 4068#define BCE_RXP_CFTQ_CMD_ADD_DATA (1L<<28) 4069#define BCE_RXP_CFTQ_CMD_INTERVENE_CLR (1L<<29) 4070#define BCE_RXP_CFTQ_CMD_POP (1L<<30) 4071#define BCE_RXP_CFTQ_CMD_BUSY (1L<<31) 4072 4073#define BCE_RXP_CFTQ_CTL 0x000c53bc 4074#define BCE_RXP_CFTQ_CTL_INTERVENE (1L<<0) 4075#define BCE_RXP_CFTQ_CTL_OVERFLOW (1L<<1) 4076#define BCE_RXP_CFTQ_CTL_FORCE_INTERVENE (1L<<2) 4077#define BCE_RXP_CFTQ_CTL_MAX_DEPTH (0x3ffL<<12) 4078#define BCE_RXP_CFTQ_CTL_CUR_DEPTH (0x3ffL<<22) 4079 4080#define BCE_RXP_FTQ_DATA 0x000c53c0 4081#define BCE_RXP_FTQ_CMD 0x000c53f8 4082#define BCE_RXP_FTQ_CMD_OFFSET (0x3ffL<<0) 4083#define BCE_RXP_FTQ_CMD_WR_TOP (1L<<10) 4084#define BCE_RXP_FTQ_CMD_WR_TOP_0 (0L<<10) 4085#define BCE_RXP_FTQ_CMD_WR_TOP_1 (1L<<10) 4086#define BCE_RXP_FTQ_CMD_SFT_RESET (1L<<25) 4087#define BCE_RXP_FTQ_CMD_RD_DATA (1L<<26) 4088#define BCE_RXP_FTQ_CMD_ADD_INTERVEN (1L<<27) 4089#define BCE_RXP_FTQ_CMD_ADD_DATA (1L<<28) 4090#define BCE_RXP_FTQ_CMD_INTERVENE_CLR (1L<<29) 4091#define BCE_RXP_FTQ_CMD_POP (1L<<30) 4092#define BCE_RXP_FTQ_CMD_BUSY (1L<<31) 4093 4094#define BCE_RXP_FTQ_CTL 0x000c53fc 4095#define BCE_RXP_FTQ_CTL_INTERVENE (1L<<0) 4096#define BCE_RXP_FTQ_CTL_OVERFLOW (1L<<1) 4097#define BCE_RXP_FTQ_CTL_FORCE_INTERVENE (1L<<2) 4098#define BCE_RXP_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 4099#define BCE_RXP_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 4100 4101#define BCE_RXP_SCRATCH 0x000e0000 4102 4103 4104/* 4105 * com_reg definition 4106 * offset: 0x100000 4107 */ 4108#define BCE_COM_CPU_MODE 0x00105000 4109#define BCE_COM_CPU_MODE_LOCAL_RST (1L<<0) 4110#define BCE_COM_CPU_MODE_STEP_ENA (1L<<1) 4111#define BCE_COM_CPU_MODE_PAGE_0_DATA_ENA (1L<<2) 4112#define BCE_COM_CPU_MODE_PAGE_0_INST_ENA (1L<<3) 4113#define BCE_COM_CPU_MODE_MSG_BIT1 (1L<<6) 4114#define BCE_COM_CPU_MODE_INTERRUPT_ENA (1L<<7) 4115#define BCE_COM_CPU_MODE_SOFT_HALT (1L<<10) 4116#define BCE_COM_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11) 4117#define BCE_COM_CPU_MODE_BAD_INST_HALT_ENA (1L<<12) 4118#define BCE_COM_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13) 4119#define BCE_COM_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15) 4120 4121#define BCE_COM_CPU_STATE 0x00105004 4122#define BCE_COM_CPU_STATE_BREAKPOINT (1L<<0) 4123#define BCE_COM_CPU_STATE_BAD_INST_HALTED (1L<<2) 4124#define BCE_COM_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) 4125#define BCE_COM_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) 4126#define BCE_COM_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) 4127#define BCE_COM_CPU_STATE_BAD_pc_HALTED (1L<<6) 4128#define BCE_COM_CPU_STATE_ALIGN_HALTED (1L<<7) 4129#define BCE_COM_CPU_STATE_FIO_ABORT_HALTED (1L<<8) 4130#define BCE_COM_CPU_STATE_SOFT_HALTED (1L<<10) 4131#define BCE_COM_CPU_STATE_SPAD_UNDERFLOW (1L<<11) 4132#define BCE_COM_CPU_STATE_INTERRRUPT (1L<<12) 4133#define BCE_COM_CPU_STATE_DATA_ACCESS_STALL (1L<<14) 4134#define BCE_COM_CPU_STATE_INST_FETCH_STALL (1L<<15) 4135#define BCE_COM_CPU_STATE_BLOCKED_READ (1L<<31) 4136 4137#define BCE_COM_CPU_EVENT_MASK 0x00105008 4138#define BCE_COM_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) 4139#define BCE_COM_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2) 4140#define BCE_COM_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3) 4141#define BCE_COM_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4) 4142#define BCE_COM_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5) 4143#define BCE_COM_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6) 4144#define BCE_COM_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7) 4145#define BCE_COM_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8) 4146#define BCE_COM_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10) 4147#define BCE_COM_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11) 4148#define BCE_COM_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12) 4149 4150#define BCE_COM_CPU_PROGRAM_COUNTER 0x0010501c 4151#define BCE_COM_CPU_INSTRUCTION 0x00105020 4152#define BCE_COM_CPU_DATA_ACCESS 0x00105024 4153#define BCE_COM_CPU_INTERRUPT_ENABLE 0x00105028 4154#define BCE_COM_CPU_INTERRUPT_VECTOR 0x0010502c 4155#define BCE_COM_CPU_INTERRUPT_SAVED_PC 0x00105030 4156#define BCE_COM_CPU_HW_BREAKPOINT 0x00105034 4157#define BCE_COM_CPU_HW_BREAKPOINT_DISABLE (1L<<0) 4158#define BCE_COM_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2) 4159 4160#define BCE_COM_CPU_DEBUG_VECT_PEEK 0x00105038 4161#define BCE_COM_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) 4162#define BCE_COM_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) 4163#define BCE_COM_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) 4164#define BCE_COM_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) 4165#define BCE_COM_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) 4166#define BCE_COM_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) 4167 4168#define BCE_COM_CPU_LAST_BRANCH_ADDR 0x00105048 4169#define BCE_COM_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1) 4170#define BCE_COM_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1) 4171#define BCE_COM_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1) 4172#define BCE_COM_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2) 4173 4174#define BCE_COM_CPU_REG_FILE 0x00105200 4175#define BCE_COM_COMXQ_FTQ_DATA 0x00105340 4176#define BCE_COM_COMXQ_FTQ_CMD 0x00105378 4177#define BCE_COM_COMXQ_FTQ_CMD_OFFSET (0x3ffL<<0) 4178#define BCE_COM_COMXQ_FTQ_CMD_WR_TOP (1L<<10) 4179#define BCE_COM_COMXQ_FTQ_CMD_WR_TOP_0 (0L<<10) 4180#define BCE_COM_COMXQ_FTQ_CMD_WR_TOP_1 (1L<<10) 4181#define BCE_COM_COMXQ_FTQ_CMD_SFT_RESET (1L<<25) 4182#define BCE_COM_COMXQ_FTQ_CMD_RD_DATA (1L<<26) 4183#define BCE_COM_COMXQ_FTQ_CMD_ADD_INTERVEN (1L<<27) 4184#define BCE_COM_COMXQ_FTQ_CMD_ADD_DATA (1L<<28) 4185#define BCE_COM_COMXQ_FTQ_CMD_INTERVENE_CLR (1L<<29) 4186#define BCE_COM_COMXQ_FTQ_CMD_POP (1L<<30) 4187#define BCE_COM_COMXQ_FTQ_CMD_BUSY (1L<<31) 4188 4189#define BCE_COM_COMXQ_FTQ_CTL 0x0010537c 4190#define BCE_COM_COMXQ_FTQ_CTL_INTERVENE (1L<<0) 4191#define BCE_COM_COMXQ_FTQ_CTL_OVERFLOW (1L<<1) 4192#define BCE_COM_COMXQ_FTQ_CTL_FORCE_INTERVENE (1L<<2) 4193#define BCE_COM_COMXQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 4194#define BCE_COM_COMXQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 4195 4196#define BCE_COM_COMTQ_FTQ_DATA 0x00105380 4197#define BCE_COM_COMTQ_FTQ_CMD 0x001053b8 4198#define BCE_COM_COMTQ_FTQ_CMD_OFFSET (0x3ffL<<0) 4199#define BCE_COM_COMTQ_FTQ_CMD_WR_TOP (1L<<10) 4200#define BCE_COM_COMTQ_FTQ_CMD_WR_TOP_0 (0L<<10) 4201#define BCE_COM_COMTQ_FTQ_CMD_WR_TOP_1 (1L<<10) 4202#define BCE_COM_COMTQ_FTQ_CMD_SFT_RESET (1L<<25) 4203#define BCE_COM_COMTQ_FTQ_CMD_RD_DATA (1L<<26) 4204#define BCE_COM_COMTQ_FTQ_CMD_ADD_INTERVEN (1L<<27) 4205#define BCE_COM_COMTQ_FTQ_CMD_ADD_DATA (1L<<28) 4206#define BCE_COM_COMTQ_FTQ_CMD_INTERVENE_CLR (1L<<29) 4207#define BCE_COM_COMTQ_FTQ_CMD_POP (1L<<30) 4208#define BCE_COM_COMTQ_FTQ_CMD_BUSY (1L<<31) 4209 4210#define BCE_COM_COMTQ_FTQ_CTL 0x001053bc 4211#define BCE_COM_COMTQ_FTQ_CTL_INTERVENE (1L<<0) 4212#define BCE_COM_COMTQ_FTQ_CTL_OVERFLOW (1L<<1) 4213#define BCE_COM_COMTQ_FTQ_CTL_FORCE_INTERVENE (1L<<2) 4214#define BCE_COM_COMTQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 4215#define BCE_COM_COMTQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 4216 4217#define BCE_COM_COMQ_FTQ_DATA 0x001053c0 4218#define BCE_COM_COMQ_FTQ_CMD 0x001053f8 4219#define BCE_COM_COMQ_FTQ_CMD_OFFSET (0x3ffL<<0) 4220#define BCE_COM_COMQ_FTQ_CMD_WR_TOP (1L<<10) 4221#define BCE_COM_COMQ_FTQ_CMD_WR_TOP_0 (0L<<10) 4222#define BCE_COM_COMQ_FTQ_CMD_WR_TOP_1 (1L<<10) 4223#define BCE_COM_COMQ_FTQ_CMD_SFT_RESET (1L<<25) 4224#define BCE_COM_COMQ_FTQ_CMD_RD_DATA (1L<<26) 4225#define BCE_COM_COMQ_FTQ_CMD_ADD_INTERVEN (1L<<27) 4226#define BCE_COM_COMQ_FTQ_CMD_ADD_DATA (1L<<28) 4227#define BCE_COM_COMQ_FTQ_CMD_INTERVENE_CLR (1L<<29) 4228#define BCE_COM_COMQ_FTQ_CMD_POP (1L<<30) 4229#define BCE_COM_COMQ_FTQ_CMD_BUSY (1L<<31) 4230 4231#define BCE_COM_COMQ_FTQ_CTL 0x001053fc 4232#define BCE_COM_COMQ_FTQ_CTL_INTERVENE (1L<<0) 4233#define BCE_COM_COMQ_FTQ_CTL_OVERFLOW (1L<<1) 4234#define BCE_COM_COMQ_FTQ_CTL_FORCE_INTERVENE (1L<<2) 4235#define BCE_COM_COMQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 4236#define BCE_COM_COMQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 4237 4238#define BCE_COM_SCRATCH 0x00120000 4239 4240 4241/* 4242 * cp_reg definition 4243 * offset: 0x180000 4244 */ 4245#define BCE_CP_CPU_MODE 0x00185000 4246#define BCE_CP_CPU_MODE_LOCAL_RST (1L<<0) 4247#define BCE_CP_CPU_MODE_STEP_ENA (1L<<1) 4248#define BCE_CP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2) 4249#define BCE_CP_CPU_MODE_PAGE_0_INST_ENA (1L<<3) 4250#define BCE_CP_CPU_MODE_MSG_BIT1 (1L<<6) 4251#define BCE_CP_CPU_MODE_INTERRUPT_ENA (1L<<7) 4252#define BCE_CP_CPU_MODE_SOFT_HALT (1L<<10) 4253#define BCE_CP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11) 4254#define BCE_CP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12) 4255#define BCE_CP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13) 4256#define BCE_CP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15) 4257 4258#define BCE_CP_CPU_STATE 0x00185004 4259#define BCE_CP_CPU_STATE_BREAKPOINT (1L<<0) 4260#define BCE_CP_CPU_STATE_BAD_INST_HALTED (1L<<2) 4261#define BCE_CP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) 4262#define BCE_CP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) 4263#define BCE_CP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) 4264#define BCE_CP_CPU_STATE_BAD_pc_HALTED (1L<<6) 4265#define BCE_CP_CPU_STATE_ALIGN_HALTED (1L<<7) 4266#define BCE_CP_CPU_STATE_FIO_ABORT_HALTED (1L<<8) 4267#define BCE_CP_CPU_STATE_SOFT_HALTED (1L<<10) 4268#define BCE_CP_CPU_STATE_SPAD_UNDERFLOW (1L<<11) 4269#define BCE_CP_CPU_STATE_INTERRRUPT (1L<<12) 4270#define BCE_CP_CPU_STATE_DATA_ACCESS_STALL (1L<<14) 4271#define BCE_CP_CPU_STATE_INST_FETCH_STALL (1L<<15) 4272#define BCE_CP_CPU_STATE_BLOCKED_READ (1L<<31) 4273 4274#define BCE_CP_CPU_EVENT_MASK 0x00185008 4275#define BCE_CP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) 4276#define BCE_CP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2) 4277#define BCE_CP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3) 4278#define BCE_CP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4) 4279#define BCE_CP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5) 4280#define BCE_CP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6) 4281#define BCE_CP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7) 4282#define BCE_CP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8) 4283#define BCE_CP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10) 4284#define BCE_CP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11) 4285#define BCE_CP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12) 4286 4287#define BCE_CP_CPU_PROGRAM_COUNTER 0x0018501c 4288#define BCE_CP_CPU_INSTRUCTION 0x00185020 4289#define BCE_CP_CPU_DATA_ACCESS 0x00185024 4290#define BCE_CP_CPU_INTERRUPT_ENABLE 0x00185028 4291#define BCE_CP_CPU_INTERRUPT_VECTOR 0x0018502c 4292#define BCE_CP_CPU_INTERRUPT_SAVED_PC 0x00185030 4293#define BCE_CP_CPU_HW_BREAKPOINT 0x00185034 4294#define BCE_CP_CPU_HW_BREAKPOINT_DISABLE (1L<<0) 4295#define BCE_CP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2) 4296 4297#define BCE_CP_CPU_DEBUG_VECT_PEEK 0x00185038 4298#define BCE_CP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) 4299#define BCE_CP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) 4300#define BCE_CP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) 4301#define BCE_CP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) 4302#define BCE_CP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) 4303#define BCE_CP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) 4304 4305#define BCE_CP_CPU_LAST_BRANCH_ADDR 0x00185048 4306#define BCE_CP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1) 4307#define BCE_CP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1) 4308#define BCE_CP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1) 4309#define BCE_CP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2) 4310 4311#define BCE_CP_CPU_REG_FILE 0x00185200 4312#define BCE_CP_CPQ_FTQ_DATA 0x001853c0 4313#define BCE_CP_CPQ_FTQ_CMD 0x001853f8 4314#define BCE_CP_CPQ_FTQ_CMD_OFFSET (0x3ffL<<0) 4315#define BCE_CP_CPQ_FTQ_CMD_WR_TOP (1L<<10) 4316#define BCE_CP_CPQ_FTQ_CMD_WR_TOP_0 (0L<<10) 4317#define BCE_CP_CPQ_FTQ_CMD_WR_TOP_1 (1L<<10) 4318#define BCE_CP_CPQ_FTQ_CMD_SFT_RESET (1L<<25) 4319#define BCE_CP_CPQ_FTQ_CMD_RD_DATA (1L<<26) 4320#define BCE_CP_CPQ_FTQ_CMD_ADD_INTERVEN (1L<<27) 4321#define BCE_CP_CPQ_FTQ_CMD_ADD_DATA (1L<<28) 4322#define BCE_CP_CPQ_FTQ_CMD_INTERVENE_CLR (1L<<29) 4323#define BCE_CP_CPQ_FTQ_CMD_POP (1L<<30) 4324#define BCE_CP_CPQ_FTQ_CMD_BUSY (1L<<31) 4325 4326#define BCE_CP_CPQ_FTQ_CTL 0x001853fc 4327#define BCE_CP_CPQ_FTQ_CTL_INTERVENE (1L<<0) 4328#define BCE_CP_CPQ_FTQ_CTL_OVERFLOW (1L<<1) 4329#define BCE_CP_CPQ_FTQ_CTL_FORCE_INTERVENE (1L<<2) 4330#define BCE_CP_CPQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 4331#define BCE_CP_CPQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 4332 4333#define BCE_CP_SCRATCH 0x001a0000 4334 4335 4336/* 4337 * mcp_reg definition 4338 * offset: 0x140000 4339 */ 4340#define BCE_MCP_CPU_MODE 0x00145000 4341#define BCE_MCP_CPU_MODE_LOCAL_RST (1L<<0) 4342#define BCE_MCP_CPU_MODE_STEP_ENA (1L<<1) 4343#define BCE_MCP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2) 4344#define BCE_MCP_CPU_MODE_PAGE_0_INST_ENA (1L<<3) 4345#define BCE_MCP_CPU_MODE_MSG_BIT1 (1L<<6) 4346#define BCE_MCP_CPU_MODE_INTERRUPT_ENA (1L<<7) 4347#define BCE_MCP_CPU_MODE_SOFT_HALT (1L<<10) 4348#define BCE_MCP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11) 4349#define BCE_MCP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12) 4350#define BCE_MCP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13) 4351#define BCE_MCP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15) 4352 4353#define BCE_MCP_CPU_STATE 0x00145004 4354#define BCE_MCP_CPU_STATE_BREAKPOINT (1L<<0) 4355#define BCE_MCP_CPU_STATE_BAD_INST_HALTED (1L<<2) 4356#define BCE_MCP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) 4357#define BCE_MCP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) 4358#define BCE_MCP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) 4359#define BCE_MCP_CPU_STATE_BAD_pc_HALTED (1L<<6) 4360#define BCE_MCP_CPU_STATE_ALIGN_HALTED (1L<<7) 4361#define BCE_MCP_CPU_STATE_FIO_ABORT_HALTED (1L<<8) 4362#define BCE_MCP_CPU_STATE_SOFT_HALTED (1L<<10) 4363#define BCE_MCP_CPU_STATE_SPAD_UNDERFLOW (1L<<11) 4364#define BCE_MCP_CPU_STATE_INTERRRUPT (1L<<12) 4365#define BCE_MCP_CPU_STATE_DATA_ACCESS_STALL (1L<<14) 4366#define BCE_MCP_CPU_STATE_INST_FETCH_STALL (1L<<15) 4367#define BCE_MCP_CPU_STATE_BLOCKED_READ (1L<<31) 4368 4369#define BCE_MCP_CPU_EVENT_MASK 0x00145008 4370#define BCE_MCP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) 4371#define BCE_MCP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2) 4372#define BCE_MCP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3) 4373#define BCE_MCP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4) 4374#define BCE_MCP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5) 4375#define BCE_MCP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6) 4376#define BCE_MCP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7) 4377#define BCE_MCP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8) 4378#define BCE_MCP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10) 4379#define BCE_MCP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11) 4380#define BCE_MCP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12) 4381 4382#define BCE_MCP_CPU_PROGRAM_COUNTER 0x0014501c 4383#define BCE_MCP_CPU_INSTRUCTION 0x00145020 4384#define BCE_MCP_CPU_DATA_ACCESS 0x00145024 4385#define BCE_MCP_CPU_INTERRUPT_ENABLE 0x00145028 4386#define BCE_MCP_CPU_INTERRUPT_VECTOR 0x0014502c 4387#define BCE_MCP_CPU_INTERRUPT_SAVED_PC 0x00145030 4388#define BCE_MCP_CPU_HW_BREAKPOINT 0x00145034 4389#define BCE_MCP_CPU_HW_BREAKPOINT_DISABLE (1L<<0) 4390#define BCE_MCP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2) 4391 4392#define BCE_MCP_CPU_DEBUG_VECT_PEEK 0x00145038 4393#define BCE_MCP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) 4394#define BCE_MCP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) 4395#define BCE_MCP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) 4396#define BCE_MCP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) 4397#define BCE_MCP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) 4398#define BCE_MCP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) 4399 4400#define BCE_MCP_CPU_LAST_BRANCH_ADDR 0x00145048 4401#define BCE_MCP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1) 4402#define BCE_MCP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1) 4403#define BCE_MCP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1) 4404#define BCE_MCP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2) 4405 4406#define BCE_MCP_CPU_REG_FILE 0x00145200 4407#define BCE_MCP_MCPQ_FTQ_DATA 0x001453c0 4408#define BCE_MCP_MCPQ_FTQ_CMD 0x001453f8 4409#define BCE_MCP_MCPQ_FTQ_CMD_OFFSET (0x3ffL<<0) 4410#define BCE_MCP_MCPQ_FTQ_CMD_WR_TOP (1L<<10) 4411#define BCE_MCP_MCPQ_FTQ_CMD_WR_TOP_0 (0L<<10) 4412#define BCE_MCP_MCPQ_FTQ_CMD_WR_TOP_1 (1L<<10) 4413#define BCE_MCP_MCPQ_FTQ_CMD_SFT_RESET (1L<<25) 4414#define BCE_MCP_MCPQ_FTQ_CMD_RD_DATA (1L<<26) 4415#define BCE_MCP_MCPQ_FTQ_CMD_ADD_INTERVEN (1L<<27) 4416#define BCE_MCP_MCPQ_FTQ_CMD_ADD_DATA (1L<<28) 4417#define BCE_MCP_MCPQ_FTQ_CMD_INTERVENE_CLR (1L<<29) 4418#define BCE_MCP_MCPQ_FTQ_CMD_POP (1L<<30) 4419#define BCE_MCP_MCPQ_FTQ_CMD_BUSY (1L<<31) 4420 4421#define BCE_MCP_MCPQ_FTQ_CTL 0x001453fc 4422#define BCE_MCP_MCPQ_FTQ_CTL_INTERVENE (1L<<0) 4423#define BCE_MCP_MCPQ_FTQ_CTL_OVERFLOW (1L<<1) 4424#define BCE_MCP_MCPQ_FTQ_CTL_FORCE_INTERVENE (1L<<2) 4425#define BCE_MCP_MCPQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 4426#define BCE_MCP_MCPQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 4427 4428#define BCE_MCP_ROM 0x00150000 4429#define BCE_MCP_SCRATCH 0x00160000 4430 4431#define BCE_SHM_HDR_SIGNATURE BCE_MCP_SCRATCH 4432#define BCE_SHM_HDR_SIGNATURE_SIG_MASK 0xffff0000 4433#define BCE_SHM_HDR_SIGNATURE_SIG 0x53530000 4434#define BCE_SHM_HDR_SIGNATURE_VER_MASK 0x000000ff 4435#define BCE_SHM_HDR_SIGNATURE_VER_ONE 0x00000001 4436 4437#define BCE_SHM_HDR_ADDR_0 BCE_MCP_SCRATCH + 4 4438#define BCE_SHM_HDR_ADDR_1 BCE_MCP_SCRATCH + 8 4439 4440/****************************************************************************/ 4441/* End machine generated definitions. */ 4442/****************************************************************************/ 4443 4444#define NUM_MC_HASH_REGISTERS 8 4445 4446 4447/* PHY_ID1: bits 31-16; PHY_ID2: bits 15-0. */ 4448#define PHY_BCM5706_PHY_ID 0x00206160 4449 4450#define PHY_ID(id) ((id) & 0xfffffff0) 4451#define PHY_REV_ID(id) ((id) & 0xf) 4452 4453/* 5708 Serdes PHY registers */ 4454 4455#define BCM5708S_UP1 0xb 4456 4457#define BCM5708S_UP1_2G5 0x1 4458 4459#define BCM5708S_BLK_ADDR 0x1f 4460 4461#define BCM5708S_BLK_ADDR_DIG 0x0000 4462#define BCM5708S_BLK_ADDR_DIG3 0x0002 4463#define BCM5708S_BLK_ADDR_TX_MISC 0x0005 4464 4465/* Digital Block */ 4466#define BCM5708S_1000X_CTL1 0x10 4467 4468#define BCM5708S_1000X_CTL1_FIBER_MODE 0x0001 4469#define BCM5708S_1000X_CTL1_AUTODET_EN 0x0010 4470 4471#define BCM5708S_1000X_CTL2 0x11 4472 4473#define BCM5708S_1000X_CTL2_PLLEL_DET_EN 0x0001 4474 4475#define BCM5708S_1000X_STAT1 0x14 4476 4477#define BCM5708S_1000X_STAT1_SGMII 0x0001 4478#define BCM5708S_1000X_STAT1_LINK 0x0002 4479#define BCM5708S_1000X_STAT1_FD 0x0004 4480#define BCM5708S_1000X_STAT1_SPEED_MASK 0x0018 4481#define BCM5708S_1000X_STAT1_SPEED_10 0x0000 4482#define BCM5708S_1000X_STAT1_SPEED_100 0x0008 4483#define BCM5708S_1000X_STAT1_SPEED_1G 0x0010 4484#define BCM5708S_1000X_STAT1_SPEED_2G5 0x0018 4485#define BCM5708S_1000X_STAT1_TX_PAUSE 0x0020 4486#define BCM5708S_1000X_STAT1_RX_PAUSE 0x0040 4487 4488/* Digital3 Block */ 4489#define BCM5708S_DIG_3_0 0x10 4490 4491#define BCM5708S_DIG_3_0_USE_IEEE 0x0001 4492 4493/* Tx/Misc Block */ 4494#define BCM5708S_TX_ACTL1 0x15 4495 4496#define BCM5708S_TX_ACTL1_DRIVER_VCM 0x30 4497 4498#define BCM5708S_TX_ACTL3 0x17 4499 4500#define RX_COPY_THRESH 92 4501 4502#define DMA_READ_CHANS 5 4503#define DMA_WRITE_CHANS 3 4504 4505/* Use the natural page size of the host CPU. */ 4506/* XXX: This has only been tested on amd64/i386 systems using 4KB pages. */ 4507#define BCM_PAGE_BITS PAGE_SHIFT 4508#define BCM_PAGE_SIZE PAGE_SIZE 4509 4510#define TX_PAGES 2 4511#define TOTAL_TX_BD_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct tx_bd)) 4512#define USABLE_TX_BD_PER_PAGE (TOTAL_TX_BD_PER_PAGE - 1) 4513#define TOTAL_TX_BD (TOTAL_TX_BD_PER_PAGE * TX_PAGES) 4514#define USABLE_TX_BD (USABLE_TX_BD_PER_PAGE * TX_PAGES) 4515#define MAX_TX_BD (TOTAL_TX_BD - 1) 4516 4517#define RX_PAGES 2 4518#define TOTAL_RX_BD_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct rx_bd)) 4519#define USABLE_RX_BD_PER_PAGE (TOTAL_RX_BD_PER_PAGE - 1) 4520#define TOTAL_RX_BD (TOTAL_RX_BD_PER_PAGE * RX_PAGES) 4521#define USABLE_RX_BD (USABLE_RX_BD_PER_PAGE * RX_PAGES) 4522#define MAX_RX_BD (TOTAL_RX_BD - 1) 4523 4524#define NEXT_TX_BD(x) (((x) & USABLE_TX_BD_PER_PAGE) == \ 4525 (USABLE_TX_BD_PER_PAGE - 1)) ? \ 4526 (x) + 2 : (x) + 1 4527 4528#define TX_CHAIN_IDX(x) ((x) & MAX_TX_BD) 4529 4530#define TX_PAGE(x) (((x) & ~USABLE_TX_BD_PER_PAGE) >> 8) 4531#define TX_IDX(x) ((x) & USABLE_TX_BD_PER_PAGE) 4532 4533#define NEXT_RX_BD(x) (((x) & USABLE_RX_BD_PER_PAGE) == \ 4534 (USABLE_RX_BD_PER_PAGE - 1)) ? \ 4535 (x) + 2 : (x) + 1 4536 4537#define RX_CHAIN_IDX(x) ((x) & MAX_RX_BD) 4538 4539#define RX_PAGE(x) (((x) & ~USABLE_RX_BD_PER_PAGE) >> 8) 4540#define RX_IDX(x) ((x) & USABLE_RX_BD_PER_PAGE) 4541 4542/* Context size. */ 4543#define CTX_SHIFT 7 4544#define CTX_SIZE (1 << CTX_SHIFT) 4545#define CTX_MASK (CTX_SIZE - 1) 4546#define GET_CID_ADDR(_cid) ((_cid) << CTX_SHIFT) 4547#define GET_CID(_cid_addr) ((_cid_addr) >> CTX_SHIFT) 4548 4549#define PHY_CTX_SHIFT 6 4550#define PHY_CTX_SIZE (1 << PHY_CTX_SHIFT) 4551#define PHY_CTX_MASK (PHY_CTX_SIZE - 1) 4552#define GET_PCID_ADDR(_pcid) ((_pcid) << PHY_CTX_SHIFT) 4553#define GET_PCID(_pcid_addr) ((_pcid_addr) >> PHY_CTX_SHIFT) 4554 4555#define MB_KERNEL_CTX_SHIFT 8 4556#define MB_KERNEL_CTX_SIZE (1 << MB_KERNEL_CTX_SHIFT) 4557#define MB_KERNEL_CTX_MASK (MB_KERNEL_CTX_SIZE - 1) 4558#define MB_GET_CID_ADDR(_cid) (0x10000 + ((_cid) << MB_KERNEL_CTX_SHIFT)) 4559 4560#define MAX_CID_CNT 0x4000 4561#define MAX_CID_ADDR (GET_CID_ADDR(MAX_CID_CNT)) 4562#define INVALID_CID_ADDR 0xffffffff 4563 4564#define TX_CID 16 4565#define RX_CID 0 4566 4567#define MB_TX_CID_ADDR MB_GET_CID_ADDR(TX_CID) 4568#define MB_RX_CID_ADDR MB_GET_CID_ADDR(RX_CID) 4569 4570/****************************************************************************/ 4571/* BCE Processor Firmwware Load Definitions */ 4572/****************************************************************************/ 4573 4574struct cpu_reg { 4575 u32 mode; 4576 u32 mode_value_halt; 4577 u32 mode_value_sstep; 4578 4579 u32 state; 4580 u32 state_value_clear; 4581 4582 u32 gpr0; 4583 u32 evmask; 4584 u32 pc; 4585 u32 inst; 4586 u32 bp; 4587 4588 u32 spad_base; 4589 4590 u32 mips_view_base; 4591}; 4592 4593struct fw_info { 4594 u32 ver_major; 4595 u32 ver_minor; 4596 u32 ver_fix; 4597 4598 u32 start_addr; 4599 4600 /* Text section. */ 4601 u32 text_addr; 4602 u32 text_len; 4603 u32 text_index; 4604 u32 *text; 4605 4606 /* Data section. */ 4607 u32 data_addr; 4608 u32 data_len; 4609 u32 data_index; 4610 u32 *data; 4611 4612 /* SBSS section. */ 4613 u32 sbss_addr; 4614 u32 sbss_len; 4615 u32 sbss_index; 4616 u32 *sbss; 4617 4618 /* BSS section. */ 4619 u32 bss_addr; 4620 u32 bss_len; 4621 u32 bss_index; 4622 u32 *bss; 4623 4624 /* Read-only section. */ 4625 u32 rodata_addr; 4626 u32 rodata_len; 4627 u32 rodata_index; 4628 u32 *rodata; 4629}; 4630 4631#define RV2P_PROC1 0 4632#define RV2P_PROC2 1 4633 4634#define BCE_MIREG(x) ((x & 0x1F) << 16) 4635#define BCE_MIPHY(x) ((x & 0x1F) << 21) 4636#define BCE_PHY_TIMEOUT 50 4637 4638#define BCE_NVRAM_SIZE 0x200 4639#define BCE_NVRAM_MAGIC 0x669955aa 4640#define BCE_CRC32_RESIDUAL 0xdebb20e3 4641 4642#define BCE_TX_TIMEOUT 5 4643 4644#define BCE_MAX_SEGMENTS 32 4645#define BCE_TSO_MAX_SIZE 65536 4646#define BCE_TSO_MAX_SEG_SIZE 4096 4647 4648#define BCE_DMA_ALIGN 8 4649#define BCE_DMA_BOUNDARY 0 4650 4651/* The BCM5708 has a problem with addresses greater that 40bits. */ 4652/* Handle the sizing issue in an architecture agnostic fashion. */ 4653#if (BUS_SPACE_MAXADDR < 0xFFFFFFFFFF) 4654#define BCE_BUS_SPACE_MAXADDR BUS_SPACE_MAXADDR 4655#else 4656#define BCE_BUS_SPACE_MAXADDR 0xFFFFFFFFFF 4657#endif 4658 4659/* 4660 * XXX Checksum offload involving IP fragments seems to cause problems on 4661 * transmit. Disable it for now, hopefully there will be a more elegant 4662 * solution later. 4663 */ 4664#ifdef BCE_IP_CSUM 4665#define BCE_IF_HWASSIST (CSUM_IP | CSUM_TCP | CSUM_UDP) 4666#else 4667#define BCE_IF_HWASSIST (CSUM_TCP | CSUM_UDP) 4668#endif 4669 4670#if __FreeBSD_version < 700000 4671#define BCE_IF_CAPABILITIES (IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 4672 IFCAP_HWCSUM | IFCAP_JUMBO_MTU) 4673#else 4674#define BCE_IF_CAPABILITIES (IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 4675 IFCAP_HWCSUM | IFCAP_JUMBO_MTU | IFCAP_VLAN_HWCSUM) 4676#endif 4677 4678#define BCE_MIN_MTU 60 4679#define BCE_MIN_ETHER_MTU 64 4680 4681#define BCE_MAX_STD_MTU 1500 4682#define BCE_MAX_STD_ETHER_MTU 1518 4683#define BCE_MAX_STD_ETHER_MTU_VLAN 1522 4684 4685#define BCE_MAX_JUMBO_MTU 9000 4686#define BCE_MAX_JUMBO_ETHER_MTU 9018 4687#define BCE_MAX_JUMBO_ETHER_MTU_VLAN 9022 4688 4689// #define BCE_MAX_MTU ETHER_MAX_LEN_JUMBO + ETHER_VLAN_ENCAP_LEN /* 9022 */ 4690 4691/****************************************************************************/ 4692/* BCE Device State Data Structure */ 4693/****************************************************************************/ 4694 4695#define BCE_STATUS_BLK_SZ sizeof(struct status_block) 4696#define BCE_STATS_BLK_SZ sizeof(struct statistics_block) 4697#define BCE_TX_CHAIN_PAGE_SZ BCM_PAGE_SIZE 4698#define BCE_RX_CHAIN_PAGE_SZ BCM_PAGE_SIZE 4699 4700struct bce_softc 4701{ 4702 /* MUST start with ifnet pointer (see definition of miibus_statchg()) */ 4703 struct ifnet *bce_ifp; /* Interface info */ 4704 device_t bce_dev; /* Parent device handle */ 4705 u_int8_t bce_unit; /* Interface number */ 4706 struct resource *bce_res_mem; /* Device resource handle */ 4707 struct ifmedia bce_ifmedia; /* TBI media info */ 4708 bus_space_tag_t bce_btag; /* Device bus tag */ 4709 bus_space_handle_t bce_bhandle; /* Device bus handle */ 4710 vm_offset_t bce_vhandle; /* Device virtual memory handle */ 4711 struct resource *bce_res_irq; /* IRQ Resource Handle */ 4712 struct mtx bce_mtx; /* Mutex */ 4713 void *bce_intrhand; /* Interrupt handler */ 4714 4715 /* ASIC Chip ID. */ 4716 u32 bce_chipid; 4717 4718 /* General controller flags. */ 4719 u32 bce_flags; 4720#define BCE_PCIX_FLAG 0x00000001 4721#define BCE_PCI_32BIT_FLAG 0x00000002 4722#define BCE_ONE_TDMA_FLAG 0x00000004 /* Deprecated */ 4723#define BCE_NO_WOL_FLAG 0x00000008 4724#define BCE_USING_DAC_FLAG 0x00000010 4725#define BCE_USING_MSI_FLAG 0x00000020 4726#define BCE_MFW_ENABLE_FLAG 0x00000040 4727 4728 /* PHY specific flags. */ 4729 u32 bce_phy_flags; 4730#define BCE_PHY_SERDES_FLAG 0x00000001 4731#define BCE_PHY_CRC_FIX_FLAG 0x00000002 4732#define BCE_PHY_PARALLEL_DETECT_FLAG 0x00000004 4733#define BCE_PHY_2_5G_CAPABLE_FLAG 0x00000008 4734#define BCE_PHY_INT_MODE_MASK_FLAG 0x00000300 4735#define BCE_PHY_INT_MODE_AUTO_POLLING_FLAG 0x00000100 4736#define BCE_PHY_INT_MODE_LINK_READY_FLAG 0x00000200 4737 4738 /* Values that need to be shared with the PHY driver. */ 4739 u32 bce_shared_hw_cfg; 4740 u32 bce_port_hw_cfg; 4741 4742 bus_addr_t max_bus_addr; 4743 u16 bus_speed_mhz; /* PCI bus speed */ 4744 struct flash_spec *bce_flash_info; /* Flash NVRAM settings */ 4745 u32 bce_flash_size; /* Flash NVRAM size */ 4746 u32 bce_shmem_base; /* Shared Memory base address */ 4747 char * bce_name; /* Name string */ 4748 4749 /* Tracks the version of bootcode firmware. */ 4750 u32 bce_fw_ver; 4751 4752 /* Tracks the state of the firmware. 0 = Running while any */ 4753 /* other value indicates that the firmware is not responding. */ 4754 u16 bce_fw_timed_out; 4755 4756 /* An incrementing sequence used to coordinate messages passed */ 4757 /* from the driver to the firmware. */ 4758 u16 bce_fw_wr_seq; 4759 4760 /* An incrementing sequence used to let the firmware know that */ 4761 /* the driver is still operating. Without the pulse, management */ 4762 /* firmware such as IPMI or UMP will operate in OS absent state. */ 4763 u16 bce_fw_drv_pulse_wr_seq; 4764 4765 /* Ethernet MAC address. */ 4766 u_char eaddr[6]; 4767 4768 /* These setting are used by the host coalescing (HC) block to */ 4769 /* to control how often the status block, statistics block and */ 4770 /* interrupts are generated. */ 4771 u16 bce_tx_quick_cons_trip_int; 4772 u16 bce_tx_quick_cons_trip; 4773 u16 bce_rx_quick_cons_trip_int; 4774 u16 bce_rx_quick_cons_trip; 4775 u16 bce_comp_prod_trip_int; 4776 u16 bce_comp_prod_trip; 4777 u16 bce_tx_ticks_int; 4778 u16 bce_tx_ticks; 4779 u16 bce_rx_ticks_int; 4780 u16 bce_rx_ticks; 4781 u16 bce_com_ticks_int; 4782 u16 bce_com_ticks; 4783 u16 bce_cmd_ticks_int; 4784 u16 bce_cmd_ticks; 4785 u32 bce_stats_ticks; 4786 4787 /* The address of the integrated PHY on the MII bus. */ 4788 int bce_phy_addr; 4789 4790 /* The device handle for the MII bus child device. */ 4791 device_t bce_miibus; 4792 4793 /* Driver maintained TX chain pointers and byte counter. */ 4794 u16 rx_prod; 4795 u16 rx_cons; 4796 u32 rx_prod_bseq; /* Counts the bytes used. */ 4797 u16 tx_prod; 4798 u16 tx_cons; 4799 u32 tx_prod_bseq; /* Counts the bytes used. */ 4800 4801 int bce_link; 4802 struct callout bce_tick_callout; 4803 struct callout bce_pulse_callout; 4804 4805 int watchdog_timer; /* ticks until chip reset */ 4806 4807 /* Frame size and mbuf allocation size for RX frames. */ 4808 u32 max_frame_size; 4809 int mbuf_alloc_size; 4810 4811 /* Receive mode settings (i.e promiscuous, multicast, etc.). */ 4812 u32 rx_mode; 4813 4814#ifdef DEVICE_POLLING 4815 int bce_rxcycles; /* Counter for receive polling cycles */ 4816#endif 4817 4818 /* Bus tag for the bce controller. */ 4819 bus_dma_tag_t parent_tag; 4820 4821 /* H/W maintained TX buffer descriptor chain structure. */ 4822 bus_dma_tag_t tx_bd_chain_tag; 4823 bus_dmamap_t tx_bd_chain_map[TX_PAGES]; 4824 struct tx_bd *tx_bd_chain[TX_PAGES]; 4825 bus_addr_t tx_bd_chain_paddr[TX_PAGES]; 4826 4827 /* H/W maintained RX buffer descriptor chain structure. */ 4828 bus_dma_tag_t rx_bd_chain_tag; 4829 bus_dmamap_t rx_bd_chain_map[RX_PAGES]; 4830 struct rx_bd *rx_bd_chain[RX_PAGES]; 4831 bus_addr_t rx_bd_chain_paddr[RX_PAGES]; 4832 4833 /* H/W maintained status block. */ 4834 bus_dma_tag_t status_tag; 4835 bus_dmamap_t status_map; 4836 struct status_block *status_block; /* virtual address */ 4837 bus_addr_t status_block_paddr; /* Physical address */ 4838 4839 /* Driver maintained status block values. */ 4840 u16 last_status_idx; 4841 u16 hw_rx_cons; 4842 u16 hw_tx_cons; 4843 4844 /* H/W maintained statistics block. */ 4845 bus_dma_tag_t stats_tag; 4846 bus_dmamap_t stats_map; 4847 struct statistics_block *stats_block; /* Virtual address */ 4848 bus_addr_t stats_block_paddr; /* Physical address */ 4849 4850 /* Bus tag for RX/TX mbufs. */ 4851 bus_dma_tag_t rx_mbuf_tag; 4852 bus_dma_tag_t tx_mbuf_tag; 4853 4854 /* S/W maintained mbuf TX chain structure. */ 4855 bus_dmamap_t tx_mbuf_map[TOTAL_TX_BD]; 4856 struct mbuf *tx_mbuf_ptr[TOTAL_TX_BD]; 4857 4858 /* S/W maintained mbuf RX chain structure. */ 4859 bus_dmamap_t rx_mbuf_map[TOTAL_RX_BD]; 4860 struct mbuf *rx_mbuf_ptr[TOTAL_RX_BD]; 4861 4862 /* Track the number of rx_bd and tx_bd's in use. */ 4863 u16 free_rx_bd; 4864 u16 max_rx_bd; 4865 u16 used_tx_bd; 4866 u16 max_tx_bd; 4867 4868 /* Provides access to hardware statistics through sysctl. */ 4869 u64 stat_IfHCInOctets; 4870 u64 stat_IfHCInBadOctets; 4871 u64 stat_IfHCOutOctets; 4872 u64 stat_IfHCOutBadOctets; 4873 u64 stat_IfHCInUcastPkts; 4874 u64 stat_IfHCInMulticastPkts; 4875 u64 stat_IfHCInBroadcastPkts; 4876 u64 stat_IfHCOutUcastPkts; 4877 u64 stat_IfHCOutMulticastPkts; 4878 u64 stat_IfHCOutBroadcastPkts; 4879 4880 u32 stat_emac_tx_stat_dot3statsinternalmactransmiterrors; 4881 u32 stat_Dot3StatsCarrierSenseErrors; 4882 u32 stat_Dot3StatsFCSErrors; 4883 u32 stat_Dot3StatsAlignmentErrors; 4884 u32 stat_Dot3StatsSingleCollisionFrames; 4885 u32 stat_Dot3StatsMultipleCollisionFrames; 4886 u32 stat_Dot3StatsDeferredTransmissions; 4887 u32 stat_Dot3StatsExcessiveCollisions; 4888 u32 stat_Dot3StatsLateCollisions; 4889 u32 stat_EtherStatsCollisions; 4890 u32 stat_EtherStatsFragments; 4891 u32 stat_EtherStatsJabbers; 4892 u32 stat_EtherStatsUndersizePkts; 4893 u32 stat_EtherStatsOverrsizePkts; 4894 u32 stat_EtherStatsPktsRx64Octets; 4895 u32 stat_EtherStatsPktsRx65Octetsto127Octets; 4896 u32 stat_EtherStatsPktsRx128Octetsto255Octets; 4897 u32 stat_EtherStatsPktsRx256Octetsto511Octets; 4898 u32 stat_EtherStatsPktsRx512Octetsto1023Octets; 4899 u32 stat_EtherStatsPktsRx1024Octetsto1522Octets; 4900 u32 stat_EtherStatsPktsRx1523Octetsto9022Octets; 4901 u32 stat_EtherStatsPktsTx64Octets; 4902 u32 stat_EtherStatsPktsTx65Octetsto127Octets; 4903 u32 stat_EtherStatsPktsTx128Octetsto255Octets; 4904 u32 stat_EtherStatsPktsTx256Octetsto511Octets; 4905 u32 stat_EtherStatsPktsTx512Octetsto1023Octets; 4906 u32 stat_EtherStatsPktsTx1024Octetsto1522Octets; 4907 u32 stat_EtherStatsPktsTx1523Octetsto9022Octets; 4908 u32 stat_XonPauseFramesReceived; 4909 u32 stat_XoffPauseFramesReceived; 4910 u32 stat_OutXonSent; 4911 u32 stat_OutXoffSent; 4912 u32 stat_FlowControlDone; 4913 u32 stat_MacControlFramesReceived; 4914 u32 stat_XoffStateEntered; 4915 u32 stat_IfInFramesL2FilterDiscards; 4916 u32 stat_IfInRuleCheckerDiscards; 4917 u32 stat_IfInFTQDiscards; 4918 u32 stat_IfInMBUFDiscards; 4919 u32 stat_IfInRuleCheckerP4Hit; 4920 u32 stat_CatchupInRuleCheckerDiscards; 4921 u32 stat_CatchupInFTQDiscards; 4922 u32 stat_CatchupInMBUFDiscards; 4923 u32 stat_CatchupInRuleCheckerP4Hit; 4924 4925 /* Provides access to certain firmware statistics. */ 4926 u32 com_no_buffers; 4927 4928#ifdef BCE_DEBUG 4929 /* Track the number of enqueued mbufs. */ 4930 int tx_mbuf_alloc; 4931 int rx_mbuf_alloc; 4932 4933 /* Track how many and what type of interrupts are generated. */ 4934 u32 interrupts_generated; 4935 u32 interrupts_handled; 4936 u32 rx_interrupts; 4937 u32 tx_interrupts; 4938 4939 u32 rx_low_watermark; /* Lowest number of rx_bd's free. */ 4940 u32 rx_empty_count; /* Number of times the RX chain was empty. */ 4941 u32 tx_hi_watermark; /* Greatest number of tx_bd's used. */ 4942 u32 tx_full_count; /* Number of times the TX chain was full. */ 4943 u32 mbuf_alloc_failed; /* Mbuf allocation failure counter. */ 4944 u32 l2fhdr_status_errors; 4945 u32 unexpected_attentions; 4946 u32 lost_status_block_updates; 4947 4948 u32 requested_tso_frames; /* Number of TSO frames enqueued. */ 4949#endif 4950}; 4951 4952#endif /* #ifndef _BCE_H_DEFINED */ 4953 4954