if_bcereg.h revision 169632
1/*- 2 * Copyright (c) 2006-2007 Broadcom Corporation 3 * David Christensen <davidch@broadcom.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. Neither the name of Broadcom Corporation nor the name of its contributors 14 * may be used to endorse or promote products derived from this software 15 * without specific prior written consent. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 18 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * $FreeBSD: head/sys/dev/bce/if_bcereg.h 169632 2007-05-16 23:34:11Z davidch $ 30 */ 31 32#ifndef _BCE_H_DEFINED 33#define _BCE_H_DEFINED 34 35#ifdef HAVE_KERNEL_OPTION_HEADERS 36#include "opt_device_polling.h" 37#endif 38 39#include <sys/param.h> 40#include <sys/endian.h> 41#include <sys/systm.h> 42#include <sys/sockio.h> 43#include <sys/mbuf.h> 44#include <sys/malloc.h> 45#include <sys/kernel.h> 46#include <sys/module.h> 47#include <sys/socket.h> 48#include <sys/sysctl.h> 49#include <sys/queue.h> 50 51#include <net/bpf.h> 52#include <net/ethernet.h> 53#include <net/if.h> 54#include <net/if_arp.h> 55#include <net/if_dl.h> 56#include <net/if_media.h> 57 58#include <net/if_types.h> 59#include <net/if_vlan_var.h> 60 61#include <netinet/in_systm.h> 62#include <netinet/in.h> 63#include <netinet/if_ether.h> 64#include <netinet/ip.h> 65#include <netinet/ip6.h> 66#include <netinet/tcp.h> 67#include <netinet/udp.h> 68 69#include <machine/bus.h> 70#include <machine/resource.h> 71#include <sys/bus.h> 72#include <sys/rman.h> 73 74#include <dev/mii/mii.h> 75#include <dev/mii/miivar.h> 76#include "miidevs.h" 77#include <dev/mii/brgphyreg.h> 78 79#include <dev/pci/pcireg.h> 80#include <dev/pci/pcivar.h> 81 82#include "miibus_if.h" 83 84/****************************************************************************/ 85/* Conversion to FreeBSD type definitions. */ 86/****************************************************************************/ 87#define u64 uint64_t 88#define u32 uint32_t 89#define u16 uint16_t 90#define u8 uint8_t 91 92#if BYTE_ORDER == BIG_ENDIAN 93#define __BIG_ENDIAN 1 94#undef __LITTLE_ENDIAN 95#else 96#undef __BIG_ENDIAN 97#define __LITTLE_ENDIAN 1 98#endif 99 100/****************************************************************************/ 101/* Debugging macros and definitions. */ 102/****************************************************************************/ 103#define BCE_CP_LOAD 0x00000001 104#define BCE_CP_SEND 0x00000002 105#define BCE_CP_RECV 0x00000004 106#define BCE_CP_INTR 0x00000008 107#define BCE_CP_UNLOAD 0x00000010 108#define BCE_CP_RESET 0x00000020 109#define BCE_CP_ALL 0x00FFFFFF 110 111#define BCE_CP_MASK 0x00FFFFFF 112 113#define BCE_LEVEL_FATAL 0x00000000 114#define BCE_LEVEL_WARN 0x01000000 115#define BCE_LEVEL_INFO 0x02000000 116#define BCE_LEVEL_VERBOSE 0x03000000 117#define BCE_LEVEL_EXCESSIVE 0x04000000 118 119#define BCE_LEVEL_MASK 0xFF000000 120 121#define BCE_WARN_LOAD (BCE_CP_LOAD | BCE_LEVEL_WARN) 122#define BCE_INFO_LOAD (BCE_CP_LOAD | BCE_LEVEL_INFO) 123#define BCE_VERBOSE_LOAD (BCE_CP_LOAD | BCE_LEVEL_VERBOSE) 124#define BCE_EXCESSIVE_LOAD (BCE_CP_LOAD | BCE_LEVEL_EXCESSIVE) 125 126#define BCE_WARN_SEND (BCE_CP_SEND | BCE_LEVEL_WARN) 127#define BCE_INFO_SEND (BCE_CP_SEND | BCE_LEVEL_INFO) 128#define BCE_VERBOSE_SEND (BCE_CP_SEND | BCE_LEVEL_VERBOSE) 129#define BCE_EXCESSIVE_SEND (BCE_CP_SEND | BCE_LEVEL_EXCESSIVE) 130 131#define BCE_WARN_RECV (BCE_CP_RECV | BCE_LEVEL_WARN) 132#define BCE_INFO_RECV (BCE_CP_RECV | BCE_LEVEL_INFO) 133#define BCE_VERBOSE_RECV (BCE_CP_RECV | BCE_LEVEL_VERBOSE) 134#define BCE_EXCESSIVE_RECV (BCE_CP_RECV | BCE_LEVEL_EXCESSIVE) 135 136#define BCE_WARN_INTR (BCE_CP_INTR | BCE_LEVEL_WARN) 137#define BCE_INFO_INTR (BCE_CP_INTR | BCE_LEVEL_INFO) 138#define BCE_VERBOSE_INTR (BCE_CP_INTR | BCE_LEVEL_VERBOSE) 139#define BCE_EXCESSIVE_INTR (BCE_CP_INTR | BCE_LEVEL_EXCESSIVE) 140 141#define BCE_WARN_UNLOAD (BCE_CP_UNLOAD | BCE_LEVEL_WARN) 142#define BCE_INFO_UNLOAD (BCE_CP_UNLOAD | BCE_LEVEL_INFO) 143#define BCE_VERBOSE_UNLOAD (BCE_CP_UNLOAD | BCE_LEVEL_VERBOSE) 144#define BCE_EXCESSIVE_UNLOAD (BCE_CP_UNLOAD | BCE_LEVEL_EXCESSIVE) 145 146#define BCE_WARN_RESET (BCE_CP_RESET | BCE_LEVEL_WARN) 147#define BCE_INFO_RESET (BCE_CP_RESET | BCE_LEVEL_INFO) 148#define BCE_VERBOSE_RESET (BCE_CP_RESET | BCE_LEVEL_VERBOSE) 149#define BCE_EXCESSIVE_RESET (BCE_CP_RESET | BCE_LEVEL_EXCESSIVE) 150 151#define BCE_FATAL (BCE_CP_ALL | BCE_LEVEL_FATAL) 152#define BCE_WARN (BCE_CP_ALL | BCE_LEVEL_WARN) 153#define BCE_INFO (BCE_CP_ALL | BCE_LEVEL_INFO) 154#define BCE_VERBOSE (BCE_CP_ALL | BCE_LEVEL_VERBOSE) 155#define BCE_EXCESSIVE (BCE_CP_ALL | BCE_LEVEL_EXCESSIVE) 156 157#define BCE_CODE_PATH(cp) ((cp & BCE_CP_MASK) & bce_debug) 158#define BCE_MSG_LEVEL(lv) ((lv & BCE_LEVEL_MASK) <= (bce_debug & BCE_LEVEL_MASK)) 159#define BCE_LOG_MSG(m) (BCE_CODE_PATH(m) && BCE_MSG_LEVEL(m)) 160 161#ifdef BCE_DEBUG 162 163/* Print a message based on the logging level and code path. */ 164#define DBPRINT(sc, level, format, args...) \ 165 if (BCE_LOG_MSG(level)) { \ 166 device_printf(sc->bce_dev, format, ## args); \ 167 } 168 169/* Runs a particular command based on the logging level and code path. */ 170#define DBRUN(m, args...) \ 171 if (BCE_LOG_MSG(m)) { \ 172 args; \ 173 } 174 175/* Runs a particular command based on the logging level. */ 176#define DBRUNLV(level, args...) \ 177 if (BCE_MSG_LEVEL(level)) { \ 178 args; \ 179 } 180 181/* Runs a particular command based on the code path. */ 182#define DBRUNCP(cp, args...) \ 183 if (BCE_CODE_PATH(cp)) { \ 184 args; \ 185 } 186 187/* Runs a particular command based on a condition. */ 188#define DBRUNIF(cond, args...) \ 189 if (cond) { \ 190 args; \ 191 } 192 193/* Needed for random() function which is only used in debugging. */ 194#include <sys/random.h> 195 196/* Returns FALSE in "defects" per 2^31 - 1 calls, otherwise returns TRUE. */ 197#define DB_RANDOMFALSE(defects) (random() > defects) 198#define DB_OR_RANDOMFALSE(defects) || (random() > defects) 199#define DB_AND_RANDOMFALSE(defects) && (random() > ddfects) 200 201/* Returns TRUE in "defects" per 2^31 - 1 calls, otherwise returns FALSE. */ 202#define DB_RANDOMTRUE(defects) (random() < defects) 203#define DB_OR_RANDOMTRUE(defects) || (random() < defects) 204#define DB_AND_RANDOMTRUE(defects) && (random() < defects) 205 206#else 207 208#define DBPRINT(level, format, args...) 209#define DBRUN(m, args...) 210#define DBRUNLV(level, args...) 211#define DBRUNCP(cp, args...) 212#define DBRUNIF(cond, args...) 213#define DB_RANDOMFALSE(defects) 214#define DB_OR_RANDOMFALSE(percent) 215#define DB_AND_RANDOMFALSE(percent) 216#define DB_RANDOMTRUE(defects) 217#define DB_OR_RANDOMTRUE(percent) 218#define DB_AND_RANDOMTRUE(percent) 219 220#endif /* BCE_DEBUG */ 221 222 223/****************************************************************************/ 224/* Device identification definitions. */ 225/****************************************************************************/ 226#define BRCM_VENDORID 0x14E4 227#define BRCM_DEVICEID_BCM5706 0x164A 228#define BRCM_DEVICEID_BCM5706S 0x16AA 229#define BRCM_DEVICEID_BCM5708 0x164C 230#define BRCM_DEVICEID_BCM5708S 0x16AC 231 232#define HP_VENDORID 0x103C 233 234#define PCI_ANY_ID (u_int16_t) (~0U) 235 236/* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ 237 238#define BCE_CHIP_NUM(sc) (((sc)->bce_chipid) & 0xffff0000) 239#define BCE_CHIP_NUM_5706 0x57060000 240#define BCE_CHIP_NUM_5708 0x57080000 241 242#define BCE_CHIP_REV(sc) (((sc)->bce_chipid) & 0x0000f000) 243#define BCE_CHIP_REV_Ax 0x00000000 244#define BCE_CHIP_REV_Bx 0x00001000 245#define BCE_CHIP_REV_Cx 0x00002000 246 247#define BCE_CHIP_METAL(sc) (((sc)->bce_chipid) & 0x00000ff0) 248#define BCE_CHIP_BOND(bp) (((sc)->bce_chipid) & 0x0000000f) 249 250#define BCE_CHIP_ID(sc) (((sc)->bce_chipid) & 0xfffffff0) 251#define BCE_CHIP_ID_5706_A0 0x57060000 252#define BCE_CHIP_ID_5706_A1 0x57060010 253#define BCE_CHIP_ID_5706_A2 0x57060020 254#define BCE_CHIP_ID_5706_A3 0x57060030 255#define BCE_CHIP_ID_5708_A0 0x57080000 256#define BCE_CHIP_ID_5708_B0 0x57081000 257#define BCE_CHIP_ID_5708_B1 0x57081010 258#define BCE_CHIP_ID_5708_B2 0x57081020 259 260#define BCE_CHIP_BOND_ID(sc) (((sc)->bce_chipid) & 0xf) 261 262/* A serdes chip will have the first bit of the bond id set. */ 263#define BCE_CHIP_BOND_ID_SERDES_BIT 0x01 264 265 266/* shorthand one */ 267#define BCE_ASICREV(x) ((x) >> 28) 268#define BCE_ASICREV_BCM5700 0x06 269 270/* chip revisions */ 271#define BCE_CHIPREV(x) ((x) >> 24) 272#define BCE_CHIPREV_5700_AX 0x70 273#define BCE_CHIPREV_5700_BX 0x71 274#define BCE_CHIPREV_5700_CX 0x72 275#define BCE_CHIPREV_5701_AX 0x00 276 277struct bce_type { 278 u_int16_t bce_vid; 279 u_int16_t bce_did; 280 u_int16_t bce_svid; 281 u_int16_t bce_sdid; 282 char *bce_name; 283}; 284 285/****************************************************************************/ 286/* Byte order conversions. */ 287/****************************************************************************/ 288#if __FreeBSD_version >= 500000 289#define bce_htobe16(x) htobe16(x) 290#define bce_htobe32(x) htobe32(x) 291#define bce_htobe64(x) htobe64(x) 292#define bce_htole16(x) htole16(x) 293#define bce_htole32(x) htole32(x) 294#define bce_htole64(x) htole64(x) 295 296#define bce_be16toh(x) be16toh(x) 297#define bce_be32toh(x) be32toh(x) 298#define bce_be64toh(x) be64toh(x) 299#define bce_le16toh(x) le16toh(x) 300#define bce_le32toh(x) le32toh(x) 301#define bce_le64toh(x) le64toh(x) 302#else 303#define bce_htobe16(x) (x) 304#define bce_htobe32(x) (x) 305#define bce_htobe64(x) (x) 306#define bce_htole16(x) (x) 307#define bce_htole32(x) (x) 308#define bce_htole64(x) (x) 309 310#define bce_be16toh(x) (x) 311#define bce_be32toh(x) (x) 312#define bce_be64toh(x) (x) 313#define bce_le16toh(x) (x) 314#define bce_le32toh(x) (x) 315#define bce_le64toh(x) (x) 316#endif 317 318 319/****************************************************************************/ 320/* NVRAM Access */ 321/****************************************************************************/ 322 323/* Buffered flash (Atmel: AT45DB011B) specific information */ 324#define SEEPROM_PAGE_BITS 2 325#define SEEPROM_PHY_PAGE_SIZE (1 << SEEPROM_PAGE_BITS) 326#define SEEPROM_BYTE_ADDR_MASK (SEEPROM_PHY_PAGE_SIZE-1) 327#define SEEPROM_PAGE_SIZE 4 328#define SEEPROM_TOTAL_SIZE 65536 329 330#define BUFFERED_FLASH_PAGE_BITS 9 331#define BUFFERED_FLASH_PHY_PAGE_SIZE (1 << BUFFERED_FLASH_PAGE_BITS) 332#define BUFFERED_FLASH_BYTE_ADDR_MASK (BUFFERED_FLASH_PHY_PAGE_SIZE-1) 333#define BUFFERED_FLASH_PAGE_SIZE 264 334#define BUFFERED_FLASH_TOTAL_SIZE 0x21000 335 336#define SAIFUN_FLASH_PAGE_BITS 8 337#define SAIFUN_FLASH_PHY_PAGE_SIZE (1 << SAIFUN_FLASH_PAGE_BITS) 338#define SAIFUN_FLASH_BYTE_ADDR_MASK (SAIFUN_FLASH_PHY_PAGE_SIZE-1) 339#define SAIFUN_FLASH_PAGE_SIZE 256 340#define SAIFUN_FLASH_BASE_TOTAL_SIZE 65536 341 342#define ST_MICRO_FLASH_PAGE_BITS 8 343#define ST_MICRO_FLASH_PHY_PAGE_SIZE (1 << ST_MICRO_FLASH_PAGE_BITS) 344#define ST_MICRO_FLASH_BYTE_ADDR_MASK (ST_MICRO_FLASH_PHY_PAGE_SIZE-1) 345#define ST_MICRO_FLASH_PAGE_SIZE 256 346#define ST_MICRO_FLASH_BASE_TOTAL_SIZE 65536 347 348#define NVRAM_TIMEOUT_COUNT 30000 349#define BCE_FLASHDESC_MAX 64 350 351#define FLASH_STRAP_MASK (BCE_NVM_CFG1_FLASH_MODE | \ 352 BCE_NVM_CFG1_BUFFER_MODE | \ 353 BCE_NVM_CFG1_PROTECT_MODE | \ 354 BCE_NVM_CFG1_FLASH_SIZE) 355 356#define FLASH_BACKUP_STRAP_MASK (0xf << 26) 357 358struct flash_spec { 359 u32 strapping; 360 u32 config1; 361 u32 config2; 362 u32 config3; 363 u32 write1; 364 u32 buffered; 365 u32 page_bits; 366 u32 page_size; 367 u32 addr_mask; 368 u32 total_size; 369 u8 *name; 370}; 371 372 373/****************************************************************************/ 374/* Shared Memory layout */ 375/* The BCE bootcode will initialize this data area with port configurtion */ 376/* information which can be accessed by the driver. */ 377/****************************************************************************/ 378 379/* 380 * This value (in milliseconds) determines the frequency of the driver 381 * issuing the PULSE message code. The firmware monitors this periodic 382 * pulse to determine when to switch to an OS-absent mode. 383 */ 384#define DRV_PULSE_PERIOD_MS 250 385 386/* 387 * This value (in milliseconds) determines how long the driver should 388 * wait for an acknowledgement from the firmware before timing out. Once 389 * the firmware has timed out, the driver will assume there is no firmware 390 * running and there won't be any firmware-driver synchronization during a 391 * driver reset. 392 */ 393#define FW_ACK_TIME_OUT_MS 100 394 395 396#define BCE_DRV_RESET_SIGNATURE 0x00000000 397#define BCE_DRV_RESET_SIGNATURE_MAGIC 0x4841564b /* HAVK */ 398 399#define BCE_DRV_MB 0x00000004 400#define BCE_DRV_MSG_CODE 0xff000000 401#define BCE_DRV_MSG_CODE_RESET 0x01000000 402#define BCE_DRV_MSG_CODE_UNLOAD 0x02000000 403#define BCE_DRV_MSG_CODE_SHUTDOWN 0x03000000 404#define BCE_DRV_MSG_CODE_SUSPEND_WOL 0x04000000 405#define BCE_DRV_MSG_CODE_FW_TIMEOUT 0x05000000 406#define BCE_DRV_MSG_CODE_PULSE 0x06000000 407#define BCE_DRV_MSG_CODE_DIAG 0x07000000 408#define BCE_DRV_MSG_CODE_SUSPEND_NO_WOL 0x09000000 409 410#define BCE_DRV_MSG_DATA 0x00ff0000 411#define BCE_DRV_MSG_DATA_WAIT0 0x00010000 412#define BCE_DRV_MSG_DATA_WAIT1 0x00020000 413#define BCE_DRV_MSG_DATA_WAIT2 0x00030000 414#define BCE_DRV_MSG_DATA_WAIT3 0x00040000 415 416#define BCE_DRV_MSG_SEQ 0x0000ffff 417 418#define BCE_FW_MB 0x00000008 419#define BCE_FW_MSG_ACK 0x0000ffff 420#define BCE_FW_MSG_STATUS_MASK 0x00ff0000 421#define BCE_FW_MSG_STATUS_OK 0x00000000 422#define BCE_FW_MSG_STATUS_FAILURE 0x00ff0000 423 424#define BCE_LINK_STATUS 0x0000000c 425#define BCE_LINK_STATUS_INIT_VALUE 0xffffffff 426#define BCE_LINK_STATUS_LINK_UP 0x1 427#define BCE_LINK_STATUS_LINK_DOWN 0x0 428#define BCE_LINK_STATUS_SPEED_MASK 0x1e 429#define BCE_LINK_STATUS_AN_INCOMPLETE (0<<1) 430#define BCE_LINK_STATUS_10HALF (1<<1) 431#define BCE_LINK_STATUS_10FULL (2<<1) 432#define BCE_LINK_STATUS_100HALF (3<<1) 433#define BCE_LINK_STATUS_100BASE_T4 (4<<1) 434#define BCE_LINK_STATUS_100FULL (5<<1) 435#define BCE_LINK_STATUS_1000HALF (6<<1) 436#define BCE_LINK_STATUS_1000FULL (7<<1) 437#define BCE_LINK_STATUS_2500HALF (8<<1) 438#define BCE_LINK_STATUS_2500FULL (9<<1) 439#define BCE_LINK_STATUS_AN_ENABLED (1<<5) 440#define BCE_LINK_STATUS_AN_COMPLETE (1<<6) 441#define BCE_LINK_STATUS_PARALLEL_DET (1<<7) 442#define BCE_LINK_STATUS_RESERVED (1<<8) 443#define BCE_LINK_STATUS_PARTNER_AD_1000FULL (1<<9) 444#define BCE_LINK_STATUS_PARTNER_AD_1000HALF (1<<10) 445#define BCE_LINK_STATUS_PARTNER_AD_100BT4 (1<<11) 446#define BCE_LINK_STATUS_PARTNER_AD_100FULL (1<<12) 447#define BCE_LINK_STATUS_PARTNER_AD_100HALF (1<<13) 448#define BCE_LINK_STATUS_PARTNER_AD_10FULL (1<<14) 449#define BCE_LINK_STATUS_PARTNER_AD_10HALF (1<<15) 450#define BCE_LINK_STATUS_TX_FC_ENABLED (1<<16) 451#define BCE_LINK_STATUS_RX_FC_ENABLED (1<<17) 452#define BCE_LINK_STATUS_PARTNER_SYM_PAUSE_CAP (1<<18) 453#define BCE_LINK_STATUS_PARTNER_ASYM_PAUSE_CAP (1<<19) 454#define BCE_LINK_STATUS_SERDES_LINK (1<<20) 455#define BCE_LINK_STATUS_PARTNER_AD_2500FULL (1<<21) 456#define BCE_LINK_STATUS_PARTNER_AD_2500HALF (1<<22) 457 458#define BCE_DRV_PULSE_MB 0x00000010 459#define BCE_DRV_PULSE_SEQ_MASK 0x00007fff 460 461/* Indicate to the firmware not to go into the 462 * OS absent when it is not getting driver pulse. 463 * This is used for debugging. */ 464#define BCE_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE 0x00080000 465 466#define BCE_DEV_INFO_SIGNATURE 0x00000020 467#define BCE_DEV_INFO_SIGNATURE_MAGIC 0x44564900 468#define BCE_DEV_INFO_SIGNATURE_MAGIC_MASK 0xffffff00 469#define BCE_DEV_INFO_FEATURE_CFG_VALID 0x01 470#define BCE_DEV_INFO_SECONDARY_PORT 0x80 471#define BCE_DEV_INFO_DRV_ALWAYS_ALIVE 0x40 472 473#define BCE_SHARED_HW_CFG_PART_NUM 0x00000024 474 475#define BCE_SHARED_HW_CFG_POWER_DISSIPATED 0x00000034 476#define BCE_SHARED_HW_CFG_POWER_STATE_D3_MASK 0xff000000 477#define BCE_SHARED_HW_CFG_POWER_STATE_D2_MASK 0xff0000 478#define BCE_SHARED_HW_CFG_POWER_STATE_D1_MASK 0xff00 479#define BCE_SHARED_HW_CFG_POWER_STATE_D0_MASK 0xff 480 481#define BCE_SHARED_HW_CFG_POWER_CONSUMED 0x00000038 482#define BCE_SHARED_HW_CFG_CONFIG 0x0000003c 483#define BCE_SHARED_HW_CFG_DESIGN_NIC 0 484#define BCE_SHARED_HW_CFG_DESIGN_LOM 0x1 485#define BCE_SHARED_HW_CFG_PHY_COPPER 0 486#define BCE_SHARED_HW_CFG_PHY_FIBER 0x2 487#define BCE_SHARED_HW_CFG_PHY_2_5G 0x20 488#define BCE_SHARED_HW_CFG_PHY_BACKPLANE 0x40 489#define BCE_SHARED_HW_CFG_LED_MODE_SHIFT_BITS 8 490#define BCE_SHARED_HW_CFG_LED_MODE_MASK 0x300 491#define BCE_SHARED_HW_CFG_LED_MODE_MAC 0 492#define BCE_SHARED_HW_CFG_LED_MODE_GPHY1 0x100 493#define BCE_SHARED_HW_CFG_LED_MODE_GPHY2 0x200 494 495#define BCE_SHARED_HW_CFG_CONFIG2 0x00000040 496#define BCE_SHARED_HW_CFG2_NVM_SIZE_MASK 0x00fff000 497 498#define BCE_DEV_INFO_BC_REV 0x0000004c 499 500#define BCE_PORT_HW_CFG_MAC_UPPER 0x00000050 501#define BCE_PORT_HW_CFG_UPPERMAC_MASK 0xffff 502 503#define BCE_PORT_HW_CFG_MAC_LOWER 0x00000054 504#define BCE_PORT_HW_CFG_CONFIG 0x00000058 505#define BCE_PORT_HW_CFG_CFG_TXCTL3_MASK 0x0000ffff 506#define BCE_PORT_HW_CFG_CFG_DFLT_LINK_MASK 0x001f0000 507#define BCE_PORT_HW_CFG_CFG_DFLT_LINK_AN 0x00000000 508#define BCE_PORT_HW_CFG_CFG_DFLT_LINK_1G 0x00030000 509#define BCE_PORT_HW_CFG_CFG_DFLT_LINK_2_5G 0x00040000 510 511#define BCE_PORT_HW_CFG_IMD_MAC_A_UPPER 0x00000068 512#define BCE_PORT_HW_CFG_IMD_MAC_A_LOWER 0x0000006c 513#define BCE_PORT_HW_CFG_IMD_MAC_B_UPPER 0x00000070 514#define BCE_PORT_HW_CFG_IMD_MAC_B_LOWER 0x00000074 515#define BCE_PORT_HW_CFG_ISCSI_MAC_UPPER 0x00000078 516#define BCE_PORT_HW_CFG_ISCSI_MAC_LOWER 0x0000007c 517 518#define BCE_DEV_INFO_PER_PORT_HW_CONFIG2 0x000000b4 519 520#define BCE_DEV_INFO_FORMAT_REV 0x000000c4 521#define BCE_DEV_INFO_FORMAT_REV_MASK 0xff000000 522#define BCE_DEV_INFO_FORMAT_REV_ID ('A' << 24) 523 524#define BCE_SHARED_FEATURE 0x000000c8 525#define BCE_SHARED_FEATURE_MASK 0xffffffff 526 527#define BCE_PORT_FEATURE 0x000000d8 528#define BCE_PORT2_FEATURE 0x00000014c 529#define BCE_PORT_FEATURE_WOL_ENABLED 0x01000000 530#define BCE_PORT_FEATURE_MBA_ENABLED 0x02000000 531#define BCE_PORT_FEATURE_ASF_ENABLED 0x04000000 532#define BCE_PORT_FEATURE_IMD_ENABLED 0x08000000 533#define BCE_PORT_FEATURE_BAR1_SIZE_MASK 0xf 534#define BCE_PORT_FEATURE_BAR1_SIZE_DISABLED 0x0 535#define BCE_PORT_FEATURE_BAR1_SIZE_64K 0x1 536#define BCE_PORT_FEATURE_BAR1_SIZE_128K 0x2 537#define BCE_PORT_FEATURE_BAR1_SIZE_256K 0x3 538#define BCE_PORT_FEATURE_BAR1_SIZE_512K 0x4 539#define BCE_PORT_FEATURE_BAR1_SIZE_1M 0x5 540#define BCE_PORT_FEATURE_BAR1_SIZE_2M 0x6 541#define BCE_PORT_FEATURE_BAR1_SIZE_4M 0x7 542#define BCE_PORT_FEATURE_BAR1_SIZE_8M 0x8 543#define BCE_PORT_FEATURE_BAR1_SIZE_16M 0x9 544#define BCE_PORT_FEATURE_BAR1_SIZE_32M 0xa 545#define BCE_PORT_FEATURE_BAR1_SIZE_64M 0xb 546#define BCE_PORT_FEATURE_BAR1_SIZE_128M 0xc 547#define BCE_PORT_FEATURE_BAR1_SIZE_256M 0xd 548#define BCE_PORT_FEATURE_BAR1_SIZE_512M 0xe 549#define BCE_PORT_FEATURE_BAR1_SIZE_1G 0xf 550 551#define BCE_PORT_FEATURE_WOL 0xdc 552#define BCE_PORT2_FEATURE_WOL 0x150 553#define BCE_PORT_FEATURE_WOL_DEFAULT_SHIFT_BITS 4 554#define BCE_PORT_FEATURE_WOL_DEFAULT_MASK 0x30 555#define BCE_PORT_FEATURE_WOL_DEFAULT_DISABLE 0 556#define BCE_PORT_FEATURE_WOL_DEFAULT_MAGIC 0x10 557#define BCE_PORT_FEATURE_WOL_DEFAULT_ACPI 0x20 558#define BCE_PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI 0x30 559#define BCE_PORT_FEATURE_WOL_LINK_SPEED_MASK 0xf 560#define BCE_PORT_FEATURE_WOL_LINK_SPEED_AUTONEG 0 561#define BCE_PORT_FEATURE_WOL_LINK_SPEED_10HALF 1 562#define BCE_PORT_FEATURE_WOL_LINK_SPEED_10FULL 2 563#define BCE_PORT_FEATURE_WOL_LINK_SPEED_100HALF 3 564#define BCE_PORT_FEATURE_WOL_LINK_SPEED_100FULL 4 565#define BCE_PORT_FEATURE_WOL_LINK_SPEED_1000HALF 5 566#define BCE_PORT_FEATURE_WOL_LINK_SPEED_1000FULL 6 567#define BCE_PORT_FEATURE_WOL_AUTONEG_ADVERTISE_1000 0x40 568#define BCE_PORT_FEATURE_WOL_RESERVED_PAUSE_CAP 0x400 569#define BCE_PORT_FEATURE_WOL_RESERVED_ASYM_PAUSE_CAP 0x800 570 571#define BCE_PORT_FEATURE_MBA 0xe0 572#define BCE_PORT2_FEATURE_MBA 0x154 573#define BCE_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT_BITS 0 574#define BCE_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x3 575#define BCE_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0 576#define BCE_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 1 577#define BCE_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 2 578#define BCE_PORT_FEATURE_MBA_LINK_SPEED_SHIFT_BITS 2 579#define BCE_PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3c 580#define BCE_PORT_FEATURE_MBA_LINK_SPEED_AUTONEG 0 581#define BCE_PORT_FEATURE_MBA_LINK_SPEED_10HALF 0x4 582#define BCE_PORT_FEATURE_MBA_LINK_SPEED_10FULL 0x8 583#define BCE_PORT_FEATURE_MBA_LINK_SPEED_100HALF 0xc 584#define BCE_PORT_FEATURE_MBA_LINK_SPEED_100FULL 0x10 585#define BCE_PORT_FEATURE_MBA_LINK_SPEED_1000HALF 0x14 586#define BCE_PORT_FEATURE_MBA_LINK_SPEED_1000FULL 0x18 587#define BCE_PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x40 588#define BCE_PORT_FEATURE_MBA_HOTKEY_CTRL_S 0 589#define BCE_PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x80 590#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT_BITS 8 591#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0xff00 592#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0 593#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_1K 0x100 594#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x200 595#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x300 596#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x400 597#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x500 598#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x600 599#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x700 600#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x800 601#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x900 602#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0xa00 603#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0xb00 604#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0xc00 605#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0xd00 606#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0xe00 607#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0xf00 608#define BCE_PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT_BITS 16 609#define BCE_PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0xf0000 610#define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT_BITS 20 611#define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x300000 612#define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0 613#define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x100000 614#define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x200000 615#define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x300000 616 617#define BCE_PORT_FEATURE_IMD 0xe4 618#define BCE_PORT2_FEATURE_IMD 0x158 619#define BCE_PORT_FEATURE_IMD_LINK_OVERRIDE_DEFAULT 0 620#define BCE_PORT_FEATURE_IMD_LINK_OVERRIDE_ENABLE 1 621 622#define BCE_PORT_FEATURE_VLAN 0xe8 623#define BCE_PORT2_FEATURE_VLAN 0x15c 624#define BCE_PORT_FEATURE_MBA_VLAN_TAG_MASK 0xffff 625#define BCE_PORT_FEATURE_MBA_VLAN_ENABLE 0x10000 626 627#define BCE_BC_STATE_RESET_TYPE 0x000001c0 628#define BCE_BC_STATE_RESET_TYPE_SIG 0x00005254 629#define BCE_BC_STATE_RESET_TYPE_SIG_MASK 0x0000ffff 630#define BCE_BC_STATE_RESET_TYPE_NONE (BCE_BC_STATE_RESET_TYPE_SIG | \ 631 0x00010000) 632#define BCE_BC_STATE_RESET_TYPE_PCI (BCE_BC_STATE_RESET_TYPE_SIG | \ 633 0x00020000) 634#define BCE_BC_STATE_RESET_TYPE_VAUX (BCE_BC_STATE_RESET_TYPE_SIG | \ 635 0x00030000) 636#define BCE_BC_STATE_RESET_TYPE_DRV_MASK DRV_MSG_CODE 637#define BCE_BC_STATE_RESET_TYPE_DRV_RESET (BCE_BC_STATE_RESET_TYPE_SIG | \ 638 DRV_MSG_CODE_RESET) 639#define BCE_BC_STATE_RESET_TYPE_DRV_UNLOAD (BCE_BC_STATE_RESET_TYPE_SIG | \ 640 DRV_MSG_CODE_UNLOAD) 641#define BCE_BC_STATE_RESET_TYPE_DRV_SHUTDOWN (BCE_BC_STATE_RESET_TYPE_SIG | \ 642 DRV_MSG_CODE_SHUTDOWN) 643#define BCE_BC_STATE_RESET_TYPE_DRV_WOL (BCE_BC_STATE_RESET_TYPE_SIG | \ 644 DRV_MSG_CODE_WOL) 645#define BCE_BC_STATE_RESET_TYPE_DRV_DIAG (BCE_BC_STATE_RESET_TYPE_SIG | \ 646 DRV_MSG_CODE_DIAG) 647#define BCE_BC_STATE_RESET_TYPE_VALUE(msg) (BCE_BC_STATE_RESET_TYPE_SIG | \ 648 (msg)) 649 650#define BCE_BC_STATE 0x000001c4 651#define BCE_BC_STATE_ERR_MASK 0x0000ff00 652#define BCE_BC_STATE_SIGN 0x42530000 653#define BCE_BC_STATE_SIGN_MASK 0xffff0000 654#define BCE_BC_STATE_BC1_START (BCE_BC_STATE_SIGN | 0x1) 655#define BCE_BC_STATE_GET_NVM_CFG1 (BCE_BC_STATE_SIGN | 0x2) 656#define BCE_BC_STATE_PROG_BAR (BCE_BC_STATE_SIGN | 0x3) 657#define BCE_BC_STATE_INIT_VID (BCE_BC_STATE_SIGN | 0x4) 658#define BCE_BC_STATE_GET_NVM_CFG2 (BCE_BC_STATE_SIGN | 0x5) 659#define BCE_BC_STATE_APPLY_WKARND (BCE_BC_STATE_SIGN | 0x6) 660#define BCE_BC_STATE_LOAD_BC2 (BCE_BC_STATE_SIGN | 0x7) 661#define BCE_BC_STATE_GOING_BC2 (BCE_BC_STATE_SIGN | 0x8) 662#define BCE_BC_STATE_GOING_DIAG (BCE_BC_STATE_SIGN | 0x9) 663#define BCE_BC_STATE_RT_FINAL_INIT (BCE_BC_STATE_SIGN | 0x81) 664#define BCE_BC_STATE_RT_WKARND (BCE_BC_STATE_SIGN | 0x82) 665#define BCE_BC_STATE_RT_DRV_PULSE (BCE_BC_STATE_SIGN | 0x83) 666#define BCE_BC_STATE_RT_FIOEVTS (BCE_BC_STATE_SIGN | 0x84) 667#define BCE_BC_STATE_RT_DRV_CMD (BCE_BC_STATE_SIGN | 0x85) 668#define BCE_BC_STATE_RT_LOW_POWER (BCE_BC_STATE_SIGN | 0x86) 669#define BCE_BC_STATE_RT_SET_WOL (BCE_BC_STATE_SIGN | 0x87) 670#define BCE_BC_STATE_RT_OTHER_FW (BCE_BC_STATE_SIGN | 0x88) 671#define BCE_BC_STATE_RT_GOING_D3 (BCE_BC_STATE_SIGN | 0x89) 672#define BCE_BC_STATE_ERR_BAD_VERSION (BCE_BC_STATE_SIGN | 0x0100) 673#define BCE_BC_STATE_ERR_BAD_BC2_CRC (BCE_BC_STATE_SIGN | 0x0200) 674#define BCE_BC_STATE_ERR_BC1_LOOP (BCE_BC_STATE_SIGN | 0x0300) 675#define BCE_BC_STATE_ERR_UNKNOWN_CMD (BCE_BC_STATE_SIGN | 0x0400) 676#define BCE_BC_STATE_ERR_DRV_DEAD (BCE_BC_STATE_SIGN | 0x0500) 677#define BCE_BC_STATE_ERR_NO_RXP (BCE_BC_STATE_SIGN | 0x0600) 678#define BCE_BC_STATE_ERR_TOO_MANY_RBUF (BCE_BC_STATE_SIGN | 0x0700) 679 680#define BCE_BC_STATE_DEBUG_CMD 0x1dc 681#define BCE_BC_STATE_BC_DBG_CMD_SIGNATURE 0x42440000 682#define BCE_BC_STATE_BC_DBG_CMD_SIGNATURE_MASK 0xffff0000 683#define BCE_BC_STATE_BC_DBG_CMD_LOOP_CNT_MASK 0xffff 684#define BCE_BC_STATE_BC_DBG_CMD_LOOP_INFINITE 0xffff 685 686#define HOST_VIEW_SHMEM_BASE 0x167c00 687 688/* 689 * PCI registers defined in the PCI 2.2 spec. 690 */ 691#define BCE_PCI_PCIX_CMD 0x42 692 693 694/****************************************************************************/ 695/* Convenience definitions. */ 696/****************************************************************************/ 697#define BCE_PRINTF(fmt, args...) device_printf(sc->bce_dev, fmt, ##args) 698 699#define BCE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->bce_mtx, _name, MTX_NETWORK_LOCK, MTX_DEF) 700#define BCE_LOCK(_sc) mtx_lock(&(_sc)->bce_mtx) 701#define BCE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->bce_mtx, MA_OWNED) 702#define BCE_UNLOCK(_sc) mtx_unlock(&(_sc)->bce_mtx) 703#define BCE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->bce_mtx) 704 705#define REG_WR(sc, reg, val) bus_space_write_4(sc->bce_btag, sc->bce_bhandle, reg, val) 706#define REG_WR16(sc, reg, val) bus_space_write_2(sc->bce_btag, sc->bce_bhandle, reg, val) 707#define REG_RD(sc, reg) bus_space_read_4(sc->bce_btag, sc->bce_bhandle, reg) 708#define REG_RD_IND(sc, offset) bce_reg_rd_ind(sc, offset) 709#define REG_WR_IND(sc, offset, val) bce_reg_wr_ind(sc, offset, val) 710#define CTX_WR(sc, cid_addr, offset, val) bce_ctx_wr(sc, cid_addr, offset, val) 711#define BCE_SETBIT(sc, reg, x) REG_WR(sc, reg, (REG_RD(sc, reg) | (x))) 712#define BCE_CLRBIT(sc, reg, x) REG_WR(sc, reg, (REG_RD(sc, reg) & ~(x))) 713#define PCI_SETBIT(dev, reg, x, s) pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | (x)), s) 714#define PCI_CLRBIT(dev, reg, x, s) pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s) 715 716#define BCE_STATS(x) (u_long) stats->stat_ ## x ## _lo 717#if (BUS_SPACE_MAXADDR > 0xFFFFFFFF) 718#define BCE_ADDR_LO(y) ((u64) (y) & 0xFFFFFFFF) 719#define BCE_ADDR_HI(y) ((u64) (y) >> 32) 720#else 721#define BCE_ADDR_LO(y) ((u32)y) 722#define BCE_ADDR_HI(y) (0) 723#endif 724 725 726/* 727 * The following data structures are generated from RTL code. 728 * Do not modify any values below this line. 729 */ 730 731/****************************************************************************/ 732/* Do not modify any of the following data structures, they are generated */ 733/* from RTL code. */ 734/* */ 735/* Begin machine generated definitions. */ 736/****************************************************************************/ 737 738/* 739 * tx_bd definition 740 */ 741struct tx_bd { 742 u32 tx_bd_haddr_hi; 743 u32 tx_bd_haddr_lo; 744 u32 tx_bd_mss_nbytes; 745 u16 tx_bd_flags; 746 u16 tx_bd_vlan_tag; 747 #define TX_BD_FLAGS_CONN_FAULT (1<<0) 748 #define TX_BD_FLAGS_TCP_UDP_CKSUM (1<<1) 749 #define TX_BD_FLAGS_IP_CKSUM (1<<2) 750 #define TX_BD_FLAGS_VLAN_TAG (1<<3) 751 #define TX_BD_FLAGS_COAL_NOW (1<<4) 752 #define TX_BD_FLAGS_DONT_GEN_CRC (1<<5) 753 #define TX_BD_FLAGS_END (1<<6) 754 #define TX_BD_FLAGS_START (1<<7) 755 #define TX_BD_FLAGS_SW_OPTION_WORD (0x1f<<8) 756 #define TX_BD_FLAGS_SW_FLAGS (1<<13) 757 #define TX_BD_FLAGS_SW_SNAP (1<<14) 758 #define TX_BD_FLAGS_SW_LSO (1<<15) 759 760}; 761 762 763/* 764 * rx_bd definition 765 */ 766struct rx_bd { 767 u32 rx_bd_haddr_hi; 768 u32 rx_bd_haddr_lo; 769 u32 rx_bd_len; 770 u32 rx_bd_flags; 771 #define RX_BD_FLAGS_NOPUSH (1<<0) 772 #define RX_BD_FLAGS_DUMMY (1<<1) 773 #define RX_BD_FLAGS_END (1<<2) 774 #define RX_BD_FLAGS_START (1<<3) 775 776}; 777 778 779/* 780 * status_block definition 781 */ 782struct status_block { 783 u32 status_attn_bits; 784 #define STATUS_ATTN_BITS_LINK_STATE (1L<<0) 785 #define STATUS_ATTN_BITS_TX_SCHEDULER_ABORT (1L<<1) 786 #define STATUS_ATTN_BITS_TX_BD_READ_ABORT (1L<<2) 787 #define STATUS_ATTN_BITS_TX_BD_CACHE_ABORT (1L<<3) 788 #define STATUS_ATTN_BITS_TX_PROCESSOR_ABORT (1L<<4) 789 #define STATUS_ATTN_BITS_TX_DMA_ABORT (1L<<5) 790 #define STATUS_ATTN_BITS_TX_PATCHUP_ABORT (1L<<6) 791 #define STATUS_ATTN_BITS_TX_ASSEMBLER_ABORT (1L<<7) 792 #define STATUS_ATTN_BITS_RX_PARSER_MAC_ABORT (1L<<8) 793 #define STATUS_ATTN_BITS_RX_PARSER_CATCHUP_ABORT (1L<<9) 794 #define STATUS_ATTN_BITS_RX_MBUF_ABORT (1L<<10) 795 #define STATUS_ATTN_BITS_RX_LOOKUP_ABORT (1L<<11) 796 #define STATUS_ATTN_BITS_RX_PROCESSOR_ABORT (1L<<12) 797 #define STATUS_ATTN_BITS_RX_V2P_ABORT (1L<<13) 798 #define STATUS_ATTN_BITS_RX_BD_CACHE_ABORT (1L<<14) 799 #define STATUS_ATTN_BITS_RX_DMA_ABORT (1L<<15) 800 #define STATUS_ATTN_BITS_COMPLETION_ABORT (1L<<16) 801 #define STATUS_ATTN_BITS_HOST_COALESCE_ABORT (1L<<17) 802 #define STATUS_ATTN_BITS_MAILBOX_QUEUE_ABORT (1L<<18) 803 #define STATUS_ATTN_BITS_CONTEXT_ABORT (1L<<19) 804 #define STATUS_ATTN_BITS_CMD_SCHEDULER_ABORT (1L<<20) 805 #define STATUS_ATTN_BITS_CMD_PROCESSOR_ABORT (1L<<21) 806 #define STATUS_ATTN_BITS_MGMT_PROCESSOR_ABORT (1L<<22) 807 #define STATUS_ATTN_BITS_MAC_ABORT (1L<<23) 808 #define STATUS_ATTN_BITS_TIMER_ABORT (1L<<24) 809 #define STATUS_ATTN_BITS_DMAE_ABORT (1L<<25) 810 #define STATUS_ATTN_BITS_FLSH_ABORT (1L<<26) 811 #define STATUS_ATTN_BITS_GRC_ABORT (1L<<27) 812 #define STATUS_ATTN_BITS_PARITY_ERROR (1L<<31) 813 814 u32 status_attn_bits_ack; 815#if defined(__BIG_ENDIAN) 816 u16 status_tx_quick_consumer_index0; 817 u16 status_tx_quick_consumer_index1; 818 u16 status_tx_quick_consumer_index2; 819 u16 status_tx_quick_consumer_index3; 820 u16 status_rx_quick_consumer_index0; 821 u16 status_rx_quick_consumer_index1; 822 u16 status_rx_quick_consumer_index2; 823 u16 status_rx_quick_consumer_index3; 824 u16 status_rx_quick_consumer_index4; 825 u16 status_rx_quick_consumer_index5; 826 u16 status_rx_quick_consumer_index6; 827 u16 status_rx_quick_consumer_index7; 828 u16 status_rx_quick_consumer_index8; 829 u16 status_rx_quick_consumer_index9; 830 u16 status_rx_quick_consumer_index10; 831 u16 status_rx_quick_consumer_index11; 832 u16 status_rx_quick_consumer_index12; 833 u16 status_rx_quick_consumer_index13; 834 u16 status_rx_quick_consumer_index14; 835 u16 status_rx_quick_consumer_index15; 836 u16 status_completion_producer_index; 837 u16 status_cmd_consumer_index; 838 u16 status_idx; 839 u16 status_unused; 840#elif defined(__LITTLE_ENDIAN) 841 u16 status_tx_quick_consumer_index1; 842 u16 status_tx_quick_consumer_index0; 843 u16 status_tx_quick_consumer_index3; 844 u16 status_tx_quick_consumer_index2; 845 u16 status_rx_quick_consumer_index1; 846 u16 status_rx_quick_consumer_index0; 847 u16 status_rx_quick_consumer_index3; 848 u16 status_rx_quick_consumer_index2; 849 u16 status_rx_quick_consumer_index5; 850 u16 status_rx_quick_consumer_index4; 851 u16 status_rx_quick_consumer_index7; 852 u16 status_rx_quick_consumer_index6; 853 u16 status_rx_quick_consumer_index9; 854 u16 status_rx_quick_consumer_index8; 855 u16 status_rx_quick_consumer_index11; 856 u16 status_rx_quick_consumer_index10; 857 u16 status_rx_quick_consumer_index13; 858 u16 status_rx_quick_consumer_index12; 859 u16 status_rx_quick_consumer_index15; 860 u16 status_rx_quick_consumer_index14; 861 u16 status_cmd_consumer_index; 862 u16 status_completion_producer_index; 863 u16 status_unused; 864 u16 status_idx; 865#endif 866}; 867 868 869/* 870 * statistics_block definition 871 */ 872struct statistics_block { 873 u32 stat_IfHCInOctets_hi; 874 u32 stat_IfHCInOctets_lo; 875 u32 stat_IfHCInBadOctets_hi; 876 u32 stat_IfHCInBadOctets_lo; 877 u32 stat_IfHCOutOctets_hi; 878 u32 stat_IfHCOutOctets_lo; 879 u32 stat_IfHCOutBadOctets_hi; 880 u32 stat_IfHCOutBadOctets_lo; 881 u32 stat_IfHCInUcastPkts_hi; 882 u32 stat_IfHCInUcastPkts_lo; 883 u32 stat_IfHCInMulticastPkts_hi; 884 u32 stat_IfHCInMulticastPkts_lo; 885 u32 stat_IfHCInBroadcastPkts_hi; 886 u32 stat_IfHCInBroadcastPkts_lo; 887 u32 stat_IfHCOutUcastPkts_hi; 888 u32 stat_IfHCOutUcastPkts_lo; 889 u32 stat_IfHCOutMulticastPkts_hi; 890 u32 stat_IfHCOutMulticastPkts_lo; 891 u32 stat_IfHCOutBroadcastPkts_hi; 892 u32 stat_IfHCOutBroadcastPkts_lo; 893 u32 stat_emac_tx_stat_dot3statsinternalmactransmiterrors; 894 u32 stat_Dot3StatsCarrierSenseErrors; 895 u32 stat_Dot3StatsFCSErrors; 896 u32 stat_Dot3StatsAlignmentErrors; 897 u32 stat_Dot3StatsSingleCollisionFrames; 898 u32 stat_Dot3StatsMultipleCollisionFrames; 899 u32 stat_Dot3StatsDeferredTransmissions; 900 u32 stat_Dot3StatsExcessiveCollisions; 901 u32 stat_Dot3StatsLateCollisions; 902 u32 stat_EtherStatsCollisions; 903 u32 stat_EtherStatsFragments; 904 u32 stat_EtherStatsJabbers; 905 u32 stat_EtherStatsUndersizePkts; 906 u32 stat_EtherStatsOverrsizePkts; 907 u32 stat_EtherStatsPktsRx64Octets; 908 u32 stat_EtherStatsPktsRx65Octetsto127Octets; 909 u32 stat_EtherStatsPktsRx128Octetsto255Octets; 910 u32 stat_EtherStatsPktsRx256Octetsto511Octets; 911 u32 stat_EtherStatsPktsRx512Octetsto1023Octets; 912 u32 stat_EtherStatsPktsRx1024Octetsto1522Octets; 913 u32 stat_EtherStatsPktsRx1523Octetsto9022Octets; 914 u32 stat_EtherStatsPktsTx64Octets; 915 u32 stat_EtherStatsPktsTx65Octetsto127Octets; 916 u32 stat_EtherStatsPktsTx128Octetsto255Octets; 917 u32 stat_EtherStatsPktsTx256Octetsto511Octets; 918 u32 stat_EtherStatsPktsTx512Octetsto1023Octets; 919 u32 stat_EtherStatsPktsTx1024Octetsto1522Octets; 920 u32 stat_EtherStatsPktsTx1523Octetsto9022Octets; 921 u32 stat_XonPauseFramesReceived; 922 u32 stat_XoffPauseFramesReceived; 923 u32 stat_OutXonSent; 924 u32 stat_OutXoffSent; 925 u32 stat_FlowControlDone; 926 u32 stat_MacControlFramesReceived; 927 u32 stat_XoffStateEntered; 928 u32 stat_IfInFramesL2FilterDiscards; 929 u32 stat_IfInRuleCheckerDiscards; 930 u32 stat_IfInFTQDiscards; 931 u32 stat_IfInMBUFDiscards; 932 u32 stat_IfInRuleCheckerP4Hit; 933 u32 stat_CatchupInRuleCheckerDiscards; 934 u32 stat_CatchupInFTQDiscards; 935 u32 stat_CatchupInMBUFDiscards; 936 u32 stat_CatchupInRuleCheckerP4Hit; 937 u32 stat_GenStat00; 938 u32 stat_GenStat01; 939 u32 stat_GenStat02; 940 u32 stat_GenStat03; 941 u32 stat_GenStat04; 942 u32 stat_GenStat05; 943 u32 stat_GenStat06; 944 u32 stat_GenStat07; 945 u32 stat_GenStat08; 946 u32 stat_GenStat09; 947 u32 stat_GenStat10; 948 u32 stat_GenStat11; 949 u32 stat_GenStat12; 950 u32 stat_GenStat13; 951 u32 stat_GenStat14; 952 u32 stat_GenStat15; 953}; 954 955 956/* 957 * l2_fhdr definition 958 */ 959struct l2_fhdr { 960 u32 l2_fhdr_status; 961 #define L2_FHDR_STATUS_RULE_CLASS (0x7<<0) 962 #define L2_FHDR_STATUS_RULE_P2 (1<<3) 963 #define L2_FHDR_STATUS_RULE_P3 (1<<4) 964 #define L2_FHDR_STATUS_RULE_P4 (1<<5) 965 #define L2_FHDR_STATUS_L2_VLAN_TAG (1<<6) 966 #define L2_FHDR_STATUS_L2_LLC_SNAP (1<<7) 967 #define L2_FHDR_STATUS_RSS_HASH (1<<8) 968 #define L2_FHDR_STATUS_IP_DATAGRAM (1<<13) 969 #define L2_FHDR_STATUS_TCP_SEGMENT (1<<14) 970 #define L2_FHDR_STATUS_UDP_DATAGRAM (1<<15) 971 972 #define L2_FHDR_ERRORS_BAD_CRC (1<<17) 973 #define L2_FHDR_ERRORS_PHY_DECODE (1<<18) 974 #define L2_FHDR_ERRORS_ALIGNMENT (1<<19) 975 #define L2_FHDR_ERRORS_TOO_SHORT (1<<20) 976 #define L2_FHDR_ERRORS_GIANT_FRAME (1<<21) 977 #define L2_FHDR_ERRORS_TCP_XSUM (1<<28) 978 #define L2_FHDR_ERRORS_UDP_XSUM (1<<31) 979 980 u32 l2_fhdr_hash; 981#if defined(__BIG_ENDIAN) 982 u16 l2_fhdr_pkt_len; 983 u16 l2_fhdr_vlan_tag; 984 u16 l2_fhdr_ip_xsum; 985 u16 l2_fhdr_tcp_udp_xsum; 986#elif defined(__LITTLE_ENDIAN) 987 u16 l2_fhdr_vlan_tag; 988 u16 l2_fhdr_pkt_len; 989 u16 l2_fhdr_tcp_udp_xsum; 990 u16 l2_fhdr_ip_xsum; 991#endif 992}; 993 994 995/* 996 * l2_context definition 997 */ 998#define BCE_L2CTX_TYPE 0x00000000 999#define BCE_L2CTX_TYPE_SIZE_L2 ((0xc0/0x20)<<16) 1000#define BCE_L2CTX_TYPE_TYPE (0xf<<28) 1001#define BCE_L2CTX_TYPE_TYPE_EMPTY (0<<28) 1002#define BCE_L2CTX_TYPE_TYPE_L2 (1<<28) 1003 1004#define BCE_L2CTX_TX_HOST_BIDX 0x00000088 1005#define BCE_L2CTX_EST_NBD 0x00000088 1006#define BCE_L2CTX_CMD_TYPE 0x00000088 1007#define BCE_L2CTX_CMD_TYPE_TYPE (0xf<<24) 1008#define BCE_L2CTX_CMD_TYPE_TYPE_L2 (0<<24) 1009#define BCE_L2CTX_CMD_TYPE_TYPE_TCP (1<<24) 1010 1011#define BCE_L2CTX_TX_HOST_BSEQ 0x00000090 1012#define BCE_L2CTX_TSCH_BSEQ 0x00000094 1013#define BCE_L2CTX_TBDR_BSEQ 0x00000098 1014#define BCE_L2CTX_TBDR_BOFF 0x0000009c 1015#define BCE_L2CTX_TBDR_BIDX 0x0000009c 1016#define BCE_L2CTX_TBDR_BHADDR_HI 0x000000a0 1017#define BCE_L2CTX_TBDR_BHADDR_LO 0x000000a4 1018#define BCE_L2CTX_TXP_BOFF 0x000000a8 1019#define BCE_L2CTX_TXP_BIDX 0x000000a8 1020#define BCE_L2CTX_TXP_BSEQ 0x000000ac 1021 1022 1023/* 1024 * l2_bd_chain_context definition 1025 */ 1026#define BCE_L2CTX_BD_PRE_READ 0x00000000 1027#define BCE_L2CTX_CTX_SIZE 0x00000000 1028#define BCE_L2CTX_CTX_TYPE 0x00000000 1029#define BCE_L2CTX_CTX_TYPE_SIZE_L2 ((0x20/20)<<16) 1030#define BCE_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE (0xf<<28) 1031#define BCE_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_UNDEFINED (0<<28) 1032#define BCE_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE (1<<28) 1033 1034#define BCE_L2CTX_HOST_BDIDX 0x00000004 1035#define BCE_L2CTX_HOST_BSEQ 0x00000008 1036#define BCE_L2CTX_NX_BSEQ 0x0000000c 1037#define BCE_L2CTX_NX_BDHADDR_HI 0x00000010 1038#define BCE_L2CTX_NX_BDHADDR_LO 0x00000014 1039#define BCE_L2CTX_NX_BDIDX 0x00000018 1040 1041 1042/* 1043 * pci_config_l definition 1044 * offset: 0000 1045 */ 1046#define BCE_PCICFG_MISC_CONFIG 0x00000068 1047#define BCE_PCICFG_MISC_CONFIG_TARGET_BYTE_SWAP (1L<<2) 1048#define BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP (1L<<3) 1049#define BCE_PCICFG_MISC_CONFIG_CLOCK_CTL_ENA (1L<<5) 1050#define BCE_PCICFG_MISC_CONFIG_TARGET_GRC_WORD_SWAP (1L<<6) 1051#define BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA (1L<<7) 1052#define BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ (1L<<8) 1053#define BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY (1L<<9) 1054#define BCE_PCICFG_MISC_CONFIG_ASIC_METAL_REV (0xffL<<16) 1055#define BCE_PCICFG_MISC_CONFIG_ASIC_BASE_REV (0xfL<<24) 1056#define BCE_PCICFG_MISC_CONFIG_ASIC_ID (0xfL<<28) 1057#define BCE_PCICFG_MISC_CONFIG_ASIC_REV (0xffffL<<16) 1058 1059#define BCE_PCICFG_MISC_STATUS 0x0000006c 1060#define BCE_PCICFG_MISC_STATUS_INTA_VALUE (1L<<0) 1061#define BCE_PCICFG_MISC_STATUS_32BIT_DET (1L<<1) 1062#define BCE_PCICFG_MISC_STATUS_M66EN (1L<<2) 1063#define BCE_PCICFG_MISC_STATUS_PCIX_DET (1L<<3) 1064#define BCE_PCICFG_MISC_STATUS_PCIX_SPEED (0x3L<<4) 1065#define BCE_PCICFG_MISC_STATUS_PCIX_SPEED_66 (0L<<4) 1066#define BCE_PCICFG_MISC_STATUS_PCIX_SPEED_100 (1L<<4) 1067#define BCE_PCICFG_MISC_STATUS_PCIX_SPEED_133 (2L<<4) 1068#define BCE_PCICFG_MISC_STATUS_PCIX_SPEED_PCI_MODE (3L<<4) 1069 1070#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS 0x00000070 1071#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET (0xfL<<0) 1072#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ (0L<<0) 1073#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ (1L<<0) 1074#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ (2L<<0) 1075#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ (3L<<0) 1076#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ (4L<<0) 1077#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ (5L<<0) 1078#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ (6L<<0) 1079#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ (7L<<0) 1080#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW (0xfL<<0) 1081#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE (1L<<6) 1082#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT (1L<<7) 1083#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC (0x7L<<8) 1084#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF (0L<<8) 1085#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12 (1L<<8) 1086#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6 (2L<<8) 1087#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62 (4L<<8) 1088#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PLAY_DEAD (1L<<11) 1089#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED (0xfL<<12) 1090#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100 (0L<<12) 1091#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80 (1L<<12) 1092#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50 (2L<<12) 1093#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40 (4L<<12) 1094#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25 (8L<<12) 1095#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP (1L<<16) 1096#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_PLL_STOP (1L<<17) 1097#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_18 (1L<<18) 1098#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_USE_SPD_DET (1L<<19) 1099#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED (0xfffL<<20) 1100 1101#define BCE_PCICFG_REG_WINDOW_ADDRESS 0x00000078 1102#define BCE_PCICFG_REG_WINDOW 0x00000080 1103#define BCE_PCICFG_INT_ACK_CMD 0x00000084 1104#define BCE_PCICFG_INT_ACK_CMD_INDEX (0xffffL<<0) 1105#define BCE_PCICFG_INT_ACK_CMD_INDEX_VALID (1L<<16) 1106#define BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM (1L<<17) 1107#define BCE_PCICFG_INT_ACK_CMD_MASK_INT (1L<<18) 1108 1109#define BCE_PCICFG_STATUS_BIT_SET_CMD 0x00000088 1110#define BCE_PCICFG_STATUS_BIT_CLEAR_CMD 0x0000008c 1111#define BCE_PCICFG_MAILBOX_QUEUE_ADDR 0x00000090 1112#define BCE_PCICFG_MAILBOX_QUEUE_DATA 0x00000094 1113 1114 1115/* 1116 * pci_reg definition 1117 * offset: 0x400 1118 */ 1119#define BCE_PCI_GRC_WINDOW_ADDR 0x00000400 1120#define BCE_PCI_GRC_WINDOW_ADDR_PCI_GRC_WINDOW_ADDR_VALUE (0x3ffffL<<8) 1121 1122#define BCE_PCI_CONFIG_1 0x00000404 1123#define BCE_PCI_CONFIG_1_READ_BOUNDARY (0x7L<<8) 1124#define BCE_PCI_CONFIG_1_READ_BOUNDARY_OFF (0L<<8) 1125#define BCE_PCI_CONFIG_1_READ_BOUNDARY_16 (1L<<8) 1126#define BCE_PCI_CONFIG_1_READ_BOUNDARY_32 (2L<<8) 1127#define BCE_PCI_CONFIG_1_READ_BOUNDARY_64 (3L<<8) 1128#define BCE_PCI_CONFIG_1_READ_BOUNDARY_128 (4L<<8) 1129#define BCE_PCI_CONFIG_1_READ_BOUNDARY_256 (5L<<8) 1130#define BCE_PCI_CONFIG_1_READ_BOUNDARY_512 (6L<<8) 1131#define BCE_PCI_CONFIG_1_READ_BOUNDARY_1024 (7L<<8) 1132#define BCE_PCI_CONFIG_1_WRITE_BOUNDARY (0x7L<<11) 1133#define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_OFF (0L<<11) 1134#define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_16 (1L<<11) 1135#define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_32 (2L<<11) 1136#define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_64 (3L<<11) 1137#define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_128 (4L<<11) 1138#define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_256 (5L<<11) 1139#define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_512 (6L<<11) 1140#define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_1024 (7L<<11) 1141 1142#define BCE_PCI_CONFIG_2 0x00000408 1143#define BCE_PCI_CONFIG_2_BAR1_SIZE (0xfL<<0) 1144#define BCE_PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0) 1145#define BCE_PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0) 1146#define BCE_PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0) 1147#define BCE_PCI_CONFIG_2_BAR1_SIZE_256K (3L<<0) 1148#define BCE_PCI_CONFIG_2_BAR1_SIZE_512K (4L<<0) 1149#define BCE_PCI_CONFIG_2_BAR1_SIZE_1M (5L<<0) 1150#define BCE_PCI_CONFIG_2_BAR1_SIZE_2M (6L<<0) 1151#define BCE_PCI_CONFIG_2_BAR1_SIZE_4M (7L<<0) 1152#define BCE_PCI_CONFIG_2_BAR1_SIZE_8M (8L<<0) 1153#define BCE_PCI_CONFIG_2_BAR1_SIZE_16M (9L<<0) 1154#define BCE_PCI_CONFIG_2_BAR1_SIZE_32M (10L<<0) 1155#define BCE_PCI_CONFIG_2_BAR1_SIZE_64M (11L<<0) 1156#define BCE_PCI_CONFIG_2_BAR1_SIZE_128M (12L<<0) 1157#define BCE_PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0) 1158#define BCE_PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0) 1159#define BCE_PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0) 1160#define BCE_PCI_CONFIG_2_BAR1_64ENA (1L<<4) 1161#define BCE_PCI_CONFIG_2_EXP_ROM_RETRY (1L<<5) 1162#define BCE_PCI_CONFIG_2_CFG_CYCLE_RETRY (1L<<6) 1163#define BCE_PCI_CONFIG_2_FIRST_CFG_DONE (1L<<7) 1164#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8) 1165#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8) 1166#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_1K (1L<<8) 1167#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_2K (2L<<8) 1168#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_4K (3L<<8) 1169#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_8K (4L<<8) 1170#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_16K (5L<<8) 1171#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_32K (6L<<8) 1172#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_64K (7L<<8) 1173#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_128K (8L<<8) 1174#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_256K (9L<<8) 1175#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_512K (10L<<8) 1176#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_1M (11L<<8) 1177#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_2M (12L<<8) 1178#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_4M (13L<<8) 1179#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_8M (14L<<8) 1180#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_16M (15L<<8) 1181#define BCE_PCI_CONFIG_2_MAX_SPLIT_LIMIT (0x1fL<<16) 1182#define BCE_PCI_CONFIG_2_MAX_READ_LIMIT (0x3L<<21) 1183#define BCE_PCI_CONFIG_2_MAX_READ_LIMIT_512 (0L<<21) 1184#define BCE_PCI_CONFIG_2_MAX_READ_LIMIT_1K (1L<<21) 1185#define BCE_PCI_CONFIG_2_MAX_READ_LIMIT_2K (2L<<21) 1186#define BCE_PCI_CONFIG_2_MAX_READ_LIMIT_4K (3L<<21) 1187#define BCE_PCI_CONFIG_2_FORCE_32_BIT_MSTR (1L<<23) 1188#define BCE_PCI_CONFIG_2_FORCE_32_BIT_TGT (1L<<24) 1189#define BCE_PCI_CONFIG_2_KEEP_REQ_ASSERT (1L<<25) 1190 1191#define BCE_PCI_CONFIG_3 0x0000040c 1192#define BCE_PCI_CONFIG_3_STICKY_BYTE (0xffL<<0) 1193#define BCE_PCI_CONFIG_3_FORCE_PME (1L<<24) 1194#define BCE_PCI_CONFIG_3_PME_STATUS (1L<<25) 1195#define BCE_PCI_CONFIG_3_PME_ENABLE (1L<<26) 1196#define BCE_PCI_CONFIG_3_PM_STATE (0x3L<<27) 1197#define BCE_PCI_CONFIG_3_VAUX_PRESET (1L<<30) 1198#define BCE_PCI_CONFIG_3_PCI_POWER (1L<<31) 1199 1200#define BCE_PCI_PM_DATA_A 0x00000410 1201#define BCE_PCI_PM_DATA_A_PM_DATA_0_PRG (0xffL<<0) 1202#define BCE_PCI_PM_DATA_A_PM_DATA_1_PRG (0xffL<<8) 1203#define BCE_PCI_PM_DATA_A_PM_DATA_2_PRG (0xffL<<16) 1204#define BCE_PCI_PM_DATA_A_PM_DATA_3_PRG (0xffL<<24) 1205 1206#define BCE_PCI_PM_DATA_B 0x00000414 1207#define BCE_PCI_PM_DATA_B_PM_DATA_4_PRG (0xffL<<0) 1208#define BCE_PCI_PM_DATA_B_PM_DATA_5_PRG (0xffL<<8) 1209#define BCE_PCI_PM_DATA_B_PM_DATA_6_PRG (0xffL<<16) 1210#define BCE_PCI_PM_DATA_B_PM_DATA_7_PRG (0xffL<<24) 1211 1212#define BCE_PCI_SWAP_DIAG0 0x00000418 1213#define BCE_PCI_SWAP_DIAG1 0x0000041c 1214#define BCE_PCI_EXP_ROM_ADDR 0x00000420 1215#define BCE_PCI_EXP_ROM_ADDR_ADDRESS (0x3fffffL<<2) 1216#define BCE_PCI_EXP_ROM_ADDR_REQ (1L<<31) 1217 1218#define BCE_PCI_EXP_ROM_DATA 0x00000424 1219#define BCE_PCI_VPD_INTF 0x00000428 1220#define BCE_PCI_VPD_INTF_INTF_REQ (1L<<0) 1221 1222#define BCE_PCI_VPD_ADDR_FLAG 0x0000042c 1223#define BCE_PCI_VPD_ADDR_FLAG_ADDRESS (0x1fff<<2) 1224#define BCE_PCI_VPD_ADDR_FLAG_WR (1<<15) 1225 1226#define BCE_PCI_VPD_DATA 0x00000430 1227#define BCE_PCI_ID_VAL1 0x00000434 1228#define BCE_PCI_ID_VAL1_DEVICE_ID (0xffffL<<0) 1229#define BCE_PCI_ID_VAL1_VENDOR_ID (0xffffL<<16) 1230 1231#define BCE_PCI_ID_VAL2 0x00000438 1232#define BCE_PCI_ID_VAL2_SUBSYSTEM_VENDOR_ID (0xffffL<<0) 1233#define BCE_PCI_ID_VAL2_SUBSYSTEM_ID (0xffffL<<16) 1234 1235#define BCE_PCI_ID_VAL3 0x0000043c 1236#define BCE_PCI_ID_VAL3_CLASS_CODE (0xffffffL<<0) 1237#define BCE_PCI_ID_VAL3_REVISION_ID (0xffL<<24) 1238 1239#define BCE_PCI_ID_VAL4 0x00000440 1240#define BCE_PCI_ID_VAL4_CAP_ENA (0xfL<<0) 1241#define BCE_PCI_ID_VAL4_CAP_ENA_0 (0L<<0) 1242#define BCE_PCI_ID_VAL4_CAP_ENA_1 (1L<<0) 1243#define BCE_PCI_ID_VAL4_CAP_ENA_2 (2L<<0) 1244#define BCE_PCI_ID_VAL4_CAP_ENA_3 (3L<<0) 1245#define BCE_PCI_ID_VAL4_CAP_ENA_4 (4L<<0) 1246#define BCE_PCI_ID_VAL4_CAP_ENA_5 (5L<<0) 1247#define BCE_PCI_ID_VAL4_CAP_ENA_6 (6L<<0) 1248#define BCE_PCI_ID_VAL4_CAP_ENA_7 (7L<<0) 1249#define BCE_PCI_ID_VAL4_CAP_ENA_8 (8L<<0) 1250#define BCE_PCI_ID_VAL4_CAP_ENA_9 (9L<<0) 1251#define BCE_PCI_ID_VAL4_CAP_ENA_10 (10L<<0) 1252#define BCE_PCI_ID_VAL4_CAP_ENA_11 (11L<<0) 1253#define BCE_PCI_ID_VAL4_CAP_ENA_12 (12L<<0) 1254#define BCE_PCI_ID_VAL4_CAP_ENA_13 (13L<<0) 1255#define BCE_PCI_ID_VAL4_CAP_ENA_14 (14L<<0) 1256#define BCE_PCI_ID_VAL4_CAP_ENA_15 (15L<<0) 1257#define BCE_PCI_ID_VAL4_PM_SCALE_PRG (0x3L<<6) 1258#define BCE_PCI_ID_VAL4_PM_SCALE_PRG_0 (0L<<6) 1259#define BCE_PCI_ID_VAL4_PM_SCALE_PRG_1 (1L<<6) 1260#define BCE_PCI_ID_VAL4_PM_SCALE_PRG_2 (2L<<6) 1261#define BCE_PCI_ID_VAL4_PM_SCALE_PRG_3 (3L<<6) 1262#define BCE_PCI_ID_VAL4_MSI_LIMIT (0x7L<<9) 1263#define BCE_PCI_ID_VAL4_MSI_ADVERTIZE (0x7L<<12) 1264#define BCE_PCI_ID_VAL4_MSI_ENABLE (1L<<15) 1265#define BCE_PCI_ID_VAL4_MAX_64_ADVERTIZE (1L<<16) 1266#define BCE_PCI_ID_VAL4_MAX_133_ADVERTIZE (1L<<17) 1267#define BCE_PCI_ID_VAL4_MAX_MEM_READ_SIZE (0x3L<<21) 1268#define BCE_PCI_ID_VAL4_MAX_SPLIT_SIZE (0x7L<<23) 1269#define BCE_PCI_ID_VAL4_MAX_CUMULATIVE_SIZE (0x7L<<26) 1270 1271#define BCE_PCI_ID_VAL5 0x00000444 1272#define BCE_PCI_ID_VAL5_D1_SUPPORT (1L<<0) 1273#define BCE_PCI_ID_VAL5_D2_SUPPORT (1L<<1) 1274#define BCE_PCI_ID_VAL5_PME_IN_D0 (1L<<2) 1275#define BCE_PCI_ID_VAL5_PME_IN_D1 (1L<<3) 1276#define BCE_PCI_ID_VAL5_PME_IN_D2 (1L<<4) 1277#define BCE_PCI_ID_VAL5_PME_IN_D3_HOT (1L<<5) 1278 1279#define BCE_PCI_PCIX_EXTENDED_STATUS 0x00000448 1280#define BCE_PCI_PCIX_EXTENDED_STATUS_NO_SNOOP (1L<<8) 1281#define BCE_PCI_PCIX_EXTENDED_STATUS_LONG_BURST (1L<<9) 1282#define BCE_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_CLASS (0xfL<<16) 1283#define BCE_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_IDX (0xffL<<24) 1284 1285#define BCE_PCI_ID_VAL6 0x0000044c 1286#define BCE_PCI_ID_VAL6_MAX_LAT (0xffL<<0) 1287#define BCE_PCI_ID_VAL6_MIN_GNT (0xffL<<8) 1288#define BCE_PCI_ID_VAL6_BIST (0xffL<<16) 1289 1290#define BCE_PCI_MSI_DATA 0x00000450 1291#define BCE_PCI_MSI_DATA_PCI_MSI_DATA (0xffffL<<0) 1292 1293#define BCE_PCI_MSI_ADDR_H 0x00000454 1294#define BCE_PCI_MSI_ADDR_L 0x00000458 1295 1296 1297/* 1298 * misc_reg definition 1299 * offset: 0x800 1300 */ 1301#define BCE_MISC_COMMAND 0x00000800 1302#define BCE_MISC_COMMAND_ENABLE_ALL (1L<<0) 1303#define BCE_MISC_COMMAND_DISABLE_ALL (1L<<1) 1304#define BCE_MISC_COMMAND_CORE_RESET (1L<<4) 1305#define BCE_MISC_COMMAND_HARD_RESET (1L<<5) 1306#define BCE_MISC_COMMAND_PAR_ERROR (1L<<8) 1307#define BCE_MISC_COMMAND_PAR_ERR_RAM (0x7fL<<16) 1308 1309#define BCE_MISC_CFG 0x00000804 1310#define BCE_MISC_CFG_PCI_GRC_TMOUT (1L<<0) 1311#define BCE_MISC_CFG_NVM_WR_EN (0x3L<<1) 1312#define BCE_MISC_CFG_NVM_WR_EN_PROTECT (0L<<1) 1313#define BCE_MISC_CFG_NVM_WR_EN_PCI (1L<<1) 1314#define BCE_MISC_CFG_NVM_WR_EN_ALLOW (2L<<1) 1315#define BCE_MISC_CFG_NVM_WR_EN_ALLOW2 (3L<<1) 1316#define BCE_MISC_CFG_BIST_EN (1L<<3) 1317#define BCE_MISC_CFG_CK25_OUT_ALT_SRC (1L<<4) 1318#define BCE_MISC_CFG_BYPASS_BSCAN (1L<<5) 1319#define BCE_MISC_CFG_BYPASS_EJTAG (1L<<6) 1320#define BCE_MISC_CFG_CLK_CTL_OVERRIDE (1L<<7) 1321#define BCE_MISC_CFG_LEDMODE (0x3L<<8) 1322#define BCE_MISC_CFG_LEDMODE_MAC (0L<<8) 1323#define BCE_MISC_CFG_LEDMODE_GPHY1 (1L<<8) 1324#define BCE_MISC_CFG_LEDMODE_GPHY2 (2L<<8) 1325 1326#define BCE_MISC_ID 0x00000808 1327#define BCE_MISC_ID_BOND_ID (0xfL<<0) 1328#define BCE_MISC_ID_CHIP_METAL (0xffL<<4) 1329#define BCE_MISC_ID_CHIP_REV (0xfL<<12) 1330#define BCE_MISC_ID_CHIP_NUM (0xffffL<<16) 1331 1332#define BCE_MISC_ENABLE_STATUS_BITS 0x0000080c 1333#define BCE_MISC_ENABLE_STATUS_BITS_TX_SCHEDULER_ENABLE (1L<<0) 1334#define BCE_MISC_ENABLE_STATUS_BITS_TX_BD_READ_ENABLE (1L<<1) 1335#define BCE_MISC_ENABLE_STATUS_BITS_TX_BD_CACHE_ENABLE (1L<<2) 1336#define BCE_MISC_ENABLE_STATUS_BITS_TX_PROCESSOR_ENABLE (1L<<3) 1337#define BCE_MISC_ENABLE_STATUS_BITS_TX_DMA_ENABLE (1L<<4) 1338#define BCE_MISC_ENABLE_STATUS_BITS_TX_PATCHUP_ENABLE (1L<<5) 1339#define BCE_MISC_ENABLE_STATUS_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6) 1340#define BCE_MISC_ENABLE_STATUS_BITS_TX_HEADER_Q_ENABLE (1L<<7) 1341#define BCE_MISC_ENABLE_STATUS_BITS_TX_ASSEMBLER_ENABLE (1L<<8) 1342#define BCE_MISC_ENABLE_STATUS_BITS_EMAC_ENABLE (1L<<9) 1343#define BCE_MISC_ENABLE_STATUS_BITS_RX_PARSER_MAC_ENABLE (1L<<10) 1344#define BCE_MISC_ENABLE_STATUS_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11) 1345#define BCE_MISC_ENABLE_STATUS_BITS_RX_MBUF_ENABLE (1L<<12) 1346#define BCE_MISC_ENABLE_STATUS_BITS_RX_LOOKUP_ENABLE (1L<<13) 1347#define BCE_MISC_ENABLE_STATUS_BITS_RX_PROCESSOR_ENABLE (1L<<14) 1348#define BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE (1L<<15) 1349#define BCE_MISC_ENABLE_STATUS_BITS_RX_BD_CACHE_ENABLE (1L<<16) 1350#define BCE_MISC_ENABLE_STATUS_BITS_RX_DMA_ENABLE (1L<<17) 1351#define BCE_MISC_ENABLE_STATUS_BITS_COMPLETION_ENABLE (1L<<18) 1352#define BCE_MISC_ENABLE_STATUS_BITS_HOST_COALESCE_ENABLE (1L<<19) 1353#define BCE_MISC_ENABLE_STATUS_BITS_MAILBOX_QUEUE_ENABLE (1L<<20) 1354#define BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE (1L<<21) 1355#define BCE_MISC_ENABLE_STATUS_BITS_CMD_SCHEDULER_ENABLE (1L<<22) 1356#define BCE_MISC_ENABLE_STATUS_BITS_CMD_PROCESSOR_ENABLE (1L<<23) 1357#define BCE_MISC_ENABLE_STATUS_BITS_MGMT_PROCESSOR_ENABLE (1L<<24) 1358#define BCE_MISC_ENABLE_STATUS_BITS_TIMER_ENABLE (1L<<25) 1359#define BCE_MISC_ENABLE_STATUS_BITS_DMA_ENGINE_ENABLE (1L<<26) 1360#define BCE_MISC_ENABLE_STATUS_BITS_UMP_ENABLE (1L<<27) 1361 1362#define BCE_MISC_ENABLE_SET_BITS 0x00000810 1363#define BCE_MISC_ENABLE_SET_BITS_TX_SCHEDULER_ENABLE (1L<<0) 1364#define BCE_MISC_ENABLE_SET_BITS_TX_BD_READ_ENABLE (1L<<1) 1365#define BCE_MISC_ENABLE_SET_BITS_TX_BD_CACHE_ENABLE (1L<<2) 1366#define BCE_MISC_ENABLE_SET_BITS_TX_PROCESSOR_ENABLE (1L<<3) 1367#define BCE_MISC_ENABLE_SET_BITS_TX_DMA_ENABLE (1L<<4) 1368#define BCE_MISC_ENABLE_SET_BITS_TX_PATCHUP_ENABLE (1L<<5) 1369#define BCE_MISC_ENABLE_SET_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6) 1370#define BCE_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE (1L<<7) 1371#define BCE_MISC_ENABLE_SET_BITS_TX_ASSEMBLER_ENABLE (1L<<8) 1372#define BCE_MISC_ENABLE_SET_BITS_EMAC_ENABLE (1L<<9) 1373#define BCE_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE (1L<<10) 1374#define BCE_MISC_ENABLE_SET_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11) 1375#define BCE_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE (1L<<12) 1376#define BCE_MISC_ENABLE_SET_BITS_RX_LOOKUP_ENABLE (1L<<13) 1377#define BCE_MISC_ENABLE_SET_BITS_RX_PROCESSOR_ENABLE (1L<<14) 1378#define BCE_MISC_ENABLE_SET_BITS_RX_V2P_ENABLE (1L<<15) 1379#define BCE_MISC_ENABLE_SET_BITS_RX_BD_CACHE_ENABLE (1L<<16) 1380#define BCE_MISC_ENABLE_SET_BITS_RX_DMA_ENABLE (1L<<17) 1381#define BCE_MISC_ENABLE_SET_BITS_COMPLETION_ENABLE (1L<<18) 1382#define BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE (1L<<19) 1383#define BCE_MISC_ENABLE_SET_BITS_MAILBOX_QUEUE_ENABLE (1L<<20) 1384#define BCE_MISC_ENABLE_SET_BITS_CONTEXT_ENABLE (1L<<21) 1385#define BCE_MISC_ENABLE_SET_BITS_CMD_SCHEDULER_ENABLE (1L<<22) 1386#define BCE_MISC_ENABLE_SET_BITS_CMD_PROCESSOR_ENABLE (1L<<23) 1387#define BCE_MISC_ENABLE_SET_BITS_MGMT_PROCESSOR_ENABLE (1L<<24) 1388#define BCE_MISC_ENABLE_SET_BITS_TIMER_ENABLE (1L<<25) 1389#define BCE_MISC_ENABLE_SET_BITS_DMA_ENGINE_ENABLE (1L<<26) 1390#define BCE_MISC_ENABLE_SET_BITS_UMP_ENABLE (1L<<27) 1391 1392#define BCE_MISC_ENABLE_CLR_BITS 0x00000814 1393#define BCE_MISC_ENABLE_CLR_BITS_TX_SCHEDULER_ENABLE (1L<<0) 1394#define BCE_MISC_ENABLE_CLR_BITS_TX_BD_READ_ENABLE (1L<<1) 1395#define BCE_MISC_ENABLE_CLR_BITS_TX_BD_CACHE_ENABLE (1L<<2) 1396#define BCE_MISC_ENABLE_CLR_BITS_TX_PROCESSOR_ENABLE (1L<<3) 1397#define BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE (1L<<4) 1398#define BCE_MISC_ENABLE_CLR_BITS_TX_PATCHUP_ENABLE (1L<<5) 1399#define BCE_MISC_ENABLE_CLR_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6) 1400#define BCE_MISC_ENABLE_CLR_BITS_TX_HEADER_Q_ENABLE (1L<<7) 1401#define BCE_MISC_ENABLE_CLR_BITS_TX_ASSEMBLER_ENABLE (1L<<8) 1402#define BCE_MISC_ENABLE_CLR_BITS_EMAC_ENABLE (1L<<9) 1403#define BCE_MISC_ENABLE_CLR_BITS_RX_PARSER_MAC_ENABLE (1L<<10) 1404#define BCE_MISC_ENABLE_CLR_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11) 1405#define BCE_MISC_ENABLE_CLR_BITS_RX_MBUF_ENABLE (1L<<12) 1406#define BCE_MISC_ENABLE_CLR_BITS_RX_LOOKUP_ENABLE (1L<<13) 1407#define BCE_MISC_ENABLE_CLR_BITS_RX_PROCESSOR_ENABLE (1L<<14) 1408#define BCE_MISC_ENABLE_CLR_BITS_RX_V2P_ENABLE (1L<<15) 1409#define BCE_MISC_ENABLE_CLR_BITS_RX_BD_CACHE_ENABLE (1L<<16) 1410#define BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE (1L<<17) 1411#define BCE_MISC_ENABLE_CLR_BITS_COMPLETION_ENABLE (1L<<18) 1412#define BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE (1L<<19) 1413#define BCE_MISC_ENABLE_CLR_BITS_MAILBOX_QUEUE_ENABLE (1L<<20) 1414#define BCE_MISC_ENABLE_CLR_BITS_CONTEXT_ENABLE (1L<<21) 1415#define BCE_MISC_ENABLE_CLR_BITS_CMD_SCHEDULER_ENABLE (1L<<22) 1416#define BCE_MISC_ENABLE_CLR_BITS_CMD_PROCESSOR_ENABLE (1L<<23) 1417#define BCE_MISC_ENABLE_CLR_BITS_MGMT_PROCESSOR_ENABLE (1L<<24) 1418#define BCE_MISC_ENABLE_CLR_BITS_TIMER_ENABLE (1L<<25) 1419#define BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE (1L<<26) 1420#define BCE_MISC_ENABLE_CLR_BITS_UMP_ENABLE (1L<<27) 1421 1422#define BCE_MISC_CLOCK_CONTROL_BITS 0x00000818 1423#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET (0xfL<<0) 1424#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ (0L<<0) 1425#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ (1L<<0) 1426#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ (2L<<0) 1427#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ (3L<<0) 1428#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ (4L<<0) 1429#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ (5L<<0) 1430#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ (6L<<0) 1431#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ (7L<<0) 1432#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW (0xfL<<0) 1433#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE (1L<<6) 1434#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT (1L<<7) 1435#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC (0x7L<<8) 1436#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF (0L<<8) 1437#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12 (1L<<8) 1438#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6 (2L<<8) 1439#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62 (4L<<8) 1440#define BCE_MISC_CLOCK_CONTROL_BITS_PLAY_DEAD (1L<<11) 1441#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED (0xfL<<12) 1442#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100 (0L<<12) 1443#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80 (1L<<12) 1444#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50 (2L<<12) 1445#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40 (4L<<12) 1446#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25 (8L<<12) 1447#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP (1L<<16) 1448#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_PLL_STOP (1L<<17) 1449#define BCE_MISC_CLOCK_CONTROL_BITS_RESERVED_18 (1L<<18) 1450#define BCE_MISC_CLOCK_CONTROL_BITS_USE_SPD_DET (1L<<19) 1451#define BCE_MISC_CLOCK_CONTROL_BITS_RESERVED (0xfffL<<20) 1452 1453#define BCE_MISC_GPIO 0x0000081c 1454#define BCE_MISC_GPIO_VALUE (0xffL<<0) 1455#define BCE_MISC_GPIO_SET (0xffL<<8) 1456#define BCE_MISC_GPIO_CLR (0xffL<<16) 1457#define BCE_MISC_GPIO_FLOAT (0xffL<<24) 1458 1459#define BCE_MISC_GPIO_INT 0x00000820 1460#define BCE_MISC_GPIO_INT_INT_STATE (0xfL<<0) 1461#define BCE_MISC_GPIO_INT_OLD_VALUE (0xfL<<8) 1462#define BCE_MISC_GPIO_INT_OLD_SET (0xfL<<16) 1463#define BCE_MISC_GPIO_INT_OLD_CLR (0xfL<<24) 1464 1465#define BCE_MISC_CONFIG_LFSR 0x00000824 1466#define BCE_MISC_CONFIG_LFSR_DIV (0xffffL<<0) 1467 1468#define BCE_MISC_LFSR_MASK_BITS 0x00000828 1469#define BCE_MISC_LFSR_MASK_BITS_TX_SCHEDULER_ENABLE (1L<<0) 1470#define BCE_MISC_LFSR_MASK_BITS_TX_BD_READ_ENABLE (1L<<1) 1471#define BCE_MISC_LFSR_MASK_BITS_TX_BD_CACHE_ENABLE (1L<<2) 1472#define BCE_MISC_LFSR_MASK_BITS_TX_PROCESSOR_ENABLE (1L<<3) 1473#define BCE_MISC_LFSR_MASK_BITS_TX_DMA_ENABLE (1L<<4) 1474#define BCE_MISC_LFSR_MASK_BITS_TX_PATCHUP_ENABLE (1L<<5) 1475#define BCE_MISC_LFSR_MASK_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6) 1476#define BCE_MISC_LFSR_MASK_BITS_TX_HEADER_Q_ENABLE (1L<<7) 1477#define BCE_MISC_LFSR_MASK_BITS_TX_ASSEMBLER_ENABLE (1L<<8) 1478#define BCE_MISC_LFSR_MASK_BITS_EMAC_ENABLE (1L<<9) 1479#define BCE_MISC_LFSR_MASK_BITS_RX_PARSER_MAC_ENABLE (1L<<10) 1480#define BCE_MISC_LFSR_MASK_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11) 1481#define BCE_MISC_LFSR_MASK_BITS_RX_MBUF_ENABLE (1L<<12) 1482#define BCE_MISC_LFSR_MASK_BITS_RX_LOOKUP_ENABLE (1L<<13) 1483#define BCE_MISC_LFSR_MASK_BITS_RX_PROCESSOR_ENABLE (1L<<14) 1484#define BCE_MISC_LFSR_MASK_BITS_RX_V2P_ENABLE (1L<<15) 1485#define BCE_MISC_LFSR_MASK_BITS_RX_BD_CACHE_ENABLE (1L<<16) 1486#define BCE_MISC_LFSR_MASK_BITS_RX_DMA_ENABLE (1L<<17) 1487#define BCE_MISC_LFSR_MASK_BITS_COMPLETION_ENABLE (1L<<18) 1488#define BCE_MISC_LFSR_MASK_BITS_HOST_COALESCE_ENABLE (1L<<19) 1489#define BCE_MISC_LFSR_MASK_BITS_MAILBOX_QUEUE_ENABLE (1L<<20) 1490#define BCE_MISC_LFSR_MASK_BITS_CONTEXT_ENABLE (1L<<21) 1491#define BCE_MISC_LFSR_MASK_BITS_CMD_SCHEDULER_ENABLE (1L<<22) 1492#define BCE_MISC_LFSR_MASK_BITS_CMD_PROCESSOR_ENABLE (1L<<23) 1493#define BCE_MISC_LFSR_MASK_BITS_MGMT_PROCESSOR_ENABLE (1L<<24) 1494#define BCE_MISC_LFSR_MASK_BITS_TIMER_ENABLE (1L<<25) 1495#define BCE_MISC_LFSR_MASK_BITS_DMA_ENGINE_ENABLE (1L<<26) 1496#define BCE_MISC_LFSR_MASK_BITS_UMP_ENABLE (1L<<27) 1497 1498#define BCE_MISC_ARB_REQ0 0x0000082c 1499#define BCE_MISC_ARB_REQ1 0x00000830 1500#define BCE_MISC_ARB_REQ2 0x00000834 1501#define BCE_MISC_ARB_REQ3 0x00000838 1502#define BCE_MISC_ARB_REQ4 0x0000083c 1503#define BCE_MISC_ARB_FREE0 0x00000840 1504#define BCE_MISC_ARB_FREE1 0x00000844 1505#define BCE_MISC_ARB_FREE2 0x00000848 1506#define BCE_MISC_ARB_FREE3 0x0000084c 1507#define BCE_MISC_ARB_FREE4 0x00000850 1508#define BCE_MISC_ARB_REQ_STATUS0 0x00000854 1509#define BCE_MISC_ARB_REQ_STATUS1 0x00000858 1510#define BCE_MISC_ARB_REQ_STATUS2 0x0000085c 1511#define BCE_MISC_ARB_REQ_STATUS3 0x00000860 1512#define BCE_MISC_ARB_REQ_STATUS4 0x00000864 1513#define BCE_MISC_ARB_GNT0 0x00000868 1514#define BCE_MISC_ARB_GNT0_0 (0x7L<<0) 1515#define BCE_MISC_ARB_GNT0_1 (0x7L<<4) 1516#define BCE_MISC_ARB_GNT0_2 (0x7L<<8) 1517#define BCE_MISC_ARB_GNT0_3 (0x7L<<12) 1518#define BCE_MISC_ARB_GNT0_4 (0x7L<<16) 1519#define BCE_MISC_ARB_GNT0_5 (0x7L<<20) 1520#define BCE_MISC_ARB_GNT0_6 (0x7L<<24) 1521#define BCE_MISC_ARB_GNT0_7 (0x7L<<28) 1522 1523#define BCE_MISC_ARB_GNT1 0x0000086c 1524#define BCE_MISC_ARB_GNT1_8 (0x7L<<0) 1525#define BCE_MISC_ARB_GNT1_9 (0x7L<<4) 1526#define BCE_MISC_ARB_GNT1_10 (0x7L<<8) 1527#define BCE_MISC_ARB_GNT1_11 (0x7L<<12) 1528#define BCE_MISC_ARB_GNT1_12 (0x7L<<16) 1529#define BCE_MISC_ARB_GNT1_13 (0x7L<<20) 1530#define BCE_MISC_ARB_GNT1_14 (0x7L<<24) 1531#define BCE_MISC_ARB_GNT1_15 (0x7L<<28) 1532 1533#define BCE_MISC_ARB_GNT2 0x00000870 1534#define BCE_MISC_ARB_GNT2_16 (0x7L<<0) 1535#define BCE_MISC_ARB_GNT2_17 (0x7L<<4) 1536#define BCE_MISC_ARB_GNT2_18 (0x7L<<8) 1537#define BCE_MISC_ARB_GNT2_19 (0x7L<<12) 1538#define BCE_MISC_ARB_GNT2_20 (0x7L<<16) 1539#define BCE_MISC_ARB_GNT2_21 (0x7L<<20) 1540#define BCE_MISC_ARB_GNT2_22 (0x7L<<24) 1541#define BCE_MISC_ARB_GNT2_23 (0x7L<<28) 1542 1543#define BCE_MISC_ARB_GNT3 0x00000874 1544#define BCE_MISC_ARB_GNT3_24 (0x7L<<0) 1545#define BCE_MISC_ARB_GNT3_25 (0x7L<<4) 1546#define BCE_MISC_ARB_GNT3_26 (0x7L<<8) 1547#define BCE_MISC_ARB_GNT3_27 (0x7L<<12) 1548#define BCE_MISC_ARB_GNT3_28 (0x7L<<16) 1549#define BCE_MISC_ARB_GNT3_29 (0x7L<<20) 1550#define BCE_MISC_ARB_GNT3_30 (0x7L<<24) 1551#define BCE_MISC_ARB_GNT3_31 (0x7L<<28) 1552 1553#define BCE_MISC_PRBS_CONTROL 0x00000878 1554#define BCE_MISC_PRBS_CONTROL_EN (1L<<0) 1555#define BCE_MISC_PRBS_CONTROL_RSTB (1L<<1) 1556#define BCE_MISC_PRBS_CONTROL_INV (1L<<2) 1557#define BCE_MISC_PRBS_CONTROL_ERR_CLR (1L<<3) 1558#define BCE_MISC_PRBS_CONTROL_ORDER (0x3L<<4) 1559#define BCE_MISC_PRBS_CONTROL_ORDER_7TH (0L<<4) 1560#define BCE_MISC_PRBS_CONTROL_ORDER_15TH (1L<<4) 1561#define BCE_MISC_PRBS_CONTROL_ORDER_23RD (2L<<4) 1562#define BCE_MISC_PRBS_CONTROL_ORDER_31ST (3L<<4) 1563 1564#define BCE_MISC_PRBS_STATUS 0x0000087c 1565#define BCE_MISC_PRBS_STATUS_LOCK (1L<<0) 1566#define BCE_MISC_PRBS_STATUS_STKY (1L<<1) 1567#define BCE_MISC_PRBS_STATUS_ERRORS (0x3fffL<<2) 1568#define BCE_MISC_PRBS_STATUS_STATE (0xfL<<16) 1569 1570#define BCE_MISC_SM_ASF_CONTROL 0x00000880 1571#define BCE_MISC_SM_ASF_CONTROL_ASF_RST (1L<<0) 1572#define BCE_MISC_SM_ASF_CONTROL_TSC_EN (1L<<1) 1573#define BCE_MISC_SM_ASF_CONTROL_WG_TO (1L<<2) 1574#define BCE_MISC_SM_ASF_CONTROL_HB_TO (1L<<3) 1575#define BCE_MISC_SM_ASF_CONTROL_PA_TO (1L<<4) 1576#define BCE_MISC_SM_ASF_CONTROL_PL_TO (1L<<5) 1577#define BCE_MISC_SM_ASF_CONTROL_RT_TO (1L<<6) 1578#define BCE_MISC_SM_ASF_CONTROL_SMB_EVENT (1L<<7) 1579#define BCE_MISC_SM_ASF_CONTROL_RES (0xfL<<8) 1580#define BCE_MISC_SM_ASF_CONTROL_SMB_EN (1L<<12) 1581#define BCE_MISC_SM_ASF_CONTROL_SMB_BB_EN (1L<<13) 1582#define BCE_MISC_SM_ASF_CONTROL_SMB_NO_ADDR_FILT (1L<<14) 1583#define BCE_MISC_SM_ASF_CONTROL_SMB_AUTOREAD (1L<<15) 1584#define BCE_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR1 (0x3fL<<16) 1585#define BCE_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR2 (0x3fL<<24) 1586#define BCE_MISC_SM_ASF_CONTROL_EN_NIC_SMB_ADDR_0 (1L<<30) 1587#define BCE_MISC_SM_ASF_CONTROL_SMB_EARLY_ATTN (1L<<31) 1588 1589#define BCE_MISC_SMB_IN 0x00000884 1590#define BCE_MISC_SMB_IN_DAT_IN (0xffL<<0) 1591#define BCE_MISC_SMB_IN_RDY (1L<<8) 1592#define BCE_MISC_SMB_IN_DONE (1L<<9) 1593#define BCE_MISC_SMB_IN_FIRSTBYTE (1L<<10) 1594#define BCE_MISC_SMB_IN_STATUS (0x7L<<11) 1595#define BCE_MISC_SMB_IN_STATUS_OK (0x0L<<11) 1596#define BCE_MISC_SMB_IN_STATUS_PEC (0x1L<<11) 1597#define BCE_MISC_SMB_IN_STATUS_OFLOW (0x2L<<11) 1598#define BCE_MISC_SMB_IN_STATUS_STOP (0x3L<<11) 1599#define BCE_MISC_SMB_IN_STATUS_TIMEOUT (0x4L<<11) 1600 1601#define BCE_MISC_SMB_OUT 0x00000888 1602#define BCE_MISC_SMB_OUT_DAT_OUT (0xffL<<0) 1603#define BCE_MISC_SMB_OUT_RDY (1L<<8) 1604#define BCE_MISC_SMB_OUT_START (1L<<9) 1605#define BCE_MISC_SMB_OUT_LAST (1L<<10) 1606#define BCE_MISC_SMB_OUT_ACC_TYPE (1L<<11) 1607#define BCE_MISC_SMB_OUT_ENB_PEC (1L<<12) 1608#define BCE_MISC_SMB_OUT_GET_RX_LEN (1L<<13) 1609#define BCE_MISC_SMB_OUT_SMB_READ_LEN (0x3fL<<14) 1610#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS (0xfL<<20) 1611#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_OK (0L<<20) 1612#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_NACK (1L<<20) 1613#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_NACK (9L<<20) 1614#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_UFLOW (2L<<20) 1615#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_STOP (3L<<20) 1616#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_TIMEOUT (4L<<20) 1617#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_LOST (5L<<20) 1618#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_LOST (0xdL<<20) 1619#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_BADACK (0x6L<<20) 1620#define BCE_MISC_SMB_OUT_SMB_OUT_SLAVEMODE (1L<<24) 1621#define BCE_MISC_SMB_OUT_SMB_OUT_DAT_EN (1L<<25) 1622#define BCE_MISC_SMB_OUT_SMB_OUT_DAT_IN (1L<<26) 1623#define BCE_MISC_SMB_OUT_SMB_OUT_CLK_EN (1L<<27) 1624#define BCE_MISC_SMB_OUT_SMB_OUT_CLK_IN (1L<<28) 1625 1626#define BCE_MISC_SMB_WATCHDOG 0x0000088c 1627#define BCE_MISC_SMB_WATCHDOG_WATCHDOG (0xffffL<<0) 1628 1629#define BCE_MISC_SMB_HEARTBEAT 0x00000890 1630#define BCE_MISC_SMB_HEARTBEAT_HEARTBEAT (0xffffL<<0) 1631 1632#define BCE_MISC_SMB_POLL_ASF 0x00000894 1633#define BCE_MISC_SMB_POLL_ASF_POLL_ASF (0xffffL<<0) 1634 1635#define BCE_MISC_SMB_POLL_LEGACY 0x00000898 1636#define BCE_MISC_SMB_POLL_LEGACY_POLL_LEGACY (0xffffL<<0) 1637 1638#define BCE_MISC_SMB_RETRAN 0x0000089c 1639#define BCE_MISC_SMB_RETRAN_RETRAN (0xffL<<0) 1640 1641#define BCE_MISC_SMB_TIMESTAMP 0x000008a0 1642#define BCE_MISC_SMB_TIMESTAMP_TIMESTAMP (0xffffffffL<<0) 1643 1644#define BCE_MISC_PERR_ENA0 0x000008a4 1645#define BCE_MISC_PERR_ENA0_COM_MISC_CTXC (1L<<0) 1646#define BCE_MISC_PERR_ENA0_COM_MISC_REGF (1L<<1) 1647#define BCE_MISC_PERR_ENA0_COM_MISC_SCPAD (1L<<2) 1648#define BCE_MISC_PERR_ENA0_CP_MISC_CTXC (1L<<3) 1649#define BCE_MISC_PERR_ENA0_CP_MISC_REGF (1L<<4) 1650#define BCE_MISC_PERR_ENA0_CP_MISC_SCPAD (1L<<5) 1651#define BCE_MISC_PERR_ENA0_CS_MISC_TMEM (1L<<6) 1652#define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM0 (1L<<7) 1653#define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM1 (1L<<8) 1654#define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM2 (1L<<9) 1655#define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM3 (1L<<10) 1656#define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM4 (1L<<11) 1657#define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM5 (1L<<12) 1658#define BCE_MISC_PERR_ENA0_CTX_MISC_PGTBL (1L<<13) 1659#define BCE_MISC_PERR_ENA0_DMAE_MISC_DR0 (1L<<14) 1660#define BCE_MISC_PERR_ENA0_DMAE_MISC_DR1 (1L<<15) 1661#define BCE_MISC_PERR_ENA0_DMAE_MISC_DR2 (1L<<16) 1662#define BCE_MISC_PERR_ENA0_DMAE_MISC_DR3 (1L<<17) 1663#define BCE_MISC_PERR_ENA0_DMAE_MISC_DR4 (1L<<18) 1664#define BCE_MISC_PERR_ENA0_DMAE_MISC_DW0 (1L<<19) 1665#define BCE_MISC_PERR_ENA0_DMAE_MISC_DW1 (1L<<20) 1666#define BCE_MISC_PERR_ENA0_DMAE_MISC_DW2 (1L<<21) 1667#define BCE_MISC_PERR_ENA0_HC_MISC_DMA (1L<<22) 1668#define BCE_MISC_PERR_ENA0_MCP_MISC_REGF (1L<<23) 1669#define BCE_MISC_PERR_ENA0_MCP_MISC_SCPAD (1L<<24) 1670#define BCE_MISC_PERR_ENA0_MQ_MISC_CTX (1L<<25) 1671#define BCE_MISC_PERR_ENA0_RBDC_MISC (1L<<26) 1672#define BCE_MISC_PERR_ENA0_RBUF_MISC_MB (1L<<27) 1673#define BCE_MISC_PERR_ENA0_RBUF_MISC_PTR (1L<<28) 1674#define BCE_MISC_PERR_ENA0_RDE_MISC_RPC (1L<<29) 1675#define BCE_MISC_PERR_ENA0_RDE_MISC_RPM (1L<<30) 1676#define BCE_MISC_PERR_ENA0_RV2P_MISC_CB0REGS (1L<<31) 1677 1678#define BCE_MISC_PERR_ENA1 0x000008a8 1679#define BCE_MISC_PERR_ENA1_RV2P_MISC_CB1REGS (1L<<0) 1680#define BCE_MISC_PERR_ENA1_RV2P_MISC_P1IRAM (1L<<1) 1681#define BCE_MISC_PERR_ENA1_RV2P_MISC_P2IRAM (1L<<2) 1682#define BCE_MISC_PERR_ENA1_RXP_MISC_CTXC (1L<<3) 1683#define BCE_MISC_PERR_ENA1_RXP_MISC_REGF (1L<<4) 1684#define BCE_MISC_PERR_ENA1_RXP_MISC_SCPAD (1L<<5) 1685#define BCE_MISC_PERR_ENA1_RXP_MISC_RBUFC (1L<<6) 1686#define BCE_MISC_PERR_ENA1_TBDC_MISC (1L<<7) 1687#define BCE_MISC_PERR_ENA1_TDMA_MISC (1L<<8) 1688#define BCE_MISC_PERR_ENA1_THBUF_MISC_MB0 (1L<<9) 1689#define BCE_MISC_PERR_ENA1_THBUF_MISC_MB1 (1L<<10) 1690#define BCE_MISC_PERR_ENA1_TPAT_MISC_REGF (1L<<11) 1691#define BCE_MISC_PERR_ENA1_TPAT_MISC_SCPAD (1L<<12) 1692#define BCE_MISC_PERR_ENA1_TPBUF_MISC_MB (1L<<13) 1693#define BCE_MISC_PERR_ENA1_TSCH_MISC_LR (1L<<14) 1694#define BCE_MISC_PERR_ENA1_TXP_MISC_CTXC (1L<<15) 1695#define BCE_MISC_PERR_ENA1_TXP_MISC_REGF (1L<<16) 1696#define BCE_MISC_PERR_ENA1_TXP_MISC_SCPAD (1L<<17) 1697#define BCE_MISC_PERR_ENA1_UMP_MISC_FIORX (1L<<18) 1698#define BCE_MISC_PERR_ENA1_UMP_MISC_FIOTX (1L<<19) 1699#define BCE_MISC_PERR_ENA1_UMP_MISC_RX (1L<<20) 1700#define BCE_MISC_PERR_ENA1_UMP_MISC_TX (1L<<21) 1701#define BCE_MISC_PERR_ENA1_RDMAQ_MISC (1L<<22) 1702#define BCE_MISC_PERR_ENA1_CSQ_MISC (1L<<23) 1703#define BCE_MISC_PERR_ENA1_CPQ_MISC (1L<<24) 1704#define BCE_MISC_PERR_ENA1_MCPQ_MISC (1L<<25) 1705#define BCE_MISC_PERR_ENA1_RV2PMQ_MISC (1L<<26) 1706#define BCE_MISC_PERR_ENA1_RV2PPQ_MISC (1L<<27) 1707#define BCE_MISC_PERR_ENA1_RV2PTQ_MISC (1L<<28) 1708#define BCE_MISC_PERR_ENA1_RXPQ_MISC (1L<<29) 1709#define BCE_MISC_PERR_ENA1_RXPCQ_MISC (1L<<30) 1710#define BCE_MISC_PERR_ENA1_RLUPQ_MISC (1L<<31) 1711 1712#define BCE_MISC_PERR_ENA2 0x000008ac 1713#define BCE_MISC_PERR_ENA2_COMQ_MISC (1L<<0) 1714#define BCE_MISC_PERR_ENA2_COMXQ_MISC (1L<<1) 1715#define BCE_MISC_PERR_ENA2_COMTQ_MISC (1L<<2) 1716#define BCE_MISC_PERR_ENA2_TSCHQ_MISC (1L<<3) 1717#define BCE_MISC_PERR_ENA2_TBDRQ_MISC (1L<<4) 1718#define BCE_MISC_PERR_ENA2_TXPQ_MISC (1L<<5) 1719#define BCE_MISC_PERR_ENA2_TDMAQ_MISC (1L<<6) 1720#define BCE_MISC_PERR_ENA2_TPATQ_MISC (1L<<7) 1721#define BCE_MISC_PERR_ENA2_TASQ_MISC (1L<<8) 1722 1723#define BCE_MISC_DEBUG_VECTOR_SEL 0x000008b0 1724#define BCE_MISC_DEBUG_VECTOR_SEL_0 (0xfffL<<0) 1725#define BCE_MISC_DEBUG_VECTOR_SEL_1 (0xfffL<<12) 1726 1727#define BCE_MISC_VREG_CONTROL 0x000008b4 1728#define BCE_MISC_VREG_CONTROL_1_2 (0xfL<<0) 1729#define BCE_MISC_VREG_CONTROL_2_5 (0xfL<<4) 1730 1731#define BCE_MISC_FINAL_CLK_CTL_VAL 0x000008b8 1732#define BCE_MISC_FINAL_CLK_CTL_VAL_MISC_FINAL_CLK_CTL_VAL (0x3ffffffL<<6) 1733 1734#define BCE_MISC_UNUSED0 0x000008bc 1735 1736 1737/* 1738 * nvm_reg definition 1739 * offset: 0x6400 1740 */ 1741#define BCE_NVM_COMMAND 0x00006400 1742#define BCE_NVM_COMMAND_RST (1L<<0) 1743#define BCE_NVM_COMMAND_DONE (1L<<3) 1744#define BCE_NVM_COMMAND_DOIT (1L<<4) 1745#define BCE_NVM_COMMAND_WR (1L<<5) 1746#define BCE_NVM_COMMAND_ERASE (1L<<6) 1747#define BCE_NVM_COMMAND_FIRST (1L<<7) 1748#define BCE_NVM_COMMAND_LAST (1L<<8) 1749#define BCE_NVM_COMMAND_WREN (1L<<16) 1750#define BCE_NVM_COMMAND_WRDI (1L<<17) 1751#define BCE_NVM_COMMAND_EWSR (1L<<18) 1752#define BCE_NVM_COMMAND_WRSR (1L<<19) 1753 1754#define BCE_NVM_STATUS 0x00006404 1755#define BCE_NVM_STATUS_PI_FSM_STATE (0xfL<<0) 1756#define BCE_NVM_STATUS_EE_FSM_STATE (0xfL<<4) 1757#define BCE_NVM_STATUS_EQ_FSM_STATE (0xfL<<8) 1758 1759#define BCE_NVM_WRITE 0x00006408 1760#define BCE_NVM_WRITE_NVM_WRITE_VALUE (0xffffffffL<<0) 1761#define BCE_NVM_WRITE_NVM_WRITE_VALUE_BIT_BANG (0L<<0) 1762#define BCE_NVM_WRITE_NVM_WRITE_VALUE_EECLK (1L<<0) 1763#define BCE_NVM_WRITE_NVM_WRITE_VALUE_EEDATA (2L<<0) 1764#define BCE_NVM_WRITE_NVM_WRITE_VALUE_SCLK (4L<<0) 1765#define BCE_NVM_WRITE_NVM_WRITE_VALUE_CS_B (8L<<0) 1766#define BCE_NVM_WRITE_NVM_WRITE_VALUE_SO (16L<<0) 1767#define BCE_NVM_WRITE_NVM_WRITE_VALUE_SI (32L<<0) 1768 1769#define BCE_NVM_ADDR 0x0000640c 1770#define BCE_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL<<0) 1771#define BCE_NVM_ADDR_NVM_ADDR_VALUE_BIT_BANG (0L<<0) 1772#define BCE_NVM_ADDR_NVM_ADDR_VALUE_EECLK (1L<<0) 1773#define BCE_NVM_ADDR_NVM_ADDR_VALUE_EEDATA (2L<<0) 1774#define BCE_NVM_ADDR_NVM_ADDR_VALUE_SCLK (4L<<0) 1775#define BCE_NVM_ADDR_NVM_ADDR_VALUE_CS_B (8L<<0) 1776#define BCE_NVM_ADDR_NVM_ADDR_VALUE_SO (16L<<0) 1777#define BCE_NVM_ADDR_NVM_ADDR_VALUE_SI (32L<<0) 1778 1779#define BCE_NVM_READ 0x00006410 1780#define BCE_NVM_READ_NVM_READ_VALUE (0xffffffffL<<0) 1781#define BCE_NVM_READ_NVM_READ_VALUE_BIT_BANG (0L<<0) 1782#define BCE_NVM_READ_NVM_READ_VALUE_EECLK (1L<<0) 1783#define BCE_NVM_READ_NVM_READ_VALUE_EEDATA (2L<<0) 1784#define BCE_NVM_READ_NVM_READ_VALUE_SCLK (4L<<0) 1785#define BCE_NVM_READ_NVM_READ_VALUE_CS_B (8L<<0) 1786#define BCE_NVM_READ_NVM_READ_VALUE_SO (16L<<0) 1787#define BCE_NVM_READ_NVM_READ_VALUE_SI (32L<<0) 1788 1789#define BCE_NVM_CFG1 0x00006414 1790#define BCE_NVM_CFG1_FLASH_MODE (1L<<0) 1791#define BCE_NVM_CFG1_BUFFER_MODE (1L<<1) 1792#define BCE_NVM_CFG1_PASS_MODE (1L<<2) 1793#define BCE_NVM_CFG1_BITBANG_MODE (1L<<3) 1794#define BCE_NVM_CFG1_STATUS_BIT (0x7L<<4) 1795#define BCE_NVM_CFG1_STATUS_BIT_FLASH_RDY (0L<<4) 1796#define BCE_NVM_CFG1_STATUS_BIT_BUFFER_RDY (7L<<4) 1797#define BCE_NVM_CFG1_SPI_CLK_DIV (0xfL<<7) 1798#define BCE_NVM_CFG1_SEE_CLK_DIV (0x7ffL<<11) 1799#define BCE_NVM_CFG1_PROTECT_MODE (1L<<24) 1800#define BCE_NVM_CFG1_FLASH_SIZE (1L<<25) 1801#define BCE_NVM_CFG1_COMPAT_BYPASSS (1L<<31) 1802 1803#define BCE_NVM_CFG2 0x00006418 1804#define BCE_NVM_CFG2_ERASE_CMD (0xffL<<0) 1805#define BCE_NVM_CFG2_DUMMY (0xffL<<8) 1806#define BCE_NVM_CFG2_STATUS_CMD (0xffL<<16) 1807 1808#define BCE_NVM_CFG3 0x0000641c 1809#define BCE_NVM_CFG3_BUFFER_RD_CMD (0xffL<<0) 1810#define BCE_NVM_CFG3_WRITE_CMD (0xffL<<8) 1811#define BCE_NVM_CFG3_BUFFER_WRITE_CMD (0xffL<<16) 1812#define BCE_NVM_CFG3_READ_CMD (0xffL<<24) 1813 1814#define BCE_NVM_SW_ARB 0x00006420 1815#define BCE_NVM_SW_ARB_ARB_REQ_SET0 (1L<<0) 1816#define BCE_NVM_SW_ARB_ARB_REQ_SET1 (1L<<1) 1817#define BCE_NVM_SW_ARB_ARB_REQ_SET2 (1L<<2) 1818#define BCE_NVM_SW_ARB_ARB_REQ_SET3 (1L<<3) 1819#define BCE_NVM_SW_ARB_ARB_REQ_CLR0 (1L<<4) 1820#define BCE_NVM_SW_ARB_ARB_REQ_CLR1 (1L<<5) 1821#define BCE_NVM_SW_ARB_ARB_REQ_CLR2 (1L<<6) 1822#define BCE_NVM_SW_ARB_ARB_REQ_CLR3 (1L<<7) 1823#define BCE_NVM_SW_ARB_ARB_ARB0 (1L<<8) 1824#define BCE_NVM_SW_ARB_ARB_ARB1 (1L<<9) 1825#define BCE_NVM_SW_ARB_ARB_ARB2 (1L<<10) 1826#define BCE_NVM_SW_ARB_ARB_ARB3 (1L<<11) 1827#define BCE_NVM_SW_ARB_REQ0 (1L<<12) 1828#define BCE_NVM_SW_ARB_REQ1 (1L<<13) 1829#define BCE_NVM_SW_ARB_REQ2 (1L<<14) 1830#define BCE_NVM_SW_ARB_REQ3 (1L<<15) 1831 1832#define BCE_NVM_ACCESS_ENABLE 0x00006424 1833#define BCE_NVM_ACCESS_ENABLE_EN (1L<<0) 1834#define BCE_NVM_ACCESS_ENABLE_WR_EN (1L<<1) 1835 1836#define BCE_NVM_WRITE1 0x00006428 1837#define BCE_NVM_WRITE1_WREN_CMD (0xffL<<0) 1838#define BCE_NVM_WRITE1_WRDI_CMD (0xffL<<8) 1839#define BCE_NVM_WRITE1_SR_DATA (0xffL<<16) 1840 1841 1842 1843/* 1844 * dma_reg definition 1845 * offset: 0xc00 1846 */ 1847#define BCE_DMA_COMMAND 0x00000c00 1848#define BCE_DMA_COMMAND_ENABLE (1L<<0) 1849 1850#define BCE_DMA_STATUS 0x00000c04 1851#define BCE_DMA_STATUS_PAR_ERROR_STATE (1L<<0) 1852#define BCE_DMA_STATUS_READ_TRANSFERS_STAT (1L<<16) 1853#define BCE_DMA_STATUS_READ_DELAY_PCI_CLKS_STAT (1L<<17) 1854#define BCE_DMA_STATUS_BIG_READ_TRANSFERS_STAT (1L<<18) 1855#define BCE_DMA_STATUS_BIG_READ_DELAY_PCI_CLKS_STAT (1L<<19) 1856#define BCE_DMA_STATUS_BIG_READ_RETRY_AFTER_DATA_STAT (1L<<20) 1857#define BCE_DMA_STATUS_WRITE_TRANSFERS_STAT (1L<<21) 1858#define BCE_DMA_STATUS_WRITE_DELAY_PCI_CLKS_STAT (1L<<22) 1859#define BCE_DMA_STATUS_BIG_WRITE_TRANSFERS_STAT (1L<<23) 1860#define BCE_DMA_STATUS_BIG_WRITE_DELAY_PCI_CLKS_STAT (1L<<24) 1861#define BCE_DMA_STATUS_BIG_WRITE_RETRY_AFTER_DATA_STAT (1L<<25) 1862 1863#define BCE_DMA_CONFIG 0x00000c08 1864#define BCE_DMA_CONFIG_DATA_BYTE_SWAP (1L<<0) 1865#define BCE_DMA_CONFIG_DATA_WORD_SWAP (1L<<1) 1866#define BCE_DMA_CONFIG_CNTL_BYTE_SWAP (1L<<4) 1867#define BCE_DMA_CONFIG_CNTL_WORD_SWAP (1L<<5) 1868#define BCE_DMA_CONFIG_ONE_DMA (1L<<6) 1869#define BCE_DMA_CONFIG_CNTL_TWO_DMA (1L<<7) 1870#define BCE_DMA_CONFIG_CNTL_FPGA_MODE (1L<<8) 1871#define BCE_DMA_CONFIG_CNTL_PING_PONG_DMA (1L<<10) 1872#define BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY (1L<<11) 1873#define BCE_DMA_CONFIG_NO_RCHANS_IN_USE (0xfL<<12) 1874#define BCE_DMA_CONFIG_NO_WCHANS_IN_USE (0xfL<<16) 1875#define BCE_DMA_CONFIG_PCI_CLK_CMP_BITS (0x7L<<20) 1876#define BCE_DMA_CONFIG_PCI_FAST_CLK_CMP (1L<<23) 1877#define BCE_DMA_CONFIG_BIG_SIZE (0xfL<<24) 1878#define BCE_DMA_CONFIG_BIG_SIZE_NONE (0x0L<<24) 1879#define BCE_DMA_CONFIG_BIG_SIZE_64 (0x1L<<24) 1880#define BCE_DMA_CONFIG_BIG_SIZE_128 (0x2L<<24) 1881#define BCE_DMA_CONFIG_BIG_SIZE_256 (0x4L<<24) 1882#define BCE_DMA_CONFIG_BIG_SIZE_512 (0x8L<<24) 1883 1884#define BCE_DMA_BLACKOUT 0x00000c0c 1885#define BCE_DMA_BLACKOUT_RD_RETRY_BLACKOUT (0xffL<<0) 1886#define BCE_DMA_BLACKOUT_2ND_RD_RETRY_BLACKOUT (0xffL<<8) 1887#define BCE_DMA_BLACKOUT_WR_RETRY_BLACKOUT (0xffL<<16) 1888 1889#define BCE_DMA_RCHAN_STAT 0x00000c30 1890#define BCE_DMA_RCHAN_STAT_COMP_CODE_0 (0x7L<<0) 1891#define BCE_DMA_RCHAN_STAT_PAR_ERR_0 (1L<<3) 1892#define BCE_DMA_RCHAN_STAT_COMP_CODE_1 (0x7L<<4) 1893#define BCE_DMA_RCHAN_STAT_PAR_ERR_1 (1L<<7) 1894#define BCE_DMA_RCHAN_STAT_COMP_CODE_2 (0x7L<<8) 1895#define BCE_DMA_RCHAN_STAT_PAR_ERR_2 (1L<<11) 1896#define BCE_DMA_RCHAN_STAT_COMP_CODE_3 (0x7L<<12) 1897#define BCE_DMA_RCHAN_STAT_PAR_ERR_3 (1L<<15) 1898#define BCE_DMA_RCHAN_STAT_COMP_CODE_4 (0x7L<<16) 1899#define BCE_DMA_RCHAN_STAT_PAR_ERR_4 (1L<<19) 1900#define BCE_DMA_RCHAN_STAT_COMP_CODE_5 (0x7L<<20) 1901#define BCE_DMA_RCHAN_STAT_PAR_ERR_5 (1L<<23) 1902#define BCE_DMA_RCHAN_STAT_COMP_CODE_6 (0x7L<<24) 1903#define BCE_DMA_RCHAN_STAT_PAR_ERR_6 (1L<<27) 1904#define BCE_DMA_RCHAN_STAT_COMP_CODE_7 (0x7L<<28) 1905#define BCE_DMA_RCHAN_STAT_PAR_ERR_7 (1L<<31) 1906 1907#define BCE_DMA_WCHAN_STAT 0x00000c34 1908#define BCE_DMA_WCHAN_STAT_COMP_CODE_0 (0x7L<<0) 1909#define BCE_DMA_WCHAN_STAT_PAR_ERR_0 (1L<<3) 1910#define BCE_DMA_WCHAN_STAT_COMP_CODE_1 (0x7L<<4) 1911#define BCE_DMA_WCHAN_STAT_PAR_ERR_1 (1L<<7) 1912#define BCE_DMA_WCHAN_STAT_COMP_CODE_2 (0x7L<<8) 1913#define BCE_DMA_WCHAN_STAT_PAR_ERR_2 (1L<<11) 1914#define BCE_DMA_WCHAN_STAT_COMP_CODE_3 (0x7L<<12) 1915#define BCE_DMA_WCHAN_STAT_PAR_ERR_3 (1L<<15) 1916#define BCE_DMA_WCHAN_STAT_COMP_CODE_4 (0x7L<<16) 1917#define BCE_DMA_WCHAN_STAT_PAR_ERR_4 (1L<<19) 1918#define BCE_DMA_WCHAN_STAT_COMP_CODE_5 (0x7L<<20) 1919#define BCE_DMA_WCHAN_STAT_PAR_ERR_5 (1L<<23) 1920#define BCE_DMA_WCHAN_STAT_COMP_CODE_6 (0x7L<<24) 1921#define BCE_DMA_WCHAN_STAT_PAR_ERR_6 (1L<<27) 1922#define BCE_DMA_WCHAN_STAT_COMP_CODE_7 (0x7L<<28) 1923#define BCE_DMA_WCHAN_STAT_PAR_ERR_7 (1L<<31) 1924 1925#define BCE_DMA_RCHAN_ASSIGNMENT 0x00000c38 1926#define BCE_DMA_RCHAN_ASSIGNMENT_0 (0xfL<<0) 1927#define BCE_DMA_RCHAN_ASSIGNMENT_1 (0xfL<<4) 1928#define BCE_DMA_RCHAN_ASSIGNMENT_2 (0xfL<<8) 1929#define BCE_DMA_RCHAN_ASSIGNMENT_3 (0xfL<<12) 1930#define BCE_DMA_RCHAN_ASSIGNMENT_4 (0xfL<<16) 1931#define BCE_DMA_RCHAN_ASSIGNMENT_5 (0xfL<<20) 1932#define BCE_DMA_RCHAN_ASSIGNMENT_6 (0xfL<<24) 1933#define BCE_DMA_RCHAN_ASSIGNMENT_7 (0xfL<<28) 1934 1935#define BCE_DMA_WCHAN_ASSIGNMENT 0x00000c3c 1936#define BCE_DMA_WCHAN_ASSIGNMENT_0 (0xfL<<0) 1937#define BCE_DMA_WCHAN_ASSIGNMENT_1 (0xfL<<4) 1938#define BCE_DMA_WCHAN_ASSIGNMENT_2 (0xfL<<8) 1939#define BCE_DMA_WCHAN_ASSIGNMENT_3 (0xfL<<12) 1940#define BCE_DMA_WCHAN_ASSIGNMENT_4 (0xfL<<16) 1941#define BCE_DMA_WCHAN_ASSIGNMENT_5 (0xfL<<20) 1942#define BCE_DMA_WCHAN_ASSIGNMENT_6 (0xfL<<24) 1943#define BCE_DMA_WCHAN_ASSIGNMENT_7 (0xfL<<28) 1944 1945#define BCE_DMA_RCHAN_STAT_00 0x00000c40 1946#define BCE_DMA_RCHAN_STAT_00_RCHAN_STA_HOST_ADDR_LOW (0xffffffffL<<0) 1947 1948#define BCE_DMA_RCHAN_STAT_01 0x00000c44 1949#define BCE_DMA_RCHAN_STAT_01_RCHAN_STA_HOST_ADDR_HIGH (0xffffffffL<<0) 1950 1951#define BCE_DMA_RCHAN_STAT_02 0x00000c48 1952#define BCE_DMA_RCHAN_STAT_02_LENGTH (0xffffL<<0) 1953#define BCE_DMA_RCHAN_STAT_02_WORD_SWAP (1L<<16) 1954#define BCE_DMA_RCHAN_STAT_02_BYTE_SWAP (1L<<17) 1955#define BCE_DMA_RCHAN_STAT_02_PRIORITY_LVL (1L<<18) 1956 1957#define BCE_DMA_RCHAN_STAT_10 0x00000c4c 1958#define BCE_DMA_RCHAN_STAT_11 0x00000c50 1959#define BCE_DMA_RCHAN_STAT_12 0x00000c54 1960#define BCE_DMA_RCHAN_STAT_20 0x00000c58 1961#define BCE_DMA_RCHAN_STAT_21 0x00000c5c 1962#define BCE_DMA_RCHAN_STAT_22 0x00000c60 1963#define BCE_DMA_RCHAN_STAT_30 0x00000c64 1964#define BCE_DMA_RCHAN_STAT_31 0x00000c68 1965#define BCE_DMA_RCHAN_STAT_32 0x00000c6c 1966#define BCE_DMA_RCHAN_STAT_40 0x00000c70 1967#define BCE_DMA_RCHAN_STAT_41 0x00000c74 1968#define BCE_DMA_RCHAN_STAT_42 0x00000c78 1969#define BCE_DMA_RCHAN_STAT_50 0x00000c7c 1970#define BCE_DMA_RCHAN_STAT_51 0x00000c80 1971#define BCE_DMA_RCHAN_STAT_52 0x00000c84 1972#define BCE_DMA_RCHAN_STAT_60 0x00000c88 1973#define BCE_DMA_RCHAN_STAT_61 0x00000c8c 1974#define BCE_DMA_RCHAN_STAT_62 0x00000c90 1975#define BCE_DMA_RCHAN_STAT_70 0x00000c94 1976#define BCE_DMA_RCHAN_STAT_71 0x00000c98 1977#define BCE_DMA_RCHAN_STAT_72 0x00000c9c 1978#define BCE_DMA_WCHAN_STAT_00 0x00000ca0 1979#define BCE_DMA_WCHAN_STAT_00_WCHAN_STA_HOST_ADDR_LOW (0xffffffffL<<0) 1980 1981#define BCE_DMA_WCHAN_STAT_01 0x00000ca4 1982#define BCE_DMA_WCHAN_STAT_01_WCHAN_STA_HOST_ADDR_HIGH (0xffffffffL<<0) 1983 1984#define BCE_DMA_WCHAN_STAT_02 0x00000ca8 1985#define BCE_DMA_WCHAN_STAT_02_LENGTH (0xffffL<<0) 1986#define BCE_DMA_WCHAN_STAT_02_WORD_SWAP (1L<<16) 1987#define BCE_DMA_WCHAN_STAT_02_BYTE_SWAP (1L<<17) 1988#define BCE_DMA_WCHAN_STAT_02_PRIORITY_LVL (1L<<18) 1989 1990#define BCE_DMA_WCHAN_STAT_10 0x00000cac 1991#define BCE_DMA_WCHAN_STAT_11 0x00000cb0 1992#define BCE_DMA_WCHAN_STAT_12 0x00000cb4 1993#define BCE_DMA_WCHAN_STAT_20 0x00000cb8 1994#define BCE_DMA_WCHAN_STAT_21 0x00000cbc 1995#define BCE_DMA_WCHAN_STAT_22 0x00000cc0 1996#define BCE_DMA_WCHAN_STAT_30 0x00000cc4 1997#define BCE_DMA_WCHAN_STAT_31 0x00000cc8 1998#define BCE_DMA_WCHAN_STAT_32 0x00000ccc 1999#define BCE_DMA_WCHAN_STAT_40 0x00000cd0 2000#define BCE_DMA_WCHAN_STAT_41 0x00000cd4 2001#define BCE_DMA_WCHAN_STAT_42 0x00000cd8 2002#define BCE_DMA_WCHAN_STAT_50 0x00000cdc 2003#define BCE_DMA_WCHAN_STAT_51 0x00000ce0 2004#define BCE_DMA_WCHAN_STAT_52 0x00000ce4 2005#define BCE_DMA_WCHAN_STAT_60 0x00000ce8 2006#define BCE_DMA_WCHAN_STAT_61 0x00000cec 2007#define BCE_DMA_WCHAN_STAT_62 0x00000cf0 2008#define BCE_DMA_WCHAN_STAT_70 0x00000cf4 2009#define BCE_DMA_WCHAN_STAT_71 0x00000cf8 2010#define BCE_DMA_WCHAN_STAT_72 0x00000cfc 2011#define BCE_DMA_ARB_STAT_00 0x00000d00 2012#define BCE_DMA_ARB_STAT_00_MASTER (0xffffL<<0) 2013#define BCE_DMA_ARB_STAT_00_MASTER_ENC (0xffL<<16) 2014#define BCE_DMA_ARB_STAT_00_CUR_BINMSTR (0xffL<<24) 2015 2016#define BCE_DMA_ARB_STAT_01 0x00000d04 2017#define BCE_DMA_ARB_STAT_01_LPR_RPTR (0xfL<<0) 2018#define BCE_DMA_ARB_STAT_01_LPR_WPTR (0xfL<<4) 2019#define BCE_DMA_ARB_STAT_01_LPB_RPTR (0xfL<<8) 2020#define BCE_DMA_ARB_STAT_01_LPB_WPTR (0xfL<<12) 2021#define BCE_DMA_ARB_STAT_01_HPR_RPTR (0xfL<<16) 2022#define BCE_DMA_ARB_STAT_01_HPR_WPTR (0xfL<<20) 2023#define BCE_DMA_ARB_STAT_01_HPB_RPTR (0xfL<<24) 2024#define BCE_DMA_ARB_STAT_01_HPB_WPTR (0xfL<<28) 2025 2026#define BCE_DMA_FUSE_CTRL0_CMD 0x00000f00 2027#define BCE_DMA_FUSE_CTRL0_CMD_PWRUP_DONE (1L<<0) 2028#define BCE_DMA_FUSE_CTRL0_CMD_SHIFT_DONE (1L<<1) 2029#define BCE_DMA_FUSE_CTRL0_CMD_SHIFT (1L<<2) 2030#define BCE_DMA_FUSE_CTRL0_CMD_LOAD (1L<<3) 2031#define BCE_DMA_FUSE_CTRL0_CMD_SEL (0xfL<<8) 2032 2033#define BCE_DMA_FUSE_CTRL0_DATA 0x00000f04 2034#define BCE_DMA_FUSE_CTRL1_CMD 0x00000f08 2035#define BCE_DMA_FUSE_CTRL1_CMD_PWRUP_DONE (1L<<0) 2036#define BCE_DMA_FUSE_CTRL1_CMD_SHIFT_DONE (1L<<1) 2037#define BCE_DMA_FUSE_CTRL1_CMD_SHIFT (1L<<2) 2038#define BCE_DMA_FUSE_CTRL1_CMD_LOAD (1L<<3) 2039#define BCE_DMA_FUSE_CTRL1_CMD_SEL (0xfL<<8) 2040 2041#define BCE_DMA_FUSE_CTRL1_DATA 0x00000f0c 2042#define BCE_DMA_FUSE_CTRL2_CMD 0x00000f10 2043#define BCE_DMA_FUSE_CTRL2_CMD_PWRUP_DONE (1L<<0) 2044#define BCE_DMA_FUSE_CTRL2_CMD_SHIFT_DONE (1L<<1) 2045#define BCE_DMA_FUSE_CTRL2_CMD_SHIFT (1L<<2) 2046#define BCE_DMA_FUSE_CTRL2_CMD_LOAD (1L<<3) 2047#define BCE_DMA_FUSE_CTRL2_CMD_SEL (0xfL<<8) 2048 2049#define BCE_DMA_FUSE_CTRL2_DATA 0x00000f14 2050 2051 2052/* 2053 * context_reg definition 2054 * offset: 0x1000 2055 */ 2056#define BCE_CTX_COMMAND 0x00001000 2057#define BCE_CTX_COMMAND_ENABLED (1L<<0) 2058 2059#define BCE_CTX_STATUS 0x00001004 2060#define BCE_CTX_STATUS_LOCK_WAIT (1L<<0) 2061#define BCE_CTX_STATUS_READ_STAT (1L<<16) 2062#define BCE_CTX_STATUS_WRITE_STAT (1L<<17) 2063#define BCE_CTX_STATUS_ACC_STALL_STAT (1L<<18) 2064#define BCE_CTX_STATUS_LOCK_STALL_STAT (1L<<19) 2065 2066#define BCE_CTX_VIRT_ADDR 0x00001008 2067#define BCE_CTX_VIRT_ADDR_VIRT_ADDR (0x7fffL<<6) 2068 2069#define BCE_CTX_PAGE_TBL 0x0000100c 2070#define BCE_CTX_PAGE_TBL_PAGE_TBL (0x3fffL<<6) 2071 2072#define BCE_CTX_DATA_ADR 0x00001010 2073#define BCE_CTX_DATA_ADR_DATA_ADR (0x7ffffL<<2) 2074 2075#define BCE_CTX_DATA 0x00001014 2076#define BCE_CTX_LOCK 0x00001018 2077#define BCE_CTX_LOCK_TYPE (0x7L<<0) 2078#define BCE_CTX_LOCK_TYPE_LOCK_TYPE_VOID (0x0L<<0) 2079#define BCE_CTX_LOCK_TYPE_LOCK_TYPE_COMPLETE (0x7L<<0) 2080#define BCE_CTX_LOCK_TYPE_LOCK_TYPE_PROTOCOL (0x1L<<0) 2081#define BCE_CTX_LOCK_TYPE_LOCK_TYPE_TX (0x2L<<0) 2082#define BCE_CTX_LOCK_TYPE_LOCK_TYPE_TIMER (0x4L<<0) 2083#define BCE_CTX_LOCK_CID_VALUE (0x3fffL<<7) 2084#define BCE_CTX_LOCK_GRANTED (1L<<26) 2085#define BCE_CTX_LOCK_MODE (0x7L<<27) 2086#define BCE_CTX_LOCK_MODE_UNLOCK (0x0L<<27) 2087#define BCE_CTX_LOCK_MODE_IMMEDIATE (0x1L<<27) 2088#define BCE_CTX_LOCK_MODE_SURE (0x2L<<27) 2089#define BCE_CTX_LOCK_STATUS (1L<<30) 2090#define BCE_CTX_LOCK_REQ (1L<<31) 2091 2092#define BCE_CTX_ACCESS_STATUS 0x00001040 2093#define BCE_CTX_ACCESS_STATUS_MASTERENCODED (0xfL<<0) 2094#define BCE_CTX_ACCESS_STATUS_ACCESSMEMORYSM (0x3L<<10) 2095#define BCE_CTX_ACCESS_STATUS_PAGETABLEINITSM (0x3L<<12) 2096#define BCE_CTX_ACCESS_STATUS_ACCESSMEMORYINITSM (0x3L<<14) 2097#define BCE_CTX_ACCESS_STATUS_QUALIFIED_REQUEST (0x7ffL<<17) 2098 2099#define BCE_CTX_DBG_LOCK_STATUS 0x00001044 2100#define BCE_CTX_DBG_LOCK_STATUS_SM (0x3ffL<<0) 2101#define BCE_CTX_DBG_LOCK_STATUS_MATCH (0x3ffL<<22) 2102 2103#define BCE_CTX_CHNL_LOCK_STATUS_0 0x00001080 2104#define BCE_CTX_CHNL_LOCK_STATUS_0_CID (0x3fffL<<0) 2105#define BCE_CTX_CHNL_LOCK_STATUS_0_TYPE (0x3L<<14) 2106#define BCE_CTX_CHNL_LOCK_STATUS_0_MODE (1L<<16) 2107 2108#define BCE_CTX_CHNL_LOCK_STATUS_1 0x00001084 2109#define BCE_CTX_CHNL_LOCK_STATUS_2 0x00001088 2110#define BCE_CTX_CHNL_LOCK_STATUS_3 0x0000108c 2111#define BCE_CTX_CHNL_LOCK_STATUS_4 0x00001090 2112#define BCE_CTX_CHNL_LOCK_STATUS_5 0x00001094 2113#define BCE_CTX_CHNL_LOCK_STATUS_6 0x00001098 2114#define BCE_CTX_CHNL_LOCK_STATUS_7 0x0000109c 2115#define BCE_CTX_CHNL_LOCK_STATUS_8 0x000010a0 2116 2117 2118/* 2119 * emac_reg definition 2120 * offset: 0x1400 2121 */ 2122#define BCE_EMAC_MODE 0x00001400 2123#define BCE_EMAC_MODE_RESET (1L<<0) 2124#define BCE_EMAC_MODE_HALF_DUPLEX (1L<<1) 2125#define BCE_EMAC_MODE_PORT (0x3L<<2) 2126#define BCE_EMAC_MODE_PORT_NONE (0L<<2) 2127#define BCE_EMAC_MODE_PORT_MII (1L<<2) 2128#define BCE_EMAC_MODE_PORT_GMII (2L<<2) 2129#define BCE_EMAC_MODE_PORT_MII_10 (3L<<2) 2130#define BCE_EMAC_MODE_MAC_LOOP (1L<<4) 2131#define BCE_EMAC_MODE_25G (1L<<5) 2132#define BCE_EMAC_MODE_TAGGED_MAC_CTL (1L<<7) 2133#define BCE_EMAC_MODE_TX_BURST (1L<<8) 2134#define BCE_EMAC_MODE_MAX_DEFER_DROP_ENA (1L<<9) 2135#define BCE_EMAC_MODE_EXT_LINK_POL (1L<<10) 2136#define BCE_EMAC_MODE_FORCE_LINK (1L<<11) 2137#define BCE_EMAC_MODE_MPKT (1L<<18) 2138#define BCE_EMAC_MODE_MPKT_RCVD (1L<<19) 2139#define BCE_EMAC_MODE_ACPI_RCVD (1L<<20) 2140 2141#define BCE_EMAC_STATUS 0x00001404 2142#define BCE_EMAC_STATUS_LINK (1L<<11) 2143#define BCE_EMAC_STATUS_LINK_CHANGE (1L<<12) 2144#define BCE_EMAC_STATUS_MI_COMPLETE (1L<<22) 2145#define BCE_EMAC_STATUS_MI_INT (1L<<23) 2146#define BCE_EMAC_STATUS_AP_ERROR (1L<<24) 2147#define BCE_EMAC_STATUS_PARITY_ERROR_STATE (1L<<31) 2148 2149#define BCE_EMAC_ATTENTION_ENA 0x00001408 2150#define BCE_EMAC_ATTENTION_ENA_LINK (1L<<11) 2151#define BCE_EMAC_ATTENTION_ENA_MI_COMPLETE (1L<<22) 2152#define BCE_EMAC_ATTENTION_ENA_MI_INT (1L<<23) 2153#define BCE_EMAC_ATTENTION_ENA_AP_ERROR (1L<<24) 2154 2155#define BCE_EMAC_LED 0x0000140c 2156#define BCE_EMAC_LED_OVERRIDE (1L<<0) 2157#define BCE_EMAC_LED_1000MB_OVERRIDE (1L<<1) 2158#define BCE_EMAC_LED_100MB_OVERRIDE (1L<<2) 2159#define BCE_EMAC_LED_10MB_OVERRIDE (1L<<3) 2160#define BCE_EMAC_LED_TRAFFIC_OVERRIDE (1L<<4) 2161#define BCE_EMAC_LED_BLNK_TRAFFIC (1L<<5) 2162#define BCE_EMAC_LED_TRAFFIC (1L<<6) 2163#define BCE_EMAC_LED_1000MB (1L<<7) 2164#define BCE_EMAC_LED_100MB (1L<<8) 2165#define BCE_EMAC_LED_10MB (1L<<9) 2166#define BCE_EMAC_LED_TRAFFIC_STAT (1L<<10) 2167#define BCE_EMAC_LED_BLNK_RATE (0xfffL<<19) 2168#define BCE_EMAC_LED_BLNK_RATE_ENA (1L<<31) 2169 2170#define BCE_EMAC_MAC_MATCH0 0x00001410 2171#define BCE_EMAC_MAC_MATCH1 0x00001414 2172#define BCE_EMAC_MAC_MATCH2 0x00001418 2173#define BCE_EMAC_MAC_MATCH3 0x0000141c 2174#define BCE_EMAC_MAC_MATCH4 0x00001420 2175#define BCE_EMAC_MAC_MATCH5 0x00001424 2176#define BCE_EMAC_MAC_MATCH6 0x00001428 2177#define BCE_EMAC_MAC_MATCH7 0x0000142c 2178#define BCE_EMAC_MAC_MATCH8 0x00001430 2179#define BCE_EMAC_MAC_MATCH9 0x00001434 2180#define BCE_EMAC_MAC_MATCH10 0x00001438 2181#define BCE_EMAC_MAC_MATCH11 0x0000143c 2182#define BCE_EMAC_MAC_MATCH12 0x00001440 2183#define BCE_EMAC_MAC_MATCH13 0x00001444 2184#define BCE_EMAC_MAC_MATCH14 0x00001448 2185#define BCE_EMAC_MAC_MATCH15 0x0000144c 2186#define BCE_EMAC_MAC_MATCH16 0x00001450 2187#define BCE_EMAC_MAC_MATCH17 0x00001454 2188#define BCE_EMAC_MAC_MATCH18 0x00001458 2189#define BCE_EMAC_MAC_MATCH19 0x0000145c 2190#define BCE_EMAC_MAC_MATCH20 0x00001460 2191#define BCE_EMAC_MAC_MATCH21 0x00001464 2192#define BCE_EMAC_MAC_MATCH22 0x00001468 2193#define BCE_EMAC_MAC_MATCH23 0x0000146c 2194#define BCE_EMAC_MAC_MATCH24 0x00001470 2195#define BCE_EMAC_MAC_MATCH25 0x00001474 2196#define BCE_EMAC_MAC_MATCH26 0x00001478 2197#define BCE_EMAC_MAC_MATCH27 0x0000147c 2198#define BCE_EMAC_MAC_MATCH28 0x00001480 2199#define BCE_EMAC_MAC_MATCH29 0x00001484 2200#define BCE_EMAC_MAC_MATCH30 0x00001488 2201#define BCE_EMAC_MAC_MATCH31 0x0000148c 2202#define BCE_EMAC_BACKOFF_SEED 0x00001498 2203#define BCE_EMAC_BACKOFF_SEED_EMAC_BACKOFF_SEED (0x3ffL<<0) 2204 2205#define BCE_EMAC_RX_MTU_SIZE 0x0000149c 2206#define BCE_EMAC_RX_MTU_SIZE_MTU_SIZE (0xffffL<<0) 2207#define BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31) 2208 2209#define BCE_EMAC_SERDES_CNTL 0x000014a4 2210#define BCE_EMAC_SERDES_CNTL_RXR (0x7L<<0) 2211#define BCE_EMAC_SERDES_CNTL_RXG (0x3L<<3) 2212#define BCE_EMAC_SERDES_CNTL_RXCKSEL (1L<<6) 2213#define BCE_EMAC_SERDES_CNTL_TXBIAS (0x7L<<7) 2214#define BCE_EMAC_SERDES_CNTL_BGMAX (1L<<10) 2215#define BCE_EMAC_SERDES_CNTL_BGMIN (1L<<11) 2216#define BCE_EMAC_SERDES_CNTL_TXMODE (1L<<12) 2217#define BCE_EMAC_SERDES_CNTL_TXEDGE (1L<<13) 2218#define BCE_EMAC_SERDES_CNTL_SERDES_MODE (1L<<14) 2219#define BCE_EMAC_SERDES_CNTL_PLLTEST (1L<<15) 2220#define BCE_EMAC_SERDES_CNTL_CDET_EN (1L<<16) 2221#define BCE_EMAC_SERDES_CNTL_TBI_LBK (1L<<17) 2222#define BCE_EMAC_SERDES_CNTL_REMOTE_LBK (1L<<18) 2223#define BCE_EMAC_SERDES_CNTL_REV_PHASE (1L<<19) 2224#define BCE_EMAC_SERDES_CNTL_REGCTL12 (0x3L<<20) 2225#define BCE_EMAC_SERDES_CNTL_REGCTL25 (0x3L<<22) 2226 2227#define BCE_EMAC_SERDES_STATUS 0x000014a8 2228#define BCE_EMAC_SERDES_STATUS_RX_STAT (0xffL<<0) 2229#define BCE_EMAC_SERDES_STATUS_COMMA_DET (1L<<8) 2230 2231#define BCE_EMAC_MDIO_COMM 0x000014ac 2232#define BCE_EMAC_MDIO_COMM_DATA (0xffffL<<0) 2233#define BCE_EMAC_MDIO_COMM_REG_ADDR (0x1fL<<16) 2234#define BCE_EMAC_MDIO_COMM_PHY_ADDR (0x1fL<<21) 2235#define BCE_EMAC_MDIO_COMM_COMMAND (0x3L<<26) 2236#define BCE_EMAC_MDIO_COMM_COMMAND_UNDEFINED_0 (0L<<26) 2237#define BCE_EMAC_MDIO_COMM_COMMAND_WRITE (1L<<26) 2238#define BCE_EMAC_MDIO_COMM_COMMAND_READ (2L<<26) 2239#define BCE_EMAC_MDIO_COMM_COMMAND_UNDEFINED_3 (3L<<26) 2240#define BCE_EMAC_MDIO_COMM_FAIL (1L<<28) 2241#define BCE_EMAC_MDIO_COMM_START_BUSY (1L<<29) 2242#define BCE_EMAC_MDIO_COMM_DISEXT (1L<<30) 2243 2244#define BCE_EMAC_MDIO_STATUS 0x000014b0 2245#define BCE_EMAC_MDIO_STATUS_LINK (1L<<0) 2246#define BCE_EMAC_MDIO_STATUS_10MB (1L<<1) 2247 2248#define BCE_EMAC_MDIO_MODE 0x000014b4 2249#define BCE_EMAC_MDIO_MODE_SHORT_PREAMBLE (1L<<1) 2250#define BCE_EMAC_MDIO_MODE_AUTO_POLL (1L<<4) 2251#define BCE_EMAC_MDIO_MODE_BIT_BANG (1L<<8) 2252#define BCE_EMAC_MDIO_MODE_MDIO (1L<<9) 2253#define BCE_EMAC_MDIO_MODE_MDIO_OE (1L<<10) 2254#define BCE_EMAC_MDIO_MODE_MDC (1L<<11) 2255#define BCE_EMAC_MDIO_MODE_MDINT (1L<<12) 2256#define BCE_EMAC_MDIO_MODE_CLOCK_CNT (0x1fL<<16) 2257 2258#define BCE_EMAC_MDIO_AUTO_STATUS 0x000014b8 2259#define BCE_EMAC_MDIO_AUTO_STATUS_AUTO_ERR (1L<<0) 2260 2261#define BCE_EMAC_TX_MODE 0x000014bc 2262#define BCE_EMAC_TX_MODE_RESET (1L<<0) 2263#define BCE_EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3) 2264#define BCE_EMAC_TX_MODE_FLOW_EN (1L<<4) 2265#define BCE_EMAC_TX_MODE_BIG_BACKOFF (1L<<5) 2266#define BCE_EMAC_TX_MODE_LONG_PAUSE (1L<<6) 2267#define BCE_EMAC_TX_MODE_LINK_AWARE (1L<<7) 2268 2269#define BCE_EMAC_TX_STATUS 0x000014c0 2270#define BCE_EMAC_TX_STATUS_XOFFED (1L<<0) 2271#define BCE_EMAC_TX_STATUS_XOFF_SENT (1L<<1) 2272#define BCE_EMAC_TX_STATUS_XON_SENT (1L<<2) 2273#define BCE_EMAC_TX_STATUS_LINK_UP (1L<<3) 2274#define BCE_EMAC_TX_STATUS_UNDERRUN (1L<<4) 2275 2276#define BCE_EMAC_TX_LENGTHS 0x000014c4 2277#define BCE_EMAC_TX_LENGTHS_SLOT (0xffL<<0) 2278#define BCE_EMAC_TX_LENGTHS_IPG (0xfL<<8) 2279#define BCE_EMAC_TX_LENGTHS_IPG_CRS (0x3L<<12) 2280 2281#define BCE_EMAC_RX_MODE 0x000014c8 2282#define BCE_EMAC_RX_MODE_RESET (1L<<0) 2283#define BCE_EMAC_RX_MODE_FLOW_EN (1L<<2) 2284#define BCE_EMAC_RX_MODE_KEEP_MAC_CONTROL (1L<<3) 2285#define BCE_EMAC_RX_MODE_KEEP_PAUSE (1L<<4) 2286#define BCE_EMAC_RX_MODE_ACCEPT_OVERSIZE (1L<<5) 2287#define BCE_EMAC_RX_MODE_ACCEPT_RUNTS (1L<<6) 2288#define BCE_EMAC_RX_MODE_LLC_CHK (1L<<7) 2289#define BCE_EMAC_RX_MODE_PROMISCUOUS (1L<<8) 2290#define BCE_EMAC_RX_MODE_NO_CRC_CHK (1L<<9) 2291#define BCE_EMAC_RX_MODE_KEEP_VLAN_TAG (1L<<10) 2292#define BCE_EMAC_RX_MODE_FILT_BROADCAST (1L<<11) 2293#define BCE_EMAC_RX_MODE_SORT_MODE (1L<<12) 2294 2295#define BCE_EMAC_RX_STATUS 0x000014cc 2296#define BCE_EMAC_RX_STATUS_FFED (1L<<0) 2297#define BCE_EMAC_RX_STATUS_FF_RECEIVED (1L<<1) 2298#define BCE_EMAC_RX_STATUS_N_RECEIVED (1L<<2) 2299 2300#define BCE_EMAC_MULTICAST_HASH0 0x000014d0 2301#define BCE_EMAC_MULTICAST_HASH1 0x000014d4 2302#define BCE_EMAC_MULTICAST_HASH2 0x000014d8 2303#define BCE_EMAC_MULTICAST_HASH3 0x000014dc 2304#define BCE_EMAC_MULTICAST_HASH4 0x000014e0 2305#define BCE_EMAC_MULTICAST_HASH5 0x000014e4 2306#define BCE_EMAC_MULTICAST_HASH6 0x000014e8 2307#define BCE_EMAC_MULTICAST_HASH7 0x000014ec 2308#define BCE_EMAC_RX_STAT_IFHCINOCTETS 0x00001500 2309#define BCE_EMAC_RX_STAT_IFHCINBADOCTETS 0x00001504 2310#define BCE_EMAC_RX_STAT_ETHERSTATSFRAGMENTS 0x00001508 2311#define BCE_EMAC_RX_STAT_IFHCINUCASTPKTS 0x0000150c 2312#define BCE_EMAC_RX_STAT_IFHCINMULTICASTPKTS 0x00001510 2313#define BCE_EMAC_RX_STAT_IFHCINBROADCASTPKTS 0x00001514 2314#define BCE_EMAC_RX_STAT_DOT3STATSFCSERRORS 0x00001518 2315#define BCE_EMAC_RX_STAT_DOT3STATSALIGNMENTERRORS 0x0000151c 2316#define BCE_EMAC_RX_STAT_DOT3STATSCARRIERSENSEERRORS 0x00001520 2317#define BCE_EMAC_RX_STAT_XONPAUSEFRAMESRECEIVED 0x00001524 2318#define BCE_EMAC_RX_STAT_XOFFPAUSEFRAMESRECEIVED 0x00001528 2319#define BCE_EMAC_RX_STAT_MACCONTROLFRAMESRECEIVED 0x0000152c 2320#define BCE_EMAC_RX_STAT_XOFFSTATEENTERED 0x00001530 2321#define BCE_EMAC_RX_STAT_DOT3STATSFRAMESTOOLONG 0x00001534 2322#define BCE_EMAC_RX_STAT_ETHERSTATSJABBERS 0x00001538 2323#define BCE_EMAC_RX_STAT_ETHERSTATSUNDERSIZEPKTS 0x0000153c 2324#define BCE_EMAC_RX_STAT_ETHERSTATSPKTS64OCTETS 0x00001540 2325#define BCE_EMAC_RX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS 0x00001544 2326#define BCE_EMAC_RX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS 0x00001548 2327#define BCE_EMAC_RX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS 0x0000154c 2328#define BCE_EMAC_RX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS 0x00001550 2329#define BCE_EMAC_RX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS 0x00001554 2330#define BCE_EMAC_RX_STAT_ETHERSTATSPKTS1523OCTETSTO9022OCTETS 0x00001558 2331#define BCE_EMAC_RXMAC_DEBUG0 0x0000155c 2332#define BCE_EMAC_RXMAC_DEBUG1 0x00001560 2333#define BCE_EMAC_RXMAC_DEBUG1_LENGTH_NE_BYTE_COUNT (1L<<0) 2334#define BCE_EMAC_RXMAC_DEBUG1_LENGTH_OUT_RANGE (1L<<1) 2335#define BCE_EMAC_RXMAC_DEBUG1_BAD_CRC (1L<<2) 2336#define BCE_EMAC_RXMAC_DEBUG1_RX_ERROR (1L<<3) 2337#define BCE_EMAC_RXMAC_DEBUG1_ALIGN_ERROR (1L<<4) 2338#define BCE_EMAC_RXMAC_DEBUG1_LAST_DATA (1L<<5) 2339#define BCE_EMAC_RXMAC_DEBUG1_ODD_BYTE_START (1L<<6) 2340#define BCE_EMAC_RXMAC_DEBUG1_BYTE_COUNT (0xffffL<<7) 2341#define BCE_EMAC_RXMAC_DEBUG1_SLOT_TIME (0xffL<<23) 2342 2343#define BCE_EMAC_RXMAC_DEBUG2 0x00001564 2344#define BCE_EMAC_RXMAC_DEBUG2_SM_STATE (0x7L<<0) 2345#define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_IDLE (0x0L<<0) 2346#define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_SFD (0x1L<<0) 2347#define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_DATA (0x2L<<0) 2348#define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_SKEEP (0x3L<<0) 2349#define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_EXT (0x4L<<0) 2350#define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_DROP (0x5L<<0) 2351#define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_SDROP (0x6L<<0) 2352#define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_FC (0x7L<<0) 2353#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE (0xfL<<3) 2354#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_IDLE (0x0L<<3) 2355#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA0 (0x1L<<3) 2356#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA1 (0x2L<<3) 2357#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA2 (0x3L<<3) 2358#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA3 (0x4L<<3) 2359#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_ABORT (0x5L<<3) 2360#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_WAIT (0x6L<<3) 2361#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_STATUS (0x7L<<3) 2362#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_LAST (0x8L<<3) 2363#define BCE_EMAC_RXMAC_DEBUG2_BYTE_IN (0xffL<<7) 2364#define BCE_EMAC_RXMAC_DEBUG2_FALSEC (1L<<15) 2365#define BCE_EMAC_RXMAC_DEBUG2_TAGGED (1L<<16) 2366#define BCE_EMAC_RXMAC_DEBUG2_PAUSE_STATE (1L<<18) 2367#define BCE_EMAC_RXMAC_DEBUG2_PAUSE_STATE_IDLE (0L<<18) 2368#define BCE_EMAC_RXMAC_DEBUG2_PAUSE_STATE_PAUSED (1L<<18) 2369#define BCE_EMAC_RXMAC_DEBUG2_SE_COUNTER (0xfL<<19) 2370#define BCE_EMAC_RXMAC_DEBUG2_QUANTA (0x1fL<<23) 2371 2372#define BCE_EMAC_RXMAC_DEBUG3 0x00001568 2373#define BCE_EMAC_RXMAC_DEBUG3_PAUSE_CTR (0xffffL<<0) 2374#define BCE_EMAC_RXMAC_DEBUG3_TMP_PAUSE_CTR (0xffffL<<16) 2375 2376#define BCE_EMAC_RXMAC_DEBUG4 0x0000156c 2377#define BCE_EMAC_RXMAC_DEBUG4_TYPE_FIELD (0xffffL<<0) 2378#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE (0x3fL<<16) 2379#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_IDLE (0x0L<<16) 2380#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC2 (0x1L<<16) 2381#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC3 (0x2L<<16) 2382#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UNI (0x3L<<16) 2383#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC2 (0x7L<<16) 2384#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC3 (0x5L<<16) 2385#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA1 (0x6L<<16) 2386#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA2 (0x7L<<16) 2387#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA3 (0x8L<<16) 2388#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MC2 (0x9L<<16) 2389#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MC3 (0xaL<<16) 2390#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT1 (0xeL<<16) 2391#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT2 (0xfL<<16) 2392#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MCHECK (0x10L<<16) 2393#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MC (0x11L<<16) 2394#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BC2 (0x12L<<16) 2395#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BC3 (0x13L<<16) 2396#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA1 (0x14L<<16) 2397#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA2 (0x15L<<16) 2398#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA3 (0x16L<<16) 2399#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BTYPE (0x17L<<16) 2400#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BC (0x18L<<16) 2401#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_PTYPE (0x19L<<16) 2402#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_CMD (0x1aL<<16) 2403#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MAC (0x1bL<<16) 2404#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_LATCH (0x1cL<<16) 2405#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_XOFF (0x1dL<<16) 2406#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_XON (0x1eL<<16) 2407#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_PAUSED (0x1fL<<16) 2408#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_NPAUSED (0x20L<<16) 2409#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_TTYPE (0x21L<<16) 2410#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_TVAL (0x22L<<16) 2411#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_USA1 (0x23L<<16) 2412#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_USA2 (0x24L<<16) 2413#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_USA3 (0x25L<<16) 2414#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UTYPE (0x26L<<16) 2415#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UTTYPE (0x27L<<16) 2416#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UTVAL (0x28L<<16) 2417#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MTYPE (0x29L<<16) 2418#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_DROP (0x2aL<<16) 2419#define BCE_EMAC_RXMAC_DEBUG4_DROP_PKT (1L<<22) 2420#define BCE_EMAC_RXMAC_DEBUG4_SLOT_FILLED (1L<<23) 2421#define BCE_EMAC_RXMAC_DEBUG4_FALSE_CARRIER (1L<<24) 2422#define BCE_EMAC_RXMAC_DEBUG4_LAST_DATA (1L<<25) 2423#define BCE_EMAC_RXMAC_DEBUG4_sfd_FOUND (1L<<26) 2424#define BCE_EMAC_RXMAC_DEBUG4_ADVANCE (1L<<27) 2425#define BCE_EMAC_RXMAC_DEBUG4_START (1L<<28) 2426 2427#define BCE_EMAC_RXMAC_DEBUG5 0x00001570 2428#define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM (0x7L<<0) 2429#define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_IDLE (0L<<0) 2430#define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_EOF (1L<<0) 2431#define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_STAT (2L<<0) 2432#define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4FCRC (3L<<0) 2433#define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4RDE (4L<<0) 2434#define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4ALL (5L<<0) 2435#define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_1WD_WAIT_STAT (6L<<0) 2436#define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1 (0x7L<<4) 2437#define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_VDW (0x0L<<4) 2438#define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_STAT (0x1L<<4) 2439#define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_AEOF (0x2L<<4) 2440#define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_NEOF (0x3L<<4) 2441#define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SOF (0x4L<<4) 2442#define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SAEOF (0x6L<<4) 2443#define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SNEOF (0x7L<<4) 2444#define BCE_EMAC_RXMAC_DEBUG5_EOF_DETECTED (1L<<7) 2445#define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF0 (0x7L<<8) 2446#define BCE_EMAC_RXMAC_DEBUG5_RPM_IDI_FIFO_FULL (1L<<11) 2447#define BCE_EMAC_RXMAC_DEBUG5_LOAD_CCODE (1L<<12) 2448#define BCE_EMAC_RXMAC_DEBUG5_LOAD_DATA (1L<<13) 2449#define BCE_EMAC_RXMAC_DEBUG5_LOAD_STAT (1L<<14) 2450#define BCE_EMAC_RXMAC_DEBUG5_CLR_STAT (1L<<15) 2451#define BCE_EMAC_RXMAC_DEBUG5_IDI_RPM_CCODE (0x3L<<16) 2452#define BCE_EMAC_RXMAC_DEBUG5_IDI_RPM_ACCEPT (1L<<19) 2453#define BCE_EMAC_RXMAC_DEBUG5_FMLEN (0xfffL<<20) 2454 2455#define BCE_EMAC_RX_STAT_AC0 0x00001580 2456#define BCE_EMAC_RX_STAT_AC1 0x00001584 2457#define BCE_EMAC_RX_STAT_AC2 0x00001588 2458#define BCE_EMAC_RX_STAT_AC3 0x0000158c 2459#define BCE_EMAC_RX_STAT_AC4 0x00001590 2460#define BCE_EMAC_RX_STAT_AC5 0x00001594 2461#define BCE_EMAC_RX_STAT_AC6 0x00001598 2462#define BCE_EMAC_RX_STAT_AC7 0x0000159c 2463#define BCE_EMAC_RX_STAT_AC8 0x000015a0 2464#define BCE_EMAC_RX_STAT_AC9 0x000015a4 2465#define BCE_EMAC_RX_STAT_AC10 0x000015a8 2466#define BCE_EMAC_RX_STAT_AC11 0x000015ac 2467#define BCE_EMAC_RX_STAT_AC12 0x000015b0 2468#define BCE_EMAC_RX_STAT_AC13 0x000015b4 2469#define BCE_EMAC_RX_STAT_AC14 0x000015b8 2470#define BCE_EMAC_RX_STAT_AC15 0x000015bc 2471#define BCE_EMAC_RX_STAT_AC16 0x000015c0 2472#define BCE_EMAC_RX_STAT_AC17 0x000015c4 2473#define BCE_EMAC_RX_STAT_AC18 0x000015c8 2474#define BCE_EMAC_RX_STAT_AC19 0x000015cc 2475#define BCE_EMAC_RX_STAT_AC20 0x000015d0 2476#define BCE_EMAC_RX_STAT_AC21 0x000015d4 2477#define BCE_EMAC_RX_STAT_AC22 0x000015d8 2478#define BCE_EMAC_RXMAC_SUC_DBG_OVERRUNVEC 0x000015dc 2479#define BCE_EMAC_TX_STAT_IFHCOUTOCTETS 0x00001600 2480#define BCE_EMAC_TX_STAT_IFHCOUTBADOCTETS 0x00001604 2481#define BCE_EMAC_TX_STAT_ETHERSTATSCOLLISIONS 0x00001608 2482#define BCE_EMAC_TX_STAT_OUTXONSENT 0x0000160c 2483#define BCE_EMAC_TX_STAT_OUTXOFFSENT 0x00001610 2484#define BCE_EMAC_TX_STAT_FLOWCONTROLDONE 0x00001614 2485#define BCE_EMAC_TX_STAT_DOT3STATSSINGLECOLLISIONFRAMES 0x00001618 2486#define BCE_EMAC_TX_STAT_DOT3STATSMULTIPLECOLLISIONFRAMES 0x0000161c 2487#define BCE_EMAC_TX_STAT_DOT3STATSDEFERREDTRANSMISSIONS 0x00001620 2488#define BCE_EMAC_TX_STAT_DOT3STATSEXCESSIVECOLLISIONS 0x00001624 2489#define BCE_EMAC_TX_STAT_DOT3STATSLATECOLLISIONS 0x00001628 2490#define BCE_EMAC_TX_STAT_IFHCOUTUCASTPKTS 0x0000162c 2491#define BCE_EMAC_TX_STAT_IFHCOUTMULTICASTPKTS 0x00001630 2492#define BCE_EMAC_TX_STAT_IFHCOUTBROADCASTPKTS 0x00001634 2493#define BCE_EMAC_TX_STAT_ETHERSTATSPKTS64OCTETS 0x00001638 2494#define BCE_EMAC_TX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS 0x0000163c 2495#define BCE_EMAC_TX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS 0x00001640 2496#define BCE_EMAC_TX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS 0x00001644 2497#define BCE_EMAC_TX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS 0x00001648 2498#define BCE_EMAC_TX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS 0x0000164c 2499#define BCE_EMAC_TX_STAT_ETHERSTATSPKTS1523OCTETSTO9022OCTETS 0x00001650 2500#define BCE_EMAC_TX_STAT_DOT3STATSINTERNALMACTRANSMITERRORS 0x00001654 2501#define BCE_EMAC_TXMAC_DEBUG0 0x00001658 2502#define BCE_EMAC_TXMAC_DEBUG1 0x0000165c 2503#define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE (0xfL<<0) 2504#define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_IDLE (0x0L<<0) 2505#define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_START0 (0x1L<<0) 2506#define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA0 (0x4L<<0) 2507#define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA1 (0x5L<<0) 2508#define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA2 (0x6L<<0) 2509#define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA3 (0x7L<<0) 2510#define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT0 (0x8L<<0) 2511#define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT1 (0x9L<<0) 2512#define BCE_EMAC_TXMAC_DEBUG1_CRS_ENABLE (1L<<4) 2513#define BCE_EMAC_TXMAC_DEBUG1_BAD_CRC (1L<<5) 2514#define BCE_EMAC_TXMAC_DEBUG1_SE_COUNTER (0xfL<<6) 2515#define BCE_EMAC_TXMAC_DEBUG1_SEND_PAUSE (1L<<10) 2516#define BCE_EMAC_TXMAC_DEBUG1_LATE_COLLISION (1L<<11) 2517#define BCE_EMAC_TXMAC_DEBUG1_MAX_DEFER (1L<<12) 2518#define BCE_EMAC_TXMAC_DEBUG1_DEFERRED (1L<<13) 2519#define BCE_EMAC_TXMAC_DEBUG1_ONE_BYTE (1L<<14) 2520#define BCE_EMAC_TXMAC_DEBUG1_IPG_TIME (0xfL<<15) 2521#define BCE_EMAC_TXMAC_DEBUG1_SLOT_TIME (0xffL<<19) 2522 2523#define BCE_EMAC_TXMAC_DEBUG2 0x00001660 2524#define BCE_EMAC_TXMAC_DEBUG2_BACK_OFF (0x3ffL<<0) 2525#define BCE_EMAC_TXMAC_DEBUG2_BYTE_COUNT (0xffffL<<10) 2526#define BCE_EMAC_TXMAC_DEBUG2_COL_COUNT (0x1fL<<26) 2527#define BCE_EMAC_TXMAC_DEBUG2_COL_BIT (1L<<31) 2528 2529#define BCE_EMAC_TXMAC_DEBUG3 0x00001664 2530#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE (0xfL<<0) 2531#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_IDLE (0x0L<<0) 2532#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_PRE1 (0x1L<<0) 2533#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_PRE2 (0x2L<<0) 2534#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_SFD (0x3L<<0) 2535#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_DATA (0x4L<<0) 2536#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_CRC1 (0x5L<<0) 2537#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_CRC2 (0x6L<<0) 2538#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_EXT (0x7L<<0) 2539#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_STATB (0x8L<<0) 2540#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_STATG (0x9L<<0) 2541#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_JAM (0xaL<<0) 2542#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_EJAM (0xbL<<0) 2543#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_BJAM (0xcL<<0) 2544#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_SWAIT (0xdL<<0) 2545#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_BACKOFF (0xeL<<0) 2546#define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE (0x7L<<4) 2547#define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_IDLE (0x0L<<4) 2548#define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_WAIT (0x1L<<4) 2549#define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_UNI (0x2L<<4) 2550#define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_MC (0x3L<<4) 2551#define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_BC2 (0x4L<<4) 2552#define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_BC3 (0x5L<<4) 2553#define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_BC (0x6L<<4) 2554#define BCE_EMAC_TXMAC_DEBUG3_CRS_DONE (1L<<7) 2555#define BCE_EMAC_TXMAC_DEBUG3_XOFF (1L<<8) 2556#define BCE_EMAC_TXMAC_DEBUG3_SE_COUNTER (0xfL<<9) 2557#define BCE_EMAC_TXMAC_DEBUG3_QUANTA_COUNTER (0x1fL<<13) 2558 2559#define BCE_EMAC_TXMAC_DEBUG4 0x00001668 2560#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_COUNTER (0xffffL<<0) 2561#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE (0xfL<<16) 2562#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_IDLE (0x0L<<16) 2563#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA1 (0x2L<<16) 2564#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA2 (0x3L<<16) 2565#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA3 (0x6L<<16) 2566#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC1 (0x7L<<16) 2567#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC2 (0x5L<<16) 2568#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC3 (0x4L<<16) 2569#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TYPE (0xcL<<16) 2570#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CMD (0xeL<<16) 2571#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TIME (0xaL<<16) 2572#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC1 (0x8L<<16) 2573#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC2 (0x9L<<16) 2574#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_WAIT (0xdL<<16) 2575#define BCE_EMAC_TXMAC_DEBUG4_STATS0_VALID (1L<<20) 2576#define BCE_EMAC_TXMAC_DEBUG4_APPEND_CRC (1L<<21) 2577#define BCE_EMAC_TXMAC_DEBUG4_SLOT_FILLED (1L<<22) 2578#define BCE_EMAC_TXMAC_DEBUG4_MAX_DEFER (1L<<23) 2579#define BCE_EMAC_TXMAC_DEBUG4_SEND_EXTEND (1L<<24) 2580#define BCE_EMAC_TXMAC_DEBUG4_SEND_PADDING (1L<<25) 2581#define BCE_EMAC_TXMAC_DEBUG4_EOF_LOC (1L<<26) 2582#define BCE_EMAC_TXMAC_DEBUG4_COLLIDING (1L<<27) 2583#define BCE_EMAC_TXMAC_DEBUG4_COL_IN (1L<<28) 2584#define BCE_EMAC_TXMAC_DEBUG4_BURSTING (1L<<29) 2585#define BCE_EMAC_TXMAC_DEBUG4_ADVANCE (1L<<30) 2586#define BCE_EMAC_TXMAC_DEBUG4_GO (1L<<31) 2587 2588#define BCE_EMAC_TX_STAT_AC0 0x00001680 2589#define BCE_EMAC_TX_STAT_AC1 0x00001684 2590#define BCE_EMAC_TX_STAT_AC2 0x00001688 2591#define BCE_EMAC_TX_STAT_AC3 0x0000168c 2592#define BCE_EMAC_TX_STAT_AC4 0x00001690 2593#define BCE_EMAC_TX_STAT_AC5 0x00001694 2594#define BCE_EMAC_TX_STAT_AC6 0x00001698 2595#define BCE_EMAC_TX_STAT_AC7 0x0000169c 2596#define BCE_EMAC_TX_STAT_AC8 0x000016a0 2597#define BCE_EMAC_TX_STAT_AC9 0x000016a4 2598#define BCE_EMAC_TX_STAT_AC10 0x000016a8 2599#define BCE_EMAC_TX_STAT_AC11 0x000016ac 2600#define BCE_EMAC_TX_STAT_AC12 0x000016b0 2601#define BCE_EMAC_TX_STAT_AC13 0x000016b4 2602#define BCE_EMAC_TX_STAT_AC14 0x000016b8 2603#define BCE_EMAC_TX_STAT_AC15 0x000016bc 2604#define BCE_EMAC_TX_STAT_AC16 0x000016c0 2605#define BCE_EMAC_TX_STAT_AC17 0x000016c4 2606#define BCE_EMAC_TX_STAT_AC18 0x000016c8 2607#define BCE_EMAC_TX_STAT_AC19 0x000016cc 2608#define BCE_EMAC_TX_STAT_AC20 0x000016d0 2609#define BCE_EMAC_TX_STAT_AC21 0x000016d4 2610#define BCE_EMAC_TXMAC_SUC_DBG_OVERRUNVEC 0x000016d8 2611 2612 2613/* 2614 * rpm_reg definition 2615 * offset: 0x1800 2616 */ 2617#define BCE_RPM_COMMAND 0x00001800 2618#define BCE_RPM_COMMAND_ENABLED (1L<<0) 2619#define BCE_RPM_COMMAND_OVERRUN_ABORT (1L<<4) 2620 2621#define BCE_RPM_STATUS 0x00001804 2622#define BCE_RPM_STATUS_MBUF_WAIT (1L<<0) 2623#define BCE_RPM_STATUS_FREE_WAIT (1L<<1) 2624 2625#define BCE_RPM_CONFIG 0x00001808 2626#define BCE_RPM_CONFIG_NO_PSD_HDR_CKSUM (1L<<0) 2627#define BCE_RPM_CONFIG_ACPI_ENA (1L<<1) 2628#define BCE_RPM_CONFIG_ACPI_KEEP (1L<<2) 2629#define BCE_RPM_CONFIG_MP_KEEP (1L<<3) 2630#define BCE_RPM_CONFIG_SORT_VECT_VAL (0xfL<<4) 2631#define BCE_RPM_CONFIG_IGNORE_VLAN (1L<<31) 2632 2633#define BCE_RPM_VLAN_MATCH0 0x00001810 2634#define BCE_RPM_VLAN_MATCH0_RPM_VLAN_MTCH0_VALUE (0xfffL<<0) 2635 2636#define BCE_RPM_VLAN_MATCH1 0x00001814 2637#define BCE_RPM_VLAN_MATCH1_RPM_VLAN_MTCH1_VALUE (0xfffL<<0) 2638 2639#define BCE_RPM_VLAN_MATCH2 0x00001818 2640#define BCE_RPM_VLAN_MATCH2_RPM_VLAN_MTCH2_VALUE (0xfffL<<0) 2641 2642#define BCE_RPM_VLAN_MATCH3 0x0000181c 2643#define BCE_RPM_VLAN_MATCH3_RPM_VLAN_MTCH3_VALUE (0xfffL<<0) 2644 2645#define BCE_RPM_SORT_USER0 0x00001820 2646#define BCE_RPM_SORT_USER0_PM_EN (0xffffL<<0) 2647#define BCE_RPM_SORT_USER0_BC_EN (1L<<16) 2648#define BCE_RPM_SORT_USER0_MC_EN (1L<<17) 2649#define BCE_RPM_SORT_USER0_MC_HSH_EN (1L<<18) 2650#define BCE_RPM_SORT_USER0_PROM_EN (1L<<19) 2651#define BCE_RPM_SORT_USER0_VLAN_EN (0xfL<<20) 2652#define BCE_RPM_SORT_USER0_PROM_VLAN (1L<<24) 2653#define BCE_RPM_SORT_USER0_ENA (1L<<31) 2654 2655#define BCE_RPM_SORT_USER1 0x00001824 2656#define BCE_RPM_SORT_USER1_PM_EN (0xffffL<<0) 2657#define BCE_RPM_SORT_USER1_BC_EN (1L<<16) 2658#define BCE_RPM_SORT_USER1_MC_EN (1L<<17) 2659#define BCE_RPM_SORT_USER1_MC_HSH_EN (1L<<18) 2660#define BCE_RPM_SORT_USER1_PROM_EN (1L<<19) 2661#define BCE_RPM_SORT_USER1_VLAN_EN (0xfL<<20) 2662#define BCE_RPM_SORT_USER1_PROM_VLAN (1L<<24) 2663#define BCE_RPM_SORT_USER1_ENA (1L<<31) 2664 2665#define BCE_RPM_SORT_USER2 0x00001828 2666#define BCE_RPM_SORT_USER2_PM_EN (0xffffL<<0) 2667#define BCE_RPM_SORT_USER2_BC_EN (1L<<16) 2668#define BCE_RPM_SORT_USER2_MC_EN (1L<<17) 2669#define BCE_RPM_SORT_USER2_MC_HSH_EN (1L<<18) 2670#define BCE_RPM_SORT_USER2_PROM_EN (1L<<19) 2671#define BCE_RPM_SORT_USER2_VLAN_EN (0xfL<<20) 2672#define BCE_RPM_SORT_USER2_PROM_VLAN (1L<<24) 2673#define BCE_RPM_SORT_USER2_ENA (1L<<31) 2674 2675#define BCE_RPM_SORT_USER3 0x0000182c 2676#define BCE_RPM_SORT_USER3_PM_EN (0xffffL<<0) 2677#define BCE_RPM_SORT_USER3_BC_EN (1L<<16) 2678#define BCE_RPM_SORT_USER3_MC_EN (1L<<17) 2679#define BCE_RPM_SORT_USER3_MC_HSH_EN (1L<<18) 2680#define BCE_RPM_SORT_USER3_PROM_EN (1L<<19) 2681#define BCE_RPM_SORT_USER3_VLAN_EN (0xfL<<20) 2682#define BCE_RPM_SORT_USER3_PROM_VLAN (1L<<24) 2683#define BCE_RPM_SORT_USER3_ENA (1L<<31) 2684 2685#define BCE_RPM_STAT_L2_FILTER_DISCARDS 0x00001840 2686#define BCE_RPM_STAT_RULE_CHECKER_DISCARDS 0x00001844 2687#define BCE_RPM_STAT_IFINFTQDISCARDS 0x00001848 2688#define BCE_RPM_STAT_IFINMBUFDISCARD 0x0000184c 2689#define BCE_RPM_STAT_RULE_CHECKER_P4_HIT 0x00001850 2690#define BCE_RPM_STAT_AC0 0x00001880 2691#define BCE_RPM_STAT_AC1 0x00001884 2692#define BCE_RPM_STAT_AC2 0x00001888 2693#define BCE_RPM_STAT_AC3 0x0000188c 2694#define BCE_RPM_STAT_AC4 0x00001890 2695#define BCE_RPM_RC_CNTL_0 0x00001900 2696#define BCE_RPM_RC_CNTL_0_OFFSET (0xffL<<0) 2697#define BCE_RPM_RC_CNTL_0_CLASS (0x7L<<8) 2698#define BCE_RPM_RC_CNTL_0_PRIORITY (1L<<11) 2699#define BCE_RPM_RC_CNTL_0_P4 (1L<<12) 2700#define BCE_RPM_RC_CNTL_0_HDR_TYPE (0x7L<<13) 2701#define BCE_RPM_RC_CNTL_0_HDR_TYPE_START (0L<<13) 2702#define BCE_RPM_RC_CNTL_0_HDR_TYPE_IP (1L<<13) 2703#define BCE_RPM_RC_CNTL_0_HDR_TYPE_TCP (2L<<13) 2704#define BCE_RPM_RC_CNTL_0_HDR_TYPE_UDP (3L<<13) 2705#define BCE_RPM_RC_CNTL_0_HDR_TYPE_DATA (4L<<13) 2706#define BCE_RPM_RC_CNTL_0_COMP (0x3L<<16) 2707#define BCE_RPM_RC_CNTL_0_COMP_EQUAL (0L<<16) 2708#define BCE_RPM_RC_CNTL_0_COMP_NEQUAL (1L<<16) 2709#define BCE_RPM_RC_CNTL_0_COMP_GREATER (2L<<16) 2710#define BCE_RPM_RC_CNTL_0_COMP_LESS (3L<<16) 2711#define BCE_RPM_RC_CNTL_0_SBIT (1L<<19) 2712#define BCE_RPM_RC_CNTL_0_CMDSEL (0xfL<<20) 2713#define BCE_RPM_RC_CNTL_0_MAP (1L<<24) 2714#define BCE_RPM_RC_CNTL_0_DISCARD (1L<<25) 2715#define BCE_RPM_RC_CNTL_0_MASK (1L<<26) 2716#define BCE_RPM_RC_CNTL_0_P1 (1L<<27) 2717#define BCE_RPM_RC_CNTL_0_P2 (1L<<28) 2718#define BCE_RPM_RC_CNTL_0_P3 (1L<<29) 2719#define BCE_RPM_RC_CNTL_0_NBIT (1L<<30) 2720 2721#define BCE_RPM_RC_VALUE_MASK_0 0x00001904 2722#define BCE_RPM_RC_VALUE_MASK_0_VALUE (0xffffL<<0) 2723#define BCE_RPM_RC_VALUE_MASK_0_MASK (0xffffL<<16) 2724 2725#define BCE_RPM_RC_CNTL_1 0x00001908 2726#define BCE_RPM_RC_CNTL_1_A (0x3ffffL<<0) 2727#define BCE_RPM_RC_CNTL_1_B (0xfffL<<19) 2728 2729#define BCE_RPM_RC_VALUE_MASK_1 0x0000190c 2730#define BCE_RPM_RC_CNTL_2 0x00001910 2731#define BCE_RPM_RC_CNTL_2_A (0x3ffffL<<0) 2732#define BCE_RPM_RC_CNTL_2_B (0xfffL<<19) 2733 2734#define BCE_RPM_RC_VALUE_MASK_2 0x00001914 2735#define BCE_RPM_RC_CNTL_3 0x00001918 2736#define BCE_RPM_RC_CNTL_3_A (0x3ffffL<<0) 2737#define BCE_RPM_RC_CNTL_3_B (0xfffL<<19) 2738 2739#define BCE_RPM_RC_VALUE_MASK_3 0x0000191c 2740#define BCE_RPM_RC_CNTL_4 0x00001920 2741#define BCE_RPM_RC_CNTL_4_A (0x3ffffL<<0) 2742#define BCE_RPM_RC_CNTL_4_B (0xfffL<<19) 2743 2744#define BCE_RPM_RC_VALUE_MASK_4 0x00001924 2745#define BCE_RPM_RC_CNTL_5 0x00001928 2746#define BCE_RPM_RC_CNTL_5_A (0x3ffffL<<0) 2747#define BCE_RPM_RC_CNTL_5_B (0xfffL<<19) 2748 2749#define BCE_RPM_RC_VALUE_MASK_5 0x0000192c 2750#define BCE_RPM_RC_CNTL_6 0x00001930 2751#define BCE_RPM_RC_CNTL_6_A (0x3ffffL<<0) 2752#define BCE_RPM_RC_CNTL_6_B (0xfffL<<19) 2753 2754#define BCE_RPM_RC_VALUE_MASK_6 0x00001934 2755#define BCE_RPM_RC_CNTL_7 0x00001938 2756#define BCE_RPM_RC_CNTL_7_A (0x3ffffL<<0) 2757#define BCE_RPM_RC_CNTL_7_B (0xfffL<<19) 2758 2759#define BCE_RPM_RC_VALUE_MASK_7 0x0000193c 2760#define BCE_RPM_RC_CNTL_8 0x00001940 2761#define BCE_RPM_RC_CNTL_8_A (0x3ffffL<<0) 2762#define BCE_RPM_RC_CNTL_8_B (0xfffL<<19) 2763 2764#define BCE_RPM_RC_VALUE_MASK_8 0x00001944 2765#define BCE_RPM_RC_CNTL_9 0x00001948 2766#define BCE_RPM_RC_CNTL_9_A (0x3ffffL<<0) 2767#define BCE_RPM_RC_CNTL_9_B (0xfffL<<19) 2768 2769#define BCE_RPM_RC_VALUE_MASK_9 0x0000194c 2770#define BCE_RPM_RC_CNTL_10 0x00001950 2771#define BCE_RPM_RC_CNTL_10_A (0x3ffffL<<0) 2772#define BCE_RPM_RC_CNTL_10_B (0xfffL<<19) 2773 2774#define BCE_RPM_RC_VALUE_MASK_10 0x00001954 2775#define BCE_RPM_RC_CNTL_11 0x00001958 2776#define BCE_RPM_RC_CNTL_11_A (0x3ffffL<<0) 2777#define BCE_RPM_RC_CNTL_11_B (0xfffL<<19) 2778 2779#define BCE_RPM_RC_VALUE_MASK_11 0x0000195c 2780#define BCE_RPM_RC_CNTL_12 0x00001960 2781#define BCE_RPM_RC_CNTL_12_A (0x3ffffL<<0) 2782#define BCE_RPM_RC_CNTL_12_B (0xfffL<<19) 2783 2784#define BCE_RPM_RC_VALUE_MASK_12 0x00001964 2785#define BCE_RPM_RC_CNTL_13 0x00001968 2786#define BCE_RPM_RC_CNTL_13_A (0x3ffffL<<0) 2787#define BCE_RPM_RC_CNTL_13_B (0xfffL<<19) 2788 2789#define BCE_RPM_RC_VALUE_MASK_13 0x0000196c 2790#define BCE_RPM_RC_CNTL_14 0x00001970 2791#define BCE_RPM_RC_CNTL_14_A (0x3ffffL<<0) 2792#define BCE_RPM_RC_CNTL_14_B (0xfffL<<19) 2793 2794#define BCE_RPM_RC_VALUE_MASK_14 0x00001974 2795#define BCE_RPM_RC_CNTL_15 0x00001978 2796#define BCE_RPM_RC_CNTL_15_A (0x3ffffL<<0) 2797#define BCE_RPM_RC_CNTL_15_B (0xfffL<<19) 2798 2799#define BCE_RPM_RC_VALUE_MASK_15 0x0000197c 2800#define BCE_RPM_RC_CONFIG 0x00001980 2801#define BCE_RPM_RC_CONFIG_RULE_ENABLE (0xffffL<<0) 2802#define BCE_RPM_RC_CONFIG_DEF_CLASS (0x7L<<24) 2803 2804#define BCE_RPM_DEBUG0 0x00001984 2805#define BCE_RPM_DEBUG0_FM_BCNT (0xffffL<<0) 2806#define BCE_RPM_DEBUG0_T_DATA_OFST_VLD (1L<<16) 2807#define BCE_RPM_DEBUG0_T_UDP_OFST_VLD (1L<<17) 2808#define BCE_RPM_DEBUG0_T_TCP_OFST_VLD (1L<<18) 2809#define BCE_RPM_DEBUG0_T_IP_OFST_VLD (1L<<19) 2810#define BCE_RPM_DEBUG0_IP_MORE_FRGMT (1L<<20) 2811#define BCE_RPM_DEBUG0_T_IP_NO_TCP_UDP_HDR (1L<<21) 2812#define BCE_RPM_DEBUG0_LLC_SNAP (1L<<22) 2813#define BCE_RPM_DEBUG0_FM_STARTED (1L<<23) 2814#define BCE_RPM_DEBUG0_DONE (1L<<24) 2815#define BCE_RPM_DEBUG0_WAIT_4_DONE (1L<<25) 2816#define BCE_RPM_DEBUG0_USE_TPBUF_CKSUM (1L<<26) 2817#define BCE_RPM_DEBUG0_RX_NO_PSD_HDR_CKSUM (1L<<27) 2818#define BCE_RPM_DEBUG0_IGNORE_VLAN (1L<<28) 2819#define BCE_RPM_DEBUG0_RP_ENA_ACTIVE (1L<<31) 2820 2821#define BCE_RPM_DEBUG1 0x00001988 2822#define BCE_RPM_DEBUG1_FSM_CUR_ST (0xffffL<<0) 2823#define BCE_RPM_DEBUG1_FSM_CUR_ST_IDLE (0L<<0) 2824#define BCE_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_ALL (1L<<0) 2825#define BCE_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IPLLC (2L<<0) 2826#define BCE_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_IP (4L<<0) 2827#define BCE_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IP (8L<<0) 2828#define BCE_RPM_DEBUG1_FSM_CUR_ST_IP_START (16L<<0) 2829#define BCE_RPM_DEBUG1_FSM_CUR_ST_IP (32L<<0) 2830#define BCE_RPM_DEBUG1_FSM_CUR_ST_TCP (64L<<0) 2831#define BCE_RPM_DEBUG1_FSM_CUR_ST_UDP (128L<<0) 2832#define BCE_RPM_DEBUG1_FSM_CUR_ST_AH (256L<<0) 2833#define BCE_RPM_DEBUG1_FSM_CUR_ST_ESP (512L<<0) 2834#define BCE_RPM_DEBUG1_FSM_CUR_ST_ESP_PAYLOAD (1024L<<0) 2835#define BCE_RPM_DEBUG1_FSM_CUR_ST_DATA (2048L<<0) 2836#define BCE_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRY (0x2000L<<0) 2837#define BCE_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRYOUT (0x4000L<<0) 2838#define BCE_RPM_DEBUG1_FSM_CUR_ST_LATCH_RESULT (0x8000L<<0) 2839#define BCE_RPM_DEBUG1_HDR_BCNT (0x7ffL<<16) 2840#define BCE_RPM_DEBUG1_UNKNOWN_ETYPE_D (1L<<28) 2841#define BCE_RPM_DEBUG1_VLAN_REMOVED_D2 (1L<<29) 2842#define BCE_RPM_DEBUG1_VLAN_REMOVED_D1 (1L<<30) 2843#define BCE_RPM_DEBUG1_EOF_0XTRA_WD (1L<<31) 2844 2845#define BCE_RPM_DEBUG2 0x0000198c 2846#define BCE_RPM_DEBUG2_CMD_HIT_VEC (0xffffL<<0) 2847#define BCE_RPM_DEBUG2_IP_BCNT (0xffL<<16) 2848#define BCE_RPM_DEBUG2_THIS_CMD_M4 (1L<<24) 2849#define BCE_RPM_DEBUG2_THIS_CMD_M3 (1L<<25) 2850#define BCE_RPM_DEBUG2_THIS_CMD_M2 (1L<<26) 2851#define BCE_RPM_DEBUG2_THIS_CMD_M1 (1L<<27) 2852#define BCE_RPM_DEBUG2_IPIPE_EMPTY (1L<<28) 2853#define BCE_RPM_DEBUG2_FM_DISCARD (1L<<29) 2854#define BCE_RPM_DEBUG2_LAST_RULE_IN_FM_D2 (1L<<30) 2855#define BCE_RPM_DEBUG2_LAST_RULE_IN_FM_D1 (1L<<31) 2856 2857#define BCE_RPM_DEBUG3 0x00001990 2858#define BCE_RPM_DEBUG3_AVAIL_MBUF_PTR (0x1ffL<<0) 2859#define BCE_RPM_DEBUG3_RDE_RLUPQ_WR_REQ_INT (1L<<9) 2860#define BCE_RPM_DEBUG3_RDE_RBUF_WR_LAST_INT (1L<<10) 2861#define BCE_RPM_DEBUG3_RDE_RBUF_WR_REQ_INT (1L<<11) 2862#define BCE_RPM_DEBUG3_RDE_RBUF_FREE_REQ (1L<<12) 2863#define BCE_RPM_DEBUG3_RDE_RBUF_ALLOC_REQ (1L<<13) 2864#define BCE_RPM_DEBUG3_DFSM_MBUF_NOTAVAIL (1L<<14) 2865#define BCE_RPM_DEBUG3_RBUF_RDE_SOF_DROP (1L<<15) 2866#define BCE_RPM_DEBUG3_DFIFO_VLD_ENTRY_CT (0xfL<<16) 2867#define BCE_RPM_DEBUG3_RDE_SRC_FIFO_ALMFULL (1L<<21) 2868#define BCE_RPM_DEBUG3_DROP_NXT_VLD (1L<<22) 2869#define BCE_RPM_DEBUG3_DROP_NXT (1L<<23) 2870#define BCE_RPM_DEBUG3_FTQ_FSM (0x3L<<24) 2871#define BCE_RPM_DEBUG3_FTQ_FSM_IDLE (0x0L<<24) 2872#define BCE_RPM_DEBUG3_FTQ_FSM_WAIT_ACK (0x1L<<24) 2873#define BCE_RPM_DEBUG3_FTQ_FSM_WAIT_FREE (0x2L<<24) 2874#define BCE_RPM_DEBUG3_MBWRITE_FSM (0x3L<<26) 2875#define BCE_RPM_DEBUG3_MBWRITE_FSM_WAIT_SOF (0x0L<<26) 2876#define BCE_RPM_DEBUG3_MBWRITE_FSM_GET_MBUF (0x1L<<26) 2877#define BCE_RPM_DEBUG3_MBWRITE_FSM_DMA_DATA (0x2L<<26) 2878#define BCE_RPM_DEBUG3_MBWRITE_FSM_WAIT_DATA (0x3L<<26) 2879#define BCE_RPM_DEBUG3_MBWRITE_FSM_WAIT_EOF (0x4L<<26) 2880#define BCE_RPM_DEBUG3_MBWRITE_FSM_WAIT_MF_ACK (0x5L<<26) 2881#define BCE_RPM_DEBUG3_MBWRITE_FSM_WAIT_DROP_NXT_VLD (0x6L<<26) 2882#define BCE_RPM_DEBUG3_MBWRITE_FSM_DONE (0x7L<<26) 2883#define BCE_RPM_DEBUG3_MBFREE_FSM (1L<<29) 2884#define BCE_RPM_DEBUG3_MBFREE_FSM_IDLE (0L<<29) 2885#define BCE_RPM_DEBUG3_MBFREE_FSM_WAIT_ACK (1L<<29) 2886#define BCE_RPM_DEBUG3_MBALLOC_FSM (1L<<30) 2887#define BCE_RPM_DEBUG3_MBALLOC_FSM_ET_MBUF (0x0L<<30) 2888#define BCE_RPM_DEBUG3_MBALLOC_FSM_IVE_MBUF (0x1L<<30) 2889#define BCE_RPM_DEBUG3_CCODE_EOF_ERROR (1L<<31) 2890 2891#define BCE_RPM_DEBUG4 0x00001994 2892#define BCE_RPM_DEBUG4_DFSM_MBUF_CLUSTER (0x1ffffffL<<0) 2893#define BCE_RPM_DEBUG4_DFIFO_CUR_CCODE (0x7L<<25) 2894#define BCE_RPM_DEBUG4_MBWRITE_FSM (0x7L<<28) 2895#define BCE_RPM_DEBUG4_DFIFO_EMPTY (1L<<31) 2896 2897#define BCE_RPM_DEBUG5 0x00001998 2898#define BCE_RPM_DEBUG5_RDROP_WPTR (0x1fL<<0) 2899#define BCE_RPM_DEBUG5_RDROP_ACPI_RPTR (0x1fL<<5) 2900#define BCE_RPM_DEBUG5_RDROP_MC_RPTR (0x1fL<<10) 2901#define BCE_RPM_DEBUG5_RDROP_RC_RPTR (0x1fL<<15) 2902#define BCE_RPM_DEBUG5_RDROP_ACPI_EMPTY (1L<<20) 2903#define BCE_RPM_DEBUG5_RDROP_MC_EMPTY (1L<<21) 2904#define BCE_RPM_DEBUG5_RDROP_AEOF_VEC_AT_RDROP_MC_RPTR (1L<<22) 2905#define BCE_RPM_DEBUG5_HOLDREG_WOL_DROP_INT (1L<<23) 2906#define BCE_RPM_DEBUG5_HOLDREG_DISCARD (1L<<24) 2907#define BCE_RPM_DEBUG5_HOLDREG_MBUF_NOTAVAIL (1L<<25) 2908#define BCE_RPM_DEBUG5_HOLDREG_MC_EMPTY (1L<<26) 2909#define BCE_RPM_DEBUG5_HOLDREG_RC_EMPTY (1L<<27) 2910#define BCE_RPM_DEBUG5_HOLDREG_FC_EMPTY (1L<<28) 2911#define BCE_RPM_DEBUG5_HOLDREG_ACPI_EMPTY (1L<<29) 2912#define BCE_RPM_DEBUG5_HOLDREG_FULL_T (1L<<30) 2913#define BCE_RPM_DEBUG5_HOLDREG_RD (1L<<31) 2914 2915#define BCE_RPM_DEBUG6 0x0000199c 2916#define BCE_RPM_DEBUG6_ACPI_VEC (0xffffL<<0) 2917#define BCE_RPM_DEBUG6_VEC (0xffffL<<16) 2918 2919#define BCE_RPM_DEBUG7 0x000019a0 2920#define BCE_RPM_DEBUG7_RPM_DBG7_LAST_CRC (0xffffffffL<<0) 2921 2922#define BCE_RPM_DEBUG8 0x000019a4 2923#define BCE_RPM_DEBUG8_PS_ACPI_FSM (0xfL<<0) 2924#define BCE_RPM_DEBUG8_PS_ACPI_FSM_IDLE (0L<<0) 2925#define BCE_RPM_DEBUG8_PS_ACPI_FSM_SOF_W1_ADDR (1L<<0) 2926#define BCE_RPM_DEBUG8_PS_ACPI_FSM_SOF_W2_ADDR (2L<<0) 2927#define BCE_RPM_DEBUG8_PS_ACPI_FSM_SOF_W3_ADDR (3L<<0) 2928#define BCE_RPM_DEBUG8_PS_ACPI_FSM_SOF_WAIT_THBUF (4L<<0) 2929#define BCE_RPM_DEBUG8_PS_ACPI_FSM_W3_DATA (5L<<0) 2930#define BCE_RPM_DEBUG8_PS_ACPI_FSM_W0_ADDR (6L<<0) 2931#define BCE_RPM_DEBUG8_PS_ACPI_FSM_W1_ADDR (7L<<0) 2932#define BCE_RPM_DEBUG8_PS_ACPI_FSM_W2_ADDR (8L<<0) 2933#define BCE_RPM_DEBUG8_PS_ACPI_FSM_W3_ADDR (9L<<0) 2934#define BCE_RPM_DEBUG8_PS_ACPI_FSM_WAIT_THBUF (10L<<0) 2935#define BCE_RPM_DEBUG8_COMPARE_AT_W0 (1L<<4) 2936#define BCE_RPM_DEBUG8_COMPARE_AT_W3_DATA (1L<<5) 2937#define BCE_RPM_DEBUG8_COMPARE_AT_SOF_WAIT (1L<<6) 2938#define BCE_RPM_DEBUG8_COMPARE_AT_SOF_W3 (1L<<7) 2939#define BCE_RPM_DEBUG8_COMPARE_AT_SOF_W2 (1L<<8) 2940#define BCE_RPM_DEBUG8_EOF_W_LTEQ6_VLDBYTES (1L<<9) 2941#define BCE_RPM_DEBUG8_EOF_W_LTEQ4_VLDBYTES (1L<<10) 2942#define BCE_RPM_DEBUG8_NXT_EOF_W_12_VLDBYTES (1L<<11) 2943#define BCE_RPM_DEBUG8_EOF_DET (1L<<12) 2944#define BCE_RPM_DEBUG8_SOF_DET (1L<<13) 2945#define BCE_RPM_DEBUG8_WAIT_4_SOF (1L<<14) 2946#define BCE_RPM_DEBUG8_ALL_DONE (1L<<15) 2947#define BCE_RPM_DEBUG8_THBUF_ADDR (0x7fL<<16) 2948#define BCE_RPM_DEBUG8_BYTE_CTR (0xffL<<24) 2949 2950#define BCE_RPM_DEBUG9 0x000019a8 2951#define BCE_RPM_DEBUG9_OUTFIFO_COUNT (0x7L<<0) 2952#define BCE_RPM_DEBUG9_RDE_ACPI_RDY (1L<<3) 2953#define BCE_RPM_DEBUG9_VLD_RD_ENTRY_CT (0x7L<<4) 2954#define BCE_RPM_DEBUG9_OUTFIFO_OVERRUN_OCCURRED (1L<<28) 2955#define BCE_RPM_DEBUG9_INFIFO_OVERRUN_OCCURRED (1L<<29) 2956#define BCE_RPM_DEBUG9_ACPI_MATCH_INT (1L<<30) 2957#define BCE_RPM_DEBUG9_ACPI_ENABLE_SYN (1L<<31) 2958 2959#define BCE_RPM_ACPI_DBG_BUF_W00 0x000019c0 2960#define BCE_RPM_ACPI_DBG_BUF_W01 0x000019c4 2961#define BCE_RPM_ACPI_DBG_BUF_W02 0x000019c8 2962#define BCE_RPM_ACPI_DBG_BUF_W03 0x000019cc 2963#define BCE_RPM_ACPI_DBG_BUF_W10 0x000019d0 2964#define BCE_RPM_ACPI_DBG_BUF_W11 0x000019d4 2965#define BCE_RPM_ACPI_DBG_BUF_W12 0x000019d8 2966#define BCE_RPM_ACPI_DBG_BUF_W13 0x000019dc 2967#define BCE_RPM_ACPI_DBG_BUF_W20 0x000019e0 2968#define BCE_RPM_ACPI_DBG_BUF_W21 0x000019e4 2969#define BCE_RPM_ACPI_DBG_BUF_W22 0x000019e8 2970#define BCE_RPM_ACPI_DBG_BUF_W23 0x000019ec 2971#define BCE_RPM_ACPI_DBG_BUF_W30 0x000019f0 2972#define BCE_RPM_ACPI_DBG_BUF_W31 0x000019f4 2973#define BCE_RPM_ACPI_DBG_BUF_W32 0x000019f8 2974#define BCE_RPM_ACPI_DBG_BUF_W33 0x000019fc 2975 2976 2977/* 2978 * rbuf_reg definition 2979 * offset: 0x200000 2980 */ 2981#define BCE_RBUF_COMMAND 0x00200000 2982#define BCE_RBUF_COMMAND_ENABLED (1L<<0) 2983#define BCE_RBUF_COMMAND_FREE_INIT (1L<<1) 2984#define BCE_RBUF_COMMAND_RAM_INIT (1L<<2) 2985#define BCE_RBUF_COMMAND_OVER_FREE (1L<<4) 2986#define BCE_RBUF_COMMAND_ALLOC_REQ (1L<<5) 2987 2988#define BCE_RBUF_STATUS1 0x00200004 2989#define BCE_RBUF_STATUS1_FREE_COUNT (0x3ffL<<0) 2990 2991#define BCE_RBUF_STATUS2 0x00200008 2992#define BCE_RBUF_STATUS2_FREE_TAIL (0x3ffL<<0) 2993#define BCE_RBUF_STATUS2_FREE_HEAD (0x3ffL<<16) 2994 2995#define BCE_RBUF_CONFIG 0x0020000c 2996#define BCE_RBUF_CONFIG_XOFF_TRIP (0x3ffL<<0) 2997#define BCE_RBUF_CONFIG_XON_TRIP (0x3ffL<<16) 2998 2999#define BCE_RBUF_FW_BUF_ALLOC 0x00200010 3000#define BCE_RBUF_FW_BUF_ALLOC_VALUE (0x1ffL<<7) 3001 3002#define BCE_RBUF_FW_BUF_FREE 0x00200014 3003#define BCE_RBUF_FW_BUF_FREE_COUNT (0x7fL<<0) 3004#define BCE_RBUF_FW_BUF_FREE_TAIL (0x1ffL<<7) 3005#define BCE_RBUF_FW_BUF_FREE_HEAD (0x1ffL<<16) 3006 3007#define BCE_RBUF_FW_BUF_SEL 0x00200018 3008#define BCE_RBUF_FW_BUF_SEL_COUNT (0x7fL<<0) 3009#define BCE_RBUF_FW_BUF_SEL_TAIL (0x1ffL<<7) 3010#define BCE_RBUF_FW_BUF_SEL_HEAD (0x1ffL<<16) 3011 3012#define BCE_RBUF_CONFIG2 0x0020001c 3013#define BCE_RBUF_CONFIG2_MAC_DROP_TRIP (0x3ffL<<0) 3014#define BCE_RBUF_CONFIG2_MAC_KEEP_TRIP (0x3ffL<<16) 3015 3016#define BCE_RBUF_CONFIG3 0x00200020 3017#define BCE_RBUF_CONFIG3_CU_DROP_TRIP (0x3ffL<<0) 3018#define BCE_RBUF_CONFIG3_CU_KEEP_TRIP (0x3ffL<<16) 3019 3020#define BCE_RBUF_PKT_DATA 0x00208000 3021#define BCE_RBUF_CLIST_DATA 0x00210000 3022#define BCE_RBUF_BUF_DATA 0x00220000 3023 3024 3025/* 3026 * rv2p_reg definition 3027 * offset: 0x2800 3028 */ 3029#define BCE_RV2P_COMMAND 0x00002800 3030#define BCE_RV2P_COMMAND_ENABLED (1L<<0) 3031#define BCE_RV2P_COMMAND_PROC1_INTRPT (1L<<1) 3032#define BCE_RV2P_COMMAND_PROC2_INTRPT (1L<<2) 3033#define BCE_RV2P_COMMAND_ABORT0 (1L<<4) 3034#define BCE_RV2P_COMMAND_ABORT1 (1L<<5) 3035#define BCE_RV2P_COMMAND_ABORT2 (1L<<6) 3036#define BCE_RV2P_COMMAND_ABORT3 (1L<<7) 3037#define BCE_RV2P_COMMAND_ABORT4 (1L<<8) 3038#define BCE_RV2P_COMMAND_ABORT5 (1L<<9) 3039#define BCE_RV2P_COMMAND_PROC1_RESET (1L<<16) 3040#define BCE_RV2P_COMMAND_PROC2_RESET (1L<<17) 3041#define BCE_RV2P_COMMAND_CTXIF_RESET (1L<<18) 3042 3043#define BCE_RV2P_STATUS 0x00002804 3044#define BCE_RV2P_STATUS_ALWAYS_0 (1L<<0) 3045#define BCE_RV2P_STATUS_RV2P_GEN_STAT0_CNT (1L<<8) 3046#define BCE_RV2P_STATUS_RV2P_GEN_STAT1_CNT (1L<<9) 3047#define BCE_RV2P_STATUS_RV2P_GEN_STAT2_CNT (1L<<10) 3048#define BCE_RV2P_STATUS_RV2P_GEN_STAT3_CNT (1L<<11) 3049#define BCE_RV2P_STATUS_RV2P_GEN_STAT4_CNT (1L<<12) 3050#define BCE_RV2P_STATUS_RV2P_GEN_STAT5_CNT (1L<<13) 3051 3052#define BCE_RV2P_CONFIG 0x00002808 3053#define BCE_RV2P_CONFIG_STALL_PROC1 (1L<<0) 3054#define BCE_RV2P_CONFIG_STALL_PROC2 (1L<<1) 3055#define BCE_RV2P_CONFIG_PROC1_STALL_ON_ABORT0 (1L<<8) 3056#define BCE_RV2P_CONFIG_PROC1_STALL_ON_ABORT1 (1L<<9) 3057#define BCE_RV2P_CONFIG_PROC1_STALL_ON_ABORT2 (1L<<10) 3058#define BCE_RV2P_CONFIG_PROC1_STALL_ON_ABORT3 (1L<<11) 3059#define BCE_RV2P_CONFIG_PROC1_STALL_ON_ABORT4 (1L<<12) 3060#define BCE_RV2P_CONFIG_PROC1_STALL_ON_ABORT5 (1L<<13) 3061#define BCE_RV2P_CONFIG_PROC2_STALL_ON_ABORT0 (1L<<16) 3062#define BCE_RV2P_CONFIG_PROC2_STALL_ON_ABORT1 (1L<<17) 3063#define BCE_RV2P_CONFIG_PROC2_STALL_ON_ABORT2 (1L<<18) 3064#define BCE_RV2P_CONFIG_PROC2_STALL_ON_ABORT3 (1L<<19) 3065#define BCE_RV2P_CONFIG_PROC2_STALL_ON_ABORT4 (1L<<20) 3066#define BCE_RV2P_CONFIG_PROC2_STALL_ON_ABORT5 (1L<<21) 3067#define BCE_RV2P_CONFIG_PAGE_SIZE (0xfL<<24) 3068#define BCE_RV2P_CONFIG_PAGE_SIZE_256 (0L<<24) 3069#define BCE_RV2P_CONFIG_PAGE_SIZE_512 (1L<<24) 3070#define BCE_RV2P_CONFIG_PAGE_SIZE_1K (2L<<24) 3071#define BCE_RV2P_CONFIG_PAGE_SIZE_2K (3L<<24) 3072#define BCE_RV2P_CONFIG_PAGE_SIZE_4K (4L<<24) 3073#define BCE_RV2P_CONFIG_PAGE_SIZE_8K (5L<<24) 3074#define BCE_RV2P_CONFIG_PAGE_SIZE_16K (6L<<24) 3075#define BCE_RV2P_CONFIG_PAGE_SIZE_32K (7L<<24) 3076#define BCE_RV2P_CONFIG_PAGE_SIZE_64K (8L<<24) 3077#define BCE_RV2P_CONFIG_PAGE_SIZE_128K (9L<<24) 3078#define BCE_RV2P_CONFIG_PAGE_SIZE_256K (10L<<24) 3079#define BCE_RV2P_CONFIG_PAGE_SIZE_512K (11L<<24) 3080#define BCE_RV2P_CONFIG_PAGE_SIZE_1M (12L<<24) 3081 3082#define BCE_RV2P_GEN_BFR_ADDR_0 0x00002810 3083#define BCE_RV2P_GEN_BFR_ADDR_0_VALUE (0xffffL<<16) 3084 3085#define BCE_RV2P_GEN_BFR_ADDR_1 0x00002814 3086#define BCE_RV2P_GEN_BFR_ADDR_1_VALUE (0xffffL<<16) 3087 3088#define BCE_RV2P_GEN_BFR_ADDR_2 0x00002818 3089#define BCE_RV2P_GEN_BFR_ADDR_2_VALUE (0xffffL<<16) 3090 3091#define BCE_RV2P_GEN_BFR_ADDR_3 0x0000281c 3092#define BCE_RV2P_GEN_BFR_ADDR_3_VALUE (0xffffL<<16) 3093 3094#define BCE_RV2P_INSTR_HIGH 0x00002830 3095#define BCE_RV2P_INSTR_HIGH_HIGH (0x1fL<<0) 3096 3097#define BCE_RV2P_INSTR_LOW 0x00002834 3098#define BCE_RV2P_PROC1_ADDR_CMD 0x00002838 3099#define BCE_RV2P_PROC1_ADDR_CMD_ADD (0x3ffL<<0) 3100#define BCE_RV2P_PROC1_ADDR_CMD_RDWR (1L<<31) 3101 3102#define BCE_RV2P_PROC2_ADDR_CMD 0x0000283c 3103#define BCE_RV2P_PROC2_ADDR_CMD_ADD (0x3ffL<<0) 3104#define BCE_RV2P_PROC2_ADDR_CMD_RDWR (1L<<31) 3105 3106#define BCE_RV2P_PROC1_GRC_DEBUG 0x00002840 3107#define BCE_RV2P_PROC2_GRC_DEBUG 0x00002844 3108#define BCE_RV2P_GRC_PROC_DEBUG 0x00002848 3109#define BCE_RV2P_DEBUG_VECT_PEEK 0x0000284c 3110#define BCE_RV2P_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) 3111#define BCE_RV2P_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) 3112#define BCE_RV2P_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) 3113#define BCE_RV2P_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) 3114#define BCE_RV2P_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) 3115#define BCE_RV2P_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) 3116 3117#define BCE_RV2P_PFTQ_DATA 0x00002b40 3118#define BCE_RV2P_PFTQ_CMD 0x00002b78 3119#define BCE_RV2P_PFTQ_CMD_OFFSET (0x3ffL<<0) 3120#define BCE_RV2P_PFTQ_CMD_WR_TOP (1L<<10) 3121#define BCE_RV2P_PFTQ_CMD_WR_TOP_0 (0L<<10) 3122#define BCE_RV2P_PFTQ_CMD_WR_TOP_1 (1L<<10) 3123#define BCE_RV2P_PFTQ_CMD_SFT_RESET (1L<<25) 3124#define BCE_RV2P_PFTQ_CMD_RD_DATA (1L<<26) 3125#define BCE_RV2P_PFTQ_CMD_ADD_INTERVEN (1L<<27) 3126#define BCE_RV2P_PFTQ_CMD_ADD_DATA (1L<<28) 3127#define BCE_RV2P_PFTQ_CMD_INTERVENE_CLR (1L<<29) 3128#define BCE_RV2P_PFTQ_CMD_POP (1L<<30) 3129#define BCE_RV2P_PFTQ_CMD_BUSY (1L<<31) 3130 3131#define BCE_RV2P_PFTQ_CTL 0x00002b7c 3132#define BCE_RV2P_PFTQ_CTL_INTERVENE (1L<<0) 3133#define BCE_RV2P_PFTQ_CTL_OVERFLOW (1L<<1) 3134#define BCE_RV2P_PFTQ_CTL_FORCE_INTERVENE (1L<<2) 3135#define BCE_RV2P_PFTQ_CTL_MAX_DEPTH (0x3ffL<<12) 3136#define BCE_RV2P_PFTQ_CTL_CUR_DEPTH (0x3ffL<<22) 3137 3138#define BCE_RV2P_TFTQ_DATA 0x00002b80 3139#define BCE_RV2P_TFTQ_CMD 0x00002bb8 3140#define BCE_RV2P_TFTQ_CMD_OFFSET (0x3ffL<<0) 3141#define BCE_RV2P_TFTQ_CMD_WR_TOP (1L<<10) 3142#define BCE_RV2P_TFTQ_CMD_WR_TOP_0 (0L<<10) 3143#define BCE_RV2P_TFTQ_CMD_WR_TOP_1 (1L<<10) 3144#define BCE_RV2P_TFTQ_CMD_SFT_RESET (1L<<25) 3145#define BCE_RV2P_TFTQ_CMD_RD_DATA (1L<<26) 3146#define BCE_RV2P_TFTQ_CMD_ADD_INTERVEN (1L<<27) 3147#define BCE_RV2P_TFTQ_CMD_ADD_DATA (1L<<28) 3148#define BCE_RV2P_TFTQ_CMD_INTERVENE_CLR (1L<<29) 3149#define BCE_RV2P_TFTQ_CMD_POP (1L<<30) 3150#define BCE_RV2P_TFTQ_CMD_BUSY (1L<<31) 3151 3152#define BCE_RV2P_TFTQ_CTL 0x00002bbc 3153#define BCE_RV2P_TFTQ_CTL_INTERVENE (1L<<0) 3154#define BCE_RV2P_TFTQ_CTL_OVERFLOW (1L<<1) 3155#define BCE_RV2P_TFTQ_CTL_FORCE_INTERVENE (1L<<2) 3156#define BCE_RV2P_TFTQ_CTL_MAX_DEPTH (0x3ffL<<12) 3157#define BCE_RV2P_TFTQ_CTL_CUR_DEPTH (0x3ffL<<22) 3158 3159#define BCE_RV2P_MFTQ_DATA 0x00002bc0 3160#define BCE_RV2P_MFTQ_CMD 0x00002bf8 3161#define BCE_RV2P_MFTQ_CMD_OFFSET (0x3ffL<<0) 3162#define BCE_RV2P_MFTQ_CMD_WR_TOP (1L<<10) 3163#define BCE_RV2P_MFTQ_CMD_WR_TOP_0 (0L<<10) 3164#define BCE_RV2P_MFTQ_CMD_WR_TOP_1 (1L<<10) 3165#define BCE_RV2P_MFTQ_CMD_SFT_RESET (1L<<25) 3166#define BCE_RV2P_MFTQ_CMD_RD_DATA (1L<<26) 3167#define BCE_RV2P_MFTQ_CMD_ADD_INTERVEN (1L<<27) 3168#define BCE_RV2P_MFTQ_CMD_ADD_DATA (1L<<28) 3169#define BCE_RV2P_MFTQ_CMD_INTERVENE_CLR (1L<<29) 3170#define BCE_RV2P_MFTQ_CMD_POP (1L<<30) 3171#define BCE_RV2P_MFTQ_CMD_BUSY (1L<<31) 3172 3173#define BCE_RV2P_MFTQ_CTL 0x00002bfc 3174#define BCE_RV2P_MFTQ_CTL_INTERVENE (1L<<0) 3175#define BCE_RV2P_MFTQ_CTL_OVERFLOW (1L<<1) 3176#define BCE_RV2P_MFTQ_CTL_FORCE_INTERVENE (1L<<2) 3177#define BCE_RV2P_MFTQ_CTL_MAX_DEPTH (0x3ffL<<12) 3178#define BCE_RV2P_MFTQ_CTL_CUR_DEPTH (0x3ffL<<22) 3179 3180 3181 3182/* 3183 * mq_reg definition 3184 * offset: 0x3c00 3185 */ 3186#define BCE_MQ_COMMAND 0x00003c00 3187#define BCE_MQ_COMMAND_ENABLED (1L<<0) 3188#define BCE_MQ_COMMAND_OVERFLOW (1L<<4) 3189#define BCE_MQ_COMMAND_WR_ERROR (1L<<5) 3190#define BCE_MQ_COMMAND_RD_ERROR (1L<<6) 3191 3192#define BCE_MQ_STATUS 0x00003c04 3193#define BCE_MQ_STATUS_CTX_ACCESS_STAT (1L<<16) 3194#define BCE_MQ_STATUS_CTX_ACCESS64_STAT (1L<<17) 3195#define BCE_MQ_STATUS_PCI_STALL_STAT (1L<<18) 3196 3197#define BCE_MQ_CONFIG 0x00003c08 3198#define BCE_MQ_CONFIG_TX_HIGH_PRI (1L<<0) 3199#define BCE_MQ_CONFIG_HALT_DIS (1L<<1) 3200#define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE (0x7L<<4) 3201#define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256 (0L<<4) 3202#define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_512 (1L<<4) 3203#define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_1K (2L<<4) 3204#define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_2K (3L<<4) 3205#define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_4K (4L<<4) 3206#define BCE_MQ_CONFIG_MAX_DEPTH (0x7fL<<8) 3207#define BCE_MQ_CONFIG_CUR_DEPTH (0x7fL<<20) 3208 3209#define BCE_MQ_ENQUEUE1 0x00003c0c 3210#define BCE_MQ_ENQUEUE1_OFFSET (0x3fL<<2) 3211#define BCE_MQ_ENQUEUE1_CID (0x3fffL<<8) 3212#define BCE_MQ_ENQUEUE1_BYTE_MASK (0xfL<<24) 3213#define BCE_MQ_ENQUEUE1_KNL_MODE (1L<<28) 3214 3215#define BCE_MQ_ENQUEUE2 0x00003c10 3216#define BCE_MQ_BAD_WR_ADDR 0x00003c14 3217#define BCE_MQ_BAD_RD_ADDR 0x00003c18 3218#define BCE_MQ_KNL_BYP_WIND_START 0x00003c1c 3219#define BCE_MQ_KNL_BYP_WIND_START_VALUE (0xfffffL<<12) 3220 3221#define BCE_MQ_KNL_WIND_END 0x00003c20 3222#define BCE_MQ_KNL_WIND_END_VALUE (0xffffffL<<8) 3223 3224#define BCE_MQ_KNL_WRITE_MASK1 0x00003c24 3225#define BCE_MQ_KNL_TX_MASK1 0x00003c28 3226#define BCE_MQ_KNL_CMD_MASK1 0x00003c2c 3227#define BCE_MQ_KNL_COND_ENQUEUE_MASK1 0x00003c30 3228#define BCE_MQ_KNL_RX_V2P_MASK1 0x00003c34 3229#define BCE_MQ_KNL_WRITE_MASK2 0x00003c38 3230#define BCE_MQ_KNL_TX_MASK2 0x00003c3c 3231#define BCE_MQ_KNL_CMD_MASK2 0x00003c40 3232#define BCE_MQ_KNL_COND_ENQUEUE_MASK2 0x00003c44 3233#define BCE_MQ_KNL_RX_V2P_MASK2 0x00003c48 3234#define BCE_MQ_KNL_BYP_WRITE_MASK1 0x00003c4c 3235#define BCE_MQ_KNL_BYP_TX_MASK1 0x00003c50 3236#define BCE_MQ_KNL_BYP_CMD_MASK1 0x00003c54 3237#define BCE_MQ_KNL_BYP_COND_ENQUEUE_MASK1 0x00003c58 3238#define BCE_MQ_KNL_BYP_RX_V2P_MASK1 0x00003c5c 3239#define BCE_MQ_KNL_BYP_WRITE_MASK2 0x00003c60 3240#define BCE_MQ_KNL_BYP_TX_MASK2 0x00003c64 3241#define BCE_MQ_KNL_BYP_CMD_MASK2 0x00003c68 3242#define BCE_MQ_KNL_BYP_COND_ENQUEUE_MASK2 0x00003c6c 3243#define BCE_MQ_KNL_BYP_RX_V2P_MASK2 0x00003c70 3244#define BCE_MQ_MEM_WR_ADDR 0x00003c74 3245#define BCE_MQ_MEM_WR_ADDR_VALUE (0x3fL<<0) 3246 3247#define BCE_MQ_MEM_WR_DATA0 0x00003c78 3248#define BCE_MQ_MEM_WR_DATA0_VALUE (0xffffffffL<<0) 3249 3250#define BCE_MQ_MEM_WR_DATA1 0x00003c7c 3251#define BCE_MQ_MEM_WR_DATA1_VALUE (0xffffffffL<<0) 3252 3253#define BCE_MQ_MEM_WR_DATA2 0x00003c80 3254#define BCE_MQ_MEM_WR_DATA2_VALUE (0x3fffffffL<<0) 3255 3256#define BCE_MQ_MEM_RD_ADDR 0x00003c84 3257#define BCE_MQ_MEM_RD_ADDR_VALUE (0x3fL<<0) 3258 3259#define BCE_MQ_MEM_RD_DATA0 0x00003c88 3260#define BCE_MQ_MEM_RD_DATA0_VALUE (0xffffffffL<<0) 3261 3262#define BCE_MQ_MEM_RD_DATA1 0x00003c8c 3263#define BCE_MQ_MEM_RD_DATA1_VALUE (0xffffffffL<<0) 3264 3265#define BCE_MQ_MEM_RD_DATA2 0x00003c90 3266#define BCE_MQ_MEM_RD_DATA2_VALUE (0x3fffffffL<<0) 3267 3268 3269 3270/* 3271 * tbdr_reg definition 3272 * offset: 0x5000 3273 */ 3274#define BCE_TBDR_COMMAND 0x00005000 3275#define BCE_TBDR_COMMAND_ENABLE (1L<<0) 3276#define BCE_TBDR_COMMAND_SOFT_RST (1L<<1) 3277#define BCE_TBDR_COMMAND_MSTR_ABORT (1L<<4) 3278 3279#define BCE_TBDR_STATUS 0x00005004 3280#define BCE_TBDR_STATUS_DMA_WAIT (1L<<0) 3281#define BCE_TBDR_STATUS_FTQ_WAIT (1L<<1) 3282#define BCE_TBDR_STATUS_FIFO_OVERFLOW (1L<<2) 3283#define BCE_TBDR_STATUS_FIFO_UNDERFLOW (1L<<3) 3284#define BCE_TBDR_STATUS_SEARCHMISS_ERROR (1L<<4) 3285#define BCE_TBDR_STATUS_FTQ_ENTRY_CNT (1L<<5) 3286#define BCE_TBDR_STATUS_BURST_CNT (1L<<6) 3287 3288#define BCE_TBDR_CONFIG 0x00005008 3289#define BCE_TBDR_CONFIG_MAX_BDS (0xffL<<0) 3290#define BCE_TBDR_CONFIG_SWAP_MODE (1L<<8) 3291#define BCE_TBDR_CONFIG_PRIORITY (1L<<9) 3292#define BCE_TBDR_CONFIG_CACHE_NEXT_PAGE_PTRS (1L<<10) 3293#define BCE_TBDR_CONFIG_PAGE_SIZE (0xfL<<24) 3294#define BCE_TBDR_CONFIG_PAGE_SIZE_256 (0L<<24) 3295#define BCE_TBDR_CONFIG_PAGE_SIZE_512 (1L<<24) 3296#define BCE_TBDR_CONFIG_PAGE_SIZE_1K (2L<<24) 3297#define BCE_TBDR_CONFIG_PAGE_SIZE_2K (3L<<24) 3298#define BCE_TBDR_CONFIG_PAGE_SIZE_4K (4L<<24) 3299#define BCE_TBDR_CONFIG_PAGE_SIZE_8K (5L<<24) 3300#define BCE_TBDR_CONFIG_PAGE_SIZE_16K (6L<<24) 3301#define BCE_TBDR_CONFIG_PAGE_SIZE_32K (7L<<24) 3302#define BCE_TBDR_CONFIG_PAGE_SIZE_64K (8L<<24) 3303#define BCE_TBDR_CONFIG_PAGE_SIZE_128K (9L<<24) 3304#define BCE_TBDR_CONFIG_PAGE_SIZE_256K (10L<<24) 3305#define BCE_TBDR_CONFIG_PAGE_SIZE_512K (11L<<24) 3306#define BCE_TBDR_CONFIG_PAGE_SIZE_1M (12L<<24) 3307 3308#define BCE_TBDR_DEBUG_VECT_PEEK 0x0000500c 3309#define BCE_TBDR_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) 3310#define BCE_TBDR_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) 3311#define BCE_TBDR_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) 3312#define BCE_TBDR_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) 3313#define BCE_TBDR_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) 3314#define BCE_TBDR_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) 3315 3316#define BCE_TBDR_FTQ_DATA 0x000053c0 3317#define BCE_TBDR_FTQ_CMD 0x000053f8 3318#define BCE_TBDR_FTQ_CMD_OFFSET (0x3ffL<<0) 3319#define BCE_TBDR_FTQ_CMD_WR_TOP (1L<<10) 3320#define BCE_TBDR_FTQ_CMD_WR_TOP_0 (0L<<10) 3321#define BCE_TBDR_FTQ_CMD_WR_TOP_1 (1L<<10) 3322#define BCE_TBDR_FTQ_CMD_SFT_RESET (1L<<25) 3323#define BCE_TBDR_FTQ_CMD_RD_DATA (1L<<26) 3324#define BCE_TBDR_FTQ_CMD_ADD_INTERVEN (1L<<27) 3325#define BCE_TBDR_FTQ_CMD_ADD_DATA (1L<<28) 3326#define BCE_TBDR_FTQ_CMD_INTERVENE_CLR (1L<<29) 3327#define BCE_TBDR_FTQ_CMD_POP (1L<<30) 3328#define BCE_TBDR_FTQ_CMD_BUSY (1L<<31) 3329 3330#define BCE_TBDR_FTQ_CTL 0x000053fc 3331#define BCE_TBDR_FTQ_CTL_INTERVENE (1L<<0) 3332#define BCE_TBDR_FTQ_CTL_OVERFLOW (1L<<1) 3333#define BCE_TBDR_FTQ_CTL_FORCE_INTERVENE (1L<<2) 3334#define BCE_TBDR_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 3335#define BCE_TBDR_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 3336 3337 3338 3339/* 3340 * tdma_reg definition 3341 * offset: 0x5c00 3342 */ 3343#define BCE_TDMA_COMMAND 0x00005c00 3344#define BCE_TDMA_COMMAND_ENABLED (1L<<0) 3345#define BCE_TDMA_COMMAND_MASTER_ABORT (1L<<4) 3346#define BCE_TDMA_COMMAND_BAD_L2_LENGTH_ABORT (1L<<7) 3347 3348#define BCE_TDMA_STATUS 0x00005c04 3349#define BCE_TDMA_STATUS_DMA_WAIT (1L<<0) 3350#define BCE_TDMA_STATUS_PAYLOAD_WAIT (1L<<1) 3351#define BCE_TDMA_STATUS_PATCH_FTQ_WAIT (1L<<2) 3352#define BCE_TDMA_STATUS_LOCK_WAIT (1L<<3) 3353#define BCE_TDMA_STATUS_FTQ_ENTRY_CNT (1L<<16) 3354#define BCE_TDMA_STATUS_BURST_CNT (1L<<17) 3355 3356#define BCE_TDMA_CONFIG 0x00005c08 3357#define BCE_TDMA_CONFIG_ONE_DMA (1L<<0) 3358#define BCE_TDMA_CONFIG_ONE_RECORD (1L<<1) 3359#define BCE_TDMA_CONFIG_LIMIT_SZ (0xfL<<4) 3360#define BCE_TDMA_CONFIG_LIMIT_SZ_64 (0L<<4) 3361#define BCE_TDMA_CONFIG_LIMIT_SZ_128 (0x4L<<4) 3362#define BCE_TDMA_CONFIG_LIMIT_SZ_256 (0x6L<<4) 3363#define BCE_TDMA_CONFIG_LIMIT_SZ_512 (0x8L<<4) 3364#define BCE_TDMA_CONFIG_LINE_SZ (0xfL<<8) 3365#define BCE_TDMA_CONFIG_LINE_SZ_64 (0L<<8) 3366#define BCE_TDMA_CONFIG_LINE_SZ_128 (4L<<8) 3367#define BCE_TDMA_CONFIG_LINE_SZ_256 (6L<<8) 3368#define BCE_TDMA_CONFIG_LINE_SZ_512 (8L<<8) 3369#define BCE_TDMA_CONFIG_ALIGN_ENA (1L<<15) 3370#define BCE_TDMA_CONFIG_CHK_L2_BD (1L<<16) 3371#define BCE_TDMA_CONFIG_FIFO_CMP (0xfL<<20) 3372 3373#define BCE_TDMA_PAYLOAD_PROD 0x00005c0c 3374#define BCE_TDMA_PAYLOAD_PROD_VALUE (0x1fffL<<3) 3375 3376#define BCE_TDMA_DBG_WATCHDOG 0x00005c10 3377#define BCE_TDMA_DBG_TRIGGER 0x00005c14 3378#define BCE_TDMA_DMAD_FSM 0x00005c80 3379#define BCE_TDMA_DMAD_FSM_BD_INVLD (1L<<0) 3380#define BCE_TDMA_DMAD_FSM_PUSH (0xfL<<4) 3381#define BCE_TDMA_DMAD_FSM_ARB_TBDC (0x3L<<8) 3382#define BCE_TDMA_DMAD_FSM_ARB_CTX (1L<<12) 3383#define BCE_TDMA_DMAD_FSM_DR_INTF (1L<<16) 3384#define BCE_TDMA_DMAD_FSM_DMAD (0x7L<<20) 3385#define BCE_TDMA_DMAD_FSM_BD (0xfL<<24) 3386 3387#define BCE_TDMA_DMAD_STATUS 0x00005c84 3388#define BCE_TDMA_DMAD_STATUS_RHOLD_PUSH_ENTRY (0x3L<<0) 3389#define BCE_TDMA_DMAD_STATUS_RHOLD_DMAD_ENTRY (0x3L<<4) 3390#define BCE_TDMA_DMAD_STATUS_RHOLD_BD_ENTRY (0x3L<<8) 3391#define BCE_TDMA_DMAD_STATUS_IFTQ_ENUM (0xfL<<12) 3392 3393#define BCE_TDMA_DR_INTF_FSM 0x00005c88 3394#define BCE_TDMA_DR_INTF_FSM_L2_COMP (0x3L<<0) 3395#define BCE_TDMA_DR_INTF_FSM_TPATQ (0x7L<<4) 3396#define BCE_TDMA_DR_INTF_FSM_TPBUF (0x3L<<8) 3397#define BCE_TDMA_DR_INTF_FSM_DR_BUF (0x7L<<12) 3398#define BCE_TDMA_DR_INTF_FSM_DMAD (0x7L<<16) 3399 3400#define BCE_TDMA_DR_INTF_STATUS 0x00005c8c 3401#define BCE_TDMA_DR_INTF_STATUS_HOLE_PHASE (0x7L<<0) 3402#define BCE_TDMA_DR_INTF_STATUS_DATA_AVAIL (0x3L<<4) 3403#define BCE_TDMA_DR_INTF_STATUS_SHIFT_ADDR (0x7L<<8) 3404#define BCE_TDMA_DR_INTF_STATUS_NXT_PNTR (0xfL<<12) 3405#define BCE_TDMA_DR_INTF_STATUS_BYTE_COUNT (0x7L<<16) 3406 3407#define BCE_TDMA_FTQ_DATA 0x00005fc0 3408#define BCE_TDMA_FTQ_CMD 0x00005ff8 3409#define BCE_TDMA_FTQ_CMD_OFFSET (0x3ffL<<0) 3410#define BCE_TDMA_FTQ_CMD_WR_TOP (1L<<10) 3411#define BCE_TDMA_FTQ_CMD_WR_TOP_0 (0L<<10) 3412#define BCE_TDMA_FTQ_CMD_WR_TOP_1 (1L<<10) 3413#define BCE_TDMA_FTQ_CMD_SFT_RESET (1L<<25) 3414#define BCE_TDMA_FTQ_CMD_RD_DATA (1L<<26) 3415#define BCE_TDMA_FTQ_CMD_ADD_INTERVEN (1L<<27) 3416#define BCE_TDMA_FTQ_CMD_ADD_DATA (1L<<28) 3417#define BCE_TDMA_FTQ_CMD_INTERVENE_CLR (1L<<29) 3418#define BCE_TDMA_FTQ_CMD_POP (1L<<30) 3419#define BCE_TDMA_FTQ_CMD_BUSY (1L<<31) 3420 3421#define BCE_TDMA_FTQ_CTL 0x00005ffc 3422#define BCE_TDMA_FTQ_CTL_INTERVENE (1L<<0) 3423#define BCE_TDMA_FTQ_CTL_OVERFLOW (1L<<1) 3424#define BCE_TDMA_FTQ_CTL_FORCE_INTERVENE (1L<<2) 3425#define BCE_TDMA_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 3426#define BCE_TDMA_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 3427 3428 3429 3430/* 3431 * hc_reg definition 3432 * offset: 0x6800 3433 */ 3434#define BCE_HC_COMMAND 0x00006800 3435#define BCE_HC_COMMAND_ENABLE (1L<<0) 3436#define BCE_HC_COMMAND_SKIP_ABORT (1L<<4) 3437#define BCE_HC_COMMAND_COAL_NOW (1L<<16) 3438#define BCE_HC_COMMAND_COAL_NOW_WO_INT (1L<<17) 3439#define BCE_HC_COMMAND_STATS_NOW (1L<<18) 3440#define BCE_HC_COMMAND_FORCE_INT (0x3L<<19) 3441#define BCE_HC_COMMAND_FORCE_INT_NULL (0L<<19) 3442#define BCE_HC_COMMAND_FORCE_INT_HIGH (1L<<19) 3443#define BCE_HC_COMMAND_FORCE_INT_LOW (2L<<19) 3444#define BCE_HC_COMMAND_FORCE_INT_FREE (3L<<19) 3445#define BCE_HC_COMMAND_CLR_STAT_NOW (1L<<21) 3446 3447#define BCE_HC_STATUS 0x00006804 3448#define BCE_HC_STATUS_MASTER_ABORT (1L<<0) 3449#define BCE_HC_STATUS_PARITY_ERROR_STATE (1L<<1) 3450#define BCE_HC_STATUS_PCI_CLK_CNT_STAT (1L<<16) 3451#define BCE_HC_STATUS_CORE_CLK_CNT_STAT (1L<<17) 3452#define BCE_HC_STATUS_NUM_STATUS_BLOCKS_STAT (1L<<18) 3453#define BCE_HC_STATUS_NUM_INT_GEN_STAT (1L<<19) 3454#define BCE_HC_STATUS_NUM_INT_MBOX_WR_STAT (1L<<20) 3455#define BCE_HC_STATUS_CORE_CLKS_TO_HW_INTACK_STAT (1L<<23) 3456#define BCE_HC_STATUS_CORE_CLKS_TO_SW_INTACK_STAT (1L<<24) 3457#define BCE_HC_STATUS_CORE_CLKS_DURING_SW_INTACK_STAT (1L<<25) 3458 3459#define BCE_HC_CONFIG 0x00006808 3460#define BCE_HC_CONFIG_COLLECT_STATS (1L<<0) 3461#define BCE_HC_CONFIG_RX_TMR_MODE (1L<<1) 3462#define BCE_HC_CONFIG_TX_TMR_MODE (1L<<2) 3463#define BCE_HC_CONFIG_COM_TMR_MODE (1L<<3) 3464#define BCE_HC_CONFIG_CMD_TMR_MODE (1L<<4) 3465#define BCE_HC_CONFIG_STATISTIC_PRIORITY (1L<<5) 3466#define BCE_HC_CONFIG_STATUS_PRIORITY (1L<<6) 3467#define BCE_HC_CONFIG_STAT_MEM_ADDR (0xffL<<8) 3468 3469#define BCE_HC_ATTN_BITS_ENABLE 0x0000680c 3470#define BCE_HC_STATUS_ADDR_L 0x00006810 3471#define BCE_HC_STATUS_ADDR_H 0x00006814 3472#define BCE_HC_STATISTICS_ADDR_L 0x00006818 3473#define BCE_HC_STATISTICS_ADDR_H 0x0000681c 3474#define BCE_HC_TX_QUICK_CONS_TRIP 0x00006820 3475#define BCE_HC_TX_QUICK_CONS_TRIP_VALUE (0xffL<<0) 3476#define BCE_HC_TX_QUICK_CONS_TRIP_INT (0xffL<<16) 3477 3478#define BCE_HC_COMP_PROD_TRIP 0x00006824 3479#define BCE_HC_COMP_PROD_TRIP_VALUE (0xffL<<0) 3480#define BCE_HC_COMP_PROD_TRIP_INT (0xffL<<16) 3481 3482#define BCE_HC_RX_QUICK_CONS_TRIP 0x00006828 3483#define BCE_HC_RX_QUICK_CONS_TRIP_VALUE (0xffL<<0) 3484#define BCE_HC_RX_QUICK_CONS_TRIP_INT (0xffL<<16) 3485 3486#define BCE_HC_RX_TICKS 0x0000682c 3487#define BCE_HC_RX_TICKS_VALUE (0x3ffL<<0) 3488#define BCE_HC_RX_TICKS_INT (0x3ffL<<16) 3489 3490#define BCE_HC_TX_TICKS 0x00006830 3491#define BCE_HC_TX_TICKS_VALUE (0x3ffL<<0) 3492#define BCE_HC_TX_TICKS_INT (0x3ffL<<16) 3493 3494#define BCE_HC_COM_TICKS 0x00006834 3495#define BCE_HC_COM_TICKS_VALUE (0x3ffL<<0) 3496#define BCE_HC_COM_TICKS_INT (0x3ffL<<16) 3497 3498#define BCE_HC_CMD_TICKS 0x00006838 3499#define BCE_HC_CMD_TICKS_VALUE (0x3ffL<<0) 3500#define BCE_HC_CMD_TICKS_INT (0x3ffL<<16) 3501 3502#define BCE_HC_PERIODIC_TICKS 0x0000683c 3503#define BCE_HC_PERIODIC_TICKS_HC_PERIODIC_TICKS (0xffffL<<0) 3504 3505#define BCE_HC_STAT_COLLECT_TICKS 0x00006840 3506#define BCE_HC_STAT_COLLECT_TICKS_HC_STAT_COLL_TICKS (0xffL<<4) 3507 3508#define BCE_HC_STATS_TICKS 0x00006844 3509#define BCE_HC_STATS_TICKS_HC_STAT_TICKS (0xffffL<<8) 3510 3511#define BCE_HC_STAT_MEM_DATA 0x0000684c 3512#define BCE_HC_STAT_GEN_SEL_0 0x00006850 3513#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0 (0x7fL<<0) 3514#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT0 (0L<<0) 3515#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT1 (1L<<0) 3516#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT2 (2L<<0) 3517#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT3 (3L<<0) 3518#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT4 (4L<<0) 3519#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT5 (5L<<0) 3520#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT6 (6L<<0) 3521#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT7 (7L<<0) 3522#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT8 (8L<<0) 3523#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT9 (9L<<0) 3524#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT10 (10L<<0) 3525#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT11 (11L<<0) 3526#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT0 (12L<<0) 3527#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT1 (13L<<0) 3528#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT2 (14L<<0) 3529#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT3 (15L<<0) 3530#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT4 (16L<<0) 3531#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT5 (17L<<0) 3532#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT6 (18L<<0) 3533#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT7 (19L<<0) 3534#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT0 (20L<<0) 3535#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT1 (21L<<0) 3536#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT2 (22L<<0) 3537#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT3 (23L<<0) 3538#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT4 (24L<<0) 3539#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT5 (25L<<0) 3540#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT6 (26L<<0) 3541#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT7 (27L<<0) 3542#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT8 (28L<<0) 3543#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT9 (29L<<0) 3544#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT10 (30L<<0) 3545#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT11 (31L<<0) 3546#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT0 (32L<<0) 3547#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT1 (33L<<0) 3548#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT2 (34L<<0) 3549#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT3 (35L<<0) 3550#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT0 (36L<<0) 3551#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT1 (37L<<0) 3552#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT2 (38L<<0) 3553#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT3 (39L<<0) 3554#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT4 (40L<<0) 3555#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT5 (41L<<0) 3556#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT6 (42L<<0) 3557#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT7 (43L<<0) 3558#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT0 (44L<<0) 3559#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT1 (45L<<0) 3560#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT2 (46L<<0) 3561#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT3 (47L<<0) 3562#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT4 (48L<<0) 3563#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT5 (49L<<0) 3564#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT6 (50L<<0) 3565#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT7 (51L<<0) 3566#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_PCI_CLK_CNT (52L<<0) 3567#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CORE_CLK_CNT (53L<<0) 3568#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS (54L<<0) 3569#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN (55L<<0) 3570#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR (56L<<0) 3571#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK (59L<<0) 3572#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK (60L<<0) 3573#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK (61L<<0) 3574#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_CMD_CNT (62L<<0) 3575#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_SLOT_CNT (63L<<0) 3576#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_CMD_CNT (64L<<0) 3577#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_SLOT_CNT (65L<<0) 3578#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT (66L<<0) 3579#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT (67L<<0) 3580#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT (68L<<0) 3581#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT (69L<<0) 3582#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT (70L<<0) 3583#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT (71L<<0) 3584#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT (72L<<0) 3585#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT (73L<<0) 3586#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT (74L<<0) 3587#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT (75L<<0) 3588#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT (76L<<0) 3589#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT (77L<<0) 3590#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT (78L<<0) 3591#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT (79L<<0) 3592#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT (80L<<0) 3593#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT (81L<<0) 3594#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT (82L<<0) 3595#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT (83L<<0) 3596#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT (84L<<0) 3597#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_TRANSFERS_CNT (85L<<0) 3598#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_DELAY_PCI_CLKS_CNT (86L<<0) 3599#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_TRANSFERS_CNT (87L<<0) 3600#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_DELAY_PCI_CLKS_CNT (88L<<0) 3601#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_RETRY_AFTER_DATA_CNT (89L<<0) 3602#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_TRANSFERS_CNT (90L<<0) 3603#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_DELAY_PCI_CLKS_CNT (91L<<0) 3604#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_TRANSFERS_CNT (92L<<0) 3605#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_DELAY_PCI_CLKS_CNT (93L<<0) 3606#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_RETRY_AFTER_DATA_CNT (94L<<0) 3607#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_WR_CNT64 (95L<<0) 3608#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_RD_CNT64 (96L<<0) 3609#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_ACC_STALL_CLKS (97L<<0) 3610#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_LOCK_STALL_CLKS (98L<<0) 3611#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS_STAT (99L<<0) 3612#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS64_STAT (100L<<0) 3613#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_PCI_STALL_STAT (101L<<0) 3614#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_FTQ_ENTRY_CNT (102L<<0) 3615#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_BURST_CNT (103L<<0) 3616#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_FTQ_ENTRY_CNT (104L<<0) 3617#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_BURST_CNT (105L<<0) 3618#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_FTQ_ENTRY_CNT (106L<<0) 3619#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_BURST_CNT (107L<<0) 3620#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUP_MATCH_CNT (108L<<0) 3621#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_POLL_PASS_CNT (109L<<0) 3622#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR1_CNT (110L<<0) 3623#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR2_CNT (111L<<0) 3624#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR3_CNT (112L<<0) 3625#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR4_CNT (113L<<0) 3626#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR5_CNT (114L<<0) 3627#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT0 (115L<<0) 3628#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT1 (116L<<0) 3629#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT2 (117L<<0) 3630#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT3 (118L<<0) 3631#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT4 (119L<<0) 3632#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT5 (120L<<0) 3633#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC1_MISS (121L<<0) 3634#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC2_MISS (122L<<0) 3635#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_BURST_CNT (127L<<0) 3636#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_1 (0x7fL<<8) 3637#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_2 (0x7fL<<16) 3638#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_3 (0x7fL<<24) 3639 3640#define BCE_HC_STAT_GEN_SEL_1 0x00006854 3641#define BCE_HC_STAT_GEN_SEL_1_GEN_SEL_4 (0x7fL<<0) 3642#define BCE_HC_STAT_GEN_SEL_1_GEN_SEL_5 (0x7fL<<8) 3643#define BCE_HC_STAT_GEN_SEL_1_GEN_SEL_6 (0x7fL<<16) 3644#define BCE_HC_STAT_GEN_SEL_1_GEN_SEL_7 (0x7fL<<24) 3645 3646#define BCE_HC_STAT_GEN_SEL_2 0x00006858 3647#define BCE_HC_STAT_GEN_SEL_2_GEN_SEL_8 (0x7fL<<0) 3648#define BCE_HC_STAT_GEN_SEL_2_GEN_SEL_9 (0x7fL<<8) 3649#define BCE_HC_STAT_GEN_SEL_2_GEN_SEL_10 (0x7fL<<16) 3650#define BCE_HC_STAT_GEN_SEL_2_GEN_SEL_11 (0x7fL<<24) 3651 3652#define BCE_HC_STAT_GEN_SEL_3 0x0000685c 3653#define BCE_HC_STAT_GEN_SEL_3_GEN_SEL_12 (0x7fL<<0) 3654#define BCE_HC_STAT_GEN_SEL_3_GEN_SEL_13 (0x7fL<<8) 3655#define BCE_HC_STAT_GEN_SEL_3_GEN_SEL_14 (0x7fL<<16) 3656#define BCE_HC_STAT_GEN_SEL_3_GEN_SEL_15 (0x7fL<<24) 3657 3658#define BCE_HC_STAT_GEN_STAT0 0x00006888 3659#define BCE_HC_STAT_GEN_STAT1 0x0000688c 3660#define BCE_HC_STAT_GEN_STAT2 0x00006890 3661#define BCE_HC_STAT_GEN_STAT3 0x00006894 3662#define BCE_HC_STAT_GEN_STAT4 0x00006898 3663#define BCE_HC_STAT_GEN_STAT5 0x0000689c 3664#define BCE_HC_STAT_GEN_STAT6 0x000068a0 3665#define BCE_HC_STAT_GEN_STAT7 0x000068a4 3666#define BCE_HC_STAT_GEN_STAT8 0x000068a8 3667#define BCE_HC_STAT_GEN_STAT9 0x000068ac 3668#define BCE_HC_STAT_GEN_STAT10 0x000068b0 3669#define BCE_HC_STAT_GEN_STAT11 0x000068b4 3670#define BCE_HC_STAT_GEN_STAT12 0x000068b8 3671#define BCE_HC_STAT_GEN_STAT13 0x000068bc 3672#define BCE_HC_STAT_GEN_STAT14 0x000068c0 3673#define BCE_HC_STAT_GEN_STAT15 0x000068c4 3674#define BCE_HC_STAT_GEN_STAT_AC0 0x000068c8 3675#define BCE_HC_STAT_GEN_STAT_AC1 0x000068cc 3676#define BCE_HC_STAT_GEN_STAT_AC2 0x000068d0 3677#define BCE_HC_STAT_GEN_STAT_AC3 0x000068d4 3678#define BCE_HC_STAT_GEN_STAT_AC4 0x000068d8 3679#define BCE_HC_STAT_GEN_STAT_AC5 0x000068dc 3680#define BCE_HC_STAT_GEN_STAT_AC6 0x000068e0 3681#define BCE_HC_STAT_GEN_STAT_AC7 0x000068e4 3682#define BCE_HC_STAT_GEN_STAT_AC8 0x000068e8 3683#define BCE_HC_STAT_GEN_STAT_AC9 0x000068ec 3684#define BCE_HC_STAT_GEN_STAT_AC10 0x000068f0 3685#define BCE_HC_STAT_GEN_STAT_AC11 0x000068f4 3686#define BCE_HC_STAT_GEN_STAT_AC12 0x000068f8 3687#define BCE_HC_STAT_GEN_STAT_AC13 0x000068fc 3688#define BCE_HC_STAT_GEN_STAT_AC14 0x00006900 3689#define BCE_HC_STAT_GEN_STAT_AC15 0x00006904 3690#define BCE_HC_VIS 0x00006908 3691#define BCE_HC_VIS_STAT_BUILD_STATE (0xfL<<0) 3692#define BCE_HC_VIS_STAT_BUILD_STATE_IDLE (0L<<0) 3693#define BCE_HC_VIS_STAT_BUILD_STATE_START (1L<<0) 3694#define BCE_HC_VIS_STAT_BUILD_STATE_REQUEST (2L<<0) 3695#define BCE_HC_VIS_STAT_BUILD_STATE_UPDATE64 (3L<<0) 3696#define BCE_HC_VIS_STAT_BUILD_STATE_UPDATE32 (4L<<0) 3697#define BCE_HC_VIS_STAT_BUILD_STATE_UPDATE_DONE (5L<<0) 3698#define BCE_HC_VIS_STAT_BUILD_STATE_DMA (6L<<0) 3699#define BCE_HC_VIS_STAT_BUILD_STATE_MSI_CONTROL (7L<<0) 3700#define BCE_HC_VIS_STAT_BUILD_STATE_MSI_LOW (8L<<0) 3701#define BCE_HC_VIS_STAT_BUILD_STATE_MSI_HIGH (9L<<0) 3702#define BCE_HC_VIS_STAT_BUILD_STATE_MSI_DATA (10L<<0) 3703#define BCE_HC_VIS_DMA_STAT_STATE (0xfL<<8) 3704#define BCE_HC_VIS_DMA_STAT_STATE_IDLE (0L<<8) 3705#define BCE_HC_VIS_DMA_STAT_STATE_STATUS_PARAM (1L<<8) 3706#define BCE_HC_VIS_DMA_STAT_STATE_STATUS_DMA (2L<<8) 3707#define BCE_HC_VIS_DMA_STAT_STATE_WRITE_COMP (3L<<8) 3708#define BCE_HC_VIS_DMA_STAT_STATE_COMP (4L<<8) 3709#define BCE_HC_VIS_DMA_STAT_STATE_STATISTIC_PARAM (5L<<8) 3710#define BCE_HC_VIS_DMA_STAT_STATE_STATISTIC_DMA (6L<<8) 3711#define BCE_HC_VIS_DMA_STAT_STATE_WRITE_COMP_1 (7L<<8) 3712#define BCE_HC_VIS_DMA_STAT_STATE_WRITE_COMP_2 (8L<<8) 3713#define BCE_HC_VIS_DMA_STAT_STATE_WAIT (9L<<8) 3714#define BCE_HC_VIS_DMA_STAT_STATE_ABORT (15L<<8) 3715#define BCE_HC_VIS_DMA_MSI_STATE (0x7L<<12) 3716#define BCE_HC_VIS_STATISTIC_DMA_EN_STATE (0x3L<<15) 3717#define BCE_HC_VIS_STATISTIC_DMA_EN_STATE_IDLE (0L<<15) 3718#define BCE_HC_VIS_STATISTIC_DMA_EN_STATE_COUNT (1L<<15) 3719#define BCE_HC_VIS_STATISTIC_DMA_EN_STATE_START (2L<<15) 3720 3721#define BCE_HC_VIS_1 0x0000690c 3722#define BCE_HC_VIS_1_HW_INTACK_STATE (1L<<4) 3723#define BCE_HC_VIS_1_HW_INTACK_STATE_IDLE (0L<<4) 3724#define BCE_HC_VIS_1_HW_INTACK_STATE_COUNT (1L<<4) 3725#define BCE_HC_VIS_1_SW_INTACK_STATE (1L<<5) 3726#define BCE_HC_VIS_1_SW_INTACK_STATE_IDLE (0L<<5) 3727#define BCE_HC_VIS_1_SW_INTACK_STATE_COUNT (1L<<5) 3728#define BCE_HC_VIS_1_DURING_SW_INTACK_STATE (1L<<6) 3729#define BCE_HC_VIS_1_DURING_SW_INTACK_STATE_IDLE (0L<<6) 3730#define BCE_HC_VIS_1_DURING_SW_INTACK_STATE_COUNT (1L<<6) 3731#define BCE_HC_VIS_1_MAILBOX_COUNT_STATE (1L<<7) 3732#define BCE_HC_VIS_1_MAILBOX_COUNT_STATE_IDLE (0L<<7) 3733#define BCE_HC_VIS_1_MAILBOX_COUNT_STATE_COUNT (1L<<7) 3734#define BCE_HC_VIS_1_RAM_RD_ARB_STATE (0xfL<<17) 3735#define BCE_HC_VIS_1_RAM_RD_ARB_STATE_IDLE (0L<<17) 3736#define BCE_HC_VIS_1_RAM_RD_ARB_STATE_DMA (1L<<17) 3737#define BCE_HC_VIS_1_RAM_RD_ARB_STATE_UPDATE (2L<<17) 3738#define BCE_HC_VIS_1_RAM_RD_ARB_STATE_ASSIGN (3L<<17) 3739#define BCE_HC_VIS_1_RAM_RD_ARB_STATE_WAIT (4L<<17) 3740#define BCE_HC_VIS_1_RAM_RD_ARB_STATE_REG_UPDATE (5L<<17) 3741#define BCE_HC_VIS_1_RAM_RD_ARB_STATE_REG_ASSIGN (6L<<17) 3742#define BCE_HC_VIS_1_RAM_RD_ARB_STATE_REG_WAIT (7L<<17) 3743#define BCE_HC_VIS_1_RAM_WR_ARB_STATE (0x3L<<21) 3744#define BCE_HC_VIS_1_RAM_WR_ARB_STATE_NORMAL (0L<<21) 3745#define BCE_HC_VIS_1_RAM_WR_ARB_STATE_CLEAR (1L<<21) 3746#define BCE_HC_VIS_1_INT_GEN_STATE (1L<<23) 3747#define BCE_HC_VIS_1_INT_GEN_STATE_DLE (0L<<23) 3748#define BCE_HC_VIS_1_INT_GEN_STATE_NTERRUPT (1L<<23) 3749#define BCE_HC_VIS_1_STAT_CHAN_ID (0x7L<<24) 3750#define BCE_HC_VIS_1_INT_B (1L<<27) 3751 3752#define BCE_HC_DEBUG_VECT_PEEK 0x00006910 3753#define BCE_HC_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) 3754#define BCE_HC_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) 3755#define BCE_HC_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) 3756#define BCE_HC_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) 3757#define BCE_HC_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) 3758#define BCE_HC_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) 3759 3760 3761 3762/* 3763 * txp_reg definition 3764 * offset: 0x40000 3765 */ 3766#define BCE_TXP_CPU_MODE 0x00045000 3767#define BCE_TXP_CPU_MODE_LOCAL_RST (1L<<0) 3768#define BCE_TXP_CPU_MODE_STEP_ENA (1L<<1) 3769#define BCE_TXP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2) 3770#define BCE_TXP_CPU_MODE_PAGE_0_INST_ENA (1L<<3) 3771#define BCE_TXP_CPU_MODE_MSG_BIT1 (1L<<6) 3772#define BCE_TXP_CPU_MODE_INTERRUPT_ENA (1L<<7) 3773#define BCE_TXP_CPU_MODE_SOFT_HALT (1L<<10) 3774#define BCE_TXP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11) 3775#define BCE_TXP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12) 3776#define BCE_TXP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13) 3777#define BCE_TXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15) 3778 3779#define BCE_TXP_CPU_STATE 0x00045004 3780#define BCE_TXP_CPU_STATE_BREAKPOINT (1L<<0) 3781#define BCE_TXP_CPU_STATE_BAD_INST_HALTED (1L<<2) 3782#define BCE_TXP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) 3783#define BCE_TXP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) 3784#define BCE_TXP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) 3785#define BCE_TXP_CPU_STATE_BAD_pc_HALTED (1L<<6) 3786#define BCE_TXP_CPU_STATE_ALIGN_HALTED (1L<<7) 3787#define BCE_TXP_CPU_STATE_FIO_ABORT_HALTED (1L<<8) 3788#define BCE_TXP_CPU_STATE_SOFT_HALTED (1L<<10) 3789#define BCE_TXP_CPU_STATE_SPAD_UNDERFLOW (1L<<11) 3790#define BCE_TXP_CPU_STATE_INTERRRUPT (1L<<12) 3791#define BCE_TXP_CPU_STATE_DATA_ACCESS_STALL (1L<<14) 3792#define BCE_TXP_CPU_STATE_INST_FETCH_STALL (1L<<15) 3793#define BCE_TXP_CPU_STATE_BLOCKED_READ (1L<<31) 3794 3795#define BCE_TXP_CPU_EVENT_MASK 0x00045008 3796#define BCE_TXP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) 3797#define BCE_TXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2) 3798#define BCE_TXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3) 3799#define BCE_TXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4) 3800#define BCE_TXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5) 3801#define BCE_TXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6) 3802#define BCE_TXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7) 3803#define BCE_TXP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8) 3804#define BCE_TXP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10) 3805#define BCE_TXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11) 3806#define BCE_TXP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12) 3807 3808#define BCE_TXP_CPU_PROGRAM_COUNTER 0x0004501c 3809#define BCE_TXP_CPU_INSTRUCTION 0x00045020 3810#define BCE_TXP_CPU_DATA_ACCESS 0x00045024 3811#define BCE_TXP_CPU_INTERRUPT_ENABLE 0x00045028 3812#define BCE_TXP_CPU_INTERRUPT_VECTOR 0x0004502c 3813#define BCE_TXP_CPU_INTERRUPT_SAVED_PC 0x00045030 3814#define BCE_TXP_CPU_HW_BREAKPOINT 0x00045034 3815#define BCE_TXP_CPU_HW_BREAKPOINT_DISABLE (1L<<0) 3816#define BCE_TXP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2) 3817 3818#define BCE_TXP_CPU_DEBUG_VECT_PEEK 0x00045038 3819#define BCE_TXP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) 3820#define BCE_TXP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) 3821#define BCE_TXP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) 3822#define BCE_TXP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) 3823#define BCE_TXP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) 3824#define BCE_TXP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) 3825 3826#define BCE_TXP_CPU_LAST_BRANCH_ADDR 0x00045048 3827#define BCE_TXP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1) 3828#define BCE_TXP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1) 3829#define BCE_TXP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1) 3830#define BCE_TXP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2) 3831 3832#define BCE_TXP_CPU_REG_FILE 0x00045200 3833#define BCE_TXP_FTQ_DATA 0x000453c0 3834#define BCE_TXP_FTQ_CMD 0x000453f8 3835#define BCE_TXP_FTQ_CMD_OFFSET (0x3ffL<<0) 3836#define BCE_TXP_FTQ_CMD_WR_TOP (1L<<10) 3837#define BCE_TXP_FTQ_CMD_WR_TOP_0 (0L<<10) 3838#define BCE_TXP_FTQ_CMD_WR_TOP_1 (1L<<10) 3839#define BCE_TXP_FTQ_CMD_SFT_RESET (1L<<25) 3840#define BCE_TXP_FTQ_CMD_RD_DATA (1L<<26) 3841#define BCE_TXP_FTQ_CMD_ADD_INTERVEN (1L<<27) 3842#define BCE_TXP_FTQ_CMD_ADD_DATA (1L<<28) 3843#define BCE_TXP_FTQ_CMD_INTERVENE_CLR (1L<<29) 3844#define BCE_TXP_FTQ_CMD_POP (1L<<30) 3845#define BCE_TXP_FTQ_CMD_BUSY (1L<<31) 3846 3847#define BCE_TXP_FTQ_CTL 0x000453fc 3848#define BCE_TXP_FTQ_CTL_INTERVENE (1L<<0) 3849#define BCE_TXP_FTQ_CTL_OVERFLOW (1L<<1) 3850#define BCE_TXP_FTQ_CTL_FORCE_INTERVENE (1L<<2) 3851#define BCE_TXP_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 3852#define BCE_TXP_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 3853 3854#define BCE_TXP_SCRATCH 0x00060000 3855 3856 3857/* 3858 * tpat_reg definition 3859 * offset: 0x80000 3860 */ 3861#define BCE_TPAT_CPU_MODE 0x00085000 3862#define BCE_TPAT_CPU_MODE_LOCAL_RST (1L<<0) 3863#define BCE_TPAT_CPU_MODE_STEP_ENA (1L<<1) 3864#define BCE_TPAT_CPU_MODE_PAGE_0_DATA_ENA (1L<<2) 3865#define BCE_TPAT_CPU_MODE_PAGE_0_INST_ENA (1L<<3) 3866#define BCE_TPAT_CPU_MODE_MSG_BIT1 (1L<<6) 3867#define BCE_TPAT_CPU_MODE_INTERRUPT_ENA (1L<<7) 3868#define BCE_TPAT_CPU_MODE_SOFT_HALT (1L<<10) 3869#define BCE_TPAT_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11) 3870#define BCE_TPAT_CPU_MODE_BAD_INST_HALT_ENA (1L<<12) 3871#define BCE_TPAT_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13) 3872#define BCE_TPAT_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15) 3873 3874#define BCE_TPAT_CPU_STATE 0x00085004 3875#define BCE_TPAT_CPU_STATE_BREAKPOINT (1L<<0) 3876#define BCE_TPAT_CPU_STATE_BAD_INST_HALTED (1L<<2) 3877#define BCE_TPAT_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) 3878#define BCE_TPAT_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) 3879#define BCE_TPAT_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) 3880#define BCE_TPAT_CPU_STATE_BAD_pc_HALTED (1L<<6) 3881#define BCE_TPAT_CPU_STATE_ALIGN_HALTED (1L<<7) 3882#define BCE_TPAT_CPU_STATE_FIO_ABORT_HALTED (1L<<8) 3883#define BCE_TPAT_CPU_STATE_SOFT_HALTED (1L<<10) 3884#define BCE_TPAT_CPU_STATE_SPAD_UNDERFLOW (1L<<11) 3885#define BCE_TPAT_CPU_STATE_INTERRRUPT (1L<<12) 3886#define BCE_TPAT_CPU_STATE_DATA_ACCESS_STALL (1L<<14) 3887#define BCE_TPAT_CPU_STATE_INST_FETCH_STALL (1L<<15) 3888#define BCE_TPAT_CPU_STATE_BLOCKED_READ (1L<<31) 3889 3890#define BCE_TPAT_CPU_EVENT_MASK 0x00085008 3891#define BCE_TPAT_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) 3892#define BCE_TPAT_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2) 3893#define BCE_TPAT_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3) 3894#define BCE_TPAT_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4) 3895#define BCE_TPAT_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5) 3896#define BCE_TPAT_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6) 3897#define BCE_TPAT_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7) 3898#define BCE_TPAT_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8) 3899#define BCE_TPAT_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10) 3900#define BCE_TPAT_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11) 3901#define BCE_TPAT_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12) 3902 3903#define BCE_TPAT_CPU_PROGRAM_COUNTER 0x0008501c 3904#define BCE_TPAT_CPU_INSTRUCTION 0x00085020 3905#define BCE_TPAT_CPU_DATA_ACCESS 0x00085024 3906#define BCE_TPAT_CPU_INTERRUPT_ENABLE 0x00085028 3907#define BCE_TPAT_CPU_INTERRUPT_VECTOR 0x0008502c 3908#define BCE_TPAT_CPU_INTERRUPT_SAVED_PC 0x00085030 3909#define BCE_TPAT_CPU_HW_BREAKPOINT 0x00085034 3910#define BCE_TPAT_CPU_HW_BREAKPOINT_DISABLE (1L<<0) 3911#define BCE_TPAT_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2) 3912 3913#define BCE_TPAT_CPU_DEBUG_VECT_PEEK 0x00085038 3914#define BCE_TPAT_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) 3915#define BCE_TPAT_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) 3916#define BCE_TPAT_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) 3917#define BCE_TPAT_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) 3918#define BCE_TPAT_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) 3919#define BCE_TPAT_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) 3920 3921#define BCE_TPAT_CPU_LAST_BRANCH_ADDR 0x00085048 3922#define BCE_TPAT_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1) 3923#define BCE_TPAT_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1) 3924#define BCE_TPAT_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1) 3925#define BCE_TPAT_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2) 3926 3927#define BCE_TPAT_CPU_REG_FILE 0x00085200 3928#define BCE_TPAT_FTQ_DATA 0x000853c0 3929#define BCE_TPAT_FTQ_CMD 0x000853f8 3930#define BCE_TPAT_FTQ_CMD_OFFSET (0x3ffL<<0) 3931#define BCE_TPAT_FTQ_CMD_WR_TOP (1L<<10) 3932#define BCE_TPAT_FTQ_CMD_WR_TOP_0 (0L<<10) 3933#define BCE_TPAT_FTQ_CMD_WR_TOP_1 (1L<<10) 3934#define BCE_TPAT_FTQ_CMD_SFT_RESET (1L<<25) 3935#define BCE_TPAT_FTQ_CMD_RD_DATA (1L<<26) 3936#define BCE_TPAT_FTQ_CMD_ADD_INTERVEN (1L<<27) 3937#define BCE_TPAT_FTQ_CMD_ADD_DATA (1L<<28) 3938#define BCE_TPAT_FTQ_CMD_INTERVENE_CLR (1L<<29) 3939#define BCE_TPAT_FTQ_CMD_POP (1L<<30) 3940#define BCE_TPAT_FTQ_CMD_BUSY (1L<<31) 3941 3942#define BCE_TPAT_FTQ_CTL 0x000853fc 3943#define BCE_TPAT_FTQ_CTL_INTERVENE (1L<<0) 3944#define BCE_TPAT_FTQ_CTL_OVERFLOW (1L<<1) 3945#define BCE_TPAT_FTQ_CTL_FORCE_INTERVENE (1L<<2) 3946#define BCE_TPAT_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 3947#define BCE_TPAT_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 3948 3949#define BCE_TPAT_SCRATCH 0x000a0000 3950 3951 3952/* 3953 * rxp_reg definition 3954 * offset: 0xc0000 3955 */ 3956#define BCE_RXP_CPU_MODE 0x000c5000 3957#define BCE_RXP_CPU_MODE_LOCAL_RST (1L<<0) 3958#define BCE_RXP_CPU_MODE_STEP_ENA (1L<<1) 3959#define BCE_RXP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2) 3960#define BCE_RXP_CPU_MODE_PAGE_0_INST_ENA (1L<<3) 3961#define BCE_RXP_CPU_MODE_MSG_BIT1 (1L<<6) 3962#define BCE_RXP_CPU_MODE_INTERRUPT_ENA (1L<<7) 3963#define BCE_RXP_CPU_MODE_SOFT_HALT (1L<<10) 3964#define BCE_RXP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11) 3965#define BCE_RXP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12) 3966#define BCE_RXP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13) 3967#define BCE_RXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15) 3968 3969#define BCE_RXP_CPU_STATE 0x000c5004 3970#define BCE_RXP_CPU_STATE_BREAKPOINT (1L<<0) 3971#define BCE_RXP_CPU_STATE_BAD_INST_HALTED (1L<<2) 3972#define BCE_RXP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) 3973#define BCE_RXP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) 3974#define BCE_RXP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) 3975#define BCE_RXP_CPU_STATE_BAD_pc_HALTED (1L<<6) 3976#define BCE_RXP_CPU_STATE_ALIGN_HALTED (1L<<7) 3977#define BCE_RXP_CPU_STATE_FIO_ABORT_HALTED (1L<<8) 3978#define BCE_RXP_CPU_STATE_SOFT_HALTED (1L<<10) 3979#define BCE_RXP_CPU_STATE_SPAD_UNDERFLOW (1L<<11) 3980#define BCE_RXP_CPU_STATE_INTERRRUPT (1L<<12) 3981#define BCE_RXP_CPU_STATE_DATA_ACCESS_STALL (1L<<14) 3982#define BCE_RXP_CPU_STATE_INST_FETCH_STALL (1L<<15) 3983#define BCE_RXP_CPU_STATE_BLOCKED_READ (1L<<31) 3984 3985#define BCE_RXP_CPU_EVENT_MASK 0x000c5008 3986#define BCE_RXP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) 3987#define BCE_RXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2) 3988#define BCE_RXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3) 3989#define BCE_RXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4) 3990#define BCE_RXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5) 3991#define BCE_RXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6) 3992#define BCE_RXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7) 3993#define BCE_RXP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8) 3994#define BCE_RXP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10) 3995#define BCE_RXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11) 3996#define BCE_RXP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12) 3997 3998#define BCE_RXP_CPU_PROGRAM_COUNTER 0x000c501c 3999#define BCE_RXP_CPU_INSTRUCTION 0x000c5020 4000#define BCE_RXP_CPU_DATA_ACCESS 0x000c5024 4001#define BCE_RXP_CPU_INTERRUPT_ENABLE 0x000c5028 4002#define BCE_RXP_CPU_INTERRUPT_VECTOR 0x000c502c 4003#define BCE_RXP_CPU_INTERRUPT_SAVED_PC 0x000c5030 4004#define BCE_RXP_CPU_HW_BREAKPOINT 0x000c5034 4005#define BCE_RXP_CPU_HW_BREAKPOINT_DISABLE (1L<<0) 4006#define BCE_RXP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2) 4007 4008#define BCE_RXP_CPU_DEBUG_VECT_PEEK 0x000c5038 4009#define BCE_RXP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) 4010#define BCE_RXP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) 4011#define BCE_RXP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) 4012#define BCE_RXP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) 4013#define BCE_RXP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) 4014#define BCE_RXP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) 4015 4016#define BCE_RXP_CPU_LAST_BRANCH_ADDR 0x000c5048 4017#define BCE_RXP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1) 4018#define BCE_RXP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1) 4019#define BCE_RXP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1) 4020#define BCE_RXP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2) 4021 4022#define BCE_RXP_CPU_REG_FILE 0x000c5200 4023#define BCE_RXP_CFTQ_DATA 0x000c5380 4024#define BCE_RXP_CFTQ_CMD 0x000c53b8 4025#define BCE_RXP_CFTQ_CMD_OFFSET (0x3ffL<<0) 4026#define BCE_RXP_CFTQ_CMD_WR_TOP (1L<<10) 4027#define BCE_RXP_CFTQ_CMD_WR_TOP_0 (0L<<10) 4028#define BCE_RXP_CFTQ_CMD_WR_TOP_1 (1L<<10) 4029#define BCE_RXP_CFTQ_CMD_SFT_RESET (1L<<25) 4030#define BCE_RXP_CFTQ_CMD_RD_DATA (1L<<26) 4031#define BCE_RXP_CFTQ_CMD_ADD_INTERVEN (1L<<27) 4032#define BCE_RXP_CFTQ_CMD_ADD_DATA (1L<<28) 4033#define BCE_RXP_CFTQ_CMD_INTERVENE_CLR (1L<<29) 4034#define BCE_RXP_CFTQ_CMD_POP (1L<<30) 4035#define BCE_RXP_CFTQ_CMD_BUSY (1L<<31) 4036 4037#define BCE_RXP_CFTQ_CTL 0x000c53bc 4038#define BCE_RXP_CFTQ_CTL_INTERVENE (1L<<0) 4039#define BCE_RXP_CFTQ_CTL_OVERFLOW (1L<<1) 4040#define BCE_RXP_CFTQ_CTL_FORCE_INTERVENE (1L<<2) 4041#define BCE_RXP_CFTQ_CTL_MAX_DEPTH (0x3ffL<<12) 4042#define BCE_RXP_CFTQ_CTL_CUR_DEPTH (0x3ffL<<22) 4043 4044#define BCE_RXP_FTQ_DATA 0x000c53c0 4045#define BCE_RXP_FTQ_CMD 0x000c53f8 4046#define BCE_RXP_FTQ_CMD_OFFSET (0x3ffL<<0) 4047#define BCE_RXP_FTQ_CMD_WR_TOP (1L<<10) 4048#define BCE_RXP_FTQ_CMD_WR_TOP_0 (0L<<10) 4049#define BCE_RXP_FTQ_CMD_WR_TOP_1 (1L<<10) 4050#define BCE_RXP_FTQ_CMD_SFT_RESET (1L<<25) 4051#define BCE_RXP_FTQ_CMD_RD_DATA (1L<<26) 4052#define BCE_RXP_FTQ_CMD_ADD_INTERVEN (1L<<27) 4053#define BCE_RXP_FTQ_CMD_ADD_DATA (1L<<28) 4054#define BCE_RXP_FTQ_CMD_INTERVENE_CLR (1L<<29) 4055#define BCE_RXP_FTQ_CMD_POP (1L<<30) 4056#define BCE_RXP_FTQ_CMD_BUSY (1L<<31) 4057 4058#define BCE_RXP_FTQ_CTL 0x000c53fc 4059#define BCE_RXP_FTQ_CTL_INTERVENE (1L<<0) 4060#define BCE_RXP_FTQ_CTL_OVERFLOW (1L<<1) 4061#define BCE_RXP_FTQ_CTL_FORCE_INTERVENE (1L<<2) 4062#define BCE_RXP_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 4063#define BCE_RXP_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 4064 4065#define BCE_RXP_SCRATCH 0x000e0000 4066 4067 4068/* 4069 * com_reg definition 4070 * offset: 0x100000 4071 */ 4072#define BCE_COM_CPU_MODE 0x00105000 4073#define BCE_COM_CPU_MODE_LOCAL_RST (1L<<0) 4074#define BCE_COM_CPU_MODE_STEP_ENA (1L<<1) 4075#define BCE_COM_CPU_MODE_PAGE_0_DATA_ENA (1L<<2) 4076#define BCE_COM_CPU_MODE_PAGE_0_INST_ENA (1L<<3) 4077#define BCE_COM_CPU_MODE_MSG_BIT1 (1L<<6) 4078#define BCE_COM_CPU_MODE_INTERRUPT_ENA (1L<<7) 4079#define BCE_COM_CPU_MODE_SOFT_HALT (1L<<10) 4080#define BCE_COM_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11) 4081#define BCE_COM_CPU_MODE_BAD_INST_HALT_ENA (1L<<12) 4082#define BCE_COM_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13) 4083#define BCE_COM_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15) 4084 4085#define BCE_COM_CPU_STATE 0x00105004 4086#define BCE_COM_CPU_STATE_BREAKPOINT (1L<<0) 4087#define BCE_COM_CPU_STATE_BAD_INST_HALTED (1L<<2) 4088#define BCE_COM_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) 4089#define BCE_COM_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) 4090#define BCE_COM_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) 4091#define BCE_COM_CPU_STATE_BAD_pc_HALTED (1L<<6) 4092#define BCE_COM_CPU_STATE_ALIGN_HALTED (1L<<7) 4093#define BCE_COM_CPU_STATE_FIO_ABORT_HALTED (1L<<8) 4094#define BCE_COM_CPU_STATE_SOFT_HALTED (1L<<10) 4095#define BCE_COM_CPU_STATE_SPAD_UNDERFLOW (1L<<11) 4096#define BCE_COM_CPU_STATE_INTERRRUPT (1L<<12) 4097#define BCE_COM_CPU_STATE_DATA_ACCESS_STALL (1L<<14) 4098#define BCE_COM_CPU_STATE_INST_FETCH_STALL (1L<<15) 4099#define BCE_COM_CPU_STATE_BLOCKED_READ (1L<<31) 4100 4101#define BCE_COM_CPU_EVENT_MASK 0x00105008 4102#define BCE_COM_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) 4103#define BCE_COM_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2) 4104#define BCE_COM_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3) 4105#define BCE_COM_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4) 4106#define BCE_COM_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5) 4107#define BCE_COM_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6) 4108#define BCE_COM_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7) 4109#define BCE_COM_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8) 4110#define BCE_COM_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10) 4111#define BCE_COM_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11) 4112#define BCE_COM_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12) 4113 4114#define BCE_COM_CPU_PROGRAM_COUNTER 0x0010501c 4115#define BCE_COM_CPU_INSTRUCTION 0x00105020 4116#define BCE_COM_CPU_DATA_ACCESS 0x00105024 4117#define BCE_COM_CPU_INTERRUPT_ENABLE 0x00105028 4118#define BCE_COM_CPU_INTERRUPT_VECTOR 0x0010502c 4119#define BCE_COM_CPU_INTERRUPT_SAVED_PC 0x00105030 4120#define BCE_COM_CPU_HW_BREAKPOINT 0x00105034 4121#define BCE_COM_CPU_HW_BREAKPOINT_DISABLE (1L<<0) 4122#define BCE_COM_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2) 4123 4124#define BCE_COM_CPU_DEBUG_VECT_PEEK 0x00105038 4125#define BCE_COM_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) 4126#define BCE_COM_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) 4127#define BCE_COM_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) 4128#define BCE_COM_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) 4129#define BCE_COM_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) 4130#define BCE_COM_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) 4131 4132#define BCE_COM_CPU_LAST_BRANCH_ADDR 0x00105048 4133#define BCE_COM_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1) 4134#define BCE_COM_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1) 4135#define BCE_COM_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1) 4136#define BCE_COM_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2) 4137 4138#define BCE_COM_CPU_REG_FILE 0x00105200 4139#define BCE_COM_COMXQ_FTQ_DATA 0x00105340 4140#define BCE_COM_COMXQ_FTQ_CMD 0x00105378 4141#define BCE_COM_COMXQ_FTQ_CMD_OFFSET (0x3ffL<<0) 4142#define BCE_COM_COMXQ_FTQ_CMD_WR_TOP (1L<<10) 4143#define BCE_COM_COMXQ_FTQ_CMD_WR_TOP_0 (0L<<10) 4144#define BCE_COM_COMXQ_FTQ_CMD_WR_TOP_1 (1L<<10) 4145#define BCE_COM_COMXQ_FTQ_CMD_SFT_RESET (1L<<25) 4146#define BCE_COM_COMXQ_FTQ_CMD_RD_DATA (1L<<26) 4147#define BCE_COM_COMXQ_FTQ_CMD_ADD_INTERVEN (1L<<27) 4148#define BCE_COM_COMXQ_FTQ_CMD_ADD_DATA (1L<<28) 4149#define BCE_COM_COMXQ_FTQ_CMD_INTERVENE_CLR (1L<<29) 4150#define BCE_COM_COMXQ_FTQ_CMD_POP (1L<<30) 4151#define BCE_COM_COMXQ_FTQ_CMD_BUSY (1L<<31) 4152 4153#define BCE_COM_COMXQ_FTQ_CTL 0x0010537c 4154#define BCE_COM_COMXQ_FTQ_CTL_INTERVENE (1L<<0) 4155#define BCE_COM_COMXQ_FTQ_CTL_OVERFLOW (1L<<1) 4156#define BCE_COM_COMXQ_FTQ_CTL_FORCE_INTERVENE (1L<<2) 4157#define BCE_COM_COMXQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 4158#define BCE_COM_COMXQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 4159 4160#define BCE_COM_COMTQ_FTQ_DATA 0x00105380 4161#define BCE_COM_COMTQ_FTQ_CMD 0x001053b8 4162#define BCE_COM_COMTQ_FTQ_CMD_OFFSET (0x3ffL<<0) 4163#define BCE_COM_COMTQ_FTQ_CMD_WR_TOP (1L<<10) 4164#define BCE_COM_COMTQ_FTQ_CMD_WR_TOP_0 (0L<<10) 4165#define BCE_COM_COMTQ_FTQ_CMD_WR_TOP_1 (1L<<10) 4166#define BCE_COM_COMTQ_FTQ_CMD_SFT_RESET (1L<<25) 4167#define BCE_COM_COMTQ_FTQ_CMD_RD_DATA (1L<<26) 4168#define BCE_COM_COMTQ_FTQ_CMD_ADD_INTERVEN (1L<<27) 4169#define BCE_COM_COMTQ_FTQ_CMD_ADD_DATA (1L<<28) 4170#define BCE_COM_COMTQ_FTQ_CMD_INTERVENE_CLR (1L<<29) 4171#define BCE_COM_COMTQ_FTQ_CMD_POP (1L<<30) 4172#define BCE_COM_COMTQ_FTQ_CMD_BUSY (1L<<31) 4173 4174#define BCE_COM_COMTQ_FTQ_CTL 0x001053bc 4175#define BCE_COM_COMTQ_FTQ_CTL_INTERVENE (1L<<0) 4176#define BCE_COM_COMTQ_FTQ_CTL_OVERFLOW (1L<<1) 4177#define BCE_COM_COMTQ_FTQ_CTL_FORCE_INTERVENE (1L<<2) 4178#define BCE_COM_COMTQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 4179#define BCE_COM_COMTQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 4180 4181#define BCE_COM_COMQ_FTQ_DATA 0x001053c0 4182#define BCE_COM_COMQ_FTQ_CMD 0x001053f8 4183#define BCE_COM_COMQ_FTQ_CMD_OFFSET (0x3ffL<<0) 4184#define BCE_COM_COMQ_FTQ_CMD_WR_TOP (1L<<10) 4185#define BCE_COM_COMQ_FTQ_CMD_WR_TOP_0 (0L<<10) 4186#define BCE_COM_COMQ_FTQ_CMD_WR_TOP_1 (1L<<10) 4187#define BCE_COM_COMQ_FTQ_CMD_SFT_RESET (1L<<25) 4188#define BCE_COM_COMQ_FTQ_CMD_RD_DATA (1L<<26) 4189#define BCE_COM_COMQ_FTQ_CMD_ADD_INTERVEN (1L<<27) 4190#define BCE_COM_COMQ_FTQ_CMD_ADD_DATA (1L<<28) 4191#define BCE_COM_COMQ_FTQ_CMD_INTERVENE_CLR (1L<<29) 4192#define BCE_COM_COMQ_FTQ_CMD_POP (1L<<30) 4193#define BCE_COM_COMQ_FTQ_CMD_BUSY (1L<<31) 4194 4195#define BCE_COM_COMQ_FTQ_CTL 0x001053fc 4196#define BCE_COM_COMQ_FTQ_CTL_INTERVENE (1L<<0) 4197#define BCE_COM_COMQ_FTQ_CTL_OVERFLOW (1L<<1) 4198#define BCE_COM_COMQ_FTQ_CTL_FORCE_INTERVENE (1L<<2) 4199#define BCE_COM_COMQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 4200#define BCE_COM_COMQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 4201 4202#define BCE_COM_SCRATCH 0x00120000 4203 4204 4205/* 4206 * cp_reg definition 4207 * offset: 0x180000 4208 */ 4209#define BCE_CP_CPU_MODE 0x00185000 4210#define BCE_CP_CPU_MODE_LOCAL_RST (1L<<0) 4211#define BCE_CP_CPU_MODE_STEP_ENA (1L<<1) 4212#define BCE_CP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2) 4213#define BCE_CP_CPU_MODE_PAGE_0_INST_ENA (1L<<3) 4214#define BCE_CP_CPU_MODE_MSG_BIT1 (1L<<6) 4215#define BCE_CP_CPU_MODE_INTERRUPT_ENA (1L<<7) 4216#define BCE_CP_CPU_MODE_SOFT_HALT (1L<<10) 4217#define BCE_CP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11) 4218#define BCE_CP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12) 4219#define BCE_CP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13) 4220#define BCE_CP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15) 4221 4222#define BCE_CP_CPU_STATE 0x00185004 4223#define BCE_CP_CPU_STATE_BREAKPOINT (1L<<0) 4224#define BCE_CP_CPU_STATE_BAD_INST_HALTED (1L<<2) 4225#define BCE_CP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) 4226#define BCE_CP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) 4227#define BCE_CP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) 4228#define BCE_CP_CPU_STATE_BAD_pc_HALTED (1L<<6) 4229#define BCE_CP_CPU_STATE_ALIGN_HALTED (1L<<7) 4230#define BCE_CP_CPU_STATE_FIO_ABORT_HALTED (1L<<8) 4231#define BCE_CP_CPU_STATE_SOFT_HALTED (1L<<10) 4232#define BCE_CP_CPU_STATE_SPAD_UNDERFLOW (1L<<11) 4233#define BCE_CP_CPU_STATE_INTERRRUPT (1L<<12) 4234#define BCE_CP_CPU_STATE_DATA_ACCESS_STALL (1L<<14) 4235#define BCE_CP_CPU_STATE_INST_FETCH_STALL (1L<<15) 4236#define BCE_CP_CPU_STATE_BLOCKED_READ (1L<<31) 4237 4238#define BCE_CP_CPU_EVENT_MASK 0x00185008 4239#define BCE_CP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) 4240#define BCE_CP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2) 4241#define BCE_CP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3) 4242#define BCE_CP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4) 4243#define BCE_CP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5) 4244#define BCE_CP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6) 4245#define BCE_CP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7) 4246#define BCE_CP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8) 4247#define BCE_CP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10) 4248#define BCE_CP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11) 4249#define BCE_CP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12) 4250 4251#define BCE_CP_CPU_PROGRAM_COUNTER 0x0018501c 4252#define BCE_CP_CPU_INSTRUCTION 0x00185020 4253#define BCE_CP_CPU_DATA_ACCESS 0x00185024 4254#define BCE_CP_CPU_INTERRUPT_ENABLE 0x00185028 4255#define BCE_CP_CPU_INTERRUPT_VECTOR 0x0018502c 4256#define BCE_CP_CPU_INTERRUPT_SAVED_PC 0x00185030 4257#define BCE_CP_CPU_HW_BREAKPOINT 0x00185034 4258#define BCE_CP_CPU_HW_BREAKPOINT_DISABLE (1L<<0) 4259#define BCE_CP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2) 4260 4261#define BCE_CP_CPU_DEBUG_VECT_PEEK 0x00185038 4262#define BCE_CP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) 4263#define BCE_CP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) 4264#define BCE_CP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) 4265#define BCE_CP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) 4266#define BCE_CP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) 4267#define BCE_CP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) 4268 4269#define BCE_CP_CPU_LAST_BRANCH_ADDR 0x00185048 4270#define BCE_CP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1) 4271#define BCE_CP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1) 4272#define BCE_CP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1) 4273#define BCE_CP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2) 4274 4275#define BCE_CP_CPU_REG_FILE 0x00185200 4276#define BCE_CP_CPQ_FTQ_DATA 0x001853c0 4277#define BCE_CP_CPQ_FTQ_CMD 0x001853f8 4278#define BCE_CP_CPQ_FTQ_CMD_OFFSET (0x3ffL<<0) 4279#define BCE_CP_CPQ_FTQ_CMD_WR_TOP (1L<<10) 4280#define BCE_CP_CPQ_FTQ_CMD_WR_TOP_0 (0L<<10) 4281#define BCE_CP_CPQ_FTQ_CMD_WR_TOP_1 (1L<<10) 4282#define BCE_CP_CPQ_FTQ_CMD_SFT_RESET (1L<<25) 4283#define BCE_CP_CPQ_FTQ_CMD_RD_DATA (1L<<26) 4284#define BCE_CP_CPQ_FTQ_CMD_ADD_INTERVEN (1L<<27) 4285#define BCE_CP_CPQ_FTQ_CMD_ADD_DATA (1L<<28) 4286#define BCE_CP_CPQ_FTQ_CMD_INTERVENE_CLR (1L<<29) 4287#define BCE_CP_CPQ_FTQ_CMD_POP (1L<<30) 4288#define BCE_CP_CPQ_FTQ_CMD_BUSY (1L<<31) 4289 4290#define BCE_CP_CPQ_FTQ_CTL 0x001853fc 4291#define BCE_CP_CPQ_FTQ_CTL_INTERVENE (1L<<0) 4292#define BCE_CP_CPQ_FTQ_CTL_OVERFLOW (1L<<1) 4293#define BCE_CP_CPQ_FTQ_CTL_FORCE_INTERVENE (1L<<2) 4294#define BCE_CP_CPQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 4295#define BCE_CP_CPQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 4296 4297#define BCE_CP_SCRATCH 0x001a0000 4298 4299 4300/* 4301 * mcp_reg definition 4302 * offset: 0x140000 4303 */ 4304#define BCE_MCP_CPU_MODE 0x00145000 4305#define BCE_MCP_CPU_MODE_LOCAL_RST (1L<<0) 4306#define BCE_MCP_CPU_MODE_STEP_ENA (1L<<1) 4307#define BCE_MCP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2) 4308#define BCE_MCP_CPU_MODE_PAGE_0_INST_ENA (1L<<3) 4309#define BCE_MCP_CPU_MODE_MSG_BIT1 (1L<<6) 4310#define BCE_MCP_CPU_MODE_INTERRUPT_ENA (1L<<7) 4311#define BCE_MCP_CPU_MODE_SOFT_HALT (1L<<10) 4312#define BCE_MCP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11) 4313#define BCE_MCP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12) 4314#define BCE_MCP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13) 4315#define BCE_MCP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15) 4316 4317#define BCE_MCP_CPU_STATE 0x00145004 4318#define BCE_MCP_CPU_STATE_BREAKPOINT (1L<<0) 4319#define BCE_MCP_CPU_STATE_BAD_INST_HALTED (1L<<2) 4320#define BCE_MCP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) 4321#define BCE_MCP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) 4322#define BCE_MCP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) 4323#define BCE_MCP_CPU_STATE_BAD_pc_HALTED (1L<<6) 4324#define BCE_MCP_CPU_STATE_ALIGN_HALTED (1L<<7) 4325#define BCE_MCP_CPU_STATE_FIO_ABORT_HALTED (1L<<8) 4326#define BCE_MCP_CPU_STATE_SOFT_HALTED (1L<<10) 4327#define BCE_MCP_CPU_STATE_SPAD_UNDERFLOW (1L<<11) 4328#define BCE_MCP_CPU_STATE_INTERRRUPT (1L<<12) 4329#define BCE_MCP_CPU_STATE_DATA_ACCESS_STALL (1L<<14) 4330#define BCE_MCP_CPU_STATE_INST_FETCH_STALL (1L<<15) 4331#define BCE_MCP_CPU_STATE_BLOCKED_READ (1L<<31) 4332 4333#define BCE_MCP_CPU_EVENT_MASK 0x00145008 4334#define BCE_MCP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) 4335#define BCE_MCP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2) 4336#define BCE_MCP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3) 4337#define BCE_MCP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4) 4338#define BCE_MCP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5) 4339#define BCE_MCP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6) 4340#define BCE_MCP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7) 4341#define BCE_MCP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8) 4342#define BCE_MCP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10) 4343#define BCE_MCP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11) 4344#define BCE_MCP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12) 4345 4346#define BCE_MCP_CPU_PROGRAM_COUNTER 0x0014501c 4347#define BCE_MCP_CPU_INSTRUCTION 0x00145020 4348#define BCE_MCP_CPU_DATA_ACCESS 0x00145024 4349#define BCE_MCP_CPU_INTERRUPT_ENABLE 0x00145028 4350#define BCE_MCP_CPU_INTERRUPT_VECTOR 0x0014502c 4351#define BCE_MCP_CPU_INTERRUPT_SAVED_PC 0x00145030 4352#define BCE_MCP_CPU_HW_BREAKPOINT 0x00145034 4353#define BCE_MCP_CPU_HW_BREAKPOINT_DISABLE (1L<<0) 4354#define BCE_MCP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2) 4355 4356#define BCE_MCP_CPU_DEBUG_VECT_PEEK 0x00145038 4357#define BCE_MCP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) 4358#define BCE_MCP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) 4359#define BCE_MCP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) 4360#define BCE_MCP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) 4361#define BCE_MCP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) 4362#define BCE_MCP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) 4363 4364#define BCE_MCP_CPU_LAST_BRANCH_ADDR 0x00145048 4365#define BCE_MCP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1) 4366#define BCE_MCP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1) 4367#define BCE_MCP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1) 4368#define BCE_MCP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2) 4369 4370#define BCE_MCP_CPU_REG_FILE 0x00145200 4371#define BCE_MCP_MCPQ_FTQ_DATA 0x001453c0 4372#define BCE_MCP_MCPQ_FTQ_CMD 0x001453f8 4373#define BCE_MCP_MCPQ_FTQ_CMD_OFFSET (0x3ffL<<0) 4374#define BCE_MCP_MCPQ_FTQ_CMD_WR_TOP (1L<<10) 4375#define BCE_MCP_MCPQ_FTQ_CMD_WR_TOP_0 (0L<<10) 4376#define BCE_MCP_MCPQ_FTQ_CMD_WR_TOP_1 (1L<<10) 4377#define BCE_MCP_MCPQ_FTQ_CMD_SFT_RESET (1L<<25) 4378#define BCE_MCP_MCPQ_FTQ_CMD_RD_DATA (1L<<26) 4379#define BCE_MCP_MCPQ_FTQ_CMD_ADD_INTERVEN (1L<<27) 4380#define BCE_MCP_MCPQ_FTQ_CMD_ADD_DATA (1L<<28) 4381#define BCE_MCP_MCPQ_FTQ_CMD_INTERVENE_CLR (1L<<29) 4382#define BCE_MCP_MCPQ_FTQ_CMD_POP (1L<<30) 4383#define BCE_MCP_MCPQ_FTQ_CMD_BUSY (1L<<31) 4384 4385#define BCE_MCP_MCPQ_FTQ_CTL 0x001453fc 4386#define BCE_MCP_MCPQ_FTQ_CTL_INTERVENE (1L<<0) 4387#define BCE_MCP_MCPQ_FTQ_CTL_OVERFLOW (1L<<1) 4388#define BCE_MCP_MCPQ_FTQ_CTL_FORCE_INTERVENE (1L<<2) 4389#define BCE_MCP_MCPQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 4390#define BCE_MCP_MCPQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 4391 4392#define BCE_MCP_ROM 0x00150000 4393#define BCE_MCP_SCRATCH 0x00160000 4394 4395#define BCE_SHM_HDR_SIGNATURE BCE_MCP_SCRATCH 4396#define BCE_SHM_HDR_SIGNATURE_SIG_MASK 0xffff0000 4397#define BCE_SHM_HDR_SIGNATURE_SIG 0x53530000 4398#define BCE_SHM_HDR_SIGNATURE_VER_MASK 0x000000ff 4399#define BCE_SHM_HDR_SIGNATURE_VER_ONE 0x00000001 4400 4401#define BCE_SHM_HDR_ADDR_0 BCE_MCP_SCRATCH + 4 4402#define BCE_SHM_HDR_ADDR_1 BCE_MCP_SCRATCH + 8 4403 4404/****************************************************************************/ 4405/* End machine generated definitions. */ 4406/****************************************************************************/ 4407 4408#define NUM_MC_HASH_REGISTERS 8 4409 4410 4411/* PHY_ID1: bits 31-16; PHY_ID2: bits 15-0. */ 4412#define PHY_BCM5706_PHY_ID 0x00206160 4413 4414#define PHY_ID(id) ((id) & 0xfffffff0) 4415#define PHY_REV_ID(id) ((id) & 0xf) 4416 4417/* 5708 Serdes PHY registers */ 4418 4419#define BCM5708S_UP1 0xb 4420 4421#define BCM5708S_UP1_2G5 0x1 4422 4423#define BCM5708S_BLK_ADDR 0x1f 4424 4425#define BCM5708S_BLK_ADDR_DIG 0x0000 4426#define BCM5708S_BLK_ADDR_DIG3 0x0002 4427#define BCM5708S_BLK_ADDR_TX_MISC 0x0005 4428 4429/* Digital Block */ 4430#define BCM5708S_1000X_CTL1 0x10 4431 4432#define BCM5708S_1000X_CTL1_FIBER_MODE 0x0001 4433#define BCM5708S_1000X_CTL1_AUTODET_EN 0x0010 4434 4435#define BCM5708S_1000X_CTL2 0x11 4436 4437#define BCM5708S_1000X_CTL2_PLLEL_DET_EN 0x0001 4438 4439#define BCM5708S_1000X_STAT1 0x14 4440 4441#define BCM5708S_1000X_STAT1_SGMII 0x0001 4442#define BCM5708S_1000X_STAT1_LINK 0x0002 4443#define BCM5708S_1000X_STAT1_FD 0x0004 4444#define BCM5708S_1000X_STAT1_SPEED_MASK 0x0018 4445#define BCM5708S_1000X_STAT1_SPEED_10 0x0000 4446#define BCM5708S_1000X_STAT1_SPEED_100 0x0008 4447#define BCM5708S_1000X_STAT1_SPEED_1G 0x0010 4448#define BCM5708S_1000X_STAT1_SPEED_2G5 0x0018 4449#define BCM5708S_1000X_STAT1_TX_PAUSE 0x0020 4450#define BCM5708S_1000X_STAT1_RX_PAUSE 0x0040 4451 4452/* Digital3 Block */ 4453#define BCM5708S_DIG_3_0 0x10 4454 4455#define BCM5708S_DIG_3_0_USE_IEEE 0x0001 4456 4457/* Tx/Misc Block */ 4458#define BCM5708S_TX_ACTL1 0x15 4459 4460#define BCM5708S_TX_ACTL1_DRIVER_VCM 0x30 4461 4462#define BCM5708S_TX_ACTL3 0x17 4463 4464#define RX_COPY_THRESH 92 4465 4466#define DMA_READ_CHANS 5 4467#define DMA_WRITE_CHANS 3 4468 4469/* Use the natural page size of the host CPU. */ 4470/* XXX: This has only been tested on amd64/i386 systems using 4KB pages. */ 4471#define BCM_PAGE_BITS PAGE_SHIFT 4472#define BCM_PAGE_SIZE PAGE_SIZE 4473 4474#define TX_PAGES 2 4475#define TOTAL_TX_BD_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct tx_bd)) 4476#define USABLE_TX_BD_PER_PAGE (TOTAL_TX_BD_PER_PAGE - 1) 4477#define TOTAL_TX_BD (TOTAL_TX_BD_PER_PAGE * TX_PAGES) 4478#define USABLE_TX_BD (USABLE_TX_BD_PER_PAGE * TX_PAGES) 4479#define MAX_TX_BD (TOTAL_TX_BD - 1) 4480 4481#define RX_PAGES 2 4482#define TOTAL_RX_BD_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct rx_bd)) 4483#define USABLE_RX_BD_PER_PAGE (TOTAL_RX_BD_PER_PAGE - 1) 4484#define TOTAL_RX_BD (TOTAL_RX_BD_PER_PAGE * RX_PAGES) 4485#define USABLE_RX_BD (USABLE_RX_BD_PER_PAGE * RX_PAGES) 4486#define MAX_RX_BD (TOTAL_RX_BD - 1) 4487 4488#define NEXT_TX_BD(x) (((x) & USABLE_TX_BD_PER_PAGE) == \ 4489 (USABLE_TX_BD_PER_PAGE - 1)) ? \ 4490 (x) + 2 : (x) + 1 4491 4492#define TX_CHAIN_IDX(x) ((x) & MAX_TX_BD) 4493 4494#define TX_PAGE(x) (((x) & ~USABLE_TX_BD_PER_PAGE) >> 8) 4495#define TX_IDX(x) ((x) & USABLE_TX_BD_PER_PAGE) 4496 4497#define NEXT_RX_BD(x) (((x) & USABLE_RX_BD_PER_PAGE) == \ 4498 (USABLE_RX_BD_PER_PAGE - 1)) ? \ 4499 (x) + 2 : (x) + 1 4500 4501#define RX_CHAIN_IDX(x) ((x) & MAX_RX_BD) 4502 4503#define RX_PAGE(x) (((x) & ~USABLE_RX_BD_PER_PAGE) >> 8) 4504#define RX_IDX(x) ((x) & USABLE_RX_BD_PER_PAGE) 4505 4506/* Context size. */ 4507#define CTX_SHIFT 7 4508#define CTX_SIZE (1 << CTX_SHIFT) 4509#define CTX_MASK (CTX_SIZE - 1) 4510#define GET_CID_ADDR(_cid) ((_cid) << CTX_SHIFT) 4511#define GET_CID(_cid_addr) ((_cid_addr) >> CTX_SHIFT) 4512 4513#define PHY_CTX_SHIFT 6 4514#define PHY_CTX_SIZE (1 << PHY_CTX_SHIFT) 4515#define PHY_CTX_MASK (PHY_CTX_SIZE - 1) 4516#define GET_PCID_ADDR(_pcid) ((_pcid) << PHY_CTX_SHIFT) 4517#define GET_PCID(_pcid_addr) ((_pcid_addr) >> PHY_CTX_SHIFT) 4518 4519#define MB_KERNEL_CTX_SHIFT 8 4520#define MB_KERNEL_CTX_SIZE (1 << MB_KERNEL_CTX_SHIFT) 4521#define MB_KERNEL_CTX_MASK (MB_KERNEL_CTX_SIZE - 1) 4522#define MB_GET_CID_ADDR(_cid) (0x10000 + ((_cid) << MB_KERNEL_CTX_SHIFT)) 4523 4524#define MAX_CID_CNT 0x4000 4525#define MAX_CID_ADDR (GET_CID_ADDR(MAX_CID_CNT)) 4526#define INVALID_CID_ADDR 0xffffffff 4527 4528#define TX_CID 16 4529#define RX_CID 0 4530 4531#define MB_TX_CID_ADDR MB_GET_CID_ADDR(TX_CID) 4532#define MB_RX_CID_ADDR MB_GET_CID_ADDR(RX_CID) 4533 4534/****************************************************************************/ 4535/* BCE Processor Firmwware Load Definitions */ 4536/****************************************************************************/ 4537 4538struct cpu_reg { 4539 u32 mode; 4540 u32 mode_value_halt; 4541 u32 mode_value_sstep; 4542 4543 u32 state; 4544 u32 state_value_clear; 4545 4546 u32 gpr0; 4547 u32 evmask; 4548 u32 pc; 4549 u32 inst; 4550 u32 bp; 4551 4552 u32 spad_base; 4553 4554 u32 mips_view_base; 4555}; 4556 4557struct fw_info { 4558 u32 ver_major; 4559 u32 ver_minor; 4560 u32 ver_fix; 4561 4562 u32 start_addr; 4563 4564 /* Text section. */ 4565 u32 text_addr; 4566 u32 text_len; 4567 u32 text_index; 4568 u32 *text; 4569 4570 /* Data section. */ 4571 u32 data_addr; 4572 u32 data_len; 4573 u32 data_index; 4574 u32 *data; 4575 4576 /* SBSS section. */ 4577 u32 sbss_addr; 4578 u32 sbss_len; 4579 u32 sbss_index; 4580 u32 *sbss; 4581 4582 /* BSS section. */ 4583 u32 bss_addr; 4584 u32 bss_len; 4585 u32 bss_index; 4586 u32 *bss; 4587 4588 /* Read-only section. */ 4589 u32 rodata_addr; 4590 u32 rodata_len; 4591 u32 rodata_index; 4592 u32 *rodata; 4593}; 4594 4595#define RV2P_PROC1 0 4596#define RV2P_PROC2 1 4597 4598#define BCE_MIREG(x) ((x & 0x1F) << 16) 4599#define BCE_MIPHY(x) ((x & 0x1F) << 21) 4600#define BCE_PHY_TIMEOUT 50 4601 4602#define BCE_NVRAM_SIZE 0x200 4603#define BCE_NVRAM_MAGIC 0x669955aa 4604#define BCE_CRC32_RESIDUAL 0xdebb20e3 4605 4606#define BCE_TX_TIMEOUT 5 4607 4608#define BCE_MAX_SEGMENTS 32 4609#define BCE_TSO_MAX_SIZE 65536 4610#define BCE_TSO_MAX_SEG_SIZE 4096 4611 4612#define BCE_DMA_ALIGN 8 4613#define BCE_DMA_BOUNDARY 0 4614 4615/* The BCM5708 has a problem with addresses greater that 40bits. */ 4616/* Handle the sizing issue in an architecture agnostic fashion. */ 4617#if (BUS_SPACE_MAXADDR < 0xFFFFFFFFFF) 4618#define BCE_BUS_SPACE_MAXADDR BUS_SPACE_MAXADDR 4619#else 4620#define BCE_BUS_SPACE_MAXADDR 0xFFFFFFFFFF 4621#endif 4622 4623/* 4624 * XXX Checksum offload involving IP fragments seems to cause problems on 4625 * transmit. Disable it for now, hopefully there will be a more elegant 4626 * solution later. 4627 */ 4628#ifdef BCE_IP_CSUM 4629#define BCE_IF_HWASSIST (CSUM_IP | CSUM_TCP | CSUM_UDP) 4630#else 4631#define BCE_IF_HWASSIST (CSUM_TCP | CSUM_UDP) 4632#endif 4633 4634#if __FreeBSD_version < 700000 4635#define BCE_IF_CAPABILITIES (IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 4636 IFCAP_HWCSUM | IFCAP_JUMBO_MTU) 4637#else 4638#define BCE_IF_CAPABILITIES (IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 4639 IFCAP_HWCSUM | IFCAP_JUMBO_MTU | IFCAP_VLAN_HWCSUM) 4640#endif 4641 4642#define BCE_MIN_MTU 60 4643#define BCE_MIN_ETHER_MTU 64 4644 4645#define BCE_MAX_STD_MTU 1500 4646#define BCE_MAX_STD_ETHER_MTU 1518 4647#define BCE_MAX_STD_ETHER_MTU_VLAN 1522 4648 4649#define BCE_MAX_JUMBO_MTU 9000 4650#define BCE_MAX_JUMBO_ETHER_MTU 9018 4651#define BCE_MAX_JUMBO_ETHER_MTU_VLAN 9022 4652 4653// #define BCE_MAX_MTU ETHER_MAX_LEN_JUMBO + ETHER_VLAN_ENCAP_LEN /* 9022 */ 4654 4655/****************************************************************************/ 4656/* BCE Device State Data Structure */ 4657/****************************************************************************/ 4658 4659#define BCE_STATUS_BLK_SZ sizeof(struct status_block) 4660#define BCE_STATS_BLK_SZ sizeof(struct statistics_block) 4661#define BCE_TX_CHAIN_PAGE_SZ BCM_PAGE_SIZE 4662#define BCE_RX_CHAIN_PAGE_SZ BCM_PAGE_SIZE 4663 4664struct bce_softc 4665{ 4666 /* MUST start with ifnet pointer (see definition of miibus_statchg()) */ 4667 struct ifnet *bce_ifp; /* Interface info */ 4668 device_t bce_dev; /* Parent device handle */ 4669 u_int8_t bce_unit; /* Interface number */ 4670 struct resource *bce_res_mem; /* Device resource handle */ 4671 struct ifmedia bce_ifmedia; /* TBI media info */ 4672 bus_space_tag_t bce_btag; /* Device bus tag */ 4673 bus_space_handle_t bce_bhandle; /* Device bus handle */ 4674 vm_offset_t bce_vhandle; /* Device virtual memory handle */ 4675 struct resource *bce_res_irq; /* IRQ Resource Handle */ 4676 struct mtx bce_mtx; /* Mutex */ 4677 void *bce_intrhand; /* Interrupt handler */ 4678 4679 /* ASIC Chip ID. */ 4680 u32 bce_chipid; 4681 4682 /* General controller flags. */ 4683 u32 bce_flags; 4684#define BCE_PCIX_FLAG 0x01 4685#define BCE_PCI_32BIT_FLAG 0x02 4686#define BCE_ONE_TDMA_FLAG 0x04 /* Deprecated */ 4687#define BCE_NO_WOL_FLAG 0x08 4688#define BCE_USING_DAC_FLAG 0x10 4689#define BCE_USING_MSI_FLAG 0x20 4690#define BCE_MFW_ENABLE_FLAG 0x40 /* Management F/W is enabled */ 4691 4692 /* PHY specific flags. */ 4693 u32 bce_phy_flags; 4694#define BCE_PHY_SERDES_FLAG 0x001 4695#define BCE_PHY_CRC_FIX_FLAG 0x002 4696#define BCE_PHY_PARALLEL_DETECT_FLAG 0x004 4697#define BCE_PHY_2_5G_CAPABLE_FLAG 0x008 4698#define BCE_PHY_INT_MODE_MASK_FLAG 0x300 4699#define BCE_PHY_INT_MODE_AUTO_POLLING_FLAG 0x100 4700#define BCE_PHY_INT_MODE_LINK_READY_FLAG 0x200 4701 4702 bus_addr_t max_bus_addr; 4703 u16 bus_speed_mhz; /* PCI bus speed */ 4704 struct flash_spec *bce_flash_info; /* Flash NVRAM settings */ 4705 u32 bce_flash_size; /* Flash NVRAM size */ 4706 u32 bce_shmem_base; /* Shared Memory base address */ 4707 char * bce_name; /* Name string */ 4708 4709 /* Tracks the version of bootcode firmware. */ 4710 u32 bce_fw_ver; 4711 4712 /* Tracks the state of the firmware. 0 = Running while any */ 4713 /* other value indicates that the firmware is not responding. */ 4714 u16 bce_fw_timed_out; 4715 4716 /* An incrementing sequence used to coordinate messages passed */ 4717 /* from the driver to the firmware. */ 4718 u16 bce_fw_wr_seq; 4719 4720 /* An incrementing sequence used to let the firmware know that */ 4721 /* the driver is still operating. Without the pulse, management */ 4722 /* firmware such as IPMI or UMP will operate in OS absent state. */ 4723 u16 bce_fw_drv_pulse_wr_seq; 4724 4725 /* Ethernet MAC address. */ 4726 u_char eaddr[6]; 4727 4728 /* These setting are used by the host coalescing (HC) block to */ 4729 /* to control how often the status block, statistics block and */ 4730 /* interrupts are generated. */ 4731 u16 bce_tx_quick_cons_trip_int; 4732 u16 bce_tx_quick_cons_trip; 4733 u16 bce_rx_quick_cons_trip_int; 4734 u16 bce_rx_quick_cons_trip; 4735 u16 bce_comp_prod_trip_int; 4736 u16 bce_comp_prod_trip; 4737 u16 bce_tx_ticks_int; 4738 u16 bce_tx_ticks; 4739 u16 bce_rx_ticks_int; 4740 u16 bce_rx_ticks; 4741 u16 bce_com_ticks_int; 4742 u16 bce_com_ticks; 4743 u16 bce_cmd_ticks_int; 4744 u16 bce_cmd_ticks; 4745 u32 bce_stats_ticks; 4746 4747 /* The address of the integrated PHY on the MII bus. */ 4748 int bce_phy_addr; 4749 4750 /* The device handle for the MII bus child device. */ 4751 device_t bce_miibus; 4752 4753 /* Driver maintained TX chain pointers and byte counter. */ 4754 u16 rx_prod; 4755 u16 rx_cons; 4756 u32 rx_prod_bseq; /* Counts the bytes used. */ 4757 u16 tx_prod; 4758 u16 tx_cons; 4759 u32 tx_prod_bseq; /* Counts the bytes used. */ 4760 4761 int bce_link; 4762 struct callout bce_stat_ch; 4763 4764 int watchdog_timer; /* ticks until chip reset */ 4765 4766 /* Frame size and mbuf allocation size for RX frames. */ 4767 u32 max_frame_size; 4768 int mbuf_alloc_size; 4769 4770 /* Receive mode settings (i.e promiscuous, multicast, etc.). */ 4771 u32 rx_mode; 4772 4773#ifdef DEVICE_POLLING 4774 int bce_rxcycles; /* Counter for receive polling cycles */ 4775#endif 4776 4777 /* Bus tag for the bce controller. */ 4778 bus_dma_tag_t parent_tag; 4779 4780 /* H/W maintained TX buffer descriptor chain structure. */ 4781 bus_dma_tag_t tx_bd_chain_tag; 4782 bus_dmamap_t tx_bd_chain_map[TX_PAGES]; 4783 struct tx_bd *tx_bd_chain[TX_PAGES]; 4784 bus_addr_t tx_bd_chain_paddr[TX_PAGES]; 4785 4786 /* H/W maintained RX buffer descriptor chain structure. */ 4787 bus_dma_tag_t rx_bd_chain_tag; 4788 bus_dmamap_t rx_bd_chain_map[RX_PAGES]; 4789 struct rx_bd *rx_bd_chain[RX_PAGES]; 4790 bus_addr_t rx_bd_chain_paddr[RX_PAGES]; 4791 4792 /* H/W maintained status block. */ 4793 bus_dma_tag_t status_tag; 4794 bus_dmamap_t status_map; 4795 struct status_block *status_block; /* virtual address */ 4796 bus_addr_t status_block_paddr; /* Physical address */ 4797 4798 /* Driver maintained status block values. */ 4799 u16 last_status_idx; 4800 u16 hw_rx_cons; 4801 u16 hw_tx_cons; 4802 4803 /* H/W maintained statistics block. */ 4804 bus_dma_tag_t stats_tag; 4805 bus_dmamap_t stats_map; 4806 struct statistics_block *stats_block; /* Virtual address */ 4807 bus_addr_t stats_block_paddr; /* Physical address */ 4808 4809 /* Bus tag for RX/TX mbufs. */ 4810 bus_dma_tag_t rx_mbuf_tag; 4811 bus_dma_tag_t tx_mbuf_tag; 4812 4813 /* S/W maintained mbuf TX chain structure. */ 4814 bus_dmamap_t tx_mbuf_map[TOTAL_TX_BD]; 4815 struct mbuf *tx_mbuf_ptr[TOTAL_TX_BD]; 4816 4817 /* S/W maintained mbuf RX chain structure. */ 4818 bus_dmamap_t rx_mbuf_map[TOTAL_RX_BD]; 4819 struct mbuf *rx_mbuf_ptr[TOTAL_RX_BD]; 4820 4821 /* Track the number of rx_bd and tx_bd's in use. */ 4822 u16 free_rx_bd; 4823 u16 max_rx_bd; 4824 u16 used_tx_bd; 4825 u16 max_tx_bd; 4826 4827 /* Provides access to hardware statistics through sysctl. */ 4828 u64 stat_IfHCInOctets; 4829 u64 stat_IfHCInBadOctets; 4830 u64 stat_IfHCOutOctets; 4831 u64 stat_IfHCOutBadOctets; 4832 u64 stat_IfHCInUcastPkts; 4833 u64 stat_IfHCInMulticastPkts; 4834 u64 stat_IfHCInBroadcastPkts; 4835 u64 stat_IfHCOutUcastPkts; 4836 u64 stat_IfHCOutMulticastPkts; 4837 u64 stat_IfHCOutBroadcastPkts; 4838 4839 u32 stat_emac_tx_stat_dot3statsinternalmactransmiterrors; 4840 u32 stat_Dot3StatsCarrierSenseErrors; 4841 u32 stat_Dot3StatsFCSErrors; 4842 u32 stat_Dot3StatsAlignmentErrors; 4843 u32 stat_Dot3StatsSingleCollisionFrames; 4844 u32 stat_Dot3StatsMultipleCollisionFrames; 4845 u32 stat_Dot3StatsDeferredTransmissions; 4846 u32 stat_Dot3StatsExcessiveCollisions; 4847 u32 stat_Dot3StatsLateCollisions; 4848 u32 stat_EtherStatsCollisions; 4849 u32 stat_EtherStatsFragments; 4850 u32 stat_EtherStatsJabbers; 4851 u32 stat_EtherStatsUndersizePkts; 4852 u32 stat_EtherStatsOverrsizePkts; 4853 u32 stat_EtherStatsPktsRx64Octets; 4854 u32 stat_EtherStatsPktsRx65Octetsto127Octets; 4855 u32 stat_EtherStatsPktsRx128Octetsto255Octets; 4856 u32 stat_EtherStatsPktsRx256Octetsto511Octets; 4857 u32 stat_EtherStatsPktsRx512Octetsto1023Octets; 4858 u32 stat_EtherStatsPktsRx1024Octetsto1522Octets; 4859 u32 stat_EtherStatsPktsRx1523Octetsto9022Octets; 4860 u32 stat_EtherStatsPktsTx64Octets; 4861 u32 stat_EtherStatsPktsTx65Octetsto127Octets; 4862 u32 stat_EtherStatsPktsTx128Octetsto255Octets; 4863 u32 stat_EtherStatsPktsTx256Octetsto511Octets; 4864 u32 stat_EtherStatsPktsTx512Octetsto1023Octets; 4865 u32 stat_EtherStatsPktsTx1024Octetsto1522Octets; 4866 u32 stat_EtherStatsPktsTx1523Octetsto9022Octets; 4867 u32 stat_XonPauseFramesReceived; 4868 u32 stat_XoffPauseFramesReceived; 4869 u32 stat_OutXonSent; 4870 u32 stat_OutXoffSent; 4871 u32 stat_FlowControlDone; 4872 u32 stat_MacControlFramesReceived; 4873 u32 stat_XoffStateEntered; 4874 u32 stat_IfInFramesL2FilterDiscards; 4875 u32 stat_IfInRuleCheckerDiscards; 4876 u32 stat_IfInFTQDiscards; 4877 u32 stat_IfInMBUFDiscards; 4878 u32 stat_IfInRuleCheckerP4Hit; 4879 u32 stat_CatchupInRuleCheckerDiscards; 4880 u32 stat_CatchupInFTQDiscards; 4881 u32 stat_CatchupInMBUFDiscards; 4882 u32 stat_CatchupInRuleCheckerP4Hit; 4883 4884 /* Provides access to certain firmware statistics. */ 4885 u32 com_no_buffers; 4886 4887#ifdef BCE_DEBUG 4888 /* Track the number of enqueued mbufs. */ 4889 int tx_mbuf_alloc; 4890 int rx_mbuf_alloc; 4891 4892 /* Track how many and what type of interrupts are generated. */ 4893 u32 interrupts_generated; 4894 u32 interrupts_handled; 4895 u32 rx_interrupts; 4896 u32 tx_interrupts; 4897 4898 u32 rx_low_watermark; /* Lowest number of rx_bd's free. */ 4899 u32 rx_empty_count; /* Number of times the RX chain was empty. */ 4900 u32 tx_hi_watermark; /* Greatest number of tx_bd's used. */ 4901 u32 tx_full_count; /* Number of times the TX chain was full. */ 4902 u32 mbuf_alloc_failed; /* Mbuf allocation failure counter. */ 4903 u32 l2fhdr_status_errors; 4904 u32 unexpected_attentions; 4905 u32 lost_status_block_updates; 4906 4907 u32 requested_tso_frames; /* Number of TSO frames enqueued. */ 4908#endif 4909}; 4910 4911#endif /* #ifndef _BCE_H_DEFINED */ 4912