if_bce.c revision 257307
1/*- 2 * Copyright (c) 2006-2010 Broadcom Corporation 3 * David Christensen <davidch@broadcom.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. Neither the name of Broadcom Corporation nor the name of its contributors 15 * may be used to endorse or promote products derived from this software 16 * without specific prior written consent. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 28 * THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#include <sys/cdefs.h> 32__FBSDID("$FreeBSD: head/sys/dev/bce/if_bce.c 257307 2013-10-29 06:37:27Z yongari $"); 33 34/* 35 * The following controllers are supported by this driver: 36 * BCM5706C A2, A3 37 * BCM5706S A2, A3 38 * BCM5708C B1, B2 39 * BCM5708S B1, B2 40 * BCM5709C A1, C0 41 * BCM5709S A1, C0 42 * BCM5716C C0 43 * BCM5716S C0 44 * 45 * The following controllers are not supported by this driver: 46 * BCM5706C A0, A1 (pre-production) 47 * BCM5706S A0, A1 (pre-production) 48 * BCM5708C A0, B0 (pre-production) 49 * BCM5708S A0, B0 (pre-production) 50 * BCM5709C A0 B0, B1, B2 (pre-production) 51 * BCM5709S A0, B0, B1, B2 (pre-production) 52 */ 53 54#include "opt_bce.h" 55 56#include <sys/param.h> 57#include <sys/endian.h> 58#include <sys/systm.h> 59#include <sys/sockio.h> 60#include <sys/lock.h> 61#include <sys/mbuf.h> 62#include <sys/malloc.h> 63#include <sys/mutex.h> 64#include <sys/kernel.h> 65#include <sys/module.h> 66#include <sys/socket.h> 67#include <sys/sysctl.h> 68#include <sys/queue.h> 69 70#include <net/bpf.h> 71#include <net/ethernet.h> 72#include <net/if.h> 73#include <net/if_var.h> 74#include <net/if_arp.h> 75#include <net/if_dl.h> 76#include <net/if_media.h> 77 78#include <net/if_types.h> 79#include <net/if_vlan_var.h> 80 81#include <netinet/in_systm.h> 82#include <netinet/in.h> 83#include <netinet/if_ether.h> 84#include <netinet/ip.h> 85#include <netinet/ip6.h> 86#include <netinet/tcp.h> 87#include <netinet/udp.h> 88 89#include <machine/bus.h> 90#include <machine/resource.h> 91#include <sys/bus.h> 92#include <sys/rman.h> 93 94#include <dev/mii/mii.h> 95#include <dev/mii/miivar.h> 96#include "miidevs.h" 97#include <dev/mii/brgphyreg.h> 98 99#include <dev/pci/pcireg.h> 100#include <dev/pci/pcivar.h> 101 102#include "miibus_if.h" 103 104#include <dev/bce/if_bcereg.h> 105#include <dev/bce/if_bcefw.h> 106 107/****************************************************************************/ 108/* BCE Debug Options */ 109/****************************************************************************/ 110#ifdef BCE_DEBUG 111 u32 bce_debug = BCE_WARN; 112 113 /* 0 = Never */ 114 /* 1 = 1 in 2,147,483,648 */ 115 /* 256 = 1 in 8,388,608 */ 116 /* 2048 = 1 in 1,048,576 */ 117 /* 65536 = 1 in 32,768 */ 118 /* 1048576 = 1 in 2,048 */ 119 /* 268435456 = 1 in 8 */ 120 /* 536870912 = 1 in 4 */ 121 /* 1073741824 = 1 in 2 */ 122 123 /* Controls how often the l2_fhdr frame error check will fail. */ 124 int l2fhdr_error_sim_control = 0; 125 126 /* Controls how often the unexpected attention check will fail. */ 127 int unexpected_attention_sim_control = 0; 128 129 /* Controls how often to simulate an mbuf allocation failure. */ 130 int mbuf_alloc_failed_sim_control = 0; 131 132 /* Controls how often to simulate a DMA mapping failure. */ 133 int dma_map_addr_failed_sim_control = 0; 134 135 /* Controls how often to simulate a bootcode failure. */ 136 int bootcode_running_failure_sim_control = 0; 137#endif 138 139/****************************************************************************/ 140/* PCI Device ID Table */ 141/* */ 142/* Used by bce_probe() to identify the devices supported by this driver. */ 143/****************************************************************************/ 144#define BCE_DEVDESC_MAX 64 145 146static const struct bce_type bce_devs[] = { 147 /* BCM5706C Controllers and OEM boards. */ 148 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3101, 149 "HP NC370T Multifunction Gigabit Server Adapter" }, 150 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3106, 151 "HP NC370i Multifunction Gigabit Server Adapter" }, 152 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3070, 153 "HP NC380T PCIe DP Multifunc Gig Server Adapter" }, 154 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x1709, 155 "HP NC371i Multifunction Gigabit Server Adapter" }, 156 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, PCI_ANY_ID, PCI_ANY_ID, 157 "Broadcom NetXtreme II BCM5706 1000Base-T" }, 158 159 /* BCM5706S controllers and OEM boards. */ 160 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, HP_VENDORID, 0x3102, 161 "HP NC370F Multifunction Gigabit Server Adapter" }, 162 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, PCI_ANY_ID, PCI_ANY_ID, 163 "Broadcom NetXtreme II BCM5706 1000Base-SX" }, 164 165 /* BCM5708C controllers and OEM boards. */ 166 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7037, 167 "HP NC373T PCIe Multifunction Gig Server Adapter" }, 168 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7038, 169 "HP NC373i Multifunction Gigabit Server Adapter" }, 170 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7045, 171 "HP NC374m PCIe Multifunction Adapter" }, 172 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, PCI_ANY_ID, PCI_ANY_ID, 173 "Broadcom NetXtreme II BCM5708 1000Base-T" }, 174 175 /* BCM5708S controllers and OEM boards. */ 176 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x1706, 177 "HP NC373m Multifunction Gigabit Server Adapter" }, 178 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x703b, 179 "HP NC373i Multifunction Gigabit Server Adapter" }, 180 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x703d, 181 "HP NC373F PCIe Multifunc Giga Server Adapter" }, 182 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, PCI_ANY_ID, PCI_ANY_ID, 183 "Broadcom NetXtreme II BCM5708 1000Base-SX" }, 184 185 /* BCM5709C controllers and OEM boards. */ 186 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, HP_VENDORID, 0x7055, 187 "HP NC382i DP Multifunction Gigabit Server Adapter" }, 188 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, HP_VENDORID, 0x7059, 189 "HP NC382T PCIe DP Multifunction Gigabit Server Adapter" }, 190 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, PCI_ANY_ID, PCI_ANY_ID, 191 "Broadcom NetXtreme II BCM5709 1000Base-T" }, 192 193 /* BCM5709S controllers and OEM boards. */ 194 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, HP_VENDORID, 0x171d, 195 "HP NC382m DP 1GbE Multifunction BL-c Adapter" }, 196 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, HP_VENDORID, 0x7056, 197 "HP NC382i DP Multifunction Gigabit Server Adapter" }, 198 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, PCI_ANY_ID, PCI_ANY_ID, 199 "Broadcom NetXtreme II BCM5709 1000Base-SX" }, 200 201 /* BCM5716 controllers and OEM boards. */ 202 { BRCM_VENDORID, BRCM_DEVICEID_BCM5716, PCI_ANY_ID, PCI_ANY_ID, 203 "Broadcom NetXtreme II BCM5716 1000Base-T" }, 204 205 { 0, 0, 0, 0, NULL } 206}; 207 208 209/****************************************************************************/ 210/* Supported Flash NVRAM device data. */ 211/****************************************************************************/ 212static const struct flash_spec flash_table[] = 213{ 214#define BUFFERED_FLAGS (BCE_NV_BUFFERED | BCE_NV_TRANSLATE) 215#define NONBUFFERED_FLAGS (BCE_NV_WREN) 216 217 /* Slow EEPROM */ 218 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400, 219 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 220 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 221 "EEPROM - slow"}, 222 /* Expansion entry 0001 */ 223 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406, 224 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 225 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 226 "Entry 0001"}, 227 /* Saifun SA25F010 (non-buffered flash) */ 228 /* strap, cfg1, & write1 need updates */ 229 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406, 230 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 231 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2, 232 "Non-buffered flash (128kB)"}, 233 /* Saifun SA25F020 (non-buffered flash) */ 234 /* strap, cfg1, & write1 need updates */ 235 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406, 236 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 237 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4, 238 "Non-buffered flash (256kB)"}, 239 /* Expansion entry 0100 */ 240 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406, 241 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 242 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 243 "Entry 0100"}, 244 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */ 245 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406, 246 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 247 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2, 248 "Entry 0101: ST M45PE10 (128kB non-bufferred)"}, 249 /* Entry 0110: ST M45PE20 (non-buffered flash)*/ 250 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406, 251 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 252 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4, 253 "Entry 0110: ST M45PE20 (256kB non-bufferred)"}, 254 /* Saifun SA25F005 (non-buffered flash) */ 255 /* strap, cfg1, & write1 need updates */ 256 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406, 257 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 258 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE, 259 "Non-buffered flash (64kB)"}, 260 /* Fast EEPROM */ 261 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400, 262 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 263 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 264 "EEPROM - fast"}, 265 /* Expansion entry 1001 */ 266 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406, 267 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 268 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 269 "Entry 1001"}, 270 /* Expansion entry 1010 */ 271 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406, 272 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 273 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 274 "Entry 1010"}, 275 /* ATMEL AT45DB011B (buffered flash) */ 276 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400, 277 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 278 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE, 279 "Buffered flash (128kB)"}, 280 /* Expansion entry 1100 */ 281 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406, 282 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 283 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 284 "Entry 1100"}, 285 /* Expansion entry 1101 */ 286 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406, 287 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 288 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 289 "Entry 1101"}, 290 /* Ateml Expansion entry 1110 */ 291 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400, 292 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 293 BUFFERED_FLASH_BYTE_ADDR_MASK, 0, 294 "Entry 1110 (Atmel)"}, 295 /* ATMEL AT45DB021B (buffered flash) */ 296 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400, 297 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 298 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2, 299 "Buffered flash (256kB)"}, 300}; 301 302/* 303 * The BCM5709 controllers transparently handle the 304 * differences between Atmel 264 byte pages and all 305 * flash devices which use 256 byte pages, so no 306 * logical-to-physical mapping is required in the 307 * driver. 308 */ 309static const struct flash_spec flash_5709 = { 310 .flags = BCE_NV_BUFFERED, 311 .page_bits = BCM5709_FLASH_PAGE_BITS, 312 .page_size = BCM5709_FLASH_PAGE_SIZE, 313 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK, 314 .total_size = BUFFERED_FLASH_TOTAL_SIZE * 2, 315 .name = "5709/5716 buffered flash (256kB)", 316}; 317 318 319/****************************************************************************/ 320/* FreeBSD device entry points. */ 321/****************************************************************************/ 322static int bce_probe (device_t); 323static int bce_attach (device_t); 324static int bce_detach (device_t); 325static int bce_shutdown (device_t); 326 327 328/****************************************************************************/ 329/* BCE Debug Data Structure Dump Routines */ 330/****************************************************************************/ 331#ifdef BCE_DEBUG 332static u32 bce_reg_rd (struct bce_softc *, u32); 333static void bce_reg_wr (struct bce_softc *, u32, u32); 334static void bce_reg_wr16 (struct bce_softc *, u32, u16); 335static u32 bce_ctx_rd (struct bce_softc *, u32, u32); 336static void bce_dump_enet (struct bce_softc *, struct mbuf *); 337static void bce_dump_mbuf (struct bce_softc *, struct mbuf *); 338static void bce_dump_tx_mbuf_chain (struct bce_softc *, u16, int); 339static void bce_dump_rx_mbuf_chain (struct bce_softc *, u16, int); 340static void bce_dump_pg_mbuf_chain (struct bce_softc *, u16, int); 341static void bce_dump_txbd (struct bce_softc *, 342 int, struct tx_bd *); 343static void bce_dump_rxbd (struct bce_softc *, 344 int, struct rx_bd *); 345static void bce_dump_pgbd (struct bce_softc *, 346 int, struct rx_bd *); 347static void bce_dump_l2fhdr (struct bce_softc *, 348 int, struct l2_fhdr *); 349static void bce_dump_ctx (struct bce_softc *, u16); 350static void bce_dump_ftqs (struct bce_softc *); 351static void bce_dump_tx_chain (struct bce_softc *, u16, int); 352static void bce_dump_rx_bd_chain (struct bce_softc *, u16, int); 353static void bce_dump_pg_chain (struct bce_softc *, u16, int); 354static void bce_dump_status_block (struct bce_softc *); 355static void bce_dump_stats_block (struct bce_softc *); 356static void bce_dump_driver_state (struct bce_softc *); 357static void bce_dump_hw_state (struct bce_softc *); 358static void bce_dump_shmem_state (struct bce_softc *); 359static void bce_dump_mq_regs (struct bce_softc *); 360static void bce_dump_bc_state (struct bce_softc *); 361static void bce_dump_txp_state (struct bce_softc *, int); 362static void bce_dump_rxp_state (struct bce_softc *, int); 363static void bce_dump_tpat_state (struct bce_softc *, int); 364static void bce_dump_cp_state (struct bce_softc *, int); 365static void bce_dump_com_state (struct bce_softc *, int); 366static void bce_dump_rv2p_state (struct bce_softc *); 367static void bce_breakpoint (struct bce_softc *); 368#endif /*BCE_DEBUG */ 369 370 371/****************************************************************************/ 372/* BCE Register/Memory Access Routines */ 373/****************************************************************************/ 374static u32 bce_reg_rd_ind (struct bce_softc *, u32); 375static void bce_reg_wr_ind (struct bce_softc *, u32, u32); 376static void bce_shmem_wr (struct bce_softc *, u32, u32); 377static u32 bce_shmem_rd (struct bce_softc *, u32); 378static void bce_ctx_wr (struct bce_softc *, u32, u32, u32); 379static int bce_miibus_read_reg (device_t, int, int); 380static int bce_miibus_write_reg (device_t, int, int, int); 381static void bce_miibus_statchg (device_t); 382 383#ifdef BCE_DEBUG 384static int bce_sysctl_nvram_dump(SYSCTL_HANDLER_ARGS); 385#ifdef BCE_NVRAM_WRITE_SUPPORT 386static int bce_sysctl_nvram_write(SYSCTL_HANDLER_ARGS); 387#endif 388#endif 389 390/****************************************************************************/ 391/* BCE NVRAM Access Routines */ 392/****************************************************************************/ 393static int bce_acquire_nvram_lock (struct bce_softc *); 394static int bce_release_nvram_lock (struct bce_softc *); 395static void bce_enable_nvram_access(struct bce_softc *); 396static void bce_disable_nvram_access(struct bce_softc *); 397static int bce_nvram_read_dword (struct bce_softc *, u32, u8 *, u32); 398static int bce_init_nvram (struct bce_softc *); 399static int bce_nvram_read (struct bce_softc *, u32, u8 *, int); 400static int bce_nvram_test (struct bce_softc *); 401#ifdef BCE_NVRAM_WRITE_SUPPORT 402static int bce_enable_nvram_write (struct bce_softc *); 403static void bce_disable_nvram_write(struct bce_softc *); 404static int bce_nvram_erase_page (struct bce_softc *, u32); 405static int bce_nvram_write_dword (struct bce_softc *, u32, u8 *, u32); 406static int bce_nvram_write (struct bce_softc *, u32, u8 *, int); 407#endif 408 409/****************************************************************************/ 410/* */ 411/****************************************************************************/ 412static void bce_get_rx_buffer_sizes(struct bce_softc *, int); 413static void bce_get_media (struct bce_softc *); 414static void bce_init_media (struct bce_softc *); 415static u32 bce_get_rphy_link (struct bce_softc *); 416static void bce_dma_map_addr (void *, bus_dma_segment_t *, int, int); 417static int bce_dma_alloc (device_t); 418static void bce_dma_free (struct bce_softc *); 419static void bce_release_resources (struct bce_softc *); 420 421/****************************************************************************/ 422/* BCE Firmware Synchronization and Load */ 423/****************************************************************************/ 424static void bce_fw_cap_init (struct bce_softc *); 425static int bce_fw_sync (struct bce_softc *, u32); 426static void bce_load_rv2p_fw (struct bce_softc *, const u32 *, u32, 427 u32); 428static void bce_load_cpu_fw (struct bce_softc *, 429 struct cpu_reg *, struct fw_info *); 430static void bce_start_cpu (struct bce_softc *, struct cpu_reg *); 431static void bce_halt_cpu (struct bce_softc *, struct cpu_reg *); 432static void bce_start_rxp_cpu (struct bce_softc *); 433static void bce_init_rxp_cpu (struct bce_softc *); 434static void bce_init_txp_cpu (struct bce_softc *); 435static void bce_init_tpat_cpu (struct bce_softc *); 436static void bce_init_cp_cpu (struct bce_softc *); 437static void bce_init_com_cpu (struct bce_softc *); 438static void bce_init_cpus (struct bce_softc *); 439 440static void bce_print_adapter_info (struct bce_softc *); 441static void bce_probe_pci_caps (device_t, struct bce_softc *); 442static void bce_stop (struct bce_softc *); 443static int bce_reset (struct bce_softc *, u32); 444static int bce_chipinit (struct bce_softc *); 445static int bce_blockinit (struct bce_softc *); 446 447static int bce_init_tx_chain (struct bce_softc *); 448static void bce_free_tx_chain (struct bce_softc *); 449 450static int bce_get_rx_buf (struct bce_softc *, u16, u16, u32 *); 451static int bce_init_rx_chain (struct bce_softc *); 452static void bce_fill_rx_chain (struct bce_softc *); 453static void bce_free_rx_chain (struct bce_softc *); 454 455static int bce_get_pg_buf (struct bce_softc *, u16, u16); 456static int bce_init_pg_chain (struct bce_softc *); 457static void bce_fill_pg_chain (struct bce_softc *); 458static void bce_free_pg_chain (struct bce_softc *); 459 460static struct mbuf *bce_tso_setup (struct bce_softc *, 461 struct mbuf **, u16 *); 462static int bce_tx_encap (struct bce_softc *, struct mbuf **); 463static void bce_start_locked (struct ifnet *); 464static void bce_start (struct ifnet *); 465static int bce_ioctl (struct ifnet *, u_long, caddr_t); 466static void bce_watchdog (struct bce_softc *); 467static int bce_ifmedia_upd (struct ifnet *); 468static int bce_ifmedia_upd_locked (struct ifnet *); 469static void bce_ifmedia_sts (struct ifnet *, struct ifmediareq *); 470static void bce_ifmedia_sts_rphy (struct bce_softc *, struct ifmediareq *); 471static void bce_init_locked (struct bce_softc *); 472static void bce_init (void *); 473static void bce_mgmt_init_locked (struct bce_softc *sc); 474 475static int bce_init_ctx (struct bce_softc *); 476static void bce_get_mac_addr (struct bce_softc *); 477static void bce_set_mac_addr (struct bce_softc *); 478static void bce_phy_intr (struct bce_softc *); 479static inline u16 bce_get_hw_rx_cons (struct bce_softc *); 480static void bce_rx_intr (struct bce_softc *); 481static void bce_tx_intr (struct bce_softc *); 482static void bce_disable_intr (struct bce_softc *); 483static void bce_enable_intr (struct bce_softc *, int); 484 485static void bce_intr (void *); 486static void bce_set_rx_mode (struct bce_softc *); 487static void bce_stats_update (struct bce_softc *); 488static void bce_tick (void *); 489static void bce_pulse (void *); 490static void bce_add_sysctls (struct bce_softc *); 491 492 493/****************************************************************************/ 494/* FreeBSD device dispatch table. */ 495/****************************************************************************/ 496static device_method_t bce_methods[] = { 497 /* Device interface (device_if.h) */ 498 DEVMETHOD(device_probe, bce_probe), 499 DEVMETHOD(device_attach, bce_attach), 500 DEVMETHOD(device_detach, bce_detach), 501 DEVMETHOD(device_shutdown, bce_shutdown), 502/* Supported by device interface but not used here. */ 503/* DEVMETHOD(device_identify, bce_identify), */ 504/* DEVMETHOD(device_suspend, bce_suspend), */ 505/* DEVMETHOD(device_resume, bce_resume), */ 506/* DEVMETHOD(device_quiesce, bce_quiesce), */ 507 508 /* MII interface (miibus_if.h) */ 509 DEVMETHOD(miibus_readreg, bce_miibus_read_reg), 510 DEVMETHOD(miibus_writereg, bce_miibus_write_reg), 511 DEVMETHOD(miibus_statchg, bce_miibus_statchg), 512/* Supported by MII interface but not used here. */ 513/* DEVMETHOD(miibus_linkchg, bce_miibus_linkchg), */ 514/* DEVMETHOD(miibus_mediainit, bce_miibus_mediainit), */ 515 516 DEVMETHOD_END 517}; 518 519static driver_t bce_driver = { 520 "bce", 521 bce_methods, 522 sizeof(struct bce_softc) 523}; 524 525static devclass_t bce_devclass; 526 527MODULE_DEPEND(bce, pci, 1, 1, 1); 528MODULE_DEPEND(bce, ether, 1, 1, 1); 529MODULE_DEPEND(bce, miibus, 1, 1, 1); 530 531DRIVER_MODULE(bce, pci, bce_driver, bce_devclass, NULL, NULL); 532DRIVER_MODULE(miibus, bce, miibus_driver, miibus_devclass, NULL, NULL); 533 534 535/****************************************************************************/ 536/* Tunable device values */ 537/****************************************************************************/ 538static SYSCTL_NODE(_hw, OID_AUTO, bce, CTLFLAG_RD, 0, "bce driver parameters"); 539 540/* Allowable values are TRUE or FALSE */ 541static int bce_verbose = TRUE; 542TUNABLE_INT("hw.bce.verbose", &bce_verbose); 543SYSCTL_INT(_hw_bce, OID_AUTO, verbose, CTLFLAG_RDTUN, &bce_verbose, 0, 544 "Verbose output enable/disable"); 545 546/* Allowable values are TRUE or FALSE */ 547static int bce_tso_enable = TRUE; 548TUNABLE_INT("hw.bce.tso_enable", &bce_tso_enable); 549SYSCTL_INT(_hw_bce, OID_AUTO, tso_enable, CTLFLAG_RDTUN, &bce_tso_enable, 0, 550 "TSO Enable/Disable"); 551 552/* Allowable values are 0 (IRQ), 1 (MSI/IRQ), and 2 (MSI-X/MSI/IRQ) */ 553/* ToDo: Add MSI-X support. */ 554static int bce_msi_enable = 1; 555TUNABLE_INT("hw.bce.msi_enable", &bce_msi_enable); 556SYSCTL_INT(_hw_bce, OID_AUTO, msi_enable, CTLFLAG_RDTUN, &bce_msi_enable, 0, 557 "MSI-X|MSI|INTx selector"); 558 559/* Allowable values are 1, 2, 4, 8. */ 560static int bce_rx_pages = DEFAULT_RX_PAGES; 561TUNABLE_INT("hw.bce.rx_pages", &bce_rx_pages); 562SYSCTL_UINT(_hw_bce, OID_AUTO, rx_pages, CTLFLAG_RDTUN, &bce_rx_pages, 0, 563 "Receive buffer descriptor pages (1 page = 255 buffer descriptors)"); 564 565/* Allowable values are 1, 2, 4, 8. */ 566static int bce_tx_pages = DEFAULT_TX_PAGES; 567TUNABLE_INT("hw.bce.tx_pages", &bce_tx_pages); 568SYSCTL_UINT(_hw_bce, OID_AUTO, tx_pages, CTLFLAG_RDTUN, &bce_tx_pages, 0, 569 "Transmit buffer descriptor pages (1 page = 255 buffer descriptors)"); 570 571/* Allowable values are TRUE or FALSE. */ 572static int bce_hdr_split = TRUE; 573TUNABLE_INT("hw.bce.hdr_split", &bce_hdr_split); 574SYSCTL_UINT(_hw_bce, OID_AUTO, hdr_split, CTLFLAG_RDTUN, &bce_hdr_split, 0, 575 "Frame header/payload splitting Enable/Disable"); 576 577/* Allowable values are TRUE or FALSE. */ 578static int bce_strict_rx_mtu = FALSE; 579TUNABLE_INT("hw.bce.strict_rx_mtu", &bce_strict_rx_mtu); 580SYSCTL_UINT(_hw_bce, OID_AUTO, strict_rx_mtu, CTLFLAG_RDTUN, 581 &bce_strict_rx_mtu, 0, 582 "Enable/Disable strict RX frame size checking"); 583 584/* Allowable values are 0 ... 100 */ 585#ifdef BCE_DEBUG 586/* Generate 1 interrupt for every transmit completion. */ 587static int bce_tx_quick_cons_trip_int = 1; 588#else 589/* Generate 1 interrupt for every 20 transmit completions. */ 590static int bce_tx_quick_cons_trip_int = DEFAULT_TX_QUICK_CONS_TRIP_INT; 591#endif 592TUNABLE_INT("hw.bce.tx_quick_cons_trip_int", &bce_tx_quick_cons_trip_int); 593SYSCTL_UINT(_hw_bce, OID_AUTO, tx_quick_cons_trip_int, CTLFLAG_RDTUN, 594 &bce_tx_quick_cons_trip_int, 0, 595 "Transmit BD trip point during interrupts"); 596 597/* Allowable values are 0 ... 100 */ 598/* Generate 1 interrupt for every transmit completion. */ 599#ifdef BCE_DEBUG 600static int bce_tx_quick_cons_trip = 1; 601#else 602/* Generate 1 interrupt for every 20 transmit completions. */ 603static int bce_tx_quick_cons_trip = DEFAULT_TX_QUICK_CONS_TRIP; 604#endif 605TUNABLE_INT("hw.bce.tx_quick_cons_trip", &bce_tx_quick_cons_trip); 606SYSCTL_UINT(_hw_bce, OID_AUTO, tx_quick_cons_trip, CTLFLAG_RDTUN, 607 &bce_tx_quick_cons_trip, 0, 608 "Transmit BD trip point"); 609 610/* Allowable values are 0 ... 100 */ 611#ifdef BCE_DEBUG 612/* Generate an interrupt if 0us have elapsed since the last TX completion. */ 613static int bce_tx_ticks_int = 0; 614#else 615/* Generate an interrupt if 80us have elapsed since the last TX completion. */ 616static int bce_tx_ticks_int = DEFAULT_TX_TICKS_INT; 617#endif 618TUNABLE_INT("hw.bce.tx_ticks_int", &bce_tx_ticks_int); 619SYSCTL_UINT(_hw_bce, OID_AUTO, tx_ticks_int, CTLFLAG_RDTUN, 620 &bce_tx_ticks_int, 0, "Transmit ticks count during interrupt"); 621 622/* Allowable values are 0 ... 100 */ 623#ifdef BCE_DEBUG 624/* Generate an interrupt if 0us have elapsed since the last TX completion. */ 625static int bce_tx_ticks = 0; 626#else 627/* Generate an interrupt if 80us have elapsed since the last TX completion. */ 628static int bce_tx_ticks = DEFAULT_TX_TICKS; 629#endif 630TUNABLE_INT("hw.bce.tx_ticks", &bce_tx_ticks); 631SYSCTL_UINT(_hw_bce, OID_AUTO, tx_ticks, CTLFLAG_RDTUN, 632 &bce_tx_ticks, 0, "Transmit ticks count"); 633 634/* Allowable values are 1 ... 100 */ 635#ifdef BCE_DEBUG 636/* Generate 1 interrupt for every received frame. */ 637static int bce_rx_quick_cons_trip_int = 1; 638#else 639/* Generate 1 interrupt for every 6 received frames. */ 640static int bce_rx_quick_cons_trip_int = DEFAULT_RX_QUICK_CONS_TRIP_INT; 641#endif 642TUNABLE_INT("hw.bce.rx_quick_cons_trip_int", &bce_rx_quick_cons_trip_int); 643SYSCTL_UINT(_hw_bce, OID_AUTO, rx_quick_cons_trip_int, CTLFLAG_RDTUN, 644 &bce_rx_quick_cons_trip_int, 0, 645 "Receive BD trip point duirng interrupts"); 646 647/* Allowable values are 1 ... 100 */ 648#ifdef BCE_DEBUG 649/* Generate 1 interrupt for every received frame. */ 650static int bce_rx_quick_cons_trip = 1; 651#else 652/* Generate 1 interrupt for every 6 received frames. */ 653static int bce_rx_quick_cons_trip = DEFAULT_RX_QUICK_CONS_TRIP; 654#endif 655TUNABLE_INT("hw.bce.rx_quick_cons_trip", &bce_rx_quick_cons_trip); 656SYSCTL_UINT(_hw_bce, OID_AUTO, rx_quick_cons_trip, CTLFLAG_RDTUN, 657 &bce_rx_quick_cons_trip, 0, 658 "Receive BD trip point"); 659 660/* Allowable values are 0 ... 100 */ 661#ifdef BCE_DEBUG 662/* Generate an int. if 0us have elapsed since the last received frame. */ 663static int bce_rx_ticks_int = 0; 664#else 665/* Generate an int. if 18us have elapsed since the last received frame. */ 666static int bce_rx_ticks_int = DEFAULT_RX_TICKS_INT; 667#endif 668TUNABLE_INT("hw.bce.rx_ticks_int", &bce_rx_ticks_int); 669SYSCTL_UINT(_hw_bce, OID_AUTO, rx_ticks_int, CTLFLAG_RDTUN, 670 &bce_rx_ticks_int, 0, "Receive ticks count during interrupt"); 671 672/* Allowable values are 0 ... 100 */ 673#ifdef BCE_DEBUG 674/* Generate an int. if 0us have elapsed since the last received frame. */ 675static int bce_rx_ticks = 0; 676#else 677/* Generate an int. if 18us have elapsed since the last received frame. */ 678static int bce_rx_ticks = DEFAULT_RX_TICKS; 679#endif 680TUNABLE_INT("hw.bce.rx_ticks", &bce_rx_ticks); 681SYSCTL_UINT(_hw_bce, OID_AUTO, rx_ticks, CTLFLAG_RDTUN, 682 &bce_rx_ticks, 0, "Receive ticks count"); 683 684 685/****************************************************************************/ 686/* Device probe function. */ 687/* */ 688/* Compares the device to the driver's list of supported devices and */ 689/* reports back to the OS whether this is the right driver for the device. */ 690/* */ 691/* Returns: */ 692/* BUS_PROBE_DEFAULT on success, positive value on failure. */ 693/****************************************************************************/ 694static int 695bce_probe(device_t dev) 696{ 697 const struct bce_type *t; 698 struct bce_softc *sc; 699 char *descbuf; 700 u16 vid = 0, did = 0, svid = 0, sdid = 0; 701 702 t = bce_devs; 703 704 sc = device_get_softc(dev); 705 sc->bce_unit = device_get_unit(dev); 706 sc->bce_dev = dev; 707 708 /* Get the data for the device to be probed. */ 709 vid = pci_get_vendor(dev); 710 did = pci_get_device(dev); 711 svid = pci_get_subvendor(dev); 712 sdid = pci_get_subdevice(dev); 713 714 DBPRINT(sc, BCE_EXTREME_LOAD, 715 "%s(); VID = 0x%04X, DID = 0x%04X, SVID = 0x%04X, " 716 "SDID = 0x%04X\n", __FUNCTION__, vid, did, svid, sdid); 717 718 /* Look through the list of known devices for a match. */ 719 while(t->bce_name != NULL) { 720 721 if ((vid == t->bce_vid) && (did == t->bce_did) && 722 ((svid == t->bce_svid) || (t->bce_svid == PCI_ANY_ID)) && 723 ((sdid == t->bce_sdid) || (t->bce_sdid == PCI_ANY_ID))) { 724 725 descbuf = malloc(BCE_DEVDESC_MAX, M_TEMP, M_NOWAIT); 726 727 if (descbuf == NULL) 728 return(ENOMEM); 729 730 /* Print out the device identity. */ 731 snprintf(descbuf, BCE_DEVDESC_MAX, "%s (%c%d)", 732 t->bce_name, (((pci_read_config(dev, 733 PCIR_REVID, 4) & 0xf0) >> 4) + 'A'), 734 (pci_read_config(dev, PCIR_REVID, 4) & 0xf)); 735 736 device_set_desc_copy(dev, descbuf); 737 free(descbuf, M_TEMP); 738 return(BUS_PROBE_DEFAULT); 739 } 740 t++; 741 } 742 743 return(ENXIO); 744} 745 746 747/****************************************************************************/ 748/* PCI Capabilities Probe Function. */ 749/* */ 750/* Walks the PCI capabiites list for the device to find what features are */ 751/* supported. */ 752/* */ 753/* Returns: */ 754/* None. */ 755/****************************************************************************/ 756static void 757bce_print_adapter_info(struct bce_softc *sc) 758{ 759 int i = 0; 760 761 DBENTER(BCE_VERBOSE_LOAD); 762 763 if (bce_verbose || bootverbose) { 764 BCE_PRINTF("ASIC (0x%08X); ", sc->bce_chipid); 765 printf("Rev (%c%d); ", ((BCE_CHIP_ID(sc) & 0xf000) >> 766 12) + 'A', ((BCE_CHIP_ID(sc) & 0x0ff0) >> 4)); 767 768 769 /* Bus info. */ 770 if (sc->bce_flags & BCE_PCIE_FLAG) { 771 printf("Bus (PCIe x%d, ", sc->link_width); 772 switch (sc->link_speed) { 773 case 1: printf("2.5Gbps); "); break; 774 case 2: printf("5Gbps); "); break; 775 default: printf("Unknown link speed); "); 776 } 777 } else { 778 printf("Bus (PCI%s, %s, %dMHz); ", 779 ((sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : ""), 780 ((sc->bce_flags & BCE_PCI_32BIT_FLAG) ? 781 "32-bit" : "64-bit"), sc->bus_speed_mhz); 782 } 783 784 /* Firmware version and device features. */ 785 printf("B/C (%s); Bufs (RX:%d;TX:%d;PG:%d); Flags (", 786 sc->bce_bc_ver, sc->rx_pages, sc->tx_pages, 787 (bce_hdr_split == TRUE ? sc->pg_pages: 0)); 788 789 if (bce_hdr_split == TRUE) { 790 printf("SPLT"); 791 i++; 792 } 793 794 if (sc->bce_flags & BCE_USING_MSI_FLAG) { 795 if (i > 0) printf("|"); 796 printf("MSI"); i++; 797 } 798 799 if (sc->bce_flags & BCE_USING_MSIX_FLAG) { 800 if (i > 0) printf("|"); 801 printf("MSI-X"); i++; 802 } 803 804 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) { 805 if (i > 0) printf("|"); 806 printf("2.5G"); i++; 807 } 808 809 if (sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) { 810 if (i > 0) printf("|"); 811 printf("Remote PHY(%s)", 812 sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG ? 813 "FIBER" : "TP"); i++; 814 } 815 816 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 817 if (i > 0) printf("|"); 818 printf("MFW); MFW (%s)\n", sc->bce_mfw_ver); 819 } else { 820 printf(")\n"); 821 } 822 823 printf("Coal (RX:%d,%d,%d,%d; TX:%d,%d,%d,%d)\n", 824 sc->bce_rx_quick_cons_trip_int, 825 sc->bce_rx_quick_cons_trip, 826 sc->bce_rx_ticks_int, 827 sc->bce_rx_ticks, 828 sc->bce_tx_quick_cons_trip_int, 829 sc->bce_tx_quick_cons_trip, 830 sc->bce_tx_ticks_int, 831 sc->bce_tx_ticks); 832 833 } 834 835 DBEXIT(BCE_VERBOSE_LOAD); 836} 837 838 839/****************************************************************************/ 840/* PCI Capabilities Probe Function. */ 841/* */ 842/* Walks the PCI capabiites list for the device to find what features are */ 843/* supported. */ 844/* */ 845/* Returns: */ 846/* None. */ 847/****************************************************************************/ 848static void 849bce_probe_pci_caps(device_t dev, struct bce_softc *sc) 850{ 851 u32 reg; 852 853 DBENTER(BCE_VERBOSE_LOAD); 854 855 /* Check if PCI-X capability is enabled. */ 856 if (pci_find_cap(dev, PCIY_PCIX, ®) == 0) { 857 if (reg != 0) 858 sc->bce_cap_flags |= BCE_PCIX_CAPABLE_FLAG; 859 } 860 861 /* Check if PCIe capability is enabled. */ 862 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) { 863 if (reg != 0) { 864 u16 link_status = pci_read_config(dev, reg + 0x12, 2); 865 DBPRINT(sc, BCE_INFO_LOAD, "PCIe link_status = " 866 "0x%08X\n", link_status); 867 sc->link_speed = link_status & 0xf; 868 sc->link_width = (link_status >> 4) & 0x3f; 869 sc->bce_cap_flags |= BCE_PCIE_CAPABLE_FLAG; 870 sc->bce_flags |= BCE_PCIE_FLAG; 871 } 872 } 873 874 /* Check if MSI capability is enabled. */ 875 if (pci_find_cap(dev, PCIY_MSI, ®) == 0) { 876 if (reg != 0) 877 sc->bce_cap_flags |= BCE_MSI_CAPABLE_FLAG; 878 } 879 880 /* Check if MSI-X capability is enabled. */ 881 if (pci_find_cap(dev, PCIY_MSIX, ®) == 0) { 882 if (reg != 0) 883 sc->bce_cap_flags |= BCE_MSIX_CAPABLE_FLAG; 884 } 885 886 DBEXIT(BCE_VERBOSE_LOAD); 887} 888 889 890/****************************************************************************/ 891/* Load and validate user tunable settings. */ 892/* */ 893/* Returns: */ 894/* Nothing. */ 895/****************************************************************************/ 896static void 897bce_set_tunables(struct bce_softc *sc) 898{ 899 /* Set sysctl values for RX page count. */ 900 switch (bce_rx_pages) { 901 case 1: 902 /* fall-through */ 903 case 2: 904 /* fall-through */ 905 case 4: 906 /* fall-through */ 907 case 8: 908 sc->rx_pages = bce_rx_pages; 909 break; 910 default: 911 sc->rx_pages = DEFAULT_RX_PAGES; 912 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 913 "hw.bce.rx_pages! Setting default of %d.\n", 914 __FILE__, __LINE__, bce_rx_pages, DEFAULT_RX_PAGES); 915 } 916 917 /* ToDo: Consider allowing user setting for pg_pages. */ 918 sc->pg_pages = min((sc->rx_pages * 4), MAX_PG_PAGES); 919 920 /* Set sysctl values for TX page count. */ 921 switch (bce_tx_pages) { 922 case 1: 923 /* fall-through */ 924 case 2: 925 /* fall-through */ 926 case 4: 927 /* fall-through */ 928 case 8: 929 sc->tx_pages = bce_tx_pages; 930 break; 931 default: 932 sc->tx_pages = DEFAULT_TX_PAGES; 933 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 934 "hw.bce.tx_pages! Setting default of %d.\n", 935 __FILE__, __LINE__, bce_tx_pages, DEFAULT_TX_PAGES); 936 } 937 938 /* 939 * Validate the TX trip point (i.e. the number of 940 * TX completions before a status block update is 941 * generated and an interrupt is asserted. 942 */ 943 if (bce_tx_quick_cons_trip_int <= 100) { 944 sc->bce_tx_quick_cons_trip_int = 945 bce_tx_quick_cons_trip_int; 946 } else { 947 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 948 "hw.bce.tx_quick_cons_trip_int! Setting default of %d.\n", 949 __FILE__, __LINE__, bce_tx_quick_cons_trip_int, 950 DEFAULT_TX_QUICK_CONS_TRIP_INT); 951 sc->bce_tx_quick_cons_trip_int = 952 DEFAULT_TX_QUICK_CONS_TRIP_INT; 953 } 954 955 if (bce_tx_quick_cons_trip <= 100) { 956 sc->bce_tx_quick_cons_trip = 957 bce_tx_quick_cons_trip; 958 } else { 959 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 960 "hw.bce.tx_quick_cons_trip! Setting default of %d.\n", 961 __FILE__, __LINE__, bce_tx_quick_cons_trip, 962 DEFAULT_TX_QUICK_CONS_TRIP); 963 sc->bce_tx_quick_cons_trip = 964 DEFAULT_TX_QUICK_CONS_TRIP; 965 } 966 967 /* 968 * Validate the TX ticks count (i.e. the maximum amount 969 * of time to wait after the last TX completion has 970 * occurred before a status block update is generated 971 * and an interrupt is asserted. 972 */ 973 if (bce_tx_ticks_int <= 100) { 974 sc->bce_tx_ticks_int = 975 bce_tx_ticks_int; 976 } else { 977 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 978 "hw.bce.tx_ticks_int! Setting default of %d.\n", 979 __FILE__, __LINE__, bce_tx_ticks_int, 980 DEFAULT_TX_TICKS_INT); 981 sc->bce_tx_ticks_int = 982 DEFAULT_TX_TICKS_INT; 983 } 984 985 if (bce_tx_ticks <= 100) { 986 sc->bce_tx_ticks = 987 bce_tx_ticks; 988 } else { 989 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 990 "hw.bce.tx_ticks! Setting default of %d.\n", 991 __FILE__, __LINE__, bce_tx_ticks, 992 DEFAULT_TX_TICKS); 993 sc->bce_tx_ticks = 994 DEFAULT_TX_TICKS; 995 } 996 997 /* 998 * Validate the RX trip point (i.e. the number of 999 * RX frames received before a status block update is 1000 * generated and an interrupt is asserted. 1001 */ 1002 if (bce_rx_quick_cons_trip_int <= 100) { 1003 sc->bce_rx_quick_cons_trip_int = 1004 bce_rx_quick_cons_trip_int; 1005 } else { 1006 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 1007 "hw.bce.rx_quick_cons_trip_int! Setting default of %d.\n", 1008 __FILE__, __LINE__, bce_rx_quick_cons_trip_int, 1009 DEFAULT_RX_QUICK_CONS_TRIP_INT); 1010 sc->bce_rx_quick_cons_trip_int = 1011 DEFAULT_RX_QUICK_CONS_TRIP_INT; 1012 } 1013 1014 if (bce_rx_quick_cons_trip <= 100) { 1015 sc->bce_rx_quick_cons_trip = 1016 bce_rx_quick_cons_trip; 1017 } else { 1018 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 1019 "hw.bce.rx_quick_cons_trip! Setting default of %d.\n", 1020 __FILE__, __LINE__, bce_rx_quick_cons_trip, 1021 DEFAULT_RX_QUICK_CONS_TRIP); 1022 sc->bce_rx_quick_cons_trip = 1023 DEFAULT_RX_QUICK_CONS_TRIP; 1024 } 1025 1026 /* 1027 * Validate the RX ticks count (i.e. the maximum amount 1028 * of time to wait after the last RX frame has been 1029 * received before a status block update is generated 1030 * and an interrupt is asserted. 1031 */ 1032 if (bce_rx_ticks_int <= 100) { 1033 sc->bce_rx_ticks_int = bce_rx_ticks_int; 1034 } else { 1035 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 1036 "hw.bce.rx_ticks_int! Setting default of %d.\n", 1037 __FILE__, __LINE__, bce_rx_ticks_int, 1038 DEFAULT_RX_TICKS_INT); 1039 sc->bce_rx_ticks_int = DEFAULT_RX_TICKS_INT; 1040 } 1041 1042 if (bce_rx_ticks <= 100) { 1043 sc->bce_rx_ticks = bce_rx_ticks; 1044 } else { 1045 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 1046 "hw.bce.rx_ticks! Setting default of %d.\n", 1047 __FILE__, __LINE__, bce_rx_ticks, 1048 DEFAULT_RX_TICKS); 1049 sc->bce_rx_ticks = DEFAULT_RX_TICKS; 1050 } 1051 1052 /* Disabling both RX ticks and RX trips will prevent interrupts. */ 1053 if ((bce_rx_quick_cons_trip == 0) && (bce_rx_ticks == 0)) { 1054 BCE_PRINTF("%s(%d): Cannot set both hw.bce.rx_ticks and " 1055 "hw.bce.rx_quick_cons_trip to 0. Setting default values.\n", 1056 __FILE__, __LINE__); 1057 sc->bce_rx_ticks = DEFAULT_RX_TICKS; 1058 sc->bce_rx_quick_cons_trip = DEFAULT_RX_QUICK_CONS_TRIP; 1059 } 1060 1061 /* Disabling both TX ticks and TX trips will prevent interrupts. */ 1062 if ((bce_tx_quick_cons_trip == 0) && (bce_tx_ticks == 0)) { 1063 BCE_PRINTF("%s(%d): Cannot set both hw.bce.tx_ticks and " 1064 "hw.bce.tx_quick_cons_trip to 0. Setting default values.\n", 1065 __FILE__, __LINE__); 1066 sc->bce_tx_ticks = DEFAULT_TX_TICKS; 1067 sc->bce_tx_quick_cons_trip = DEFAULT_TX_QUICK_CONS_TRIP; 1068 } 1069} 1070 1071 1072/****************************************************************************/ 1073/* Device attach function. */ 1074/* */ 1075/* Allocates device resources, performs secondary chip identification, */ 1076/* resets and initializes the hardware, and initializes driver instance */ 1077/* variables. */ 1078/* */ 1079/* Returns: */ 1080/* 0 on success, positive value on failure. */ 1081/****************************************************************************/ 1082static int 1083bce_attach(device_t dev) 1084{ 1085 struct bce_softc *sc; 1086 struct ifnet *ifp; 1087 u32 val; 1088 int count, error, rc = 0, rid; 1089 1090 sc = device_get_softc(dev); 1091 sc->bce_dev = dev; 1092 1093 DBENTER(BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 1094 1095 sc->bce_unit = device_get_unit(dev); 1096 1097 /* Set initial device and PHY flags */ 1098 sc->bce_flags = 0; 1099 sc->bce_phy_flags = 0; 1100 1101 bce_set_tunables(sc); 1102 1103 pci_enable_busmaster(dev); 1104 1105 /* Allocate PCI memory resources. */ 1106 rid = PCIR_BAR(0); 1107 sc->bce_res_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1108 &rid, RF_ACTIVE); 1109 1110 if (sc->bce_res_mem == NULL) { 1111 BCE_PRINTF("%s(%d): PCI memory allocation failed\n", 1112 __FILE__, __LINE__); 1113 rc = ENXIO; 1114 goto bce_attach_fail; 1115 } 1116 1117 /* Get various resource handles. */ 1118 sc->bce_btag = rman_get_bustag(sc->bce_res_mem); 1119 sc->bce_bhandle = rman_get_bushandle(sc->bce_res_mem); 1120 sc->bce_vhandle = (vm_offset_t) rman_get_virtual(sc->bce_res_mem); 1121 1122 bce_probe_pci_caps(dev, sc); 1123 1124 rid = 1; 1125 count = 0; 1126#if 0 1127 /* Try allocating MSI-X interrupts. */ 1128 if ((sc->bce_cap_flags & BCE_MSIX_CAPABLE_FLAG) && 1129 (bce_msi_enable >= 2) && 1130 ((sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1131 &rid, RF_ACTIVE)) != NULL)) { 1132 1133 msi_needed = count = 1; 1134 1135 if (((error = pci_alloc_msix(dev, &count)) != 0) || 1136 (count != msi_needed)) { 1137 BCE_PRINTF("%s(%d): MSI-X allocation failed! Requested = %d," 1138 "Received = %d, error = %d\n", __FILE__, __LINE__, 1139 msi_needed, count, error); 1140 count = 0; 1141 pci_release_msi(dev); 1142 bus_release_resource(dev, SYS_RES_MEMORY, rid, 1143 sc->bce_res_irq); 1144 sc->bce_res_irq = NULL; 1145 } else { 1146 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using MSI-X interrupt.\n", 1147 __FUNCTION__); 1148 sc->bce_flags |= BCE_USING_MSIX_FLAG; 1149 } 1150 } 1151#endif 1152 1153 /* Try allocating a MSI interrupt. */ 1154 if ((sc->bce_cap_flags & BCE_MSI_CAPABLE_FLAG) && 1155 (bce_msi_enable >= 1) && (count == 0)) { 1156 count = 1; 1157 if ((error = pci_alloc_msi(dev, &count)) != 0) { 1158 BCE_PRINTF("%s(%d): MSI allocation failed! " 1159 "error = %d\n", __FILE__, __LINE__, error); 1160 count = 0; 1161 pci_release_msi(dev); 1162 } else { 1163 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using MSI " 1164 "interrupt.\n", __FUNCTION__); 1165 sc->bce_flags |= BCE_USING_MSI_FLAG; 1166 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) 1167 sc->bce_flags |= BCE_ONE_SHOT_MSI_FLAG; 1168 rid = 1; 1169 } 1170 } 1171 1172 /* Try allocating a legacy interrupt. */ 1173 if (count == 0) { 1174 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using INTx interrupt.\n", 1175 __FUNCTION__); 1176 rid = 0; 1177 } 1178 1179 sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 1180 &rid, RF_ACTIVE | (count != 0 ? 0 : RF_SHAREABLE)); 1181 1182 /* Report any IRQ allocation errors. */ 1183 if (sc->bce_res_irq == NULL) { 1184 BCE_PRINTF("%s(%d): PCI map interrupt failed!\n", 1185 __FILE__, __LINE__); 1186 rc = ENXIO; 1187 goto bce_attach_fail; 1188 } 1189 1190 /* Initialize mutex for the current device instance. */ 1191 BCE_LOCK_INIT(sc, device_get_nameunit(dev)); 1192 1193 /* 1194 * Configure byte swap and enable indirect register access. 1195 * Rely on CPU to do target byte swapping on big endian systems. 1196 * Access to registers outside of PCI configurtion space are not 1197 * valid until this is done. 1198 */ 1199 pci_write_config(dev, BCE_PCICFG_MISC_CONFIG, 1200 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 1201 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP, 4); 1202 1203 /* Save ASIC revsion info. */ 1204 sc->bce_chipid = REG_RD(sc, BCE_MISC_ID); 1205 1206 /* Weed out any non-production controller revisions. */ 1207 switch(BCE_CHIP_ID(sc)) { 1208 case BCE_CHIP_ID_5706_A0: 1209 case BCE_CHIP_ID_5706_A1: 1210 case BCE_CHIP_ID_5708_A0: 1211 case BCE_CHIP_ID_5708_B0: 1212 case BCE_CHIP_ID_5709_A0: 1213 case BCE_CHIP_ID_5709_B0: 1214 case BCE_CHIP_ID_5709_B1: 1215 case BCE_CHIP_ID_5709_B2: 1216 BCE_PRINTF("%s(%d): Unsupported controller " 1217 "revision (%c%d)!\n", __FILE__, __LINE__, 1218 (((pci_read_config(dev, PCIR_REVID, 4) & 1219 0xf0) >> 4) + 'A'), (pci_read_config(dev, 1220 PCIR_REVID, 4) & 0xf)); 1221 rc = ENODEV; 1222 goto bce_attach_fail; 1223 } 1224 1225 /* 1226 * The embedded PCIe to PCI-X bridge (EPB) 1227 * in the 5708 cannot address memory above 1228 * 40 bits (E7_5708CB1_23043 & E6_5708SB1_23043). 1229 */ 1230 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708) 1231 sc->max_bus_addr = BCE_BUS_SPACE_MAXADDR; 1232 else 1233 sc->max_bus_addr = BUS_SPACE_MAXADDR; 1234 1235 /* 1236 * Find the base address for shared memory access. 1237 * Newer versions of bootcode use a signature and offset 1238 * while older versions use a fixed address. 1239 */ 1240 val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE); 1241 if ((val & BCE_SHM_HDR_SIGNATURE_SIG_MASK) == BCE_SHM_HDR_SIGNATURE_SIG) 1242 /* Multi-port devices use different offsets in shared memory. */ 1243 sc->bce_shmem_base = REG_RD_IND(sc, BCE_SHM_HDR_ADDR_0 + 1244 (pci_get_function(sc->bce_dev) << 2)); 1245 else 1246 sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE; 1247 1248 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): bce_shmem_base = 0x%08X\n", 1249 __FUNCTION__, sc->bce_shmem_base); 1250 1251 /* Fetch the bootcode revision. */ 1252 val = bce_shmem_rd(sc, BCE_DEV_INFO_BC_REV); 1253 for (int i = 0, j = 0; i < 3; i++) { 1254 u8 num; 1255 1256 num = (u8) (val >> (24 - (i * 8))); 1257 for (int k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) { 1258 if (num >= k || !skip0 || k == 1) { 1259 sc->bce_bc_ver[j++] = (num / k) + '0'; 1260 skip0 = 0; 1261 } 1262 } 1263 1264 if (i != 2) 1265 sc->bce_bc_ver[j++] = '.'; 1266 } 1267 1268 /* Check if any management firwmare is enabled. */ 1269 val = bce_shmem_rd(sc, BCE_PORT_FEATURE); 1270 if (val & BCE_PORT_FEATURE_ASF_ENABLED) { 1271 sc->bce_flags |= BCE_MFW_ENABLE_FLAG; 1272 1273 /* Allow time for firmware to enter the running state. */ 1274 for (int i = 0; i < 30; i++) { 1275 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); 1276 if (val & BCE_CONDITION_MFW_RUN_MASK) 1277 break; 1278 DELAY(10000); 1279 } 1280 1281 /* Check if management firmware is running. */ 1282 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); 1283 val &= BCE_CONDITION_MFW_RUN_MASK; 1284 if ((val != BCE_CONDITION_MFW_RUN_UNKNOWN) && 1285 (val != BCE_CONDITION_MFW_RUN_NONE)) { 1286 u32 addr = bce_shmem_rd(sc, BCE_MFW_VER_PTR); 1287 int i = 0; 1288 1289 /* Read the management firmware version string. */ 1290 for (int j = 0; j < 3; j++) { 1291 val = bce_reg_rd_ind(sc, addr + j * 4); 1292 val = bswap32(val); 1293 memcpy(&sc->bce_mfw_ver[i], &val, 4); 1294 i += 4; 1295 } 1296 } else { 1297 /* May cause firmware synchronization timeouts. */ 1298 BCE_PRINTF("%s(%d): Management firmware enabled " 1299 "but not running!\n", __FILE__, __LINE__); 1300 strcpy(sc->bce_mfw_ver, "NOT RUNNING!"); 1301 1302 /* ToDo: Any action the driver should take? */ 1303 } 1304 } 1305 1306 /* Get PCI bus information (speed and type). */ 1307 val = REG_RD(sc, BCE_PCICFG_MISC_STATUS); 1308 if (val & BCE_PCICFG_MISC_STATUS_PCIX_DET) { 1309 u32 clkreg; 1310 1311 sc->bce_flags |= BCE_PCIX_FLAG; 1312 1313 clkreg = REG_RD(sc, BCE_PCICFG_PCI_CLOCK_CONTROL_BITS); 1314 1315 clkreg &= BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET; 1316 switch (clkreg) { 1317 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ: 1318 sc->bus_speed_mhz = 133; 1319 break; 1320 1321 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ: 1322 sc->bus_speed_mhz = 100; 1323 break; 1324 1325 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ: 1326 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ: 1327 sc->bus_speed_mhz = 66; 1328 break; 1329 1330 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ: 1331 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ: 1332 sc->bus_speed_mhz = 50; 1333 break; 1334 1335 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW: 1336 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ: 1337 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ: 1338 sc->bus_speed_mhz = 33; 1339 break; 1340 } 1341 } else { 1342 if (val & BCE_PCICFG_MISC_STATUS_M66EN) 1343 sc->bus_speed_mhz = 66; 1344 else 1345 sc->bus_speed_mhz = 33; 1346 } 1347 1348 if (val & BCE_PCICFG_MISC_STATUS_32BIT_DET) 1349 sc->bce_flags |= BCE_PCI_32BIT_FLAG; 1350 1351 /* Find the media type for the adapter. */ 1352 bce_get_media(sc); 1353 1354 /* Reset controller and announce to bootcode that driver is present. */ 1355 if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) { 1356 BCE_PRINTF("%s(%d): Controller reset failed!\n", 1357 __FILE__, __LINE__); 1358 rc = ENXIO; 1359 goto bce_attach_fail; 1360 } 1361 1362 /* Initialize the controller. */ 1363 if (bce_chipinit(sc)) { 1364 BCE_PRINTF("%s(%d): Controller initialization failed!\n", 1365 __FILE__, __LINE__); 1366 rc = ENXIO; 1367 goto bce_attach_fail; 1368 } 1369 1370 /* Perform NVRAM test. */ 1371 if (bce_nvram_test(sc)) { 1372 BCE_PRINTF("%s(%d): NVRAM test failed!\n", 1373 __FILE__, __LINE__); 1374 rc = ENXIO; 1375 goto bce_attach_fail; 1376 } 1377 1378 /* Fetch the permanent Ethernet MAC address. */ 1379 bce_get_mac_addr(sc); 1380 1381 /* Update statistics once every second. */ 1382 sc->bce_stats_ticks = 1000000 & 0xffff00; 1383 1384 /* Store data needed by PHY driver for backplane applications */ 1385 sc->bce_shared_hw_cfg = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG); 1386 sc->bce_port_hw_cfg = bce_shmem_rd(sc, BCE_PORT_HW_CFG_CONFIG); 1387 1388 /* Allocate DMA memory resources. */ 1389 if (bce_dma_alloc(dev)) { 1390 BCE_PRINTF("%s(%d): DMA resource allocation failed!\n", 1391 __FILE__, __LINE__); 1392 rc = ENXIO; 1393 goto bce_attach_fail; 1394 } 1395 1396 /* Allocate an ifnet structure. */ 1397 ifp = sc->bce_ifp = if_alloc(IFT_ETHER); 1398 if (ifp == NULL) { 1399 BCE_PRINTF("%s(%d): Interface allocation failed!\n", 1400 __FILE__, __LINE__); 1401 rc = ENXIO; 1402 goto bce_attach_fail; 1403 } 1404 1405 /* Initialize the ifnet interface. */ 1406 ifp->if_softc = sc; 1407 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1408 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1409 ifp->if_ioctl = bce_ioctl; 1410 ifp->if_start = bce_start; 1411 ifp->if_init = bce_init; 1412 ifp->if_mtu = ETHERMTU; 1413 1414 if (bce_tso_enable) { 1415 ifp->if_hwassist = BCE_IF_HWASSIST | CSUM_TSO; 1416 ifp->if_capabilities = BCE_IF_CAPABILITIES | IFCAP_TSO4 | 1417 IFCAP_VLAN_HWTSO; 1418 } else { 1419 ifp->if_hwassist = BCE_IF_HWASSIST; 1420 ifp->if_capabilities = BCE_IF_CAPABILITIES; 1421 } 1422 1423#if __FreeBSD_version >= 800505 1424 /* 1425 * Introducing IFCAP_LINKSTATE didn't bump __FreeBSD_version 1426 * so it's approximate value. 1427 */ 1428 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) 1429 ifp->if_capabilities |= IFCAP_LINKSTATE; 1430#endif 1431 1432 ifp->if_capenable = ifp->if_capabilities; 1433 1434 /* 1435 * Assume standard mbuf sizes for buffer allocation. 1436 * This may change later if the MTU size is set to 1437 * something other than 1500. 1438 */ 1439 bce_get_rx_buffer_sizes(sc, 1440 (ETHER_MAX_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN)); 1441 1442 /* Recalculate our buffer allocation sizes. */ 1443 ifp->if_snd.ifq_drv_maxlen = USABLE_TX_BD_ALLOC; 1444 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 1445 IFQ_SET_READY(&ifp->if_snd); 1446 1447 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) 1448 ifp->if_baudrate = IF_Mbps(2500ULL); 1449 else 1450 ifp->if_baudrate = IF_Mbps(1000); 1451 1452 /* Handle any special PHY initialization for SerDes PHYs. */ 1453 bce_init_media(sc); 1454 1455 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) { 1456 ifmedia_init(&sc->bce_ifmedia, IFM_IMASK, bce_ifmedia_upd, 1457 bce_ifmedia_sts); 1458 /* 1459 * We can't manually override remote PHY's link and assume 1460 * PHY port configuration(Fiber or TP) is not changed after 1461 * device attach. This may not be correct though. 1462 */ 1463 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) != 0) { 1464 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) { 1465 ifmedia_add(&sc->bce_ifmedia, 1466 IFM_ETHER | IFM_2500_SX, 0, NULL); 1467 ifmedia_add(&sc->bce_ifmedia, 1468 IFM_ETHER | IFM_2500_SX | IFM_FDX, 0, NULL); 1469 } 1470 ifmedia_add(&sc->bce_ifmedia, 1471 IFM_ETHER | IFM_1000_SX, 0, NULL); 1472 ifmedia_add(&sc->bce_ifmedia, 1473 IFM_ETHER | IFM_1000_SX | IFM_FDX, 0, NULL); 1474 } else { 1475 ifmedia_add(&sc->bce_ifmedia, 1476 IFM_ETHER | IFM_10_T, 0, NULL); 1477 ifmedia_add(&sc->bce_ifmedia, 1478 IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 1479 ifmedia_add(&sc->bce_ifmedia, 1480 IFM_ETHER | IFM_100_TX, 0, NULL); 1481 ifmedia_add(&sc->bce_ifmedia, 1482 IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 1483 ifmedia_add(&sc->bce_ifmedia, 1484 IFM_ETHER | IFM_1000_T, 0, NULL); 1485 ifmedia_add(&sc->bce_ifmedia, 1486 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 1487 } 1488 ifmedia_add(&sc->bce_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 1489 ifmedia_set(&sc->bce_ifmedia, IFM_ETHER | IFM_AUTO); 1490 sc->bce_ifmedia.ifm_media = sc->bce_ifmedia.ifm_cur->ifm_media; 1491 } else { 1492 /* MII child bus by attaching the PHY. */ 1493 rc = mii_attach(dev, &sc->bce_miibus, ifp, bce_ifmedia_upd, 1494 bce_ifmedia_sts, BMSR_DEFCAPMASK, sc->bce_phy_addr, 1495 MII_OFFSET_ANY, MIIF_DOPAUSE); 1496 if (rc != 0) { 1497 BCE_PRINTF("%s(%d): attaching PHYs failed\n", __FILE__, 1498 __LINE__); 1499 goto bce_attach_fail; 1500 } 1501 } 1502 1503 /* Attach to the Ethernet interface list. */ 1504 ether_ifattach(ifp, sc->eaddr); 1505 1506#if __FreeBSD_version < 500000 1507 callout_init(&sc->bce_tick_callout); 1508 callout_init(&sc->bce_pulse_callout); 1509#else 1510 callout_init_mtx(&sc->bce_tick_callout, &sc->bce_mtx, 0); 1511 callout_init_mtx(&sc->bce_pulse_callout, &sc->bce_mtx, 0); 1512#endif 1513 1514 /* Hookup IRQ last. */ 1515 rc = bus_setup_intr(dev, sc->bce_res_irq, INTR_TYPE_NET | INTR_MPSAFE, 1516 NULL, bce_intr, sc, &sc->bce_intrhand); 1517 1518 if (rc) { 1519 BCE_PRINTF("%s(%d): Failed to setup IRQ!\n", 1520 __FILE__, __LINE__); 1521 bce_detach(dev); 1522 goto bce_attach_exit; 1523 } 1524 1525 /* 1526 * At this point we've acquired all the resources 1527 * we need to run so there's no turning back, we're 1528 * cleared for launch. 1529 */ 1530 1531 /* Print some important debugging info. */ 1532 DBRUNMSG(BCE_INFO, bce_dump_driver_state(sc)); 1533 1534 /* Add the supported sysctls to the kernel. */ 1535 bce_add_sysctls(sc); 1536 1537 BCE_LOCK(sc); 1538 1539 /* 1540 * The chip reset earlier notified the bootcode that 1541 * a driver is present. We now need to start our pulse 1542 * routine so that the bootcode is reminded that we're 1543 * still running. 1544 */ 1545 bce_pulse(sc); 1546 1547 bce_mgmt_init_locked(sc); 1548 BCE_UNLOCK(sc); 1549 1550 /* Finally, print some useful adapter info */ 1551 bce_print_adapter_info(sc); 1552 DBPRINT(sc, BCE_FATAL, "%s(): sc = %p\n", 1553 __FUNCTION__, sc); 1554 1555 goto bce_attach_exit; 1556 1557bce_attach_fail: 1558 bce_release_resources(sc); 1559 1560bce_attach_exit: 1561 1562 DBEXIT(BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 1563 1564 return(rc); 1565} 1566 1567 1568/****************************************************************************/ 1569/* Device detach function. */ 1570/* */ 1571/* Stops the controller, resets the controller, and releases resources. */ 1572/* */ 1573/* Returns: */ 1574/* 0 on success, positive value on failure. */ 1575/****************************************************************************/ 1576static int 1577bce_detach(device_t dev) 1578{ 1579 struct bce_softc *sc = device_get_softc(dev); 1580 struct ifnet *ifp; 1581 u32 msg; 1582 1583 DBENTER(BCE_VERBOSE_UNLOAD | BCE_VERBOSE_RESET); 1584 1585 ifp = sc->bce_ifp; 1586 1587 /* Stop and reset the controller. */ 1588 BCE_LOCK(sc); 1589 1590 /* Stop the pulse so the bootcode can go to driver absent state. */ 1591 callout_stop(&sc->bce_pulse_callout); 1592 1593 bce_stop(sc); 1594 if (sc->bce_flags & BCE_NO_WOL_FLAG) 1595 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN; 1596 else 1597 msg = BCE_DRV_MSG_CODE_UNLOAD; 1598 bce_reset(sc, msg); 1599 1600 BCE_UNLOCK(sc); 1601 1602 ether_ifdetach(ifp); 1603 1604 /* If we have a child device on the MII bus remove it too. */ 1605 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) 1606 ifmedia_removeall(&sc->bce_ifmedia); 1607 else { 1608 bus_generic_detach(dev); 1609 device_delete_child(dev, sc->bce_miibus); 1610 } 1611 1612 /* Release all remaining resources. */ 1613 bce_release_resources(sc); 1614 1615 DBEXIT(BCE_VERBOSE_UNLOAD | BCE_VERBOSE_RESET); 1616 1617 return(0); 1618} 1619 1620 1621/****************************************************************************/ 1622/* Device shutdown function. */ 1623/* */ 1624/* Stops and resets the controller. */ 1625/* */ 1626/* Returns: */ 1627/* 0 on success, positive value on failure. */ 1628/****************************************************************************/ 1629static int 1630bce_shutdown(device_t dev) 1631{ 1632 struct bce_softc *sc = device_get_softc(dev); 1633 u32 msg; 1634 1635 DBENTER(BCE_VERBOSE); 1636 1637 BCE_LOCK(sc); 1638 bce_stop(sc); 1639 if (sc->bce_flags & BCE_NO_WOL_FLAG) 1640 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN; 1641 else 1642 msg = BCE_DRV_MSG_CODE_UNLOAD; 1643 bce_reset(sc, msg); 1644 BCE_UNLOCK(sc); 1645 1646 DBEXIT(BCE_VERBOSE); 1647 1648 return (0); 1649} 1650 1651 1652#ifdef BCE_DEBUG 1653/****************************************************************************/ 1654/* Register read. */ 1655/* */ 1656/* Returns: */ 1657/* The value of the register. */ 1658/****************************************************************************/ 1659static u32 1660bce_reg_rd(struct bce_softc *sc, u32 offset) 1661{ 1662 u32 val = REG_RD(sc, offset); 1663 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1664 __FUNCTION__, offset, val); 1665 return val; 1666} 1667 1668 1669/****************************************************************************/ 1670/* Register write (16 bit). */ 1671/* */ 1672/* Returns: */ 1673/* Nothing. */ 1674/****************************************************************************/ 1675static void 1676bce_reg_wr16(struct bce_softc *sc, u32 offset, u16 val) 1677{ 1678 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%04X\n", 1679 __FUNCTION__, offset, val); 1680 REG_WR16(sc, offset, val); 1681} 1682 1683 1684/****************************************************************************/ 1685/* Register write. */ 1686/* */ 1687/* Returns: */ 1688/* Nothing. */ 1689/****************************************************************************/ 1690static void 1691bce_reg_wr(struct bce_softc *sc, u32 offset, u32 val) 1692{ 1693 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1694 __FUNCTION__, offset, val); 1695 REG_WR(sc, offset, val); 1696} 1697#endif 1698 1699/****************************************************************************/ 1700/* Indirect register read. */ 1701/* */ 1702/* Reads NetXtreme II registers using an index/data register pair in PCI */ 1703/* configuration space. Using this mechanism avoids issues with posted */ 1704/* reads but is much slower than memory-mapped I/O. */ 1705/* */ 1706/* Returns: */ 1707/* The value of the register. */ 1708/****************************************************************************/ 1709static u32 1710bce_reg_rd_ind(struct bce_softc *sc, u32 offset) 1711{ 1712 device_t dev; 1713 dev = sc->bce_dev; 1714 1715 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4); 1716#ifdef BCE_DEBUG 1717 { 1718 u32 val; 1719 val = pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4); 1720 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1721 __FUNCTION__, offset, val); 1722 return val; 1723 } 1724#else 1725 return pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4); 1726#endif 1727} 1728 1729 1730/****************************************************************************/ 1731/* Indirect register write. */ 1732/* */ 1733/* Writes NetXtreme II registers using an index/data register pair in PCI */ 1734/* configuration space. Using this mechanism avoids issues with posted */ 1735/* writes but is muchh slower than memory-mapped I/O. */ 1736/* */ 1737/* Returns: */ 1738/* Nothing. */ 1739/****************************************************************************/ 1740static void 1741bce_reg_wr_ind(struct bce_softc *sc, u32 offset, u32 val) 1742{ 1743 device_t dev; 1744 dev = sc->bce_dev; 1745 1746 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1747 __FUNCTION__, offset, val); 1748 1749 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4); 1750 pci_write_config(dev, BCE_PCICFG_REG_WINDOW, val, 4); 1751} 1752 1753 1754/****************************************************************************/ 1755/* Shared memory write. */ 1756/* */ 1757/* Writes NetXtreme II shared memory region. */ 1758/* */ 1759/* Returns: */ 1760/* Nothing. */ 1761/****************************************************************************/ 1762static void 1763bce_shmem_wr(struct bce_softc *sc, u32 offset, u32 val) 1764{ 1765 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): Writing 0x%08X to " 1766 "0x%08X\n", __FUNCTION__, val, offset); 1767 1768 bce_reg_wr_ind(sc, sc->bce_shmem_base + offset, val); 1769} 1770 1771 1772/****************************************************************************/ 1773/* Shared memory read. */ 1774/* */ 1775/* Reads NetXtreme II shared memory region. */ 1776/* */ 1777/* Returns: */ 1778/* The 32 bit value read. */ 1779/****************************************************************************/ 1780static u32 1781bce_shmem_rd(struct bce_softc *sc, u32 offset) 1782{ 1783 u32 val = bce_reg_rd_ind(sc, sc->bce_shmem_base + offset); 1784 1785 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): Reading 0x%08X from " 1786 "0x%08X\n", __FUNCTION__, val, offset); 1787 1788 return val; 1789} 1790 1791 1792#ifdef BCE_DEBUG 1793/****************************************************************************/ 1794/* Context memory read. */ 1795/* */ 1796/* The NetXtreme II controller uses context memory to track connection */ 1797/* information for L2 and higher network protocols. */ 1798/* */ 1799/* Returns: */ 1800/* The requested 32 bit value of context memory. */ 1801/****************************************************************************/ 1802static u32 1803bce_ctx_rd(struct bce_softc *sc, u32 cid_addr, u32 ctx_offset) 1804{ 1805 u32 idx, offset, retry_cnt = 5, val; 1806 1807 DBRUNIF((cid_addr > MAX_CID_ADDR || ctx_offset & 0x3 || 1808 cid_addr & CTX_MASK), BCE_PRINTF("%s(): Invalid CID " 1809 "address: 0x%08X.\n", __FUNCTION__, cid_addr)); 1810 1811 offset = ctx_offset + cid_addr; 1812 1813 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 1814 1815 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_READ_REQ)); 1816 1817 for (idx = 0; idx < retry_cnt; idx++) { 1818 val = REG_RD(sc, BCE_CTX_CTX_CTRL); 1819 if ((val & BCE_CTX_CTX_CTRL_READ_REQ) == 0) 1820 break; 1821 DELAY(5); 1822 } 1823 1824 if (val & BCE_CTX_CTX_CTRL_READ_REQ) 1825 BCE_PRINTF("%s(%d); Unable to read CTX memory: " 1826 "cid_addr = 0x%08X, offset = 0x%08X!\n", 1827 __FILE__, __LINE__, cid_addr, ctx_offset); 1828 1829 val = REG_RD(sc, BCE_CTX_CTX_DATA); 1830 } else { 1831 REG_WR(sc, BCE_CTX_DATA_ADR, offset); 1832 val = REG_RD(sc, BCE_CTX_DATA); 1833 } 1834 1835 DBPRINT(sc, BCE_EXTREME_CTX, "%s(); cid_addr = 0x%08X, offset = 0x%08X, " 1836 "val = 0x%08X\n", __FUNCTION__, cid_addr, ctx_offset, val); 1837 1838 return(val); 1839} 1840#endif 1841 1842 1843/****************************************************************************/ 1844/* Context memory write. */ 1845/* */ 1846/* The NetXtreme II controller uses context memory to track connection */ 1847/* information for L2 and higher network protocols. */ 1848/* */ 1849/* Returns: */ 1850/* Nothing. */ 1851/****************************************************************************/ 1852static void 1853bce_ctx_wr(struct bce_softc *sc, u32 cid_addr, u32 ctx_offset, u32 ctx_val) 1854{ 1855 u32 idx, offset = ctx_offset + cid_addr; 1856 u32 val, retry_cnt = 5; 1857 1858 DBPRINT(sc, BCE_EXTREME_CTX, "%s(); cid_addr = 0x%08X, offset = 0x%08X, " 1859 "val = 0x%08X\n", __FUNCTION__, cid_addr, ctx_offset, ctx_val); 1860 1861 DBRUNIF((cid_addr > MAX_CID_ADDR || ctx_offset & 0x3 || cid_addr & CTX_MASK), 1862 BCE_PRINTF("%s(): Invalid CID address: 0x%08X.\n", 1863 __FUNCTION__, cid_addr)); 1864 1865 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 1866 1867 REG_WR(sc, BCE_CTX_CTX_DATA, ctx_val); 1868 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_WRITE_REQ)); 1869 1870 for (idx = 0; idx < retry_cnt; idx++) { 1871 val = REG_RD(sc, BCE_CTX_CTX_CTRL); 1872 if ((val & BCE_CTX_CTX_CTRL_WRITE_REQ) == 0) 1873 break; 1874 DELAY(5); 1875 } 1876 1877 if (val & BCE_CTX_CTX_CTRL_WRITE_REQ) 1878 BCE_PRINTF("%s(%d); Unable to write CTX memory: " 1879 "cid_addr = 0x%08X, offset = 0x%08X!\n", 1880 __FILE__, __LINE__, cid_addr, ctx_offset); 1881 1882 } else { 1883 REG_WR(sc, BCE_CTX_DATA_ADR, offset); 1884 REG_WR(sc, BCE_CTX_DATA, ctx_val); 1885 } 1886} 1887 1888 1889/****************************************************************************/ 1890/* PHY register read. */ 1891/* */ 1892/* Implements register reads on the MII bus. */ 1893/* */ 1894/* Returns: */ 1895/* The value of the register. */ 1896/****************************************************************************/ 1897static int 1898bce_miibus_read_reg(device_t dev, int phy, int reg) 1899{ 1900 struct bce_softc *sc; 1901 u32 val; 1902 int i; 1903 1904 sc = device_get_softc(dev); 1905 1906 /* 1907 * The 5709S PHY is an IEEE Clause 45 PHY 1908 * with special mappings to work with IEEE 1909 * Clause 22 register accesses. 1910 */ 1911 if ((sc->bce_phy_flags & BCE_PHY_IEEE_CLAUSE_45_FLAG) != 0) { 1912 if (reg >= MII_BMCR && reg <= MII_ANLPRNP) 1913 reg += 0x10; 1914 } 1915 1916 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1917 val = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1918 val &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL; 1919 1920 REG_WR(sc, BCE_EMAC_MDIO_MODE, val); 1921 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1922 1923 DELAY(40); 1924 } 1925 1926 1927 val = BCE_MIPHY(phy) | BCE_MIREG(reg) | 1928 BCE_EMAC_MDIO_COMM_COMMAND_READ | BCE_EMAC_MDIO_COMM_DISEXT | 1929 BCE_EMAC_MDIO_COMM_START_BUSY; 1930 REG_WR(sc, BCE_EMAC_MDIO_COMM, val); 1931 1932 for (i = 0; i < BCE_PHY_TIMEOUT; i++) { 1933 DELAY(10); 1934 1935 val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1936 if (!(val & BCE_EMAC_MDIO_COMM_START_BUSY)) { 1937 DELAY(5); 1938 1939 val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1940 val &= BCE_EMAC_MDIO_COMM_DATA; 1941 1942 break; 1943 } 1944 } 1945 1946 if (val & BCE_EMAC_MDIO_COMM_START_BUSY) { 1947 BCE_PRINTF("%s(%d): Error: PHY read timeout! phy = %d, " 1948 "reg = 0x%04X\n", __FILE__, __LINE__, phy, reg); 1949 val = 0x0; 1950 } else { 1951 val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1952 } 1953 1954 1955 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1956 val = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1957 val |= BCE_EMAC_MDIO_MODE_AUTO_POLL; 1958 1959 REG_WR(sc, BCE_EMAC_MDIO_MODE, val); 1960 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1961 1962 DELAY(40); 1963 } 1964 1965 DB_PRINT_PHY_REG(reg, val); 1966 return (val & 0xffff); 1967} 1968 1969 1970/****************************************************************************/ 1971/* PHY register write. */ 1972/* */ 1973/* Implements register writes on the MII bus. */ 1974/* */ 1975/* Returns: */ 1976/* The value of the register. */ 1977/****************************************************************************/ 1978static int 1979bce_miibus_write_reg(device_t dev, int phy, int reg, int val) 1980{ 1981 struct bce_softc *sc; 1982 u32 val1; 1983 int i; 1984 1985 sc = device_get_softc(dev); 1986 1987 DB_PRINT_PHY_REG(reg, val); 1988 1989 /* 1990 * The 5709S PHY is an IEEE Clause 45 PHY 1991 * with special mappings to work with IEEE 1992 * Clause 22 register accesses. 1993 */ 1994 if ((sc->bce_phy_flags & BCE_PHY_IEEE_CLAUSE_45_FLAG) != 0) { 1995 if (reg >= MII_BMCR && reg <= MII_ANLPRNP) 1996 reg += 0x10; 1997 } 1998 1999 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 2000 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE); 2001 val1 &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL; 2002 2003 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1); 2004 REG_RD(sc, BCE_EMAC_MDIO_MODE); 2005 2006 DELAY(40); 2007 } 2008 2009 val1 = BCE_MIPHY(phy) | BCE_MIREG(reg) | val | 2010 BCE_EMAC_MDIO_COMM_COMMAND_WRITE | 2011 BCE_EMAC_MDIO_COMM_START_BUSY | BCE_EMAC_MDIO_COMM_DISEXT; 2012 REG_WR(sc, BCE_EMAC_MDIO_COMM, val1); 2013 2014 for (i = 0; i < BCE_PHY_TIMEOUT; i++) { 2015 DELAY(10); 2016 2017 val1 = REG_RD(sc, BCE_EMAC_MDIO_COMM); 2018 if (!(val1 & BCE_EMAC_MDIO_COMM_START_BUSY)) { 2019 DELAY(5); 2020 break; 2021 } 2022 } 2023 2024 if (val1 & BCE_EMAC_MDIO_COMM_START_BUSY) 2025 BCE_PRINTF("%s(%d): PHY write timeout!\n", 2026 __FILE__, __LINE__); 2027 2028 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 2029 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE); 2030 val1 |= BCE_EMAC_MDIO_MODE_AUTO_POLL; 2031 2032 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1); 2033 REG_RD(sc, BCE_EMAC_MDIO_MODE); 2034 2035 DELAY(40); 2036 } 2037 2038 return 0; 2039} 2040 2041 2042/****************************************************************************/ 2043/* MII bus status change. */ 2044/* */ 2045/* Called by the MII bus driver when the PHY establishes link to set the */ 2046/* MAC interface registers. */ 2047/* */ 2048/* Returns: */ 2049/* Nothing. */ 2050/****************************************************************************/ 2051static void 2052bce_miibus_statchg(device_t dev) 2053{ 2054 struct bce_softc *sc; 2055 struct mii_data *mii; 2056 struct ifmediareq ifmr; 2057 int media_active, media_status, val; 2058 2059 sc = device_get_softc(dev); 2060 2061 DBENTER(BCE_VERBOSE_PHY); 2062 2063 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) { 2064 bzero(&ifmr, sizeof(ifmr)); 2065 bce_ifmedia_sts_rphy(sc, &ifmr); 2066 media_active = ifmr.ifm_active; 2067 media_status = ifmr.ifm_status; 2068 } else { 2069 mii = device_get_softc(sc->bce_miibus); 2070 media_active = mii->mii_media_active; 2071 media_status = mii->mii_media_status; 2072 } 2073 2074 /* Ignore invalid media status. */ 2075 if ((media_status & (IFM_ACTIVE | IFM_AVALID)) != 2076 (IFM_ACTIVE | IFM_AVALID)) 2077 goto bce_miibus_statchg_exit; 2078 2079 val = REG_RD(sc, BCE_EMAC_MODE); 2080 val &= ~(BCE_EMAC_MODE_PORT | BCE_EMAC_MODE_HALF_DUPLEX | 2081 BCE_EMAC_MODE_MAC_LOOP | BCE_EMAC_MODE_FORCE_LINK | 2082 BCE_EMAC_MODE_25G); 2083 2084 /* Set MII or GMII interface based on the PHY speed. */ 2085 switch (IFM_SUBTYPE(media_active)) { 2086 case IFM_10_T: 2087 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) { 2088 DBPRINT(sc, BCE_INFO_PHY, 2089 "Enabling 10Mb interface.\n"); 2090 val |= BCE_EMAC_MODE_PORT_MII_10; 2091 break; 2092 } 2093 /* fall-through */ 2094 case IFM_100_TX: 2095 DBPRINT(sc, BCE_INFO_PHY, "Enabling MII interface.\n"); 2096 val |= BCE_EMAC_MODE_PORT_MII; 2097 break; 2098 case IFM_2500_SX: 2099 DBPRINT(sc, BCE_INFO_PHY, "Enabling 2.5G MAC mode.\n"); 2100 val |= BCE_EMAC_MODE_25G; 2101 /* fall-through */ 2102 case IFM_1000_T: 2103 case IFM_1000_SX: 2104 DBPRINT(sc, BCE_INFO_PHY, "Enabling GMII interface.\n"); 2105 val |= BCE_EMAC_MODE_PORT_GMII; 2106 break; 2107 default: 2108 DBPRINT(sc, BCE_INFO_PHY, "Unknown link speed, enabling " 2109 "default GMII interface.\n"); 2110 val |= BCE_EMAC_MODE_PORT_GMII; 2111 } 2112 2113 /* Set half or full duplex based on PHY settings. */ 2114 if ((IFM_OPTIONS(media_active) & IFM_FDX) == 0) { 2115 DBPRINT(sc, BCE_INFO_PHY, 2116 "Setting Half-Duplex interface.\n"); 2117 val |= BCE_EMAC_MODE_HALF_DUPLEX; 2118 } else 2119 DBPRINT(sc, BCE_INFO_PHY, 2120 "Setting Full-Duplex interface.\n"); 2121 2122 REG_WR(sc, BCE_EMAC_MODE, val); 2123 2124 if ((IFM_OPTIONS(media_active) & IFM_ETH_RXPAUSE) != 0) { 2125 DBPRINT(sc, BCE_INFO_PHY, 2126 "%s(): Enabling RX flow control.\n", __FUNCTION__); 2127 BCE_SETBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_RX_MODE_FLOW_EN); 2128 sc->bce_flags |= BCE_USING_RX_FLOW_CONTROL; 2129 } else { 2130 DBPRINT(sc, BCE_INFO_PHY, 2131 "%s(): Disabling RX flow control.\n", __FUNCTION__); 2132 BCE_CLRBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_RX_MODE_FLOW_EN); 2133 sc->bce_flags &= ~BCE_USING_RX_FLOW_CONTROL; 2134 } 2135 2136 if ((IFM_OPTIONS(media_active) & IFM_ETH_TXPAUSE) != 0) { 2137 DBPRINT(sc, BCE_INFO_PHY, 2138 "%s(): Enabling TX flow control.\n", __FUNCTION__); 2139 BCE_SETBIT(sc, BCE_EMAC_TX_MODE, BCE_EMAC_TX_MODE_FLOW_EN); 2140 sc->bce_flags |= BCE_USING_TX_FLOW_CONTROL; 2141 } else { 2142 DBPRINT(sc, BCE_INFO_PHY, 2143 "%s(): Disabling TX flow control.\n", __FUNCTION__); 2144 BCE_CLRBIT(sc, BCE_EMAC_TX_MODE, BCE_EMAC_TX_MODE_FLOW_EN); 2145 sc->bce_flags &= ~BCE_USING_TX_FLOW_CONTROL; 2146 } 2147 2148 /* ToDo: Update watermarks in bce_init_rx_context(). */ 2149 2150bce_miibus_statchg_exit: 2151 DBEXIT(BCE_VERBOSE_PHY); 2152} 2153 2154 2155/****************************************************************************/ 2156/* Acquire NVRAM lock. */ 2157/* */ 2158/* Before the NVRAM can be accessed the caller must acquire an NVRAM lock. */ 2159/* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 2160/* for use by the driver. */ 2161/* */ 2162/* Returns: */ 2163/* 0 on success, positive value on failure. */ 2164/****************************************************************************/ 2165static int 2166bce_acquire_nvram_lock(struct bce_softc *sc) 2167{ 2168 u32 val; 2169 int j, rc = 0; 2170 2171 DBENTER(BCE_VERBOSE_NVRAM); 2172 2173 /* Request access to the flash interface. */ 2174 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2); 2175 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2176 val = REG_RD(sc, BCE_NVM_SW_ARB); 2177 if (val & BCE_NVM_SW_ARB_ARB_ARB2) 2178 break; 2179 2180 DELAY(5); 2181 } 2182 2183 if (j >= NVRAM_TIMEOUT_COUNT) { 2184 DBPRINT(sc, BCE_WARN, "Timeout acquiring NVRAM lock!\n"); 2185 rc = EBUSY; 2186 } 2187 2188 DBEXIT(BCE_VERBOSE_NVRAM); 2189 return (rc); 2190} 2191 2192 2193/****************************************************************************/ 2194/* Release NVRAM lock. */ 2195/* */ 2196/* When the caller is finished accessing NVRAM the lock must be released. */ 2197/* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 2198/* for use by the driver. */ 2199/* */ 2200/* Returns: */ 2201/* 0 on success, positive value on failure. */ 2202/****************************************************************************/ 2203static int 2204bce_release_nvram_lock(struct bce_softc *sc) 2205{ 2206 u32 val; 2207 int j, rc = 0; 2208 2209 DBENTER(BCE_VERBOSE_NVRAM); 2210 2211 /* 2212 * Relinquish nvram interface. 2213 */ 2214 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2); 2215 2216 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2217 val = REG_RD(sc, BCE_NVM_SW_ARB); 2218 if (!(val & BCE_NVM_SW_ARB_ARB_ARB2)) 2219 break; 2220 2221 DELAY(5); 2222 } 2223 2224 if (j >= NVRAM_TIMEOUT_COUNT) { 2225 DBPRINT(sc, BCE_WARN, "Timeout releasing NVRAM lock!\n"); 2226 rc = EBUSY; 2227 } 2228 2229 DBEXIT(BCE_VERBOSE_NVRAM); 2230 return (rc); 2231} 2232 2233 2234#ifdef BCE_NVRAM_WRITE_SUPPORT 2235/****************************************************************************/ 2236/* Enable NVRAM write access. */ 2237/* */ 2238/* Before writing to NVRAM the caller must enable NVRAM writes. */ 2239/* */ 2240/* Returns: */ 2241/* 0 on success, positive value on failure. */ 2242/****************************************************************************/ 2243static int 2244bce_enable_nvram_write(struct bce_softc *sc) 2245{ 2246 u32 val; 2247 int rc = 0; 2248 2249 DBENTER(BCE_VERBOSE_NVRAM); 2250 2251 val = REG_RD(sc, BCE_MISC_CFG); 2252 REG_WR(sc, BCE_MISC_CFG, val | BCE_MISC_CFG_NVM_WR_EN_PCI); 2253 2254 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2255 int j; 2256 2257 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 2258 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_WREN | BCE_NVM_COMMAND_DOIT); 2259 2260 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2261 DELAY(5); 2262 2263 val = REG_RD(sc, BCE_NVM_COMMAND); 2264 if (val & BCE_NVM_COMMAND_DONE) 2265 break; 2266 } 2267 2268 if (j >= NVRAM_TIMEOUT_COUNT) { 2269 DBPRINT(sc, BCE_WARN, "Timeout writing NVRAM!\n"); 2270 rc = EBUSY; 2271 } 2272 } 2273 2274 DBENTER(BCE_VERBOSE_NVRAM); 2275 return (rc); 2276} 2277 2278 2279/****************************************************************************/ 2280/* Disable NVRAM write access. */ 2281/* */ 2282/* When the caller is finished writing to NVRAM write access must be */ 2283/* disabled. */ 2284/* */ 2285/* Returns: */ 2286/* Nothing. */ 2287/****************************************************************************/ 2288static void 2289bce_disable_nvram_write(struct bce_softc *sc) 2290{ 2291 u32 val; 2292 2293 DBENTER(BCE_VERBOSE_NVRAM); 2294 2295 val = REG_RD(sc, BCE_MISC_CFG); 2296 REG_WR(sc, BCE_MISC_CFG, val & ~BCE_MISC_CFG_NVM_WR_EN); 2297 2298 DBEXIT(BCE_VERBOSE_NVRAM); 2299 2300} 2301#endif 2302 2303 2304/****************************************************************************/ 2305/* Enable NVRAM access. */ 2306/* */ 2307/* Before accessing NVRAM for read or write operations the caller must */ 2308/* enabled NVRAM access. */ 2309/* */ 2310/* Returns: */ 2311/* Nothing. */ 2312/****************************************************************************/ 2313static void 2314bce_enable_nvram_access(struct bce_softc *sc) 2315{ 2316 u32 val; 2317 2318 DBENTER(BCE_VERBOSE_NVRAM); 2319 2320 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE); 2321 /* Enable both bits, even on read. */ 2322 REG_WR(sc, BCE_NVM_ACCESS_ENABLE, val | 2323 BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN); 2324 2325 DBEXIT(BCE_VERBOSE_NVRAM); 2326} 2327 2328 2329/****************************************************************************/ 2330/* Disable NVRAM access. */ 2331/* */ 2332/* When the caller is finished accessing NVRAM access must be disabled. */ 2333/* */ 2334/* Returns: */ 2335/* Nothing. */ 2336/****************************************************************************/ 2337static void 2338bce_disable_nvram_access(struct bce_softc *sc) 2339{ 2340 u32 val; 2341 2342 DBENTER(BCE_VERBOSE_NVRAM); 2343 2344 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE); 2345 2346 /* Disable both bits, even after read. */ 2347 REG_WR(sc, BCE_NVM_ACCESS_ENABLE, val & 2348 ~(BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN)); 2349 2350 DBEXIT(BCE_VERBOSE_NVRAM); 2351} 2352 2353 2354#ifdef BCE_NVRAM_WRITE_SUPPORT 2355/****************************************************************************/ 2356/* Erase NVRAM page before writing. */ 2357/* */ 2358/* Non-buffered flash parts require that a page be erased before it is */ 2359/* written. */ 2360/* */ 2361/* Returns: */ 2362/* 0 on success, positive value on failure. */ 2363/****************************************************************************/ 2364static int 2365bce_nvram_erase_page(struct bce_softc *sc, u32 offset) 2366{ 2367 u32 cmd; 2368 int j, rc = 0; 2369 2370 DBENTER(BCE_VERBOSE_NVRAM); 2371 2372 /* Buffered flash doesn't require an erase. */ 2373 if (sc->bce_flash_info->flags & BCE_NV_BUFFERED) 2374 goto bce_nvram_erase_page_exit; 2375 2376 /* Build an erase command. */ 2377 cmd = BCE_NVM_COMMAND_ERASE | BCE_NVM_COMMAND_WR | 2378 BCE_NVM_COMMAND_DOIT; 2379 2380 /* 2381 * Clear the DONE bit separately, set the NVRAM adress to erase, 2382 * and issue the erase command. 2383 */ 2384 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 2385 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 2386 REG_WR(sc, BCE_NVM_COMMAND, cmd); 2387 2388 /* Wait for completion. */ 2389 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2390 u32 val; 2391 2392 DELAY(5); 2393 2394 val = REG_RD(sc, BCE_NVM_COMMAND); 2395 if (val & BCE_NVM_COMMAND_DONE) 2396 break; 2397 } 2398 2399 if (j >= NVRAM_TIMEOUT_COUNT) { 2400 DBPRINT(sc, BCE_WARN, "Timeout erasing NVRAM.\n"); 2401 rc = EBUSY; 2402 } 2403 2404bce_nvram_erase_page_exit: 2405 DBEXIT(BCE_VERBOSE_NVRAM); 2406 return (rc); 2407} 2408#endif /* BCE_NVRAM_WRITE_SUPPORT */ 2409 2410 2411/****************************************************************************/ 2412/* Read a dword (32 bits) from NVRAM. */ 2413/* */ 2414/* Read a 32 bit word from NVRAM. The caller is assumed to have already */ 2415/* obtained the NVRAM lock and enabled the controller for NVRAM access. */ 2416/* */ 2417/* Returns: */ 2418/* 0 on success and the 32 bit value read, positive value on failure. */ 2419/****************************************************************************/ 2420static int 2421bce_nvram_read_dword(struct bce_softc *sc, 2422 u32 offset, u8 *ret_val, u32 cmd_flags) 2423{ 2424 u32 cmd; 2425 int i, rc = 0; 2426 2427 DBENTER(BCE_EXTREME_NVRAM); 2428 2429 /* Build the command word. */ 2430 cmd = BCE_NVM_COMMAND_DOIT | cmd_flags; 2431 2432 /* Calculate the offset for buffered flash if translation is used. */ 2433 if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) { 2434 offset = ((offset / sc->bce_flash_info->page_size) << 2435 sc->bce_flash_info->page_bits) + 2436 (offset % sc->bce_flash_info->page_size); 2437 } 2438 2439 /* 2440 * Clear the DONE bit separately, set the address to read, 2441 * and issue the read. 2442 */ 2443 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 2444 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 2445 REG_WR(sc, BCE_NVM_COMMAND, cmd); 2446 2447 /* Wait for completion. */ 2448 for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) { 2449 u32 val; 2450 2451 DELAY(5); 2452 2453 val = REG_RD(sc, BCE_NVM_COMMAND); 2454 if (val & BCE_NVM_COMMAND_DONE) { 2455 val = REG_RD(sc, BCE_NVM_READ); 2456 2457 val = bce_be32toh(val); 2458 memcpy(ret_val, &val, 4); 2459 break; 2460 } 2461 } 2462 2463 /* Check for errors. */ 2464 if (i >= NVRAM_TIMEOUT_COUNT) { 2465 BCE_PRINTF("%s(%d): Timeout error reading NVRAM at " 2466 "offset 0x%08X!\n", __FILE__, __LINE__, offset); 2467 rc = EBUSY; 2468 } 2469 2470 DBEXIT(BCE_EXTREME_NVRAM); 2471 return(rc); 2472} 2473 2474 2475#ifdef BCE_NVRAM_WRITE_SUPPORT 2476/****************************************************************************/ 2477/* Write a dword (32 bits) to NVRAM. */ 2478/* */ 2479/* Write a 32 bit word to NVRAM. The caller is assumed to have already */ 2480/* obtained the NVRAM lock, enabled the controller for NVRAM access, and */ 2481/* enabled NVRAM write access. */ 2482/* */ 2483/* Returns: */ 2484/* 0 on success, positive value on failure. */ 2485/****************************************************************************/ 2486static int 2487bce_nvram_write_dword(struct bce_softc *sc, u32 offset, u8 *val, 2488 u32 cmd_flags) 2489{ 2490 u32 cmd, val32; 2491 int j, rc = 0; 2492 2493 DBENTER(BCE_VERBOSE_NVRAM); 2494 2495 /* Build the command word. */ 2496 cmd = BCE_NVM_COMMAND_DOIT | BCE_NVM_COMMAND_WR | cmd_flags; 2497 2498 /* Calculate the offset for buffered flash if translation is used. */ 2499 if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) { 2500 offset = ((offset / sc->bce_flash_info->page_size) << 2501 sc->bce_flash_info->page_bits) + 2502 (offset % sc->bce_flash_info->page_size); 2503 } 2504 2505 /* 2506 * Clear the DONE bit separately, convert NVRAM data to big-endian, 2507 * set the NVRAM address to write, and issue the write command 2508 */ 2509 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 2510 memcpy(&val32, val, 4); 2511 val32 = htobe32(val32); 2512 REG_WR(sc, BCE_NVM_WRITE, val32); 2513 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 2514 REG_WR(sc, BCE_NVM_COMMAND, cmd); 2515 2516 /* Wait for completion. */ 2517 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2518 DELAY(5); 2519 2520 if (REG_RD(sc, BCE_NVM_COMMAND) & BCE_NVM_COMMAND_DONE) 2521 break; 2522 } 2523 if (j >= NVRAM_TIMEOUT_COUNT) { 2524 BCE_PRINTF("%s(%d): Timeout error writing NVRAM at " 2525 "offset 0x%08X\n", __FILE__, __LINE__, offset); 2526 rc = EBUSY; 2527 } 2528 2529 DBEXIT(BCE_VERBOSE_NVRAM); 2530 return (rc); 2531} 2532#endif /* BCE_NVRAM_WRITE_SUPPORT */ 2533 2534 2535/****************************************************************************/ 2536/* Initialize NVRAM access. */ 2537/* */ 2538/* Identify the NVRAM device in use and prepare the NVRAM interface to */ 2539/* access that device. */ 2540/* */ 2541/* Returns: */ 2542/* 0 on success, positive value on failure. */ 2543/****************************************************************************/ 2544static int 2545bce_init_nvram(struct bce_softc *sc) 2546{ 2547 u32 val; 2548 int j, entry_count, rc = 0; 2549 const struct flash_spec *flash; 2550 2551 DBENTER(BCE_VERBOSE_NVRAM); 2552 2553 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 2554 sc->bce_flash_info = &flash_5709; 2555 goto bce_init_nvram_get_flash_size; 2556 } 2557 2558 /* Determine the selected interface. */ 2559 val = REG_RD(sc, BCE_NVM_CFG1); 2560 2561 entry_count = sizeof(flash_table) / sizeof(struct flash_spec); 2562 2563 /* 2564 * Flash reconfiguration is required to support additional 2565 * NVRAM devices not directly supported in hardware. 2566 * Check if the flash interface was reconfigured 2567 * by the bootcode. 2568 */ 2569 2570 if (val & 0x40000000) { 2571 /* Flash interface reconfigured by bootcode. */ 2572 2573 DBPRINT(sc,BCE_INFO_LOAD, 2574 "bce_init_nvram(): Flash WAS reconfigured.\n"); 2575 2576 for (j = 0, flash = &flash_table[0]; j < entry_count; 2577 j++, flash++) { 2578 if ((val & FLASH_BACKUP_STRAP_MASK) == 2579 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) { 2580 sc->bce_flash_info = flash; 2581 break; 2582 } 2583 } 2584 } else { 2585 /* Flash interface not yet reconfigured. */ 2586 u32 mask; 2587 2588 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Flash was NOT reconfigured.\n", 2589 __FUNCTION__); 2590 2591 if (val & (1 << 23)) 2592 mask = FLASH_BACKUP_STRAP_MASK; 2593 else 2594 mask = FLASH_STRAP_MASK; 2595 2596 /* Look for the matching NVRAM device configuration data. */ 2597 for (j = 0, flash = &flash_table[0]; j < entry_count; j++, flash++) { 2598 2599 /* Check if the device matches any of the known devices. */ 2600 if ((val & mask) == (flash->strapping & mask)) { 2601 /* Found a device match. */ 2602 sc->bce_flash_info = flash; 2603 2604 /* Request access to the flash interface. */ 2605 if ((rc = bce_acquire_nvram_lock(sc)) != 0) 2606 return rc; 2607 2608 /* Reconfigure the flash interface. */ 2609 bce_enable_nvram_access(sc); 2610 REG_WR(sc, BCE_NVM_CFG1, flash->config1); 2611 REG_WR(sc, BCE_NVM_CFG2, flash->config2); 2612 REG_WR(sc, BCE_NVM_CFG3, flash->config3); 2613 REG_WR(sc, BCE_NVM_WRITE1, flash->write1); 2614 bce_disable_nvram_access(sc); 2615 bce_release_nvram_lock(sc); 2616 2617 break; 2618 } 2619 } 2620 } 2621 2622 /* Check if a matching device was found. */ 2623 if (j == entry_count) { 2624 sc->bce_flash_info = NULL; 2625 BCE_PRINTF("%s(%d): Unknown Flash NVRAM found!\n", 2626 __FILE__, __LINE__); 2627 DBEXIT(BCE_VERBOSE_NVRAM); 2628 return (ENODEV); 2629 } 2630 2631bce_init_nvram_get_flash_size: 2632 /* Write the flash config data to the shared memory interface. */ 2633 val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG2); 2634 val &= BCE_SHARED_HW_CFG2_NVM_SIZE_MASK; 2635 if (val) 2636 sc->bce_flash_size = val; 2637 else 2638 sc->bce_flash_size = sc->bce_flash_info->total_size; 2639 2640 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Found %s, size = 0x%08X\n", 2641 __FUNCTION__, sc->bce_flash_info->name, 2642 sc->bce_flash_info->total_size); 2643 2644 DBEXIT(BCE_VERBOSE_NVRAM); 2645 return rc; 2646} 2647 2648 2649/****************************************************************************/ 2650/* Read an arbitrary range of data from NVRAM. */ 2651/* */ 2652/* Prepares the NVRAM interface for access and reads the requested data */ 2653/* into the supplied buffer. */ 2654/* */ 2655/* Returns: */ 2656/* 0 on success and the data read, positive value on failure. */ 2657/****************************************************************************/ 2658static int 2659bce_nvram_read(struct bce_softc *sc, u32 offset, u8 *ret_buf, 2660 int buf_size) 2661{ 2662 int rc = 0; 2663 u32 cmd_flags, offset32, len32, extra; 2664 2665 DBENTER(BCE_VERBOSE_NVRAM); 2666 2667 if (buf_size == 0) 2668 goto bce_nvram_read_exit; 2669 2670 /* Request access to the flash interface. */ 2671 if ((rc = bce_acquire_nvram_lock(sc)) != 0) 2672 goto bce_nvram_read_exit; 2673 2674 /* Enable access to flash interface */ 2675 bce_enable_nvram_access(sc); 2676 2677 len32 = buf_size; 2678 offset32 = offset; 2679 extra = 0; 2680 2681 cmd_flags = 0; 2682 2683 if (offset32 & 3) { 2684 u8 buf[4]; 2685 u32 pre_len; 2686 2687 offset32 &= ~3; 2688 pre_len = 4 - (offset & 3); 2689 2690 if (pre_len >= len32) { 2691 pre_len = len32; 2692 cmd_flags = BCE_NVM_COMMAND_FIRST | BCE_NVM_COMMAND_LAST; 2693 } 2694 else { 2695 cmd_flags = BCE_NVM_COMMAND_FIRST; 2696 } 2697 2698 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 2699 2700 if (rc) 2701 return rc; 2702 2703 memcpy(ret_buf, buf + (offset & 3), pre_len); 2704 2705 offset32 += 4; 2706 ret_buf += pre_len; 2707 len32 -= pre_len; 2708 } 2709 2710 if (len32 & 3) { 2711 extra = 4 - (len32 & 3); 2712 len32 = (len32 + 4) & ~3; 2713 } 2714 2715 if (len32 == 4) { 2716 u8 buf[4]; 2717 2718 if (cmd_flags) 2719 cmd_flags = BCE_NVM_COMMAND_LAST; 2720 else 2721 cmd_flags = BCE_NVM_COMMAND_FIRST | 2722 BCE_NVM_COMMAND_LAST; 2723 2724 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 2725 2726 memcpy(ret_buf, buf, 4 - extra); 2727 } 2728 else if (len32 > 0) { 2729 u8 buf[4]; 2730 2731 /* Read the first word. */ 2732 if (cmd_flags) 2733 cmd_flags = 0; 2734 else 2735 cmd_flags = BCE_NVM_COMMAND_FIRST; 2736 2737 rc = bce_nvram_read_dword(sc, offset32, ret_buf, cmd_flags); 2738 2739 /* Advance to the next dword. */ 2740 offset32 += 4; 2741 ret_buf += 4; 2742 len32 -= 4; 2743 2744 while (len32 > 4 && rc == 0) { 2745 rc = bce_nvram_read_dword(sc, offset32, ret_buf, 0); 2746 2747 /* Advance to the next dword. */ 2748 offset32 += 4; 2749 ret_buf += 4; 2750 len32 -= 4; 2751 } 2752 2753 if (rc) 2754 goto bce_nvram_read_locked_exit; 2755 2756 cmd_flags = BCE_NVM_COMMAND_LAST; 2757 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 2758 2759 memcpy(ret_buf, buf, 4 - extra); 2760 } 2761 2762bce_nvram_read_locked_exit: 2763 /* Disable access to flash interface and release the lock. */ 2764 bce_disable_nvram_access(sc); 2765 bce_release_nvram_lock(sc); 2766 2767bce_nvram_read_exit: 2768 DBEXIT(BCE_VERBOSE_NVRAM); 2769 return rc; 2770} 2771 2772 2773#ifdef BCE_NVRAM_WRITE_SUPPORT 2774/****************************************************************************/ 2775/* Write an arbitrary range of data from NVRAM. */ 2776/* */ 2777/* Prepares the NVRAM interface for write access and writes the requested */ 2778/* data from the supplied buffer. The caller is responsible for */ 2779/* calculating any appropriate CRCs. */ 2780/* */ 2781/* Returns: */ 2782/* 0 on success, positive value on failure. */ 2783/****************************************************************************/ 2784static int 2785bce_nvram_write(struct bce_softc *sc, u32 offset, u8 *data_buf, 2786 int buf_size) 2787{ 2788 u32 written, offset32, len32; 2789 u8 *buf, start[4], end[4]; 2790 int rc = 0; 2791 int align_start, align_end; 2792 2793 DBENTER(BCE_VERBOSE_NVRAM); 2794 2795 buf = data_buf; 2796 offset32 = offset; 2797 len32 = buf_size; 2798 align_start = align_end = 0; 2799 2800 if ((align_start = (offset32 & 3))) { 2801 offset32 &= ~3; 2802 len32 += align_start; 2803 if ((rc = bce_nvram_read(sc, offset32, start, 4))) 2804 goto bce_nvram_write_exit; 2805 } 2806 2807 if (len32 & 3) { 2808 if ((len32 > 4) || !align_start) { 2809 align_end = 4 - (len32 & 3); 2810 len32 += align_end; 2811 if ((rc = bce_nvram_read(sc, offset32 + len32 - 4, 2812 end, 4))) { 2813 goto bce_nvram_write_exit; 2814 } 2815 } 2816 } 2817 2818 if (align_start || align_end) { 2819 buf = malloc(len32, M_DEVBUF, M_NOWAIT); 2820 if (buf == 0) { 2821 rc = ENOMEM; 2822 goto bce_nvram_write_exit; 2823 } 2824 2825 if (align_start) { 2826 memcpy(buf, start, 4); 2827 } 2828 2829 if (align_end) { 2830 memcpy(buf + len32 - 4, end, 4); 2831 } 2832 memcpy(buf + align_start, data_buf, buf_size); 2833 } 2834 2835 written = 0; 2836 while ((written < len32) && (rc == 0)) { 2837 u32 page_start, page_end, data_start, data_end; 2838 u32 addr, cmd_flags; 2839 int i; 2840 u8 flash_buffer[264]; 2841 2842 /* Find the page_start addr */ 2843 page_start = offset32 + written; 2844 page_start -= (page_start % sc->bce_flash_info->page_size); 2845 /* Find the page_end addr */ 2846 page_end = page_start + sc->bce_flash_info->page_size; 2847 /* Find the data_start addr */ 2848 data_start = (written == 0) ? offset32 : page_start; 2849 /* Find the data_end addr */ 2850 data_end = (page_end > offset32 + len32) ? 2851 (offset32 + len32) : page_end; 2852 2853 /* Request access to the flash interface. */ 2854 if ((rc = bce_acquire_nvram_lock(sc)) != 0) 2855 goto bce_nvram_write_exit; 2856 2857 /* Enable access to flash interface */ 2858 bce_enable_nvram_access(sc); 2859 2860 cmd_flags = BCE_NVM_COMMAND_FIRST; 2861 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2862 int j; 2863 2864 /* Read the whole page into the buffer 2865 * (non-buffer flash only) */ 2866 for (j = 0; j < sc->bce_flash_info->page_size; j += 4) { 2867 if (j == (sc->bce_flash_info->page_size - 4)) { 2868 cmd_flags |= BCE_NVM_COMMAND_LAST; 2869 } 2870 rc = bce_nvram_read_dword(sc, 2871 page_start + j, 2872 &flash_buffer[j], 2873 cmd_flags); 2874 2875 if (rc) 2876 goto bce_nvram_write_locked_exit; 2877 2878 cmd_flags = 0; 2879 } 2880 } 2881 2882 /* Enable writes to flash interface (unlock write-protect) */ 2883 if ((rc = bce_enable_nvram_write(sc)) != 0) 2884 goto bce_nvram_write_locked_exit; 2885 2886 /* Erase the page */ 2887 if ((rc = bce_nvram_erase_page(sc, page_start)) != 0) 2888 goto bce_nvram_write_locked_exit; 2889 2890 /* Re-enable the write again for the actual write */ 2891 bce_enable_nvram_write(sc); 2892 2893 /* Loop to write back the buffer data from page_start to 2894 * data_start */ 2895 i = 0; 2896 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2897 for (addr = page_start; addr < data_start; 2898 addr += 4, i += 4) { 2899 2900 rc = bce_nvram_write_dword(sc, addr, 2901 &flash_buffer[i], cmd_flags); 2902 2903 if (rc != 0) 2904 goto bce_nvram_write_locked_exit; 2905 2906 cmd_flags = 0; 2907 } 2908 } 2909 2910 /* Loop to write the new data from data_start to data_end */ 2911 for (addr = data_start; addr < data_end; addr += 4, i++) { 2912 if ((addr == page_end - 4) || 2913 ((sc->bce_flash_info->flags & BCE_NV_BUFFERED) && 2914 (addr == data_end - 4))) { 2915 2916 cmd_flags |= BCE_NVM_COMMAND_LAST; 2917 } 2918 rc = bce_nvram_write_dword(sc, addr, buf, 2919 cmd_flags); 2920 2921 if (rc != 0) 2922 goto bce_nvram_write_locked_exit; 2923 2924 cmd_flags = 0; 2925 buf += 4; 2926 } 2927 2928 /* Loop to write back the buffer data from data_end 2929 * to page_end */ 2930 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2931 for (addr = data_end; addr < page_end; 2932 addr += 4, i += 4) { 2933 2934 if (addr == page_end-4) { 2935 cmd_flags = BCE_NVM_COMMAND_LAST; 2936 } 2937 rc = bce_nvram_write_dword(sc, addr, 2938 &flash_buffer[i], cmd_flags); 2939 2940 if (rc != 0) 2941 goto bce_nvram_write_locked_exit; 2942 2943 cmd_flags = 0; 2944 } 2945 } 2946 2947 /* Disable writes to flash interface (lock write-protect) */ 2948 bce_disable_nvram_write(sc); 2949 2950 /* Disable access to flash interface */ 2951 bce_disable_nvram_access(sc); 2952 bce_release_nvram_lock(sc); 2953 2954 /* Increment written */ 2955 written += data_end - data_start; 2956 } 2957 2958 goto bce_nvram_write_exit; 2959 2960bce_nvram_write_locked_exit: 2961 bce_disable_nvram_write(sc); 2962 bce_disable_nvram_access(sc); 2963 bce_release_nvram_lock(sc); 2964 2965bce_nvram_write_exit: 2966 if (align_start || align_end) 2967 free(buf, M_DEVBUF); 2968 2969 DBEXIT(BCE_VERBOSE_NVRAM); 2970 return (rc); 2971} 2972#endif /* BCE_NVRAM_WRITE_SUPPORT */ 2973 2974 2975/****************************************************************************/ 2976/* Verifies that NVRAM is accessible and contains valid data. */ 2977/* */ 2978/* Reads the configuration data from NVRAM and verifies that the CRC is */ 2979/* correct. */ 2980/* */ 2981/* Returns: */ 2982/* 0 on success, positive value on failure. */ 2983/****************************************************************************/ 2984static int 2985bce_nvram_test(struct bce_softc *sc) 2986{ 2987 u32 buf[BCE_NVRAM_SIZE / 4]; 2988 u8 *data = (u8 *) buf; 2989 int rc = 0; 2990 u32 magic, csum; 2991 2992 DBENTER(BCE_VERBOSE_NVRAM | BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 2993 2994 /* 2995 * Check that the device NVRAM is valid by reading 2996 * the magic value at offset 0. 2997 */ 2998 if ((rc = bce_nvram_read(sc, 0, data, 4)) != 0) { 2999 BCE_PRINTF("%s(%d): Unable to read NVRAM!\n", 3000 __FILE__, __LINE__); 3001 goto bce_nvram_test_exit; 3002 } 3003 3004 /* 3005 * Verify that offset 0 of the NVRAM contains 3006 * a valid magic number. 3007 */ 3008 magic = bce_be32toh(buf[0]); 3009 if (magic != BCE_NVRAM_MAGIC) { 3010 rc = ENODEV; 3011 BCE_PRINTF("%s(%d): Invalid NVRAM magic value! " 3012 "Expected: 0x%08X, Found: 0x%08X\n", 3013 __FILE__, __LINE__, BCE_NVRAM_MAGIC, magic); 3014 goto bce_nvram_test_exit; 3015 } 3016 3017 /* 3018 * Verify that the device NVRAM includes valid 3019 * configuration data. 3020 */ 3021 if ((rc = bce_nvram_read(sc, 0x100, data, BCE_NVRAM_SIZE)) != 0) { 3022 BCE_PRINTF("%s(%d): Unable to read manufacturing " 3023 "Information from NVRAM!\n", __FILE__, __LINE__); 3024 goto bce_nvram_test_exit; 3025 } 3026 3027 csum = ether_crc32_le(data, 0x100); 3028 if (csum != BCE_CRC32_RESIDUAL) { 3029 rc = ENODEV; 3030 BCE_PRINTF("%s(%d): Invalid manufacturing information " 3031 "NVRAM CRC! Expected: 0x%08X, Found: 0x%08X\n", 3032 __FILE__, __LINE__, BCE_CRC32_RESIDUAL, csum); 3033 goto bce_nvram_test_exit; 3034 } 3035 3036 csum = ether_crc32_le(data + 0x100, 0x100); 3037 if (csum != BCE_CRC32_RESIDUAL) { 3038 rc = ENODEV; 3039 BCE_PRINTF("%s(%d): Invalid feature configuration " 3040 "information NVRAM CRC! Expected: 0x%08X, " 3041 "Found: 08%08X\n", __FILE__, __LINE__, 3042 BCE_CRC32_RESIDUAL, csum); 3043 } 3044 3045bce_nvram_test_exit: 3046 DBEXIT(BCE_VERBOSE_NVRAM | BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 3047 return rc; 3048} 3049 3050 3051/****************************************************************************/ 3052/* Calculates the size of the buffers to allocate based on the MTU. */ 3053/* */ 3054/* Returns: */ 3055/* Nothing. */ 3056/****************************************************************************/ 3057static void 3058bce_get_rx_buffer_sizes(struct bce_softc *sc, int mtu) 3059{ 3060 DBENTER(BCE_VERBOSE_LOAD); 3061 3062 /* Use a single allocation type when header splitting enabled. */ 3063 if (bce_hdr_split == TRUE) { 3064 sc->rx_bd_mbuf_alloc_size = MHLEN; 3065 /* Make sure offset is 16 byte aligned for hardware. */ 3066 sc->rx_bd_mbuf_align_pad = 3067 roundup2((MSIZE - MHLEN), 16) - (MSIZE - MHLEN); 3068 sc->rx_bd_mbuf_data_len = sc->rx_bd_mbuf_alloc_size - 3069 sc->rx_bd_mbuf_align_pad; 3070 } else { 3071 if ((mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + 3072 ETHER_CRC_LEN) > MCLBYTES) { 3073 /* Setup for jumbo RX buffer allocations. */ 3074 sc->rx_bd_mbuf_alloc_size = MJUM9BYTES; 3075 sc->rx_bd_mbuf_align_pad = 3076 roundup2(MJUM9BYTES, 16) - MJUM9BYTES; 3077 sc->rx_bd_mbuf_data_len = 3078 sc->rx_bd_mbuf_alloc_size - 3079 sc->rx_bd_mbuf_align_pad; 3080 } else { 3081 /* Setup for standard RX buffer allocations. */ 3082 sc->rx_bd_mbuf_alloc_size = MCLBYTES; 3083 sc->rx_bd_mbuf_align_pad = 3084 roundup2(MCLBYTES, 16) - MCLBYTES; 3085 sc->rx_bd_mbuf_data_len = 3086 sc->rx_bd_mbuf_alloc_size - 3087 sc->rx_bd_mbuf_align_pad; 3088 } 3089 } 3090 3091// DBPRINT(sc, BCE_INFO_LOAD, 3092 DBPRINT(sc, BCE_WARN, 3093 "%s(): rx_bd_mbuf_alloc_size = %d, rx_bd_mbuf_data_len = %d, " 3094 "rx_bd_mbuf_align_pad = %d\n", __FUNCTION__, 3095 sc->rx_bd_mbuf_alloc_size, sc->rx_bd_mbuf_data_len, 3096 sc->rx_bd_mbuf_align_pad); 3097 3098 DBEXIT(BCE_VERBOSE_LOAD); 3099} 3100 3101/****************************************************************************/ 3102/* Identifies the current media type of the controller and sets the PHY */ 3103/* address. */ 3104/* */ 3105/* Returns: */ 3106/* Nothing. */ 3107/****************************************************************************/ 3108static void 3109bce_get_media(struct bce_softc *sc) 3110{ 3111 u32 val; 3112 3113 DBENTER(BCE_VERBOSE_PHY); 3114 3115 /* Assume PHY address for copper controllers. */ 3116 sc->bce_phy_addr = 1; 3117 3118 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 3119 u32 val = REG_RD(sc, BCE_MISC_DUAL_MEDIA_CTRL); 3120 u32 bond_id = val & BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID; 3121 u32 strap; 3122 3123 /* 3124 * The BCM5709S is software configurable 3125 * for Copper or SerDes operation. 3126 */ 3127 if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) { 3128 DBPRINT(sc, BCE_INFO_LOAD, "5709 bonded " 3129 "for copper.\n"); 3130 goto bce_get_media_exit; 3131 } else if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) { 3132 DBPRINT(sc, BCE_INFO_LOAD, "5709 bonded " 3133 "for dual media.\n"); 3134 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 3135 goto bce_get_media_exit; 3136 } 3137 3138 if (val & BCE_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE) 3139 strap = (val & 3140 BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21; 3141 else 3142 strap = (val & 3143 BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8; 3144 3145 if (pci_get_function(sc->bce_dev) == 0) { 3146 switch (strap) { 3147 case 0x4: 3148 case 0x5: 3149 case 0x6: 3150 DBPRINT(sc, BCE_INFO_LOAD, 3151 "BCM5709 s/w configured for SerDes.\n"); 3152 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 3153 break; 3154 default: 3155 DBPRINT(sc, BCE_INFO_LOAD, 3156 "BCM5709 s/w configured for Copper.\n"); 3157 break; 3158 } 3159 } else { 3160 switch (strap) { 3161 case 0x1: 3162 case 0x2: 3163 case 0x4: 3164 DBPRINT(sc, BCE_INFO_LOAD, 3165 "BCM5709 s/w configured for SerDes.\n"); 3166 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 3167 break; 3168 default: 3169 DBPRINT(sc, BCE_INFO_LOAD, 3170 "BCM5709 s/w configured for Copper.\n"); 3171 break; 3172 } 3173 } 3174 3175 } else if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT) 3176 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 3177 3178 if (sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) { 3179 3180 sc->bce_flags |= BCE_NO_WOL_FLAG; 3181 3182 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) 3183 sc->bce_phy_flags |= BCE_PHY_IEEE_CLAUSE_45_FLAG; 3184 3185 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) { 3186 /* 5708S/09S/16S use a separate PHY for SerDes. */ 3187 sc->bce_phy_addr = 2; 3188 3189 val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG); 3190 if (val & BCE_SHARED_HW_CFG_PHY_2_5G) { 3191 sc->bce_phy_flags |= 3192 BCE_PHY_2_5G_CAPABLE_FLAG; 3193 DBPRINT(sc, BCE_INFO_LOAD, "Found 2.5Gb " 3194 "capable adapter\n"); 3195 } 3196 } 3197 } else if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) || 3198 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)) 3199 sc->bce_phy_flags |= BCE_PHY_CRC_FIX_FLAG; 3200 3201bce_get_media_exit: 3202 DBPRINT(sc, (BCE_INFO_LOAD | BCE_INFO_PHY), 3203 "Using PHY address %d.\n", sc->bce_phy_addr); 3204 3205 DBEXIT(BCE_VERBOSE_PHY); 3206} 3207 3208 3209/****************************************************************************/ 3210/* Performs PHY initialization required before MII drivers access the */ 3211/* device. */ 3212/* */ 3213/* Returns: */ 3214/* Nothing. */ 3215/****************************************************************************/ 3216static void 3217bce_init_media(struct bce_softc *sc) 3218{ 3219 if ((sc->bce_phy_flags & (BCE_PHY_IEEE_CLAUSE_45_FLAG | 3220 BCE_PHY_REMOTE_CAP_FLAG)) == BCE_PHY_IEEE_CLAUSE_45_FLAG) { 3221 /* 3222 * Configure 5709S/5716S PHYs to use traditional IEEE 3223 * Clause 22 method. Otherwise we have no way to attach 3224 * the PHY in mii(4) layer. PHY specific configuration 3225 * is done in mii layer. 3226 */ 3227 3228 /* Select auto-negotiation MMD of the PHY. */ 3229 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr, 3230 BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_ADDR_EXT); 3231 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr, 3232 BRGPHY_ADDR_EXT, BRGPHY_ADDR_EXT_AN_MMD); 3233 3234 /* Set IEEE0 block of AN MMD (assumed in brgphy(4) code). */ 3235 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr, 3236 BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 3237 } 3238} 3239 3240 3241/****************************************************************************/ 3242/* Free any DMA memory owned by the driver. */ 3243/* */ 3244/* Scans through each data structre that requires DMA memory and frees */ 3245/* the memory if allocated. */ 3246/* */ 3247/* Returns: */ 3248/* Nothing. */ 3249/****************************************************************************/ 3250static void 3251bce_dma_free(struct bce_softc *sc) 3252{ 3253 int i; 3254 3255 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_UNLOAD | BCE_VERBOSE_CTX); 3256 3257 /* Free, unmap, and destroy the status block. */ 3258 if (sc->status_block != NULL) { 3259 bus_dmamem_free( 3260 sc->status_tag, 3261 sc->status_block, 3262 sc->status_map); 3263 sc->status_block = NULL; 3264 } 3265 3266 if (sc->status_map != NULL) { 3267 bus_dmamap_unload( 3268 sc->status_tag, 3269 sc->status_map); 3270 bus_dmamap_destroy(sc->status_tag, 3271 sc->status_map); 3272 sc->status_map = NULL; 3273 } 3274 3275 if (sc->status_tag != NULL) { 3276 bus_dma_tag_destroy(sc->status_tag); 3277 sc->status_tag = NULL; 3278 } 3279 3280 3281 /* Free, unmap, and destroy the statistics block. */ 3282 if (sc->stats_block != NULL) { 3283 bus_dmamem_free( 3284 sc->stats_tag, 3285 sc->stats_block, 3286 sc->stats_map); 3287 sc->stats_block = NULL; 3288 } 3289 3290 if (sc->stats_map != NULL) { 3291 bus_dmamap_unload( 3292 sc->stats_tag, 3293 sc->stats_map); 3294 bus_dmamap_destroy(sc->stats_tag, 3295 sc->stats_map); 3296 sc->stats_map = NULL; 3297 } 3298 3299 if (sc->stats_tag != NULL) { 3300 bus_dma_tag_destroy(sc->stats_tag); 3301 sc->stats_tag = NULL; 3302 } 3303 3304 3305 /* Free, unmap and destroy all context memory pages. */ 3306 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 3307 for (i = 0; i < sc->ctx_pages; i++ ) { 3308 if (sc->ctx_block[i] != NULL) { 3309 bus_dmamem_free( 3310 sc->ctx_tag, 3311 sc->ctx_block[i], 3312 sc->ctx_map[i]); 3313 sc->ctx_block[i] = NULL; 3314 } 3315 3316 if (sc->ctx_map[i] != NULL) { 3317 bus_dmamap_unload( 3318 sc->ctx_tag, 3319 sc->ctx_map[i]); 3320 bus_dmamap_destroy( 3321 sc->ctx_tag, 3322 sc->ctx_map[i]); 3323 sc->ctx_map[i] = NULL; 3324 } 3325 } 3326 3327 /* Destroy the context memory tag. */ 3328 if (sc->ctx_tag != NULL) { 3329 bus_dma_tag_destroy(sc->ctx_tag); 3330 sc->ctx_tag = NULL; 3331 } 3332 } 3333 3334 3335 /* Free, unmap and destroy all TX buffer descriptor chain pages. */ 3336 for (i = 0; i < sc->tx_pages; i++ ) { 3337 if (sc->tx_bd_chain[i] != NULL) { 3338 bus_dmamem_free( 3339 sc->tx_bd_chain_tag, 3340 sc->tx_bd_chain[i], 3341 sc->tx_bd_chain_map[i]); 3342 sc->tx_bd_chain[i] = NULL; 3343 } 3344 3345 if (sc->tx_bd_chain_map[i] != NULL) { 3346 bus_dmamap_unload( 3347 sc->tx_bd_chain_tag, 3348 sc->tx_bd_chain_map[i]); 3349 bus_dmamap_destroy( 3350 sc->tx_bd_chain_tag, 3351 sc->tx_bd_chain_map[i]); 3352 sc->tx_bd_chain_map[i] = NULL; 3353 } 3354 } 3355 3356 /* Destroy the TX buffer descriptor tag. */ 3357 if (sc->tx_bd_chain_tag != NULL) { 3358 bus_dma_tag_destroy(sc->tx_bd_chain_tag); 3359 sc->tx_bd_chain_tag = NULL; 3360 } 3361 3362 3363 /* Free, unmap and destroy all RX buffer descriptor chain pages. */ 3364 for (i = 0; i < sc->rx_pages; i++ ) { 3365 if (sc->rx_bd_chain[i] != NULL) { 3366 bus_dmamem_free( 3367 sc->rx_bd_chain_tag, 3368 sc->rx_bd_chain[i], 3369 sc->rx_bd_chain_map[i]); 3370 sc->rx_bd_chain[i] = NULL; 3371 } 3372 3373 if (sc->rx_bd_chain_map[i] != NULL) { 3374 bus_dmamap_unload( 3375 sc->rx_bd_chain_tag, 3376 sc->rx_bd_chain_map[i]); 3377 bus_dmamap_destroy( 3378 sc->rx_bd_chain_tag, 3379 sc->rx_bd_chain_map[i]); 3380 sc->rx_bd_chain_map[i] = NULL; 3381 } 3382 } 3383 3384 /* Destroy the RX buffer descriptor tag. */ 3385 if (sc->rx_bd_chain_tag != NULL) { 3386 bus_dma_tag_destroy(sc->rx_bd_chain_tag); 3387 sc->rx_bd_chain_tag = NULL; 3388 } 3389 3390 3391 /* Free, unmap and destroy all page buffer descriptor chain pages. */ 3392 if (bce_hdr_split == TRUE) { 3393 for (i = 0; i < sc->pg_pages; i++ ) { 3394 if (sc->pg_bd_chain[i] != NULL) { 3395 bus_dmamem_free( 3396 sc->pg_bd_chain_tag, 3397 sc->pg_bd_chain[i], 3398 sc->pg_bd_chain_map[i]); 3399 sc->pg_bd_chain[i] = NULL; 3400 } 3401 3402 if (sc->pg_bd_chain_map[i] != NULL) { 3403 bus_dmamap_unload( 3404 sc->pg_bd_chain_tag, 3405 sc->pg_bd_chain_map[i]); 3406 bus_dmamap_destroy( 3407 sc->pg_bd_chain_tag, 3408 sc->pg_bd_chain_map[i]); 3409 sc->pg_bd_chain_map[i] = NULL; 3410 } 3411 } 3412 3413 /* Destroy the page buffer descriptor tag. */ 3414 if (sc->pg_bd_chain_tag != NULL) { 3415 bus_dma_tag_destroy(sc->pg_bd_chain_tag); 3416 sc->pg_bd_chain_tag = NULL; 3417 } 3418 } 3419 3420 3421 /* Unload and destroy the TX mbuf maps. */ 3422 for (i = 0; i < MAX_TX_BD_AVAIL; i++) { 3423 if (sc->tx_mbuf_map[i] != NULL) { 3424 bus_dmamap_unload(sc->tx_mbuf_tag, 3425 sc->tx_mbuf_map[i]); 3426 bus_dmamap_destroy(sc->tx_mbuf_tag, 3427 sc->tx_mbuf_map[i]); 3428 sc->tx_mbuf_map[i] = NULL; 3429 } 3430 } 3431 3432 /* Destroy the TX mbuf tag. */ 3433 if (sc->tx_mbuf_tag != NULL) { 3434 bus_dma_tag_destroy(sc->tx_mbuf_tag); 3435 sc->tx_mbuf_tag = NULL; 3436 } 3437 3438 /* Unload and destroy the RX mbuf maps. */ 3439 for (i = 0; i < MAX_RX_BD_AVAIL; i++) { 3440 if (sc->rx_mbuf_map[i] != NULL) { 3441 bus_dmamap_unload(sc->rx_mbuf_tag, 3442 sc->rx_mbuf_map[i]); 3443 bus_dmamap_destroy(sc->rx_mbuf_tag, 3444 sc->rx_mbuf_map[i]); 3445 sc->rx_mbuf_map[i] = NULL; 3446 } 3447 } 3448 3449 /* Destroy the RX mbuf tag. */ 3450 if (sc->rx_mbuf_tag != NULL) { 3451 bus_dma_tag_destroy(sc->rx_mbuf_tag); 3452 sc->rx_mbuf_tag = NULL; 3453 } 3454 3455 /* Unload and destroy the page mbuf maps. */ 3456 if (bce_hdr_split == TRUE) { 3457 for (i = 0; i < MAX_PG_BD_AVAIL; i++) { 3458 if (sc->pg_mbuf_map[i] != NULL) { 3459 bus_dmamap_unload(sc->pg_mbuf_tag, 3460 sc->pg_mbuf_map[i]); 3461 bus_dmamap_destroy(sc->pg_mbuf_tag, 3462 sc->pg_mbuf_map[i]); 3463 sc->pg_mbuf_map[i] = NULL; 3464 } 3465 } 3466 3467 /* Destroy the page mbuf tag. */ 3468 if (sc->pg_mbuf_tag != NULL) { 3469 bus_dma_tag_destroy(sc->pg_mbuf_tag); 3470 sc->pg_mbuf_tag = NULL; 3471 } 3472 } 3473 3474 /* Destroy the parent tag */ 3475 if (sc->parent_tag != NULL) { 3476 bus_dma_tag_destroy(sc->parent_tag); 3477 sc->parent_tag = NULL; 3478 } 3479 3480 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_UNLOAD | BCE_VERBOSE_CTX); 3481} 3482 3483 3484/****************************************************************************/ 3485/* Get DMA memory from the OS. */ 3486/* */ 3487/* Validates that the OS has provided DMA buffers in response to a */ 3488/* bus_dmamap_load() call and saves the physical address of those buffers. */ 3489/* When the callback is used the OS will return 0 for the mapping function */ 3490/* (bus_dmamap_load()) so we use the value of map_arg->maxsegs to pass any */ 3491/* failures back to the caller. */ 3492/* */ 3493/* Returns: */ 3494/* Nothing. */ 3495/****************************************************************************/ 3496static void 3497bce_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 3498{ 3499 bus_addr_t *busaddr = arg; 3500 3501 KASSERT(nseg == 1, ("%s(): Too many segments returned (%d)!", 3502 __FUNCTION__, nseg)); 3503 /* Simulate a mapping failure. */ 3504 DBRUNIF(DB_RANDOMTRUE(dma_map_addr_failed_sim_control), 3505 error = ENOMEM); 3506 3507 /* ToDo: How to increment debug sim_count variable here? */ 3508 3509 /* Check for an error and signal the caller that an error occurred. */ 3510 if (error) { 3511 *busaddr = 0; 3512 } else { 3513 *busaddr = segs->ds_addr; 3514 } 3515} 3516 3517 3518/****************************************************************************/ 3519/* Allocate any DMA memory needed by the driver. */ 3520/* */ 3521/* Allocates DMA memory needed for the various global structures needed by */ 3522/* hardware. */ 3523/* */ 3524/* Memory alignment requirements: */ 3525/* +-----------------+----------+----------+----------+----------+ */ 3526/* | | 5706 | 5708 | 5709 | 5716 | */ 3527/* +-----------------+----------+----------+----------+----------+ */ 3528/* |Status Block | 8 bytes | 8 bytes | 16 bytes | 16 bytes | */ 3529/* |Statistics Block | 8 bytes | 8 bytes | 16 bytes | 16 bytes | */ 3530/* |RX Buffers | 16 bytes | 16 bytes | 16 bytes | 16 bytes | */ 3531/* |PG Buffers | none | none | none | none | */ 3532/* |TX Buffers | none | none | none | none | */ 3533/* |Chain Pages(1) | 4KiB | 4KiB | 4KiB | 4KiB | */ 3534/* |Context Memory | | | | | */ 3535/* +-----------------+----------+----------+----------+----------+ */ 3536/* */ 3537/* (1) Must align with CPU page size (BCM_PAGE_SZIE). */ 3538/* */ 3539/* Returns: */ 3540/* 0 for success, positive value for failure. */ 3541/****************************************************************************/ 3542static int 3543bce_dma_alloc(device_t dev) 3544{ 3545 struct bce_softc *sc; 3546 int i, error, rc = 0; 3547 bus_size_t max_size, max_seg_size; 3548 int max_segments; 3549 3550 sc = device_get_softc(dev); 3551 3552 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 3553 3554 /* 3555 * Allocate the parent bus DMA tag appropriate for PCI. 3556 */ 3557 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1, BCE_DMA_BOUNDARY, 3558 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, 3559 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, 3560 &sc->parent_tag)) { 3561 BCE_PRINTF("%s(%d): Could not allocate parent DMA tag!\n", 3562 __FILE__, __LINE__); 3563 rc = ENOMEM; 3564 goto bce_dma_alloc_exit; 3565 } 3566 3567 /* 3568 * Create a DMA tag for the status block, allocate and clear the 3569 * memory, map the memory into DMA space, and fetch the physical 3570 * address of the block. 3571 */ 3572 if (bus_dma_tag_create(sc->parent_tag, BCE_DMA_ALIGN, 3573 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, 3574 NULL, NULL, BCE_STATUS_BLK_SZ, 1, BCE_STATUS_BLK_SZ, 3575 0, NULL, NULL, &sc->status_tag)) { 3576 BCE_PRINTF("%s(%d): Could not allocate status block " 3577 "DMA tag!\n", __FILE__, __LINE__); 3578 rc = ENOMEM; 3579 goto bce_dma_alloc_exit; 3580 } 3581 3582 if(bus_dmamem_alloc(sc->status_tag, (void **)&sc->status_block, 3583 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3584 &sc->status_map)) { 3585 BCE_PRINTF("%s(%d): Could not allocate status block " 3586 "DMA memory!\n", __FILE__, __LINE__); 3587 rc = ENOMEM; 3588 goto bce_dma_alloc_exit; 3589 } 3590 3591 error = bus_dmamap_load(sc->status_tag, sc->status_map, 3592 sc->status_block, BCE_STATUS_BLK_SZ, bce_dma_map_addr, 3593 &sc->status_block_paddr, BUS_DMA_NOWAIT); 3594 3595 if (error || sc->status_block_paddr == 0) { 3596 BCE_PRINTF("%s(%d): Could not map status block " 3597 "DMA memory!\n", __FILE__, __LINE__); 3598 rc = ENOMEM; 3599 goto bce_dma_alloc_exit; 3600 } 3601 3602 DBPRINT(sc, BCE_INFO_LOAD, "%s(): status_block_paddr = 0x%jX\n", 3603 __FUNCTION__, (uintmax_t) sc->status_block_paddr); 3604 3605 /* 3606 * Create a DMA tag for the statistics block, allocate and clear the 3607 * memory, map the memory into DMA space, and fetch the physical 3608 * address of the block. 3609 */ 3610 if (bus_dma_tag_create(sc->parent_tag, BCE_DMA_ALIGN, 3611 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, 3612 NULL, NULL, BCE_STATS_BLK_SZ, 1, BCE_STATS_BLK_SZ, 3613 0, NULL, NULL, &sc->stats_tag)) { 3614 BCE_PRINTF("%s(%d): Could not allocate statistics block " 3615 "DMA tag!\n", __FILE__, __LINE__); 3616 rc = ENOMEM; 3617 goto bce_dma_alloc_exit; 3618 } 3619 3620 if (bus_dmamem_alloc(sc->stats_tag, (void **)&sc->stats_block, 3621 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->stats_map)) { 3622 BCE_PRINTF("%s(%d): Could not allocate statistics block " 3623 "DMA memory!\n", __FILE__, __LINE__); 3624 rc = ENOMEM; 3625 goto bce_dma_alloc_exit; 3626 } 3627 3628 error = bus_dmamap_load(sc->stats_tag, sc->stats_map, 3629 sc->stats_block, BCE_STATS_BLK_SZ, bce_dma_map_addr, 3630 &sc->stats_block_paddr, BUS_DMA_NOWAIT); 3631 3632 if (error || sc->stats_block_paddr == 0) { 3633 BCE_PRINTF("%s(%d): Could not map statistics block " 3634 "DMA memory!\n", __FILE__, __LINE__); 3635 rc = ENOMEM; 3636 goto bce_dma_alloc_exit; 3637 } 3638 3639 DBPRINT(sc, BCE_INFO_LOAD, "%s(): stats_block_paddr = 0x%jX\n", 3640 __FUNCTION__, (uintmax_t) sc->stats_block_paddr); 3641 3642 /* BCM5709 uses host memory as cache for context memory. */ 3643 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 3644 sc->ctx_pages = 0x2000 / BCM_PAGE_SIZE; 3645 if (sc->ctx_pages == 0) 3646 sc->ctx_pages = 1; 3647 3648 DBRUNIF((sc->ctx_pages > 512), 3649 BCE_PRINTF("%s(%d): Too many CTX pages! %d > 512\n", 3650 __FILE__, __LINE__, sc->ctx_pages)); 3651 3652 /* 3653 * Create a DMA tag for the context pages, 3654 * allocate and clear the memory, map the 3655 * memory into DMA space, and fetch the 3656 * physical address of the block. 3657 */ 3658 if(bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 3659 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, 3660 NULL, NULL, BCM_PAGE_SIZE, 1, BCM_PAGE_SIZE, 3661 0, NULL, NULL, &sc->ctx_tag)) { 3662 BCE_PRINTF("%s(%d): Could not allocate CTX " 3663 "DMA tag!\n", __FILE__, __LINE__); 3664 rc = ENOMEM; 3665 goto bce_dma_alloc_exit; 3666 } 3667 3668 for (i = 0; i < sc->ctx_pages; i++) { 3669 3670 if(bus_dmamem_alloc(sc->ctx_tag, 3671 (void **)&sc->ctx_block[i], 3672 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3673 &sc->ctx_map[i])) { 3674 BCE_PRINTF("%s(%d): Could not allocate CTX " 3675 "DMA memory!\n", __FILE__, __LINE__); 3676 rc = ENOMEM; 3677 goto bce_dma_alloc_exit; 3678 } 3679 3680 error = bus_dmamap_load(sc->ctx_tag, sc->ctx_map[i], 3681 sc->ctx_block[i], BCM_PAGE_SIZE, bce_dma_map_addr, 3682 &sc->ctx_paddr[i], BUS_DMA_NOWAIT); 3683 3684 if (error || sc->ctx_paddr[i] == 0) { 3685 BCE_PRINTF("%s(%d): Could not map CTX " 3686 "DMA memory!\n", __FILE__, __LINE__); 3687 rc = ENOMEM; 3688 goto bce_dma_alloc_exit; 3689 } 3690 3691 DBPRINT(sc, BCE_INFO_LOAD, "%s(): ctx_paddr[%d] " 3692 "= 0x%jX\n", __FUNCTION__, i, 3693 (uintmax_t) sc->ctx_paddr[i]); 3694 } 3695 } 3696 3697 /* 3698 * Create a DMA tag for the TX buffer descriptor chain, 3699 * allocate and clear the memory, and fetch the 3700 * physical address of the block. 3701 */ 3702 if(bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, BCE_DMA_BOUNDARY, 3703 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, 3704 BCE_TX_CHAIN_PAGE_SZ, 1, BCE_TX_CHAIN_PAGE_SZ, 0, 3705 NULL, NULL, &sc->tx_bd_chain_tag)) { 3706 BCE_PRINTF("%s(%d): Could not allocate TX descriptor " 3707 "chain DMA tag!\n", __FILE__, __LINE__); 3708 rc = ENOMEM; 3709 goto bce_dma_alloc_exit; 3710 } 3711 3712 for (i = 0; i < sc->tx_pages; i++) { 3713 3714 if(bus_dmamem_alloc(sc->tx_bd_chain_tag, 3715 (void **)&sc->tx_bd_chain[i], 3716 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3717 &sc->tx_bd_chain_map[i])) { 3718 BCE_PRINTF("%s(%d): Could not allocate TX descriptor " 3719 "chain DMA memory!\n", __FILE__, __LINE__); 3720 rc = ENOMEM; 3721 goto bce_dma_alloc_exit; 3722 } 3723 3724 error = bus_dmamap_load(sc->tx_bd_chain_tag, 3725 sc->tx_bd_chain_map[i], sc->tx_bd_chain[i], 3726 BCE_TX_CHAIN_PAGE_SZ, bce_dma_map_addr, 3727 &sc->tx_bd_chain_paddr[i], BUS_DMA_NOWAIT); 3728 3729 if (error || sc->tx_bd_chain_paddr[i] == 0) { 3730 BCE_PRINTF("%s(%d): Could not map TX descriptor " 3731 "chain DMA memory!\n", __FILE__, __LINE__); 3732 rc = ENOMEM; 3733 goto bce_dma_alloc_exit; 3734 } 3735 3736 DBPRINT(sc, BCE_INFO_LOAD, "%s(): tx_bd_chain_paddr[%d] = " 3737 "0x%jX\n", __FUNCTION__, i, 3738 (uintmax_t) sc->tx_bd_chain_paddr[i]); 3739 } 3740 3741 /* Check the required size before mapping to conserve resources. */ 3742 if (bce_tso_enable) { 3743 max_size = BCE_TSO_MAX_SIZE; 3744 max_segments = BCE_MAX_SEGMENTS; 3745 max_seg_size = BCE_TSO_MAX_SEG_SIZE; 3746 } else { 3747 max_size = MCLBYTES * BCE_MAX_SEGMENTS; 3748 max_segments = BCE_MAX_SEGMENTS; 3749 max_seg_size = MCLBYTES; 3750 } 3751 3752 /* Create a DMA tag for TX mbufs. */ 3753 if (bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY, 3754 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, max_size, 3755 max_segments, max_seg_size, 0, NULL, NULL, &sc->tx_mbuf_tag)) { 3756 BCE_PRINTF("%s(%d): Could not allocate TX mbuf DMA tag!\n", 3757 __FILE__, __LINE__); 3758 rc = ENOMEM; 3759 goto bce_dma_alloc_exit; 3760 } 3761 3762 /* Create DMA maps for the TX mbufs clusters. */ 3763 for (i = 0; i < TOTAL_TX_BD_ALLOC; i++) { 3764 if (bus_dmamap_create(sc->tx_mbuf_tag, BUS_DMA_NOWAIT, 3765 &sc->tx_mbuf_map[i])) { 3766 BCE_PRINTF("%s(%d): Unable to create TX mbuf DMA " 3767 "map!\n", __FILE__, __LINE__); 3768 rc = ENOMEM; 3769 goto bce_dma_alloc_exit; 3770 } 3771 } 3772 3773 /* 3774 * Create a DMA tag for the RX buffer descriptor chain, 3775 * allocate and clear the memory, and fetch the physical 3776 * address of the blocks. 3777 */ 3778 if (bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 3779 BCE_DMA_BOUNDARY, BUS_SPACE_MAXADDR, 3780 sc->max_bus_addr, NULL, NULL, 3781 BCE_RX_CHAIN_PAGE_SZ, 1, BCE_RX_CHAIN_PAGE_SZ, 3782 0, NULL, NULL, &sc->rx_bd_chain_tag)) { 3783 BCE_PRINTF("%s(%d): Could not allocate RX descriptor chain " 3784 "DMA tag!\n", __FILE__, __LINE__); 3785 rc = ENOMEM; 3786 goto bce_dma_alloc_exit; 3787 } 3788 3789 for (i = 0; i < sc->rx_pages; i++) { 3790 3791 if (bus_dmamem_alloc(sc->rx_bd_chain_tag, 3792 (void **)&sc->rx_bd_chain[i], 3793 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3794 &sc->rx_bd_chain_map[i])) { 3795 BCE_PRINTF("%s(%d): Could not allocate RX descriptor " 3796 "chain DMA memory!\n", __FILE__, __LINE__); 3797 rc = ENOMEM; 3798 goto bce_dma_alloc_exit; 3799 } 3800 3801 error = bus_dmamap_load(sc->rx_bd_chain_tag, 3802 sc->rx_bd_chain_map[i], sc->rx_bd_chain[i], 3803 BCE_RX_CHAIN_PAGE_SZ, bce_dma_map_addr, 3804 &sc->rx_bd_chain_paddr[i], BUS_DMA_NOWAIT); 3805 3806 if (error || sc->rx_bd_chain_paddr[i] == 0) { 3807 BCE_PRINTF("%s(%d): Could not map RX descriptor " 3808 "chain DMA memory!\n", __FILE__, __LINE__); 3809 rc = ENOMEM; 3810 goto bce_dma_alloc_exit; 3811 } 3812 3813 DBPRINT(sc, BCE_INFO_LOAD, "%s(): rx_bd_chain_paddr[%d] = " 3814 "0x%jX\n", __FUNCTION__, i, 3815 (uintmax_t) sc->rx_bd_chain_paddr[i]); 3816 } 3817 3818 /* 3819 * Create a DMA tag for RX mbufs. 3820 */ 3821 if (bce_hdr_split == TRUE) 3822 max_size = ((sc->rx_bd_mbuf_alloc_size < MCLBYTES) ? 3823 MCLBYTES : sc->rx_bd_mbuf_alloc_size); 3824 else 3825 max_size = MJUM9BYTES; 3826 3827 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Creating rx_mbuf_tag " 3828 "(max size = 0x%jX)\n", __FUNCTION__, (uintmax_t)max_size); 3829 3830 if (bus_dma_tag_create(sc->parent_tag, BCE_RX_BUF_ALIGN, 3831 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, 3832 max_size, 1, max_size, 0, NULL, NULL, &sc->rx_mbuf_tag)) { 3833 BCE_PRINTF("%s(%d): Could not allocate RX mbuf DMA tag!\n", 3834 __FILE__, __LINE__); 3835 rc = ENOMEM; 3836 goto bce_dma_alloc_exit; 3837 } 3838 3839 /* Create DMA maps for the RX mbuf clusters. */ 3840 for (i = 0; i < TOTAL_RX_BD_ALLOC; i++) { 3841 if (bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_NOWAIT, 3842 &sc->rx_mbuf_map[i])) { 3843 BCE_PRINTF("%s(%d): Unable to create RX mbuf " 3844 "DMA map!\n", __FILE__, __LINE__); 3845 rc = ENOMEM; 3846 goto bce_dma_alloc_exit; 3847 } 3848 } 3849 3850 if (bce_hdr_split == TRUE) { 3851 /* 3852 * Create a DMA tag for the page buffer descriptor chain, 3853 * allocate and clear the memory, and fetch the physical 3854 * address of the blocks. 3855 */ 3856 if (bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 3857 BCE_DMA_BOUNDARY, BUS_SPACE_MAXADDR, sc->max_bus_addr, 3858 NULL, NULL, BCE_PG_CHAIN_PAGE_SZ, 1, BCE_PG_CHAIN_PAGE_SZ, 3859 0, NULL, NULL, &sc->pg_bd_chain_tag)) { 3860 BCE_PRINTF("%s(%d): Could not allocate page descriptor " 3861 "chain DMA tag!\n", __FILE__, __LINE__); 3862 rc = ENOMEM; 3863 goto bce_dma_alloc_exit; 3864 } 3865 3866 for (i = 0; i < sc->pg_pages; i++) { 3867 if (bus_dmamem_alloc(sc->pg_bd_chain_tag, 3868 (void **)&sc->pg_bd_chain[i], 3869 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3870 &sc->pg_bd_chain_map[i])) { 3871 BCE_PRINTF("%s(%d): Could not allocate page " 3872 "descriptor chain DMA memory!\n", 3873 __FILE__, __LINE__); 3874 rc = ENOMEM; 3875 goto bce_dma_alloc_exit; 3876 } 3877 3878 error = bus_dmamap_load(sc->pg_bd_chain_tag, 3879 sc->pg_bd_chain_map[i], sc->pg_bd_chain[i], 3880 BCE_PG_CHAIN_PAGE_SZ, bce_dma_map_addr, 3881 &sc->pg_bd_chain_paddr[i], BUS_DMA_NOWAIT); 3882 3883 if (error || sc->pg_bd_chain_paddr[i] == 0) { 3884 BCE_PRINTF("%s(%d): Could not map page descriptor " 3885 "chain DMA memory!\n", __FILE__, __LINE__); 3886 rc = ENOMEM; 3887 goto bce_dma_alloc_exit; 3888 } 3889 3890 DBPRINT(sc, BCE_INFO_LOAD, "%s(): pg_bd_chain_paddr[%d] = " 3891 "0x%jX\n", __FUNCTION__, i, 3892 (uintmax_t) sc->pg_bd_chain_paddr[i]); 3893 } 3894 3895 /* 3896 * Create a DMA tag for page mbufs. 3897 */ 3898 if (bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY, 3899 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 3900 1, MCLBYTES, 0, NULL, NULL, &sc->pg_mbuf_tag)) { 3901 BCE_PRINTF("%s(%d): Could not allocate page mbuf " 3902 "DMA tag!\n", __FILE__, __LINE__); 3903 rc = ENOMEM; 3904 goto bce_dma_alloc_exit; 3905 } 3906 3907 /* Create DMA maps for the page mbuf clusters. */ 3908 for (i = 0; i < TOTAL_PG_BD_ALLOC; i++) { 3909 if (bus_dmamap_create(sc->pg_mbuf_tag, BUS_DMA_NOWAIT, 3910 &sc->pg_mbuf_map[i])) { 3911 BCE_PRINTF("%s(%d): Unable to create page mbuf " 3912 "DMA map!\n", __FILE__, __LINE__); 3913 rc = ENOMEM; 3914 goto bce_dma_alloc_exit; 3915 } 3916 } 3917 } 3918 3919bce_dma_alloc_exit: 3920 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 3921 return(rc); 3922} 3923 3924 3925/****************************************************************************/ 3926/* Release all resources used by the driver. */ 3927/* */ 3928/* Releases all resources acquired by the driver including interrupts, */ 3929/* interrupt handler, interfaces, mutexes, and DMA memory. */ 3930/* */ 3931/* Returns: */ 3932/* Nothing. */ 3933/****************************************************************************/ 3934static void 3935bce_release_resources(struct bce_softc *sc) 3936{ 3937 device_t dev; 3938 3939 DBENTER(BCE_VERBOSE_RESET); 3940 3941 dev = sc->bce_dev; 3942 3943 bce_dma_free(sc); 3944 3945 if (sc->bce_intrhand != NULL) { 3946 DBPRINT(sc, BCE_INFO_RESET, "Removing interrupt handler.\n"); 3947 bus_teardown_intr(dev, sc->bce_res_irq, sc->bce_intrhand); 3948 } 3949 3950 if (sc->bce_res_irq != NULL) { 3951 DBPRINT(sc, BCE_INFO_RESET, "Releasing IRQ.\n"); 3952 bus_release_resource(dev, SYS_RES_IRQ, 3953 rman_get_rid(sc->bce_res_irq), sc->bce_res_irq); 3954 } 3955 3956 if (sc->bce_flags & (BCE_USING_MSI_FLAG | BCE_USING_MSIX_FLAG)) { 3957 DBPRINT(sc, BCE_INFO_RESET, "Releasing MSI/MSI-X vector.\n"); 3958 pci_release_msi(dev); 3959 } 3960 3961 if (sc->bce_res_mem != NULL) { 3962 DBPRINT(sc, BCE_INFO_RESET, "Releasing PCI memory.\n"); 3963 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0), 3964 sc->bce_res_mem); 3965 } 3966 3967 if (sc->bce_ifp != NULL) { 3968 DBPRINT(sc, BCE_INFO_RESET, "Releasing IF.\n"); 3969 if_free(sc->bce_ifp); 3970 } 3971 3972 if (mtx_initialized(&sc->bce_mtx)) 3973 BCE_LOCK_DESTROY(sc); 3974 3975 DBEXIT(BCE_VERBOSE_RESET); 3976} 3977 3978 3979/****************************************************************************/ 3980/* Firmware synchronization. */ 3981/* */ 3982/* Before performing certain events such as a chip reset, synchronize with */ 3983/* the firmware first. */ 3984/* */ 3985/* Returns: */ 3986/* 0 for success, positive value for failure. */ 3987/****************************************************************************/ 3988static int 3989bce_fw_sync(struct bce_softc *sc, u32 msg_data) 3990{ 3991 int i, rc = 0; 3992 u32 val; 3993 3994 DBENTER(BCE_VERBOSE_RESET); 3995 3996 /* Don't waste any time if we've timed out before. */ 3997 if (sc->bce_fw_timed_out == TRUE) { 3998 rc = EBUSY; 3999 goto bce_fw_sync_exit; 4000 } 4001 4002 /* Increment the message sequence number. */ 4003 sc->bce_fw_wr_seq++; 4004 msg_data |= sc->bce_fw_wr_seq; 4005 4006 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "bce_fw_sync(): msg_data = " 4007 "0x%08X\n", msg_data); 4008 4009 /* Send the message to the bootcode driver mailbox. */ 4010 bce_shmem_wr(sc, BCE_DRV_MB, msg_data); 4011 4012 /* Wait for the bootcode to acknowledge the message. */ 4013 for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) { 4014 /* Check for a response in the bootcode firmware mailbox. */ 4015 val = bce_shmem_rd(sc, BCE_FW_MB); 4016 if ((val & BCE_FW_MSG_ACK) == (msg_data & BCE_DRV_MSG_SEQ)) 4017 break; 4018 DELAY(1000); 4019 } 4020 4021 /* If we've timed out, tell bootcode that we've stopped waiting. */ 4022 if (((val & BCE_FW_MSG_ACK) != (msg_data & BCE_DRV_MSG_SEQ)) && 4023 ((msg_data & BCE_DRV_MSG_DATA) != BCE_DRV_MSG_DATA_WAIT0)) { 4024 4025 BCE_PRINTF("%s(%d): Firmware synchronization timeout! " 4026 "msg_data = 0x%08X\n", __FILE__, __LINE__, msg_data); 4027 4028 msg_data &= ~BCE_DRV_MSG_CODE; 4029 msg_data |= BCE_DRV_MSG_CODE_FW_TIMEOUT; 4030 4031 bce_shmem_wr(sc, BCE_DRV_MB, msg_data); 4032 4033 sc->bce_fw_timed_out = TRUE; 4034 rc = EBUSY; 4035 } 4036 4037bce_fw_sync_exit: 4038 DBEXIT(BCE_VERBOSE_RESET); 4039 return (rc); 4040} 4041 4042 4043/****************************************************************************/ 4044/* Load Receive Virtual 2 Physical (RV2P) processor firmware. */ 4045/* */ 4046/* Returns: */ 4047/* Nothing. */ 4048/****************************************************************************/ 4049static void 4050bce_load_rv2p_fw(struct bce_softc *sc, const u32 *rv2p_code, 4051 u32 rv2p_code_len, u32 rv2p_proc) 4052{ 4053 int i; 4054 u32 val; 4055 4056 DBENTER(BCE_VERBOSE_RESET); 4057 4058 /* Set the page size used by RV2P. */ 4059 if (rv2p_proc == RV2P_PROC2) { 4060 BCE_RV2P_PROC2_CHG_MAX_BD_PAGE(USABLE_RX_BD_PER_PAGE); 4061 } 4062 4063 for (i = 0; i < rv2p_code_len; i += 8) { 4064 REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code); 4065 rv2p_code++; 4066 REG_WR(sc, BCE_RV2P_INSTR_LOW, *rv2p_code); 4067 rv2p_code++; 4068 4069 if (rv2p_proc == RV2P_PROC1) { 4070 val = (i / 8) | BCE_RV2P_PROC1_ADDR_CMD_RDWR; 4071 REG_WR(sc, BCE_RV2P_PROC1_ADDR_CMD, val); 4072 } 4073 else { 4074 val = (i / 8) | BCE_RV2P_PROC2_ADDR_CMD_RDWR; 4075 REG_WR(sc, BCE_RV2P_PROC2_ADDR_CMD, val); 4076 } 4077 } 4078 4079 /* Reset the processor, un-stall is done later. */ 4080 if (rv2p_proc == RV2P_PROC1) { 4081 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET); 4082 } 4083 else { 4084 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET); 4085 } 4086 4087 DBEXIT(BCE_VERBOSE_RESET); 4088} 4089 4090 4091/****************************************************************************/ 4092/* Load RISC processor firmware. */ 4093/* */ 4094/* Loads firmware from the file if_bcefw.h into the scratchpad memory */ 4095/* associated with a particular processor. */ 4096/* */ 4097/* Returns: */ 4098/* Nothing. */ 4099/****************************************************************************/ 4100static void 4101bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg, 4102 struct fw_info *fw) 4103{ 4104 u32 offset; 4105 4106 DBENTER(BCE_VERBOSE_RESET); 4107 4108 bce_halt_cpu(sc, cpu_reg); 4109 4110 /* Load the Text area. */ 4111 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base); 4112 if (fw->text) { 4113 int j; 4114 4115 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) { 4116 REG_WR_IND(sc, offset, fw->text[j]); 4117 } 4118 } 4119 4120 /* Load the Data area. */ 4121 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base); 4122 if (fw->data) { 4123 int j; 4124 4125 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) { 4126 REG_WR_IND(sc, offset, fw->data[j]); 4127 } 4128 } 4129 4130 /* Load the SBSS area. */ 4131 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base); 4132 if (fw->sbss) { 4133 int j; 4134 4135 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) { 4136 REG_WR_IND(sc, offset, fw->sbss[j]); 4137 } 4138 } 4139 4140 /* Load the BSS area. */ 4141 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base); 4142 if (fw->bss) { 4143 int j; 4144 4145 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) { 4146 REG_WR_IND(sc, offset, fw->bss[j]); 4147 } 4148 } 4149 4150 /* Load the Read-Only area. */ 4151 offset = cpu_reg->spad_base + 4152 (fw->rodata_addr - cpu_reg->mips_view_base); 4153 if (fw->rodata) { 4154 int j; 4155 4156 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) { 4157 REG_WR_IND(sc, offset, fw->rodata[j]); 4158 } 4159 } 4160 4161 /* Clear the pre-fetch instruction and set the FW start address. */ 4162 REG_WR_IND(sc, cpu_reg->inst, 0); 4163 REG_WR_IND(sc, cpu_reg->pc, fw->start_addr); 4164 4165 DBEXIT(BCE_VERBOSE_RESET); 4166} 4167 4168 4169/****************************************************************************/ 4170/* Starts the RISC processor. */ 4171/* */ 4172/* Assumes the CPU starting address has already been set. */ 4173/* */ 4174/* Returns: */ 4175/* Nothing. */ 4176/****************************************************************************/ 4177static void 4178bce_start_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg) 4179{ 4180 u32 val; 4181 4182 DBENTER(BCE_VERBOSE_RESET); 4183 4184 /* Start the CPU. */ 4185 val = REG_RD_IND(sc, cpu_reg->mode); 4186 val &= ~cpu_reg->mode_value_halt; 4187 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 4188 REG_WR_IND(sc, cpu_reg->mode, val); 4189 4190 DBEXIT(BCE_VERBOSE_RESET); 4191} 4192 4193 4194/****************************************************************************/ 4195/* Halts the RISC processor. */ 4196/* */ 4197/* Returns: */ 4198/* Nothing. */ 4199/****************************************************************************/ 4200static void 4201bce_halt_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg) 4202{ 4203 u32 val; 4204 4205 DBENTER(BCE_VERBOSE_RESET); 4206 4207 /* Halt the CPU. */ 4208 val = REG_RD_IND(sc, cpu_reg->mode); 4209 val |= cpu_reg->mode_value_halt; 4210 REG_WR_IND(sc, cpu_reg->mode, val); 4211 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 4212 4213 DBEXIT(BCE_VERBOSE_RESET); 4214} 4215 4216 4217/****************************************************************************/ 4218/* Initialize the RX CPU. */ 4219/* */ 4220/* Returns: */ 4221/* Nothing. */ 4222/****************************************************************************/ 4223static void 4224bce_start_rxp_cpu(struct bce_softc *sc) 4225{ 4226 struct cpu_reg cpu_reg; 4227 4228 DBENTER(BCE_VERBOSE_RESET); 4229 4230 cpu_reg.mode = BCE_RXP_CPU_MODE; 4231 cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT; 4232 cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA; 4233 cpu_reg.state = BCE_RXP_CPU_STATE; 4234 cpu_reg.state_value_clear = 0xffffff; 4235 cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE; 4236 cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK; 4237 cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER; 4238 cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION; 4239 cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT; 4240 cpu_reg.spad_base = BCE_RXP_SCRATCH; 4241 cpu_reg.mips_view_base = 0x8000000; 4242 4243 DBPRINT(sc, BCE_INFO_RESET, "Starting RX firmware.\n"); 4244 bce_start_cpu(sc, &cpu_reg); 4245 4246 DBEXIT(BCE_VERBOSE_RESET); 4247} 4248 4249 4250/****************************************************************************/ 4251/* Initialize the RX CPU. */ 4252/* */ 4253/* Returns: */ 4254/* Nothing. */ 4255/****************************************************************************/ 4256static void 4257bce_init_rxp_cpu(struct bce_softc *sc) 4258{ 4259 struct cpu_reg cpu_reg; 4260 struct fw_info fw; 4261 4262 DBENTER(BCE_VERBOSE_RESET); 4263 4264 cpu_reg.mode = BCE_RXP_CPU_MODE; 4265 cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT; 4266 cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA; 4267 cpu_reg.state = BCE_RXP_CPU_STATE; 4268 cpu_reg.state_value_clear = 0xffffff; 4269 cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE; 4270 cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK; 4271 cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER; 4272 cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION; 4273 cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT; 4274 cpu_reg.spad_base = BCE_RXP_SCRATCH; 4275 cpu_reg.mips_view_base = 0x8000000; 4276 4277 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4278 fw.ver_major = bce_RXP_b09FwReleaseMajor; 4279 fw.ver_minor = bce_RXP_b09FwReleaseMinor; 4280 fw.ver_fix = bce_RXP_b09FwReleaseFix; 4281 fw.start_addr = bce_RXP_b09FwStartAddr; 4282 4283 fw.text_addr = bce_RXP_b09FwTextAddr; 4284 fw.text_len = bce_RXP_b09FwTextLen; 4285 fw.text_index = 0; 4286 fw.text = bce_RXP_b09FwText; 4287 4288 fw.data_addr = bce_RXP_b09FwDataAddr; 4289 fw.data_len = bce_RXP_b09FwDataLen; 4290 fw.data_index = 0; 4291 fw.data = bce_RXP_b09FwData; 4292 4293 fw.sbss_addr = bce_RXP_b09FwSbssAddr; 4294 fw.sbss_len = bce_RXP_b09FwSbssLen; 4295 fw.sbss_index = 0; 4296 fw.sbss = bce_RXP_b09FwSbss; 4297 4298 fw.bss_addr = bce_RXP_b09FwBssAddr; 4299 fw.bss_len = bce_RXP_b09FwBssLen; 4300 fw.bss_index = 0; 4301 fw.bss = bce_RXP_b09FwBss; 4302 4303 fw.rodata_addr = bce_RXP_b09FwRodataAddr; 4304 fw.rodata_len = bce_RXP_b09FwRodataLen; 4305 fw.rodata_index = 0; 4306 fw.rodata = bce_RXP_b09FwRodata; 4307 } else { 4308 fw.ver_major = bce_RXP_b06FwReleaseMajor; 4309 fw.ver_minor = bce_RXP_b06FwReleaseMinor; 4310 fw.ver_fix = bce_RXP_b06FwReleaseFix; 4311 fw.start_addr = bce_RXP_b06FwStartAddr; 4312 4313 fw.text_addr = bce_RXP_b06FwTextAddr; 4314 fw.text_len = bce_RXP_b06FwTextLen; 4315 fw.text_index = 0; 4316 fw.text = bce_RXP_b06FwText; 4317 4318 fw.data_addr = bce_RXP_b06FwDataAddr; 4319 fw.data_len = bce_RXP_b06FwDataLen; 4320 fw.data_index = 0; 4321 fw.data = bce_RXP_b06FwData; 4322 4323 fw.sbss_addr = bce_RXP_b06FwSbssAddr; 4324 fw.sbss_len = bce_RXP_b06FwSbssLen; 4325 fw.sbss_index = 0; 4326 fw.sbss = bce_RXP_b06FwSbss; 4327 4328 fw.bss_addr = bce_RXP_b06FwBssAddr; 4329 fw.bss_len = bce_RXP_b06FwBssLen; 4330 fw.bss_index = 0; 4331 fw.bss = bce_RXP_b06FwBss; 4332 4333 fw.rodata_addr = bce_RXP_b06FwRodataAddr; 4334 fw.rodata_len = bce_RXP_b06FwRodataLen; 4335 fw.rodata_index = 0; 4336 fw.rodata = bce_RXP_b06FwRodata; 4337 } 4338 4339 DBPRINT(sc, BCE_INFO_RESET, "Loading RX firmware.\n"); 4340 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4341 4342 /* Delay RXP start until initialization is complete. */ 4343 4344 DBEXIT(BCE_VERBOSE_RESET); 4345} 4346 4347 4348/****************************************************************************/ 4349/* Initialize the TX CPU. */ 4350/* */ 4351/* Returns: */ 4352/* Nothing. */ 4353/****************************************************************************/ 4354static void 4355bce_init_txp_cpu(struct bce_softc *sc) 4356{ 4357 struct cpu_reg cpu_reg; 4358 struct fw_info fw; 4359 4360 DBENTER(BCE_VERBOSE_RESET); 4361 4362 cpu_reg.mode = BCE_TXP_CPU_MODE; 4363 cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT; 4364 cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA; 4365 cpu_reg.state = BCE_TXP_CPU_STATE; 4366 cpu_reg.state_value_clear = 0xffffff; 4367 cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE; 4368 cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK; 4369 cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER; 4370 cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION; 4371 cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT; 4372 cpu_reg.spad_base = BCE_TXP_SCRATCH; 4373 cpu_reg.mips_view_base = 0x8000000; 4374 4375 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4376 fw.ver_major = bce_TXP_b09FwReleaseMajor; 4377 fw.ver_minor = bce_TXP_b09FwReleaseMinor; 4378 fw.ver_fix = bce_TXP_b09FwReleaseFix; 4379 fw.start_addr = bce_TXP_b09FwStartAddr; 4380 4381 fw.text_addr = bce_TXP_b09FwTextAddr; 4382 fw.text_len = bce_TXP_b09FwTextLen; 4383 fw.text_index = 0; 4384 fw.text = bce_TXP_b09FwText; 4385 4386 fw.data_addr = bce_TXP_b09FwDataAddr; 4387 fw.data_len = bce_TXP_b09FwDataLen; 4388 fw.data_index = 0; 4389 fw.data = bce_TXP_b09FwData; 4390 4391 fw.sbss_addr = bce_TXP_b09FwSbssAddr; 4392 fw.sbss_len = bce_TXP_b09FwSbssLen; 4393 fw.sbss_index = 0; 4394 fw.sbss = bce_TXP_b09FwSbss; 4395 4396 fw.bss_addr = bce_TXP_b09FwBssAddr; 4397 fw.bss_len = bce_TXP_b09FwBssLen; 4398 fw.bss_index = 0; 4399 fw.bss = bce_TXP_b09FwBss; 4400 4401 fw.rodata_addr = bce_TXP_b09FwRodataAddr; 4402 fw.rodata_len = bce_TXP_b09FwRodataLen; 4403 fw.rodata_index = 0; 4404 fw.rodata = bce_TXP_b09FwRodata; 4405 } else { 4406 fw.ver_major = bce_TXP_b06FwReleaseMajor; 4407 fw.ver_minor = bce_TXP_b06FwReleaseMinor; 4408 fw.ver_fix = bce_TXP_b06FwReleaseFix; 4409 fw.start_addr = bce_TXP_b06FwStartAddr; 4410 4411 fw.text_addr = bce_TXP_b06FwTextAddr; 4412 fw.text_len = bce_TXP_b06FwTextLen; 4413 fw.text_index = 0; 4414 fw.text = bce_TXP_b06FwText; 4415 4416 fw.data_addr = bce_TXP_b06FwDataAddr; 4417 fw.data_len = bce_TXP_b06FwDataLen; 4418 fw.data_index = 0; 4419 fw.data = bce_TXP_b06FwData; 4420 4421 fw.sbss_addr = bce_TXP_b06FwSbssAddr; 4422 fw.sbss_len = bce_TXP_b06FwSbssLen; 4423 fw.sbss_index = 0; 4424 fw.sbss = bce_TXP_b06FwSbss; 4425 4426 fw.bss_addr = bce_TXP_b06FwBssAddr; 4427 fw.bss_len = bce_TXP_b06FwBssLen; 4428 fw.bss_index = 0; 4429 fw.bss = bce_TXP_b06FwBss; 4430 4431 fw.rodata_addr = bce_TXP_b06FwRodataAddr; 4432 fw.rodata_len = bce_TXP_b06FwRodataLen; 4433 fw.rodata_index = 0; 4434 fw.rodata = bce_TXP_b06FwRodata; 4435 } 4436 4437 DBPRINT(sc, BCE_INFO_RESET, "Loading TX firmware.\n"); 4438 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4439 bce_start_cpu(sc, &cpu_reg); 4440 4441 DBEXIT(BCE_VERBOSE_RESET); 4442} 4443 4444 4445/****************************************************************************/ 4446/* Initialize the TPAT CPU. */ 4447/* */ 4448/* Returns: */ 4449/* Nothing. */ 4450/****************************************************************************/ 4451static void 4452bce_init_tpat_cpu(struct bce_softc *sc) 4453{ 4454 struct cpu_reg cpu_reg; 4455 struct fw_info fw; 4456 4457 DBENTER(BCE_VERBOSE_RESET); 4458 4459 cpu_reg.mode = BCE_TPAT_CPU_MODE; 4460 cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT; 4461 cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA; 4462 cpu_reg.state = BCE_TPAT_CPU_STATE; 4463 cpu_reg.state_value_clear = 0xffffff; 4464 cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE; 4465 cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK; 4466 cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER; 4467 cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION; 4468 cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT; 4469 cpu_reg.spad_base = BCE_TPAT_SCRATCH; 4470 cpu_reg.mips_view_base = 0x8000000; 4471 4472 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4473 fw.ver_major = bce_TPAT_b09FwReleaseMajor; 4474 fw.ver_minor = bce_TPAT_b09FwReleaseMinor; 4475 fw.ver_fix = bce_TPAT_b09FwReleaseFix; 4476 fw.start_addr = bce_TPAT_b09FwStartAddr; 4477 4478 fw.text_addr = bce_TPAT_b09FwTextAddr; 4479 fw.text_len = bce_TPAT_b09FwTextLen; 4480 fw.text_index = 0; 4481 fw.text = bce_TPAT_b09FwText; 4482 4483 fw.data_addr = bce_TPAT_b09FwDataAddr; 4484 fw.data_len = bce_TPAT_b09FwDataLen; 4485 fw.data_index = 0; 4486 fw.data = bce_TPAT_b09FwData; 4487 4488 fw.sbss_addr = bce_TPAT_b09FwSbssAddr; 4489 fw.sbss_len = bce_TPAT_b09FwSbssLen; 4490 fw.sbss_index = 0; 4491 fw.sbss = bce_TPAT_b09FwSbss; 4492 4493 fw.bss_addr = bce_TPAT_b09FwBssAddr; 4494 fw.bss_len = bce_TPAT_b09FwBssLen; 4495 fw.bss_index = 0; 4496 fw.bss = bce_TPAT_b09FwBss; 4497 4498 fw.rodata_addr = bce_TPAT_b09FwRodataAddr; 4499 fw.rodata_len = bce_TPAT_b09FwRodataLen; 4500 fw.rodata_index = 0; 4501 fw.rodata = bce_TPAT_b09FwRodata; 4502 } else { 4503 fw.ver_major = bce_TPAT_b06FwReleaseMajor; 4504 fw.ver_minor = bce_TPAT_b06FwReleaseMinor; 4505 fw.ver_fix = bce_TPAT_b06FwReleaseFix; 4506 fw.start_addr = bce_TPAT_b06FwStartAddr; 4507 4508 fw.text_addr = bce_TPAT_b06FwTextAddr; 4509 fw.text_len = bce_TPAT_b06FwTextLen; 4510 fw.text_index = 0; 4511 fw.text = bce_TPAT_b06FwText; 4512 4513 fw.data_addr = bce_TPAT_b06FwDataAddr; 4514 fw.data_len = bce_TPAT_b06FwDataLen; 4515 fw.data_index = 0; 4516 fw.data = bce_TPAT_b06FwData; 4517 4518 fw.sbss_addr = bce_TPAT_b06FwSbssAddr; 4519 fw.sbss_len = bce_TPAT_b06FwSbssLen; 4520 fw.sbss_index = 0; 4521 fw.sbss = bce_TPAT_b06FwSbss; 4522 4523 fw.bss_addr = bce_TPAT_b06FwBssAddr; 4524 fw.bss_len = bce_TPAT_b06FwBssLen; 4525 fw.bss_index = 0; 4526 fw.bss = bce_TPAT_b06FwBss; 4527 4528 fw.rodata_addr = bce_TPAT_b06FwRodataAddr; 4529 fw.rodata_len = bce_TPAT_b06FwRodataLen; 4530 fw.rodata_index = 0; 4531 fw.rodata = bce_TPAT_b06FwRodata; 4532 } 4533 4534 DBPRINT(sc, BCE_INFO_RESET, "Loading TPAT firmware.\n"); 4535 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4536 bce_start_cpu(sc, &cpu_reg); 4537 4538 DBEXIT(BCE_VERBOSE_RESET); 4539} 4540 4541 4542/****************************************************************************/ 4543/* Initialize the CP CPU. */ 4544/* */ 4545/* Returns: */ 4546/* Nothing. */ 4547/****************************************************************************/ 4548static void 4549bce_init_cp_cpu(struct bce_softc *sc) 4550{ 4551 struct cpu_reg cpu_reg; 4552 struct fw_info fw; 4553 4554 DBENTER(BCE_VERBOSE_RESET); 4555 4556 cpu_reg.mode = BCE_CP_CPU_MODE; 4557 cpu_reg.mode_value_halt = BCE_CP_CPU_MODE_SOFT_HALT; 4558 cpu_reg.mode_value_sstep = BCE_CP_CPU_MODE_STEP_ENA; 4559 cpu_reg.state = BCE_CP_CPU_STATE; 4560 cpu_reg.state_value_clear = 0xffffff; 4561 cpu_reg.gpr0 = BCE_CP_CPU_REG_FILE; 4562 cpu_reg.evmask = BCE_CP_CPU_EVENT_MASK; 4563 cpu_reg.pc = BCE_CP_CPU_PROGRAM_COUNTER; 4564 cpu_reg.inst = BCE_CP_CPU_INSTRUCTION; 4565 cpu_reg.bp = BCE_CP_CPU_HW_BREAKPOINT; 4566 cpu_reg.spad_base = BCE_CP_SCRATCH; 4567 cpu_reg.mips_view_base = 0x8000000; 4568 4569 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4570 fw.ver_major = bce_CP_b09FwReleaseMajor; 4571 fw.ver_minor = bce_CP_b09FwReleaseMinor; 4572 fw.ver_fix = bce_CP_b09FwReleaseFix; 4573 fw.start_addr = bce_CP_b09FwStartAddr; 4574 4575 fw.text_addr = bce_CP_b09FwTextAddr; 4576 fw.text_len = bce_CP_b09FwTextLen; 4577 fw.text_index = 0; 4578 fw.text = bce_CP_b09FwText; 4579 4580 fw.data_addr = bce_CP_b09FwDataAddr; 4581 fw.data_len = bce_CP_b09FwDataLen; 4582 fw.data_index = 0; 4583 fw.data = bce_CP_b09FwData; 4584 4585 fw.sbss_addr = bce_CP_b09FwSbssAddr; 4586 fw.sbss_len = bce_CP_b09FwSbssLen; 4587 fw.sbss_index = 0; 4588 fw.sbss = bce_CP_b09FwSbss; 4589 4590 fw.bss_addr = bce_CP_b09FwBssAddr; 4591 fw.bss_len = bce_CP_b09FwBssLen; 4592 fw.bss_index = 0; 4593 fw.bss = bce_CP_b09FwBss; 4594 4595 fw.rodata_addr = bce_CP_b09FwRodataAddr; 4596 fw.rodata_len = bce_CP_b09FwRodataLen; 4597 fw.rodata_index = 0; 4598 fw.rodata = bce_CP_b09FwRodata; 4599 } else { 4600 fw.ver_major = bce_CP_b06FwReleaseMajor; 4601 fw.ver_minor = bce_CP_b06FwReleaseMinor; 4602 fw.ver_fix = bce_CP_b06FwReleaseFix; 4603 fw.start_addr = bce_CP_b06FwStartAddr; 4604 4605 fw.text_addr = bce_CP_b06FwTextAddr; 4606 fw.text_len = bce_CP_b06FwTextLen; 4607 fw.text_index = 0; 4608 fw.text = bce_CP_b06FwText; 4609 4610 fw.data_addr = bce_CP_b06FwDataAddr; 4611 fw.data_len = bce_CP_b06FwDataLen; 4612 fw.data_index = 0; 4613 fw.data = bce_CP_b06FwData; 4614 4615 fw.sbss_addr = bce_CP_b06FwSbssAddr; 4616 fw.sbss_len = bce_CP_b06FwSbssLen; 4617 fw.sbss_index = 0; 4618 fw.sbss = bce_CP_b06FwSbss; 4619 4620 fw.bss_addr = bce_CP_b06FwBssAddr; 4621 fw.bss_len = bce_CP_b06FwBssLen; 4622 fw.bss_index = 0; 4623 fw.bss = bce_CP_b06FwBss; 4624 4625 fw.rodata_addr = bce_CP_b06FwRodataAddr; 4626 fw.rodata_len = bce_CP_b06FwRodataLen; 4627 fw.rodata_index = 0; 4628 fw.rodata = bce_CP_b06FwRodata; 4629 } 4630 4631 DBPRINT(sc, BCE_INFO_RESET, "Loading CP firmware.\n"); 4632 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4633 bce_start_cpu(sc, &cpu_reg); 4634 4635 DBEXIT(BCE_VERBOSE_RESET); 4636} 4637 4638 4639/****************************************************************************/ 4640/* Initialize the COM CPU. */ 4641/* */ 4642/* Returns: */ 4643/* Nothing. */ 4644/****************************************************************************/ 4645static void 4646bce_init_com_cpu(struct bce_softc *sc) 4647{ 4648 struct cpu_reg cpu_reg; 4649 struct fw_info fw; 4650 4651 DBENTER(BCE_VERBOSE_RESET); 4652 4653 cpu_reg.mode = BCE_COM_CPU_MODE; 4654 cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT; 4655 cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA; 4656 cpu_reg.state = BCE_COM_CPU_STATE; 4657 cpu_reg.state_value_clear = 0xffffff; 4658 cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE; 4659 cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK; 4660 cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER; 4661 cpu_reg.inst = BCE_COM_CPU_INSTRUCTION; 4662 cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT; 4663 cpu_reg.spad_base = BCE_COM_SCRATCH; 4664 cpu_reg.mips_view_base = 0x8000000; 4665 4666 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4667 fw.ver_major = bce_COM_b09FwReleaseMajor; 4668 fw.ver_minor = bce_COM_b09FwReleaseMinor; 4669 fw.ver_fix = bce_COM_b09FwReleaseFix; 4670 fw.start_addr = bce_COM_b09FwStartAddr; 4671 4672 fw.text_addr = bce_COM_b09FwTextAddr; 4673 fw.text_len = bce_COM_b09FwTextLen; 4674 fw.text_index = 0; 4675 fw.text = bce_COM_b09FwText; 4676 4677 fw.data_addr = bce_COM_b09FwDataAddr; 4678 fw.data_len = bce_COM_b09FwDataLen; 4679 fw.data_index = 0; 4680 fw.data = bce_COM_b09FwData; 4681 4682 fw.sbss_addr = bce_COM_b09FwSbssAddr; 4683 fw.sbss_len = bce_COM_b09FwSbssLen; 4684 fw.sbss_index = 0; 4685 fw.sbss = bce_COM_b09FwSbss; 4686 4687 fw.bss_addr = bce_COM_b09FwBssAddr; 4688 fw.bss_len = bce_COM_b09FwBssLen; 4689 fw.bss_index = 0; 4690 fw.bss = bce_COM_b09FwBss; 4691 4692 fw.rodata_addr = bce_COM_b09FwRodataAddr; 4693 fw.rodata_len = bce_COM_b09FwRodataLen; 4694 fw.rodata_index = 0; 4695 fw.rodata = bce_COM_b09FwRodata; 4696 } else { 4697 fw.ver_major = bce_COM_b06FwReleaseMajor; 4698 fw.ver_minor = bce_COM_b06FwReleaseMinor; 4699 fw.ver_fix = bce_COM_b06FwReleaseFix; 4700 fw.start_addr = bce_COM_b06FwStartAddr; 4701 4702 fw.text_addr = bce_COM_b06FwTextAddr; 4703 fw.text_len = bce_COM_b06FwTextLen; 4704 fw.text_index = 0; 4705 fw.text = bce_COM_b06FwText; 4706 4707 fw.data_addr = bce_COM_b06FwDataAddr; 4708 fw.data_len = bce_COM_b06FwDataLen; 4709 fw.data_index = 0; 4710 fw.data = bce_COM_b06FwData; 4711 4712 fw.sbss_addr = bce_COM_b06FwSbssAddr; 4713 fw.sbss_len = bce_COM_b06FwSbssLen; 4714 fw.sbss_index = 0; 4715 fw.sbss = bce_COM_b06FwSbss; 4716 4717 fw.bss_addr = bce_COM_b06FwBssAddr; 4718 fw.bss_len = bce_COM_b06FwBssLen; 4719 fw.bss_index = 0; 4720 fw.bss = bce_COM_b06FwBss; 4721 4722 fw.rodata_addr = bce_COM_b06FwRodataAddr; 4723 fw.rodata_len = bce_COM_b06FwRodataLen; 4724 fw.rodata_index = 0; 4725 fw.rodata = bce_COM_b06FwRodata; 4726 } 4727 4728 DBPRINT(sc, BCE_INFO_RESET, "Loading COM firmware.\n"); 4729 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4730 bce_start_cpu(sc, &cpu_reg); 4731 4732 DBEXIT(BCE_VERBOSE_RESET); 4733} 4734 4735 4736/****************************************************************************/ 4737/* Initialize the RV2P, RX, TX, TPAT, COM, and CP CPUs. */ 4738/* */ 4739/* Loads the firmware for each CPU and starts the CPU. */ 4740/* */ 4741/* Returns: */ 4742/* Nothing. */ 4743/****************************************************************************/ 4744static void 4745bce_init_cpus(struct bce_softc *sc) 4746{ 4747 DBENTER(BCE_VERBOSE_RESET); 4748 4749 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4750 4751 if ((BCE_CHIP_REV(sc) == BCE_CHIP_REV_Ax)) { 4752 bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc1, 4753 sizeof(bce_xi90_rv2p_proc1), RV2P_PROC1); 4754 bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc2, 4755 sizeof(bce_xi90_rv2p_proc2), RV2P_PROC2); 4756 } else { 4757 bce_load_rv2p_fw(sc, bce_xi_rv2p_proc1, 4758 sizeof(bce_xi_rv2p_proc1), RV2P_PROC1); 4759 bce_load_rv2p_fw(sc, bce_xi_rv2p_proc2, 4760 sizeof(bce_xi_rv2p_proc2), RV2P_PROC2); 4761 } 4762 4763 } else { 4764 bce_load_rv2p_fw(sc, bce_rv2p_proc1, 4765 sizeof(bce_rv2p_proc1), RV2P_PROC1); 4766 bce_load_rv2p_fw(sc, bce_rv2p_proc2, 4767 sizeof(bce_rv2p_proc2), RV2P_PROC2); 4768 } 4769 4770 bce_init_rxp_cpu(sc); 4771 bce_init_txp_cpu(sc); 4772 bce_init_tpat_cpu(sc); 4773 bce_init_com_cpu(sc); 4774 bce_init_cp_cpu(sc); 4775 4776 DBEXIT(BCE_VERBOSE_RESET); 4777} 4778 4779 4780/****************************************************************************/ 4781/* Initialize context memory. */ 4782/* */ 4783/* Clears the memory associated with each Context ID (CID). */ 4784/* */ 4785/* Returns: */ 4786/* Nothing. */ 4787/****************************************************************************/ 4788static int 4789bce_init_ctx(struct bce_softc *sc) 4790{ 4791 u32 offset, val, vcid_addr; 4792 int i, j, rc, retry_cnt; 4793 4794 rc = 0; 4795 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 4796 4797 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4798 retry_cnt = CTX_INIT_RETRY_COUNT; 4799 4800 DBPRINT(sc, BCE_INFO_CTX, "Initializing 5709 context.\n"); 4801 4802 /* 4803 * BCM5709 context memory may be cached 4804 * in host memory so prepare the host memory 4805 * for access. 4806 */ 4807 val = BCE_CTX_COMMAND_ENABLED | 4808 BCE_CTX_COMMAND_MEM_INIT | (1 << 12); 4809 val |= (BCM_PAGE_BITS - 8) << 16; 4810 REG_WR(sc, BCE_CTX_COMMAND, val); 4811 4812 /* Wait for mem init command to complete. */ 4813 for (i = 0; i < retry_cnt; i++) { 4814 val = REG_RD(sc, BCE_CTX_COMMAND); 4815 if (!(val & BCE_CTX_COMMAND_MEM_INIT)) 4816 break; 4817 DELAY(2); 4818 } 4819 if ((val & BCE_CTX_COMMAND_MEM_INIT) != 0) { 4820 BCE_PRINTF("%s(): Context memory initialization failed!\n", 4821 __FUNCTION__); 4822 rc = EBUSY; 4823 goto init_ctx_fail; 4824 } 4825 4826 for (i = 0; i < sc->ctx_pages; i++) { 4827 /* Set the physical address of the context memory. */ 4828 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA0, 4829 BCE_ADDR_LO(sc->ctx_paddr[i] & 0xfffffff0) | 4830 BCE_CTX_HOST_PAGE_TBL_DATA0_VALID); 4831 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA1, 4832 BCE_ADDR_HI(sc->ctx_paddr[i])); 4833 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_CTRL, i | 4834 BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ); 4835 4836 /* Verify the context memory write was successful. */ 4837 for (j = 0; j < retry_cnt; j++) { 4838 val = REG_RD(sc, BCE_CTX_HOST_PAGE_TBL_CTRL); 4839 if ((val & 4840 BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0) 4841 break; 4842 DELAY(5); 4843 } 4844 if ((val & BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) != 0) { 4845 BCE_PRINTF("%s(): Failed to initialize " 4846 "context page %d!\n", __FUNCTION__, i); 4847 rc = EBUSY; 4848 goto init_ctx_fail; 4849 } 4850 } 4851 } else { 4852 4853 DBPRINT(sc, BCE_INFO, "Initializing 5706/5708 context.\n"); 4854 4855 /* 4856 * For the 5706/5708, context memory is local to 4857 * the controller, so initialize the controller 4858 * context memory. 4859 */ 4860 4861 vcid_addr = GET_CID_ADDR(96); 4862 while (vcid_addr) { 4863 4864 vcid_addr -= PHY_CTX_SIZE; 4865 4866 REG_WR(sc, BCE_CTX_VIRT_ADDR, 0); 4867 REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr); 4868 4869 for(offset = 0; offset < PHY_CTX_SIZE; offset += 4) { 4870 CTX_WR(sc, 0x00, offset, 0); 4871 } 4872 4873 REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr); 4874 REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr); 4875 } 4876 4877 } 4878init_ctx_fail: 4879 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 4880 return (rc); 4881} 4882 4883 4884/****************************************************************************/ 4885/* Fetch the permanent MAC address of the controller. */ 4886/* */ 4887/* Returns: */ 4888/* Nothing. */ 4889/****************************************************************************/ 4890static void 4891bce_get_mac_addr(struct bce_softc *sc) 4892{ 4893 u32 mac_lo = 0, mac_hi = 0; 4894 4895 DBENTER(BCE_VERBOSE_RESET); 4896 4897 /* 4898 * The NetXtreme II bootcode populates various NIC 4899 * power-on and runtime configuration items in a 4900 * shared memory area. The factory configured MAC 4901 * address is available from both NVRAM and the 4902 * shared memory area so we'll read the value from 4903 * shared memory for speed. 4904 */ 4905 4906 mac_hi = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_UPPER); 4907 mac_lo = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_LOWER); 4908 4909 if ((mac_lo == 0) && (mac_hi == 0)) { 4910 BCE_PRINTF("%s(%d): Invalid Ethernet address!\n", 4911 __FILE__, __LINE__); 4912 } else { 4913 sc->eaddr[0] = (u_char)(mac_hi >> 8); 4914 sc->eaddr[1] = (u_char)(mac_hi >> 0); 4915 sc->eaddr[2] = (u_char)(mac_lo >> 24); 4916 sc->eaddr[3] = (u_char)(mac_lo >> 16); 4917 sc->eaddr[4] = (u_char)(mac_lo >> 8); 4918 sc->eaddr[5] = (u_char)(mac_lo >> 0); 4919 } 4920 4921 DBPRINT(sc, BCE_INFO_MISC, "Permanent Ethernet " 4922 "address = %6D\n", sc->eaddr, ":"); 4923 DBEXIT(BCE_VERBOSE_RESET); 4924} 4925 4926 4927/****************************************************************************/ 4928/* Program the MAC address. */ 4929/* */ 4930/* Returns: */ 4931/* Nothing. */ 4932/****************************************************************************/ 4933static void 4934bce_set_mac_addr(struct bce_softc *sc) 4935{ 4936 u32 val; 4937 u8 *mac_addr = sc->eaddr; 4938 4939 /* ToDo: Add support for setting multiple MAC addresses. */ 4940 4941 DBENTER(BCE_VERBOSE_RESET); 4942 DBPRINT(sc, BCE_INFO_MISC, "Setting Ethernet address = " 4943 "%6D\n", sc->eaddr, ":"); 4944 4945 val = (mac_addr[0] << 8) | mac_addr[1]; 4946 4947 REG_WR(sc, BCE_EMAC_MAC_MATCH0, val); 4948 4949 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 4950 (mac_addr[4] << 8) | mac_addr[5]; 4951 4952 REG_WR(sc, BCE_EMAC_MAC_MATCH1, val); 4953 4954 DBEXIT(BCE_VERBOSE_RESET); 4955} 4956 4957 4958/****************************************************************************/ 4959/* Stop the controller. */ 4960/* */ 4961/* Returns: */ 4962/* Nothing. */ 4963/****************************************************************************/ 4964static void 4965bce_stop(struct bce_softc *sc) 4966{ 4967 struct ifnet *ifp; 4968 4969 DBENTER(BCE_VERBOSE_RESET); 4970 4971 BCE_LOCK_ASSERT(sc); 4972 4973 ifp = sc->bce_ifp; 4974 4975 callout_stop(&sc->bce_tick_callout); 4976 4977 /* Disable the transmit/receive blocks. */ 4978 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, BCE_MISC_ENABLE_CLR_DEFAULT); 4979 REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS); 4980 DELAY(20); 4981 4982 bce_disable_intr(sc); 4983 4984 /* Free RX buffers. */ 4985 if (bce_hdr_split == TRUE) { 4986 bce_free_pg_chain(sc); 4987 } 4988 bce_free_rx_chain(sc); 4989 4990 /* Free TX buffers. */ 4991 bce_free_tx_chain(sc); 4992 4993 sc->watchdog_timer = 0; 4994 4995 sc->bce_link_up = FALSE; 4996 4997 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 4998 4999 DBEXIT(BCE_VERBOSE_RESET); 5000} 5001 5002 5003static int 5004bce_reset(struct bce_softc *sc, u32 reset_code) 5005{ 5006 u32 emac_mode_save, val; 5007 int i, rc = 0; 5008 static const u32 emac_mode_mask = BCE_EMAC_MODE_PORT | 5009 BCE_EMAC_MODE_HALF_DUPLEX | BCE_EMAC_MODE_25G; 5010 5011 DBENTER(BCE_VERBOSE_RESET); 5012 5013 DBPRINT(sc, BCE_VERBOSE_RESET, "%s(): reset_code = 0x%08X\n", 5014 __FUNCTION__, reset_code); 5015 5016 /* 5017 * If ASF/IPMI is operational, then the EMAC Mode register already 5018 * contains appropriate values for the link settings that have 5019 * been auto-negotiated. Resetting the chip will clobber those 5020 * values. Save the important bits so we can restore them after 5021 * the reset. 5022 */ 5023 emac_mode_save = REG_RD(sc, BCE_EMAC_MODE) & emac_mode_mask; 5024 5025 /* Wait for pending PCI transactions to complete. */ 5026 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, 5027 BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE | 5028 BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE | 5029 BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE | 5030 BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE); 5031 val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS); 5032 DELAY(5); 5033 5034 /* Disable DMA */ 5035 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5036 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL); 5037 val &= ~BCE_MISC_NEW_CORE_CTL_DMA_ENABLE; 5038 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val); 5039 } 5040 5041 /* Assume bootcode is running. */ 5042 sc->bce_fw_timed_out = FALSE; 5043 sc->bce_drv_cardiac_arrest = FALSE; 5044 5045 /* Give the firmware a chance to prepare for the reset. */ 5046 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT0 | reset_code); 5047 if (rc) 5048 goto bce_reset_exit; 5049 5050 /* Set a firmware reminder that this is a soft reset. */ 5051 bce_shmem_wr(sc, BCE_DRV_RESET_SIGNATURE, BCE_DRV_RESET_SIGNATURE_MAGIC); 5052 5053 /* Dummy read to force the chip to complete all current transactions. */ 5054 val = REG_RD(sc, BCE_MISC_ID); 5055 5056 /* Chip reset. */ 5057 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5058 REG_WR(sc, BCE_MISC_COMMAND, BCE_MISC_COMMAND_SW_RESET); 5059 REG_RD(sc, BCE_MISC_COMMAND); 5060 DELAY(5); 5061 5062 val = BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 5063 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 5064 5065 pci_write_config(sc->bce_dev, BCE_PCICFG_MISC_CONFIG, val, 4); 5066 } else { 5067 val = BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 5068 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 5069 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 5070 REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val); 5071 5072 /* Allow up to 30us for reset to complete. */ 5073 for (i = 0; i < 10; i++) { 5074 val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG); 5075 if ((val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 5076 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) { 5077 break; 5078 } 5079 DELAY(10); 5080 } 5081 5082 /* Check that reset completed successfully. */ 5083 if (val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 5084 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) { 5085 BCE_PRINTF("%s(%d): Reset failed!\n", 5086 __FILE__, __LINE__); 5087 rc = EBUSY; 5088 goto bce_reset_exit; 5089 } 5090 } 5091 5092 /* Make sure byte swapping is properly configured. */ 5093 val = REG_RD(sc, BCE_PCI_SWAP_DIAG0); 5094 if (val != 0x01020304) { 5095 BCE_PRINTF("%s(%d): Byte swap is incorrect!\n", 5096 __FILE__, __LINE__); 5097 rc = ENODEV; 5098 goto bce_reset_exit; 5099 } 5100 5101 /* Just completed a reset, assume that firmware is running again. */ 5102 sc->bce_fw_timed_out = FALSE; 5103 sc->bce_drv_cardiac_arrest = FALSE; 5104 5105 /* Wait for the firmware to finish its initialization. */ 5106 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT1 | reset_code); 5107 if (rc) 5108 BCE_PRINTF("%s(%d): Firmware did not complete " 5109 "initialization!\n", __FILE__, __LINE__); 5110 /* Get firmware capabilities. */ 5111 bce_fw_cap_init(sc); 5112 5113bce_reset_exit: 5114 /* Restore EMAC Mode bits needed to keep ASF/IPMI running. */ 5115 if (reset_code == BCE_DRV_MSG_CODE_RESET) { 5116 val = REG_RD(sc, BCE_EMAC_MODE); 5117 val = (val & ~emac_mode_mask) | emac_mode_save; 5118 REG_WR(sc, BCE_EMAC_MODE, val); 5119 } 5120 5121 DBEXIT(BCE_VERBOSE_RESET); 5122 return (rc); 5123} 5124 5125 5126static int 5127bce_chipinit(struct bce_softc *sc) 5128{ 5129 u32 val; 5130 int rc = 0; 5131 5132 DBENTER(BCE_VERBOSE_RESET); 5133 5134 bce_disable_intr(sc); 5135 5136 /* 5137 * Initialize DMA byte/word swapping, configure the number of DMA 5138 * channels and PCI clock compensation delay. 5139 */ 5140 val = BCE_DMA_CONFIG_DATA_BYTE_SWAP | 5141 BCE_DMA_CONFIG_DATA_WORD_SWAP | 5142#if BYTE_ORDER == BIG_ENDIAN 5143 BCE_DMA_CONFIG_CNTL_BYTE_SWAP | 5144#endif 5145 BCE_DMA_CONFIG_CNTL_WORD_SWAP | 5146 DMA_READ_CHANS << 12 | 5147 DMA_WRITE_CHANS << 16; 5148 5149 val |= (0x2 << 20) | BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY; 5150 5151 if ((sc->bce_flags & BCE_PCIX_FLAG) && (sc->bus_speed_mhz == 133)) 5152 val |= BCE_DMA_CONFIG_PCI_FAST_CLK_CMP; 5153 5154 /* 5155 * This setting resolves a problem observed on certain Intel PCI 5156 * chipsets that cannot handle multiple outstanding DMA operations. 5157 * See errata E9_5706A1_65. 5158 */ 5159 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) && 5160 (BCE_CHIP_ID(sc) != BCE_CHIP_ID_5706_A0) && 5161 !(sc->bce_flags & BCE_PCIX_FLAG)) 5162 val |= BCE_DMA_CONFIG_CNTL_PING_PONG_DMA; 5163 5164 REG_WR(sc, BCE_DMA_CONFIG, val); 5165 5166 /* Enable the RX_V2P and Context state machines before access. */ 5167 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 5168 BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE | 5169 BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE | 5170 BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE); 5171 5172 /* Initialize context mapping and zero out the quick contexts. */ 5173 if ((rc = bce_init_ctx(sc)) != 0) 5174 goto bce_chipinit_exit; 5175 5176 /* Initialize the on-boards CPUs */ 5177 bce_init_cpus(sc); 5178 5179 /* Enable management frames (NC-SI) to flow to the MCP. */ 5180 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 5181 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) | BCE_RPM_MGMT_PKT_CTRL_MGMT_EN; 5182 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val); 5183 } 5184 5185 /* Prepare NVRAM for access. */ 5186 if ((rc = bce_init_nvram(sc)) != 0) 5187 goto bce_chipinit_exit; 5188 5189 /* Set the kernel bypass block size */ 5190 val = REG_RD(sc, BCE_MQ_CONFIG); 5191 val &= ~BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE; 5192 val |= BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256; 5193 5194 /* Enable bins used on the 5709. */ 5195 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5196 val |= BCE_MQ_CONFIG_BIN_MQ_MODE; 5197 if (BCE_CHIP_ID(sc) == BCE_CHIP_ID_5709_A1) 5198 val |= BCE_MQ_CONFIG_HALT_DIS; 5199 } 5200 5201 REG_WR(sc, BCE_MQ_CONFIG, val); 5202 5203 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE); 5204 REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val); 5205 REG_WR(sc, BCE_MQ_KNL_WIND_END, val); 5206 5207 /* Set the page size and clear the RV2P processor stall bits. */ 5208 val = (BCM_PAGE_BITS - 8) << 24; 5209 REG_WR(sc, BCE_RV2P_CONFIG, val); 5210 5211 /* Configure page size. */ 5212 val = REG_RD(sc, BCE_TBDR_CONFIG); 5213 val &= ~BCE_TBDR_CONFIG_PAGE_SIZE; 5214 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40; 5215 REG_WR(sc, BCE_TBDR_CONFIG, val); 5216 5217 /* Set the perfect match control register to default. */ 5218 REG_WR_IND(sc, BCE_RXP_PM_CTRL, 0); 5219 5220bce_chipinit_exit: 5221 DBEXIT(BCE_VERBOSE_RESET); 5222 5223 return(rc); 5224} 5225 5226 5227/****************************************************************************/ 5228/* Initialize the controller in preparation to send/receive traffic. */ 5229/* */ 5230/* Returns: */ 5231/* 0 for success, positive value for failure. */ 5232/****************************************************************************/ 5233static int 5234bce_blockinit(struct bce_softc *sc) 5235{ 5236 u32 reg, val; 5237 int rc = 0; 5238 5239 DBENTER(BCE_VERBOSE_RESET); 5240 5241 /* Load the hardware default MAC address. */ 5242 bce_set_mac_addr(sc); 5243 5244 /* Set the Ethernet backoff seed value */ 5245 val = sc->eaddr[0] + (sc->eaddr[1] << 8) + 5246 (sc->eaddr[2] << 16) + (sc->eaddr[3] ) + 5247 (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16); 5248 REG_WR(sc, BCE_EMAC_BACKOFF_SEED, val); 5249 5250 sc->last_status_idx = 0; 5251 sc->rx_mode = BCE_EMAC_RX_MODE_SORT_MODE; 5252 5253 /* Set up link change interrupt generation. */ 5254 REG_WR(sc, BCE_EMAC_ATTENTION_ENA, BCE_EMAC_ATTENTION_ENA_LINK); 5255 5256 /* Program the physical address of the status block. */ 5257 REG_WR(sc, BCE_HC_STATUS_ADDR_L, 5258 BCE_ADDR_LO(sc->status_block_paddr)); 5259 REG_WR(sc, BCE_HC_STATUS_ADDR_H, 5260 BCE_ADDR_HI(sc->status_block_paddr)); 5261 5262 /* Program the physical address of the statistics block. */ 5263 REG_WR(sc, BCE_HC_STATISTICS_ADDR_L, 5264 BCE_ADDR_LO(sc->stats_block_paddr)); 5265 REG_WR(sc, BCE_HC_STATISTICS_ADDR_H, 5266 BCE_ADDR_HI(sc->stats_block_paddr)); 5267 5268 /* 5269 * Program various host coalescing parameters. 5270 * Trip points control how many BDs should be ready before generating 5271 * an interrupt while ticks control how long a BD can sit in the chain 5272 * before generating an interrupt. 5273 */ 5274 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP, 5275 (sc->bce_tx_quick_cons_trip_int << 16) | 5276 sc->bce_tx_quick_cons_trip); 5277 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP, 5278 (sc->bce_rx_quick_cons_trip_int << 16) | 5279 sc->bce_rx_quick_cons_trip); 5280 REG_WR(sc, BCE_HC_TX_TICKS, 5281 (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks); 5282 REG_WR(sc, BCE_HC_RX_TICKS, 5283 (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks); 5284 REG_WR(sc, BCE_HC_STATS_TICKS, sc->bce_stats_ticks & 0xffff00); 5285 REG_WR(sc, BCE_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */ 5286 /* Not used for L2. */ 5287 REG_WR(sc, BCE_HC_COMP_PROD_TRIP, 0); 5288 REG_WR(sc, BCE_HC_COM_TICKS, 0); 5289 REG_WR(sc, BCE_HC_CMD_TICKS, 0); 5290 5291 /* Configure the Host Coalescing block. */ 5292 val = BCE_HC_CONFIG_RX_TMR_MODE | BCE_HC_CONFIG_TX_TMR_MODE | 5293 BCE_HC_CONFIG_COLLECT_STATS; 5294 5295#if 0 5296 /* ToDo: Add MSI-X support. */ 5297 if (sc->bce_flags & BCE_USING_MSIX_FLAG) { 5298 u32 base = ((BCE_TX_VEC - 1) * BCE_HC_SB_CONFIG_SIZE) + 5299 BCE_HC_SB_CONFIG_1; 5300 5301 REG_WR(sc, BCE_HC_MSIX_BIT_VECTOR, BCE_HC_MSIX_BIT_VECTOR_VAL); 5302 5303 REG_WR(sc, base, BCE_HC_SB_CONFIG_1_TX_TMR_MODE | 5304 BCE_HC_SB_CONFIG_1_ONE_SHOT); 5305 5306 REG_WR(sc, base + BCE_HC_TX_QUICK_CONS_TRIP_OFF, 5307 (sc->tx_quick_cons_trip_int << 16) | 5308 sc->tx_quick_cons_trip); 5309 5310 REG_WR(sc, base + BCE_HC_TX_TICKS_OFF, 5311 (sc->tx_ticks_int << 16) | sc->tx_ticks); 5312 5313 val |= BCE_HC_CONFIG_SB_ADDR_INC_128B; 5314 } 5315 5316 /* 5317 * Tell the HC block to automatically set the 5318 * INT_MASK bit after an MSI/MSI-X interrupt 5319 * is generated so the driver doesn't have to. 5320 */ 5321 if (sc->bce_flags & BCE_ONE_SHOT_MSI_FLAG) 5322 val |= BCE_HC_CONFIG_ONE_SHOT; 5323 5324 /* Set the MSI-X status blocks to 128 byte boundaries. */ 5325 if (sc->bce_flags & BCE_USING_MSIX_FLAG) 5326 val |= BCE_HC_CONFIG_SB_ADDR_INC_128B; 5327#endif 5328 5329 REG_WR(sc, BCE_HC_CONFIG, val); 5330 5331 /* Clear the internal statistics counters. */ 5332 REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW); 5333 5334 /* Verify that bootcode is running. */ 5335 reg = bce_shmem_rd(sc, BCE_DEV_INFO_SIGNATURE); 5336 5337 DBRUNIF(DB_RANDOMTRUE(bootcode_running_failure_sim_control), 5338 BCE_PRINTF("%s(%d): Simulating bootcode failure.\n", 5339 __FILE__, __LINE__); 5340 reg = 0); 5341 5342 if ((reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK) != 5343 BCE_DEV_INFO_SIGNATURE_MAGIC) { 5344 BCE_PRINTF("%s(%d): Bootcode not running! Found: 0x%08X, " 5345 "Expected: 08%08X\n", __FILE__, __LINE__, 5346 (reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK), 5347 BCE_DEV_INFO_SIGNATURE_MAGIC); 5348 rc = ENODEV; 5349 goto bce_blockinit_exit; 5350 } 5351 5352 /* Enable DMA */ 5353 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5354 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL); 5355 val |= BCE_MISC_NEW_CORE_CTL_DMA_ENABLE; 5356 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val); 5357 } 5358 5359 /* Allow bootcode to apply additional fixes before enabling MAC. */ 5360 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT2 | 5361 BCE_DRV_MSG_CODE_RESET); 5362 5363 /* Enable link state change interrupt generation. */ 5364 REG_WR(sc, BCE_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE); 5365 5366 /* Enable the RXP. */ 5367 bce_start_rxp_cpu(sc); 5368 5369 /* Disable management frames (NC-SI) from flowing to the MCP. */ 5370 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 5371 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) & 5372 ~BCE_RPM_MGMT_PKT_CTRL_MGMT_EN; 5373 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val); 5374 } 5375 5376 /* Enable all remaining blocks in the MAC. */ 5377 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) 5378 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 5379 BCE_MISC_ENABLE_DEFAULT_XI); 5380 else 5381 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 5382 BCE_MISC_ENABLE_DEFAULT); 5383 5384 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS); 5385 DELAY(20); 5386 5387 /* Save the current host coalescing block settings. */ 5388 sc->hc_command = REG_RD(sc, BCE_HC_COMMAND); 5389 5390bce_blockinit_exit: 5391 DBEXIT(BCE_VERBOSE_RESET); 5392 5393 return (rc); 5394} 5395 5396 5397/****************************************************************************/ 5398/* Encapsulate an mbuf into the rx_bd chain. */ 5399/* */ 5400/* Returns: */ 5401/* 0 for success, positive value for failure. */ 5402/****************************************************************************/ 5403static int 5404bce_get_rx_buf(struct bce_softc *sc, u16 prod, u16 chain_prod, u32 *prod_bseq) 5405{ 5406 bus_dma_segment_t segs[1]; 5407 struct mbuf *m_new = NULL; 5408 struct rx_bd *rxbd; 5409 int nsegs, error, rc = 0; 5410#ifdef BCE_DEBUG 5411 u16 debug_chain_prod = chain_prod; 5412#endif 5413 5414 DBENTER(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5415 5416 /* Make sure the inputs are valid. */ 5417 DBRUNIF((chain_prod > MAX_RX_BD_ALLOC), 5418 BCE_PRINTF("%s(%d): RX producer out of range: " 5419 "0x%04X > 0x%04X\n", __FILE__, __LINE__, 5420 chain_prod, (u16)MAX_RX_BD_ALLOC)); 5421 5422 DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): prod = 0x%04X, " 5423 "chain_prod = 0x%04X, prod_bseq = 0x%08X\n", __FUNCTION__, 5424 prod, chain_prod, *prod_bseq); 5425 5426 /* Update some debug statistic counters */ 5427 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 5428 sc->rx_low_watermark = sc->free_rx_bd); 5429 DBRUNIF((sc->free_rx_bd == sc->max_rx_bd), 5430 sc->rx_empty_count++); 5431 5432 /* Simulate an mbuf allocation failure. */ 5433 DBRUNIF(DB_RANDOMTRUE(mbuf_alloc_failed_sim_control), 5434 sc->mbuf_alloc_failed_count++; 5435 sc->mbuf_alloc_failed_sim_count++; 5436 rc = ENOBUFS; 5437 goto bce_get_rx_buf_exit); 5438 5439 /* This is a new mbuf allocation. */ 5440 if (bce_hdr_split == TRUE) 5441 MGETHDR(m_new, M_NOWAIT, MT_DATA); 5442 else 5443 m_new = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, 5444 sc->rx_bd_mbuf_alloc_size); 5445 5446 if (m_new == NULL) { 5447 sc->mbuf_alloc_failed_count++; 5448 rc = ENOBUFS; 5449 goto bce_get_rx_buf_exit; 5450 } 5451 5452 DBRUN(sc->debug_rx_mbuf_alloc++); 5453 5454 /* Make sure we have a valid packet header. */ 5455 M_ASSERTPKTHDR(m_new); 5456 5457 /* Initialize the mbuf size and pad if necessary for alignment. */ 5458 m_new->m_pkthdr.len = m_new->m_len = sc->rx_bd_mbuf_alloc_size; 5459 m_adj(m_new, sc->rx_bd_mbuf_align_pad); 5460 5461 /* ToDo: Consider calling m_fragment() to test error handling. */ 5462 5463 /* Map the mbuf cluster into device memory. */ 5464 error = bus_dmamap_load_mbuf_sg(sc->rx_mbuf_tag, 5465 sc->rx_mbuf_map[chain_prod], m_new, segs, &nsegs, BUS_DMA_NOWAIT); 5466 5467 /* Handle any mapping errors. */ 5468 if (error) { 5469 BCE_PRINTF("%s(%d): Error mapping mbuf into RX " 5470 "chain (%d)!\n", __FILE__, __LINE__, error); 5471 5472 sc->dma_map_addr_rx_failed_count++; 5473 m_freem(m_new); 5474 5475 DBRUN(sc->debug_rx_mbuf_alloc--); 5476 5477 rc = ENOBUFS; 5478 goto bce_get_rx_buf_exit; 5479 } 5480 5481 /* All mbufs must map to a single segment. */ 5482 KASSERT(nsegs == 1, ("%s(): Too many segments returned (%d)!", 5483 __FUNCTION__, nsegs)); 5484 5485 /* Setup the rx_bd for the segment. */ 5486 rxbd = &sc->rx_bd_chain[RX_PAGE(chain_prod)][RX_IDX(chain_prod)]; 5487 5488 rxbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[0].ds_addr)); 5489 rxbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[0].ds_addr)); 5490 rxbd->rx_bd_len = htole32(segs[0].ds_len); 5491 rxbd->rx_bd_flags = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END); 5492 *prod_bseq += segs[0].ds_len; 5493 5494 /* Save the mbuf and update our counter. */ 5495 sc->rx_mbuf_ptr[chain_prod] = m_new; 5496 sc->free_rx_bd -= nsegs; 5497 5498 DBRUNMSG(BCE_INSANE_RECV, 5499 bce_dump_rx_mbuf_chain(sc, debug_chain_prod, nsegs)); 5500 5501 DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): prod = 0x%04X, " 5502 "chain_prod = 0x%04X, prod_bseq = 0x%08X\n", __FUNCTION__, prod, 5503 chain_prod, *prod_bseq); 5504 5505bce_get_rx_buf_exit: 5506 DBEXIT(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5507 5508 return(rc); 5509} 5510 5511 5512/****************************************************************************/ 5513/* Encapsulate an mbuf cluster into the page chain. */ 5514/* */ 5515/* Returns: */ 5516/* 0 for success, positive value for failure. */ 5517/****************************************************************************/ 5518static int 5519bce_get_pg_buf(struct bce_softc *sc, u16 prod, u16 prod_idx) 5520{ 5521 bus_dma_segment_t segs[1]; 5522 struct mbuf *m_new = NULL; 5523 struct rx_bd *pgbd; 5524 int error, nsegs, rc = 0; 5525#ifdef BCE_DEBUG 5526 u16 debug_prod_idx = prod_idx; 5527#endif 5528 5529 DBENTER(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5530 5531 /* Make sure the inputs are valid. */ 5532 DBRUNIF((prod_idx > MAX_PG_BD_ALLOC), 5533 BCE_PRINTF("%s(%d): page producer out of range: " 5534 "0x%04X > 0x%04X\n", __FILE__, __LINE__, 5535 prod_idx, (u16)MAX_PG_BD_ALLOC)); 5536 5537 DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): prod = 0x%04X, " 5538 "chain_prod = 0x%04X\n", __FUNCTION__, prod, prod_idx); 5539 5540 /* Update counters if we've hit a new low or run out of pages. */ 5541 DBRUNIF((sc->free_pg_bd < sc->pg_low_watermark), 5542 sc->pg_low_watermark = sc->free_pg_bd); 5543 DBRUNIF((sc->free_pg_bd == sc->max_pg_bd), sc->pg_empty_count++); 5544 5545 /* Simulate an mbuf allocation failure. */ 5546 DBRUNIF(DB_RANDOMTRUE(mbuf_alloc_failed_sim_control), 5547 sc->mbuf_alloc_failed_count++; 5548 sc->mbuf_alloc_failed_sim_count++; 5549 rc = ENOBUFS; 5550 goto bce_get_pg_buf_exit); 5551 5552 /* This is a new mbuf allocation. */ 5553 m_new = m_getcl(M_NOWAIT, MT_DATA, 0); 5554 if (m_new == NULL) { 5555 sc->mbuf_alloc_failed_count++; 5556 rc = ENOBUFS; 5557 goto bce_get_pg_buf_exit; 5558 } 5559 5560 DBRUN(sc->debug_pg_mbuf_alloc++); 5561 5562 m_new->m_len = MCLBYTES; 5563 5564 /* ToDo: Consider calling m_fragment() to test error handling. */ 5565 5566 /* Map the mbuf cluster into device memory. */ 5567 error = bus_dmamap_load_mbuf_sg(sc->pg_mbuf_tag, 5568 sc->pg_mbuf_map[prod_idx], m_new, segs, &nsegs, BUS_DMA_NOWAIT); 5569 5570 /* Handle any mapping errors. */ 5571 if (error) { 5572 BCE_PRINTF("%s(%d): Error mapping mbuf into page chain!\n", 5573 __FILE__, __LINE__); 5574 5575 m_freem(m_new); 5576 DBRUN(sc->debug_pg_mbuf_alloc--); 5577 5578 rc = ENOBUFS; 5579 goto bce_get_pg_buf_exit; 5580 } 5581 5582 /* All mbufs must map to a single segment. */ 5583 KASSERT(nsegs == 1, ("%s(): Too many segments returned (%d)!", 5584 __FUNCTION__, nsegs)); 5585 5586 /* ToDo: Do we need bus_dmamap_sync(,,BUS_DMASYNC_PREREAD) here? */ 5587 5588 /* 5589 * The page chain uses the same rx_bd data structure 5590 * as the receive chain but doesn't require a byte sequence (bseq). 5591 */ 5592 pgbd = &sc->pg_bd_chain[PG_PAGE(prod_idx)][PG_IDX(prod_idx)]; 5593 5594 pgbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[0].ds_addr)); 5595 pgbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[0].ds_addr)); 5596 pgbd->rx_bd_len = htole32(MCLBYTES); 5597 pgbd->rx_bd_flags = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END); 5598 5599 /* Save the mbuf and update our counter. */ 5600 sc->pg_mbuf_ptr[prod_idx] = m_new; 5601 sc->free_pg_bd--; 5602 5603 DBRUNMSG(BCE_INSANE_RECV, 5604 bce_dump_pg_mbuf_chain(sc, debug_prod_idx, 1)); 5605 5606 DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): prod = 0x%04X, " 5607 "prod_idx = 0x%04X\n", __FUNCTION__, prod, prod_idx); 5608 5609bce_get_pg_buf_exit: 5610 DBEXIT(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5611 5612 return(rc); 5613} 5614 5615 5616/****************************************************************************/ 5617/* Initialize the TX context memory. */ 5618/* */ 5619/* Returns: */ 5620/* Nothing */ 5621/****************************************************************************/ 5622static void 5623bce_init_tx_context(struct bce_softc *sc) 5624{ 5625 u32 val; 5626 5627 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 5628 5629 /* Initialize the context ID for an L2 TX chain. */ 5630 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5631 /* Set the CID type to support an L2 connection. */ 5632 val = BCE_L2CTX_TX_TYPE_TYPE_L2_XI | 5633 BCE_L2CTX_TX_TYPE_SIZE_L2_XI; 5634 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE_XI, val); 5635 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2_XI | (8 << 16); 5636 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5637 BCE_L2CTX_TX_CMD_TYPE_XI, val); 5638 5639 /* Point the hardware to the first page in the chain. */ 5640 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]); 5641 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5642 BCE_L2CTX_TX_TBDR_BHADDR_HI_XI, val); 5643 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]); 5644 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5645 BCE_L2CTX_TX_TBDR_BHADDR_LO_XI, val); 5646 } else { 5647 /* Set the CID type to support an L2 connection. */ 5648 val = BCE_L2CTX_TX_TYPE_TYPE_L2 | BCE_L2CTX_TX_TYPE_SIZE_L2; 5649 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE, val); 5650 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2 | (8 << 16); 5651 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_CMD_TYPE, val); 5652 5653 /* Point the hardware to the first page in the chain. */ 5654 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]); 5655 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5656 BCE_L2CTX_TX_TBDR_BHADDR_HI, val); 5657 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]); 5658 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5659 BCE_L2CTX_TX_TBDR_BHADDR_LO, val); 5660 } 5661 5662 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 5663} 5664 5665 5666/****************************************************************************/ 5667/* Allocate memory and initialize the TX data structures. */ 5668/* */ 5669/* Returns: */ 5670/* 0 for success, positive value for failure. */ 5671/****************************************************************************/ 5672static int 5673bce_init_tx_chain(struct bce_softc *sc) 5674{ 5675 struct tx_bd *txbd; 5676 int i, rc = 0; 5677 5678 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_LOAD); 5679 5680 /* Set the initial TX producer/consumer indices. */ 5681 sc->tx_prod = 0; 5682 sc->tx_cons = 0; 5683 sc->tx_prod_bseq = 0; 5684 sc->used_tx_bd = 0; 5685 sc->max_tx_bd = USABLE_TX_BD_ALLOC; 5686 DBRUN(sc->tx_hi_watermark = 0); 5687 DBRUN(sc->tx_full_count = 0); 5688 5689 /* 5690 * The NetXtreme II supports a linked-list structre called 5691 * a Buffer Descriptor Chain (or BD chain). A BD chain 5692 * consists of a series of 1 or more chain pages, each of which 5693 * consists of a fixed number of BD entries. 5694 * The last BD entry on each page is a pointer to the next page 5695 * in the chain, and the last pointer in the BD chain 5696 * points back to the beginning of the chain. 5697 */ 5698 5699 /* Set the TX next pointer chain entries. */ 5700 for (i = 0; i < sc->tx_pages; i++) { 5701 int j; 5702 5703 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE]; 5704 5705 /* Check if we've reached the last page. */ 5706 if (i == (sc->tx_pages - 1)) 5707 j = 0; 5708 else 5709 j = i + 1; 5710 5711 txbd->tx_bd_haddr_hi = 5712 htole32(BCE_ADDR_HI(sc->tx_bd_chain_paddr[j])); 5713 txbd->tx_bd_haddr_lo = 5714 htole32(BCE_ADDR_LO(sc->tx_bd_chain_paddr[j])); 5715 } 5716 5717 bce_init_tx_context(sc); 5718 5719 DBRUNMSG(BCE_INSANE_SEND, bce_dump_tx_chain(sc, 0, TOTAL_TX_BD_ALLOC)); 5720 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_LOAD); 5721 5722 return(rc); 5723} 5724 5725 5726/****************************************************************************/ 5727/* Free memory and clear the TX data structures. */ 5728/* */ 5729/* Returns: */ 5730/* Nothing. */ 5731/****************************************************************************/ 5732static void 5733bce_free_tx_chain(struct bce_softc *sc) 5734{ 5735 int i; 5736 5737 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_UNLOAD); 5738 5739 /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */ 5740 for (i = 0; i < MAX_TX_BD_AVAIL; i++) { 5741 if (sc->tx_mbuf_ptr[i] != NULL) { 5742 if (sc->tx_mbuf_map[i] != NULL) 5743 bus_dmamap_sync(sc->tx_mbuf_tag, 5744 sc->tx_mbuf_map[i], 5745 BUS_DMASYNC_POSTWRITE); 5746 m_freem(sc->tx_mbuf_ptr[i]); 5747 sc->tx_mbuf_ptr[i] = NULL; 5748 DBRUN(sc->debug_tx_mbuf_alloc--); 5749 } 5750 } 5751 5752 /* Clear each TX chain page. */ 5753 for (i = 0; i < sc->tx_pages; i++) 5754 bzero((char *)sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ); 5755 5756 sc->used_tx_bd = 0; 5757 5758 /* Check if we lost any mbufs in the process. */ 5759 DBRUNIF((sc->debug_tx_mbuf_alloc), 5760 BCE_PRINTF("%s(%d): Memory leak! Lost %d mbufs " 5761 "from tx chain!\n", __FILE__, __LINE__, 5762 sc->debug_tx_mbuf_alloc)); 5763 5764 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_UNLOAD); 5765} 5766 5767 5768/****************************************************************************/ 5769/* Initialize the RX context memory. */ 5770/* */ 5771/* Returns: */ 5772/* Nothing */ 5773/****************************************************************************/ 5774static void 5775bce_init_rx_context(struct bce_softc *sc) 5776{ 5777 u32 val; 5778 5779 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_CTX); 5780 5781 /* Init the type, size, and BD cache levels for the RX context. */ 5782 val = BCE_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE | 5783 BCE_L2CTX_RX_CTX_TYPE_SIZE_L2 | 5784 (0x02 << BCE_L2CTX_RX_BD_PRE_READ_SHIFT); 5785 5786 /* 5787 * Set the level for generating pause frames 5788 * when the number of available rx_bd's gets 5789 * too low (the low watermark) and the level 5790 * when pause frames can be stopped (the high 5791 * watermark). 5792 */ 5793 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5794 u32 lo_water, hi_water; 5795 5796 if (sc->bce_flags & BCE_USING_TX_FLOW_CONTROL) { 5797 lo_water = BCE_L2CTX_RX_LO_WATER_MARK_DEFAULT; 5798 } else { 5799 lo_water = 0; 5800 } 5801 5802 if (lo_water >= USABLE_RX_BD_ALLOC) { 5803 lo_water = 0; 5804 } 5805 5806 hi_water = USABLE_RX_BD_ALLOC / 4; 5807 5808 if (hi_water <= lo_water) { 5809 lo_water = 0; 5810 } 5811 5812 lo_water /= BCE_L2CTX_RX_LO_WATER_MARK_SCALE; 5813 hi_water /= BCE_L2CTX_RX_HI_WATER_MARK_SCALE; 5814 5815 if (hi_water > 0xf) 5816 hi_water = 0xf; 5817 else if (hi_water == 0) 5818 lo_water = 0; 5819 5820 val |= (lo_water << BCE_L2CTX_RX_LO_WATER_MARK_SHIFT) | 5821 (hi_water << BCE_L2CTX_RX_HI_WATER_MARK_SHIFT); 5822 } 5823 5824 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_CTX_TYPE, val); 5825 5826 /* Setup the MQ BIN mapping for l2_ctx_host_bseq. */ 5827 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5828 val = REG_RD(sc, BCE_MQ_MAP_L2_5); 5829 REG_WR(sc, BCE_MQ_MAP_L2_5, val | BCE_MQ_MAP_L2_5_ARM); 5830 } 5831 5832 /* Point the hardware to the first page in the chain. */ 5833 val = BCE_ADDR_HI(sc->rx_bd_chain_paddr[0]); 5834 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_HI, val); 5835 val = BCE_ADDR_LO(sc->rx_bd_chain_paddr[0]); 5836 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_LO, val); 5837 5838 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_CTX); 5839} 5840 5841 5842/****************************************************************************/ 5843/* Allocate memory and initialize the RX data structures. */ 5844/* */ 5845/* Returns: */ 5846/* 0 for success, positive value for failure. */ 5847/****************************************************************************/ 5848static int 5849bce_init_rx_chain(struct bce_softc *sc) 5850{ 5851 struct rx_bd *rxbd; 5852 int i, rc = 0; 5853 5854 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 5855 BCE_VERBOSE_CTX); 5856 5857 /* Initialize the RX producer and consumer indices. */ 5858 sc->rx_prod = 0; 5859 sc->rx_cons = 0; 5860 sc->rx_prod_bseq = 0; 5861 sc->free_rx_bd = USABLE_RX_BD_ALLOC; 5862 sc->max_rx_bd = USABLE_RX_BD_ALLOC; 5863 5864 /* Initialize the RX next pointer chain entries. */ 5865 for (i = 0; i < sc->rx_pages; i++) { 5866 int j; 5867 5868 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE]; 5869 5870 /* Check if we've reached the last page. */ 5871 if (i == (sc->rx_pages - 1)) 5872 j = 0; 5873 else 5874 j = i + 1; 5875 5876 /* Setup the chain page pointers. */ 5877 rxbd->rx_bd_haddr_hi = 5878 htole32(BCE_ADDR_HI(sc->rx_bd_chain_paddr[j])); 5879 rxbd->rx_bd_haddr_lo = 5880 htole32(BCE_ADDR_LO(sc->rx_bd_chain_paddr[j])); 5881 } 5882 5883 /* Fill up the RX chain. */ 5884 bce_fill_rx_chain(sc); 5885 5886 DBRUN(sc->rx_low_watermark = USABLE_RX_BD_ALLOC); 5887 DBRUN(sc->rx_empty_count = 0); 5888 for (i = 0; i < sc->rx_pages; i++) { 5889 bus_dmamap_sync(sc->rx_bd_chain_tag, sc->rx_bd_chain_map[i], 5890 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 5891 } 5892 5893 bce_init_rx_context(sc); 5894 5895 DBRUNMSG(BCE_EXTREME_RECV, 5896 bce_dump_rx_bd_chain(sc, 0, TOTAL_RX_BD_ALLOC)); 5897 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 5898 BCE_VERBOSE_CTX); 5899 5900 /* ToDo: Are there possible failure modes here? */ 5901 5902 return(rc); 5903} 5904 5905 5906/****************************************************************************/ 5907/* Add mbufs to the RX chain until its full or an mbuf allocation error */ 5908/* occurs. */ 5909/* */ 5910/* Returns: */ 5911/* Nothing */ 5912/****************************************************************************/ 5913static void 5914bce_fill_rx_chain(struct bce_softc *sc) 5915{ 5916 u16 prod, prod_idx; 5917 u32 prod_bseq; 5918 5919 DBENTER(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 5920 BCE_VERBOSE_CTX); 5921 5922 /* Get the RX chain producer indices. */ 5923 prod = sc->rx_prod; 5924 prod_bseq = sc->rx_prod_bseq; 5925 5926 /* Keep filling the RX chain until it's full. */ 5927 while (sc->free_rx_bd > 0) { 5928 prod_idx = RX_CHAIN_IDX(prod); 5929 if (bce_get_rx_buf(sc, prod, prod_idx, &prod_bseq)) { 5930 /* Bail out if we can't add an mbuf to the chain. */ 5931 break; 5932 } 5933 prod = NEXT_RX_BD(prod); 5934 } 5935 5936 /* Save the RX chain producer indices. */ 5937 sc->rx_prod = prod; 5938 sc->rx_prod_bseq = prod_bseq; 5939 5940 /* We should never end up pointing to a next page pointer. */ 5941 DBRUNIF(((prod & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE), 5942 BCE_PRINTF("%s(): Invalid rx_prod value: 0x%04X\n", 5943 __FUNCTION__, rx_prod)); 5944 5945 /* Write the mailbox and tell the chip about the waiting rx_bd's. */ 5946 REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BDIDX, prod); 5947 REG_WR(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BSEQ, prod_bseq); 5948 5949 DBEXIT(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 5950 BCE_VERBOSE_CTX); 5951} 5952 5953 5954/****************************************************************************/ 5955/* Free memory and clear the RX data structures. */ 5956/* */ 5957/* Returns: */ 5958/* Nothing. */ 5959/****************************************************************************/ 5960static void 5961bce_free_rx_chain(struct bce_softc *sc) 5962{ 5963 int i; 5964 5965 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 5966 5967 /* Free any mbufs still in the RX mbuf chain. */ 5968 for (i = 0; i < MAX_RX_BD_AVAIL; i++) { 5969 if (sc->rx_mbuf_ptr[i] != NULL) { 5970 if (sc->rx_mbuf_map[i] != NULL) 5971 bus_dmamap_sync(sc->rx_mbuf_tag, 5972 sc->rx_mbuf_map[i], 5973 BUS_DMASYNC_POSTREAD); 5974 m_freem(sc->rx_mbuf_ptr[i]); 5975 sc->rx_mbuf_ptr[i] = NULL; 5976 DBRUN(sc->debug_rx_mbuf_alloc--); 5977 } 5978 } 5979 5980 /* Clear each RX chain page. */ 5981 for (i = 0; i < sc->rx_pages; i++) 5982 if (sc->rx_bd_chain[i] != NULL) 5983 bzero((char *)sc->rx_bd_chain[i], 5984 BCE_RX_CHAIN_PAGE_SZ); 5985 5986 sc->free_rx_bd = sc->max_rx_bd; 5987 5988 /* Check if we lost any mbufs in the process. */ 5989 DBRUNIF((sc->debug_rx_mbuf_alloc), 5990 BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from rx chain!\n", 5991 __FUNCTION__, sc->debug_rx_mbuf_alloc)); 5992 5993 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 5994} 5995 5996 5997/****************************************************************************/ 5998/* Allocate memory and initialize the page data structures. */ 5999/* Assumes that bce_init_rx_chain() has not already been called. */ 6000/* */ 6001/* Returns: */ 6002/* 0 for success, positive value for failure. */ 6003/****************************************************************************/ 6004static int 6005bce_init_pg_chain(struct bce_softc *sc) 6006{ 6007 struct rx_bd *pgbd; 6008 int i, rc = 0; 6009 u32 val; 6010 6011 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 6012 BCE_VERBOSE_CTX); 6013 6014 /* Initialize the page producer and consumer indices. */ 6015 sc->pg_prod = 0; 6016 sc->pg_cons = 0; 6017 sc->free_pg_bd = USABLE_PG_BD_ALLOC; 6018 sc->max_pg_bd = USABLE_PG_BD_ALLOC; 6019 DBRUN(sc->pg_low_watermark = sc->max_pg_bd); 6020 DBRUN(sc->pg_empty_count = 0); 6021 6022 /* Initialize the page next pointer chain entries. */ 6023 for (i = 0; i < sc->pg_pages; i++) { 6024 int j; 6025 6026 pgbd = &sc->pg_bd_chain[i][USABLE_PG_BD_PER_PAGE]; 6027 6028 /* Check if we've reached the last page. */ 6029 if (i == (sc->pg_pages - 1)) 6030 j = 0; 6031 else 6032 j = i + 1; 6033 6034 /* Setup the chain page pointers. */ 6035 pgbd->rx_bd_haddr_hi = 6036 htole32(BCE_ADDR_HI(sc->pg_bd_chain_paddr[j])); 6037 pgbd->rx_bd_haddr_lo = 6038 htole32(BCE_ADDR_LO(sc->pg_bd_chain_paddr[j])); 6039 } 6040 6041 /* Setup the MQ BIN mapping for host_pg_bidx. */ 6042 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) 6043 REG_WR(sc, BCE_MQ_MAP_L2_3, BCE_MQ_MAP_L2_3_DEFAULT); 6044 6045 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_PG_BUF_SIZE, 0); 6046 6047 /* Configure the rx_bd and page chain mbuf cluster size. */ 6048 val = (sc->rx_bd_mbuf_data_len << 16) | MCLBYTES; 6049 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_PG_BUF_SIZE, val); 6050 6051 /* Configure the context reserved for jumbo support. */ 6052 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_RBDC_KEY, 6053 BCE_L2CTX_RX_RBDC_JUMBO_KEY); 6054 6055 /* Point the hardware to the first page in the page chain. */ 6056 val = BCE_ADDR_HI(sc->pg_bd_chain_paddr[0]); 6057 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_PG_BDHADDR_HI, val); 6058 val = BCE_ADDR_LO(sc->pg_bd_chain_paddr[0]); 6059 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_PG_BDHADDR_LO, val); 6060 6061 /* Fill up the page chain. */ 6062 bce_fill_pg_chain(sc); 6063 6064 for (i = 0; i < sc->pg_pages; i++) { 6065 bus_dmamap_sync(sc->pg_bd_chain_tag, sc->pg_bd_chain_map[i], 6066 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 6067 } 6068 6069 DBRUNMSG(BCE_EXTREME_RECV, 6070 bce_dump_pg_chain(sc, 0, TOTAL_PG_BD_ALLOC)); 6071 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 6072 BCE_VERBOSE_CTX); 6073 return(rc); 6074} 6075 6076 6077/****************************************************************************/ 6078/* Add mbufs to the page chain until its full or an mbuf allocation error */ 6079/* occurs. */ 6080/* */ 6081/* Returns: */ 6082/* Nothing */ 6083/****************************************************************************/ 6084static void 6085bce_fill_pg_chain(struct bce_softc *sc) 6086{ 6087 u16 prod, prod_idx; 6088 6089 DBENTER(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 6090 BCE_VERBOSE_CTX); 6091 6092 /* Get the page chain prodcuer index. */ 6093 prod = sc->pg_prod; 6094 6095 /* Keep filling the page chain until it's full. */ 6096 while (sc->free_pg_bd > 0) { 6097 prod_idx = PG_CHAIN_IDX(prod); 6098 if (bce_get_pg_buf(sc, prod, prod_idx)) { 6099 /* Bail out if we can't add an mbuf to the chain. */ 6100 break; 6101 } 6102 prod = NEXT_PG_BD(prod); 6103 } 6104 6105 /* Save the page chain producer index. */ 6106 sc->pg_prod = prod; 6107 6108 DBRUNIF(((prod & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE), 6109 BCE_PRINTF("%s(): Invalid pg_prod value: 0x%04X\n", 6110 __FUNCTION__, pg_prod)); 6111 6112 /* 6113 * Write the mailbox and tell the chip about 6114 * the new rx_bd's in the page chain. 6115 */ 6116 REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_PG_BDIDX, 6117 prod); 6118 6119 DBEXIT(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 6120 BCE_VERBOSE_CTX); 6121} 6122 6123 6124/****************************************************************************/ 6125/* Free memory and clear the RX data structures. */ 6126/* */ 6127/* Returns: */ 6128/* Nothing. */ 6129/****************************************************************************/ 6130static void 6131bce_free_pg_chain(struct bce_softc *sc) 6132{ 6133 int i; 6134 6135 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 6136 6137 /* Free any mbufs still in the mbuf page chain. */ 6138 for (i = 0; i < MAX_PG_BD_AVAIL; i++) { 6139 if (sc->pg_mbuf_ptr[i] != NULL) { 6140 if (sc->pg_mbuf_map[i] != NULL) 6141 bus_dmamap_sync(sc->pg_mbuf_tag, 6142 sc->pg_mbuf_map[i], 6143 BUS_DMASYNC_POSTREAD); 6144 m_freem(sc->pg_mbuf_ptr[i]); 6145 sc->pg_mbuf_ptr[i] = NULL; 6146 DBRUN(sc->debug_pg_mbuf_alloc--); 6147 } 6148 } 6149 6150 /* Clear each page chain pages. */ 6151 for (i = 0; i < sc->pg_pages; i++) 6152 bzero((char *)sc->pg_bd_chain[i], BCE_PG_CHAIN_PAGE_SZ); 6153 6154 sc->free_pg_bd = sc->max_pg_bd; 6155 6156 /* Check if we lost any mbufs in the process. */ 6157 DBRUNIF((sc->debug_pg_mbuf_alloc), 6158 BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from page chain!\n", 6159 __FUNCTION__, sc->debug_pg_mbuf_alloc)); 6160 6161 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 6162} 6163 6164 6165static u32 6166bce_get_rphy_link(struct bce_softc *sc) 6167{ 6168 u32 advertise, link; 6169 int fdpx; 6170 6171 advertise = 0; 6172 fdpx = 0; 6173 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) != 0) 6174 link = bce_shmem_rd(sc, BCE_RPHY_SERDES_LINK); 6175 else 6176 link = bce_shmem_rd(sc, BCE_RPHY_COPPER_LINK); 6177 if (link & BCE_NETLINK_ANEG_ENB) 6178 advertise |= BCE_NETLINK_ANEG_ENB; 6179 if (link & BCE_NETLINK_SPEED_10HALF) 6180 advertise |= BCE_NETLINK_SPEED_10HALF; 6181 if (link & BCE_NETLINK_SPEED_10FULL) { 6182 advertise |= BCE_NETLINK_SPEED_10FULL; 6183 fdpx++; 6184 } 6185 if (link & BCE_NETLINK_SPEED_100HALF) 6186 advertise |= BCE_NETLINK_SPEED_100HALF; 6187 if (link & BCE_NETLINK_SPEED_100FULL) { 6188 advertise |= BCE_NETLINK_SPEED_100FULL; 6189 fdpx++; 6190 } 6191 if (link & BCE_NETLINK_SPEED_1000HALF) 6192 advertise |= BCE_NETLINK_SPEED_1000HALF; 6193 if (link & BCE_NETLINK_SPEED_1000FULL) { 6194 advertise |= BCE_NETLINK_SPEED_1000FULL; 6195 fdpx++; 6196 } 6197 if (link & BCE_NETLINK_SPEED_2500HALF) 6198 advertise |= BCE_NETLINK_SPEED_2500HALF; 6199 if (link & BCE_NETLINK_SPEED_2500FULL) { 6200 advertise |= BCE_NETLINK_SPEED_2500FULL; 6201 fdpx++; 6202 } 6203 if (fdpx) 6204 advertise |= BCE_NETLINK_FC_PAUSE_SYM | 6205 BCE_NETLINK_FC_PAUSE_ASYM; 6206 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) 6207 advertise |= BCE_NETLINK_PHY_APP_REMOTE | 6208 BCE_NETLINK_ETH_AT_WIRESPEED; 6209 6210 return (advertise); 6211} 6212 6213 6214/****************************************************************************/ 6215/* Set media options. */ 6216/* */ 6217/* Returns: */ 6218/* 0 for success, positive value for failure. */ 6219/****************************************************************************/ 6220static int 6221bce_ifmedia_upd(struct ifnet *ifp) 6222{ 6223 struct bce_softc *sc = ifp->if_softc; 6224 int error; 6225 6226 DBENTER(BCE_VERBOSE); 6227 6228 BCE_LOCK(sc); 6229 error = bce_ifmedia_upd_locked(ifp); 6230 BCE_UNLOCK(sc); 6231 6232 DBEXIT(BCE_VERBOSE); 6233 return (error); 6234} 6235 6236 6237/****************************************************************************/ 6238/* Set media options. */ 6239/* */ 6240/* Returns: */ 6241/* Nothing. */ 6242/****************************************************************************/ 6243static int 6244bce_ifmedia_upd_locked(struct ifnet *ifp) 6245{ 6246 struct bce_softc *sc = ifp->if_softc; 6247 struct mii_data *mii; 6248 struct mii_softc *miisc; 6249 struct ifmedia *ifm; 6250 u32 link; 6251 int error, fdx; 6252 6253 DBENTER(BCE_VERBOSE_PHY); 6254 6255 error = 0; 6256 BCE_LOCK_ASSERT(sc); 6257 6258 sc->bce_link_up = FALSE; 6259 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) { 6260 ifm = &sc->bce_ifmedia; 6261 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 6262 return (EINVAL); 6263 link = 0; 6264 fdx = IFM_OPTIONS(ifm->ifm_media) & IFM_FDX; 6265 switch(IFM_SUBTYPE(ifm->ifm_media)) { 6266 case IFM_AUTO: 6267 /* 6268 * Check advertised link of remote PHY by reading 6269 * BCE_RPHY_SERDES_LINK or BCE_RPHY_COPPER_LINK. 6270 * Always use the same link type of remote PHY. 6271 */ 6272 link = bce_get_rphy_link(sc); 6273 break; 6274 case IFM_2500_SX: 6275 if ((sc->bce_phy_flags & 6276 (BCE_PHY_REMOTE_PORT_FIBER_FLAG | 6277 BCE_PHY_2_5G_CAPABLE_FLAG)) == 0) 6278 return (EINVAL); 6279 /* 6280 * XXX 6281 * Have to enable forced 2.5Gbps configuration. 6282 */ 6283 if (fdx != 0) 6284 link |= BCE_NETLINK_SPEED_2500FULL; 6285 else 6286 link |= BCE_NETLINK_SPEED_2500HALF; 6287 break; 6288 case IFM_1000_SX: 6289 if ((sc->bce_phy_flags & 6290 BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) 6291 return (EINVAL); 6292 /* 6293 * XXX 6294 * Have to disable 2.5Gbps configuration. 6295 */ 6296 if (fdx != 0) 6297 link = BCE_NETLINK_SPEED_1000FULL; 6298 else 6299 link = BCE_NETLINK_SPEED_1000HALF; 6300 break; 6301 case IFM_1000_T: 6302 if (sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) 6303 return (EINVAL); 6304 if (fdx != 0) 6305 link = BCE_NETLINK_SPEED_1000FULL; 6306 else 6307 link = BCE_NETLINK_SPEED_1000HALF; 6308 break; 6309 case IFM_100_TX: 6310 if (sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) 6311 return (EINVAL); 6312 if (fdx != 0) 6313 link = BCE_NETLINK_SPEED_100FULL; 6314 else 6315 link = BCE_NETLINK_SPEED_100HALF; 6316 break; 6317 case IFM_10_T: 6318 if (sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) 6319 return (EINVAL); 6320 if (fdx != 0) 6321 link = BCE_NETLINK_SPEED_10FULL; 6322 else 6323 link = BCE_NETLINK_SPEED_10HALF; 6324 break; 6325 default: 6326 return (EINVAL); 6327 } 6328 if (IFM_SUBTYPE(ifm->ifm_media) != IFM_AUTO) { 6329 /* 6330 * XXX 6331 * Advertise pause capability for full-duplex media. 6332 */ 6333 if (fdx != 0) 6334 link |= BCE_NETLINK_FC_PAUSE_SYM | 6335 BCE_NETLINK_FC_PAUSE_ASYM; 6336 if ((sc->bce_phy_flags & 6337 BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) 6338 link |= BCE_NETLINK_PHY_APP_REMOTE | 6339 BCE_NETLINK_ETH_AT_WIRESPEED; 6340 } 6341 6342 bce_shmem_wr(sc, BCE_MB_ARGS_0, link); 6343 error = bce_fw_sync(sc, BCE_DRV_MSG_CODE_CMD_SET_LINK); 6344 } else { 6345 mii = device_get_softc(sc->bce_miibus); 6346 6347 /* Make sure the MII bus has been enumerated. */ 6348 if (mii) { 6349 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 6350 PHY_RESET(miisc); 6351 error = mii_mediachg(mii); 6352 } 6353 } 6354 6355 DBEXIT(BCE_VERBOSE_PHY); 6356 return (error); 6357} 6358 6359 6360static void 6361bce_ifmedia_sts_rphy(struct bce_softc *sc, struct ifmediareq *ifmr) 6362{ 6363 struct ifnet *ifp; 6364 u32 link; 6365 6366 ifp = sc->bce_ifp; 6367 BCE_LOCK_ASSERT(sc); 6368 6369 ifmr->ifm_status = IFM_AVALID; 6370 ifmr->ifm_active = IFM_ETHER; 6371 link = bce_shmem_rd(sc, BCE_LINK_STATUS); 6372 /* XXX Handle heart beat status? */ 6373 if ((link & BCE_LINK_STATUS_LINK_UP) != 0) 6374 ifmr->ifm_status |= IFM_ACTIVE; 6375 else { 6376 ifmr->ifm_active |= IFM_NONE; 6377 ifp->if_baudrate = 0; 6378 return; 6379 } 6380 switch (link & BCE_LINK_STATUS_SPEED_MASK) { 6381 case BCE_LINK_STATUS_10HALF: 6382 ifmr->ifm_active |= IFM_10_T | IFM_HDX; 6383 ifp->if_baudrate = IF_Mbps(10UL); 6384 break; 6385 case BCE_LINK_STATUS_10FULL: 6386 ifmr->ifm_active |= IFM_10_T | IFM_FDX; 6387 ifp->if_baudrate = IF_Mbps(10UL); 6388 break; 6389 case BCE_LINK_STATUS_100HALF: 6390 ifmr->ifm_active |= IFM_100_TX | IFM_HDX; 6391 ifp->if_baudrate = IF_Mbps(100UL); 6392 break; 6393 case BCE_LINK_STATUS_100FULL: 6394 ifmr->ifm_active |= IFM_100_TX | IFM_FDX; 6395 ifp->if_baudrate = IF_Mbps(100UL); 6396 break; 6397 case BCE_LINK_STATUS_1000HALF: 6398 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) 6399 ifmr->ifm_active |= IFM_1000_T | IFM_HDX; 6400 else 6401 ifmr->ifm_active |= IFM_1000_SX | IFM_HDX; 6402 ifp->if_baudrate = IF_Mbps(1000UL); 6403 break; 6404 case BCE_LINK_STATUS_1000FULL: 6405 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) 6406 ifmr->ifm_active |= IFM_1000_T | IFM_FDX; 6407 else 6408 ifmr->ifm_active |= IFM_1000_SX | IFM_FDX; 6409 ifp->if_baudrate = IF_Mbps(1000UL); 6410 break; 6411 case BCE_LINK_STATUS_2500HALF: 6412 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) { 6413 ifmr->ifm_active |= IFM_NONE; 6414 return; 6415 } else 6416 ifmr->ifm_active |= IFM_2500_SX | IFM_HDX; 6417 ifp->if_baudrate = IF_Mbps(2500UL); 6418 break; 6419 case BCE_LINK_STATUS_2500FULL: 6420 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) { 6421 ifmr->ifm_active |= IFM_NONE; 6422 return; 6423 } else 6424 ifmr->ifm_active |= IFM_2500_SX | IFM_FDX; 6425 ifp->if_baudrate = IF_Mbps(2500UL); 6426 break; 6427 default: 6428 ifmr->ifm_active |= IFM_NONE; 6429 return; 6430 } 6431 6432 if ((link & BCE_LINK_STATUS_RX_FC_ENABLED) != 0) 6433 ifmr->ifm_active |= IFM_ETH_RXPAUSE; 6434 if ((link & BCE_LINK_STATUS_TX_FC_ENABLED) != 0) 6435 ifmr->ifm_active |= IFM_ETH_TXPAUSE; 6436} 6437 6438 6439/****************************************************************************/ 6440/* Reports current media status. */ 6441/* */ 6442/* Returns: */ 6443/* Nothing. */ 6444/****************************************************************************/ 6445static void 6446bce_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 6447{ 6448 struct bce_softc *sc = ifp->if_softc; 6449 struct mii_data *mii; 6450 6451 DBENTER(BCE_VERBOSE_PHY); 6452 6453 BCE_LOCK(sc); 6454 6455 if ((ifp->if_flags & IFF_UP) == 0) { 6456 BCE_UNLOCK(sc); 6457 return; 6458 } 6459 6460 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) 6461 bce_ifmedia_sts_rphy(sc, ifmr); 6462 else { 6463 mii = device_get_softc(sc->bce_miibus); 6464 mii_pollstat(mii); 6465 ifmr->ifm_active = mii->mii_media_active; 6466 ifmr->ifm_status = mii->mii_media_status; 6467 } 6468 6469 BCE_UNLOCK(sc); 6470 6471 DBEXIT(BCE_VERBOSE_PHY); 6472} 6473 6474 6475/****************************************************************************/ 6476/* Handles PHY generated interrupt events. */ 6477/* */ 6478/* Returns: */ 6479/* Nothing. */ 6480/****************************************************************************/ 6481static void 6482bce_phy_intr(struct bce_softc *sc) 6483{ 6484 u32 new_link_state, old_link_state; 6485 6486 DBENTER(BCE_VERBOSE_PHY | BCE_VERBOSE_INTR); 6487 6488 DBRUN(sc->phy_interrupts++); 6489 6490 new_link_state = sc->status_block->status_attn_bits & 6491 STATUS_ATTN_BITS_LINK_STATE; 6492 old_link_state = sc->status_block->status_attn_bits_ack & 6493 STATUS_ATTN_BITS_LINK_STATE; 6494 6495 /* Handle any changes if the link state has changed. */ 6496 if (new_link_state != old_link_state) { 6497 6498 /* Update the status_attn_bits_ack field. */ 6499 if (new_link_state) { 6500 REG_WR(sc, BCE_PCICFG_STATUS_BIT_SET_CMD, 6501 STATUS_ATTN_BITS_LINK_STATE); 6502 DBPRINT(sc, BCE_INFO_PHY, "%s(): Link is now UP.\n", 6503 __FUNCTION__); 6504 } else { 6505 REG_WR(sc, BCE_PCICFG_STATUS_BIT_CLEAR_CMD, 6506 STATUS_ATTN_BITS_LINK_STATE); 6507 DBPRINT(sc, BCE_INFO_PHY, "%s(): Link is now DOWN.\n", 6508 __FUNCTION__); 6509 } 6510 6511 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) { 6512 if (new_link_state) { 6513 if (bootverbose) 6514 if_printf(sc->bce_ifp, "link UP\n"); 6515 if_link_state_change(sc->bce_ifp, 6516 LINK_STATE_UP); 6517 } else { 6518 if (bootverbose) 6519 if_printf(sc->bce_ifp, "link DOWN\n"); 6520 if_link_state_change(sc->bce_ifp, 6521 LINK_STATE_DOWN); 6522 } 6523 } 6524 /* 6525 * Assume link is down and allow 6526 * tick routine to update the state 6527 * based on the actual media state. 6528 */ 6529 sc->bce_link_up = FALSE; 6530 callout_stop(&sc->bce_tick_callout); 6531 bce_tick(sc); 6532 } 6533 6534 /* Acknowledge the link change interrupt. */ 6535 REG_WR(sc, BCE_EMAC_STATUS, BCE_EMAC_STATUS_LINK_CHANGE); 6536 6537 DBEXIT(BCE_VERBOSE_PHY | BCE_VERBOSE_INTR); 6538} 6539 6540 6541/****************************************************************************/ 6542/* Reads the receive consumer value from the status block (skipping over */ 6543/* chain page pointer if necessary). */ 6544/* */ 6545/* Returns: */ 6546/* hw_cons */ 6547/****************************************************************************/ 6548static inline u16 6549bce_get_hw_rx_cons(struct bce_softc *sc) 6550{ 6551 u16 hw_cons; 6552 6553 rmb(); 6554 hw_cons = sc->status_block->status_rx_quick_consumer_index0; 6555 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 6556 hw_cons++; 6557 6558 return hw_cons; 6559} 6560 6561/****************************************************************************/ 6562/* Handles received frame interrupt events. */ 6563/* */ 6564/* Returns: */ 6565/* Nothing. */ 6566/****************************************************************************/ 6567static void 6568bce_rx_intr(struct bce_softc *sc) 6569{ 6570 struct ifnet *ifp = sc->bce_ifp; 6571 struct l2_fhdr *l2fhdr; 6572 struct ether_vlan_header *vh; 6573 unsigned int pkt_len; 6574 u16 sw_rx_cons, sw_rx_cons_idx, hw_rx_cons; 6575 u32 status; 6576 unsigned int rem_len; 6577 u16 sw_pg_cons, sw_pg_cons_idx; 6578 6579 DBENTER(BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 6580 DBRUN(sc->interrupts_rx++); 6581 DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): rx_prod = 0x%04X, " 6582 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n", 6583 __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq); 6584 6585 /* Prepare the RX chain pages to be accessed by the host CPU. */ 6586 for (int i = 0; i < sc->rx_pages; i++) 6587 bus_dmamap_sync(sc->rx_bd_chain_tag, 6588 sc->rx_bd_chain_map[i], BUS_DMASYNC_POSTREAD); 6589 6590 /* Prepare the page chain pages to be accessed by the host CPU. */ 6591 if (bce_hdr_split == TRUE) { 6592 for (int i = 0; i < sc->pg_pages; i++) 6593 bus_dmamap_sync(sc->pg_bd_chain_tag, 6594 sc->pg_bd_chain_map[i], BUS_DMASYNC_POSTREAD); 6595 } 6596 6597 /* Get the hardware's view of the RX consumer index. */ 6598 hw_rx_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc); 6599 6600 /* Get working copies of the driver's view of the consumer indices. */ 6601 sw_rx_cons = sc->rx_cons; 6602 sw_pg_cons = sc->pg_cons; 6603 6604 /* Update some debug statistics counters */ 6605 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 6606 sc->rx_low_watermark = sc->free_rx_bd); 6607 DBRUNIF((sc->free_rx_bd == sc->max_rx_bd), 6608 sc->rx_empty_count++); 6609 6610 /* Scan through the receive chain as long as there is work to do */ 6611 /* ToDo: Consider setting a limit on the number of packets processed. */ 6612 rmb(); 6613 while (sw_rx_cons != hw_rx_cons) { 6614 struct mbuf *m0; 6615 6616 /* Convert the producer/consumer indices to an actual rx_bd index. */ 6617 sw_rx_cons_idx = RX_CHAIN_IDX(sw_rx_cons); 6618 6619 /* Unmap the mbuf from DMA space. */ 6620 bus_dmamap_sync(sc->rx_mbuf_tag, 6621 sc->rx_mbuf_map[sw_rx_cons_idx], 6622 BUS_DMASYNC_POSTREAD); 6623 bus_dmamap_unload(sc->rx_mbuf_tag, 6624 sc->rx_mbuf_map[sw_rx_cons_idx]); 6625 6626 /* Remove the mbuf from the RX chain. */ 6627 m0 = sc->rx_mbuf_ptr[sw_rx_cons_idx]; 6628 sc->rx_mbuf_ptr[sw_rx_cons_idx] = NULL; 6629 DBRUN(sc->debug_rx_mbuf_alloc--); 6630 sc->free_rx_bd++; 6631 6632 /* 6633 * Frames received on the NetXteme II are prepended 6634 * with an l2_fhdr structure which provides status 6635 * information about the received frame (including 6636 * VLAN tags and checksum info). The frames are 6637 * also automatically adjusted to word align the IP 6638 * header (i.e. two null bytes are inserted before 6639 * the Ethernet header). As a result the data 6640 * DMA'd by the controller into the mbuf looks 6641 * like this: 6642 * 6643 * +---------+-----+---------------------+-----+ 6644 * | l2_fhdr | pad | packet data | FCS | 6645 * +---------+-----+---------------------+-----+ 6646 * 6647 * The l2_fhdr needs to be checked and skipped and 6648 * the FCS needs to be stripped before sending the 6649 * packet up the stack. 6650 */ 6651 l2fhdr = mtod(m0, struct l2_fhdr *); 6652 6653 /* Get the packet data + FCS length and the status. */ 6654 pkt_len = l2fhdr->l2_fhdr_pkt_len; 6655 status = l2fhdr->l2_fhdr_status; 6656 6657 /* 6658 * Skip over the l2_fhdr and pad, resulting in the 6659 * following data in the mbuf: 6660 * +---------------------+-----+ 6661 * | packet data | FCS | 6662 * +---------------------+-----+ 6663 */ 6664 m_adj(m0, sizeof(struct l2_fhdr) + ETHER_ALIGN); 6665 6666 /* 6667 * When split header mode is used, an ethernet frame 6668 * may be split across the receive chain and the 6669 * page chain. If that occurs an mbuf cluster must be 6670 * reassembled from the individual mbuf pieces. 6671 */ 6672 if (bce_hdr_split == TRUE) { 6673 /* 6674 * Check whether the received frame fits in a single 6675 * mbuf or not (i.e. packet data + FCS <= 6676 * sc->rx_bd_mbuf_data_len bytes). 6677 */ 6678 if (pkt_len > m0->m_len) { 6679 /* 6680 * The received frame is larger than a single mbuf. 6681 * If the frame was a TCP frame then only the TCP 6682 * header is placed in the mbuf, the remaining 6683 * payload (including FCS) is placed in the page 6684 * chain, the SPLIT flag is set, and the header 6685 * length is placed in the IP checksum field. 6686 * If the frame is not a TCP frame then the mbuf 6687 * is filled and the remaining bytes are placed 6688 * in the page chain. 6689 */ 6690 6691 DBPRINT(sc, BCE_INFO_RECV, "%s(): Found a large " 6692 "packet.\n", __FUNCTION__); 6693 DBRUN(sc->split_header_frames_rcvd++); 6694 6695 /* 6696 * When the page chain is enabled and the TCP 6697 * header has been split from the TCP payload, 6698 * the ip_xsum structure will reflect the length 6699 * of the TCP header, not the IP checksum. Set 6700 * the packet length of the mbuf accordingly. 6701 */ 6702 if (status & L2_FHDR_STATUS_SPLIT) { 6703 m0->m_len = l2fhdr->l2_fhdr_ip_xsum; 6704 DBRUN(sc->split_header_tcp_frames_rcvd++); 6705 } 6706 6707 rem_len = pkt_len - m0->m_len; 6708 6709 /* Pull mbufs off the page chain for any remaining data. */ 6710 while (rem_len > 0) { 6711 struct mbuf *m_pg; 6712 6713 sw_pg_cons_idx = PG_CHAIN_IDX(sw_pg_cons); 6714 6715 /* Remove the mbuf from the page chain. */ 6716 m_pg = sc->pg_mbuf_ptr[sw_pg_cons_idx]; 6717 sc->pg_mbuf_ptr[sw_pg_cons_idx] = NULL; 6718 DBRUN(sc->debug_pg_mbuf_alloc--); 6719 sc->free_pg_bd++; 6720 6721 /* Unmap the page chain mbuf from DMA space. */ 6722 bus_dmamap_sync(sc->pg_mbuf_tag, 6723 sc->pg_mbuf_map[sw_pg_cons_idx], 6724 BUS_DMASYNC_POSTREAD); 6725 bus_dmamap_unload(sc->pg_mbuf_tag, 6726 sc->pg_mbuf_map[sw_pg_cons_idx]); 6727 6728 /* Adjust the mbuf length. */ 6729 if (rem_len < m_pg->m_len) { 6730 /* The mbuf chain is complete. */ 6731 m_pg->m_len = rem_len; 6732 rem_len = 0; 6733 } else { 6734 /* More packet data is waiting. */ 6735 rem_len -= m_pg->m_len; 6736 } 6737 6738 /* Concatenate the mbuf cluster to the mbuf. */ 6739 m_cat(m0, m_pg); 6740 6741 sw_pg_cons = NEXT_PG_BD(sw_pg_cons); 6742 } 6743 6744 /* Set the total packet length. */ 6745 m0->m_pkthdr.len = pkt_len; 6746 6747 } else { 6748 /* 6749 * The received packet is small and fits in a 6750 * single mbuf (i.e. the l2_fhdr + pad + packet + 6751 * FCS <= MHLEN). In other words, the packet is 6752 * 154 bytes or less in size. 6753 */ 6754 6755 DBPRINT(sc, BCE_INFO_RECV, "%s(): Found a small " 6756 "packet.\n", __FUNCTION__); 6757 6758 /* Set the total packet length. */ 6759 m0->m_pkthdr.len = m0->m_len = pkt_len; 6760 } 6761 } else 6762 /* Set the total packet length. */ 6763 m0->m_pkthdr.len = m0->m_len = pkt_len; 6764 6765 /* Remove the trailing Ethernet FCS. */ 6766 m_adj(m0, -ETHER_CRC_LEN); 6767 6768 /* Check that the resulting mbuf chain is valid. */ 6769 DBRUN(m_sanity(m0, FALSE)); 6770 DBRUNIF(((m0->m_len < ETHER_HDR_LEN) | 6771 (m0->m_pkthdr.len > BCE_MAX_JUMBO_ETHER_MTU_VLAN)), 6772 BCE_PRINTF("Invalid Ethernet frame size!\n"); 6773 m_print(m0, 128)); 6774 6775 DBRUNIF(DB_RANDOMTRUE(l2fhdr_error_sim_control), 6776 sc->l2fhdr_error_sim_count++; 6777 status = status | L2_FHDR_ERRORS_PHY_DECODE); 6778 6779 /* Check the received frame for errors. */ 6780 if (status & (L2_FHDR_ERRORS_BAD_CRC | 6781 L2_FHDR_ERRORS_PHY_DECODE | L2_FHDR_ERRORS_ALIGNMENT | 6782 L2_FHDR_ERRORS_TOO_SHORT | L2_FHDR_ERRORS_GIANT_FRAME)) { 6783 6784 /* Log the error and release the mbuf. */ 6785 ifp->if_ierrors++; 6786 sc->l2fhdr_error_count++; 6787 6788 m_freem(m0); 6789 m0 = NULL; 6790 goto bce_rx_intr_next_rx; 6791 } 6792 6793 /* Send the packet to the appropriate interface. */ 6794 m0->m_pkthdr.rcvif = ifp; 6795 6796 /* Assume no hardware checksum. */ 6797 m0->m_pkthdr.csum_flags = 0; 6798 6799 /* Validate the checksum if offload enabled. */ 6800 if (ifp->if_capenable & IFCAP_RXCSUM) { 6801 /* Check for an IP datagram. */ 6802 if (!(status & L2_FHDR_STATUS_SPLIT) && 6803 (status & L2_FHDR_STATUS_IP_DATAGRAM)) { 6804 m0->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 6805 DBRUN(sc->csum_offload_ip++); 6806 /* Check if the IP checksum is valid. */ 6807 if ((l2fhdr->l2_fhdr_ip_xsum ^ 0xffff) == 0) 6808 m0->m_pkthdr.csum_flags |= 6809 CSUM_IP_VALID; 6810 } 6811 6812 /* Check for a valid TCP/UDP frame. */ 6813 if (status & (L2_FHDR_STATUS_TCP_SEGMENT | 6814 L2_FHDR_STATUS_UDP_DATAGRAM)) { 6815 6816 /* Check for a good TCP/UDP checksum. */ 6817 if ((status & (L2_FHDR_ERRORS_TCP_XSUM | 6818 L2_FHDR_ERRORS_UDP_XSUM)) == 0) { 6819 DBRUN(sc->csum_offload_tcp_udp++); 6820 m0->m_pkthdr.csum_data = 6821 l2fhdr->l2_fhdr_tcp_udp_xsum; 6822 m0->m_pkthdr.csum_flags |= 6823 (CSUM_DATA_VALID 6824 | CSUM_PSEUDO_HDR); 6825 } 6826 } 6827 } 6828 6829 /* Attach the VLAN tag. */ 6830 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && 6831 !(sc->rx_mode & BCE_EMAC_RX_MODE_KEEP_VLAN_TAG)) { 6832 DBRUN(sc->vlan_tagged_frames_rcvd++); 6833 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) { 6834 DBRUN(sc->vlan_tagged_frames_stripped++); 6835#if __FreeBSD_version < 700000 6836 VLAN_INPUT_TAG(ifp, m0, 6837 l2fhdr->l2_fhdr_vlan_tag, continue); 6838#else 6839 m0->m_pkthdr.ether_vtag = 6840 l2fhdr->l2_fhdr_vlan_tag; 6841 m0->m_flags |= M_VLANTAG; 6842#endif 6843 } else { 6844 /* 6845 * bce(4) controllers can't disable VLAN 6846 * tag stripping if management firmware 6847 * (ASF/IPMI/UMP) is running. So we always 6848 * strip VLAN tag and manually reconstruct 6849 * the VLAN frame by appending stripped 6850 * VLAN tag in driver if VLAN tag stripping 6851 * was disabled. 6852 * 6853 * TODO: LLC SNAP handling. 6854 */ 6855 bcopy(mtod(m0, uint8_t *), 6856 mtod(m0, uint8_t *) - ETHER_VLAN_ENCAP_LEN, 6857 ETHER_ADDR_LEN * 2); 6858 m0->m_data -= ETHER_VLAN_ENCAP_LEN; 6859 vh = mtod(m0, struct ether_vlan_header *); 6860 vh->evl_encap_proto = htons(ETHERTYPE_VLAN); 6861 vh->evl_tag = htons(l2fhdr->l2_fhdr_vlan_tag); 6862 m0->m_pkthdr.len += ETHER_VLAN_ENCAP_LEN; 6863 m0->m_len += ETHER_VLAN_ENCAP_LEN; 6864 } 6865 } 6866 6867 /* Increment received packet statistics. */ 6868 ifp->if_ipackets++; 6869 6870bce_rx_intr_next_rx: 6871 sw_rx_cons = NEXT_RX_BD(sw_rx_cons); 6872 6873 /* If we have a packet, pass it up the stack */ 6874 if (m0) { 6875 /* Make sure we don't lose our place when we release the lock. */ 6876 sc->rx_cons = sw_rx_cons; 6877 sc->pg_cons = sw_pg_cons; 6878 6879 BCE_UNLOCK(sc); 6880 (*ifp->if_input)(ifp, m0); 6881 BCE_LOCK(sc); 6882 6883 /* Recover our place. */ 6884 sw_rx_cons = sc->rx_cons; 6885 sw_pg_cons = sc->pg_cons; 6886 } 6887 6888 /* Refresh hw_cons to see if there's new work */ 6889 if (sw_rx_cons == hw_rx_cons) 6890 hw_rx_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc); 6891 } 6892 6893 /* No new packets. Refill the page chain. */ 6894 if (bce_hdr_split == TRUE) { 6895 sc->pg_cons = sw_pg_cons; 6896 bce_fill_pg_chain(sc); 6897 } 6898 6899 /* No new packets. Refill the RX chain. */ 6900 sc->rx_cons = sw_rx_cons; 6901 bce_fill_rx_chain(sc); 6902 6903 /* Prepare the page chain pages to be accessed by the NIC. */ 6904 for (int i = 0; i < sc->rx_pages; i++) 6905 bus_dmamap_sync(sc->rx_bd_chain_tag, 6906 sc->rx_bd_chain_map[i], BUS_DMASYNC_PREWRITE); 6907 6908 if (bce_hdr_split == TRUE) { 6909 for (int i = 0; i < sc->pg_pages; i++) 6910 bus_dmamap_sync(sc->pg_bd_chain_tag, 6911 sc->pg_bd_chain_map[i], BUS_DMASYNC_PREWRITE); 6912 } 6913 6914 DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): rx_prod = 0x%04X, " 6915 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n", 6916 __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq); 6917 DBEXIT(BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 6918} 6919 6920 6921/****************************************************************************/ 6922/* Reads the transmit consumer value from the status block (skipping over */ 6923/* chain page pointer if necessary). */ 6924/* */ 6925/* Returns: */ 6926/* hw_cons */ 6927/****************************************************************************/ 6928static inline u16 6929bce_get_hw_tx_cons(struct bce_softc *sc) 6930{ 6931 u16 hw_cons; 6932 6933 mb(); 6934 hw_cons = sc->status_block->status_tx_quick_consumer_index0; 6935 if ((hw_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 6936 hw_cons++; 6937 6938 return hw_cons; 6939} 6940 6941 6942/****************************************************************************/ 6943/* Handles transmit completion interrupt events. */ 6944/* */ 6945/* Returns: */ 6946/* Nothing. */ 6947/****************************************************************************/ 6948static void 6949bce_tx_intr(struct bce_softc *sc) 6950{ 6951 struct ifnet *ifp = sc->bce_ifp; 6952 u16 hw_tx_cons, sw_tx_cons, sw_tx_chain_cons; 6953 6954 DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_INTR); 6955 DBRUN(sc->interrupts_tx++); 6956 DBPRINT(sc, BCE_EXTREME_SEND, "%s(enter): tx_prod = 0x%04X, " 6957 "tx_cons = 0x%04X, tx_prod_bseq = 0x%08X\n", 6958 __FUNCTION__, sc->tx_prod, sc->tx_cons, sc->tx_prod_bseq); 6959 6960 BCE_LOCK_ASSERT(sc); 6961 6962 /* Get the hardware's view of the TX consumer index. */ 6963 hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc); 6964 sw_tx_cons = sc->tx_cons; 6965 6966 /* Prevent speculative reads of the status block. */ 6967 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 6968 BUS_SPACE_BARRIER_READ); 6969 6970 /* Cycle through any completed TX chain page entries. */ 6971 while (sw_tx_cons != hw_tx_cons) { 6972#ifdef BCE_DEBUG 6973 struct tx_bd *txbd = NULL; 6974#endif 6975 sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons); 6976 6977 DBPRINT(sc, BCE_INFO_SEND, 6978 "%s(): hw_tx_cons = 0x%04X, sw_tx_cons = 0x%04X, " 6979 "sw_tx_chain_cons = 0x%04X\n", 6980 __FUNCTION__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons); 6981 6982 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD_ALLOC), 6983 BCE_PRINTF("%s(%d): TX chain consumer out of range! " 6984 " 0x%04X > 0x%04X\n", __FILE__, __LINE__, sw_tx_chain_cons, 6985 (int) MAX_TX_BD_ALLOC); 6986 bce_breakpoint(sc)); 6987 6988 DBRUN(txbd = &sc->tx_bd_chain[TX_PAGE(sw_tx_chain_cons)] 6989 [TX_IDX(sw_tx_chain_cons)]); 6990 6991 DBRUNIF((txbd == NULL), 6992 BCE_PRINTF("%s(%d): Unexpected NULL tx_bd[0x%04X]!\n", 6993 __FILE__, __LINE__, sw_tx_chain_cons); 6994 bce_breakpoint(sc)); 6995 6996 DBRUNMSG(BCE_INFO_SEND, BCE_PRINTF("%s(): ", __FUNCTION__); 6997 bce_dump_txbd(sc, sw_tx_chain_cons, txbd)); 6998 6999 /* 7000 * Free the associated mbuf. Remember 7001 * that only the last tx_bd of a packet 7002 * has an mbuf pointer and DMA map. 7003 */ 7004 if (sc->tx_mbuf_ptr[sw_tx_chain_cons] != NULL) { 7005 7006 /* Validate that this is the last tx_bd. */ 7007 DBRUNIF((!(txbd->tx_bd_flags & TX_BD_FLAGS_END)), 7008 BCE_PRINTF("%s(%d): tx_bd END flag not set but " 7009 "txmbuf == NULL!\n", __FILE__, __LINE__); 7010 bce_breakpoint(sc)); 7011 7012 DBRUNMSG(BCE_INFO_SEND, 7013 BCE_PRINTF("%s(): Unloading map/freeing mbuf " 7014 "from tx_bd[0x%04X]\n", __FUNCTION__, 7015 sw_tx_chain_cons)); 7016 7017 /* Unmap the mbuf. */ 7018 bus_dmamap_unload(sc->tx_mbuf_tag, 7019 sc->tx_mbuf_map[sw_tx_chain_cons]); 7020 7021 /* Free the mbuf. */ 7022 m_freem(sc->tx_mbuf_ptr[sw_tx_chain_cons]); 7023 sc->tx_mbuf_ptr[sw_tx_chain_cons] = NULL; 7024 DBRUN(sc->debug_tx_mbuf_alloc--); 7025 7026 ifp->if_opackets++; 7027 } 7028 7029 sc->used_tx_bd--; 7030 sw_tx_cons = NEXT_TX_BD(sw_tx_cons); 7031 7032 /* Refresh hw_cons to see if there's new work. */ 7033 hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc); 7034 7035 /* Prevent speculative reads of the status block. */ 7036 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 7037 BUS_SPACE_BARRIER_READ); 7038 } 7039 7040 /* Clear the TX timeout timer. */ 7041 sc->watchdog_timer = 0; 7042 7043 /* Clear the tx hardware queue full flag. */ 7044 if (sc->used_tx_bd < sc->max_tx_bd) { 7045 DBRUNIF((ifp->if_drv_flags & IFF_DRV_OACTIVE), 7046 DBPRINT(sc, BCE_INFO_SEND, 7047 "%s(): Open TX chain! %d/%d (used/total)\n", 7048 __FUNCTION__, sc->used_tx_bd, sc->max_tx_bd)); 7049 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 7050 } 7051 7052 sc->tx_cons = sw_tx_cons; 7053 7054 DBPRINT(sc, BCE_EXTREME_SEND, "%s(exit): tx_prod = 0x%04X, " 7055 "tx_cons = 0x%04X, tx_prod_bseq = 0x%08X\n", 7056 __FUNCTION__, sc->tx_prod, sc->tx_cons, sc->tx_prod_bseq); 7057 DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_INTR); 7058} 7059 7060 7061/****************************************************************************/ 7062/* Disables interrupt generation. */ 7063/* */ 7064/* Returns: */ 7065/* Nothing. */ 7066/****************************************************************************/ 7067static void 7068bce_disable_intr(struct bce_softc *sc) 7069{ 7070 DBENTER(BCE_VERBOSE_INTR); 7071 7072 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT); 7073 REG_RD(sc, BCE_PCICFG_INT_ACK_CMD); 7074 7075 DBEXIT(BCE_VERBOSE_INTR); 7076} 7077 7078 7079/****************************************************************************/ 7080/* Enables interrupt generation. */ 7081/* */ 7082/* Returns: */ 7083/* Nothing. */ 7084/****************************************************************************/ 7085static void 7086bce_enable_intr(struct bce_softc *sc, int coal_now) 7087{ 7088 DBENTER(BCE_VERBOSE_INTR); 7089 7090 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 7091 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | 7092 BCE_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx); 7093 7094 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 7095 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx); 7096 7097 /* Force an immediate interrupt (whether there is new data or not). */ 7098 if (coal_now) 7099 REG_WR(sc, BCE_HC_COMMAND, sc->hc_command | BCE_HC_COMMAND_COAL_NOW); 7100 7101 DBEXIT(BCE_VERBOSE_INTR); 7102} 7103 7104 7105/****************************************************************************/ 7106/* Handles controller initialization. */ 7107/* */ 7108/* Returns: */ 7109/* Nothing. */ 7110/****************************************************************************/ 7111static void 7112bce_init_locked(struct bce_softc *sc) 7113{ 7114 struct ifnet *ifp; 7115 u32 ether_mtu = 0; 7116 7117 DBENTER(BCE_VERBOSE_RESET); 7118 7119 BCE_LOCK_ASSERT(sc); 7120 7121 ifp = sc->bce_ifp; 7122 7123 /* Check if the driver is still running and bail out if it is. */ 7124 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 7125 goto bce_init_locked_exit; 7126 7127 bce_stop(sc); 7128 7129 if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) { 7130 BCE_PRINTF("%s(%d): Controller reset failed!\n", 7131 __FILE__, __LINE__); 7132 goto bce_init_locked_exit; 7133 } 7134 7135 if (bce_chipinit(sc)) { 7136 BCE_PRINTF("%s(%d): Controller initialization failed!\n", 7137 __FILE__, __LINE__); 7138 goto bce_init_locked_exit; 7139 } 7140 7141 if (bce_blockinit(sc)) { 7142 BCE_PRINTF("%s(%d): Block initialization failed!\n", 7143 __FILE__, __LINE__); 7144 goto bce_init_locked_exit; 7145 } 7146 7147 /* Load our MAC address. */ 7148 bcopy(IF_LLADDR(sc->bce_ifp), sc->eaddr, ETHER_ADDR_LEN); 7149 bce_set_mac_addr(sc); 7150 7151 if (bce_hdr_split == FALSE) 7152 bce_get_rx_buffer_sizes(sc, ifp->if_mtu); 7153 /* 7154 * Calculate and program the hardware Ethernet MTU 7155 * size. Be generous on the receive if we have room 7156 * and allowed by the user. 7157 */ 7158 if (bce_strict_rx_mtu == TRUE) 7159 ether_mtu = ifp->if_mtu; 7160 else { 7161 if (bce_hdr_split == TRUE) { 7162 if (ifp->if_mtu <= sc->rx_bd_mbuf_data_len + MCLBYTES) 7163 ether_mtu = sc->rx_bd_mbuf_data_len + 7164 MCLBYTES; 7165 else 7166 ether_mtu = ifp->if_mtu; 7167 } else { 7168 if (ifp->if_mtu <= sc->rx_bd_mbuf_data_len) 7169 ether_mtu = sc->rx_bd_mbuf_data_len; 7170 else 7171 ether_mtu = ifp->if_mtu; 7172 } 7173 } 7174 7175 ether_mtu += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN; 7176 7177 DBPRINT(sc, BCE_INFO_MISC, "%s(): setting h/w mtu = %d\n", 7178 __FUNCTION__, ether_mtu); 7179 7180 /* Program the mtu, enabling jumbo frame support if necessary. */ 7181 if (ether_mtu > (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN)) 7182 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, 7183 min(ether_mtu, BCE_MAX_JUMBO_ETHER_MTU) | 7184 BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA); 7185 else 7186 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, ether_mtu); 7187 7188 /* Program appropriate promiscuous/multicast filtering. */ 7189 bce_set_rx_mode(sc); 7190 7191 if (bce_hdr_split == TRUE) { 7192 /* Init page buffer descriptor chain. */ 7193 bce_init_pg_chain(sc); 7194 } 7195 7196 /* Init RX buffer descriptor chain. */ 7197 bce_init_rx_chain(sc); 7198 7199 /* Init TX buffer descriptor chain. */ 7200 bce_init_tx_chain(sc); 7201 7202 /* Enable host interrupts. */ 7203 bce_enable_intr(sc, 1); 7204 7205 bce_ifmedia_upd_locked(ifp); 7206 7207 /* Let the OS know the driver is up and running. */ 7208 ifp->if_drv_flags |= IFF_DRV_RUNNING; 7209 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 7210 7211 callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc); 7212 7213bce_init_locked_exit: 7214 DBEXIT(BCE_VERBOSE_RESET); 7215} 7216 7217 7218/****************************************************************************/ 7219/* Initialize the controller just enough so that any management firmware */ 7220/* running on the device will continue to operate correctly. */ 7221/* */ 7222/* Returns: */ 7223/* Nothing. */ 7224/****************************************************************************/ 7225static void 7226bce_mgmt_init_locked(struct bce_softc *sc) 7227{ 7228 struct ifnet *ifp; 7229 7230 DBENTER(BCE_VERBOSE_RESET); 7231 7232 BCE_LOCK_ASSERT(sc); 7233 7234 /* Bail out if management firmware is not running. */ 7235 if (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG)) { 7236 DBPRINT(sc, BCE_VERBOSE_SPECIAL, 7237 "No management firmware running...\n"); 7238 goto bce_mgmt_init_locked_exit; 7239 } 7240 7241 ifp = sc->bce_ifp; 7242 7243 /* Enable all critical blocks in the MAC. */ 7244 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT); 7245 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS); 7246 DELAY(20); 7247 7248 bce_ifmedia_upd_locked(ifp); 7249 7250bce_mgmt_init_locked_exit: 7251 DBEXIT(BCE_VERBOSE_RESET); 7252} 7253 7254 7255/****************************************************************************/ 7256/* Handles controller initialization when called from an unlocked routine. */ 7257/* */ 7258/* Returns: */ 7259/* Nothing. */ 7260/****************************************************************************/ 7261static void 7262bce_init(void *xsc) 7263{ 7264 struct bce_softc *sc = xsc; 7265 7266 DBENTER(BCE_VERBOSE_RESET); 7267 7268 BCE_LOCK(sc); 7269 bce_init_locked(sc); 7270 BCE_UNLOCK(sc); 7271 7272 DBEXIT(BCE_VERBOSE_RESET); 7273} 7274 7275 7276/****************************************************************************/ 7277/* Modifies an mbuf for TSO on the hardware. */ 7278/* */ 7279/* Returns: */ 7280/* Pointer to a modified mbuf. */ 7281/****************************************************************************/ 7282static struct mbuf * 7283bce_tso_setup(struct bce_softc *sc, struct mbuf **m_head, u16 *flags) 7284{ 7285 struct mbuf *m; 7286 struct ether_header *eh; 7287 struct ip *ip; 7288 struct tcphdr *th; 7289 u16 etype; 7290 int hdr_len, ip_hlen = 0, tcp_hlen = 0, ip_len = 0; 7291 7292 DBRUN(sc->tso_frames_requested++); 7293 7294 /* Controller may modify mbuf chains. */ 7295 if (M_WRITABLE(*m_head) == 0) { 7296 m = m_dup(*m_head, M_NOWAIT); 7297 m_freem(*m_head); 7298 if (m == NULL) { 7299 sc->mbuf_alloc_failed_count++; 7300 *m_head = NULL; 7301 return (NULL); 7302 } 7303 *m_head = m; 7304 } 7305 7306 /* 7307 * For TSO the controller needs two pieces of info, 7308 * the MSS and the IP+TCP options length. 7309 */ 7310 m = m_pullup(*m_head, sizeof(struct ether_header) + sizeof(struct ip)); 7311 if (m == NULL) { 7312 *m_head = NULL; 7313 return (NULL); 7314 } 7315 eh = mtod(m, struct ether_header *); 7316 etype = ntohs(eh->ether_type); 7317 7318 /* Check for supported TSO Ethernet types (only IPv4 for now) */ 7319 switch (etype) { 7320 case ETHERTYPE_IP: 7321 ip = (struct ip *)(m->m_data + sizeof(struct ether_header)); 7322 /* TSO only supported for TCP protocol. */ 7323 if (ip->ip_p != IPPROTO_TCP) { 7324 BCE_PRINTF("%s(%d): TSO enabled for non-TCP frame!.\n", 7325 __FILE__, __LINE__); 7326 m_freem(*m_head); 7327 *m_head = NULL; 7328 return (NULL); 7329 } 7330 7331 /* Get IP header length in bytes (min 20) */ 7332 ip_hlen = ip->ip_hl << 2; 7333 m = m_pullup(*m_head, sizeof(struct ether_header) + ip_hlen + 7334 sizeof(struct tcphdr)); 7335 if (m == NULL) { 7336 *m_head = NULL; 7337 return (NULL); 7338 } 7339 7340 /* Get the TCP header length in bytes (min 20) */ 7341 ip = (struct ip *)(m->m_data + sizeof(struct ether_header)); 7342 th = (struct tcphdr *)((caddr_t)ip + ip_hlen); 7343 tcp_hlen = (th->th_off << 2); 7344 7345 /* Make sure all IP/TCP options live in the same buffer. */ 7346 m = m_pullup(*m_head, sizeof(struct ether_header)+ ip_hlen + 7347 tcp_hlen); 7348 if (m == NULL) { 7349 *m_head = NULL; 7350 return (NULL); 7351 } 7352 7353 /* Clear IP header length and checksum, will be calc'd by h/w. */ 7354 ip = (struct ip *)(m->m_data + sizeof(struct ether_header)); 7355 ip_len = ip->ip_len; 7356 ip->ip_len = 0; 7357 ip->ip_sum = 0; 7358 break; 7359 case ETHERTYPE_IPV6: 7360 BCE_PRINTF("%s(%d): TSO over IPv6 not supported!.\n", 7361 __FILE__, __LINE__); 7362 m_freem(*m_head); 7363 *m_head = NULL; 7364 return (NULL); 7365 /* NOT REACHED */ 7366 default: 7367 BCE_PRINTF("%s(%d): TSO enabled for unsupported protocol!.\n", 7368 __FILE__, __LINE__); 7369 m_freem(*m_head); 7370 *m_head = NULL; 7371 return (NULL); 7372 } 7373 7374 hdr_len = sizeof(struct ether_header) + ip_hlen + tcp_hlen; 7375 7376 DBPRINT(sc, BCE_EXTREME_SEND, "%s(): hdr_len = %d, e_hlen = %d, " 7377 "ip_hlen = %d, tcp_hlen = %d, ip_len = %d\n", 7378 __FUNCTION__, hdr_len, (int) sizeof(struct ether_header), ip_hlen, 7379 tcp_hlen, ip_len); 7380 7381 /* Set the LSO flag in the TX BD */ 7382 *flags |= TX_BD_FLAGS_SW_LSO; 7383 7384 /* Set the length of IP + TCP options (in 32 bit words) */ 7385 *flags |= (((ip_hlen + tcp_hlen - sizeof(struct ip) - 7386 sizeof(struct tcphdr)) >> 2) << 8); 7387 7388 DBRUN(sc->tso_frames_completed++); 7389 return (*m_head); 7390} 7391 7392 7393/****************************************************************************/ 7394/* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */ 7395/* memory visible to the controller. */ 7396/* */ 7397/* Returns: */ 7398/* 0 for success, positive value for failure. */ 7399/* Modified: */ 7400/* m_head: May be set to NULL if MBUF is excessively fragmented. */ 7401/****************************************************************************/ 7402static int 7403bce_tx_encap(struct bce_softc *sc, struct mbuf **m_head) 7404{ 7405 bus_dma_segment_t segs[BCE_MAX_SEGMENTS]; 7406 bus_dmamap_t map; 7407 struct tx_bd *txbd = NULL; 7408 struct mbuf *m0; 7409 u16 prod, chain_prod, mss = 0, vlan_tag = 0, flags = 0; 7410 u32 prod_bseq; 7411 7412#ifdef BCE_DEBUG 7413 u16 debug_prod; 7414#endif 7415 7416 int i, error, nsegs, rc = 0; 7417 7418 DBENTER(BCE_VERBOSE_SEND); 7419 7420 /* Make sure we have room in the TX chain. */ 7421 if (sc->used_tx_bd >= sc->max_tx_bd) 7422 goto bce_tx_encap_exit; 7423 7424 /* Transfer any checksum offload flags to the bd. */ 7425 m0 = *m_head; 7426 if (m0->m_pkthdr.csum_flags) { 7427 if (m0->m_pkthdr.csum_flags & CSUM_TSO) { 7428 m0 = bce_tso_setup(sc, m_head, &flags); 7429 if (m0 == NULL) { 7430 DBRUN(sc->tso_frames_failed++); 7431 goto bce_tx_encap_exit; 7432 } 7433 mss = htole16(m0->m_pkthdr.tso_segsz); 7434 } else { 7435 if (m0->m_pkthdr.csum_flags & CSUM_IP) 7436 flags |= TX_BD_FLAGS_IP_CKSUM; 7437 if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 7438 flags |= TX_BD_FLAGS_TCP_UDP_CKSUM; 7439 } 7440 } 7441 7442 /* Transfer any VLAN tags to the bd. */ 7443 if (m0->m_flags & M_VLANTAG) { 7444 flags |= TX_BD_FLAGS_VLAN_TAG; 7445 vlan_tag = m0->m_pkthdr.ether_vtag; 7446 } 7447 7448 /* Map the mbuf into DMAable memory. */ 7449 prod = sc->tx_prod; 7450 chain_prod = TX_CHAIN_IDX(prod); 7451 map = sc->tx_mbuf_map[chain_prod]; 7452 7453 /* Map the mbuf into our DMA address space. */ 7454 error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag, map, m0, 7455 segs, &nsegs, BUS_DMA_NOWAIT); 7456 7457 /* Check if the DMA mapping was successful */ 7458 if (error == EFBIG) { 7459 sc->mbuf_frag_count++; 7460 7461 /* Try to defrag the mbuf. */ 7462 m0 = m_collapse(*m_head, M_NOWAIT, BCE_MAX_SEGMENTS); 7463 if (m0 == NULL) { 7464 /* Defrag was unsuccessful */ 7465 m_freem(*m_head); 7466 *m_head = NULL; 7467 sc->mbuf_alloc_failed_count++; 7468 rc = ENOBUFS; 7469 goto bce_tx_encap_exit; 7470 } 7471 7472 /* Defrag was successful, try mapping again */ 7473 *m_head = m0; 7474 error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag, 7475 map, m0, segs, &nsegs, BUS_DMA_NOWAIT); 7476 7477 /* Still getting an error after a defrag. */ 7478 if (error == ENOMEM) { 7479 /* Insufficient DMA buffers available. */ 7480 sc->dma_map_addr_tx_failed_count++; 7481 rc = error; 7482 goto bce_tx_encap_exit; 7483 } else if (error != 0) { 7484 /* Release it and return an error. */ 7485 BCE_PRINTF("%s(%d): Unknown error mapping mbuf into " 7486 "TX chain!\n", __FILE__, __LINE__); 7487 m_freem(m0); 7488 *m_head = NULL; 7489 sc->dma_map_addr_tx_failed_count++; 7490 rc = ENOBUFS; 7491 goto bce_tx_encap_exit; 7492 } 7493 } else if (error == ENOMEM) { 7494 /* Insufficient DMA buffers available. */ 7495 sc->dma_map_addr_tx_failed_count++; 7496 rc = error; 7497 goto bce_tx_encap_exit; 7498 } else if (error != 0) { 7499 m_freem(m0); 7500 *m_head = NULL; 7501 sc->dma_map_addr_tx_failed_count++; 7502 rc = error; 7503 goto bce_tx_encap_exit; 7504 } 7505 7506 /* Make sure there's room in the chain */ 7507 if (nsegs > (sc->max_tx_bd - sc->used_tx_bd)) { 7508 bus_dmamap_unload(sc->tx_mbuf_tag, map); 7509 rc = ENOBUFS; 7510 goto bce_tx_encap_exit; 7511 } 7512 7513 /* prod points to an empty tx_bd at this point. */ 7514 prod_bseq = sc->tx_prod_bseq; 7515 7516#ifdef BCE_DEBUG 7517 debug_prod = chain_prod; 7518#endif 7519 7520 DBPRINT(sc, BCE_INFO_SEND, 7521 "%s(start): prod = 0x%04X, chain_prod = 0x%04X, " 7522 "prod_bseq = 0x%08X\n", 7523 __FUNCTION__, prod, chain_prod, prod_bseq); 7524 7525 /* 7526 * Cycle through each mbuf segment that makes up 7527 * the outgoing frame, gathering the mapping info 7528 * for that segment and creating a tx_bd for 7529 * the mbuf. 7530 */ 7531 for (i = 0; i < nsegs ; i++) { 7532 7533 chain_prod = TX_CHAIN_IDX(prod); 7534 txbd= &sc->tx_bd_chain[TX_PAGE(chain_prod)] 7535 [TX_IDX(chain_prod)]; 7536 7537 txbd->tx_bd_haddr_lo = 7538 htole32(BCE_ADDR_LO(segs[i].ds_addr)); 7539 txbd->tx_bd_haddr_hi = 7540 htole32(BCE_ADDR_HI(segs[i].ds_addr)); 7541 txbd->tx_bd_mss_nbytes = htole32(mss << 16) | 7542 htole16(segs[i].ds_len); 7543 txbd->tx_bd_vlan_tag = htole16(vlan_tag); 7544 txbd->tx_bd_flags = htole16(flags); 7545 prod_bseq += segs[i].ds_len; 7546 if (i == 0) 7547 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_START); 7548 prod = NEXT_TX_BD(prod); 7549 } 7550 7551 /* Set the END flag on the last TX buffer descriptor. */ 7552 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_END); 7553 7554 DBRUNMSG(BCE_EXTREME_SEND, 7555 bce_dump_tx_chain(sc, debug_prod, nsegs)); 7556 7557 /* 7558 * Ensure that the mbuf pointer for this transmission 7559 * is placed at the array index of the last 7560 * descriptor in this chain. This is done 7561 * because a single map is used for all 7562 * segments of the mbuf and we don't want to 7563 * unload the map before all of the segments 7564 * have been freed. 7565 */ 7566 sc->tx_mbuf_ptr[chain_prod] = m0; 7567 sc->used_tx_bd += nsegs; 7568 7569 /* Update some debug statistic counters */ 7570 DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark), 7571 sc->tx_hi_watermark = sc->used_tx_bd); 7572 DBRUNIF((sc->used_tx_bd == sc->max_tx_bd), sc->tx_full_count++); 7573 DBRUNIF(sc->debug_tx_mbuf_alloc++); 7574 7575 DBRUNMSG(BCE_EXTREME_SEND, bce_dump_tx_mbuf_chain(sc, chain_prod, 1)); 7576 7577 /* prod points to the next free tx_bd at this point. */ 7578 sc->tx_prod = prod; 7579 sc->tx_prod_bseq = prod_bseq; 7580 7581 /* Tell the chip about the waiting TX frames. */ 7582 REG_WR16(sc, MB_GET_CID_ADDR(TX_CID) + 7583 BCE_L2MQ_TX_HOST_BIDX, sc->tx_prod); 7584 REG_WR(sc, MB_GET_CID_ADDR(TX_CID) + 7585 BCE_L2MQ_TX_HOST_BSEQ, sc->tx_prod_bseq); 7586 7587bce_tx_encap_exit: 7588 DBEXIT(BCE_VERBOSE_SEND); 7589 return(rc); 7590} 7591 7592 7593/****************************************************************************/ 7594/* Main transmit routine when called from another routine with a lock. */ 7595/* */ 7596/* Returns: */ 7597/* Nothing. */ 7598/****************************************************************************/ 7599static void 7600bce_start_locked(struct ifnet *ifp) 7601{ 7602 struct bce_softc *sc = ifp->if_softc; 7603 struct mbuf *m_head = NULL; 7604 int count = 0; 7605 u16 tx_prod, tx_chain_prod; 7606 7607 DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 7608 7609 BCE_LOCK_ASSERT(sc); 7610 7611 /* prod points to the next free tx_bd. */ 7612 tx_prod = sc->tx_prod; 7613 tx_chain_prod = TX_CHAIN_IDX(tx_prod); 7614 7615 DBPRINT(sc, BCE_INFO_SEND, 7616 "%s(enter): tx_prod = 0x%04X, tx_chain_prod = 0x%04X, " 7617 "tx_prod_bseq = 0x%08X\n", 7618 __FUNCTION__, tx_prod, tx_chain_prod, sc->tx_prod_bseq); 7619 7620 /* If there's no link or the transmit queue is empty then just exit. */ 7621 if (sc->bce_link_up == FALSE) { 7622 DBPRINT(sc, BCE_INFO_SEND, "%s(): No link.\n", 7623 __FUNCTION__); 7624 goto bce_start_locked_exit; 7625 } 7626 7627 if (IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 7628 DBPRINT(sc, BCE_INFO_SEND, "%s(): Transmit queue empty.\n", 7629 __FUNCTION__); 7630 goto bce_start_locked_exit; 7631 } 7632 7633 /* 7634 * Keep adding entries while there is space in the ring. 7635 */ 7636 while (sc->used_tx_bd < sc->max_tx_bd) { 7637 7638 /* Check for any frames to send. */ 7639 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 7640 7641 /* Stop when the transmit queue is empty. */ 7642 if (m_head == NULL) 7643 break; 7644 7645 /* 7646 * Pack the data into the transmit ring. If we 7647 * don't have room, place the mbuf back at the 7648 * head of the queue and set the OACTIVE flag 7649 * to wait for the NIC to drain the chain. 7650 */ 7651 if (bce_tx_encap(sc, &m_head)) { 7652 if (m_head != NULL) 7653 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 7654 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 7655 DBPRINT(sc, BCE_INFO_SEND, 7656 "TX chain is closed for business! Total " 7657 "tx_bd used = %d\n", sc->used_tx_bd); 7658 break; 7659 } 7660 7661 count++; 7662 7663 /* Send a copy of the frame to any BPF listeners. */ 7664 ETHER_BPF_MTAP(ifp, m_head); 7665 } 7666 7667 /* Exit if no packets were dequeued. */ 7668 if (count == 0) { 7669 DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): No packets were " 7670 "dequeued\n", __FUNCTION__); 7671 goto bce_start_locked_exit; 7672 } 7673 7674 DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): Inserted %d frames into " 7675 "send queue.\n", __FUNCTION__, count); 7676 7677 /* Set the tx timeout. */ 7678 sc->watchdog_timer = BCE_TX_TIMEOUT; 7679 7680 DBRUNMSG(BCE_VERBOSE_SEND, bce_dump_ctx(sc, TX_CID)); 7681 DBRUNMSG(BCE_VERBOSE_SEND, bce_dump_mq_regs(sc)); 7682 7683bce_start_locked_exit: 7684 DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 7685} 7686 7687 7688/****************************************************************************/ 7689/* Main transmit routine when called from another routine without a lock. */ 7690/* */ 7691/* Returns: */ 7692/* Nothing. */ 7693/****************************************************************************/ 7694static void 7695bce_start(struct ifnet *ifp) 7696{ 7697 struct bce_softc *sc = ifp->if_softc; 7698 7699 DBENTER(BCE_VERBOSE_SEND); 7700 7701 BCE_LOCK(sc); 7702 bce_start_locked(ifp); 7703 BCE_UNLOCK(sc); 7704 7705 DBEXIT(BCE_VERBOSE_SEND); 7706} 7707 7708 7709/****************************************************************************/ 7710/* Handles any IOCTL calls from the operating system. */ 7711/* */ 7712/* Returns: */ 7713/* 0 for success, positive value for failure. */ 7714/****************************************************************************/ 7715static int 7716bce_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 7717{ 7718 struct bce_softc *sc = ifp->if_softc; 7719 struct ifreq *ifr = (struct ifreq *) data; 7720 struct mii_data *mii; 7721 int mask, error = 0; 7722 7723 DBENTER(BCE_VERBOSE_MISC); 7724 7725 switch(command) { 7726 7727 /* Set the interface MTU. */ 7728 case SIOCSIFMTU: 7729 /* Check that the MTU setting is supported. */ 7730 if ((ifr->ifr_mtu < BCE_MIN_MTU) || 7731 (ifr->ifr_mtu > BCE_MAX_JUMBO_MTU)) { 7732 error = EINVAL; 7733 break; 7734 } 7735 7736 DBPRINT(sc, BCE_INFO_MISC, 7737 "SIOCSIFMTU: Changing MTU from %d to %d\n", 7738 (int) ifp->if_mtu, (int) ifr->ifr_mtu); 7739 7740 BCE_LOCK(sc); 7741 ifp->if_mtu = ifr->ifr_mtu; 7742 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 7743 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 7744 bce_init_locked(sc); 7745 } 7746 BCE_UNLOCK(sc); 7747 break; 7748 7749 /* Set interface flags. */ 7750 case SIOCSIFFLAGS: 7751 DBPRINT(sc, BCE_VERBOSE_SPECIAL, "Received SIOCSIFFLAGS\n"); 7752 7753 BCE_LOCK(sc); 7754 7755 /* Check if the interface is up. */ 7756 if (ifp->if_flags & IFF_UP) { 7757 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 7758 /* Change promiscuous/multicast flags as necessary. */ 7759 bce_set_rx_mode(sc); 7760 } else { 7761 /* Start the HW */ 7762 bce_init_locked(sc); 7763 } 7764 } else { 7765 /* The interface is down, check if driver is running. */ 7766 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 7767 bce_stop(sc); 7768 7769 /* If MFW is running, restart the controller a bit. */ 7770 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 7771 bce_reset(sc, BCE_DRV_MSG_CODE_RESET); 7772 bce_chipinit(sc); 7773 bce_mgmt_init_locked(sc); 7774 } 7775 } 7776 } 7777 7778 BCE_UNLOCK(sc); 7779 break; 7780 7781 /* Add/Delete multicast address */ 7782 case SIOCADDMULTI: 7783 case SIOCDELMULTI: 7784 DBPRINT(sc, BCE_VERBOSE_MISC, 7785 "Received SIOCADDMULTI/SIOCDELMULTI\n"); 7786 7787 BCE_LOCK(sc); 7788 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 7789 bce_set_rx_mode(sc); 7790 BCE_UNLOCK(sc); 7791 7792 break; 7793 7794 /* Set/Get Interface media */ 7795 case SIOCSIFMEDIA: 7796 case SIOCGIFMEDIA: 7797 DBPRINT(sc, BCE_VERBOSE_MISC, 7798 "Received SIOCSIFMEDIA/SIOCGIFMEDIA\n"); 7799 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) 7800 error = ifmedia_ioctl(ifp, ifr, &sc->bce_ifmedia, 7801 command); 7802 else { 7803 mii = device_get_softc(sc->bce_miibus); 7804 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 7805 command); 7806 } 7807 break; 7808 7809 /* Set interface capability */ 7810 case SIOCSIFCAP: 7811 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 7812 DBPRINT(sc, BCE_INFO_MISC, 7813 "Received SIOCSIFCAP = 0x%08X\n", (u32) mask); 7814 7815 /* Toggle the TX checksum capabilities enable flag. */ 7816 if (mask & IFCAP_TXCSUM && 7817 ifp->if_capabilities & IFCAP_TXCSUM) { 7818 ifp->if_capenable ^= IFCAP_TXCSUM; 7819 if (IFCAP_TXCSUM & ifp->if_capenable) 7820 ifp->if_hwassist |= BCE_IF_HWASSIST; 7821 else 7822 ifp->if_hwassist &= ~BCE_IF_HWASSIST; 7823 } 7824 7825 /* Toggle the RX checksum capabilities enable flag. */ 7826 if (mask & IFCAP_RXCSUM && 7827 ifp->if_capabilities & IFCAP_RXCSUM) 7828 ifp->if_capenable ^= IFCAP_RXCSUM; 7829 7830 /* Toggle the TSO capabilities enable flag. */ 7831 if (bce_tso_enable && (mask & IFCAP_TSO4) && 7832 ifp->if_capabilities & IFCAP_TSO4) { 7833 ifp->if_capenable ^= IFCAP_TSO4; 7834 if (IFCAP_TSO4 & ifp->if_capenable) 7835 ifp->if_hwassist |= CSUM_TSO; 7836 else 7837 ifp->if_hwassist &= ~CSUM_TSO; 7838 } 7839 7840 if (mask & IFCAP_VLAN_HWCSUM && 7841 ifp->if_capabilities & IFCAP_VLAN_HWCSUM) 7842 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 7843 7844 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 7845 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 7846 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 7847 /* 7848 * Don't actually disable VLAN tag stripping as 7849 * management firmware (ASF/IPMI/UMP) requires the 7850 * feature. If VLAN tag stripping is disabled driver 7851 * will manually reconstruct the VLAN frame by 7852 * appending stripped VLAN tag. 7853 */ 7854 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 7855 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING)) { 7856 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 7857 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 7858 == 0) 7859 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 7860 } 7861 VLAN_CAPABILITIES(ifp); 7862 break; 7863 default: 7864 /* We don't know how to handle the IOCTL, pass it on. */ 7865 error = ether_ioctl(ifp, command, data); 7866 break; 7867 } 7868 7869 DBEXIT(BCE_VERBOSE_MISC); 7870 return(error); 7871} 7872 7873 7874/****************************************************************************/ 7875/* Transmit timeout handler. */ 7876/* */ 7877/* Returns: */ 7878/* Nothing. */ 7879/****************************************************************************/ 7880static void 7881bce_watchdog(struct bce_softc *sc) 7882{ 7883 uint32_t status; 7884 7885 DBENTER(BCE_EXTREME_SEND); 7886 7887 BCE_LOCK_ASSERT(sc); 7888 7889 status = 0; 7890 /* If the watchdog timer hasn't expired then just exit. */ 7891 if (sc->watchdog_timer == 0 || --sc->watchdog_timer) 7892 goto bce_watchdog_exit; 7893 7894 status = REG_RD(sc, BCE_EMAC_RX_STATUS); 7895 /* If pause frames are active then don't reset the hardware. */ 7896 if ((sc->bce_flags & BCE_USING_RX_FLOW_CONTROL) != 0) { 7897 if ((status & BCE_EMAC_RX_STATUS_FFED) != 0) { 7898 /* 7899 * If link partner has us in XOFF state then wait for 7900 * the condition to clear. 7901 */ 7902 sc->watchdog_timer = BCE_TX_TIMEOUT; 7903 goto bce_watchdog_exit; 7904 } else if ((status & BCE_EMAC_RX_STATUS_FF_RECEIVED) != 0 && 7905 (status & BCE_EMAC_RX_STATUS_N_RECEIVED) != 0) { 7906 /* 7907 * If we're not currently XOFF'ed but have recently 7908 * been XOFF'd/XON'd then assume that's delaying TX 7909 * this time around. 7910 */ 7911 sc->watchdog_timer = BCE_TX_TIMEOUT; 7912 goto bce_watchdog_exit; 7913 } 7914 /* 7915 * Any other condition is unexpected and the controller 7916 * should be reset. 7917 */ 7918 } 7919 7920 BCE_PRINTF("%s(%d): Watchdog timeout occurred, resetting!\n", 7921 __FILE__, __LINE__); 7922 7923 DBRUNMSG(BCE_INFO, 7924 bce_dump_driver_state(sc); 7925 bce_dump_status_block(sc); 7926 bce_dump_stats_block(sc); 7927 bce_dump_ftqs(sc); 7928 bce_dump_txp_state(sc, 0); 7929 bce_dump_rxp_state(sc, 0); 7930 bce_dump_tpat_state(sc, 0); 7931 bce_dump_cp_state(sc, 0); 7932 bce_dump_com_state(sc, 0)); 7933 7934 DBRUN(bce_breakpoint(sc)); 7935 7936 sc->bce_ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 7937 7938 bce_init_locked(sc); 7939 sc->bce_ifp->if_oerrors++; 7940 7941bce_watchdog_exit: 7942 REG_WR(sc, BCE_EMAC_RX_STATUS, status); 7943 DBEXIT(BCE_EXTREME_SEND); 7944} 7945 7946 7947/* 7948 * Interrupt handler. 7949 */ 7950/****************************************************************************/ 7951/* Main interrupt entry point. Verifies that the controller generated the */ 7952/* interrupt and then calls a separate routine for handle the various */ 7953/* interrupt causes (PHY, TX, RX). */ 7954/* */ 7955/* Returns: */ 7956/* Nothing. */ 7957/****************************************************************************/ 7958static void 7959bce_intr(void *xsc) 7960{ 7961 struct bce_softc *sc; 7962 struct ifnet *ifp; 7963 u32 status_attn_bits; 7964 u16 hw_rx_cons, hw_tx_cons; 7965 7966 sc = xsc; 7967 ifp = sc->bce_ifp; 7968 7969 DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 7970 DBRUNMSG(BCE_VERBOSE_INTR, bce_dump_status_block(sc)); 7971 DBRUNMSG(BCE_VERBOSE_INTR, bce_dump_stats_block(sc)); 7972 7973 BCE_LOCK(sc); 7974 7975 DBRUN(sc->interrupts_generated++); 7976 7977 /* Synchnorize before we read from interface's status block */ 7978 bus_dmamap_sync(sc->status_tag, sc->status_map, BUS_DMASYNC_POSTREAD); 7979 7980 /* 7981 * If the hardware status block index matches the last value read 7982 * by the driver and we haven't asserted our interrupt then there's 7983 * nothing to do. This may only happen in case of INTx due to the 7984 * interrupt arriving at the CPU before the status block is updated. 7985 */ 7986 if ((sc->bce_flags & (BCE_USING_MSI_FLAG | BCE_USING_MSIX_FLAG)) == 0 && 7987 sc->status_block->status_idx == sc->last_status_idx && 7988 (REG_RD(sc, BCE_PCICFG_MISC_STATUS) & 7989 BCE_PCICFG_MISC_STATUS_INTA_VALUE)) { 7990 DBPRINT(sc, BCE_VERBOSE_INTR, "%s(): Spurious interrupt.\n", 7991 __FUNCTION__); 7992 goto bce_intr_exit; 7993 } 7994 7995 /* Ack the interrupt and stop others from occuring. */ 7996 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 7997 BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM | 7998 BCE_PCICFG_INT_ACK_CMD_MASK_INT); 7999 8000 /* Check if the hardware has finished any work. */ 8001 hw_rx_cons = bce_get_hw_rx_cons(sc); 8002 hw_tx_cons = bce_get_hw_tx_cons(sc); 8003 8004 /* Keep processing data as long as there is work to do. */ 8005 for (;;) { 8006 8007 status_attn_bits = sc->status_block->status_attn_bits; 8008 8009 DBRUNIF(DB_RANDOMTRUE(unexpected_attention_sim_control), 8010 BCE_PRINTF("Simulating unexpected status attention " 8011 "bit set."); 8012 sc->unexpected_attention_sim_count++; 8013 status_attn_bits = status_attn_bits | 8014 STATUS_ATTN_BITS_PARITY_ERROR); 8015 8016 /* Was it a link change interrupt? */ 8017 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != 8018 (sc->status_block->status_attn_bits_ack & 8019 STATUS_ATTN_BITS_LINK_STATE)) { 8020 bce_phy_intr(sc); 8021 8022 /* Clear transient updates during link state change. */ 8023 REG_WR(sc, BCE_HC_COMMAND, sc->hc_command | 8024 BCE_HC_COMMAND_COAL_NOW_WO_INT); 8025 REG_RD(sc, BCE_HC_COMMAND); 8026 } 8027 8028 /* If any other attention is asserted, the chip is toast. */ 8029 if (((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) != 8030 (sc->status_block->status_attn_bits_ack & 8031 ~STATUS_ATTN_BITS_LINK_STATE))) { 8032 8033 sc->unexpected_attention_count++; 8034 8035 BCE_PRINTF("%s(%d): Fatal attention detected: " 8036 "0x%08X\n", __FILE__, __LINE__, 8037 sc->status_block->status_attn_bits); 8038 8039 DBRUNMSG(BCE_FATAL, 8040 if (unexpected_attention_sim_control == 0) 8041 bce_breakpoint(sc)); 8042 8043 bce_init_locked(sc); 8044 goto bce_intr_exit; 8045 } 8046 8047 /* Check for any completed RX frames. */ 8048 if (hw_rx_cons != sc->hw_rx_cons) 8049 bce_rx_intr(sc); 8050 8051 /* Check for any completed TX frames. */ 8052 if (hw_tx_cons != sc->hw_tx_cons) 8053 bce_tx_intr(sc); 8054 8055 /* Save status block index value for the next interrupt. */ 8056 sc->last_status_idx = sc->status_block->status_idx; 8057 8058 /* 8059 * Prevent speculative reads from getting 8060 * ahead of the status block. 8061 */ 8062 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 8063 BUS_SPACE_BARRIER_READ); 8064 8065 /* 8066 * If there's no work left then exit the 8067 * interrupt service routine. 8068 */ 8069 hw_rx_cons = bce_get_hw_rx_cons(sc); 8070 hw_tx_cons = bce_get_hw_tx_cons(sc); 8071 8072 if ((hw_rx_cons == sc->hw_rx_cons) && 8073 (hw_tx_cons == sc->hw_tx_cons)) 8074 break; 8075 } 8076 8077 bus_dmamap_sync(sc->status_tag, sc->status_map, BUS_DMASYNC_PREREAD); 8078 8079 /* Re-enable interrupts. */ 8080 bce_enable_intr(sc, 0); 8081 8082 /* Handle any frames that arrived while handling the interrupt. */ 8083 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 8084 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 8085 bce_start_locked(ifp); 8086 8087bce_intr_exit: 8088 BCE_UNLOCK(sc); 8089 8090 DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 8091} 8092 8093 8094/****************************************************************************/ 8095/* Programs the various packet receive modes (broadcast and multicast). */ 8096/* */ 8097/* Returns: */ 8098/* Nothing. */ 8099/****************************************************************************/ 8100static void 8101bce_set_rx_mode(struct bce_softc *sc) 8102{ 8103 struct ifnet *ifp; 8104 struct ifmultiaddr *ifma; 8105 u32 hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 8106 u32 rx_mode, sort_mode; 8107 int h, i; 8108 8109 DBENTER(BCE_VERBOSE_MISC); 8110 8111 BCE_LOCK_ASSERT(sc); 8112 8113 ifp = sc->bce_ifp; 8114 8115 /* Initialize receive mode default settings. */ 8116 rx_mode = sc->rx_mode & ~(BCE_EMAC_RX_MODE_PROMISCUOUS | 8117 BCE_EMAC_RX_MODE_KEEP_VLAN_TAG); 8118 sort_mode = 1 | BCE_RPM_SORT_USER0_BC_EN; 8119 8120 /* 8121 * ASF/IPMI/UMP firmware requires that VLAN tag stripping 8122 * be enbled. 8123 */ 8124 if (!(BCE_IF_CAPABILITIES & IFCAP_VLAN_HWTAGGING) && 8125 (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG))) 8126 rx_mode |= BCE_EMAC_RX_MODE_KEEP_VLAN_TAG; 8127 8128 /* 8129 * Check for promiscuous, all multicast, or selected 8130 * multicast address filtering. 8131 */ 8132 if (ifp->if_flags & IFF_PROMISC) { 8133 DBPRINT(sc, BCE_INFO_MISC, "Enabling promiscuous mode.\n"); 8134 8135 /* Enable promiscuous mode. */ 8136 rx_mode |= BCE_EMAC_RX_MODE_PROMISCUOUS; 8137 sort_mode |= BCE_RPM_SORT_USER0_PROM_EN; 8138 } else if (ifp->if_flags & IFF_ALLMULTI) { 8139 DBPRINT(sc, BCE_INFO_MISC, "Enabling all multicast mode.\n"); 8140 8141 /* Enable all multicast addresses. */ 8142 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) { 8143 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), 8144 0xffffffff); 8145 } 8146 sort_mode |= BCE_RPM_SORT_USER0_MC_EN; 8147 } else { 8148 /* Accept one or more multicast(s). */ 8149 DBPRINT(sc, BCE_INFO_MISC, "Enabling selective multicast mode.\n"); 8150 8151 if_maddr_rlock(ifp); 8152 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 8153 if (ifma->ifma_addr->sa_family != AF_LINK) 8154 continue; 8155 h = ether_crc32_le(LLADDR((struct sockaddr_dl *) 8156 ifma->ifma_addr), ETHER_ADDR_LEN) & 0xFF; 8157 hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F); 8158 } 8159 if_maddr_runlock(ifp); 8160 8161 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) 8162 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), hashes[i]); 8163 8164 sort_mode |= BCE_RPM_SORT_USER0_MC_HSH_EN; 8165 } 8166 8167 /* Only make changes if the recive mode has actually changed. */ 8168 if (rx_mode != sc->rx_mode) { 8169 DBPRINT(sc, BCE_VERBOSE_MISC, "Enabling new receive mode: " 8170 "0x%08X\n", rx_mode); 8171 8172 sc->rx_mode = rx_mode; 8173 REG_WR(sc, BCE_EMAC_RX_MODE, rx_mode); 8174 } 8175 8176 /* Disable and clear the exisitng sort before enabling a new sort. */ 8177 REG_WR(sc, BCE_RPM_SORT_USER0, 0x0); 8178 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode); 8179 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode | BCE_RPM_SORT_USER0_ENA); 8180 8181 DBEXIT(BCE_VERBOSE_MISC); 8182} 8183 8184 8185/****************************************************************************/ 8186/* Called periodically to updates statistics from the controllers */ 8187/* statistics block. */ 8188/* */ 8189/* Returns: */ 8190/* Nothing. */ 8191/****************************************************************************/ 8192static void 8193bce_stats_update(struct bce_softc *sc) 8194{ 8195 struct ifnet *ifp; 8196 struct statistics_block *stats; 8197 8198 DBENTER(BCE_EXTREME_MISC); 8199 8200 ifp = sc->bce_ifp; 8201 8202 bus_dmamap_sync(sc->stats_tag, sc->stats_map, BUS_DMASYNC_POSTREAD); 8203 8204 stats = (struct statistics_block *) sc->stats_block; 8205 8206 /* 8207 * Certain controllers don't report 8208 * carrier sense errors correctly. 8209 * See errata E11_5708CA0_1165. 8210 */ 8211 if (!(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) && 8212 !(BCE_CHIP_ID(sc) == BCE_CHIP_ID_5708_A0)) 8213 ifp->if_oerrors += 8214 (u_long) stats->stat_Dot3StatsCarrierSenseErrors; 8215 8216 /* 8217 * Update the sysctl statistics from the 8218 * hardware statistics. 8219 */ 8220 sc->stat_IfHCInOctets = 8221 ((u64) stats->stat_IfHCInOctets_hi << 32) + 8222 (u64) stats->stat_IfHCInOctets_lo; 8223 8224 sc->stat_IfHCInBadOctets = 8225 ((u64) stats->stat_IfHCInBadOctets_hi << 32) + 8226 (u64) stats->stat_IfHCInBadOctets_lo; 8227 8228 sc->stat_IfHCOutOctets = 8229 ((u64) stats->stat_IfHCOutOctets_hi << 32) + 8230 (u64) stats->stat_IfHCOutOctets_lo; 8231 8232 sc->stat_IfHCOutBadOctets = 8233 ((u64) stats->stat_IfHCOutBadOctets_hi << 32) + 8234 (u64) stats->stat_IfHCOutBadOctets_lo; 8235 8236 sc->stat_IfHCInUcastPkts = 8237 ((u64) stats->stat_IfHCInUcastPkts_hi << 32) + 8238 (u64) stats->stat_IfHCInUcastPkts_lo; 8239 8240 sc->stat_IfHCInMulticastPkts = 8241 ((u64) stats->stat_IfHCInMulticastPkts_hi << 32) + 8242 (u64) stats->stat_IfHCInMulticastPkts_lo; 8243 8244 sc->stat_IfHCInBroadcastPkts = 8245 ((u64) stats->stat_IfHCInBroadcastPkts_hi << 32) + 8246 (u64) stats->stat_IfHCInBroadcastPkts_lo; 8247 8248 sc->stat_IfHCOutUcastPkts = 8249 ((u64) stats->stat_IfHCOutUcastPkts_hi << 32) + 8250 (u64) stats->stat_IfHCOutUcastPkts_lo; 8251 8252 sc->stat_IfHCOutMulticastPkts = 8253 ((u64) stats->stat_IfHCOutMulticastPkts_hi << 32) + 8254 (u64) stats->stat_IfHCOutMulticastPkts_lo; 8255 8256 sc->stat_IfHCOutBroadcastPkts = 8257 ((u64) stats->stat_IfHCOutBroadcastPkts_hi << 32) + 8258 (u64) stats->stat_IfHCOutBroadcastPkts_lo; 8259 8260 /* ToDo: Preserve counters beyond 32 bits? */ 8261 /* ToDo: Read the statistics from auto-clear regs? */ 8262 8263 sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors = 8264 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors; 8265 8266 sc->stat_Dot3StatsCarrierSenseErrors = 8267 stats->stat_Dot3StatsCarrierSenseErrors; 8268 8269 sc->stat_Dot3StatsFCSErrors = 8270 stats->stat_Dot3StatsFCSErrors; 8271 8272 sc->stat_Dot3StatsAlignmentErrors = 8273 stats->stat_Dot3StatsAlignmentErrors; 8274 8275 sc->stat_Dot3StatsSingleCollisionFrames = 8276 stats->stat_Dot3StatsSingleCollisionFrames; 8277 8278 sc->stat_Dot3StatsMultipleCollisionFrames = 8279 stats->stat_Dot3StatsMultipleCollisionFrames; 8280 8281 sc->stat_Dot3StatsDeferredTransmissions = 8282 stats->stat_Dot3StatsDeferredTransmissions; 8283 8284 sc->stat_Dot3StatsExcessiveCollisions = 8285 stats->stat_Dot3StatsExcessiveCollisions; 8286 8287 sc->stat_Dot3StatsLateCollisions = 8288 stats->stat_Dot3StatsLateCollisions; 8289 8290 sc->stat_EtherStatsCollisions = 8291 stats->stat_EtherStatsCollisions; 8292 8293 sc->stat_EtherStatsFragments = 8294 stats->stat_EtherStatsFragments; 8295 8296 sc->stat_EtherStatsJabbers = 8297 stats->stat_EtherStatsJabbers; 8298 8299 sc->stat_EtherStatsUndersizePkts = 8300 stats->stat_EtherStatsUndersizePkts; 8301 8302 sc->stat_EtherStatsOversizePkts = 8303 stats->stat_EtherStatsOversizePkts; 8304 8305 sc->stat_EtherStatsPktsRx64Octets = 8306 stats->stat_EtherStatsPktsRx64Octets; 8307 8308 sc->stat_EtherStatsPktsRx65Octetsto127Octets = 8309 stats->stat_EtherStatsPktsRx65Octetsto127Octets; 8310 8311 sc->stat_EtherStatsPktsRx128Octetsto255Octets = 8312 stats->stat_EtherStatsPktsRx128Octetsto255Octets; 8313 8314 sc->stat_EtherStatsPktsRx256Octetsto511Octets = 8315 stats->stat_EtherStatsPktsRx256Octetsto511Octets; 8316 8317 sc->stat_EtherStatsPktsRx512Octetsto1023Octets = 8318 stats->stat_EtherStatsPktsRx512Octetsto1023Octets; 8319 8320 sc->stat_EtherStatsPktsRx1024Octetsto1522Octets = 8321 stats->stat_EtherStatsPktsRx1024Octetsto1522Octets; 8322 8323 sc->stat_EtherStatsPktsRx1523Octetsto9022Octets = 8324 stats->stat_EtherStatsPktsRx1523Octetsto9022Octets; 8325 8326 sc->stat_EtherStatsPktsTx64Octets = 8327 stats->stat_EtherStatsPktsTx64Octets; 8328 8329 sc->stat_EtherStatsPktsTx65Octetsto127Octets = 8330 stats->stat_EtherStatsPktsTx65Octetsto127Octets; 8331 8332 sc->stat_EtherStatsPktsTx128Octetsto255Octets = 8333 stats->stat_EtherStatsPktsTx128Octetsto255Octets; 8334 8335 sc->stat_EtherStatsPktsTx256Octetsto511Octets = 8336 stats->stat_EtherStatsPktsTx256Octetsto511Octets; 8337 8338 sc->stat_EtherStatsPktsTx512Octetsto1023Octets = 8339 stats->stat_EtherStatsPktsTx512Octetsto1023Octets; 8340 8341 sc->stat_EtherStatsPktsTx1024Octetsto1522Octets = 8342 stats->stat_EtherStatsPktsTx1024Octetsto1522Octets; 8343 8344 sc->stat_EtherStatsPktsTx1523Octetsto9022Octets = 8345 stats->stat_EtherStatsPktsTx1523Octetsto9022Octets; 8346 8347 sc->stat_XonPauseFramesReceived = 8348 stats->stat_XonPauseFramesReceived; 8349 8350 sc->stat_XoffPauseFramesReceived = 8351 stats->stat_XoffPauseFramesReceived; 8352 8353 sc->stat_OutXonSent = 8354 stats->stat_OutXonSent; 8355 8356 sc->stat_OutXoffSent = 8357 stats->stat_OutXoffSent; 8358 8359 sc->stat_FlowControlDone = 8360 stats->stat_FlowControlDone; 8361 8362 sc->stat_MacControlFramesReceived = 8363 stats->stat_MacControlFramesReceived; 8364 8365 sc->stat_XoffStateEntered = 8366 stats->stat_XoffStateEntered; 8367 8368 sc->stat_IfInFramesL2FilterDiscards = 8369 stats->stat_IfInFramesL2FilterDiscards; 8370 8371 sc->stat_IfInRuleCheckerDiscards = 8372 stats->stat_IfInRuleCheckerDiscards; 8373 8374 sc->stat_IfInFTQDiscards = 8375 stats->stat_IfInFTQDiscards; 8376 8377 sc->stat_IfInMBUFDiscards = 8378 stats->stat_IfInMBUFDiscards; 8379 8380 sc->stat_IfInRuleCheckerP4Hit = 8381 stats->stat_IfInRuleCheckerP4Hit; 8382 8383 sc->stat_CatchupInRuleCheckerDiscards = 8384 stats->stat_CatchupInRuleCheckerDiscards; 8385 8386 sc->stat_CatchupInFTQDiscards = 8387 stats->stat_CatchupInFTQDiscards; 8388 8389 sc->stat_CatchupInMBUFDiscards = 8390 stats->stat_CatchupInMBUFDiscards; 8391 8392 sc->stat_CatchupInRuleCheckerP4Hit = 8393 stats->stat_CatchupInRuleCheckerP4Hit; 8394 8395 sc->com_no_buffers = REG_RD_IND(sc, 0x120084); 8396 8397 /* 8398 * Update the interface statistics from the 8399 * hardware statistics. 8400 */ 8401 ifp->if_collisions = 8402 (u_long) sc->stat_EtherStatsCollisions; 8403 8404 /* ToDo: This method loses soft errors. */ 8405 ifp->if_ierrors = 8406 (u_long) sc->stat_EtherStatsUndersizePkts + 8407 (u_long) sc->stat_EtherStatsOversizePkts + 8408 (u_long) sc->stat_IfInMBUFDiscards + 8409 (u_long) sc->stat_Dot3StatsAlignmentErrors + 8410 (u_long) sc->stat_Dot3StatsFCSErrors + 8411 (u_long) sc->stat_IfInRuleCheckerDiscards + 8412 (u_long) sc->stat_IfInFTQDiscards + 8413 (u_long) sc->com_no_buffers; 8414 8415 /* ToDo: This method loses soft errors. */ 8416 ifp->if_oerrors = 8417 (u_long) sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors + 8418 (u_long) sc->stat_Dot3StatsExcessiveCollisions + 8419 (u_long) sc->stat_Dot3StatsLateCollisions; 8420 8421 /* ToDo: Add additional statistics? */ 8422 8423 DBEXIT(BCE_EXTREME_MISC); 8424} 8425 8426 8427/****************************************************************************/ 8428/* Periodic function to notify the bootcode that the driver is still */ 8429/* present. */ 8430/* */ 8431/* Returns: */ 8432/* Nothing. */ 8433/****************************************************************************/ 8434static void 8435bce_pulse(void *xsc) 8436{ 8437 struct bce_softc *sc = xsc; 8438 u32 msg; 8439 8440 DBENTER(BCE_EXTREME_MISC); 8441 8442 BCE_LOCK_ASSERT(sc); 8443 8444 /* Tell the firmware that the driver is still running. */ 8445 msg = (u32) ++sc->bce_fw_drv_pulse_wr_seq; 8446 bce_shmem_wr(sc, BCE_DRV_PULSE_MB, msg); 8447 8448 /* Update the bootcode condition. */ 8449 sc->bc_state = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); 8450 8451 /* Report whether the bootcode still knows the driver is running. */ 8452 if (bce_verbose || bootverbose) { 8453 if (sc->bce_drv_cardiac_arrest == FALSE) { 8454 if (!(sc->bc_state & BCE_CONDITION_DRV_PRESENT)) { 8455 sc->bce_drv_cardiac_arrest = TRUE; 8456 BCE_PRINTF("%s(): Warning: bootcode " 8457 "thinks driver is absent! " 8458 "(bc_state = 0x%08X)\n", 8459 __FUNCTION__, sc->bc_state); 8460 } 8461 } else { 8462 /* 8463 * Not supported by all bootcode versions. 8464 * (v5.0.11+ and v5.2.1+) Older bootcode 8465 * will require the driver to reset the 8466 * controller to clear this condition. 8467 */ 8468 if (sc->bc_state & BCE_CONDITION_DRV_PRESENT) { 8469 sc->bce_drv_cardiac_arrest = FALSE; 8470 BCE_PRINTF("%s(): Bootcode found the " 8471 "driver pulse! (bc_state = 0x%08X)\n", 8472 __FUNCTION__, sc->bc_state); 8473 } 8474 } 8475 } 8476 8477 8478 /* Schedule the next pulse. */ 8479 callout_reset(&sc->bce_pulse_callout, hz, bce_pulse, sc); 8480 8481 DBEXIT(BCE_EXTREME_MISC); 8482} 8483 8484 8485/****************************************************************************/ 8486/* Periodic function to perform maintenance tasks. */ 8487/* */ 8488/* Returns: */ 8489/* Nothing. */ 8490/****************************************************************************/ 8491static void 8492bce_tick(void *xsc) 8493{ 8494 struct bce_softc *sc = xsc; 8495 struct mii_data *mii; 8496 struct ifnet *ifp; 8497 struct ifmediareq ifmr; 8498 8499 ifp = sc->bce_ifp; 8500 8501 DBENTER(BCE_EXTREME_MISC); 8502 8503 BCE_LOCK_ASSERT(sc); 8504 8505 /* Schedule the next tick. */ 8506 callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc); 8507 8508 /* Update the statistics from the hardware statistics block. */ 8509 bce_stats_update(sc); 8510 8511 /* Ensure page and RX chains get refilled in low-memory situations. */ 8512 if (bce_hdr_split == TRUE) 8513 bce_fill_pg_chain(sc); 8514 bce_fill_rx_chain(sc); 8515 8516 /* Check that chip hasn't hung. */ 8517 bce_watchdog(sc); 8518 8519 /* If link is up already up then we're done. */ 8520 if (sc->bce_link_up == TRUE) 8521 goto bce_tick_exit; 8522 8523 /* Link is down. Check what the PHY's doing. */ 8524 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) { 8525 bzero(&ifmr, sizeof(ifmr)); 8526 bce_ifmedia_sts_rphy(sc, &ifmr); 8527 if ((ifmr.ifm_status & (IFM_ACTIVE | IFM_AVALID)) == 8528 (IFM_ACTIVE | IFM_AVALID)) { 8529 sc->bce_link_up = TRUE; 8530 bce_miibus_statchg(sc->bce_dev); 8531 } 8532 } else { 8533 mii = device_get_softc(sc->bce_miibus); 8534 mii_tick(mii); 8535 /* Check if the link has come up. */ 8536 if ((mii->mii_media_status & IFM_ACTIVE) && 8537 (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)) { 8538 DBPRINT(sc, BCE_VERBOSE_MISC, "%s(): Link up!\n", 8539 __FUNCTION__); 8540 sc->bce_link_up = TRUE; 8541 if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 8542 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX || 8543 IFM_SUBTYPE(mii->mii_media_active) == IFM_2500_SX) && 8544 (bce_verbose || bootverbose)) 8545 BCE_PRINTF("Gigabit link up!\n"); 8546 } 8547 8548 } 8549 if (sc->bce_link_up == TRUE) { 8550 /* Now that link is up, handle any outstanding TX traffic. */ 8551 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 8552 DBPRINT(sc, BCE_VERBOSE_MISC, "%s(): Found " 8553 "pending TX traffic.\n", __FUNCTION__); 8554 bce_start_locked(ifp); 8555 } 8556 } 8557 8558bce_tick_exit: 8559 DBEXIT(BCE_EXTREME_MISC); 8560} 8561 8562static void 8563bce_fw_cap_init(struct bce_softc *sc) 8564{ 8565 u32 ack, cap, link; 8566 8567 ack = 0; 8568 cap = bce_shmem_rd(sc, BCE_FW_CAP_MB); 8569 if ((cap & BCE_FW_CAP_SIGNATURE_MAGIC_MASK) != 8570 BCE_FW_CAP_SIGNATURE_MAGIC) 8571 return; 8572 if ((cap & (BCE_FW_CAP_MFW_KEEP_VLAN | BCE_FW_CAP_BC_KEEP_VLAN)) == 8573 (BCE_FW_CAP_MFW_KEEP_VLAN | BCE_FW_CAP_BC_KEEP_VLAN)) 8574 ack |= BCE_DRV_ACK_CAP_SIGNATURE_MAGIC | 8575 BCE_FW_CAP_MFW_KEEP_VLAN | BCE_FW_CAP_BC_KEEP_VLAN; 8576 if ((sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) != 0 && 8577 (cap & BCE_FW_CAP_REMOTE_PHY_CAP) != 0) { 8578 sc->bce_phy_flags &= ~BCE_PHY_REMOTE_PORT_FIBER_FLAG; 8579 sc->bce_phy_flags |= BCE_PHY_REMOTE_CAP_FLAG; 8580 link = bce_shmem_rd(sc, BCE_LINK_STATUS); 8581 if ((link & BCE_LINK_STATUS_SERDES_LINK) != 0) 8582 sc->bce_phy_flags |= BCE_PHY_REMOTE_PORT_FIBER_FLAG; 8583 ack |= BCE_DRV_ACK_CAP_SIGNATURE_MAGIC | 8584 BCE_FW_CAP_REMOTE_PHY_CAP; 8585 } 8586 8587 if (ack != 0) 8588 bce_shmem_wr(sc, BCE_DRV_ACK_CAP_MB, ack); 8589} 8590 8591 8592#ifdef BCE_DEBUG 8593/****************************************************************************/ 8594/* Allows the driver state to be dumped through the sysctl interface. */ 8595/* */ 8596/* Returns: */ 8597/* 0 for success, positive value for failure. */ 8598/****************************************************************************/ 8599static int 8600bce_sysctl_driver_state(SYSCTL_HANDLER_ARGS) 8601{ 8602 int error; 8603 int result; 8604 struct bce_softc *sc; 8605 8606 result = -1; 8607 error = sysctl_handle_int(oidp, &result, 0, req); 8608 8609 if (error || !req->newptr) 8610 return (error); 8611 8612 if (result == 1) { 8613 sc = (struct bce_softc *)arg1; 8614 bce_dump_driver_state(sc); 8615 } 8616 8617 return error; 8618} 8619 8620 8621/****************************************************************************/ 8622/* Allows the hardware state to be dumped through the sysctl interface. */ 8623/* */ 8624/* Returns: */ 8625/* 0 for success, positive value for failure. */ 8626/****************************************************************************/ 8627static int 8628bce_sysctl_hw_state(SYSCTL_HANDLER_ARGS) 8629{ 8630 int error; 8631 int result; 8632 struct bce_softc *sc; 8633 8634 result = -1; 8635 error = sysctl_handle_int(oidp, &result, 0, req); 8636 8637 if (error || !req->newptr) 8638 return (error); 8639 8640 if (result == 1) { 8641 sc = (struct bce_softc *)arg1; 8642 bce_dump_hw_state(sc); 8643 } 8644 8645 return error; 8646} 8647 8648 8649/****************************************************************************/ 8650/* Allows the status block to be dumped through the sysctl interface. */ 8651/* */ 8652/* Returns: */ 8653/* 0 for success, positive value for failure. */ 8654/****************************************************************************/ 8655static int 8656bce_sysctl_status_block(SYSCTL_HANDLER_ARGS) 8657{ 8658 int error; 8659 int result; 8660 struct bce_softc *sc; 8661 8662 result = -1; 8663 error = sysctl_handle_int(oidp, &result, 0, req); 8664 8665 if (error || !req->newptr) 8666 return (error); 8667 8668 if (result == 1) { 8669 sc = (struct bce_softc *)arg1; 8670 bce_dump_status_block(sc); 8671 } 8672 8673 return error; 8674} 8675 8676 8677/****************************************************************************/ 8678/* Allows the stats block to be dumped through the sysctl interface. */ 8679/* */ 8680/* Returns: */ 8681/* 0 for success, positive value for failure. */ 8682/****************************************************************************/ 8683static int 8684bce_sysctl_stats_block(SYSCTL_HANDLER_ARGS) 8685{ 8686 int error; 8687 int result; 8688 struct bce_softc *sc; 8689 8690 result = -1; 8691 error = sysctl_handle_int(oidp, &result, 0, req); 8692 8693 if (error || !req->newptr) 8694 return (error); 8695 8696 if (result == 1) { 8697 sc = (struct bce_softc *)arg1; 8698 bce_dump_stats_block(sc); 8699 } 8700 8701 return error; 8702} 8703 8704 8705/****************************************************************************/ 8706/* Allows the stat counters to be cleared without unloading/reloading the */ 8707/* driver. */ 8708/* */ 8709/* Returns: */ 8710/* 0 for success, positive value for failure. */ 8711/****************************************************************************/ 8712static int 8713bce_sysctl_stats_clear(SYSCTL_HANDLER_ARGS) 8714{ 8715 int error; 8716 int result; 8717 struct bce_softc *sc; 8718 8719 result = -1; 8720 error = sysctl_handle_int(oidp, &result, 0, req); 8721 8722 if (error || !req->newptr) 8723 return (error); 8724 8725 if (result == 1) { 8726 sc = (struct bce_softc *)arg1; 8727 struct statistics_block *stats; 8728 8729 stats = (struct statistics_block *) sc->stats_block; 8730 bzero(stats, sizeof(struct statistics_block)); 8731 bus_dmamap_sync(sc->stats_tag, sc->stats_map, 8732 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 8733 8734 /* Clear the internal H/W statistics counters. */ 8735 REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW); 8736 8737 /* Reset the driver maintained statistics. */ 8738 sc->interrupts_rx = 8739 sc->interrupts_tx = 0; 8740 sc->tso_frames_requested = 8741 sc->tso_frames_completed = 8742 sc->tso_frames_failed = 0; 8743 sc->rx_empty_count = 8744 sc->tx_full_count = 0; 8745 sc->rx_low_watermark = USABLE_RX_BD_ALLOC; 8746 sc->tx_hi_watermark = 0; 8747 sc->l2fhdr_error_count = 8748 sc->l2fhdr_error_sim_count = 0; 8749 sc->mbuf_alloc_failed_count = 8750 sc->mbuf_alloc_failed_sim_count = 0; 8751 sc->dma_map_addr_rx_failed_count = 8752 sc->dma_map_addr_tx_failed_count = 0; 8753 sc->mbuf_frag_count = 0; 8754 sc->csum_offload_tcp_udp = 8755 sc->csum_offload_ip = 0; 8756 sc->vlan_tagged_frames_rcvd = 8757 sc->vlan_tagged_frames_stripped = 0; 8758 sc->split_header_frames_rcvd = 8759 sc->split_header_tcp_frames_rcvd = 0; 8760 8761 /* Clear firmware maintained statistics. */ 8762 REG_WR_IND(sc, 0x120084, 0); 8763 } 8764 8765 return error; 8766} 8767 8768 8769/****************************************************************************/ 8770/* Allows the shared memory contents to be dumped through the sysctl . */ 8771/* interface. */ 8772/* */ 8773/* Returns: */ 8774/* 0 for success, positive value for failure. */ 8775/****************************************************************************/ 8776static int 8777bce_sysctl_shmem_state(SYSCTL_HANDLER_ARGS) 8778{ 8779 int error; 8780 int result; 8781 struct bce_softc *sc; 8782 8783 result = -1; 8784 error = sysctl_handle_int(oidp, &result, 0, req); 8785 8786 if (error || !req->newptr) 8787 return (error); 8788 8789 if (result == 1) { 8790 sc = (struct bce_softc *)arg1; 8791 bce_dump_shmem_state(sc); 8792 } 8793 8794 return error; 8795} 8796 8797 8798/****************************************************************************/ 8799/* Allows the bootcode state to be dumped through the sysctl interface. */ 8800/* */ 8801/* Returns: */ 8802/* 0 for success, positive value for failure. */ 8803/****************************************************************************/ 8804static int 8805bce_sysctl_bc_state(SYSCTL_HANDLER_ARGS) 8806{ 8807 int error; 8808 int result; 8809 struct bce_softc *sc; 8810 8811 result = -1; 8812 error = sysctl_handle_int(oidp, &result, 0, req); 8813 8814 if (error || !req->newptr) 8815 return (error); 8816 8817 if (result == 1) { 8818 sc = (struct bce_softc *)arg1; 8819 bce_dump_bc_state(sc); 8820 } 8821 8822 return error; 8823} 8824 8825 8826/****************************************************************************/ 8827/* Provides a sysctl interface to allow dumping the RX BD chain. */ 8828/* */ 8829/* Returns: */ 8830/* 0 for success, positive value for failure. */ 8831/****************************************************************************/ 8832static int 8833bce_sysctl_dump_rx_bd_chain(SYSCTL_HANDLER_ARGS) 8834{ 8835 int error; 8836 int result; 8837 struct bce_softc *sc; 8838 8839 result = -1; 8840 error = sysctl_handle_int(oidp, &result, 0, req); 8841 8842 if (error || !req->newptr) 8843 return (error); 8844 8845 if (result == 1) { 8846 sc = (struct bce_softc *)arg1; 8847 bce_dump_rx_bd_chain(sc, 0, TOTAL_RX_BD_ALLOC); 8848 } 8849 8850 return error; 8851} 8852 8853 8854/****************************************************************************/ 8855/* Provides a sysctl interface to allow dumping the RX MBUF chain. */ 8856/* */ 8857/* Returns: */ 8858/* 0 for success, positive value for failure. */ 8859/****************************************************************************/ 8860static int 8861bce_sysctl_dump_rx_mbuf_chain(SYSCTL_HANDLER_ARGS) 8862{ 8863 int error; 8864 int result; 8865 struct bce_softc *sc; 8866 8867 result = -1; 8868 error = sysctl_handle_int(oidp, &result, 0, req); 8869 8870 if (error || !req->newptr) 8871 return (error); 8872 8873 if (result == 1) { 8874 sc = (struct bce_softc *)arg1; 8875 bce_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD_ALLOC); 8876 } 8877 8878 return error; 8879} 8880 8881 8882/****************************************************************************/ 8883/* Provides a sysctl interface to allow dumping the TX chain. */ 8884/* */ 8885/* Returns: */ 8886/* 0 for success, positive value for failure. */ 8887/****************************************************************************/ 8888static int 8889bce_sysctl_dump_tx_chain(SYSCTL_HANDLER_ARGS) 8890{ 8891 int error; 8892 int result; 8893 struct bce_softc *sc; 8894 8895 result = -1; 8896 error = sysctl_handle_int(oidp, &result, 0, req); 8897 8898 if (error || !req->newptr) 8899 return (error); 8900 8901 if (result == 1) { 8902 sc = (struct bce_softc *)arg1; 8903 bce_dump_tx_chain(sc, 0, TOTAL_TX_BD_ALLOC); 8904 } 8905 8906 return error; 8907} 8908 8909 8910/****************************************************************************/ 8911/* Provides a sysctl interface to allow dumping the page chain. */ 8912/* */ 8913/* Returns: */ 8914/* 0 for success, positive value for failure. */ 8915/****************************************************************************/ 8916static int 8917bce_sysctl_dump_pg_chain(SYSCTL_HANDLER_ARGS) 8918{ 8919 int error; 8920 int result; 8921 struct bce_softc *sc; 8922 8923 result = -1; 8924 error = sysctl_handle_int(oidp, &result, 0, req); 8925 8926 if (error || !req->newptr) 8927 return (error); 8928 8929 if (result == 1) { 8930 sc = (struct bce_softc *)arg1; 8931 bce_dump_pg_chain(sc, 0, TOTAL_PG_BD_ALLOC); 8932 } 8933 8934 return error; 8935} 8936 8937/****************************************************************************/ 8938/* Provides a sysctl interface to allow reading arbitrary NVRAM offsets in */ 8939/* the device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8940/* */ 8941/* Returns: */ 8942/* 0 for success, positive value for failure. */ 8943/****************************************************************************/ 8944static int 8945bce_sysctl_nvram_read(SYSCTL_HANDLER_ARGS) 8946{ 8947 struct bce_softc *sc = (struct bce_softc *)arg1; 8948 int error; 8949 u32 result; 8950 u32 val[1]; 8951 u8 *data = (u8 *) val; 8952 8953 result = -1; 8954 error = sysctl_handle_int(oidp, &result, 0, req); 8955 if (error || (req->newptr == NULL)) 8956 return (error); 8957 8958 error = bce_nvram_read(sc, result, data, 4); 8959 8960 BCE_PRINTF("offset 0x%08X = 0x%08X\n", result, bce_be32toh(val[0])); 8961 8962 return (error); 8963} 8964 8965 8966/****************************************************************************/ 8967/* Provides a sysctl interface to allow reading arbitrary registers in the */ 8968/* device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8969/* */ 8970/* Returns: */ 8971/* 0 for success, positive value for failure. */ 8972/****************************************************************************/ 8973static int 8974bce_sysctl_reg_read(SYSCTL_HANDLER_ARGS) 8975{ 8976 struct bce_softc *sc = (struct bce_softc *)arg1; 8977 int error; 8978 u32 val, result; 8979 8980 result = -1; 8981 error = sysctl_handle_int(oidp, &result, 0, req); 8982 if (error || (req->newptr == NULL)) 8983 return (error); 8984 8985 /* Make sure the register is accessible. */ 8986 if (result < 0x8000) { 8987 val = REG_RD(sc, result); 8988 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val); 8989 } else if (result < 0x0280000) { 8990 val = REG_RD_IND(sc, result); 8991 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val); 8992 } 8993 8994 return (error); 8995} 8996 8997 8998/****************************************************************************/ 8999/* Provides a sysctl interface to allow reading arbitrary PHY registers in */ 9000/* the device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 9001/* */ 9002/* Returns: */ 9003/* 0 for success, positive value for failure. */ 9004/****************************************************************************/ 9005static int 9006bce_sysctl_phy_read(SYSCTL_HANDLER_ARGS) 9007{ 9008 struct bce_softc *sc; 9009 device_t dev; 9010 int error, result; 9011 u16 val; 9012 9013 result = -1; 9014 error = sysctl_handle_int(oidp, &result, 0, req); 9015 if (error || (req->newptr == NULL)) 9016 return (error); 9017 9018 /* Make sure the register is accessible. */ 9019 if (result < 0x20) { 9020 sc = (struct bce_softc *)arg1; 9021 dev = sc->bce_dev; 9022 val = bce_miibus_read_reg(dev, sc->bce_phy_addr, result); 9023 BCE_PRINTF("phy 0x%02X = 0x%04X\n", result, val); 9024 } 9025 return (error); 9026} 9027 9028 9029/****************************************************************************/ 9030/* Provides a sysctl interface for dumping the nvram contents. */ 9031/* DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 9032/* */ 9033/* Returns: */ 9034/* 0 for success, positive errno for failure. */ 9035/****************************************************************************/ 9036static int 9037bce_sysctl_nvram_dump(SYSCTL_HANDLER_ARGS) 9038{ 9039 struct bce_softc *sc = (struct bce_softc *)arg1; 9040 int error, i; 9041 9042 if (sc->nvram_buf == NULL) 9043 sc->nvram_buf = malloc(sc->bce_flash_size, 9044 M_TEMP, M_ZERO | M_WAITOK); 9045 9046 error = 0; 9047 if (req->oldlen == sc->bce_flash_size) { 9048 for (i = 0; i < sc->bce_flash_size && error == 0; i++) 9049 error = bce_nvram_read(sc, i, &sc->nvram_buf[i], 1); 9050 } 9051 9052 if (error == 0) 9053 error = SYSCTL_OUT(req, sc->nvram_buf, sc->bce_flash_size); 9054 9055 return error; 9056} 9057 9058#ifdef BCE_NVRAM_WRITE_SUPPORT 9059/****************************************************************************/ 9060/* Provides a sysctl interface for writing to nvram. */ 9061/* DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 9062/* */ 9063/* Returns: */ 9064/* 0 for success, positive errno for failure. */ 9065/****************************************************************************/ 9066static int 9067bce_sysctl_nvram_write(SYSCTL_HANDLER_ARGS) 9068{ 9069 struct bce_softc *sc = (struct bce_softc *)arg1; 9070 int error; 9071 9072 if (sc->nvram_buf == NULL) 9073 sc->nvram_buf = malloc(sc->bce_flash_size, 9074 M_TEMP, M_ZERO | M_WAITOK); 9075 else 9076 bzero(sc->nvram_buf, sc->bce_flash_size); 9077 9078 error = SYSCTL_IN(req, sc->nvram_buf, sc->bce_flash_size); 9079 if (error == 0) 9080 return (error); 9081 9082 if (req->newlen == sc->bce_flash_size) 9083 error = bce_nvram_write(sc, 0, sc->nvram_buf, 9084 sc->bce_flash_size); 9085 9086 9087 return error; 9088} 9089#endif 9090 9091 9092/****************************************************************************/ 9093/* Provides a sysctl interface to allow reading a CID. */ 9094/* */ 9095/* Returns: */ 9096/* 0 for success, positive value for failure. */ 9097/****************************************************************************/ 9098static int 9099bce_sysctl_dump_ctx(SYSCTL_HANDLER_ARGS) 9100{ 9101 struct bce_softc *sc; 9102 int error, result; 9103 9104 result = -1; 9105 error = sysctl_handle_int(oidp, &result, 0, req); 9106 if (error || (req->newptr == NULL)) 9107 return (error); 9108 9109 /* Make sure the register is accessible. */ 9110 if (result <= TX_CID) { 9111 sc = (struct bce_softc *)arg1; 9112 bce_dump_ctx(sc, result); 9113 } 9114 9115 return (error); 9116} 9117 9118 9119/****************************************************************************/ 9120/* Provides a sysctl interface to forcing the driver to dump state and */ 9121/* enter the debugger. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 9122/* */ 9123/* Returns: */ 9124/* 0 for success, positive value for failure. */ 9125/****************************************************************************/ 9126static int 9127bce_sysctl_breakpoint(SYSCTL_HANDLER_ARGS) 9128{ 9129 int error; 9130 int result; 9131 struct bce_softc *sc; 9132 9133 result = -1; 9134 error = sysctl_handle_int(oidp, &result, 0, req); 9135 9136 if (error || !req->newptr) 9137 return (error); 9138 9139 if (result == 1) { 9140 sc = (struct bce_softc *)arg1; 9141 bce_breakpoint(sc); 9142 } 9143 9144 return error; 9145} 9146#endif 9147 9148/****************************************************************************/ 9149/* Adds any sysctl parameters for tuning or debugging purposes. */ 9150/* */ 9151/* Returns: */ 9152/* 0 for success, positive value for failure. */ 9153/****************************************************************************/ 9154static void 9155bce_add_sysctls(struct bce_softc *sc) 9156{ 9157 struct sysctl_ctx_list *ctx; 9158 struct sysctl_oid_list *children; 9159 9160 DBENTER(BCE_VERBOSE_MISC); 9161 9162 ctx = device_get_sysctl_ctx(sc->bce_dev); 9163 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bce_dev)); 9164 9165#ifdef BCE_DEBUG 9166 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 9167 "l2fhdr_error_sim_control", 9168 CTLFLAG_RW, &l2fhdr_error_sim_control, 9169 0, "Debug control to force l2fhdr errors"); 9170 9171 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 9172 "l2fhdr_error_sim_count", 9173 CTLFLAG_RD, &sc->l2fhdr_error_sim_count, 9174 0, "Number of simulated l2_fhdr errors"); 9175#endif 9176 9177 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9178 "l2fhdr_error_count", 9179 CTLFLAG_RD, &sc->l2fhdr_error_count, 9180 0, "Number of l2_fhdr errors"); 9181 9182#ifdef BCE_DEBUG 9183 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 9184 "mbuf_alloc_failed_sim_control", 9185 CTLFLAG_RW, &mbuf_alloc_failed_sim_control, 9186 0, "Debug control to force mbuf allocation failures"); 9187 9188 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9189 "mbuf_alloc_failed_sim_count", 9190 CTLFLAG_RD, &sc->mbuf_alloc_failed_sim_count, 9191 0, "Number of simulated mbuf cluster allocation failures"); 9192#endif 9193 9194 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9195 "mbuf_alloc_failed_count", 9196 CTLFLAG_RD, &sc->mbuf_alloc_failed_count, 9197 0, "Number of mbuf allocation failures"); 9198 9199 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9200 "mbuf_frag_count", 9201 CTLFLAG_RD, &sc->mbuf_frag_count, 9202 0, "Number of fragmented mbufs"); 9203 9204#ifdef BCE_DEBUG 9205 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 9206 "dma_map_addr_failed_sim_control", 9207 CTLFLAG_RW, &dma_map_addr_failed_sim_control, 9208 0, "Debug control to force DMA mapping failures"); 9209 9210 /* ToDo: Figure out how to update this value in bce_dma_map_addr(). */ 9211 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9212 "dma_map_addr_failed_sim_count", 9213 CTLFLAG_RD, &sc->dma_map_addr_failed_sim_count, 9214 0, "Number of simulated DMA mapping failures"); 9215 9216#endif 9217 9218 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9219 "dma_map_addr_rx_failed_count", 9220 CTLFLAG_RD, &sc->dma_map_addr_rx_failed_count, 9221 0, "Number of RX DMA mapping failures"); 9222 9223 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9224 "dma_map_addr_tx_failed_count", 9225 CTLFLAG_RD, &sc->dma_map_addr_tx_failed_count, 9226 0, "Number of TX DMA mapping failures"); 9227 9228#ifdef BCE_DEBUG 9229 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 9230 "unexpected_attention_sim_control", 9231 CTLFLAG_RW, &unexpected_attention_sim_control, 9232 0, "Debug control to simulate unexpected attentions"); 9233 9234 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9235 "unexpected_attention_sim_count", 9236 CTLFLAG_RW, &sc->unexpected_attention_sim_count, 9237 0, "Number of simulated unexpected attentions"); 9238#endif 9239 9240 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9241 "unexpected_attention_count", 9242 CTLFLAG_RW, &sc->unexpected_attention_count, 9243 0, "Number of unexpected attentions"); 9244 9245#ifdef BCE_DEBUG 9246 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 9247 "debug_bootcode_running_failure", 9248 CTLFLAG_RW, &bootcode_running_failure_sim_control, 9249 0, "Debug control to force bootcode running failures"); 9250 9251 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 9252 "rx_low_watermark", 9253 CTLFLAG_RD, &sc->rx_low_watermark, 9254 0, "Lowest level of free rx_bd's"); 9255 9256 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9257 "rx_empty_count", 9258 CTLFLAG_RD, &sc->rx_empty_count, 9259 "Number of times the RX chain was empty"); 9260 9261 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 9262 "tx_hi_watermark", 9263 CTLFLAG_RD, &sc->tx_hi_watermark, 9264 0, "Highest level of used tx_bd's"); 9265 9266 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9267 "tx_full_count", 9268 CTLFLAG_RD, &sc->tx_full_count, 9269 "Number of times the TX chain was full"); 9270 9271 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9272 "tso_frames_requested", 9273 CTLFLAG_RD, &sc->tso_frames_requested, 9274 "Number of TSO frames requested"); 9275 9276 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9277 "tso_frames_completed", 9278 CTLFLAG_RD, &sc->tso_frames_completed, 9279 "Number of TSO frames completed"); 9280 9281 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9282 "tso_frames_failed", 9283 CTLFLAG_RD, &sc->tso_frames_failed, 9284 "Number of TSO frames failed"); 9285 9286 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9287 "csum_offload_ip", 9288 CTLFLAG_RD, &sc->csum_offload_ip, 9289 "Number of IP checksum offload frames"); 9290 9291 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9292 "csum_offload_tcp_udp", 9293 CTLFLAG_RD, &sc->csum_offload_tcp_udp, 9294 "Number of TCP/UDP checksum offload frames"); 9295 9296 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9297 "vlan_tagged_frames_rcvd", 9298 CTLFLAG_RD, &sc->vlan_tagged_frames_rcvd, 9299 "Number of VLAN tagged frames received"); 9300 9301 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9302 "vlan_tagged_frames_stripped", 9303 CTLFLAG_RD, &sc->vlan_tagged_frames_stripped, 9304 "Number of VLAN tagged frames stripped"); 9305 9306 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9307 "interrupts_rx", 9308 CTLFLAG_RD, &sc->interrupts_rx, 9309 "Number of RX interrupts"); 9310 9311 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9312 "interrupts_tx", 9313 CTLFLAG_RD, &sc->interrupts_tx, 9314 "Number of TX interrupts"); 9315 9316 if (bce_hdr_split == TRUE) { 9317 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9318 "split_header_frames_rcvd", 9319 CTLFLAG_RD, &sc->split_header_frames_rcvd, 9320 "Number of split header frames received"); 9321 9322 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9323 "split_header_tcp_frames_rcvd", 9324 CTLFLAG_RD, &sc->split_header_tcp_frames_rcvd, 9325 "Number of split header TCP frames received"); 9326 } 9327 9328 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9329 "nvram_dump", CTLTYPE_OPAQUE | CTLFLAG_RD, 9330 (void *)sc, 0, 9331 bce_sysctl_nvram_dump, "S", ""); 9332 9333#ifdef BCE_NVRAM_WRITE_SUPPORT 9334 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9335 "nvram_write", CTLTYPE_OPAQUE | CTLFLAG_WR, 9336 (void *)sc, 0, 9337 bce_sysctl_nvram_write, "S", ""); 9338#endif 9339#endif /* BCE_DEBUG */ 9340 9341 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9342 "stat_IfHcInOctets", 9343 CTLFLAG_RD, &sc->stat_IfHCInOctets, 9344 "Bytes received"); 9345 9346 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9347 "stat_IfHCInBadOctets", 9348 CTLFLAG_RD, &sc->stat_IfHCInBadOctets, 9349 "Bad bytes received"); 9350 9351 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9352 "stat_IfHCOutOctets", 9353 CTLFLAG_RD, &sc->stat_IfHCOutOctets, 9354 "Bytes sent"); 9355 9356 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9357 "stat_IfHCOutBadOctets", 9358 CTLFLAG_RD, &sc->stat_IfHCOutBadOctets, 9359 "Bad bytes sent"); 9360 9361 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9362 "stat_IfHCInUcastPkts", 9363 CTLFLAG_RD, &sc->stat_IfHCInUcastPkts, 9364 "Unicast packets received"); 9365 9366 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9367 "stat_IfHCInMulticastPkts", 9368 CTLFLAG_RD, &sc->stat_IfHCInMulticastPkts, 9369 "Multicast packets received"); 9370 9371 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9372 "stat_IfHCInBroadcastPkts", 9373 CTLFLAG_RD, &sc->stat_IfHCInBroadcastPkts, 9374 "Broadcast packets received"); 9375 9376 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9377 "stat_IfHCOutUcastPkts", 9378 CTLFLAG_RD, &sc->stat_IfHCOutUcastPkts, 9379 "Unicast packets sent"); 9380 9381 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9382 "stat_IfHCOutMulticastPkts", 9383 CTLFLAG_RD, &sc->stat_IfHCOutMulticastPkts, 9384 "Multicast packets sent"); 9385 9386 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9387 "stat_IfHCOutBroadcastPkts", 9388 CTLFLAG_RD, &sc->stat_IfHCOutBroadcastPkts, 9389 "Broadcast packets sent"); 9390 9391 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9392 "stat_emac_tx_stat_dot3statsinternalmactransmiterrors", 9393 CTLFLAG_RD, &sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors, 9394 0, "Internal MAC transmit errors"); 9395 9396 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9397 "stat_Dot3StatsCarrierSenseErrors", 9398 CTLFLAG_RD, &sc->stat_Dot3StatsCarrierSenseErrors, 9399 0, "Carrier sense errors"); 9400 9401 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9402 "stat_Dot3StatsFCSErrors", 9403 CTLFLAG_RD, &sc->stat_Dot3StatsFCSErrors, 9404 0, "Frame check sequence errors"); 9405 9406 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9407 "stat_Dot3StatsAlignmentErrors", 9408 CTLFLAG_RD, &sc->stat_Dot3StatsAlignmentErrors, 9409 0, "Alignment errors"); 9410 9411 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9412 "stat_Dot3StatsSingleCollisionFrames", 9413 CTLFLAG_RD, &sc->stat_Dot3StatsSingleCollisionFrames, 9414 0, "Single Collision Frames"); 9415 9416 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9417 "stat_Dot3StatsMultipleCollisionFrames", 9418 CTLFLAG_RD, &sc->stat_Dot3StatsMultipleCollisionFrames, 9419 0, "Multiple Collision Frames"); 9420 9421 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9422 "stat_Dot3StatsDeferredTransmissions", 9423 CTLFLAG_RD, &sc->stat_Dot3StatsDeferredTransmissions, 9424 0, "Deferred Transmissions"); 9425 9426 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9427 "stat_Dot3StatsExcessiveCollisions", 9428 CTLFLAG_RD, &sc->stat_Dot3StatsExcessiveCollisions, 9429 0, "Excessive Collisions"); 9430 9431 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9432 "stat_Dot3StatsLateCollisions", 9433 CTLFLAG_RD, &sc->stat_Dot3StatsLateCollisions, 9434 0, "Late Collisions"); 9435 9436 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9437 "stat_EtherStatsCollisions", 9438 CTLFLAG_RD, &sc->stat_EtherStatsCollisions, 9439 0, "Collisions"); 9440 9441 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9442 "stat_EtherStatsFragments", 9443 CTLFLAG_RD, &sc->stat_EtherStatsFragments, 9444 0, "Fragments"); 9445 9446 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9447 "stat_EtherStatsJabbers", 9448 CTLFLAG_RD, &sc->stat_EtherStatsJabbers, 9449 0, "Jabbers"); 9450 9451 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9452 "stat_EtherStatsUndersizePkts", 9453 CTLFLAG_RD, &sc->stat_EtherStatsUndersizePkts, 9454 0, "Undersize packets"); 9455 9456 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9457 "stat_EtherStatsOversizePkts", 9458 CTLFLAG_RD, &sc->stat_EtherStatsOversizePkts, 9459 0, "stat_EtherStatsOversizePkts"); 9460 9461 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9462 "stat_EtherStatsPktsRx64Octets", 9463 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx64Octets, 9464 0, "Bytes received in 64 byte packets"); 9465 9466 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9467 "stat_EtherStatsPktsRx65Octetsto127Octets", 9468 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx65Octetsto127Octets, 9469 0, "Bytes received in 65 to 127 byte packets"); 9470 9471 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9472 "stat_EtherStatsPktsRx128Octetsto255Octets", 9473 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx128Octetsto255Octets, 9474 0, "Bytes received in 128 to 255 byte packets"); 9475 9476 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9477 "stat_EtherStatsPktsRx256Octetsto511Octets", 9478 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx256Octetsto511Octets, 9479 0, "Bytes received in 256 to 511 byte packets"); 9480 9481 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9482 "stat_EtherStatsPktsRx512Octetsto1023Octets", 9483 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx512Octetsto1023Octets, 9484 0, "Bytes received in 512 to 1023 byte packets"); 9485 9486 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9487 "stat_EtherStatsPktsRx1024Octetsto1522Octets", 9488 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1024Octetsto1522Octets, 9489 0, "Bytes received in 1024 t0 1522 byte packets"); 9490 9491 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9492 "stat_EtherStatsPktsRx1523Octetsto9022Octets", 9493 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1523Octetsto9022Octets, 9494 0, "Bytes received in 1523 to 9022 byte packets"); 9495 9496 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9497 "stat_EtherStatsPktsTx64Octets", 9498 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx64Octets, 9499 0, "Bytes sent in 64 byte packets"); 9500 9501 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9502 "stat_EtherStatsPktsTx65Octetsto127Octets", 9503 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx65Octetsto127Octets, 9504 0, "Bytes sent in 65 to 127 byte packets"); 9505 9506 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9507 "stat_EtherStatsPktsTx128Octetsto255Octets", 9508 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx128Octetsto255Octets, 9509 0, "Bytes sent in 128 to 255 byte packets"); 9510 9511 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9512 "stat_EtherStatsPktsTx256Octetsto511Octets", 9513 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx256Octetsto511Octets, 9514 0, "Bytes sent in 256 to 511 byte packets"); 9515 9516 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9517 "stat_EtherStatsPktsTx512Octetsto1023Octets", 9518 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx512Octetsto1023Octets, 9519 0, "Bytes sent in 512 to 1023 byte packets"); 9520 9521 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9522 "stat_EtherStatsPktsTx1024Octetsto1522Octets", 9523 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1024Octetsto1522Octets, 9524 0, "Bytes sent in 1024 to 1522 byte packets"); 9525 9526 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9527 "stat_EtherStatsPktsTx1523Octetsto9022Octets", 9528 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1523Octetsto9022Octets, 9529 0, "Bytes sent in 1523 to 9022 byte packets"); 9530 9531 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9532 "stat_XonPauseFramesReceived", 9533 CTLFLAG_RD, &sc->stat_XonPauseFramesReceived, 9534 0, "XON pause frames receved"); 9535 9536 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9537 "stat_XoffPauseFramesReceived", 9538 CTLFLAG_RD, &sc->stat_XoffPauseFramesReceived, 9539 0, "XOFF pause frames received"); 9540 9541 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9542 "stat_OutXonSent", 9543 CTLFLAG_RD, &sc->stat_OutXonSent, 9544 0, "XON pause frames sent"); 9545 9546 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9547 "stat_OutXoffSent", 9548 CTLFLAG_RD, &sc->stat_OutXoffSent, 9549 0, "XOFF pause frames sent"); 9550 9551 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9552 "stat_FlowControlDone", 9553 CTLFLAG_RD, &sc->stat_FlowControlDone, 9554 0, "Flow control done"); 9555 9556 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9557 "stat_MacControlFramesReceived", 9558 CTLFLAG_RD, &sc->stat_MacControlFramesReceived, 9559 0, "MAC control frames received"); 9560 9561 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9562 "stat_XoffStateEntered", 9563 CTLFLAG_RD, &sc->stat_XoffStateEntered, 9564 0, "XOFF state entered"); 9565 9566 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9567 "stat_IfInFramesL2FilterDiscards", 9568 CTLFLAG_RD, &sc->stat_IfInFramesL2FilterDiscards, 9569 0, "Received L2 packets discarded"); 9570 9571 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9572 "stat_IfInRuleCheckerDiscards", 9573 CTLFLAG_RD, &sc->stat_IfInRuleCheckerDiscards, 9574 0, "Received packets discarded by rule"); 9575 9576 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9577 "stat_IfInFTQDiscards", 9578 CTLFLAG_RD, &sc->stat_IfInFTQDiscards, 9579 0, "Received packet FTQ discards"); 9580 9581 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9582 "stat_IfInMBUFDiscards", 9583 CTLFLAG_RD, &sc->stat_IfInMBUFDiscards, 9584 0, "Received packets discarded due to lack " 9585 "of controller buffer memory"); 9586 9587 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9588 "stat_IfInRuleCheckerP4Hit", 9589 CTLFLAG_RD, &sc->stat_IfInRuleCheckerP4Hit, 9590 0, "Received packets rule checker hits"); 9591 9592 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9593 "stat_CatchupInRuleCheckerDiscards", 9594 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerDiscards, 9595 0, "Received packets discarded in Catchup path"); 9596 9597 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9598 "stat_CatchupInFTQDiscards", 9599 CTLFLAG_RD, &sc->stat_CatchupInFTQDiscards, 9600 0, "Received packets discarded in FTQ in Catchup path"); 9601 9602 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9603 "stat_CatchupInMBUFDiscards", 9604 CTLFLAG_RD, &sc->stat_CatchupInMBUFDiscards, 9605 0, "Received packets discarded in controller " 9606 "buffer memory in Catchup path"); 9607 9608 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9609 "stat_CatchupInRuleCheckerP4Hit", 9610 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerP4Hit, 9611 0, "Received packets rule checker hits in Catchup path"); 9612 9613 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9614 "com_no_buffers", 9615 CTLFLAG_RD, &sc->com_no_buffers, 9616 0, "Valid packets received but no RX buffers available"); 9617 9618#ifdef BCE_DEBUG 9619 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9620 "driver_state", CTLTYPE_INT | CTLFLAG_RW, 9621 (void *)sc, 0, 9622 bce_sysctl_driver_state, "I", "Drive state information"); 9623 9624 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9625 "hw_state", CTLTYPE_INT | CTLFLAG_RW, 9626 (void *)sc, 0, 9627 bce_sysctl_hw_state, "I", "Hardware state information"); 9628 9629 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9630 "status_block", CTLTYPE_INT | CTLFLAG_RW, 9631 (void *)sc, 0, 9632 bce_sysctl_status_block, "I", "Dump status block"); 9633 9634 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9635 "stats_block", CTLTYPE_INT | CTLFLAG_RW, 9636 (void *)sc, 0, 9637 bce_sysctl_stats_block, "I", "Dump statistics block"); 9638 9639 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9640 "stats_clear", CTLTYPE_INT | CTLFLAG_RW, 9641 (void *)sc, 0, 9642 bce_sysctl_stats_clear, "I", "Clear statistics block"); 9643 9644 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9645 "shmem_state", CTLTYPE_INT | CTLFLAG_RW, 9646 (void *)sc, 0, 9647 bce_sysctl_shmem_state, "I", "Shared memory state information"); 9648 9649 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9650 "bc_state", CTLTYPE_INT | CTLFLAG_RW, 9651 (void *)sc, 0, 9652 bce_sysctl_bc_state, "I", "Bootcode state information"); 9653 9654 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9655 "dump_rx_bd_chain", CTLTYPE_INT | CTLFLAG_RW, 9656 (void *)sc, 0, 9657 bce_sysctl_dump_rx_bd_chain, "I", "Dump RX BD chain"); 9658 9659 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9660 "dump_rx_mbuf_chain", CTLTYPE_INT | CTLFLAG_RW, 9661 (void *)sc, 0, 9662 bce_sysctl_dump_rx_mbuf_chain, "I", "Dump RX MBUF chain"); 9663 9664 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9665 "dump_tx_chain", CTLTYPE_INT | CTLFLAG_RW, 9666 (void *)sc, 0, 9667 bce_sysctl_dump_tx_chain, "I", "Dump tx_bd chain"); 9668 9669 if (bce_hdr_split == TRUE) { 9670 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9671 "dump_pg_chain", CTLTYPE_INT | CTLFLAG_RW, 9672 (void *)sc, 0, 9673 bce_sysctl_dump_pg_chain, "I", "Dump page chain"); 9674 } 9675 9676 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9677 "dump_ctx", CTLTYPE_INT | CTLFLAG_RW, 9678 (void *)sc, 0, 9679 bce_sysctl_dump_ctx, "I", "Dump context memory"); 9680 9681 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9682 "breakpoint", CTLTYPE_INT | CTLFLAG_RW, 9683 (void *)sc, 0, 9684 bce_sysctl_breakpoint, "I", "Driver breakpoint"); 9685 9686 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9687 "reg_read", CTLTYPE_INT | CTLFLAG_RW, 9688 (void *)sc, 0, 9689 bce_sysctl_reg_read, "I", "Register read"); 9690 9691 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9692 "nvram_read", CTLTYPE_INT | CTLFLAG_RW, 9693 (void *)sc, 0, 9694 bce_sysctl_nvram_read, "I", "NVRAM read"); 9695 9696 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9697 "phy_read", CTLTYPE_INT | CTLFLAG_RW, 9698 (void *)sc, 0, 9699 bce_sysctl_phy_read, "I", "PHY register read"); 9700 9701#endif 9702 9703 DBEXIT(BCE_VERBOSE_MISC); 9704} 9705 9706 9707/****************************************************************************/ 9708/* BCE Debug Routines */ 9709/****************************************************************************/ 9710#ifdef BCE_DEBUG 9711 9712/****************************************************************************/ 9713/* Freezes the controller to allow for a cohesive state dump. */ 9714/* */ 9715/* Returns: */ 9716/* Nothing. */ 9717/****************************************************************************/ 9718static __attribute__ ((noinline)) void 9719bce_freeze_controller(struct bce_softc *sc) 9720{ 9721 u32 val; 9722 val = REG_RD(sc, BCE_MISC_COMMAND); 9723 val |= BCE_MISC_COMMAND_DISABLE_ALL; 9724 REG_WR(sc, BCE_MISC_COMMAND, val); 9725} 9726 9727 9728/****************************************************************************/ 9729/* Unfreezes the controller after a freeze operation. This may not always */ 9730/* work and the controller will require a reset! */ 9731/* */ 9732/* Returns: */ 9733/* Nothing. */ 9734/****************************************************************************/ 9735static __attribute__ ((noinline)) void 9736bce_unfreeze_controller(struct bce_softc *sc) 9737{ 9738 u32 val; 9739 val = REG_RD(sc, BCE_MISC_COMMAND); 9740 val |= BCE_MISC_COMMAND_ENABLE_ALL; 9741 REG_WR(sc, BCE_MISC_COMMAND, val); 9742} 9743 9744 9745/****************************************************************************/ 9746/* Prints out Ethernet frame information from an mbuf. */ 9747/* */ 9748/* Partially decode an Ethernet frame to look at some important headers. */ 9749/* */ 9750/* Returns: */ 9751/* Nothing. */ 9752/****************************************************************************/ 9753static __attribute__ ((noinline)) void 9754bce_dump_enet(struct bce_softc *sc, struct mbuf *m) 9755{ 9756 struct ether_vlan_header *eh; 9757 u16 etype; 9758 int ehlen; 9759 struct ip *ip; 9760 struct tcphdr *th; 9761 struct udphdr *uh; 9762 struct arphdr *ah; 9763 9764 BCE_PRINTF( 9765 "-----------------------------" 9766 " Frame Decode " 9767 "-----------------------------\n"); 9768 9769 eh = mtod(m, struct ether_vlan_header *); 9770 9771 /* Handle VLAN encapsulation if present. */ 9772 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 9773 etype = ntohs(eh->evl_proto); 9774 ehlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 9775 } else { 9776 etype = ntohs(eh->evl_encap_proto); 9777 ehlen = ETHER_HDR_LEN; 9778 } 9779 9780 /* ToDo: Add VLAN output. */ 9781 BCE_PRINTF("enet: dest = %6D, src = %6D, type = 0x%04X, hlen = %d\n", 9782 eh->evl_dhost, ":", eh->evl_shost, ":", etype, ehlen); 9783 9784 switch (etype) { 9785 case ETHERTYPE_IP: 9786 ip = (struct ip *)(m->m_data + ehlen); 9787 BCE_PRINTF("--ip: dest = 0x%08X , src = 0x%08X, " 9788 "len = %d bytes, protocol = 0x%02X, xsum = 0x%04X\n", 9789 ntohl(ip->ip_dst.s_addr), ntohl(ip->ip_src.s_addr), 9790 ntohs(ip->ip_len), ip->ip_p, ntohs(ip->ip_sum)); 9791 9792 switch (ip->ip_p) { 9793 case IPPROTO_TCP: 9794 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 9795 BCE_PRINTF("-tcp: dest = %d, src = %d, hlen = " 9796 "%d bytes, flags = 0x%b, csum = 0x%04X\n", 9797 ntohs(th->th_dport), ntohs(th->th_sport), 9798 (th->th_off << 2), th->th_flags, 9799 "\20\10CWR\07ECE\06URG\05ACK\04PSH\03RST" 9800 "\02SYN\01FIN", ntohs(th->th_sum)); 9801 break; 9802 case IPPROTO_UDP: 9803 uh = (struct udphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 9804 BCE_PRINTF("-udp: dest = %d, src = %d, len = %d " 9805 "bytes, csum = 0x%04X\n", ntohs(uh->uh_dport), 9806 ntohs(uh->uh_sport), ntohs(uh->uh_ulen), 9807 ntohs(uh->uh_sum)); 9808 break; 9809 case IPPROTO_ICMP: 9810 BCE_PRINTF("icmp:\n"); 9811 break; 9812 default: 9813 BCE_PRINTF("----: Other IP protocol.\n"); 9814 } 9815 break; 9816 case ETHERTYPE_IPV6: 9817 BCE_PRINTF("ipv6: No decode supported.\n"); 9818 break; 9819 case ETHERTYPE_ARP: 9820 BCE_PRINTF("-arp: "); 9821 ah = (struct arphdr *) (m->m_data + ehlen); 9822 switch (ntohs(ah->ar_op)) { 9823 case ARPOP_REVREQUEST: 9824 printf("reverse ARP request\n"); 9825 break; 9826 case ARPOP_REVREPLY: 9827 printf("reverse ARP reply\n"); 9828 break; 9829 case ARPOP_REQUEST: 9830 printf("ARP request\n"); 9831 break; 9832 case ARPOP_REPLY: 9833 printf("ARP reply\n"); 9834 break; 9835 default: 9836 printf("other ARP operation\n"); 9837 } 9838 break; 9839 default: 9840 BCE_PRINTF("----: Other protocol.\n"); 9841 } 9842 9843 BCE_PRINTF( 9844 "-----------------------------" 9845 "--------------" 9846 "-----------------------------\n"); 9847} 9848 9849 9850/****************************************************************************/ 9851/* Prints out information about an mbuf. */ 9852/* */ 9853/* Returns: */ 9854/* Nothing. */ 9855/****************************************************************************/ 9856static __attribute__ ((noinline)) void 9857bce_dump_mbuf(struct bce_softc *sc, struct mbuf *m) 9858{ 9859 struct mbuf *mp = m; 9860 9861 if (m == NULL) { 9862 BCE_PRINTF("mbuf: null pointer\n"); 9863 return; 9864 } 9865 9866 while (mp) { 9867 BCE_PRINTF("mbuf: %p, m_len = %d, m_flags = 0x%b, " 9868 "m_data = %p\n", mp, mp->m_len, mp->m_flags, 9869 "\20\1M_EXT\2M_PKTHDR\3M_EOR\4M_RDONLY", mp->m_data); 9870 9871 if (mp->m_flags & M_PKTHDR) { 9872 BCE_PRINTF("- m_pkthdr: len = %d, flags = 0x%b, " 9873 "csum_flags = %b\n", mp->m_pkthdr.len, 9874 mp->m_flags, M_FLAG_PRINTF, 9875 mp->m_pkthdr.csum_flags, 9876 "\20\1CSUM_IP\2CSUM_TCP\3CSUM_UDP" 9877 "\5CSUM_FRAGMENT\6CSUM_TSO\11CSUM_IP_CHECKED" 9878 "\12CSUM_IP_VALID\13CSUM_DATA_VALID" 9879 "\14CSUM_PSEUDO_HDR"); 9880 } 9881 9882 if (mp->m_flags & M_EXT) { 9883 BCE_PRINTF("- m_ext: %p, ext_size = %d, type = ", 9884 mp->m_ext.ext_buf, mp->m_ext.ext_size); 9885 switch (mp->m_ext.ext_type) { 9886 case EXT_CLUSTER: 9887 printf("EXT_CLUSTER\n"); break; 9888 case EXT_SFBUF: 9889 printf("EXT_SFBUF\n"); break; 9890 case EXT_JUMBO9: 9891 printf("EXT_JUMBO9\n"); break; 9892 case EXT_JUMBO16: 9893 printf("EXT_JUMBO16\n"); break; 9894 case EXT_PACKET: 9895 printf("EXT_PACKET\n"); break; 9896 case EXT_MBUF: 9897 printf("EXT_MBUF\n"); break; 9898 case EXT_NET_DRV: 9899 printf("EXT_NET_DRV\n"); break; 9900 case EXT_MOD_TYPE: 9901 printf("EXT_MDD_TYPE\n"); break; 9902 case EXT_DISPOSABLE: 9903 printf("EXT_DISPOSABLE\n"); break; 9904 case EXT_EXTREF: 9905 printf("EXT_EXTREF\n"); break; 9906 default: 9907 printf("UNKNOWN\n"); 9908 } 9909 } 9910 9911 mp = mp->m_next; 9912 } 9913} 9914 9915 9916/****************************************************************************/ 9917/* Prints out the mbufs in the TX mbuf chain. */ 9918/* */ 9919/* Returns: */ 9920/* Nothing. */ 9921/****************************************************************************/ 9922static __attribute__ ((noinline)) void 9923bce_dump_tx_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count) 9924{ 9925 struct mbuf *m; 9926 9927 BCE_PRINTF( 9928 "----------------------------" 9929 " tx mbuf data " 9930 "----------------------------\n"); 9931 9932 for (int i = 0; i < count; i++) { 9933 m = sc->tx_mbuf_ptr[chain_prod]; 9934 BCE_PRINTF("txmbuf[0x%04X]\n", chain_prod); 9935 bce_dump_mbuf(sc, m); 9936 chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod)); 9937 } 9938 9939 BCE_PRINTF( 9940 "----------------------------" 9941 "----------------" 9942 "----------------------------\n"); 9943} 9944 9945 9946/****************************************************************************/ 9947/* Prints out the mbufs in the RX mbuf chain. */ 9948/* */ 9949/* Returns: */ 9950/* Nothing. */ 9951/****************************************************************************/ 9952static __attribute__ ((noinline)) void 9953bce_dump_rx_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count) 9954{ 9955 struct mbuf *m; 9956 9957 BCE_PRINTF( 9958 "----------------------------" 9959 " rx mbuf data " 9960 "----------------------------\n"); 9961 9962 for (int i = 0; i < count; i++) { 9963 m = sc->rx_mbuf_ptr[chain_prod]; 9964 BCE_PRINTF("rxmbuf[0x%04X]\n", chain_prod); 9965 bce_dump_mbuf(sc, m); 9966 chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod)); 9967 } 9968 9969 9970 BCE_PRINTF( 9971 "----------------------------" 9972 "----------------" 9973 "----------------------------\n"); 9974} 9975 9976 9977/****************************************************************************/ 9978/* Prints out the mbufs in the mbuf page chain. */ 9979/* */ 9980/* Returns: */ 9981/* Nothing. */ 9982/****************************************************************************/ 9983static __attribute__ ((noinline)) void 9984bce_dump_pg_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count) 9985{ 9986 struct mbuf *m; 9987 9988 BCE_PRINTF( 9989 "----------------------------" 9990 " pg mbuf data " 9991 "----------------------------\n"); 9992 9993 for (int i = 0; i < count; i++) { 9994 m = sc->pg_mbuf_ptr[chain_prod]; 9995 BCE_PRINTF("pgmbuf[0x%04X]\n", chain_prod); 9996 bce_dump_mbuf(sc, m); 9997 chain_prod = PG_CHAIN_IDX(NEXT_PG_BD(chain_prod)); 9998 } 9999 10000 10001 BCE_PRINTF( 10002 "----------------------------" 10003 "----------------" 10004 "----------------------------\n"); 10005} 10006 10007 10008/****************************************************************************/ 10009/* Prints out a tx_bd structure. */ 10010/* */ 10011/* Returns: */ 10012/* Nothing. */ 10013/****************************************************************************/ 10014static __attribute__ ((noinline)) void 10015bce_dump_txbd(struct bce_softc *sc, int idx, struct tx_bd *txbd) 10016{ 10017 int i = 0; 10018 10019 if (idx > MAX_TX_BD_ALLOC) 10020 /* Index out of range. */ 10021 BCE_PRINTF("tx_bd[0x%04X]: Invalid tx_bd index!\n", idx); 10022 else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 10023 /* TX Chain page pointer. */ 10024 BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page " 10025 "pointer\n", idx, txbd->tx_bd_haddr_hi, 10026 txbd->tx_bd_haddr_lo); 10027 else { 10028 /* Normal tx_bd entry. */ 10029 BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, " 10030 "mss_nbytes = 0x%08X, vlan tag = 0x%04X, flags = " 10031 "0x%04X (", idx, txbd->tx_bd_haddr_hi, 10032 txbd->tx_bd_haddr_lo, txbd->tx_bd_mss_nbytes, 10033 txbd->tx_bd_vlan_tag, txbd->tx_bd_flags); 10034 10035 if (txbd->tx_bd_flags & TX_BD_FLAGS_CONN_FAULT) { 10036 if (i>0) 10037 printf("|"); 10038 printf("CONN_FAULT"); 10039 i++; 10040 } 10041 10042 if (txbd->tx_bd_flags & TX_BD_FLAGS_TCP_UDP_CKSUM) { 10043 if (i>0) 10044 printf("|"); 10045 printf("TCP_UDP_CKSUM"); 10046 i++; 10047 } 10048 10049 if (txbd->tx_bd_flags & TX_BD_FLAGS_IP_CKSUM) { 10050 if (i>0) 10051 printf("|"); 10052 printf("IP_CKSUM"); 10053 i++; 10054 } 10055 10056 if (txbd->tx_bd_flags & TX_BD_FLAGS_VLAN_TAG) { 10057 if (i>0) 10058 printf("|"); 10059 printf("VLAN"); 10060 i++; 10061 } 10062 10063 if (txbd->tx_bd_flags & TX_BD_FLAGS_COAL_NOW) { 10064 if (i>0) 10065 printf("|"); 10066 printf("COAL_NOW"); 10067 i++; 10068 } 10069 10070 if (txbd->tx_bd_flags & TX_BD_FLAGS_DONT_GEN_CRC) { 10071 if (i>0) 10072 printf("|"); 10073 printf("DONT_GEN_CRC"); 10074 i++; 10075 } 10076 10077 if (txbd->tx_bd_flags & TX_BD_FLAGS_START) { 10078 if (i>0) 10079 printf("|"); 10080 printf("START"); 10081 i++; 10082 } 10083 10084 if (txbd->tx_bd_flags & TX_BD_FLAGS_END) { 10085 if (i>0) 10086 printf("|"); 10087 printf("END"); 10088 i++; 10089 } 10090 10091 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_LSO) { 10092 if (i>0) 10093 printf("|"); 10094 printf("LSO"); 10095 i++; 10096 } 10097 10098 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_OPTION_WORD) { 10099 if (i>0) 10100 printf("|"); 10101 printf("SW_OPTION=%d", ((txbd->tx_bd_flags & 10102 TX_BD_FLAGS_SW_OPTION_WORD) >> 8)); i++; 10103 } 10104 10105 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_FLAGS) { 10106 if (i>0) 10107 printf("|"); 10108 printf("SW_FLAGS"); 10109 i++; 10110 } 10111 10112 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_SNAP) { 10113 if (i>0) 10114 printf("|"); 10115 printf("SNAP)"); 10116 } else { 10117 printf(")\n"); 10118 } 10119 } 10120} 10121 10122 10123/****************************************************************************/ 10124/* Prints out a rx_bd structure. */ 10125/* */ 10126/* Returns: */ 10127/* Nothing. */ 10128/****************************************************************************/ 10129static __attribute__ ((noinline)) void 10130bce_dump_rxbd(struct bce_softc *sc, int idx, struct rx_bd *rxbd) 10131{ 10132 if (idx > MAX_RX_BD_ALLOC) 10133 /* Index out of range. */ 10134 BCE_PRINTF("rx_bd[0x%04X]: Invalid rx_bd index!\n", idx); 10135 else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 10136 /* RX Chain page pointer. */ 10137 BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page " 10138 "pointer\n", idx, rxbd->rx_bd_haddr_hi, 10139 rxbd->rx_bd_haddr_lo); 10140 else 10141 /* Normal rx_bd entry. */ 10142 BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = " 10143 "0x%08X, flags = 0x%08X\n", idx, rxbd->rx_bd_haddr_hi, 10144 rxbd->rx_bd_haddr_lo, rxbd->rx_bd_len, 10145 rxbd->rx_bd_flags); 10146} 10147 10148 10149/****************************************************************************/ 10150/* Prints out a rx_bd structure in the page chain. */ 10151/* */ 10152/* Returns: */ 10153/* Nothing. */ 10154/****************************************************************************/ 10155static __attribute__ ((noinline)) void 10156bce_dump_pgbd(struct bce_softc *sc, int idx, struct rx_bd *pgbd) 10157{ 10158 if (idx > MAX_PG_BD_ALLOC) 10159 /* Index out of range. */ 10160 BCE_PRINTF("pg_bd[0x%04X]: Invalid pg_bd index!\n", idx); 10161 else if ((idx & USABLE_PG_BD_PER_PAGE) == USABLE_PG_BD_PER_PAGE) 10162 /* Page Chain page pointer. */ 10163 BCE_PRINTF("px_bd[0x%04X]: haddr = 0x%08X:%08X, chain page pointer\n", 10164 idx, pgbd->rx_bd_haddr_hi, pgbd->rx_bd_haddr_lo); 10165 else 10166 /* Normal rx_bd entry. */ 10167 BCE_PRINTF("pg_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = 0x%08X, " 10168 "flags = 0x%08X\n", idx, 10169 pgbd->rx_bd_haddr_hi, pgbd->rx_bd_haddr_lo, 10170 pgbd->rx_bd_len, pgbd->rx_bd_flags); 10171} 10172 10173 10174/****************************************************************************/ 10175/* Prints out a l2_fhdr structure. */ 10176/* */ 10177/* Returns: */ 10178/* Nothing. */ 10179/****************************************************************************/ 10180static __attribute__ ((noinline)) void 10181bce_dump_l2fhdr(struct bce_softc *sc, int idx, struct l2_fhdr *l2fhdr) 10182{ 10183 BCE_PRINTF("l2_fhdr[0x%04X]: status = 0x%b, " 10184 "pkt_len = %d, vlan = 0x%04x, ip_xsum/hdr_len = 0x%04X, " 10185 "tcp_udp_xsum = 0x%04X\n", idx, 10186 l2fhdr->l2_fhdr_status, BCE_L2FHDR_PRINTFB, 10187 l2fhdr->l2_fhdr_pkt_len, l2fhdr->l2_fhdr_vlan_tag, 10188 l2fhdr->l2_fhdr_ip_xsum, l2fhdr->l2_fhdr_tcp_udp_xsum); 10189} 10190 10191 10192/****************************************************************************/ 10193/* Prints out context memory info. (Only useful for CID 0 to 16.) */ 10194/* */ 10195/* Returns: */ 10196/* Nothing. */ 10197/****************************************************************************/ 10198static __attribute__ ((noinline)) void 10199bce_dump_ctx(struct bce_softc *sc, u16 cid) 10200{ 10201 if (cid > TX_CID) { 10202 BCE_PRINTF(" Unknown CID\n"); 10203 return; 10204 } 10205 10206 BCE_PRINTF( 10207 "----------------------------" 10208 " CTX Data " 10209 "----------------------------\n"); 10210 10211 BCE_PRINTF(" 0x%04X - (CID) Context ID\n", cid); 10212 10213 if (cid == RX_CID) { 10214 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_BDIDX) host rx " 10215 "producer index\n", 10216 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_HOST_BDIDX)); 10217 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_BSEQ) host " 10218 "byte sequence\n", CTX_RD(sc, GET_CID_ADDR(cid), 10219 BCE_L2CTX_RX_HOST_BSEQ)); 10220 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BSEQ) h/w byte sequence\n", 10221 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BSEQ)); 10222 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDHADDR_HI) h/w buffer " 10223 "descriptor address\n", 10224 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BDHADDR_HI)); 10225 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDHADDR_LO) h/w buffer " 10226 "descriptor address\n", 10227 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BDHADDR_LO)); 10228 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDIDX) h/w rx consumer " 10229 "index\n", CTX_RD(sc, GET_CID_ADDR(cid), 10230 BCE_L2CTX_RX_NX_BDIDX)); 10231 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_PG_BDIDX) host page " 10232 "producer index\n", CTX_RD(sc, GET_CID_ADDR(cid), 10233 BCE_L2CTX_RX_HOST_PG_BDIDX)); 10234 BCE_PRINTF(" 0x%08X - (L2CTX_RX_PG_BUF_SIZE) host rx_bd/page " 10235 "buffer size\n", CTX_RD(sc, GET_CID_ADDR(cid), 10236 BCE_L2CTX_RX_PG_BUF_SIZE)); 10237 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDHADDR_HI) h/w page " 10238 "chain address\n", CTX_RD(sc, GET_CID_ADDR(cid), 10239 BCE_L2CTX_RX_NX_PG_BDHADDR_HI)); 10240 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDHADDR_LO) h/w page " 10241 "chain address\n", CTX_RD(sc, GET_CID_ADDR(cid), 10242 BCE_L2CTX_RX_NX_PG_BDHADDR_LO)); 10243 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDIDX) h/w page " 10244 "consumer index\n", CTX_RD(sc, GET_CID_ADDR(cid), 10245 BCE_L2CTX_RX_NX_PG_BDIDX)); 10246 } else if (cid == TX_CID) { 10247 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 10248 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TYPE_XI) ctx type\n", 10249 CTX_RD(sc, GET_CID_ADDR(cid), 10250 BCE_L2CTX_TX_TYPE_XI)); 10251 BCE_PRINTF(" 0x%08X - (L2CTX_CMD_TX_TYPE_XI) ctx " 10252 "cmd\n", CTX_RD(sc, GET_CID_ADDR(cid), 10253 BCE_L2CTX_TX_CMD_TYPE_XI)); 10254 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BDHADDR_HI_XI) " 10255 "h/w buffer descriptor address\n", 10256 CTX_RD(sc, GET_CID_ADDR(cid), 10257 BCE_L2CTX_TX_TBDR_BHADDR_HI_XI)); 10258 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BHADDR_LO_XI) " 10259 "h/w buffer descriptor address\n", 10260 CTX_RD(sc, GET_CID_ADDR(cid), 10261 BCE_L2CTX_TX_TBDR_BHADDR_LO_XI)); 10262 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BIDX_XI) " 10263 "host producer index\n", 10264 CTX_RD(sc, GET_CID_ADDR(cid), 10265 BCE_L2CTX_TX_HOST_BIDX_XI)); 10266 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BSEQ_XI) " 10267 "host byte sequence\n", 10268 CTX_RD(sc, GET_CID_ADDR(cid), 10269 BCE_L2CTX_TX_HOST_BSEQ_XI)); 10270 } else { 10271 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TYPE) ctx type\n", 10272 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_TX_TYPE)); 10273 BCE_PRINTF(" 0x%08X - (L2CTX_TX_CMD_TYPE) ctx cmd\n", 10274 CTX_RD(sc, GET_CID_ADDR(cid), 10275 BCE_L2CTX_TX_CMD_TYPE)); 10276 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BDHADDR_HI) " 10277 "h/w buffer descriptor address\n", 10278 CTX_RD(sc, GET_CID_ADDR(cid), 10279 BCE_L2CTX_TX_TBDR_BHADDR_HI)); 10280 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BHADDR_LO) " 10281 "h/w buffer descriptor address\n", 10282 CTX_RD(sc, GET_CID_ADDR(cid), 10283 BCE_L2CTX_TX_TBDR_BHADDR_LO)); 10284 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BIDX) host " 10285 "producer index\n", CTX_RD(sc, GET_CID_ADDR(cid), 10286 BCE_L2CTX_TX_HOST_BIDX)); 10287 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BSEQ) host byte " 10288 "sequence\n", CTX_RD(sc, GET_CID_ADDR(cid), 10289 BCE_L2CTX_TX_HOST_BSEQ)); 10290 } 10291 } 10292 10293 BCE_PRINTF( 10294 "----------------------------" 10295 " Raw CTX " 10296 "----------------------------\n"); 10297 10298 for (int i = 0x0; i < 0x300; i += 0x10) { 10299 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", i, 10300 CTX_RD(sc, GET_CID_ADDR(cid), i), 10301 CTX_RD(sc, GET_CID_ADDR(cid), i + 0x4), 10302 CTX_RD(sc, GET_CID_ADDR(cid), i + 0x8), 10303 CTX_RD(sc, GET_CID_ADDR(cid), i + 0xc)); 10304 } 10305 10306 10307 BCE_PRINTF( 10308 "----------------------------" 10309 "----------------" 10310 "----------------------------\n"); 10311} 10312 10313 10314/****************************************************************************/ 10315/* Prints out the FTQ data. */ 10316/* */ 10317/* Returns: */ 10318/* Nothing. */ 10319/****************************************************************************/ 10320static __attribute__ ((noinline)) void 10321bce_dump_ftqs(struct bce_softc *sc) 10322{ 10323 u32 cmd, ctl, cur_depth, max_depth, valid_cnt, val; 10324 10325 BCE_PRINTF( 10326 "----------------------------" 10327 " FTQ Data " 10328 "----------------------------\n"); 10329 10330 BCE_PRINTF(" FTQ Command Control Depth_Now " 10331 "Max_Depth Valid_Cnt \n"); 10332 BCE_PRINTF(" ------- ---------- ---------- ---------- " 10333 "---------- ----------\n"); 10334 10335 /* Setup the generic statistic counters for the FTQ valid count. */ 10336 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT << 24) | 10337 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT << 16) | 10338 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT << 8) | 10339 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT); 10340 REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val); 10341 10342 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT << 24) | 10343 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT << 16) | 10344 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT << 8) | 10345 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT); 10346 REG_WR(sc, BCE_HC_STAT_GEN_SEL_1, val); 10347 10348 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT << 24) | 10349 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT << 16) | 10350 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT << 8) | 10351 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT); 10352 REG_WR(sc, BCE_HC_STAT_GEN_SEL_2, val); 10353 10354 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT << 24) | 10355 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT << 16) | 10356 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT << 8) | 10357 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT); 10358 REG_WR(sc, BCE_HC_STAT_GEN_SEL_3, val); 10359 10360 /* Input queue to the Receive Lookup state machine */ 10361 cmd = REG_RD(sc, BCE_RLUP_FTQ_CMD); 10362 ctl = REG_RD(sc, BCE_RLUP_FTQ_CTL); 10363 cur_depth = (ctl & BCE_RLUP_FTQ_CTL_CUR_DEPTH) >> 22; 10364 max_depth = (ctl & BCE_RLUP_FTQ_CTL_MAX_DEPTH) >> 12; 10365 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0); 10366 BCE_PRINTF(" RLUP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10367 cmd, ctl, cur_depth, max_depth, valid_cnt); 10368 10369 /* Input queue to the Receive Processor */ 10370 cmd = REG_RD_IND(sc, BCE_RXP_FTQ_CMD); 10371 ctl = REG_RD_IND(sc, BCE_RXP_FTQ_CTL); 10372 cur_depth = (ctl & BCE_RXP_FTQ_CTL_CUR_DEPTH) >> 22; 10373 max_depth = (ctl & BCE_RXP_FTQ_CTL_MAX_DEPTH) >> 12; 10374 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1); 10375 BCE_PRINTF(" RXP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10376 cmd, ctl, cur_depth, max_depth, valid_cnt); 10377 10378 /* Input queue to the Recevie Processor */ 10379 cmd = REG_RD_IND(sc, BCE_RXP_CFTQ_CMD); 10380 ctl = REG_RD_IND(sc, BCE_RXP_CFTQ_CTL); 10381 cur_depth = (ctl & BCE_RXP_CFTQ_CTL_CUR_DEPTH) >> 22; 10382 max_depth = (ctl & BCE_RXP_CFTQ_CTL_MAX_DEPTH) >> 12; 10383 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2); 10384 BCE_PRINTF(" RXPC 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10385 cmd, ctl, cur_depth, max_depth, valid_cnt); 10386 10387 /* Input queue to the Receive Virtual to Physical state machine */ 10388 cmd = REG_RD(sc, BCE_RV2P_PFTQ_CMD); 10389 ctl = REG_RD(sc, BCE_RV2P_PFTQ_CTL); 10390 cur_depth = (ctl & BCE_RV2P_PFTQ_CTL_CUR_DEPTH) >> 22; 10391 max_depth = (ctl & BCE_RV2P_PFTQ_CTL_MAX_DEPTH) >> 12; 10392 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT3); 10393 BCE_PRINTF(" RV2PP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10394 cmd, ctl, cur_depth, max_depth, valid_cnt); 10395 10396 /* Input queue to the Recevie Virtual to Physical state machine */ 10397 cmd = REG_RD(sc, BCE_RV2P_MFTQ_CMD); 10398 ctl = REG_RD(sc, BCE_RV2P_MFTQ_CTL); 10399 cur_depth = (ctl & BCE_RV2P_MFTQ_CTL_CUR_DEPTH) >> 22; 10400 max_depth = (ctl & BCE_RV2P_MFTQ_CTL_MAX_DEPTH) >> 12; 10401 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT4); 10402 BCE_PRINTF(" RV2PM 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10403 cmd, ctl, cur_depth, max_depth, valid_cnt); 10404 10405 /* Input queue to the Receive Virtual to Physical state machine */ 10406 cmd = REG_RD(sc, BCE_RV2P_TFTQ_CMD); 10407 ctl = REG_RD(sc, BCE_RV2P_TFTQ_CTL); 10408 cur_depth = (ctl & BCE_RV2P_TFTQ_CTL_CUR_DEPTH) >> 22; 10409 max_depth = (ctl & BCE_RV2P_TFTQ_CTL_MAX_DEPTH) >> 12; 10410 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT5); 10411 BCE_PRINTF(" RV2PT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10412 cmd, ctl, cur_depth, max_depth, valid_cnt); 10413 10414 /* Input queue to the Receive DMA state machine */ 10415 cmd = REG_RD(sc, BCE_RDMA_FTQ_CMD); 10416 ctl = REG_RD(sc, BCE_RDMA_FTQ_CTL); 10417 cur_depth = (ctl & BCE_RDMA_FTQ_CTL_CUR_DEPTH) >> 22; 10418 max_depth = (ctl & BCE_RDMA_FTQ_CTL_MAX_DEPTH) >> 12; 10419 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT6); 10420 BCE_PRINTF(" RDMA 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10421 cmd, ctl, cur_depth, max_depth, valid_cnt); 10422 10423 /* Input queue to the Transmit Scheduler state machine */ 10424 cmd = REG_RD(sc, BCE_TSCH_FTQ_CMD); 10425 ctl = REG_RD(sc, BCE_TSCH_FTQ_CTL); 10426 cur_depth = (ctl & BCE_TSCH_FTQ_CTL_CUR_DEPTH) >> 22; 10427 max_depth = (ctl & BCE_TSCH_FTQ_CTL_MAX_DEPTH) >> 12; 10428 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT7); 10429 BCE_PRINTF(" TSCH 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10430 cmd, ctl, cur_depth, max_depth, valid_cnt); 10431 10432 /* Input queue to the Transmit Buffer Descriptor state machine */ 10433 cmd = REG_RD(sc, BCE_TBDR_FTQ_CMD); 10434 ctl = REG_RD(sc, BCE_TBDR_FTQ_CTL); 10435 cur_depth = (ctl & BCE_TBDR_FTQ_CTL_CUR_DEPTH) >> 22; 10436 max_depth = (ctl & BCE_TBDR_FTQ_CTL_MAX_DEPTH) >> 12; 10437 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT8); 10438 BCE_PRINTF(" TBDR 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10439 cmd, ctl, cur_depth, max_depth, valid_cnt); 10440 10441 /* Input queue to the Transmit Processor */ 10442 cmd = REG_RD_IND(sc, BCE_TXP_FTQ_CMD); 10443 ctl = REG_RD_IND(sc, BCE_TXP_FTQ_CTL); 10444 cur_depth = (ctl & BCE_TXP_FTQ_CTL_CUR_DEPTH) >> 22; 10445 max_depth = (ctl & BCE_TXP_FTQ_CTL_MAX_DEPTH) >> 12; 10446 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT9); 10447 BCE_PRINTF(" TXP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10448 cmd, ctl, cur_depth, max_depth, valid_cnt); 10449 10450 /* Input queue to the Transmit DMA state machine */ 10451 cmd = REG_RD(sc, BCE_TDMA_FTQ_CMD); 10452 ctl = REG_RD(sc, BCE_TDMA_FTQ_CTL); 10453 cur_depth = (ctl & BCE_TDMA_FTQ_CTL_CUR_DEPTH) >> 22; 10454 max_depth = (ctl & BCE_TDMA_FTQ_CTL_MAX_DEPTH) >> 12; 10455 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT10); 10456 BCE_PRINTF(" TDMA 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10457 cmd, ctl, cur_depth, max_depth, valid_cnt); 10458 10459 /* Input queue to the Transmit Patch-Up Processor */ 10460 cmd = REG_RD_IND(sc, BCE_TPAT_FTQ_CMD); 10461 ctl = REG_RD_IND(sc, BCE_TPAT_FTQ_CTL); 10462 cur_depth = (ctl & BCE_TPAT_FTQ_CTL_CUR_DEPTH) >> 22; 10463 max_depth = (ctl & BCE_TPAT_FTQ_CTL_MAX_DEPTH) >> 12; 10464 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT11); 10465 BCE_PRINTF(" TPAT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10466 cmd, ctl, cur_depth, max_depth, valid_cnt); 10467 10468 /* Input queue to the Transmit Assembler state machine */ 10469 cmd = REG_RD_IND(sc, BCE_TAS_FTQ_CMD); 10470 ctl = REG_RD_IND(sc, BCE_TAS_FTQ_CTL); 10471 cur_depth = (ctl & BCE_TAS_FTQ_CTL_CUR_DEPTH) >> 22; 10472 max_depth = (ctl & BCE_TAS_FTQ_CTL_MAX_DEPTH) >> 12; 10473 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT12); 10474 BCE_PRINTF(" TAS 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10475 cmd, ctl, cur_depth, max_depth, valid_cnt); 10476 10477 /* Input queue to the Completion Processor */ 10478 cmd = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CMD); 10479 ctl = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CTL); 10480 cur_depth = (ctl & BCE_COM_COMXQ_FTQ_CTL_CUR_DEPTH) >> 22; 10481 max_depth = (ctl & BCE_COM_COMXQ_FTQ_CTL_MAX_DEPTH) >> 12; 10482 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT13); 10483 BCE_PRINTF(" COMX 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10484 cmd, ctl, cur_depth, max_depth, valid_cnt); 10485 10486 /* Input queue to the Completion Processor */ 10487 cmd = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CMD); 10488 ctl = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CTL); 10489 cur_depth = (ctl & BCE_COM_COMTQ_FTQ_CTL_CUR_DEPTH) >> 22; 10490 max_depth = (ctl & BCE_COM_COMTQ_FTQ_CTL_MAX_DEPTH) >> 12; 10491 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT14); 10492 BCE_PRINTF(" COMT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10493 cmd, ctl, cur_depth, max_depth, valid_cnt); 10494 10495 /* Input queue to the Completion Processor */ 10496 cmd = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CMD); 10497 ctl = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CTL); 10498 cur_depth = (ctl & BCE_COM_COMQ_FTQ_CTL_CUR_DEPTH) >> 22; 10499 max_depth = (ctl & BCE_COM_COMQ_FTQ_CTL_MAX_DEPTH) >> 12; 10500 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT15); 10501 BCE_PRINTF(" COMX 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10502 cmd, ctl, cur_depth, max_depth, valid_cnt); 10503 10504 /* Setup the generic statistic counters for the FTQ valid count. */ 10505 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT << 16) | 10506 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT << 8) | 10507 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT); 10508 10509 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) 10510 val = val | 10511 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCSQ_VALID_CNT_XI << 10512 24); 10513 REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val); 10514 10515 /* Input queue to the Management Control Processor */ 10516 cmd = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CMD); 10517 ctl = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CTL); 10518 cur_depth = (ctl & BCE_MCP_MCPQ_FTQ_CTL_CUR_DEPTH) >> 22; 10519 max_depth = (ctl & BCE_MCP_MCPQ_FTQ_CTL_MAX_DEPTH) >> 12; 10520 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0); 10521 BCE_PRINTF(" MCP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10522 cmd, ctl, cur_depth, max_depth, valid_cnt); 10523 10524 /* Input queue to the Command Processor */ 10525 cmd = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CMD); 10526 ctl = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CTL); 10527 cur_depth = (ctl & BCE_CP_CPQ_FTQ_CTL_CUR_DEPTH) >> 22; 10528 max_depth = (ctl & BCE_CP_CPQ_FTQ_CTL_MAX_DEPTH) >> 12; 10529 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1); 10530 BCE_PRINTF(" CP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10531 cmd, ctl, cur_depth, max_depth, valid_cnt); 10532 10533 /* Input queue to the Completion Scheduler state machine */ 10534 cmd = REG_RD(sc, BCE_CSCH_CH_FTQ_CMD); 10535 ctl = REG_RD(sc, BCE_CSCH_CH_FTQ_CTL); 10536 cur_depth = (ctl & BCE_CSCH_CH_FTQ_CTL_CUR_DEPTH) >> 22; 10537 max_depth = (ctl & BCE_CSCH_CH_FTQ_CTL_MAX_DEPTH) >> 12; 10538 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2); 10539 BCE_PRINTF(" CS 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10540 cmd, ctl, cur_depth, max_depth, valid_cnt); 10541 10542 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 10543 /* Input queue to the RV2P Command Scheduler */ 10544 cmd = REG_RD(sc, BCE_RV2PCSR_FTQ_CMD); 10545 ctl = REG_RD(sc, BCE_RV2PCSR_FTQ_CTL); 10546 cur_depth = (ctl & 0xFFC00000) >> 22; 10547 max_depth = (ctl & 0x003FF000) >> 12; 10548 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT3); 10549 BCE_PRINTF(" RV2PCSR 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10550 cmd, ctl, cur_depth, max_depth, valid_cnt); 10551 } 10552 10553 BCE_PRINTF( 10554 "----------------------------" 10555 "----------------" 10556 "----------------------------\n"); 10557} 10558 10559 10560/****************************************************************************/ 10561/* Prints out the TX chain. */ 10562/* */ 10563/* Returns: */ 10564/* Nothing. */ 10565/****************************************************************************/ 10566static __attribute__ ((noinline)) void 10567bce_dump_tx_chain(struct bce_softc *sc, u16 tx_prod, int count) 10568{ 10569 struct tx_bd *txbd; 10570 10571 /* First some info about the tx_bd chain structure. */ 10572 BCE_PRINTF( 10573 "----------------------------" 10574 " tx_bd chain " 10575 "----------------------------\n"); 10576 10577 BCE_PRINTF("page size = 0x%08X, tx chain pages = 0x%08X\n", 10578 (u32) BCM_PAGE_SIZE, (u32) sc->tx_pages); 10579 BCE_PRINTF("tx_bd per page = 0x%08X, usable tx_bd per page = 0x%08X\n", 10580 (u32) TOTAL_TX_BD_PER_PAGE, (u32) USABLE_TX_BD_PER_PAGE); 10581 BCE_PRINTF("total tx_bd = 0x%08X\n", (u32) TOTAL_TX_BD_ALLOC); 10582 10583 BCE_PRINTF( 10584 "----------------------------" 10585 " tx_bd data " 10586 "----------------------------\n"); 10587 10588 /* Now print out a decoded list of TX buffer descriptors. */ 10589 for (int i = 0; i < count; i++) { 10590 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)]; 10591 bce_dump_txbd(sc, tx_prod, txbd); 10592 tx_prod++; 10593 } 10594 10595 BCE_PRINTF( 10596 "----------------------------" 10597 "----------------" 10598 "----------------------------\n"); 10599} 10600 10601 10602/****************************************************************************/ 10603/* Prints out the RX chain. */ 10604/* */ 10605/* Returns: */ 10606/* Nothing. */ 10607/****************************************************************************/ 10608static __attribute__ ((noinline)) void 10609bce_dump_rx_bd_chain(struct bce_softc *sc, u16 rx_prod, int count) 10610{ 10611 struct rx_bd *rxbd; 10612 10613 /* First some info about the rx_bd chain structure. */ 10614 BCE_PRINTF( 10615 "----------------------------" 10616 " rx_bd chain " 10617 "----------------------------\n"); 10618 10619 BCE_PRINTF("page size = 0x%08X, rx chain pages = 0x%08X\n", 10620 (u32) BCM_PAGE_SIZE, (u32) sc->rx_pages); 10621 10622 BCE_PRINTF("rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n", 10623 (u32) TOTAL_RX_BD_PER_PAGE, (u32) USABLE_RX_BD_PER_PAGE); 10624 10625 BCE_PRINTF("total rx_bd = 0x%08X\n", (u32) TOTAL_RX_BD_ALLOC); 10626 10627 BCE_PRINTF( 10628 "----------------------------" 10629 " rx_bd data " 10630 "----------------------------\n"); 10631 10632 /* Now print out the rx_bd's themselves. */ 10633 for (int i = 0; i < count; i++) { 10634 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)]; 10635 bce_dump_rxbd(sc, rx_prod, rxbd); 10636 rx_prod = RX_CHAIN_IDX(rx_prod + 1); 10637 } 10638 10639 BCE_PRINTF( 10640 "----------------------------" 10641 "----------------" 10642 "----------------------------\n"); 10643} 10644 10645 10646/****************************************************************************/ 10647/* Prints out the page chain. */ 10648/* */ 10649/* Returns: */ 10650/* Nothing. */ 10651/****************************************************************************/ 10652static __attribute__ ((noinline)) void 10653bce_dump_pg_chain(struct bce_softc *sc, u16 pg_prod, int count) 10654{ 10655 struct rx_bd *pgbd; 10656 10657 /* First some info about the page chain structure. */ 10658 BCE_PRINTF( 10659 "----------------------------" 10660 " page chain " 10661 "----------------------------\n"); 10662 10663 BCE_PRINTF("page size = 0x%08X, pg chain pages = 0x%08X\n", 10664 (u32) BCM_PAGE_SIZE, (u32) sc->pg_pages); 10665 10666 BCE_PRINTF("rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n", 10667 (u32) TOTAL_PG_BD_PER_PAGE, (u32) USABLE_PG_BD_PER_PAGE); 10668 10669 BCE_PRINTF("total pg_bd = 0x%08X\n", (u32) TOTAL_PG_BD_ALLOC); 10670 10671 BCE_PRINTF( 10672 "----------------------------" 10673 " page data " 10674 "----------------------------\n"); 10675 10676 /* Now print out the rx_bd's themselves. */ 10677 for (int i = 0; i < count; i++) { 10678 pgbd = &sc->pg_bd_chain[PG_PAGE(pg_prod)][PG_IDX(pg_prod)]; 10679 bce_dump_pgbd(sc, pg_prod, pgbd); 10680 pg_prod = PG_CHAIN_IDX(pg_prod + 1); 10681 } 10682 10683 BCE_PRINTF( 10684 "----------------------------" 10685 "----------------" 10686 "----------------------------\n"); 10687} 10688 10689 10690#define BCE_PRINT_RX_CONS(arg) \ 10691if (sblk->status_rx_quick_consumer_index##arg) \ 10692 BCE_PRINTF("0x%04X(0x%04X) - rx_quick_consumer_index%d\n", \ 10693 sblk->status_rx_quick_consumer_index##arg, (u16) \ 10694 RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index##arg), \ 10695 arg); 10696 10697 10698#define BCE_PRINT_TX_CONS(arg) \ 10699if (sblk->status_tx_quick_consumer_index##arg) \ 10700 BCE_PRINTF("0x%04X(0x%04X) - tx_quick_consumer_index%d\n", \ 10701 sblk->status_tx_quick_consumer_index##arg, (u16) \ 10702 TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index##arg), \ 10703 arg); 10704 10705/****************************************************************************/ 10706/* Prints out the status block from host memory. */ 10707/* */ 10708/* Returns: */ 10709/* Nothing. */ 10710/****************************************************************************/ 10711static __attribute__ ((noinline)) void 10712bce_dump_status_block(struct bce_softc *sc) 10713{ 10714 struct status_block *sblk; 10715 10716 bus_dmamap_sync(sc->status_tag, sc->status_map, BUS_DMASYNC_POSTREAD); 10717 10718 sblk = sc->status_block; 10719 10720 BCE_PRINTF( 10721 "----------------------------" 10722 " Status Block " 10723 "----------------------------\n"); 10724 10725 /* Theses indices are used for normal L2 drivers. */ 10726 BCE_PRINTF(" 0x%08X - attn_bits\n", 10727 sblk->status_attn_bits); 10728 10729 BCE_PRINTF(" 0x%08X - attn_bits_ack\n", 10730 sblk->status_attn_bits_ack); 10731 10732 BCE_PRINT_RX_CONS(0); 10733 BCE_PRINT_TX_CONS(0) 10734 10735 BCE_PRINTF(" 0x%04X - status_idx\n", sblk->status_idx); 10736 10737 /* Theses indices are not used for normal L2 drivers. */ 10738 BCE_PRINT_RX_CONS(1); BCE_PRINT_RX_CONS(2); BCE_PRINT_RX_CONS(3); 10739 BCE_PRINT_RX_CONS(4); BCE_PRINT_RX_CONS(5); BCE_PRINT_RX_CONS(6); 10740 BCE_PRINT_RX_CONS(7); BCE_PRINT_RX_CONS(8); BCE_PRINT_RX_CONS(9); 10741 BCE_PRINT_RX_CONS(10); BCE_PRINT_RX_CONS(11); BCE_PRINT_RX_CONS(12); 10742 BCE_PRINT_RX_CONS(13); BCE_PRINT_RX_CONS(14); BCE_PRINT_RX_CONS(15); 10743 10744 BCE_PRINT_TX_CONS(1); BCE_PRINT_TX_CONS(2); BCE_PRINT_TX_CONS(3); 10745 10746 if (sblk->status_completion_producer_index || 10747 sblk->status_cmd_consumer_index) 10748 BCE_PRINTF("com_prod = 0x%08X, cmd_cons = 0x%08X\n", 10749 sblk->status_completion_producer_index, 10750 sblk->status_cmd_consumer_index); 10751 10752 BCE_PRINTF( 10753 "----------------------------" 10754 "----------------" 10755 "----------------------------\n"); 10756} 10757 10758 10759#define BCE_PRINT_64BIT_STAT(arg) \ 10760if (sblk->arg##_lo || sblk->arg##_hi) \ 10761 BCE_PRINTF("0x%08X:%08X : %s\n", sblk->arg##_hi, \ 10762 sblk->arg##_lo, #arg); 10763 10764#define BCE_PRINT_32BIT_STAT(arg) \ 10765if (sblk->arg) \ 10766 BCE_PRINTF(" 0x%08X : %s\n", \ 10767 sblk->arg, #arg); 10768 10769/****************************************************************************/ 10770/* Prints out the statistics block from host memory. */ 10771/* */ 10772/* Returns: */ 10773/* Nothing. */ 10774/****************************************************************************/ 10775static __attribute__ ((noinline)) void 10776bce_dump_stats_block(struct bce_softc *sc) 10777{ 10778 struct statistics_block *sblk; 10779 10780 bus_dmamap_sync(sc->stats_tag, sc->stats_map, BUS_DMASYNC_POSTREAD); 10781 10782 sblk = sc->stats_block; 10783 10784 BCE_PRINTF( 10785 "---------------" 10786 " Stats Block (All Stats Not Shown Are 0) " 10787 "---------------\n"); 10788 10789 BCE_PRINT_64BIT_STAT(stat_IfHCInOctets); 10790 BCE_PRINT_64BIT_STAT(stat_IfHCInBadOctets); 10791 BCE_PRINT_64BIT_STAT(stat_IfHCOutOctets); 10792 BCE_PRINT_64BIT_STAT(stat_IfHCOutBadOctets); 10793 BCE_PRINT_64BIT_STAT(stat_IfHCInUcastPkts); 10794 BCE_PRINT_64BIT_STAT(stat_IfHCInBroadcastPkts); 10795 BCE_PRINT_64BIT_STAT(stat_IfHCInMulticastPkts); 10796 BCE_PRINT_64BIT_STAT(stat_IfHCOutUcastPkts); 10797 BCE_PRINT_64BIT_STAT(stat_IfHCOutBroadcastPkts); 10798 BCE_PRINT_64BIT_STAT(stat_IfHCOutMulticastPkts); 10799 BCE_PRINT_32BIT_STAT( 10800 stat_emac_tx_stat_dot3statsinternalmactransmiterrors); 10801 BCE_PRINT_32BIT_STAT(stat_Dot3StatsCarrierSenseErrors); 10802 BCE_PRINT_32BIT_STAT(stat_Dot3StatsFCSErrors); 10803 BCE_PRINT_32BIT_STAT(stat_Dot3StatsAlignmentErrors); 10804 BCE_PRINT_32BIT_STAT(stat_Dot3StatsSingleCollisionFrames); 10805 BCE_PRINT_32BIT_STAT(stat_Dot3StatsMultipleCollisionFrames); 10806 BCE_PRINT_32BIT_STAT(stat_Dot3StatsDeferredTransmissions); 10807 BCE_PRINT_32BIT_STAT(stat_Dot3StatsExcessiveCollisions); 10808 BCE_PRINT_32BIT_STAT(stat_Dot3StatsLateCollisions); 10809 BCE_PRINT_32BIT_STAT(stat_EtherStatsCollisions); 10810 BCE_PRINT_32BIT_STAT(stat_EtherStatsFragments); 10811 BCE_PRINT_32BIT_STAT(stat_EtherStatsJabbers); 10812 BCE_PRINT_32BIT_STAT(stat_EtherStatsUndersizePkts); 10813 BCE_PRINT_32BIT_STAT(stat_EtherStatsOversizePkts); 10814 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx64Octets); 10815 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx65Octetsto127Octets); 10816 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx128Octetsto255Octets); 10817 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx256Octetsto511Octets); 10818 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx512Octetsto1023Octets); 10819 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx1024Octetsto1522Octets); 10820 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx1523Octetsto9022Octets); 10821 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx64Octets); 10822 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx65Octetsto127Octets); 10823 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx128Octetsto255Octets); 10824 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx256Octetsto511Octets); 10825 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx512Octetsto1023Octets); 10826 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx1024Octetsto1522Octets); 10827 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx1523Octetsto9022Octets); 10828 BCE_PRINT_32BIT_STAT(stat_XonPauseFramesReceived); 10829 BCE_PRINT_32BIT_STAT(stat_XoffPauseFramesReceived); 10830 BCE_PRINT_32BIT_STAT(stat_OutXonSent); 10831 BCE_PRINT_32BIT_STAT(stat_OutXoffSent); 10832 BCE_PRINT_32BIT_STAT(stat_FlowControlDone); 10833 BCE_PRINT_32BIT_STAT(stat_MacControlFramesReceived); 10834 BCE_PRINT_32BIT_STAT(stat_XoffStateEntered); 10835 BCE_PRINT_32BIT_STAT(stat_IfInFramesL2FilterDiscards); 10836 BCE_PRINT_32BIT_STAT(stat_IfInRuleCheckerDiscards); 10837 BCE_PRINT_32BIT_STAT(stat_IfInFTQDiscards); 10838 BCE_PRINT_32BIT_STAT(stat_IfInMBUFDiscards); 10839 BCE_PRINT_32BIT_STAT(stat_IfInRuleCheckerP4Hit); 10840 BCE_PRINT_32BIT_STAT(stat_CatchupInRuleCheckerDiscards); 10841 BCE_PRINT_32BIT_STAT(stat_CatchupInFTQDiscards); 10842 BCE_PRINT_32BIT_STAT(stat_CatchupInMBUFDiscards); 10843 BCE_PRINT_32BIT_STAT(stat_CatchupInRuleCheckerP4Hit); 10844 10845 BCE_PRINTF( 10846 "----------------------------" 10847 "----------------" 10848 "----------------------------\n"); 10849} 10850 10851 10852/****************************************************************************/ 10853/* Prints out a summary of the driver state. */ 10854/* */ 10855/* Returns: */ 10856/* Nothing. */ 10857/****************************************************************************/ 10858static __attribute__ ((noinline)) void 10859bce_dump_driver_state(struct bce_softc *sc) 10860{ 10861 u32 val_hi, val_lo; 10862 10863 BCE_PRINTF( 10864 "-----------------------------" 10865 " Driver State " 10866 "-----------------------------\n"); 10867 10868 val_hi = BCE_ADDR_HI(sc); 10869 val_lo = BCE_ADDR_LO(sc); 10870 BCE_PRINTF("0x%08X:%08X - (sc) driver softc structure virtual " 10871 "address\n", val_hi, val_lo); 10872 10873 val_hi = BCE_ADDR_HI(sc->bce_vhandle); 10874 val_lo = BCE_ADDR_LO(sc->bce_vhandle); 10875 BCE_PRINTF("0x%08X:%08X - (sc->bce_vhandle) PCI BAR virtual " 10876 "address\n", val_hi, val_lo); 10877 10878 val_hi = BCE_ADDR_HI(sc->status_block); 10879 val_lo = BCE_ADDR_LO(sc->status_block); 10880 BCE_PRINTF("0x%08X:%08X - (sc->status_block) status block " 10881 "virtual address\n", val_hi, val_lo); 10882 10883 val_hi = BCE_ADDR_HI(sc->stats_block); 10884 val_lo = BCE_ADDR_LO(sc->stats_block); 10885 BCE_PRINTF("0x%08X:%08X - (sc->stats_block) statistics block " 10886 "virtual address\n", val_hi, val_lo); 10887 10888 val_hi = BCE_ADDR_HI(sc->tx_bd_chain); 10889 val_lo = BCE_ADDR_LO(sc->tx_bd_chain); 10890 BCE_PRINTF("0x%08X:%08X - (sc->tx_bd_chain) tx_bd chain " 10891 "virtual adddress\n", val_hi, val_lo); 10892 10893 val_hi = BCE_ADDR_HI(sc->rx_bd_chain); 10894 val_lo = BCE_ADDR_LO(sc->rx_bd_chain); 10895 BCE_PRINTF("0x%08X:%08X - (sc->rx_bd_chain) rx_bd chain " 10896 "virtual address\n", val_hi, val_lo); 10897 10898 if (bce_hdr_split == TRUE) { 10899 val_hi = BCE_ADDR_HI(sc->pg_bd_chain); 10900 val_lo = BCE_ADDR_LO(sc->pg_bd_chain); 10901 BCE_PRINTF("0x%08X:%08X - (sc->pg_bd_chain) page chain " 10902 "virtual address\n", val_hi, val_lo); 10903 } 10904 10905 val_hi = BCE_ADDR_HI(sc->tx_mbuf_ptr); 10906 val_lo = BCE_ADDR_LO(sc->tx_mbuf_ptr); 10907 BCE_PRINTF("0x%08X:%08X - (sc->tx_mbuf_ptr) tx mbuf chain " 10908 "virtual address\n", val_hi, val_lo); 10909 10910 val_hi = BCE_ADDR_HI(sc->rx_mbuf_ptr); 10911 val_lo = BCE_ADDR_LO(sc->rx_mbuf_ptr); 10912 BCE_PRINTF("0x%08X:%08X - (sc->rx_mbuf_ptr) rx mbuf chain " 10913 "virtual address\n", val_hi, val_lo); 10914 10915 if (bce_hdr_split == TRUE) { 10916 val_hi = BCE_ADDR_HI(sc->pg_mbuf_ptr); 10917 val_lo = BCE_ADDR_LO(sc->pg_mbuf_ptr); 10918 BCE_PRINTF("0x%08X:%08X - (sc->pg_mbuf_ptr) page mbuf chain " 10919 "virtual address\n", val_hi, val_lo); 10920 } 10921 10922 BCE_PRINTF(" 0x%016llX - (sc->interrupts_generated) " 10923 "h/w intrs\n", 10924 (long long unsigned int) sc->interrupts_generated); 10925 10926 BCE_PRINTF(" 0x%016llX - (sc->interrupts_rx) " 10927 "rx interrupts handled\n", 10928 (long long unsigned int) sc->interrupts_rx); 10929 10930 BCE_PRINTF(" 0x%016llX - (sc->interrupts_tx) " 10931 "tx interrupts handled\n", 10932 (long long unsigned int) sc->interrupts_tx); 10933 10934 BCE_PRINTF(" 0x%016llX - (sc->phy_interrupts) " 10935 "phy interrupts handled\n", 10936 (long long unsigned int) sc->phy_interrupts); 10937 10938 BCE_PRINTF(" 0x%08X - (sc->last_status_idx) " 10939 "status block index\n", sc->last_status_idx); 10940 10941 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->tx_prod) tx producer " 10942 "index\n", sc->tx_prod, (u16) TX_CHAIN_IDX(sc->tx_prod)); 10943 10944 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->tx_cons) tx consumer " 10945 "index\n", sc->tx_cons, (u16) TX_CHAIN_IDX(sc->tx_cons)); 10946 10947 BCE_PRINTF(" 0x%08X - (sc->tx_prod_bseq) tx producer " 10948 "byte seq index\n", sc->tx_prod_bseq); 10949 10950 BCE_PRINTF(" 0x%08X - (sc->debug_tx_mbuf_alloc) tx " 10951 "mbufs allocated\n", sc->debug_tx_mbuf_alloc); 10952 10953 BCE_PRINTF(" 0x%08X - (sc->used_tx_bd) used " 10954 "tx_bd's\n", sc->used_tx_bd); 10955 10956 BCE_PRINTF(" 0x%04X/0x%04X - (sc->tx_hi_watermark)/" 10957 "(sc->max_tx_bd)\n", sc->tx_hi_watermark, sc->max_tx_bd); 10958 10959 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->rx_prod) rx producer " 10960 "index\n", sc->rx_prod, (u16) RX_CHAIN_IDX(sc->rx_prod)); 10961 10962 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->rx_cons) rx consumer " 10963 "index\n", sc->rx_cons, (u16) RX_CHAIN_IDX(sc->rx_cons)); 10964 10965 BCE_PRINTF(" 0x%08X - (sc->rx_prod_bseq) rx producer " 10966 "byte seq index\n", sc->rx_prod_bseq); 10967 10968 BCE_PRINTF(" 0x%04X/0x%04X - (sc->rx_low_watermark)/" 10969 "(sc->max_rx_bd)\n", sc->rx_low_watermark, sc->max_rx_bd); 10970 10971 BCE_PRINTF(" 0x%08X - (sc->debug_rx_mbuf_alloc) rx " 10972 "mbufs allocated\n", sc->debug_rx_mbuf_alloc); 10973 10974 BCE_PRINTF(" 0x%08X - (sc->free_rx_bd) free " 10975 "rx_bd's\n", sc->free_rx_bd); 10976 10977 if (bce_hdr_split == TRUE) { 10978 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->pg_prod) page producer " 10979 "index\n", sc->pg_prod, (u16) PG_CHAIN_IDX(sc->pg_prod)); 10980 10981 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->pg_cons) page consumer " 10982 "index\n", sc->pg_cons, (u16) PG_CHAIN_IDX(sc->pg_cons)); 10983 10984 BCE_PRINTF(" 0x%08X - (sc->debug_pg_mbuf_alloc) page " 10985 "mbufs allocated\n", sc->debug_pg_mbuf_alloc); 10986 } 10987 10988 BCE_PRINTF(" 0x%08X - (sc->free_pg_bd) free page " 10989 "rx_bd's\n", sc->free_pg_bd); 10990 10991 BCE_PRINTF(" 0x%04X/0x%04X - (sc->pg_low_watermark)/" 10992 "(sc->max_pg_bd)\n", sc->pg_low_watermark, sc->max_pg_bd); 10993 10994 BCE_PRINTF(" 0x%08X - (sc->mbuf_alloc_failed_count) " 10995 "mbuf alloc failures\n", sc->mbuf_alloc_failed_count); 10996 10997 BCE_PRINTF(" 0x%08X - (sc->bce_flags) " 10998 "bce mac flags\n", sc->bce_flags); 10999 11000 BCE_PRINTF(" 0x%08X - (sc->bce_phy_flags) " 11001 "bce phy flags\n", sc->bce_phy_flags); 11002 11003 BCE_PRINTF( 11004 "----------------------------" 11005 "----------------" 11006 "----------------------------\n"); 11007} 11008 11009 11010/****************************************************************************/ 11011/* Prints out the hardware state through a summary of important register, */ 11012/* followed by a complete register dump. */ 11013/* */ 11014/* Returns: */ 11015/* Nothing. */ 11016/****************************************************************************/ 11017static __attribute__ ((noinline)) void 11018bce_dump_hw_state(struct bce_softc *sc) 11019{ 11020 u32 val; 11021 11022 BCE_PRINTF( 11023 "----------------------------" 11024 " Hardware State " 11025 "----------------------------\n"); 11026 11027 BCE_PRINTF("%s - bootcode version\n", sc->bce_bc_ver); 11028 11029 val = REG_RD(sc, BCE_MISC_ENABLE_STATUS_BITS); 11030 BCE_PRINTF("0x%08X - (0x%06X) misc_enable_status_bits\n", 11031 val, BCE_MISC_ENABLE_STATUS_BITS); 11032 11033 val = REG_RD(sc, BCE_DMA_STATUS); 11034 BCE_PRINTF("0x%08X - (0x%06X) dma_status\n", 11035 val, BCE_DMA_STATUS); 11036 11037 val = REG_RD(sc, BCE_CTX_STATUS); 11038 BCE_PRINTF("0x%08X - (0x%06X) ctx_status\n", 11039 val, BCE_CTX_STATUS); 11040 11041 val = REG_RD(sc, BCE_EMAC_STATUS); 11042 BCE_PRINTF("0x%08X - (0x%06X) emac_status\n", 11043 val, BCE_EMAC_STATUS); 11044 11045 val = REG_RD(sc, BCE_RPM_STATUS); 11046 BCE_PRINTF("0x%08X - (0x%06X) rpm_status\n", 11047 val, BCE_RPM_STATUS); 11048 11049 /* ToDo: Create a #define for this constant. */ 11050 val = REG_RD(sc, 0x2004); 11051 BCE_PRINTF("0x%08X - (0x%06X) rlup_status\n", 11052 val, 0x2004); 11053 11054 val = REG_RD(sc, BCE_RV2P_STATUS); 11055 BCE_PRINTF("0x%08X - (0x%06X) rv2p_status\n", 11056 val, BCE_RV2P_STATUS); 11057 11058 /* ToDo: Create a #define for this constant. */ 11059 val = REG_RD(sc, 0x2c04); 11060 BCE_PRINTF("0x%08X - (0x%06X) rdma_status\n", 11061 val, 0x2c04); 11062 11063 val = REG_RD(sc, BCE_TBDR_STATUS); 11064 BCE_PRINTF("0x%08X - (0x%06X) tbdr_status\n", 11065 val, BCE_TBDR_STATUS); 11066 11067 val = REG_RD(sc, BCE_TDMA_STATUS); 11068 BCE_PRINTF("0x%08X - (0x%06X) tdma_status\n", 11069 val, BCE_TDMA_STATUS); 11070 11071 val = REG_RD(sc, BCE_HC_STATUS); 11072 BCE_PRINTF("0x%08X - (0x%06X) hc_status\n", 11073 val, BCE_HC_STATUS); 11074 11075 val = REG_RD_IND(sc, BCE_TXP_CPU_STATE); 11076 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n", 11077 val, BCE_TXP_CPU_STATE); 11078 11079 val = REG_RD_IND(sc, BCE_TPAT_CPU_STATE); 11080 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n", 11081 val, BCE_TPAT_CPU_STATE); 11082 11083 val = REG_RD_IND(sc, BCE_RXP_CPU_STATE); 11084 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n", 11085 val, BCE_RXP_CPU_STATE); 11086 11087 val = REG_RD_IND(sc, BCE_COM_CPU_STATE); 11088 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n", 11089 val, BCE_COM_CPU_STATE); 11090 11091 val = REG_RD_IND(sc, BCE_MCP_CPU_STATE); 11092 BCE_PRINTF("0x%08X - (0x%06X) mcp_cpu_state\n", 11093 val, BCE_MCP_CPU_STATE); 11094 11095 val = REG_RD_IND(sc, BCE_CP_CPU_STATE); 11096 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n", 11097 val, BCE_CP_CPU_STATE); 11098 11099 BCE_PRINTF( 11100 "----------------------------" 11101 "----------------" 11102 "----------------------------\n"); 11103 11104 BCE_PRINTF( 11105 "----------------------------" 11106 " Register Dump " 11107 "----------------------------\n"); 11108 11109 for (int i = 0x400; i < 0x8000; i += 0x10) { 11110 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 11111 i, REG_RD(sc, i), REG_RD(sc, i + 0x4), 11112 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC)); 11113 } 11114 11115 BCE_PRINTF( 11116 "----------------------------" 11117 "----------------" 11118 "----------------------------\n"); 11119} 11120 11121 11122/****************************************************************************/ 11123/* Prints out the contentst of shared memory which is used for host driver */ 11124/* to bootcode firmware communication. */ 11125/* */ 11126/* Returns: */ 11127/* Nothing. */ 11128/****************************************************************************/ 11129static __attribute__ ((noinline)) void 11130bce_dump_shmem_state(struct bce_softc *sc) 11131{ 11132 BCE_PRINTF( 11133 "----------------------------" 11134 " Hardware State " 11135 "----------------------------\n"); 11136 11137 BCE_PRINTF("0x%08X - Shared memory base address\n", 11138 sc->bce_shmem_base); 11139 BCE_PRINTF("%s - bootcode version\n", 11140 sc->bce_bc_ver); 11141 11142 BCE_PRINTF( 11143 "----------------------------" 11144 " Shared Mem " 11145 "----------------------------\n"); 11146 11147 for (int i = 0x0; i < 0x200; i += 0x10) { 11148 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 11149 i, bce_shmem_rd(sc, i), bce_shmem_rd(sc, i + 0x4), 11150 bce_shmem_rd(sc, i + 0x8), bce_shmem_rd(sc, i + 0xC)); 11151 } 11152 11153 BCE_PRINTF( 11154 "----------------------------" 11155 "----------------" 11156 "----------------------------\n"); 11157} 11158 11159 11160/****************************************************************************/ 11161/* Prints out the mailbox queue registers. */ 11162/* */ 11163/* Returns: */ 11164/* Nothing. */ 11165/****************************************************************************/ 11166static __attribute__ ((noinline)) void 11167bce_dump_mq_regs(struct bce_softc *sc) 11168{ 11169 BCE_PRINTF( 11170 "----------------------------" 11171 " MQ Regs " 11172 "----------------------------\n"); 11173 11174 BCE_PRINTF( 11175 "----------------------------" 11176 "----------------" 11177 "----------------------------\n"); 11178 11179 for (int i = 0x3c00; i < 0x4000; i += 0x10) { 11180 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 11181 i, REG_RD(sc, i), REG_RD(sc, i + 0x4), 11182 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC)); 11183 } 11184 11185 BCE_PRINTF( 11186 "----------------------------" 11187 "----------------" 11188 "----------------------------\n"); 11189} 11190 11191 11192/****************************************************************************/ 11193/* Prints out the bootcode state. */ 11194/* */ 11195/* Returns: */ 11196/* Nothing. */ 11197/****************************************************************************/ 11198static __attribute__ ((noinline)) void 11199bce_dump_bc_state(struct bce_softc *sc) 11200{ 11201 u32 val; 11202 11203 BCE_PRINTF( 11204 "----------------------------" 11205 " Bootcode State " 11206 "----------------------------\n"); 11207 11208 BCE_PRINTF("%s - bootcode version\n", sc->bce_bc_ver); 11209 11210 val = bce_shmem_rd(sc, BCE_BC_RESET_TYPE); 11211 BCE_PRINTF("0x%08X - (0x%06X) reset_type\n", 11212 val, BCE_BC_RESET_TYPE); 11213 11214 val = bce_shmem_rd(sc, BCE_BC_STATE); 11215 BCE_PRINTF("0x%08X - (0x%06X) state\n", 11216 val, BCE_BC_STATE); 11217 11218 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); 11219 BCE_PRINTF("0x%08X - (0x%06X) condition\n", 11220 val, BCE_BC_STATE_CONDITION); 11221 11222 val = bce_shmem_rd(sc, BCE_BC_STATE_DEBUG_CMD); 11223 BCE_PRINTF("0x%08X - (0x%06X) debug_cmd\n", 11224 val, BCE_BC_STATE_DEBUG_CMD); 11225 11226 BCE_PRINTF( 11227 "----------------------------" 11228 "----------------" 11229 "----------------------------\n"); 11230} 11231 11232 11233/****************************************************************************/ 11234/* Prints out the TXP processor state. */ 11235/* */ 11236/* Returns: */ 11237/* Nothing. */ 11238/****************************************************************************/ 11239static __attribute__ ((noinline)) void 11240bce_dump_txp_state(struct bce_softc *sc, int regs) 11241{ 11242 u32 val; 11243 u32 fw_version[3]; 11244 11245 BCE_PRINTF( 11246 "----------------------------" 11247 " TXP State " 11248 "----------------------------\n"); 11249 11250 for (int i = 0; i < 3; i++) 11251 fw_version[i] = htonl(REG_RD_IND(sc, 11252 (BCE_TXP_SCRATCH + 0x10 + i * 4))); 11253 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 11254 11255 val = REG_RD_IND(sc, BCE_TXP_CPU_MODE); 11256 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_mode\n", 11257 val, BCE_TXP_CPU_MODE); 11258 11259 val = REG_RD_IND(sc, BCE_TXP_CPU_STATE); 11260 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n", 11261 val, BCE_TXP_CPU_STATE); 11262 11263 val = REG_RD_IND(sc, BCE_TXP_CPU_EVENT_MASK); 11264 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_event_mask\n", 11265 val, BCE_TXP_CPU_EVENT_MASK); 11266 11267 if (regs) { 11268 BCE_PRINTF( 11269 "----------------------------" 11270 " Register Dump " 11271 "----------------------------\n"); 11272 11273 for (int i = BCE_TXP_CPU_MODE; i < 0x68000; i += 0x10) { 11274 /* Skip the big blank spaces */ 11275 if (i < 0x454000 && i > 0x5ffff) 11276 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 11277 "0x%08X 0x%08X\n", i, 11278 REG_RD_IND(sc, i), 11279 REG_RD_IND(sc, i + 0x4), 11280 REG_RD_IND(sc, i + 0x8), 11281 REG_RD_IND(sc, i + 0xC)); 11282 } 11283 } 11284 11285 BCE_PRINTF( 11286 "----------------------------" 11287 "----------------" 11288 "----------------------------\n"); 11289} 11290 11291 11292/****************************************************************************/ 11293/* Prints out the RXP processor state. */ 11294/* */ 11295/* Returns: */ 11296/* Nothing. */ 11297/****************************************************************************/ 11298static __attribute__ ((noinline)) void 11299bce_dump_rxp_state(struct bce_softc *sc, int regs) 11300{ 11301 u32 val; 11302 u32 fw_version[3]; 11303 11304 BCE_PRINTF( 11305 "----------------------------" 11306 " RXP State " 11307 "----------------------------\n"); 11308 11309 for (int i = 0; i < 3; i++) 11310 fw_version[i] = htonl(REG_RD_IND(sc, 11311 (BCE_RXP_SCRATCH + 0x10 + i * 4))); 11312 11313 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 11314 11315 val = REG_RD_IND(sc, BCE_RXP_CPU_MODE); 11316 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_mode\n", 11317 val, BCE_RXP_CPU_MODE); 11318 11319 val = REG_RD_IND(sc, BCE_RXP_CPU_STATE); 11320 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n", 11321 val, BCE_RXP_CPU_STATE); 11322 11323 val = REG_RD_IND(sc, BCE_RXP_CPU_EVENT_MASK); 11324 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_event_mask\n", 11325 val, BCE_RXP_CPU_EVENT_MASK); 11326 11327 if (regs) { 11328 BCE_PRINTF( 11329 "----------------------------" 11330 " Register Dump " 11331 "----------------------------\n"); 11332 11333 for (int i = BCE_RXP_CPU_MODE; i < 0xe8fff; i += 0x10) { 11334 /* Skip the big blank sapces */ 11335 if (i < 0xc5400 && i > 0xdffff) 11336 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 11337 "0x%08X 0x%08X\n", i, 11338 REG_RD_IND(sc, i), 11339 REG_RD_IND(sc, i + 0x4), 11340 REG_RD_IND(sc, i + 0x8), 11341 REG_RD_IND(sc, i + 0xC)); 11342 } 11343 } 11344 11345 BCE_PRINTF( 11346 "----------------------------" 11347 "----------------" 11348 "----------------------------\n"); 11349} 11350 11351 11352/****************************************************************************/ 11353/* Prints out the TPAT processor state. */ 11354/* */ 11355/* Returns: */ 11356/* Nothing. */ 11357/****************************************************************************/ 11358static __attribute__ ((noinline)) void 11359bce_dump_tpat_state(struct bce_softc *sc, int regs) 11360{ 11361 u32 val; 11362 u32 fw_version[3]; 11363 11364 BCE_PRINTF( 11365 "----------------------------" 11366 " TPAT State " 11367 "----------------------------\n"); 11368 11369 for (int i = 0; i < 3; i++) 11370 fw_version[i] = htonl(REG_RD_IND(sc, 11371 (BCE_TPAT_SCRATCH + 0x410 + i * 4))); 11372 11373 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 11374 11375 val = REG_RD_IND(sc, BCE_TPAT_CPU_MODE); 11376 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_mode\n", 11377 val, BCE_TPAT_CPU_MODE); 11378 11379 val = REG_RD_IND(sc, BCE_TPAT_CPU_STATE); 11380 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n", 11381 val, BCE_TPAT_CPU_STATE); 11382 11383 val = REG_RD_IND(sc, BCE_TPAT_CPU_EVENT_MASK); 11384 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_event_mask\n", 11385 val, BCE_TPAT_CPU_EVENT_MASK); 11386 11387 if (regs) { 11388 BCE_PRINTF( 11389 "----------------------------" 11390 " Register Dump " 11391 "----------------------------\n"); 11392 11393 for (int i = BCE_TPAT_CPU_MODE; i < 0xa3fff; i += 0x10) { 11394 /* Skip the big blank spaces */ 11395 if (i < 0x854000 && i > 0x9ffff) 11396 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 11397 "0x%08X 0x%08X\n", i, 11398 REG_RD_IND(sc, i), 11399 REG_RD_IND(sc, i + 0x4), 11400 REG_RD_IND(sc, i + 0x8), 11401 REG_RD_IND(sc, i + 0xC)); 11402 } 11403 } 11404 11405 BCE_PRINTF( 11406 "----------------------------" 11407 "----------------" 11408 "----------------------------\n"); 11409} 11410 11411 11412/****************************************************************************/ 11413/* Prints out the Command Procesor (CP) state. */ 11414/* */ 11415/* Returns: */ 11416/* Nothing. */ 11417/****************************************************************************/ 11418static __attribute__ ((noinline)) void 11419bce_dump_cp_state(struct bce_softc *sc, int regs) 11420{ 11421 u32 val; 11422 u32 fw_version[3]; 11423 11424 BCE_PRINTF( 11425 "----------------------------" 11426 " CP State " 11427 "----------------------------\n"); 11428 11429 for (int i = 0; i < 3; i++) 11430 fw_version[i] = htonl(REG_RD_IND(sc, 11431 (BCE_CP_SCRATCH + 0x10 + i * 4))); 11432 11433 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 11434 11435 val = REG_RD_IND(sc, BCE_CP_CPU_MODE); 11436 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_mode\n", 11437 val, BCE_CP_CPU_MODE); 11438 11439 val = REG_RD_IND(sc, BCE_CP_CPU_STATE); 11440 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n", 11441 val, BCE_CP_CPU_STATE); 11442 11443 val = REG_RD_IND(sc, BCE_CP_CPU_EVENT_MASK); 11444 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_event_mask\n", val, 11445 BCE_CP_CPU_EVENT_MASK); 11446 11447 if (regs) { 11448 BCE_PRINTF( 11449 "----------------------------" 11450 " Register Dump " 11451 "----------------------------\n"); 11452 11453 for (int i = BCE_CP_CPU_MODE; i < 0x1aa000; i += 0x10) { 11454 /* Skip the big blank spaces */ 11455 if (i < 0x185400 && i > 0x19ffff) 11456 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 11457 "0x%08X 0x%08X\n", i, 11458 REG_RD_IND(sc, i), 11459 REG_RD_IND(sc, i + 0x4), 11460 REG_RD_IND(sc, i + 0x8), 11461 REG_RD_IND(sc, i + 0xC)); 11462 } 11463 } 11464 11465 BCE_PRINTF( 11466 "----------------------------" 11467 "----------------" 11468 "----------------------------\n"); 11469} 11470 11471 11472/****************************************************************************/ 11473/* Prints out the Completion Procesor (COM) state. */ 11474/* */ 11475/* Returns: */ 11476/* Nothing. */ 11477/****************************************************************************/ 11478static __attribute__ ((noinline)) void 11479bce_dump_com_state(struct bce_softc *sc, int regs) 11480{ 11481 u32 val; 11482 u32 fw_version[4]; 11483 11484 BCE_PRINTF( 11485 "----------------------------" 11486 " COM State " 11487 "----------------------------\n"); 11488 11489 for (int i = 0; i < 3; i++) 11490 fw_version[i] = htonl(REG_RD_IND(sc, 11491 (BCE_COM_SCRATCH + 0x10 + i * 4))); 11492 11493 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 11494 11495 val = REG_RD_IND(sc, BCE_COM_CPU_MODE); 11496 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_mode\n", 11497 val, BCE_COM_CPU_MODE); 11498 11499 val = REG_RD_IND(sc, BCE_COM_CPU_STATE); 11500 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n", 11501 val, BCE_COM_CPU_STATE); 11502 11503 val = REG_RD_IND(sc, BCE_COM_CPU_EVENT_MASK); 11504 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_event_mask\n", val, 11505 BCE_COM_CPU_EVENT_MASK); 11506 11507 if (regs) { 11508 BCE_PRINTF( 11509 "----------------------------" 11510 " Register Dump " 11511 "----------------------------\n"); 11512 11513 for (int i = BCE_COM_CPU_MODE; i < 0x1053e8; i += 0x10) { 11514 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 11515 "0x%08X 0x%08X\n", i, 11516 REG_RD_IND(sc, i), 11517 REG_RD_IND(sc, i + 0x4), 11518 REG_RD_IND(sc, i + 0x8), 11519 REG_RD_IND(sc, i + 0xC)); 11520 } 11521 } 11522 11523 BCE_PRINTF( 11524 "----------------------------" 11525 "----------------" 11526 "----------------------------\n"); 11527} 11528 11529 11530/****************************************************************************/ 11531/* Prints out the Receive Virtual 2 Physical (RV2P) state. */ 11532/* */ 11533/* Returns: */ 11534/* Nothing. */ 11535/****************************************************************************/ 11536static __attribute__ ((noinline)) void 11537bce_dump_rv2p_state(struct bce_softc *sc) 11538{ 11539 u32 val, pc1, pc2, fw_ver_high, fw_ver_low; 11540 11541 BCE_PRINTF( 11542 "----------------------------" 11543 " RV2P State " 11544 "----------------------------\n"); 11545 11546 /* Stall the RV2P processors. */ 11547 val = REG_RD_IND(sc, BCE_RV2P_CONFIG); 11548 val |= BCE_RV2P_CONFIG_STALL_PROC1 | BCE_RV2P_CONFIG_STALL_PROC2; 11549 REG_WR_IND(sc, BCE_RV2P_CONFIG, val); 11550 11551 /* Read the firmware version. */ 11552 val = 0x00000001; 11553 REG_WR_IND(sc, BCE_RV2P_PROC1_ADDR_CMD, val); 11554 fw_ver_low = REG_RD_IND(sc, BCE_RV2P_INSTR_LOW); 11555 fw_ver_high = REG_RD_IND(sc, BCE_RV2P_INSTR_HIGH) & 11556 BCE_RV2P_INSTR_HIGH_HIGH; 11557 BCE_PRINTF("RV2P1 Firmware version - 0x%08X:0x%08X\n", 11558 fw_ver_high, fw_ver_low); 11559 11560 val = 0x00000001; 11561 REG_WR_IND(sc, BCE_RV2P_PROC2_ADDR_CMD, val); 11562 fw_ver_low = REG_RD_IND(sc, BCE_RV2P_INSTR_LOW); 11563 fw_ver_high = REG_RD_IND(sc, BCE_RV2P_INSTR_HIGH) & 11564 BCE_RV2P_INSTR_HIGH_HIGH; 11565 BCE_PRINTF("RV2P2 Firmware version - 0x%08X:0x%08X\n", 11566 fw_ver_high, fw_ver_low); 11567 11568 /* Resume the RV2P processors. */ 11569 val = REG_RD_IND(sc, BCE_RV2P_CONFIG); 11570 val &= ~(BCE_RV2P_CONFIG_STALL_PROC1 | BCE_RV2P_CONFIG_STALL_PROC2); 11571 REG_WR_IND(sc, BCE_RV2P_CONFIG, val); 11572 11573 /* Fetch the program counter value. */ 11574 val = 0x68007800; 11575 REG_WR_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK, val); 11576 val = REG_RD_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK); 11577 pc1 = (val & BCE_RV2P_DEBUG_VECT_PEEK_1_VALUE); 11578 pc2 = (val & BCE_RV2P_DEBUG_VECT_PEEK_2_VALUE) >> 16; 11579 BCE_PRINTF("0x%08X - RV2P1 program counter (1st read)\n", pc1); 11580 BCE_PRINTF("0x%08X - RV2P2 program counter (1st read)\n", pc2); 11581 11582 /* Fetch the program counter value again to see if it is advancing. */ 11583 val = 0x68007800; 11584 REG_WR_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK, val); 11585 val = REG_RD_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK); 11586 pc1 = (val & BCE_RV2P_DEBUG_VECT_PEEK_1_VALUE); 11587 pc2 = (val & BCE_RV2P_DEBUG_VECT_PEEK_2_VALUE) >> 16; 11588 BCE_PRINTF("0x%08X - RV2P1 program counter (2nd read)\n", pc1); 11589 BCE_PRINTF("0x%08X - RV2P2 program counter (2nd read)\n", pc2); 11590 11591 BCE_PRINTF( 11592 "----------------------------" 11593 "----------------" 11594 "----------------------------\n"); 11595} 11596 11597 11598/****************************************************************************/ 11599/* Prints out the driver state and then enters the debugger. */ 11600/* */ 11601/* Returns: */ 11602/* Nothing. */ 11603/****************************************************************************/ 11604static __attribute__ ((noinline)) void 11605bce_breakpoint(struct bce_softc *sc) 11606{ 11607 11608 /* 11609 * Unreachable code to silence compiler warnings 11610 * about unused functions. 11611 */ 11612 if (0) { 11613 bce_freeze_controller(sc); 11614 bce_unfreeze_controller(sc); 11615 bce_dump_enet(sc, NULL); 11616 bce_dump_txbd(sc, 0, NULL); 11617 bce_dump_rxbd(sc, 0, NULL); 11618 bce_dump_tx_mbuf_chain(sc, 0, USABLE_TX_BD_ALLOC); 11619 bce_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD_ALLOC); 11620 bce_dump_pg_mbuf_chain(sc, 0, USABLE_PG_BD_ALLOC); 11621 bce_dump_l2fhdr(sc, 0, NULL); 11622 bce_dump_ctx(sc, RX_CID); 11623 bce_dump_ftqs(sc); 11624 bce_dump_tx_chain(sc, 0, USABLE_TX_BD_ALLOC); 11625 bce_dump_rx_bd_chain(sc, 0, USABLE_RX_BD_ALLOC); 11626 bce_dump_pg_chain(sc, 0, USABLE_PG_BD_ALLOC); 11627 bce_dump_status_block(sc); 11628 bce_dump_stats_block(sc); 11629 bce_dump_driver_state(sc); 11630 bce_dump_hw_state(sc); 11631 bce_dump_bc_state(sc); 11632 bce_dump_txp_state(sc, 0); 11633 bce_dump_rxp_state(sc, 0); 11634 bce_dump_tpat_state(sc, 0); 11635 bce_dump_cp_state(sc, 0); 11636 bce_dump_com_state(sc, 0); 11637 bce_dump_rv2p_state(sc); 11638 bce_dump_pgbd(sc, 0, NULL); 11639 } 11640 11641 bce_dump_status_block(sc); 11642 bce_dump_driver_state(sc); 11643 11644 /* Call the debugger. */ 11645 breakpoint(); 11646} 11647#endif 11648