if_bce.c revision 254516
1/*- 2 * Copyright (c) 2006-2010 Broadcom Corporation 3 * David Christensen <davidch@broadcom.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. Neither the name of Broadcom Corporation nor the name of its contributors 15 * may be used to endorse or promote products derived from this software 16 * without specific prior written consent. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 28 * THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#include <sys/cdefs.h> 32__FBSDID("$FreeBSD: head/sys/dev/bce/if_bce.c 254516 2013-08-19 10:20:20Z andre $"); 33 34/* 35 * The following controllers are supported by this driver: 36 * BCM5706C A2, A3 37 * BCM5706S A2, A3 38 * BCM5708C B1, B2 39 * BCM5708S B1, B2 40 * BCM5709C A1, C0 41 * BCM5709S A1, C0 42 * BCM5716C C0 43 * BCM5716S C0 44 * 45 * The following controllers are not supported by this driver: 46 * BCM5706C A0, A1 (pre-production) 47 * BCM5706S A0, A1 (pre-production) 48 * BCM5708C A0, B0 (pre-production) 49 * BCM5708S A0, B0 (pre-production) 50 * BCM5709C A0 B0, B1, B2 (pre-production) 51 * BCM5709S A0, B0, B1, B2 (pre-production) 52 */ 53 54#include "opt_bce.h" 55 56#include <dev/bce/if_bcereg.h> 57#include <dev/bce/if_bcefw.h> 58 59/****************************************************************************/ 60/* BCE Debug Options */ 61/****************************************************************************/ 62#ifdef BCE_DEBUG 63 u32 bce_debug = BCE_WARN; 64 65 /* 0 = Never */ 66 /* 1 = 1 in 2,147,483,648 */ 67 /* 256 = 1 in 8,388,608 */ 68 /* 2048 = 1 in 1,048,576 */ 69 /* 65536 = 1 in 32,768 */ 70 /* 1048576 = 1 in 2,048 */ 71 /* 268435456 = 1 in 8 */ 72 /* 536870912 = 1 in 4 */ 73 /* 1073741824 = 1 in 2 */ 74 75 /* Controls how often the l2_fhdr frame error check will fail. */ 76 int l2fhdr_error_sim_control = 0; 77 78 /* Controls how often the unexpected attention check will fail. */ 79 int unexpected_attention_sim_control = 0; 80 81 /* Controls how often to simulate an mbuf allocation failure. */ 82 int mbuf_alloc_failed_sim_control = 0; 83 84 /* Controls how often to simulate a DMA mapping failure. */ 85 int dma_map_addr_failed_sim_control = 0; 86 87 /* Controls how often to simulate a bootcode failure. */ 88 int bootcode_running_failure_sim_control = 0; 89#endif 90 91/****************************************************************************/ 92/* PCI Device ID Table */ 93/* */ 94/* Used by bce_probe() to identify the devices supported by this driver. */ 95/****************************************************************************/ 96#define BCE_DEVDESC_MAX 64 97 98static const struct bce_type bce_devs[] = { 99 /* BCM5706C Controllers and OEM boards. */ 100 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3101, 101 "HP NC370T Multifunction Gigabit Server Adapter" }, 102 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3106, 103 "HP NC370i Multifunction Gigabit Server Adapter" }, 104 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3070, 105 "HP NC380T PCIe DP Multifunc Gig Server Adapter" }, 106 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x1709, 107 "HP NC371i Multifunction Gigabit Server Adapter" }, 108 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, PCI_ANY_ID, PCI_ANY_ID, 109 "Broadcom NetXtreme II BCM5706 1000Base-T" }, 110 111 /* BCM5706S controllers and OEM boards. */ 112 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, HP_VENDORID, 0x3102, 113 "HP NC370F Multifunction Gigabit Server Adapter" }, 114 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, PCI_ANY_ID, PCI_ANY_ID, 115 "Broadcom NetXtreme II BCM5706 1000Base-SX" }, 116 117 /* BCM5708C controllers and OEM boards. */ 118 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7037, 119 "HP NC373T PCIe Multifunction Gig Server Adapter" }, 120 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7038, 121 "HP NC373i Multifunction Gigabit Server Adapter" }, 122 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7045, 123 "HP NC374m PCIe Multifunction Adapter" }, 124 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, PCI_ANY_ID, PCI_ANY_ID, 125 "Broadcom NetXtreme II BCM5708 1000Base-T" }, 126 127 /* BCM5708S controllers and OEM boards. */ 128 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x1706, 129 "HP NC373m Multifunction Gigabit Server Adapter" }, 130 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x703b, 131 "HP NC373i Multifunction Gigabit Server Adapter" }, 132 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x703d, 133 "HP NC373F PCIe Multifunc Giga Server Adapter" }, 134 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, PCI_ANY_ID, PCI_ANY_ID, 135 "Broadcom NetXtreme II BCM5708 1000Base-SX" }, 136 137 /* BCM5709C controllers and OEM boards. */ 138 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, HP_VENDORID, 0x7055, 139 "HP NC382i DP Multifunction Gigabit Server Adapter" }, 140 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, HP_VENDORID, 0x7059, 141 "HP NC382T PCIe DP Multifunction Gigabit Server Adapter" }, 142 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, PCI_ANY_ID, PCI_ANY_ID, 143 "Broadcom NetXtreme II BCM5709 1000Base-T" }, 144 145 /* BCM5709S controllers and OEM boards. */ 146 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, HP_VENDORID, 0x171d, 147 "HP NC382m DP 1GbE Multifunction BL-c Adapter" }, 148 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, HP_VENDORID, 0x7056, 149 "HP NC382i DP Multifunction Gigabit Server Adapter" }, 150 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, PCI_ANY_ID, PCI_ANY_ID, 151 "Broadcom NetXtreme II BCM5709 1000Base-SX" }, 152 153 /* BCM5716 controllers and OEM boards. */ 154 { BRCM_VENDORID, BRCM_DEVICEID_BCM5716, PCI_ANY_ID, PCI_ANY_ID, 155 "Broadcom NetXtreme II BCM5716 1000Base-T" }, 156 157 { 0, 0, 0, 0, NULL } 158}; 159 160 161/****************************************************************************/ 162/* Supported Flash NVRAM device data. */ 163/****************************************************************************/ 164static const struct flash_spec flash_table[] = 165{ 166#define BUFFERED_FLAGS (BCE_NV_BUFFERED | BCE_NV_TRANSLATE) 167#define NONBUFFERED_FLAGS (BCE_NV_WREN) 168 169 /* Slow EEPROM */ 170 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400, 171 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 172 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 173 "EEPROM - slow"}, 174 /* Expansion entry 0001 */ 175 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406, 176 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 177 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 178 "Entry 0001"}, 179 /* Saifun SA25F010 (non-buffered flash) */ 180 /* strap, cfg1, & write1 need updates */ 181 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406, 182 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 183 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2, 184 "Non-buffered flash (128kB)"}, 185 /* Saifun SA25F020 (non-buffered flash) */ 186 /* strap, cfg1, & write1 need updates */ 187 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406, 188 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 189 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4, 190 "Non-buffered flash (256kB)"}, 191 /* Expansion entry 0100 */ 192 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406, 193 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 194 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 195 "Entry 0100"}, 196 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */ 197 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406, 198 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 199 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2, 200 "Entry 0101: ST M45PE10 (128kB non-bufferred)"}, 201 /* Entry 0110: ST M45PE20 (non-buffered flash)*/ 202 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406, 203 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 204 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4, 205 "Entry 0110: ST M45PE20 (256kB non-bufferred)"}, 206 /* Saifun SA25F005 (non-buffered flash) */ 207 /* strap, cfg1, & write1 need updates */ 208 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406, 209 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 210 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE, 211 "Non-buffered flash (64kB)"}, 212 /* Fast EEPROM */ 213 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400, 214 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 215 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 216 "EEPROM - fast"}, 217 /* Expansion entry 1001 */ 218 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406, 219 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 220 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 221 "Entry 1001"}, 222 /* Expansion entry 1010 */ 223 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406, 224 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 225 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 226 "Entry 1010"}, 227 /* ATMEL AT45DB011B (buffered flash) */ 228 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400, 229 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 230 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE, 231 "Buffered flash (128kB)"}, 232 /* Expansion entry 1100 */ 233 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406, 234 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 235 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 236 "Entry 1100"}, 237 /* Expansion entry 1101 */ 238 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406, 239 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 240 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 241 "Entry 1101"}, 242 /* Ateml Expansion entry 1110 */ 243 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400, 244 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 245 BUFFERED_FLASH_BYTE_ADDR_MASK, 0, 246 "Entry 1110 (Atmel)"}, 247 /* ATMEL AT45DB021B (buffered flash) */ 248 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400, 249 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 250 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2, 251 "Buffered flash (256kB)"}, 252}; 253 254/* 255 * The BCM5709 controllers transparently handle the 256 * differences between Atmel 264 byte pages and all 257 * flash devices which use 256 byte pages, so no 258 * logical-to-physical mapping is required in the 259 * driver. 260 */ 261static const struct flash_spec flash_5709 = { 262 .flags = BCE_NV_BUFFERED, 263 .page_bits = BCM5709_FLASH_PAGE_BITS, 264 .page_size = BCM5709_FLASH_PAGE_SIZE, 265 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK, 266 .total_size = BUFFERED_FLASH_TOTAL_SIZE * 2, 267 .name = "5709/5716 buffered flash (256kB)", 268}; 269 270 271/****************************************************************************/ 272/* FreeBSD device entry points. */ 273/****************************************************************************/ 274static int bce_probe (device_t); 275static int bce_attach (device_t); 276static int bce_detach (device_t); 277static int bce_shutdown (device_t); 278 279 280/****************************************************************************/ 281/* BCE Debug Data Structure Dump Routines */ 282/****************************************************************************/ 283#ifdef BCE_DEBUG 284static u32 bce_reg_rd (struct bce_softc *, u32); 285static void bce_reg_wr (struct bce_softc *, u32, u32); 286static void bce_reg_wr16 (struct bce_softc *, u32, u16); 287static u32 bce_ctx_rd (struct bce_softc *, u32, u32); 288static void bce_dump_enet (struct bce_softc *, struct mbuf *); 289static void bce_dump_mbuf (struct bce_softc *, struct mbuf *); 290static void bce_dump_tx_mbuf_chain (struct bce_softc *, u16, int); 291static void bce_dump_rx_mbuf_chain (struct bce_softc *, u16, int); 292static void bce_dump_pg_mbuf_chain (struct bce_softc *, u16, int); 293static void bce_dump_txbd (struct bce_softc *, 294 int, struct tx_bd *); 295static void bce_dump_rxbd (struct bce_softc *, 296 int, struct rx_bd *); 297static void bce_dump_pgbd (struct bce_softc *, 298 int, struct rx_bd *); 299static void bce_dump_l2fhdr (struct bce_softc *, 300 int, struct l2_fhdr *); 301static void bce_dump_ctx (struct bce_softc *, u16); 302static void bce_dump_ftqs (struct bce_softc *); 303static void bce_dump_tx_chain (struct bce_softc *, u16, int); 304static void bce_dump_rx_bd_chain (struct bce_softc *, u16, int); 305static void bce_dump_pg_chain (struct bce_softc *, u16, int); 306static void bce_dump_status_block (struct bce_softc *); 307static void bce_dump_stats_block (struct bce_softc *); 308static void bce_dump_driver_state (struct bce_softc *); 309static void bce_dump_hw_state (struct bce_softc *); 310static void bce_dump_shmem_state (struct bce_softc *); 311static void bce_dump_mq_regs (struct bce_softc *); 312static void bce_dump_bc_state (struct bce_softc *); 313static void bce_dump_txp_state (struct bce_softc *, int); 314static void bce_dump_rxp_state (struct bce_softc *, int); 315static void bce_dump_tpat_state (struct bce_softc *, int); 316static void bce_dump_cp_state (struct bce_softc *, int); 317static void bce_dump_com_state (struct bce_softc *, int); 318static void bce_dump_rv2p_state (struct bce_softc *); 319static void bce_breakpoint (struct bce_softc *); 320#endif /*BCE_DEBUG */ 321 322 323/****************************************************************************/ 324/* BCE Register/Memory Access Routines */ 325/****************************************************************************/ 326static u32 bce_reg_rd_ind (struct bce_softc *, u32); 327static void bce_reg_wr_ind (struct bce_softc *, u32, u32); 328static void bce_shmem_wr (struct bce_softc *, u32, u32); 329static u32 bce_shmem_rd (struct bce_softc *, u32); 330static void bce_ctx_wr (struct bce_softc *, u32, u32, u32); 331static int bce_miibus_read_reg (device_t, int, int); 332static int bce_miibus_write_reg (device_t, int, int, int); 333static void bce_miibus_statchg (device_t); 334 335#ifdef BCE_DEBUG 336static int bce_sysctl_nvram_dump(SYSCTL_HANDLER_ARGS); 337#ifdef BCE_NVRAM_WRITE_SUPPORT 338static int bce_sysctl_nvram_write(SYSCTL_HANDLER_ARGS); 339#endif 340#endif 341 342/****************************************************************************/ 343/* BCE NVRAM Access Routines */ 344/****************************************************************************/ 345static int bce_acquire_nvram_lock (struct bce_softc *); 346static int bce_release_nvram_lock (struct bce_softc *); 347static void bce_enable_nvram_access(struct bce_softc *); 348static void bce_disable_nvram_access(struct bce_softc *); 349static int bce_nvram_read_dword (struct bce_softc *, u32, u8 *, u32); 350static int bce_init_nvram (struct bce_softc *); 351static int bce_nvram_read (struct bce_softc *, u32, u8 *, int); 352static int bce_nvram_test (struct bce_softc *); 353#ifdef BCE_NVRAM_WRITE_SUPPORT 354static int bce_enable_nvram_write (struct bce_softc *); 355static void bce_disable_nvram_write(struct bce_softc *); 356static int bce_nvram_erase_page (struct bce_softc *, u32); 357static int bce_nvram_write_dword (struct bce_softc *, u32, u8 *, u32); 358static int bce_nvram_write (struct bce_softc *, u32, u8 *, int); 359#endif 360 361/****************************************************************************/ 362/* */ 363/****************************************************************************/ 364static void bce_get_rx_buffer_sizes(struct bce_softc *, int); 365static void bce_get_media (struct bce_softc *); 366static void bce_init_media (struct bce_softc *); 367static u32 bce_get_rphy_link (struct bce_softc *); 368static void bce_dma_map_addr (void *, bus_dma_segment_t *, int, int); 369static int bce_dma_alloc (device_t); 370static void bce_dma_free (struct bce_softc *); 371static void bce_release_resources (struct bce_softc *); 372 373/****************************************************************************/ 374/* BCE Firmware Synchronization and Load */ 375/****************************************************************************/ 376static void bce_fw_cap_init (struct bce_softc *); 377static int bce_fw_sync (struct bce_softc *, u32); 378static void bce_load_rv2p_fw (struct bce_softc *, const u32 *, u32, 379 u32); 380static void bce_load_cpu_fw (struct bce_softc *, 381 struct cpu_reg *, struct fw_info *); 382static void bce_start_cpu (struct bce_softc *, struct cpu_reg *); 383static void bce_halt_cpu (struct bce_softc *, struct cpu_reg *); 384static void bce_start_rxp_cpu (struct bce_softc *); 385static void bce_init_rxp_cpu (struct bce_softc *); 386static void bce_init_txp_cpu (struct bce_softc *); 387static void bce_init_tpat_cpu (struct bce_softc *); 388static void bce_init_cp_cpu (struct bce_softc *); 389static void bce_init_com_cpu (struct bce_softc *); 390static void bce_init_cpus (struct bce_softc *); 391 392static void bce_print_adapter_info (struct bce_softc *); 393static void bce_probe_pci_caps (device_t, struct bce_softc *); 394static void bce_stop (struct bce_softc *); 395static int bce_reset (struct bce_softc *, u32); 396static int bce_chipinit (struct bce_softc *); 397static int bce_blockinit (struct bce_softc *); 398 399static int bce_init_tx_chain (struct bce_softc *); 400static void bce_free_tx_chain (struct bce_softc *); 401 402static int bce_get_rx_buf (struct bce_softc *, u16, u16, u32 *); 403static int bce_init_rx_chain (struct bce_softc *); 404static void bce_fill_rx_chain (struct bce_softc *); 405static void bce_free_rx_chain (struct bce_softc *); 406 407static int bce_get_pg_buf (struct bce_softc *, u16, u16); 408static int bce_init_pg_chain (struct bce_softc *); 409static void bce_fill_pg_chain (struct bce_softc *); 410static void bce_free_pg_chain (struct bce_softc *); 411 412static struct mbuf *bce_tso_setup (struct bce_softc *, 413 struct mbuf **, u16 *); 414static int bce_tx_encap (struct bce_softc *, struct mbuf **); 415static void bce_start_locked (struct ifnet *); 416static void bce_start (struct ifnet *); 417static int bce_ioctl (struct ifnet *, u_long, caddr_t); 418static void bce_watchdog (struct bce_softc *); 419static int bce_ifmedia_upd (struct ifnet *); 420static int bce_ifmedia_upd_locked (struct ifnet *); 421static void bce_ifmedia_sts (struct ifnet *, struct ifmediareq *); 422static void bce_ifmedia_sts_rphy (struct bce_softc *, struct ifmediareq *); 423static void bce_init_locked (struct bce_softc *); 424static void bce_init (void *); 425static void bce_mgmt_init_locked (struct bce_softc *sc); 426 427static int bce_init_ctx (struct bce_softc *); 428static void bce_get_mac_addr (struct bce_softc *); 429static void bce_set_mac_addr (struct bce_softc *); 430static void bce_phy_intr (struct bce_softc *); 431static inline u16 bce_get_hw_rx_cons (struct bce_softc *); 432static void bce_rx_intr (struct bce_softc *); 433static void bce_tx_intr (struct bce_softc *); 434static void bce_disable_intr (struct bce_softc *); 435static void bce_enable_intr (struct bce_softc *, int); 436 437static void bce_intr (void *); 438static void bce_set_rx_mode (struct bce_softc *); 439static void bce_stats_update (struct bce_softc *); 440static void bce_tick (void *); 441static void bce_pulse (void *); 442static void bce_add_sysctls (struct bce_softc *); 443 444 445/****************************************************************************/ 446/* FreeBSD device dispatch table. */ 447/****************************************************************************/ 448static device_method_t bce_methods[] = { 449 /* Device interface (device_if.h) */ 450 DEVMETHOD(device_probe, bce_probe), 451 DEVMETHOD(device_attach, bce_attach), 452 DEVMETHOD(device_detach, bce_detach), 453 DEVMETHOD(device_shutdown, bce_shutdown), 454/* Supported by device interface but not used here. */ 455/* DEVMETHOD(device_identify, bce_identify), */ 456/* DEVMETHOD(device_suspend, bce_suspend), */ 457/* DEVMETHOD(device_resume, bce_resume), */ 458/* DEVMETHOD(device_quiesce, bce_quiesce), */ 459 460 /* MII interface (miibus_if.h) */ 461 DEVMETHOD(miibus_readreg, bce_miibus_read_reg), 462 DEVMETHOD(miibus_writereg, bce_miibus_write_reg), 463 DEVMETHOD(miibus_statchg, bce_miibus_statchg), 464/* Supported by MII interface but not used here. */ 465/* DEVMETHOD(miibus_linkchg, bce_miibus_linkchg), */ 466/* DEVMETHOD(miibus_mediainit, bce_miibus_mediainit), */ 467 468 DEVMETHOD_END 469}; 470 471static driver_t bce_driver = { 472 "bce", 473 bce_methods, 474 sizeof(struct bce_softc) 475}; 476 477static devclass_t bce_devclass; 478 479MODULE_DEPEND(bce, pci, 1, 1, 1); 480MODULE_DEPEND(bce, ether, 1, 1, 1); 481MODULE_DEPEND(bce, miibus, 1, 1, 1); 482 483DRIVER_MODULE(bce, pci, bce_driver, bce_devclass, NULL, NULL); 484DRIVER_MODULE(miibus, bce, miibus_driver, miibus_devclass, NULL, NULL); 485 486 487/****************************************************************************/ 488/* Tunable device values */ 489/****************************************************************************/ 490static SYSCTL_NODE(_hw, OID_AUTO, bce, CTLFLAG_RD, 0, "bce driver parameters"); 491 492/* Allowable values are TRUE or FALSE */ 493static int bce_verbose = TRUE; 494TUNABLE_INT("hw.bce.verbose", &bce_verbose); 495SYSCTL_INT(_hw_bce, OID_AUTO, verbose, CTLFLAG_RDTUN, &bce_verbose, 0, 496 "Verbose output enable/disable"); 497 498/* Allowable values are TRUE or FALSE */ 499static int bce_tso_enable = TRUE; 500TUNABLE_INT("hw.bce.tso_enable", &bce_tso_enable); 501SYSCTL_INT(_hw_bce, OID_AUTO, tso_enable, CTLFLAG_RDTUN, &bce_tso_enable, 0, 502 "TSO Enable/Disable"); 503 504/* Allowable values are 0 (IRQ), 1 (MSI/IRQ), and 2 (MSI-X/MSI/IRQ) */ 505/* ToDo: Add MSI-X support. */ 506static int bce_msi_enable = 1; 507TUNABLE_INT("hw.bce.msi_enable", &bce_msi_enable); 508SYSCTL_INT(_hw_bce, OID_AUTO, msi_enable, CTLFLAG_RDTUN, &bce_msi_enable, 0, 509 "MSI-X|MSI|INTx selector"); 510 511/* Allowable values are 1, 2, 4, 8. */ 512static int bce_rx_pages = DEFAULT_RX_PAGES; 513TUNABLE_INT("hw.bce.rx_pages", &bce_rx_pages); 514SYSCTL_UINT(_hw_bce, OID_AUTO, rx_pages, CTLFLAG_RDTUN, &bce_rx_pages, 0, 515 "Receive buffer descriptor pages (1 page = 255 buffer descriptors)"); 516 517/* Allowable values are 1, 2, 4, 8. */ 518static int bce_tx_pages = DEFAULT_TX_PAGES; 519TUNABLE_INT("hw.bce.tx_pages", &bce_tx_pages); 520SYSCTL_UINT(_hw_bce, OID_AUTO, tx_pages, CTLFLAG_RDTUN, &bce_tx_pages, 0, 521 "Transmit buffer descriptor pages (1 page = 255 buffer descriptors)"); 522 523/* Allowable values are TRUE or FALSE. */ 524static int bce_hdr_split = TRUE; 525TUNABLE_INT("hw.bce.hdr_split", &bce_hdr_split); 526SYSCTL_UINT(_hw_bce, OID_AUTO, hdr_split, CTLFLAG_RDTUN, &bce_hdr_split, 0, 527 "Frame header/payload splitting Enable/Disable"); 528 529/* Allowable values are TRUE or FALSE. */ 530static int bce_strict_rx_mtu = FALSE; 531TUNABLE_INT("hw.bce.strict_rx_mtu", &bce_strict_rx_mtu); 532SYSCTL_UINT(_hw_bce, OID_AUTO, strict_rx_mtu, CTLFLAG_RDTUN, 533 &bce_strict_rx_mtu, 0, 534 "Enable/Disable strict RX frame size checking"); 535 536/* Allowable values are 0 ... 100 */ 537#ifdef BCE_DEBUG 538/* Generate 1 interrupt for every transmit completion. */ 539static int bce_tx_quick_cons_trip_int = 1; 540#else 541/* Generate 1 interrupt for every 20 transmit completions. */ 542static int bce_tx_quick_cons_trip_int = DEFAULT_TX_QUICK_CONS_TRIP_INT; 543#endif 544TUNABLE_INT("hw.bce.tx_quick_cons_trip_int", &bce_tx_quick_cons_trip_int); 545SYSCTL_UINT(_hw_bce, OID_AUTO, tx_quick_cons_trip_int, CTLFLAG_RDTUN, 546 &bce_tx_quick_cons_trip_int, 0, 547 "Transmit BD trip point during interrupts"); 548 549/* Allowable values are 0 ... 100 */ 550/* Generate 1 interrupt for every transmit completion. */ 551#ifdef BCE_DEBUG 552static int bce_tx_quick_cons_trip = 1; 553#else 554/* Generate 1 interrupt for every 20 transmit completions. */ 555static int bce_tx_quick_cons_trip = DEFAULT_TX_QUICK_CONS_TRIP; 556#endif 557TUNABLE_INT("hw.bce.tx_quick_cons_trip", &bce_tx_quick_cons_trip); 558SYSCTL_UINT(_hw_bce, OID_AUTO, tx_quick_cons_trip, CTLFLAG_RDTUN, 559 &bce_tx_quick_cons_trip, 0, 560 "Transmit BD trip point"); 561 562/* Allowable values are 0 ... 100 */ 563#ifdef BCE_DEBUG 564/* Generate an interrupt if 0us have elapsed since the last TX completion. */ 565static int bce_tx_ticks_int = 0; 566#else 567/* Generate an interrupt if 80us have elapsed since the last TX completion. */ 568static int bce_tx_ticks_int = DEFAULT_TX_TICKS_INT; 569#endif 570TUNABLE_INT("hw.bce.tx_ticks_int", &bce_tx_ticks_int); 571SYSCTL_UINT(_hw_bce, OID_AUTO, tx_ticks_int, CTLFLAG_RDTUN, 572 &bce_tx_ticks_int, 0, "Transmit ticks count during interrupt"); 573 574/* Allowable values are 0 ... 100 */ 575#ifdef BCE_DEBUG 576/* Generate an interrupt if 0us have elapsed since the last TX completion. */ 577static int bce_tx_ticks = 0; 578#else 579/* Generate an interrupt if 80us have elapsed since the last TX completion. */ 580static int bce_tx_ticks = DEFAULT_TX_TICKS; 581#endif 582TUNABLE_INT("hw.bce.tx_ticks", &bce_tx_ticks); 583SYSCTL_UINT(_hw_bce, OID_AUTO, tx_ticks, CTLFLAG_RDTUN, 584 &bce_tx_ticks, 0, "Transmit ticks count"); 585 586/* Allowable values are 1 ... 100 */ 587#ifdef BCE_DEBUG 588/* Generate 1 interrupt for every received frame. */ 589static int bce_rx_quick_cons_trip_int = 1; 590#else 591/* Generate 1 interrupt for every 6 received frames. */ 592static int bce_rx_quick_cons_trip_int = DEFAULT_RX_QUICK_CONS_TRIP_INT; 593#endif 594TUNABLE_INT("hw.bce.rx_quick_cons_trip_int", &bce_rx_quick_cons_trip_int); 595SYSCTL_UINT(_hw_bce, OID_AUTO, rx_quick_cons_trip_int, CTLFLAG_RDTUN, 596 &bce_rx_quick_cons_trip_int, 0, 597 "Receive BD trip point duirng interrupts"); 598 599/* Allowable values are 1 ... 100 */ 600#ifdef BCE_DEBUG 601/* Generate 1 interrupt for every received frame. */ 602static int bce_rx_quick_cons_trip = 1; 603#else 604/* Generate 1 interrupt for every 6 received frames. */ 605static int bce_rx_quick_cons_trip = DEFAULT_RX_QUICK_CONS_TRIP; 606#endif 607TUNABLE_INT("hw.bce.rx_quick_cons_trip", &bce_rx_quick_cons_trip); 608SYSCTL_UINT(_hw_bce, OID_AUTO, rx_quick_cons_trip, CTLFLAG_RDTUN, 609 &bce_rx_quick_cons_trip, 0, 610 "Receive BD trip point"); 611 612/* Allowable values are 0 ... 100 */ 613#ifdef BCE_DEBUG 614/* Generate an int. if 0us have elapsed since the last received frame. */ 615static int bce_rx_ticks_int = 0; 616#else 617/* Generate an int. if 18us have elapsed since the last received frame. */ 618static int bce_rx_ticks_int = DEFAULT_RX_TICKS_INT; 619#endif 620TUNABLE_INT("hw.bce.rx_ticks_int", &bce_rx_ticks_int); 621SYSCTL_UINT(_hw_bce, OID_AUTO, rx_ticks_int, CTLFLAG_RDTUN, 622 &bce_rx_ticks_int, 0, "Receive ticks count during interrupt"); 623 624/* Allowable values are 0 ... 100 */ 625#ifdef BCE_DEBUG 626/* Generate an int. if 0us have elapsed since the last received frame. */ 627static int bce_rx_ticks = 0; 628#else 629/* Generate an int. if 18us have elapsed since the last received frame. */ 630static int bce_rx_ticks = DEFAULT_RX_TICKS; 631#endif 632TUNABLE_INT("hw.bce.rx_ticks", &bce_rx_ticks); 633SYSCTL_UINT(_hw_bce, OID_AUTO, rx_ticks, CTLFLAG_RDTUN, 634 &bce_rx_ticks, 0, "Receive ticks count"); 635 636 637/****************************************************************************/ 638/* Device probe function. */ 639/* */ 640/* Compares the device to the driver's list of supported devices and */ 641/* reports back to the OS whether this is the right driver for the device. */ 642/* */ 643/* Returns: */ 644/* BUS_PROBE_DEFAULT on success, positive value on failure. */ 645/****************************************************************************/ 646static int 647bce_probe(device_t dev) 648{ 649 const struct bce_type *t; 650 struct bce_softc *sc; 651 char *descbuf; 652 u16 vid = 0, did = 0, svid = 0, sdid = 0; 653 654 t = bce_devs; 655 656 sc = device_get_softc(dev); 657 sc->bce_unit = device_get_unit(dev); 658 sc->bce_dev = dev; 659 660 /* Get the data for the device to be probed. */ 661 vid = pci_get_vendor(dev); 662 did = pci_get_device(dev); 663 svid = pci_get_subvendor(dev); 664 sdid = pci_get_subdevice(dev); 665 666 DBPRINT(sc, BCE_EXTREME_LOAD, 667 "%s(); VID = 0x%04X, DID = 0x%04X, SVID = 0x%04X, " 668 "SDID = 0x%04X\n", __FUNCTION__, vid, did, svid, sdid); 669 670 /* Look through the list of known devices for a match. */ 671 while(t->bce_name != NULL) { 672 673 if ((vid == t->bce_vid) && (did == t->bce_did) && 674 ((svid == t->bce_svid) || (t->bce_svid == PCI_ANY_ID)) && 675 ((sdid == t->bce_sdid) || (t->bce_sdid == PCI_ANY_ID))) { 676 677 descbuf = malloc(BCE_DEVDESC_MAX, M_TEMP, M_NOWAIT); 678 679 if (descbuf == NULL) 680 return(ENOMEM); 681 682 /* Print out the device identity. */ 683 snprintf(descbuf, BCE_DEVDESC_MAX, "%s (%c%d)", 684 t->bce_name, (((pci_read_config(dev, 685 PCIR_REVID, 4) & 0xf0) >> 4) + 'A'), 686 (pci_read_config(dev, PCIR_REVID, 4) & 0xf)); 687 688 device_set_desc_copy(dev, descbuf); 689 free(descbuf, M_TEMP); 690 return(BUS_PROBE_DEFAULT); 691 } 692 t++; 693 } 694 695 return(ENXIO); 696} 697 698 699/****************************************************************************/ 700/* PCI Capabilities Probe Function. */ 701/* */ 702/* Walks the PCI capabiites list for the device to find what features are */ 703/* supported. */ 704/* */ 705/* Returns: */ 706/* None. */ 707/****************************************************************************/ 708static void 709bce_print_adapter_info(struct bce_softc *sc) 710{ 711 int i = 0; 712 713 DBENTER(BCE_VERBOSE_LOAD); 714 715 if (bce_verbose || bootverbose) { 716 BCE_PRINTF("ASIC (0x%08X); ", sc->bce_chipid); 717 printf("Rev (%c%d); ", ((BCE_CHIP_ID(sc) & 0xf000) >> 718 12) + 'A', ((BCE_CHIP_ID(sc) & 0x0ff0) >> 4)); 719 720 721 /* Bus info. */ 722 if (sc->bce_flags & BCE_PCIE_FLAG) { 723 printf("Bus (PCIe x%d, ", sc->link_width); 724 switch (sc->link_speed) { 725 case 1: printf("2.5Gbps); "); break; 726 case 2: printf("5Gbps); "); break; 727 default: printf("Unknown link speed); "); 728 } 729 } else { 730 printf("Bus (PCI%s, %s, %dMHz); ", 731 ((sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : ""), 732 ((sc->bce_flags & BCE_PCI_32BIT_FLAG) ? 733 "32-bit" : "64-bit"), sc->bus_speed_mhz); 734 } 735 736 /* Firmware version and device features. */ 737 printf("B/C (%s); Bufs (RX:%d;TX:%d;PG:%d); Flags (", 738 sc->bce_bc_ver, sc->rx_pages, sc->tx_pages, 739 (bce_hdr_split == TRUE ? sc->pg_pages: 0)); 740 741 if (bce_hdr_split == TRUE) { 742 printf("SPLT"); 743 i++; 744 } 745 746 if (sc->bce_flags & BCE_USING_MSI_FLAG) { 747 if (i > 0) printf("|"); 748 printf("MSI"); i++; 749 } 750 751 if (sc->bce_flags & BCE_USING_MSIX_FLAG) { 752 if (i > 0) printf("|"); 753 printf("MSI-X"); i++; 754 } 755 756 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) { 757 if (i > 0) printf("|"); 758 printf("2.5G"); i++; 759 } 760 761 if (sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) { 762 if (i > 0) printf("|"); 763 printf("Remote PHY(%s)", 764 sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG ? 765 "FIBER" : "TP"); i++; 766 } 767 768 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 769 if (i > 0) printf("|"); 770 printf("MFW); MFW (%s)\n", sc->bce_mfw_ver); 771 } else { 772 printf(")\n"); 773 } 774 775 printf("Coal (RX:%d,%d,%d,%d; TX:%d,%d,%d,%d)\n", 776 sc->bce_rx_quick_cons_trip_int, 777 sc->bce_rx_quick_cons_trip, 778 sc->bce_rx_ticks_int, 779 sc->bce_rx_ticks, 780 sc->bce_tx_quick_cons_trip_int, 781 sc->bce_tx_quick_cons_trip, 782 sc->bce_tx_ticks_int, 783 sc->bce_tx_ticks); 784 785 } 786 787 DBEXIT(BCE_VERBOSE_LOAD); 788} 789 790 791/****************************************************************************/ 792/* PCI Capabilities Probe Function. */ 793/* */ 794/* Walks the PCI capabiites list for the device to find what features are */ 795/* supported. */ 796/* */ 797/* Returns: */ 798/* None. */ 799/****************************************************************************/ 800static void 801bce_probe_pci_caps(device_t dev, struct bce_softc *sc) 802{ 803 u32 reg; 804 805 DBENTER(BCE_VERBOSE_LOAD); 806 807 /* Check if PCI-X capability is enabled. */ 808 if (pci_find_cap(dev, PCIY_PCIX, ®) == 0) { 809 if (reg != 0) 810 sc->bce_cap_flags |= BCE_PCIX_CAPABLE_FLAG; 811 } 812 813 /* Check if PCIe capability is enabled. */ 814 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) { 815 if (reg != 0) { 816 u16 link_status = pci_read_config(dev, reg + 0x12, 2); 817 DBPRINT(sc, BCE_INFO_LOAD, "PCIe link_status = " 818 "0x%08X\n", link_status); 819 sc->link_speed = link_status & 0xf; 820 sc->link_width = (link_status >> 4) & 0x3f; 821 sc->bce_cap_flags |= BCE_PCIE_CAPABLE_FLAG; 822 sc->bce_flags |= BCE_PCIE_FLAG; 823 } 824 } 825 826 /* Check if MSI capability is enabled. */ 827 if (pci_find_cap(dev, PCIY_MSI, ®) == 0) { 828 if (reg != 0) 829 sc->bce_cap_flags |= BCE_MSI_CAPABLE_FLAG; 830 } 831 832 /* Check if MSI-X capability is enabled. */ 833 if (pci_find_cap(dev, PCIY_MSIX, ®) == 0) { 834 if (reg != 0) 835 sc->bce_cap_flags |= BCE_MSIX_CAPABLE_FLAG; 836 } 837 838 DBEXIT(BCE_VERBOSE_LOAD); 839} 840 841 842/****************************************************************************/ 843/* Load and validate user tunable settings. */ 844/* */ 845/* Returns: */ 846/* Nothing. */ 847/****************************************************************************/ 848static void 849bce_set_tunables(struct bce_softc *sc) 850{ 851 /* Set sysctl values for RX page count. */ 852 switch (bce_rx_pages) { 853 case 1: 854 /* fall-through */ 855 case 2: 856 /* fall-through */ 857 case 4: 858 /* fall-through */ 859 case 8: 860 sc->rx_pages = bce_rx_pages; 861 break; 862 default: 863 sc->rx_pages = DEFAULT_RX_PAGES; 864 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 865 "hw.bce.rx_pages! Setting default of %d.\n", 866 __FILE__, __LINE__, bce_rx_pages, DEFAULT_RX_PAGES); 867 } 868 869 /* ToDo: Consider allowing user setting for pg_pages. */ 870 sc->pg_pages = min((sc->rx_pages * 4), MAX_PG_PAGES); 871 872 /* Set sysctl values for TX page count. */ 873 switch (bce_tx_pages) { 874 case 1: 875 /* fall-through */ 876 case 2: 877 /* fall-through */ 878 case 4: 879 /* fall-through */ 880 case 8: 881 sc->tx_pages = bce_tx_pages; 882 break; 883 default: 884 sc->tx_pages = DEFAULT_TX_PAGES; 885 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 886 "hw.bce.tx_pages! Setting default of %d.\n", 887 __FILE__, __LINE__, bce_tx_pages, DEFAULT_TX_PAGES); 888 } 889 890 /* 891 * Validate the TX trip point (i.e. the number of 892 * TX completions before a status block update is 893 * generated and an interrupt is asserted. 894 */ 895 if (bce_tx_quick_cons_trip_int <= 100) { 896 sc->bce_tx_quick_cons_trip_int = 897 bce_tx_quick_cons_trip_int; 898 } else { 899 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 900 "hw.bce.tx_quick_cons_trip_int! Setting default of %d.\n", 901 __FILE__, __LINE__, bce_tx_quick_cons_trip_int, 902 DEFAULT_TX_QUICK_CONS_TRIP_INT); 903 sc->bce_tx_quick_cons_trip_int = 904 DEFAULT_TX_QUICK_CONS_TRIP_INT; 905 } 906 907 if (bce_tx_quick_cons_trip <= 100) { 908 sc->bce_tx_quick_cons_trip = 909 bce_tx_quick_cons_trip; 910 } else { 911 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 912 "hw.bce.tx_quick_cons_trip! Setting default of %d.\n", 913 __FILE__, __LINE__, bce_tx_quick_cons_trip, 914 DEFAULT_TX_QUICK_CONS_TRIP); 915 sc->bce_tx_quick_cons_trip = 916 DEFAULT_TX_QUICK_CONS_TRIP; 917 } 918 919 /* 920 * Validate the TX ticks count (i.e. the maximum amount 921 * of time to wait after the last TX completion has 922 * occurred before a status block update is generated 923 * and an interrupt is asserted. 924 */ 925 if (bce_tx_ticks_int <= 100) { 926 sc->bce_tx_ticks_int = 927 bce_tx_ticks_int; 928 } else { 929 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 930 "hw.bce.tx_ticks_int! Setting default of %d.\n", 931 __FILE__, __LINE__, bce_tx_ticks_int, 932 DEFAULT_TX_TICKS_INT); 933 sc->bce_tx_ticks_int = 934 DEFAULT_TX_TICKS_INT; 935 } 936 937 if (bce_tx_ticks <= 100) { 938 sc->bce_tx_ticks = 939 bce_tx_ticks; 940 } else { 941 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 942 "hw.bce.tx_ticks! Setting default of %d.\n", 943 __FILE__, __LINE__, bce_tx_ticks, 944 DEFAULT_TX_TICKS); 945 sc->bce_tx_ticks = 946 DEFAULT_TX_TICKS; 947 } 948 949 /* 950 * Validate the RX trip point (i.e. the number of 951 * RX frames received before a status block update is 952 * generated and an interrupt is asserted. 953 */ 954 if (bce_rx_quick_cons_trip_int <= 100) { 955 sc->bce_rx_quick_cons_trip_int = 956 bce_rx_quick_cons_trip_int; 957 } else { 958 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 959 "hw.bce.rx_quick_cons_trip_int! Setting default of %d.\n", 960 __FILE__, __LINE__, bce_rx_quick_cons_trip_int, 961 DEFAULT_RX_QUICK_CONS_TRIP_INT); 962 sc->bce_rx_quick_cons_trip_int = 963 DEFAULT_RX_QUICK_CONS_TRIP_INT; 964 } 965 966 if (bce_rx_quick_cons_trip <= 100) { 967 sc->bce_rx_quick_cons_trip = 968 bce_rx_quick_cons_trip; 969 } else { 970 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 971 "hw.bce.rx_quick_cons_trip! Setting default of %d.\n", 972 __FILE__, __LINE__, bce_rx_quick_cons_trip, 973 DEFAULT_RX_QUICK_CONS_TRIP); 974 sc->bce_rx_quick_cons_trip = 975 DEFAULT_RX_QUICK_CONS_TRIP; 976 } 977 978 /* 979 * Validate the RX ticks count (i.e. the maximum amount 980 * of time to wait after the last RX frame has been 981 * received before a status block update is generated 982 * and an interrupt is asserted. 983 */ 984 if (bce_rx_ticks_int <= 100) { 985 sc->bce_rx_ticks_int = bce_rx_ticks_int; 986 } else { 987 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 988 "hw.bce.rx_ticks_int! Setting default of %d.\n", 989 __FILE__, __LINE__, bce_rx_ticks_int, 990 DEFAULT_RX_TICKS_INT); 991 sc->bce_rx_ticks_int = DEFAULT_RX_TICKS_INT; 992 } 993 994 if (bce_rx_ticks <= 100) { 995 sc->bce_rx_ticks = bce_rx_ticks; 996 } else { 997 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 998 "hw.bce.rx_ticks! Setting default of %d.\n", 999 __FILE__, __LINE__, bce_rx_ticks, 1000 DEFAULT_RX_TICKS); 1001 sc->bce_rx_ticks = DEFAULT_RX_TICKS; 1002 } 1003 1004 /* Disabling both RX ticks and RX trips will prevent interrupts. */ 1005 if ((bce_rx_quick_cons_trip == 0) && (bce_rx_ticks == 0)) { 1006 BCE_PRINTF("%s(%d): Cannot set both hw.bce.rx_ticks and " 1007 "hw.bce.rx_quick_cons_trip to 0. Setting default values.\n", 1008 __FILE__, __LINE__); 1009 sc->bce_rx_ticks = DEFAULT_RX_TICKS; 1010 sc->bce_rx_quick_cons_trip = DEFAULT_RX_QUICK_CONS_TRIP; 1011 } 1012 1013 /* Disabling both TX ticks and TX trips will prevent interrupts. */ 1014 if ((bce_tx_quick_cons_trip == 0) && (bce_tx_ticks == 0)) { 1015 BCE_PRINTF("%s(%d): Cannot set both hw.bce.tx_ticks and " 1016 "hw.bce.tx_quick_cons_trip to 0. Setting default values.\n", 1017 __FILE__, __LINE__); 1018 sc->bce_tx_ticks = DEFAULT_TX_TICKS; 1019 sc->bce_tx_quick_cons_trip = DEFAULT_TX_QUICK_CONS_TRIP; 1020 } 1021} 1022 1023 1024/****************************************************************************/ 1025/* Device attach function. */ 1026/* */ 1027/* Allocates device resources, performs secondary chip identification, */ 1028/* resets and initializes the hardware, and initializes driver instance */ 1029/* variables. */ 1030/* */ 1031/* Returns: */ 1032/* 0 on success, positive value on failure. */ 1033/****************************************************************************/ 1034static int 1035bce_attach(device_t dev) 1036{ 1037 struct bce_softc *sc; 1038 struct ifnet *ifp; 1039 u32 val; 1040 int count, error, rc = 0, rid; 1041 1042 sc = device_get_softc(dev); 1043 sc->bce_dev = dev; 1044 1045 DBENTER(BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 1046 1047 sc->bce_unit = device_get_unit(dev); 1048 1049 /* Set initial device and PHY flags */ 1050 sc->bce_flags = 0; 1051 sc->bce_phy_flags = 0; 1052 1053 bce_set_tunables(sc); 1054 1055 pci_enable_busmaster(dev); 1056 1057 /* Allocate PCI memory resources. */ 1058 rid = PCIR_BAR(0); 1059 sc->bce_res_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1060 &rid, RF_ACTIVE); 1061 1062 if (sc->bce_res_mem == NULL) { 1063 BCE_PRINTF("%s(%d): PCI memory allocation failed\n", 1064 __FILE__, __LINE__); 1065 rc = ENXIO; 1066 goto bce_attach_fail; 1067 } 1068 1069 /* Get various resource handles. */ 1070 sc->bce_btag = rman_get_bustag(sc->bce_res_mem); 1071 sc->bce_bhandle = rman_get_bushandle(sc->bce_res_mem); 1072 sc->bce_vhandle = (vm_offset_t) rman_get_virtual(sc->bce_res_mem); 1073 1074 bce_probe_pci_caps(dev, sc); 1075 1076 rid = 1; 1077 count = 0; 1078#if 0 1079 /* Try allocating MSI-X interrupts. */ 1080 if ((sc->bce_cap_flags & BCE_MSIX_CAPABLE_FLAG) && 1081 (bce_msi_enable >= 2) && 1082 ((sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1083 &rid, RF_ACTIVE)) != NULL)) { 1084 1085 msi_needed = count = 1; 1086 1087 if (((error = pci_alloc_msix(dev, &count)) != 0) || 1088 (count != msi_needed)) { 1089 BCE_PRINTF("%s(%d): MSI-X allocation failed! Requested = %d," 1090 "Received = %d, error = %d\n", __FILE__, __LINE__, 1091 msi_needed, count, error); 1092 count = 0; 1093 pci_release_msi(dev); 1094 bus_release_resource(dev, SYS_RES_MEMORY, rid, 1095 sc->bce_res_irq); 1096 sc->bce_res_irq = NULL; 1097 } else { 1098 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using MSI-X interrupt.\n", 1099 __FUNCTION__); 1100 sc->bce_flags |= BCE_USING_MSIX_FLAG; 1101 } 1102 } 1103#endif 1104 1105 /* Try allocating a MSI interrupt. */ 1106 if ((sc->bce_cap_flags & BCE_MSI_CAPABLE_FLAG) && 1107 (bce_msi_enable >= 1) && (count == 0)) { 1108 count = 1; 1109 if ((error = pci_alloc_msi(dev, &count)) != 0) { 1110 BCE_PRINTF("%s(%d): MSI allocation failed! " 1111 "error = %d\n", __FILE__, __LINE__, error); 1112 count = 0; 1113 pci_release_msi(dev); 1114 } else { 1115 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using MSI " 1116 "interrupt.\n", __FUNCTION__); 1117 sc->bce_flags |= BCE_USING_MSI_FLAG; 1118 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) 1119 sc->bce_flags |= BCE_ONE_SHOT_MSI_FLAG; 1120 rid = 1; 1121 } 1122 } 1123 1124 /* Try allocating a legacy interrupt. */ 1125 if (count == 0) { 1126 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using INTx interrupt.\n", 1127 __FUNCTION__); 1128 rid = 0; 1129 } 1130 1131 sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 1132 &rid, RF_ACTIVE | (count != 0 ? 0 : RF_SHAREABLE)); 1133 1134 /* Report any IRQ allocation errors. */ 1135 if (sc->bce_res_irq == NULL) { 1136 BCE_PRINTF("%s(%d): PCI map interrupt failed!\n", 1137 __FILE__, __LINE__); 1138 rc = ENXIO; 1139 goto bce_attach_fail; 1140 } 1141 1142 /* Initialize mutex for the current device instance. */ 1143 BCE_LOCK_INIT(sc, device_get_nameunit(dev)); 1144 1145 /* 1146 * Configure byte swap and enable indirect register access. 1147 * Rely on CPU to do target byte swapping on big endian systems. 1148 * Access to registers outside of PCI configurtion space are not 1149 * valid until this is done. 1150 */ 1151 pci_write_config(dev, BCE_PCICFG_MISC_CONFIG, 1152 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 1153 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP, 4); 1154 1155 /* Save ASIC revsion info. */ 1156 sc->bce_chipid = REG_RD(sc, BCE_MISC_ID); 1157 1158 /* Weed out any non-production controller revisions. */ 1159 switch(BCE_CHIP_ID(sc)) { 1160 case BCE_CHIP_ID_5706_A0: 1161 case BCE_CHIP_ID_5706_A1: 1162 case BCE_CHIP_ID_5708_A0: 1163 case BCE_CHIP_ID_5708_B0: 1164 case BCE_CHIP_ID_5709_A0: 1165 case BCE_CHIP_ID_5709_B0: 1166 case BCE_CHIP_ID_5709_B1: 1167 case BCE_CHIP_ID_5709_B2: 1168 BCE_PRINTF("%s(%d): Unsupported controller " 1169 "revision (%c%d)!\n", __FILE__, __LINE__, 1170 (((pci_read_config(dev, PCIR_REVID, 4) & 1171 0xf0) >> 4) + 'A'), (pci_read_config(dev, 1172 PCIR_REVID, 4) & 0xf)); 1173 rc = ENODEV; 1174 goto bce_attach_fail; 1175 } 1176 1177 /* 1178 * The embedded PCIe to PCI-X bridge (EPB) 1179 * in the 5708 cannot address memory above 1180 * 40 bits (E7_5708CB1_23043 & E6_5708SB1_23043). 1181 */ 1182 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708) 1183 sc->max_bus_addr = BCE_BUS_SPACE_MAXADDR; 1184 else 1185 sc->max_bus_addr = BUS_SPACE_MAXADDR; 1186 1187 /* 1188 * Find the base address for shared memory access. 1189 * Newer versions of bootcode use a signature and offset 1190 * while older versions use a fixed address. 1191 */ 1192 val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE); 1193 if ((val & BCE_SHM_HDR_SIGNATURE_SIG_MASK) == BCE_SHM_HDR_SIGNATURE_SIG) 1194 /* Multi-port devices use different offsets in shared memory. */ 1195 sc->bce_shmem_base = REG_RD_IND(sc, BCE_SHM_HDR_ADDR_0 + 1196 (pci_get_function(sc->bce_dev) << 2)); 1197 else 1198 sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE; 1199 1200 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): bce_shmem_base = 0x%08X\n", 1201 __FUNCTION__, sc->bce_shmem_base); 1202 1203 /* Fetch the bootcode revision. */ 1204 val = bce_shmem_rd(sc, BCE_DEV_INFO_BC_REV); 1205 for (int i = 0, j = 0; i < 3; i++) { 1206 u8 num; 1207 1208 num = (u8) (val >> (24 - (i * 8))); 1209 for (int k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) { 1210 if (num >= k || !skip0 || k == 1) { 1211 sc->bce_bc_ver[j++] = (num / k) + '0'; 1212 skip0 = 0; 1213 } 1214 } 1215 1216 if (i != 2) 1217 sc->bce_bc_ver[j++] = '.'; 1218 } 1219 1220 /* Check if any management firwmare is enabled. */ 1221 val = bce_shmem_rd(sc, BCE_PORT_FEATURE); 1222 if (val & BCE_PORT_FEATURE_ASF_ENABLED) { 1223 sc->bce_flags |= BCE_MFW_ENABLE_FLAG; 1224 1225 /* Allow time for firmware to enter the running state. */ 1226 for (int i = 0; i < 30; i++) { 1227 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); 1228 if (val & BCE_CONDITION_MFW_RUN_MASK) 1229 break; 1230 DELAY(10000); 1231 } 1232 1233 /* Check if management firmware is running. */ 1234 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); 1235 val &= BCE_CONDITION_MFW_RUN_MASK; 1236 if ((val != BCE_CONDITION_MFW_RUN_UNKNOWN) && 1237 (val != BCE_CONDITION_MFW_RUN_NONE)) { 1238 u32 addr = bce_shmem_rd(sc, BCE_MFW_VER_PTR); 1239 int i = 0; 1240 1241 /* Read the management firmware version string. */ 1242 for (int j = 0; j < 3; j++) { 1243 val = bce_reg_rd_ind(sc, addr + j * 4); 1244 val = bswap32(val); 1245 memcpy(&sc->bce_mfw_ver[i], &val, 4); 1246 i += 4; 1247 } 1248 } else { 1249 /* May cause firmware synchronization timeouts. */ 1250 BCE_PRINTF("%s(%d): Management firmware enabled " 1251 "but not running!\n", __FILE__, __LINE__); 1252 strcpy(sc->bce_mfw_ver, "NOT RUNNING!"); 1253 1254 /* ToDo: Any action the driver should take? */ 1255 } 1256 } 1257 1258 /* Get PCI bus information (speed and type). */ 1259 val = REG_RD(sc, BCE_PCICFG_MISC_STATUS); 1260 if (val & BCE_PCICFG_MISC_STATUS_PCIX_DET) { 1261 u32 clkreg; 1262 1263 sc->bce_flags |= BCE_PCIX_FLAG; 1264 1265 clkreg = REG_RD(sc, BCE_PCICFG_PCI_CLOCK_CONTROL_BITS); 1266 1267 clkreg &= BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET; 1268 switch (clkreg) { 1269 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ: 1270 sc->bus_speed_mhz = 133; 1271 break; 1272 1273 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ: 1274 sc->bus_speed_mhz = 100; 1275 break; 1276 1277 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ: 1278 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ: 1279 sc->bus_speed_mhz = 66; 1280 break; 1281 1282 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ: 1283 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ: 1284 sc->bus_speed_mhz = 50; 1285 break; 1286 1287 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW: 1288 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ: 1289 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ: 1290 sc->bus_speed_mhz = 33; 1291 break; 1292 } 1293 } else { 1294 if (val & BCE_PCICFG_MISC_STATUS_M66EN) 1295 sc->bus_speed_mhz = 66; 1296 else 1297 sc->bus_speed_mhz = 33; 1298 } 1299 1300 if (val & BCE_PCICFG_MISC_STATUS_32BIT_DET) 1301 sc->bce_flags |= BCE_PCI_32BIT_FLAG; 1302 1303 /* Find the media type for the adapter. */ 1304 bce_get_media(sc); 1305 1306 /* Reset controller and announce to bootcode that driver is present. */ 1307 if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) { 1308 BCE_PRINTF("%s(%d): Controller reset failed!\n", 1309 __FILE__, __LINE__); 1310 rc = ENXIO; 1311 goto bce_attach_fail; 1312 } 1313 1314 /* Initialize the controller. */ 1315 if (bce_chipinit(sc)) { 1316 BCE_PRINTF("%s(%d): Controller initialization failed!\n", 1317 __FILE__, __LINE__); 1318 rc = ENXIO; 1319 goto bce_attach_fail; 1320 } 1321 1322 /* Perform NVRAM test. */ 1323 if (bce_nvram_test(sc)) { 1324 BCE_PRINTF("%s(%d): NVRAM test failed!\n", 1325 __FILE__, __LINE__); 1326 rc = ENXIO; 1327 goto bce_attach_fail; 1328 } 1329 1330 /* Fetch the permanent Ethernet MAC address. */ 1331 bce_get_mac_addr(sc); 1332 1333 /* Update statistics once every second. */ 1334 sc->bce_stats_ticks = 1000000 & 0xffff00; 1335 1336 /* Store data needed by PHY driver for backplane applications */ 1337 sc->bce_shared_hw_cfg = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG); 1338 sc->bce_port_hw_cfg = bce_shmem_rd(sc, BCE_PORT_HW_CFG_CONFIG); 1339 1340 /* Allocate DMA memory resources. */ 1341 if (bce_dma_alloc(dev)) { 1342 BCE_PRINTF("%s(%d): DMA resource allocation failed!\n", 1343 __FILE__, __LINE__); 1344 rc = ENXIO; 1345 goto bce_attach_fail; 1346 } 1347 1348 /* Allocate an ifnet structure. */ 1349 ifp = sc->bce_ifp = if_alloc(IFT_ETHER); 1350 if (ifp == NULL) { 1351 BCE_PRINTF("%s(%d): Interface allocation failed!\n", 1352 __FILE__, __LINE__); 1353 rc = ENXIO; 1354 goto bce_attach_fail; 1355 } 1356 1357 /* Initialize the ifnet interface. */ 1358 ifp->if_softc = sc; 1359 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1360 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1361 ifp->if_ioctl = bce_ioctl; 1362 ifp->if_start = bce_start; 1363 ifp->if_init = bce_init; 1364 ifp->if_mtu = ETHERMTU; 1365 1366 if (bce_tso_enable) { 1367 ifp->if_hwassist = BCE_IF_HWASSIST | CSUM_TSO; 1368 ifp->if_capabilities = BCE_IF_CAPABILITIES | IFCAP_TSO4 | 1369 IFCAP_VLAN_HWTSO; 1370 } else { 1371 ifp->if_hwassist = BCE_IF_HWASSIST; 1372 ifp->if_capabilities = BCE_IF_CAPABILITIES; 1373 } 1374 1375#if __FreeBSD_version >= 800505 1376 /* 1377 * Introducing IFCAP_LINKSTATE didn't bump __FreeBSD_version 1378 * so it's approximate value. 1379 */ 1380 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) 1381 ifp->if_capabilities |= IFCAP_LINKSTATE; 1382#endif 1383 1384 ifp->if_capenable = ifp->if_capabilities; 1385 1386 /* 1387 * Assume standard mbuf sizes for buffer allocation. 1388 * This may change later if the MTU size is set to 1389 * something other than 1500. 1390 */ 1391 bce_get_rx_buffer_sizes(sc, 1392 (ETHER_MAX_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN)); 1393 1394 /* Recalculate our buffer allocation sizes. */ 1395 ifp->if_snd.ifq_drv_maxlen = USABLE_TX_BD_ALLOC; 1396 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 1397 IFQ_SET_READY(&ifp->if_snd); 1398 1399 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) 1400 ifp->if_baudrate = IF_Mbps(2500ULL); 1401 else 1402 ifp->if_baudrate = IF_Mbps(1000); 1403 1404 /* Handle any special PHY initialization for SerDes PHYs. */ 1405 bce_init_media(sc); 1406 1407 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) { 1408 ifmedia_init(&sc->bce_ifmedia, IFM_IMASK, bce_ifmedia_upd, 1409 bce_ifmedia_sts); 1410 /* 1411 * We can't manually override remote PHY's link and assume 1412 * PHY port configuration(Fiber or TP) is not changed after 1413 * device attach. This may not be correct though. 1414 */ 1415 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) != 0) { 1416 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) { 1417 ifmedia_add(&sc->bce_ifmedia, 1418 IFM_ETHER | IFM_2500_SX, 0, NULL); 1419 ifmedia_add(&sc->bce_ifmedia, 1420 IFM_ETHER | IFM_2500_SX | IFM_FDX, 0, NULL); 1421 } 1422 ifmedia_add(&sc->bce_ifmedia, 1423 IFM_ETHER | IFM_1000_SX, 0, NULL); 1424 ifmedia_add(&sc->bce_ifmedia, 1425 IFM_ETHER | IFM_1000_SX | IFM_FDX, 0, NULL); 1426 } else { 1427 ifmedia_add(&sc->bce_ifmedia, 1428 IFM_ETHER | IFM_10_T, 0, NULL); 1429 ifmedia_add(&sc->bce_ifmedia, 1430 IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 1431 ifmedia_add(&sc->bce_ifmedia, 1432 IFM_ETHER | IFM_100_TX, 0, NULL); 1433 ifmedia_add(&sc->bce_ifmedia, 1434 IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 1435 ifmedia_add(&sc->bce_ifmedia, 1436 IFM_ETHER | IFM_1000_T, 0, NULL); 1437 ifmedia_add(&sc->bce_ifmedia, 1438 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 1439 } 1440 ifmedia_add(&sc->bce_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 1441 ifmedia_set(&sc->bce_ifmedia, IFM_ETHER | IFM_AUTO); 1442 sc->bce_ifmedia.ifm_media = sc->bce_ifmedia.ifm_cur->ifm_media; 1443 } else { 1444 /* MII child bus by attaching the PHY. */ 1445 rc = mii_attach(dev, &sc->bce_miibus, ifp, bce_ifmedia_upd, 1446 bce_ifmedia_sts, BMSR_DEFCAPMASK, sc->bce_phy_addr, 1447 MII_OFFSET_ANY, MIIF_DOPAUSE); 1448 if (rc != 0) { 1449 BCE_PRINTF("%s(%d): attaching PHYs failed\n", __FILE__, 1450 __LINE__); 1451 goto bce_attach_fail; 1452 } 1453 } 1454 1455 /* Attach to the Ethernet interface list. */ 1456 ether_ifattach(ifp, sc->eaddr); 1457 1458#if __FreeBSD_version < 500000 1459 callout_init(&sc->bce_tick_callout); 1460 callout_init(&sc->bce_pulse_callout); 1461#else 1462 callout_init_mtx(&sc->bce_tick_callout, &sc->bce_mtx, 0); 1463 callout_init_mtx(&sc->bce_pulse_callout, &sc->bce_mtx, 0); 1464#endif 1465 1466 /* Hookup IRQ last. */ 1467 rc = bus_setup_intr(dev, sc->bce_res_irq, INTR_TYPE_NET | INTR_MPSAFE, 1468 NULL, bce_intr, sc, &sc->bce_intrhand); 1469 1470 if (rc) { 1471 BCE_PRINTF("%s(%d): Failed to setup IRQ!\n", 1472 __FILE__, __LINE__); 1473 bce_detach(dev); 1474 goto bce_attach_exit; 1475 } 1476 1477 /* 1478 * At this point we've acquired all the resources 1479 * we need to run so there's no turning back, we're 1480 * cleared for launch. 1481 */ 1482 1483 /* Print some important debugging info. */ 1484 DBRUNMSG(BCE_INFO, bce_dump_driver_state(sc)); 1485 1486 /* Add the supported sysctls to the kernel. */ 1487 bce_add_sysctls(sc); 1488 1489 BCE_LOCK(sc); 1490 1491 /* 1492 * The chip reset earlier notified the bootcode that 1493 * a driver is present. We now need to start our pulse 1494 * routine so that the bootcode is reminded that we're 1495 * still running. 1496 */ 1497 bce_pulse(sc); 1498 1499 bce_mgmt_init_locked(sc); 1500 BCE_UNLOCK(sc); 1501 1502 /* Finally, print some useful adapter info */ 1503 bce_print_adapter_info(sc); 1504 DBPRINT(sc, BCE_FATAL, "%s(): sc = %p\n", 1505 __FUNCTION__, sc); 1506 1507 goto bce_attach_exit; 1508 1509bce_attach_fail: 1510 bce_release_resources(sc); 1511 1512bce_attach_exit: 1513 1514 DBEXIT(BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 1515 1516 return(rc); 1517} 1518 1519 1520/****************************************************************************/ 1521/* Device detach function. */ 1522/* */ 1523/* Stops the controller, resets the controller, and releases resources. */ 1524/* */ 1525/* Returns: */ 1526/* 0 on success, positive value on failure. */ 1527/****************************************************************************/ 1528static int 1529bce_detach(device_t dev) 1530{ 1531 struct bce_softc *sc = device_get_softc(dev); 1532 struct ifnet *ifp; 1533 u32 msg; 1534 1535 DBENTER(BCE_VERBOSE_UNLOAD | BCE_VERBOSE_RESET); 1536 1537 ifp = sc->bce_ifp; 1538 1539 /* Stop and reset the controller. */ 1540 BCE_LOCK(sc); 1541 1542 /* Stop the pulse so the bootcode can go to driver absent state. */ 1543 callout_stop(&sc->bce_pulse_callout); 1544 1545 bce_stop(sc); 1546 if (sc->bce_flags & BCE_NO_WOL_FLAG) 1547 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN; 1548 else 1549 msg = BCE_DRV_MSG_CODE_UNLOAD; 1550 bce_reset(sc, msg); 1551 1552 BCE_UNLOCK(sc); 1553 1554 ether_ifdetach(ifp); 1555 1556 /* If we have a child device on the MII bus remove it too. */ 1557 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) 1558 ifmedia_removeall(&sc->bce_ifmedia); 1559 else { 1560 bus_generic_detach(dev); 1561 device_delete_child(dev, sc->bce_miibus); 1562 } 1563 1564 /* Release all remaining resources. */ 1565 bce_release_resources(sc); 1566 1567 DBEXIT(BCE_VERBOSE_UNLOAD | BCE_VERBOSE_RESET); 1568 1569 return(0); 1570} 1571 1572 1573/****************************************************************************/ 1574/* Device shutdown function. */ 1575/* */ 1576/* Stops and resets the controller. */ 1577/* */ 1578/* Returns: */ 1579/* 0 on success, positive value on failure. */ 1580/****************************************************************************/ 1581static int 1582bce_shutdown(device_t dev) 1583{ 1584 struct bce_softc *sc = device_get_softc(dev); 1585 u32 msg; 1586 1587 DBENTER(BCE_VERBOSE); 1588 1589 BCE_LOCK(sc); 1590 bce_stop(sc); 1591 if (sc->bce_flags & BCE_NO_WOL_FLAG) 1592 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN; 1593 else 1594 msg = BCE_DRV_MSG_CODE_UNLOAD; 1595 bce_reset(sc, msg); 1596 BCE_UNLOCK(sc); 1597 1598 DBEXIT(BCE_VERBOSE); 1599 1600 return (0); 1601} 1602 1603 1604#ifdef BCE_DEBUG 1605/****************************************************************************/ 1606/* Register read. */ 1607/* */ 1608/* Returns: */ 1609/* The value of the register. */ 1610/****************************************************************************/ 1611static u32 1612bce_reg_rd(struct bce_softc *sc, u32 offset) 1613{ 1614 u32 val = REG_RD(sc, offset); 1615 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1616 __FUNCTION__, offset, val); 1617 return val; 1618} 1619 1620 1621/****************************************************************************/ 1622/* Register write (16 bit). */ 1623/* */ 1624/* Returns: */ 1625/* Nothing. */ 1626/****************************************************************************/ 1627static void 1628bce_reg_wr16(struct bce_softc *sc, u32 offset, u16 val) 1629{ 1630 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%04X\n", 1631 __FUNCTION__, offset, val); 1632 REG_WR16(sc, offset, val); 1633} 1634 1635 1636/****************************************************************************/ 1637/* Register write. */ 1638/* */ 1639/* Returns: */ 1640/* Nothing. */ 1641/****************************************************************************/ 1642static void 1643bce_reg_wr(struct bce_softc *sc, u32 offset, u32 val) 1644{ 1645 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1646 __FUNCTION__, offset, val); 1647 REG_WR(sc, offset, val); 1648} 1649#endif 1650 1651/****************************************************************************/ 1652/* Indirect register read. */ 1653/* */ 1654/* Reads NetXtreme II registers using an index/data register pair in PCI */ 1655/* configuration space. Using this mechanism avoids issues with posted */ 1656/* reads but is much slower than memory-mapped I/O. */ 1657/* */ 1658/* Returns: */ 1659/* The value of the register. */ 1660/****************************************************************************/ 1661static u32 1662bce_reg_rd_ind(struct bce_softc *sc, u32 offset) 1663{ 1664 device_t dev; 1665 dev = sc->bce_dev; 1666 1667 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4); 1668#ifdef BCE_DEBUG 1669 { 1670 u32 val; 1671 val = pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4); 1672 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1673 __FUNCTION__, offset, val); 1674 return val; 1675 } 1676#else 1677 return pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4); 1678#endif 1679} 1680 1681 1682/****************************************************************************/ 1683/* Indirect register write. */ 1684/* */ 1685/* Writes NetXtreme II registers using an index/data register pair in PCI */ 1686/* configuration space. Using this mechanism avoids issues with posted */ 1687/* writes but is muchh slower than memory-mapped I/O. */ 1688/* */ 1689/* Returns: */ 1690/* Nothing. */ 1691/****************************************************************************/ 1692static void 1693bce_reg_wr_ind(struct bce_softc *sc, u32 offset, u32 val) 1694{ 1695 device_t dev; 1696 dev = sc->bce_dev; 1697 1698 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1699 __FUNCTION__, offset, val); 1700 1701 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4); 1702 pci_write_config(dev, BCE_PCICFG_REG_WINDOW, val, 4); 1703} 1704 1705 1706/****************************************************************************/ 1707/* Shared memory write. */ 1708/* */ 1709/* Writes NetXtreme II shared memory region. */ 1710/* */ 1711/* Returns: */ 1712/* Nothing. */ 1713/****************************************************************************/ 1714static void 1715bce_shmem_wr(struct bce_softc *sc, u32 offset, u32 val) 1716{ 1717 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): Writing 0x%08X to " 1718 "0x%08X\n", __FUNCTION__, val, offset); 1719 1720 bce_reg_wr_ind(sc, sc->bce_shmem_base + offset, val); 1721} 1722 1723 1724/****************************************************************************/ 1725/* Shared memory read. */ 1726/* */ 1727/* Reads NetXtreme II shared memory region. */ 1728/* */ 1729/* Returns: */ 1730/* The 32 bit value read. */ 1731/****************************************************************************/ 1732static u32 1733bce_shmem_rd(struct bce_softc *sc, u32 offset) 1734{ 1735 u32 val = bce_reg_rd_ind(sc, sc->bce_shmem_base + offset); 1736 1737 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): Reading 0x%08X from " 1738 "0x%08X\n", __FUNCTION__, val, offset); 1739 1740 return val; 1741} 1742 1743 1744#ifdef BCE_DEBUG 1745/****************************************************************************/ 1746/* Context memory read. */ 1747/* */ 1748/* The NetXtreme II controller uses context memory to track connection */ 1749/* information for L2 and higher network protocols. */ 1750/* */ 1751/* Returns: */ 1752/* The requested 32 bit value of context memory. */ 1753/****************************************************************************/ 1754static u32 1755bce_ctx_rd(struct bce_softc *sc, u32 cid_addr, u32 ctx_offset) 1756{ 1757 u32 idx, offset, retry_cnt = 5, val; 1758 1759 DBRUNIF((cid_addr > MAX_CID_ADDR || ctx_offset & 0x3 || 1760 cid_addr & CTX_MASK), BCE_PRINTF("%s(): Invalid CID " 1761 "address: 0x%08X.\n", __FUNCTION__, cid_addr)); 1762 1763 offset = ctx_offset + cid_addr; 1764 1765 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 1766 1767 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_READ_REQ)); 1768 1769 for (idx = 0; idx < retry_cnt; idx++) { 1770 val = REG_RD(sc, BCE_CTX_CTX_CTRL); 1771 if ((val & BCE_CTX_CTX_CTRL_READ_REQ) == 0) 1772 break; 1773 DELAY(5); 1774 } 1775 1776 if (val & BCE_CTX_CTX_CTRL_READ_REQ) 1777 BCE_PRINTF("%s(%d); Unable to read CTX memory: " 1778 "cid_addr = 0x%08X, offset = 0x%08X!\n", 1779 __FILE__, __LINE__, cid_addr, ctx_offset); 1780 1781 val = REG_RD(sc, BCE_CTX_CTX_DATA); 1782 } else { 1783 REG_WR(sc, BCE_CTX_DATA_ADR, offset); 1784 val = REG_RD(sc, BCE_CTX_DATA); 1785 } 1786 1787 DBPRINT(sc, BCE_EXTREME_CTX, "%s(); cid_addr = 0x%08X, offset = 0x%08X, " 1788 "val = 0x%08X\n", __FUNCTION__, cid_addr, ctx_offset, val); 1789 1790 return(val); 1791} 1792#endif 1793 1794 1795/****************************************************************************/ 1796/* Context memory write. */ 1797/* */ 1798/* The NetXtreme II controller uses context memory to track connection */ 1799/* information for L2 and higher network protocols. */ 1800/* */ 1801/* Returns: */ 1802/* Nothing. */ 1803/****************************************************************************/ 1804static void 1805bce_ctx_wr(struct bce_softc *sc, u32 cid_addr, u32 ctx_offset, u32 ctx_val) 1806{ 1807 u32 idx, offset = ctx_offset + cid_addr; 1808 u32 val, retry_cnt = 5; 1809 1810 DBPRINT(sc, BCE_EXTREME_CTX, "%s(); cid_addr = 0x%08X, offset = 0x%08X, " 1811 "val = 0x%08X\n", __FUNCTION__, cid_addr, ctx_offset, ctx_val); 1812 1813 DBRUNIF((cid_addr > MAX_CID_ADDR || ctx_offset & 0x3 || cid_addr & CTX_MASK), 1814 BCE_PRINTF("%s(): Invalid CID address: 0x%08X.\n", 1815 __FUNCTION__, cid_addr)); 1816 1817 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 1818 1819 REG_WR(sc, BCE_CTX_CTX_DATA, ctx_val); 1820 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_WRITE_REQ)); 1821 1822 for (idx = 0; idx < retry_cnt; idx++) { 1823 val = REG_RD(sc, BCE_CTX_CTX_CTRL); 1824 if ((val & BCE_CTX_CTX_CTRL_WRITE_REQ) == 0) 1825 break; 1826 DELAY(5); 1827 } 1828 1829 if (val & BCE_CTX_CTX_CTRL_WRITE_REQ) 1830 BCE_PRINTF("%s(%d); Unable to write CTX memory: " 1831 "cid_addr = 0x%08X, offset = 0x%08X!\n", 1832 __FILE__, __LINE__, cid_addr, ctx_offset); 1833 1834 } else { 1835 REG_WR(sc, BCE_CTX_DATA_ADR, offset); 1836 REG_WR(sc, BCE_CTX_DATA, ctx_val); 1837 } 1838} 1839 1840 1841/****************************************************************************/ 1842/* PHY register read. */ 1843/* */ 1844/* Implements register reads on the MII bus. */ 1845/* */ 1846/* Returns: */ 1847/* The value of the register. */ 1848/****************************************************************************/ 1849static int 1850bce_miibus_read_reg(device_t dev, int phy, int reg) 1851{ 1852 struct bce_softc *sc; 1853 u32 val; 1854 int i; 1855 1856 sc = device_get_softc(dev); 1857 1858 /* 1859 * The 5709S PHY is an IEEE Clause 45 PHY 1860 * with special mappings to work with IEEE 1861 * Clause 22 register accesses. 1862 */ 1863 if ((sc->bce_phy_flags & BCE_PHY_IEEE_CLAUSE_45_FLAG) != 0) { 1864 if (reg >= MII_BMCR && reg <= MII_ANLPRNP) 1865 reg += 0x10; 1866 } 1867 1868 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1869 val = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1870 val &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL; 1871 1872 REG_WR(sc, BCE_EMAC_MDIO_MODE, val); 1873 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1874 1875 DELAY(40); 1876 } 1877 1878 1879 val = BCE_MIPHY(phy) | BCE_MIREG(reg) | 1880 BCE_EMAC_MDIO_COMM_COMMAND_READ | BCE_EMAC_MDIO_COMM_DISEXT | 1881 BCE_EMAC_MDIO_COMM_START_BUSY; 1882 REG_WR(sc, BCE_EMAC_MDIO_COMM, val); 1883 1884 for (i = 0; i < BCE_PHY_TIMEOUT; i++) { 1885 DELAY(10); 1886 1887 val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1888 if (!(val & BCE_EMAC_MDIO_COMM_START_BUSY)) { 1889 DELAY(5); 1890 1891 val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1892 val &= BCE_EMAC_MDIO_COMM_DATA; 1893 1894 break; 1895 } 1896 } 1897 1898 if (val & BCE_EMAC_MDIO_COMM_START_BUSY) { 1899 BCE_PRINTF("%s(%d): Error: PHY read timeout! phy = %d, " 1900 "reg = 0x%04X\n", __FILE__, __LINE__, phy, reg); 1901 val = 0x0; 1902 } else { 1903 val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1904 } 1905 1906 1907 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1908 val = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1909 val |= BCE_EMAC_MDIO_MODE_AUTO_POLL; 1910 1911 REG_WR(sc, BCE_EMAC_MDIO_MODE, val); 1912 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1913 1914 DELAY(40); 1915 } 1916 1917 DB_PRINT_PHY_REG(reg, val); 1918 return (val & 0xffff); 1919} 1920 1921 1922/****************************************************************************/ 1923/* PHY register write. */ 1924/* */ 1925/* Implements register writes on the MII bus. */ 1926/* */ 1927/* Returns: */ 1928/* The value of the register. */ 1929/****************************************************************************/ 1930static int 1931bce_miibus_write_reg(device_t dev, int phy, int reg, int val) 1932{ 1933 struct bce_softc *sc; 1934 u32 val1; 1935 int i; 1936 1937 sc = device_get_softc(dev); 1938 1939 DB_PRINT_PHY_REG(reg, val); 1940 1941 /* 1942 * The 5709S PHY is an IEEE Clause 45 PHY 1943 * with special mappings to work with IEEE 1944 * Clause 22 register accesses. 1945 */ 1946 if ((sc->bce_phy_flags & BCE_PHY_IEEE_CLAUSE_45_FLAG) != 0) { 1947 if (reg >= MII_BMCR && reg <= MII_ANLPRNP) 1948 reg += 0x10; 1949 } 1950 1951 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1952 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1953 val1 &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL; 1954 1955 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1); 1956 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1957 1958 DELAY(40); 1959 } 1960 1961 val1 = BCE_MIPHY(phy) | BCE_MIREG(reg) | val | 1962 BCE_EMAC_MDIO_COMM_COMMAND_WRITE | 1963 BCE_EMAC_MDIO_COMM_START_BUSY | BCE_EMAC_MDIO_COMM_DISEXT; 1964 REG_WR(sc, BCE_EMAC_MDIO_COMM, val1); 1965 1966 for (i = 0; i < BCE_PHY_TIMEOUT; i++) { 1967 DELAY(10); 1968 1969 val1 = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1970 if (!(val1 & BCE_EMAC_MDIO_COMM_START_BUSY)) { 1971 DELAY(5); 1972 break; 1973 } 1974 } 1975 1976 if (val1 & BCE_EMAC_MDIO_COMM_START_BUSY) 1977 BCE_PRINTF("%s(%d): PHY write timeout!\n", 1978 __FILE__, __LINE__); 1979 1980 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1981 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1982 val1 |= BCE_EMAC_MDIO_MODE_AUTO_POLL; 1983 1984 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1); 1985 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1986 1987 DELAY(40); 1988 } 1989 1990 return 0; 1991} 1992 1993 1994/****************************************************************************/ 1995/* MII bus status change. */ 1996/* */ 1997/* Called by the MII bus driver when the PHY establishes link to set the */ 1998/* MAC interface registers. */ 1999/* */ 2000/* Returns: */ 2001/* Nothing. */ 2002/****************************************************************************/ 2003static void 2004bce_miibus_statchg(device_t dev) 2005{ 2006 struct bce_softc *sc; 2007 struct mii_data *mii; 2008 struct ifmediareq ifmr; 2009 int media_active, media_status, val; 2010 2011 sc = device_get_softc(dev); 2012 2013 DBENTER(BCE_VERBOSE_PHY); 2014 2015 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) { 2016 bzero(&ifmr, sizeof(ifmr)); 2017 bce_ifmedia_sts_rphy(sc, &ifmr); 2018 media_active = ifmr.ifm_active; 2019 media_status = ifmr.ifm_status; 2020 } else { 2021 mii = device_get_softc(sc->bce_miibus); 2022 media_active = mii->mii_media_active; 2023 media_status = mii->mii_media_status; 2024 } 2025 2026 /* Ignore invalid media status. */ 2027 if ((media_status & (IFM_ACTIVE | IFM_AVALID)) != 2028 (IFM_ACTIVE | IFM_AVALID)) 2029 goto bce_miibus_statchg_exit; 2030 2031 val = REG_RD(sc, BCE_EMAC_MODE); 2032 val &= ~(BCE_EMAC_MODE_PORT | BCE_EMAC_MODE_HALF_DUPLEX | 2033 BCE_EMAC_MODE_MAC_LOOP | BCE_EMAC_MODE_FORCE_LINK | 2034 BCE_EMAC_MODE_25G); 2035 2036 /* Set MII or GMII interface based on the PHY speed. */ 2037 switch (IFM_SUBTYPE(media_active)) { 2038 case IFM_10_T: 2039 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) { 2040 DBPRINT(sc, BCE_INFO_PHY, 2041 "Enabling 10Mb interface.\n"); 2042 val |= BCE_EMAC_MODE_PORT_MII_10; 2043 break; 2044 } 2045 /* fall-through */ 2046 case IFM_100_TX: 2047 DBPRINT(sc, BCE_INFO_PHY, "Enabling MII interface.\n"); 2048 val |= BCE_EMAC_MODE_PORT_MII; 2049 break; 2050 case IFM_2500_SX: 2051 DBPRINT(sc, BCE_INFO_PHY, "Enabling 2.5G MAC mode.\n"); 2052 val |= BCE_EMAC_MODE_25G; 2053 /* fall-through */ 2054 case IFM_1000_T: 2055 case IFM_1000_SX: 2056 DBPRINT(sc, BCE_INFO_PHY, "Enabling GMII interface.\n"); 2057 val |= BCE_EMAC_MODE_PORT_GMII; 2058 break; 2059 default: 2060 DBPRINT(sc, BCE_INFO_PHY, "Unknown link speed, enabling " 2061 "default GMII interface.\n"); 2062 val |= BCE_EMAC_MODE_PORT_GMII; 2063 } 2064 2065 /* Set half or full duplex based on PHY settings. */ 2066 if ((IFM_OPTIONS(media_active) & IFM_FDX) == 0) { 2067 DBPRINT(sc, BCE_INFO_PHY, 2068 "Setting Half-Duplex interface.\n"); 2069 val |= BCE_EMAC_MODE_HALF_DUPLEX; 2070 } else 2071 DBPRINT(sc, BCE_INFO_PHY, 2072 "Setting Full-Duplex interface.\n"); 2073 2074 REG_WR(sc, BCE_EMAC_MODE, val); 2075 2076 if ((IFM_OPTIONS(media_active) & IFM_ETH_RXPAUSE) != 0) { 2077 DBPRINT(sc, BCE_INFO_PHY, 2078 "%s(): Enabling RX flow control.\n", __FUNCTION__); 2079 BCE_SETBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_RX_MODE_FLOW_EN); 2080 sc->bce_flags |= BCE_USING_RX_FLOW_CONTROL; 2081 } else { 2082 DBPRINT(sc, BCE_INFO_PHY, 2083 "%s(): Disabling RX flow control.\n", __FUNCTION__); 2084 BCE_CLRBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_RX_MODE_FLOW_EN); 2085 sc->bce_flags &= ~BCE_USING_RX_FLOW_CONTROL; 2086 } 2087 2088 if ((IFM_OPTIONS(media_active) & IFM_ETH_TXPAUSE) != 0) { 2089 DBPRINT(sc, BCE_INFO_PHY, 2090 "%s(): Enabling TX flow control.\n", __FUNCTION__); 2091 BCE_SETBIT(sc, BCE_EMAC_TX_MODE, BCE_EMAC_TX_MODE_FLOW_EN); 2092 sc->bce_flags |= BCE_USING_TX_FLOW_CONTROL; 2093 } else { 2094 DBPRINT(sc, BCE_INFO_PHY, 2095 "%s(): Disabling TX flow control.\n", __FUNCTION__); 2096 BCE_CLRBIT(sc, BCE_EMAC_TX_MODE, BCE_EMAC_TX_MODE_FLOW_EN); 2097 sc->bce_flags &= ~BCE_USING_TX_FLOW_CONTROL; 2098 } 2099 2100 /* ToDo: Update watermarks in bce_init_rx_context(). */ 2101 2102bce_miibus_statchg_exit: 2103 DBEXIT(BCE_VERBOSE_PHY); 2104} 2105 2106 2107/****************************************************************************/ 2108/* Acquire NVRAM lock. */ 2109/* */ 2110/* Before the NVRAM can be accessed the caller must acquire an NVRAM lock. */ 2111/* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 2112/* for use by the driver. */ 2113/* */ 2114/* Returns: */ 2115/* 0 on success, positive value on failure. */ 2116/****************************************************************************/ 2117static int 2118bce_acquire_nvram_lock(struct bce_softc *sc) 2119{ 2120 u32 val; 2121 int j, rc = 0; 2122 2123 DBENTER(BCE_VERBOSE_NVRAM); 2124 2125 /* Request access to the flash interface. */ 2126 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2); 2127 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2128 val = REG_RD(sc, BCE_NVM_SW_ARB); 2129 if (val & BCE_NVM_SW_ARB_ARB_ARB2) 2130 break; 2131 2132 DELAY(5); 2133 } 2134 2135 if (j >= NVRAM_TIMEOUT_COUNT) { 2136 DBPRINT(sc, BCE_WARN, "Timeout acquiring NVRAM lock!\n"); 2137 rc = EBUSY; 2138 } 2139 2140 DBEXIT(BCE_VERBOSE_NVRAM); 2141 return (rc); 2142} 2143 2144 2145/****************************************************************************/ 2146/* Release NVRAM lock. */ 2147/* */ 2148/* When the caller is finished accessing NVRAM the lock must be released. */ 2149/* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 2150/* for use by the driver. */ 2151/* */ 2152/* Returns: */ 2153/* 0 on success, positive value on failure. */ 2154/****************************************************************************/ 2155static int 2156bce_release_nvram_lock(struct bce_softc *sc) 2157{ 2158 u32 val; 2159 int j, rc = 0; 2160 2161 DBENTER(BCE_VERBOSE_NVRAM); 2162 2163 /* 2164 * Relinquish nvram interface. 2165 */ 2166 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2); 2167 2168 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2169 val = REG_RD(sc, BCE_NVM_SW_ARB); 2170 if (!(val & BCE_NVM_SW_ARB_ARB_ARB2)) 2171 break; 2172 2173 DELAY(5); 2174 } 2175 2176 if (j >= NVRAM_TIMEOUT_COUNT) { 2177 DBPRINT(sc, BCE_WARN, "Timeout releasing NVRAM lock!\n"); 2178 rc = EBUSY; 2179 } 2180 2181 DBEXIT(BCE_VERBOSE_NVRAM); 2182 return (rc); 2183} 2184 2185 2186#ifdef BCE_NVRAM_WRITE_SUPPORT 2187/****************************************************************************/ 2188/* Enable NVRAM write access. */ 2189/* */ 2190/* Before writing to NVRAM the caller must enable NVRAM writes. */ 2191/* */ 2192/* Returns: */ 2193/* 0 on success, positive value on failure. */ 2194/****************************************************************************/ 2195static int 2196bce_enable_nvram_write(struct bce_softc *sc) 2197{ 2198 u32 val; 2199 int rc = 0; 2200 2201 DBENTER(BCE_VERBOSE_NVRAM); 2202 2203 val = REG_RD(sc, BCE_MISC_CFG); 2204 REG_WR(sc, BCE_MISC_CFG, val | BCE_MISC_CFG_NVM_WR_EN_PCI); 2205 2206 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2207 int j; 2208 2209 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 2210 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_WREN | BCE_NVM_COMMAND_DOIT); 2211 2212 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2213 DELAY(5); 2214 2215 val = REG_RD(sc, BCE_NVM_COMMAND); 2216 if (val & BCE_NVM_COMMAND_DONE) 2217 break; 2218 } 2219 2220 if (j >= NVRAM_TIMEOUT_COUNT) { 2221 DBPRINT(sc, BCE_WARN, "Timeout writing NVRAM!\n"); 2222 rc = EBUSY; 2223 } 2224 } 2225 2226 DBENTER(BCE_VERBOSE_NVRAM); 2227 return (rc); 2228} 2229 2230 2231/****************************************************************************/ 2232/* Disable NVRAM write access. */ 2233/* */ 2234/* When the caller is finished writing to NVRAM write access must be */ 2235/* disabled. */ 2236/* */ 2237/* Returns: */ 2238/* Nothing. */ 2239/****************************************************************************/ 2240static void 2241bce_disable_nvram_write(struct bce_softc *sc) 2242{ 2243 u32 val; 2244 2245 DBENTER(BCE_VERBOSE_NVRAM); 2246 2247 val = REG_RD(sc, BCE_MISC_CFG); 2248 REG_WR(sc, BCE_MISC_CFG, val & ~BCE_MISC_CFG_NVM_WR_EN); 2249 2250 DBEXIT(BCE_VERBOSE_NVRAM); 2251 2252} 2253#endif 2254 2255 2256/****************************************************************************/ 2257/* Enable NVRAM access. */ 2258/* */ 2259/* Before accessing NVRAM for read or write operations the caller must */ 2260/* enabled NVRAM access. */ 2261/* */ 2262/* Returns: */ 2263/* Nothing. */ 2264/****************************************************************************/ 2265static void 2266bce_enable_nvram_access(struct bce_softc *sc) 2267{ 2268 u32 val; 2269 2270 DBENTER(BCE_VERBOSE_NVRAM); 2271 2272 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE); 2273 /* Enable both bits, even on read. */ 2274 REG_WR(sc, BCE_NVM_ACCESS_ENABLE, val | 2275 BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN); 2276 2277 DBEXIT(BCE_VERBOSE_NVRAM); 2278} 2279 2280 2281/****************************************************************************/ 2282/* Disable NVRAM access. */ 2283/* */ 2284/* When the caller is finished accessing NVRAM access must be disabled. */ 2285/* */ 2286/* Returns: */ 2287/* Nothing. */ 2288/****************************************************************************/ 2289static void 2290bce_disable_nvram_access(struct bce_softc *sc) 2291{ 2292 u32 val; 2293 2294 DBENTER(BCE_VERBOSE_NVRAM); 2295 2296 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE); 2297 2298 /* Disable both bits, even after read. */ 2299 REG_WR(sc, BCE_NVM_ACCESS_ENABLE, val & 2300 ~(BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN)); 2301 2302 DBEXIT(BCE_VERBOSE_NVRAM); 2303} 2304 2305 2306#ifdef BCE_NVRAM_WRITE_SUPPORT 2307/****************************************************************************/ 2308/* Erase NVRAM page before writing. */ 2309/* */ 2310/* Non-buffered flash parts require that a page be erased before it is */ 2311/* written. */ 2312/* */ 2313/* Returns: */ 2314/* 0 on success, positive value on failure. */ 2315/****************************************************************************/ 2316static int 2317bce_nvram_erase_page(struct bce_softc *sc, u32 offset) 2318{ 2319 u32 cmd; 2320 int j, rc = 0; 2321 2322 DBENTER(BCE_VERBOSE_NVRAM); 2323 2324 /* Buffered flash doesn't require an erase. */ 2325 if (sc->bce_flash_info->flags & BCE_NV_BUFFERED) 2326 goto bce_nvram_erase_page_exit; 2327 2328 /* Build an erase command. */ 2329 cmd = BCE_NVM_COMMAND_ERASE | BCE_NVM_COMMAND_WR | 2330 BCE_NVM_COMMAND_DOIT; 2331 2332 /* 2333 * Clear the DONE bit separately, set the NVRAM adress to erase, 2334 * and issue the erase command. 2335 */ 2336 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 2337 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 2338 REG_WR(sc, BCE_NVM_COMMAND, cmd); 2339 2340 /* Wait for completion. */ 2341 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2342 u32 val; 2343 2344 DELAY(5); 2345 2346 val = REG_RD(sc, BCE_NVM_COMMAND); 2347 if (val & BCE_NVM_COMMAND_DONE) 2348 break; 2349 } 2350 2351 if (j >= NVRAM_TIMEOUT_COUNT) { 2352 DBPRINT(sc, BCE_WARN, "Timeout erasing NVRAM.\n"); 2353 rc = EBUSY; 2354 } 2355 2356bce_nvram_erase_page_exit: 2357 DBEXIT(BCE_VERBOSE_NVRAM); 2358 return (rc); 2359} 2360#endif /* BCE_NVRAM_WRITE_SUPPORT */ 2361 2362 2363/****************************************************************************/ 2364/* Read a dword (32 bits) from NVRAM. */ 2365/* */ 2366/* Read a 32 bit word from NVRAM. The caller is assumed to have already */ 2367/* obtained the NVRAM lock and enabled the controller for NVRAM access. */ 2368/* */ 2369/* Returns: */ 2370/* 0 on success and the 32 bit value read, positive value on failure. */ 2371/****************************************************************************/ 2372static int 2373bce_nvram_read_dword(struct bce_softc *sc, 2374 u32 offset, u8 *ret_val, u32 cmd_flags) 2375{ 2376 u32 cmd; 2377 int i, rc = 0; 2378 2379 DBENTER(BCE_EXTREME_NVRAM); 2380 2381 /* Build the command word. */ 2382 cmd = BCE_NVM_COMMAND_DOIT | cmd_flags; 2383 2384 /* Calculate the offset for buffered flash if translation is used. */ 2385 if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) { 2386 offset = ((offset / sc->bce_flash_info->page_size) << 2387 sc->bce_flash_info->page_bits) + 2388 (offset % sc->bce_flash_info->page_size); 2389 } 2390 2391 /* 2392 * Clear the DONE bit separately, set the address to read, 2393 * and issue the read. 2394 */ 2395 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 2396 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 2397 REG_WR(sc, BCE_NVM_COMMAND, cmd); 2398 2399 /* Wait for completion. */ 2400 for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) { 2401 u32 val; 2402 2403 DELAY(5); 2404 2405 val = REG_RD(sc, BCE_NVM_COMMAND); 2406 if (val & BCE_NVM_COMMAND_DONE) { 2407 val = REG_RD(sc, BCE_NVM_READ); 2408 2409 val = bce_be32toh(val); 2410 memcpy(ret_val, &val, 4); 2411 break; 2412 } 2413 } 2414 2415 /* Check for errors. */ 2416 if (i >= NVRAM_TIMEOUT_COUNT) { 2417 BCE_PRINTF("%s(%d): Timeout error reading NVRAM at " 2418 "offset 0x%08X!\n", __FILE__, __LINE__, offset); 2419 rc = EBUSY; 2420 } 2421 2422 DBEXIT(BCE_EXTREME_NVRAM); 2423 return(rc); 2424} 2425 2426 2427#ifdef BCE_NVRAM_WRITE_SUPPORT 2428/****************************************************************************/ 2429/* Write a dword (32 bits) to NVRAM. */ 2430/* */ 2431/* Write a 32 bit word to NVRAM. The caller is assumed to have already */ 2432/* obtained the NVRAM lock, enabled the controller for NVRAM access, and */ 2433/* enabled NVRAM write access. */ 2434/* */ 2435/* Returns: */ 2436/* 0 on success, positive value on failure. */ 2437/****************************************************************************/ 2438static int 2439bce_nvram_write_dword(struct bce_softc *sc, u32 offset, u8 *val, 2440 u32 cmd_flags) 2441{ 2442 u32 cmd, val32; 2443 int j, rc = 0; 2444 2445 DBENTER(BCE_VERBOSE_NVRAM); 2446 2447 /* Build the command word. */ 2448 cmd = BCE_NVM_COMMAND_DOIT | BCE_NVM_COMMAND_WR | cmd_flags; 2449 2450 /* Calculate the offset for buffered flash if translation is used. */ 2451 if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) { 2452 offset = ((offset / sc->bce_flash_info->page_size) << 2453 sc->bce_flash_info->page_bits) + 2454 (offset % sc->bce_flash_info->page_size); 2455 } 2456 2457 /* 2458 * Clear the DONE bit separately, convert NVRAM data to big-endian, 2459 * set the NVRAM address to write, and issue the write command 2460 */ 2461 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 2462 memcpy(&val32, val, 4); 2463 val32 = htobe32(val32); 2464 REG_WR(sc, BCE_NVM_WRITE, val32); 2465 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 2466 REG_WR(sc, BCE_NVM_COMMAND, cmd); 2467 2468 /* Wait for completion. */ 2469 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2470 DELAY(5); 2471 2472 if (REG_RD(sc, BCE_NVM_COMMAND) & BCE_NVM_COMMAND_DONE) 2473 break; 2474 } 2475 if (j >= NVRAM_TIMEOUT_COUNT) { 2476 BCE_PRINTF("%s(%d): Timeout error writing NVRAM at " 2477 "offset 0x%08X\n", __FILE__, __LINE__, offset); 2478 rc = EBUSY; 2479 } 2480 2481 DBEXIT(BCE_VERBOSE_NVRAM); 2482 return (rc); 2483} 2484#endif /* BCE_NVRAM_WRITE_SUPPORT */ 2485 2486 2487/****************************************************************************/ 2488/* Initialize NVRAM access. */ 2489/* */ 2490/* Identify the NVRAM device in use and prepare the NVRAM interface to */ 2491/* access that device. */ 2492/* */ 2493/* Returns: */ 2494/* 0 on success, positive value on failure. */ 2495/****************************************************************************/ 2496static int 2497bce_init_nvram(struct bce_softc *sc) 2498{ 2499 u32 val; 2500 int j, entry_count, rc = 0; 2501 const struct flash_spec *flash; 2502 2503 DBENTER(BCE_VERBOSE_NVRAM); 2504 2505 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 2506 sc->bce_flash_info = &flash_5709; 2507 goto bce_init_nvram_get_flash_size; 2508 } 2509 2510 /* Determine the selected interface. */ 2511 val = REG_RD(sc, BCE_NVM_CFG1); 2512 2513 entry_count = sizeof(flash_table) / sizeof(struct flash_spec); 2514 2515 /* 2516 * Flash reconfiguration is required to support additional 2517 * NVRAM devices not directly supported in hardware. 2518 * Check if the flash interface was reconfigured 2519 * by the bootcode. 2520 */ 2521 2522 if (val & 0x40000000) { 2523 /* Flash interface reconfigured by bootcode. */ 2524 2525 DBPRINT(sc,BCE_INFO_LOAD, 2526 "bce_init_nvram(): Flash WAS reconfigured.\n"); 2527 2528 for (j = 0, flash = &flash_table[0]; j < entry_count; 2529 j++, flash++) { 2530 if ((val & FLASH_BACKUP_STRAP_MASK) == 2531 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) { 2532 sc->bce_flash_info = flash; 2533 break; 2534 } 2535 } 2536 } else { 2537 /* Flash interface not yet reconfigured. */ 2538 u32 mask; 2539 2540 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Flash was NOT reconfigured.\n", 2541 __FUNCTION__); 2542 2543 if (val & (1 << 23)) 2544 mask = FLASH_BACKUP_STRAP_MASK; 2545 else 2546 mask = FLASH_STRAP_MASK; 2547 2548 /* Look for the matching NVRAM device configuration data. */ 2549 for (j = 0, flash = &flash_table[0]; j < entry_count; j++, flash++) { 2550 2551 /* Check if the device matches any of the known devices. */ 2552 if ((val & mask) == (flash->strapping & mask)) { 2553 /* Found a device match. */ 2554 sc->bce_flash_info = flash; 2555 2556 /* Request access to the flash interface. */ 2557 if ((rc = bce_acquire_nvram_lock(sc)) != 0) 2558 return rc; 2559 2560 /* Reconfigure the flash interface. */ 2561 bce_enable_nvram_access(sc); 2562 REG_WR(sc, BCE_NVM_CFG1, flash->config1); 2563 REG_WR(sc, BCE_NVM_CFG2, flash->config2); 2564 REG_WR(sc, BCE_NVM_CFG3, flash->config3); 2565 REG_WR(sc, BCE_NVM_WRITE1, flash->write1); 2566 bce_disable_nvram_access(sc); 2567 bce_release_nvram_lock(sc); 2568 2569 break; 2570 } 2571 } 2572 } 2573 2574 /* Check if a matching device was found. */ 2575 if (j == entry_count) { 2576 sc->bce_flash_info = NULL; 2577 BCE_PRINTF("%s(%d): Unknown Flash NVRAM found!\n", 2578 __FILE__, __LINE__); 2579 DBEXIT(BCE_VERBOSE_NVRAM); 2580 return (ENODEV); 2581 } 2582 2583bce_init_nvram_get_flash_size: 2584 /* Write the flash config data to the shared memory interface. */ 2585 val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG2); 2586 val &= BCE_SHARED_HW_CFG2_NVM_SIZE_MASK; 2587 if (val) 2588 sc->bce_flash_size = val; 2589 else 2590 sc->bce_flash_size = sc->bce_flash_info->total_size; 2591 2592 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Found %s, size = 0x%08X\n", 2593 __FUNCTION__, sc->bce_flash_info->name, 2594 sc->bce_flash_info->total_size); 2595 2596 DBEXIT(BCE_VERBOSE_NVRAM); 2597 return rc; 2598} 2599 2600 2601/****************************************************************************/ 2602/* Read an arbitrary range of data from NVRAM. */ 2603/* */ 2604/* Prepares the NVRAM interface for access and reads the requested data */ 2605/* into the supplied buffer. */ 2606/* */ 2607/* Returns: */ 2608/* 0 on success and the data read, positive value on failure. */ 2609/****************************************************************************/ 2610static int 2611bce_nvram_read(struct bce_softc *sc, u32 offset, u8 *ret_buf, 2612 int buf_size) 2613{ 2614 int rc = 0; 2615 u32 cmd_flags, offset32, len32, extra; 2616 2617 DBENTER(BCE_VERBOSE_NVRAM); 2618 2619 if (buf_size == 0) 2620 goto bce_nvram_read_exit; 2621 2622 /* Request access to the flash interface. */ 2623 if ((rc = bce_acquire_nvram_lock(sc)) != 0) 2624 goto bce_nvram_read_exit; 2625 2626 /* Enable access to flash interface */ 2627 bce_enable_nvram_access(sc); 2628 2629 len32 = buf_size; 2630 offset32 = offset; 2631 extra = 0; 2632 2633 cmd_flags = 0; 2634 2635 if (offset32 & 3) { 2636 u8 buf[4]; 2637 u32 pre_len; 2638 2639 offset32 &= ~3; 2640 pre_len = 4 - (offset & 3); 2641 2642 if (pre_len >= len32) { 2643 pre_len = len32; 2644 cmd_flags = BCE_NVM_COMMAND_FIRST | BCE_NVM_COMMAND_LAST; 2645 } 2646 else { 2647 cmd_flags = BCE_NVM_COMMAND_FIRST; 2648 } 2649 2650 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 2651 2652 if (rc) 2653 return rc; 2654 2655 memcpy(ret_buf, buf + (offset & 3), pre_len); 2656 2657 offset32 += 4; 2658 ret_buf += pre_len; 2659 len32 -= pre_len; 2660 } 2661 2662 if (len32 & 3) { 2663 extra = 4 - (len32 & 3); 2664 len32 = (len32 + 4) & ~3; 2665 } 2666 2667 if (len32 == 4) { 2668 u8 buf[4]; 2669 2670 if (cmd_flags) 2671 cmd_flags = BCE_NVM_COMMAND_LAST; 2672 else 2673 cmd_flags = BCE_NVM_COMMAND_FIRST | 2674 BCE_NVM_COMMAND_LAST; 2675 2676 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 2677 2678 memcpy(ret_buf, buf, 4 - extra); 2679 } 2680 else if (len32 > 0) { 2681 u8 buf[4]; 2682 2683 /* Read the first word. */ 2684 if (cmd_flags) 2685 cmd_flags = 0; 2686 else 2687 cmd_flags = BCE_NVM_COMMAND_FIRST; 2688 2689 rc = bce_nvram_read_dword(sc, offset32, ret_buf, cmd_flags); 2690 2691 /* Advance to the next dword. */ 2692 offset32 += 4; 2693 ret_buf += 4; 2694 len32 -= 4; 2695 2696 while (len32 > 4 && rc == 0) { 2697 rc = bce_nvram_read_dword(sc, offset32, ret_buf, 0); 2698 2699 /* Advance to the next dword. */ 2700 offset32 += 4; 2701 ret_buf += 4; 2702 len32 -= 4; 2703 } 2704 2705 if (rc) 2706 goto bce_nvram_read_locked_exit; 2707 2708 cmd_flags = BCE_NVM_COMMAND_LAST; 2709 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 2710 2711 memcpy(ret_buf, buf, 4 - extra); 2712 } 2713 2714bce_nvram_read_locked_exit: 2715 /* Disable access to flash interface and release the lock. */ 2716 bce_disable_nvram_access(sc); 2717 bce_release_nvram_lock(sc); 2718 2719bce_nvram_read_exit: 2720 DBEXIT(BCE_VERBOSE_NVRAM); 2721 return rc; 2722} 2723 2724 2725#ifdef BCE_NVRAM_WRITE_SUPPORT 2726/****************************************************************************/ 2727/* Write an arbitrary range of data from NVRAM. */ 2728/* */ 2729/* Prepares the NVRAM interface for write access and writes the requested */ 2730/* data from the supplied buffer. The caller is responsible for */ 2731/* calculating any appropriate CRCs. */ 2732/* */ 2733/* Returns: */ 2734/* 0 on success, positive value on failure. */ 2735/****************************************************************************/ 2736static int 2737bce_nvram_write(struct bce_softc *sc, u32 offset, u8 *data_buf, 2738 int buf_size) 2739{ 2740 u32 written, offset32, len32; 2741 u8 *buf, start[4], end[4]; 2742 int rc = 0; 2743 int align_start, align_end; 2744 2745 DBENTER(BCE_VERBOSE_NVRAM); 2746 2747 buf = data_buf; 2748 offset32 = offset; 2749 len32 = buf_size; 2750 align_start = align_end = 0; 2751 2752 if ((align_start = (offset32 & 3))) { 2753 offset32 &= ~3; 2754 len32 += align_start; 2755 if ((rc = bce_nvram_read(sc, offset32, start, 4))) 2756 goto bce_nvram_write_exit; 2757 } 2758 2759 if (len32 & 3) { 2760 if ((len32 > 4) || !align_start) { 2761 align_end = 4 - (len32 & 3); 2762 len32 += align_end; 2763 if ((rc = bce_nvram_read(sc, offset32 + len32 - 4, 2764 end, 4))) { 2765 goto bce_nvram_write_exit; 2766 } 2767 } 2768 } 2769 2770 if (align_start || align_end) { 2771 buf = malloc(len32, M_DEVBUF, M_NOWAIT); 2772 if (buf == 0) { 2773 rc = ENOMEM; 2774 goto bce_nvram_write_exit; 2775 } 2776 2777 if (align_start) { 2778 memcpy(buf, start, 4); 2779 } 2780 2781 if (align_end) { 2782 memcpy(buf + len32 - 4, end, 4); 2783 } 2784 memcpy(buf + align_start, data_buf, buf_size); 2785 } 2786 2787 written = 0; 2788 while ((written < len32) && (rc == 0)) { 2789 u32 page_start, page_end, data_start, data_end; 2790 u32 addr, cmd_flags; 2791 int i; 2792 u8 flash_buffer[264]; 2793 2794 /* Find the page_start addr */ 2795 page_start = offset32 + written; 2796 page_start -= (page_start % sc->bce_flash_info->page_size); 2797 /* Find the page_end addr */ 2798 page_end = page_start + sc->bce_flash_info->page_size; 2799 /* Find the data_start addr */ 2800 data_start = (written == 0) ? offset32 : page_start; 2801 /* Find the data_end addr */ 2802 data_end = (page_end > offset32 + len32) ? 2803 (offset32 + len32) : page_end; 2804 2805 /* Request access to the flash interface. */ 2806 if ((rc = bce_acquire_nvram_lock(sc)) != 0) 2807 goto bce_nvram_write_exit; 2808 2809 /* Enable access to flash interface */ 2810 bce_enable_nvram_access(sc); 2811 2812 cmd_flags = BCE_NVM_COMMAND_FIRST; 2813 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2814 int j; 2815 2816 /* Read the whole page into the buffer 2817 * (non-buffer flash only) */ 2818 for (j = 0; j < sc->bce_flash_info->page_size; j += 4) { 2819 if (j == (sc->bce_flash_info->page_size - 4)) { 2820 cmd_flags |= BCE_NVM_COMMAND_LAST; 2821 } 2822 rc = bce_nvram_read_dword(sc, 2823 page_start + j, 2824 &flash_buffer[j], 2825 cmd_flags); 2826 2827 if (rc) 2828 goto bce_nvram_write_locked_exit; 2829 2830 cmd_flags = 0; 2831 } 2832 } 2833 2834 /* Enable writes to flash interface (unlock write-protect) */ 2835 if ((rc = bce_enable_nvram_write(sc)) != 0) 2836 goto bce_nvram_write_locked_exit; 2837 2838 /* Erase the page */ 2839 if ((rc = bce_nvram_erase_page(sc, page_start)) != 0) 2840 goto bce_nvram_write_locked_exit; 2841 2842 /* Re-enable the write again for the actual write */ 2843 bce_enable_nvram_write(sc); 2844 2845 /* Loop to write back the buffer data from page_start to 2846 * data_start */ 2847 i = 0; 2848 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2849 for (addr = page_start; addr < data_start; 2850 addr += 4, i += 4) { 2851 2852 rc = bce_nvram_write_dword(sc, addr, 2853 &flash_buffer[i], cmd_flags); 2854 2855 if (rc != 0) 2856 goto bce_nvram_write_locked_exit; 2857 2858 cmd_flags = 0; 2859 } 2860 } 2861 2862 /* Loop to write the new data from data_start to data_end */ 2863 for (addr = data_start; addr < data_end; addr += 4, i++) { 2864 if ((addr == page_end - 4) || 2865 ((sc->bce_flash_info->flags & BCE_NV_BUFFERED) && 2866 (addr == data_end - 4))) { 2867 2868 cmd_flags |= BCE_NVM_COMMAND_LAST; 2869 } 2870 rc = bce_nvram_write_dword(sc, addr, buf, 2871 cmd_flags); 2872 2873 if (rc != 0) 2874 goto bce_nvram_write_locked_exit; 2875 2876 cmd_flags = 0; 2877 buf += 4; 2878 } 2879 2880 /* Loop to write back the buffer data from data_end 2881 * to page_end */ 2882 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2883 for (addr = data_end; addr < page_end; 2884 addr += 4, i += 4) { 2885 2886 if (addr == page_end-4) { 2887 cmd_flags = BCE_NVM_COMMAND_LAST; 2888 } 2889 rc = bce_nvram_write_dword(sc, addr, 2890 &flash_buffer[i], cmd_flags); 2891 2892 if (rc != 0) 2893 goto bce_nvram_write_locked_exit; 2894 2895 cmd_flags = 0; 2896 } 2897 } 2898 2899 /* Disable writes to flash interface (lock write-protect) */ 2900 bce_disable_nvram_write(sc); 2901 2902 /* Disable access to flash interface */ 2903 bce_disable_nvram_access(sc); 2904 bce_release_nvram_lock(sc); 2905 2906 /* Increment written */ 2907 written += data_end - data_start; 2908 } 2909 2910 goto bce_nvram_write_exit; 2911 2912bce_nvram_write_locked_exit: 2913 bce_disable_nvram_write(sc); 2914 bce_disable_nvram_access(sc); 2915 bce_release_nvram_lock(sc); 2916 2917bce_nvram_write_exit: 2918 if (align_start || align_end) 2919 free(buf, M_DEVBUF); 2920 2921 DBEXIT(BCE_VERBOSE_NVRAM); 2922 return (rc); 2923} 2924#endif /* BCE_NVRAM_WRITE_SUPPORT */ 2925 2926 2927/****************************************************************************/ 2928/* Verifies that NVRAM is accessible and contains valid data. */ 2929/* */ 2930/* Reads the configuration data from NVRAM and verifies that the CRC is */ 2931/* correct. */ 2932/* */ 2933/* Returns: */ 2934/* 0 on success, positive value on failure. */ 2935/****************************************************************************/ 2936static int 2937bce_nvram_test(struct bce_softc *sc) 2938{ 2939 u32 buf[BCE_NVRAM_SIZE / 4]; 2940 u8 *data = (u8 *) buf; 2941 int rc = 0; 2942 u32 magic, csum; 2943 2944 DBENTER(BCE_VERBOSE_NVRAM | BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 2945 2946 /* 2947 * Check that the device NVRAM is valid by reading 2948 * the magic value at offset 0. 2949 */ 2950 if ((rc = bce_nvram_read(sc, 0, data, 4)) != 0) { 2951 BCE_PRINTF("%s(%d): Unable to read NVRAM!\n", 2952 __FILE__, __LINE__); 2953 goto bce_nvram_test_exit; 2954 } 2955 2956 /* 2957 * Verify that offset 0 of the NVRAM contains 2958 * a valid magic number. 2959 */ 2960 magic = bce_be32toh(buf[0]); 2961 if (magic != BCE_NVRAM_MAGIC) { 2962 rc = ENODEV; 2963 BCE_PRINTF("%s(%d): Invalid NVRAM magic value! " 2964 "Expected: 0x%08X, Found: 0x%08X\n", 2965 __FILE__, __LINE__, BCE_NVRAM_MAGIC, magic); 2966 goto bce_nvram_test_exit; 2967 } 2968 2969 /* 2970 * Verify that the device NVRAM includes valid 2971 * configuration data. 2972 */ 2973 if ((rc = bce_nvram_read(sc, 0x100, data, BCE_NVRAM_SIZE)) != 0) { 2974 BCE_PRINTF("%s(%d): Unable to read manufacturing " 2975 "Information from NVRAM!\n", __FILE__, __LINE__); 2976 goto bce_nvram_test_exit; 2977 } 2978 2979 csum = ether_crc32_le(data, 0x100); 2980 if (csum != BCE_CRC32_RESIDUAL) { 2981 rc = ENODEV; 2982 BCE_PRINTF("%s(%d): Invalid manufacturing information " 2983 "NVRAM CRC! Expected: 0x%08X, Found: 0x%08X\n", 2984 __FILE__, __LINE__, BCE_CRC32_RESIDUAL, csum); 2985 goto bce_nvram_test_exit; 2986 } 2987 2988 csum = ether_crc32_le(data + 0x100, 0x100); 2989 if (csum != BCE_CRC32_RESIDUAL) { 2990 rc = ENODEV; 2991 BCE_PRINTF("%s(%d): Invalid feature configuration " 2992 "information NVRAM CRC! Expected: 0x%08X, " 2993 "Found: 08%08X\n", __FILE__, __LINE__, 2994 BCE_CRC32_RESIDUAL, csum); 2995 } 2996 2997bce_nvram_test_exit: 2998 DBEXIT(BCE_VERBOSE_NVRAM | BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 2999 return rc; 3000} 3001 3002 3003/****************************************************************************/ 3004/* Calculates the size of the buffers to allocate based on the MTU. */ 3005/* */ 3006/* Returns: */ 3007/* Nothing. */ 3008/****************************************************************************/ 3009static void 3010bce_get_rx_buffer_sizes(struct bce_softc *sc, int mtu) 3011{ 3012 DBENTER(BCE_VERBOSE_LOAD); 3013 3014 /* Use a single allocation type when header splitting enabled. */ 3015 if (bce_hdr_split == TRUE) { 3016 sc->rx_bd_mbuf_alloc_size = MHLEN; 3017 /* Make sure offset is 16 byte aligned for hardware. */ 3018 sc->rx_bd_mbuf_align_pad = 3019 roundup2((MSIZE - MHLEN), 16) - (MSIZE - MHLEN); 3020 sc->rx_bd_mbuf_data_len = sc->rx_bd_mbuf_alloc_size - 3021 sc->rx_bd_mbuf_align_pad; 3022 } else { 3023 if ((mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + 3024 ETHER_CRC_LEN) > MCLBYTES) { 3025 /* Setup for jumbo RX buffer allocations. */ 3026 sc->rx_bd_mbuf_alloc_size = MJUM9BYTES; 3027 sc->rx_bd_mbuf_align_pad = 3028 roundup2(MJUM9BYTES, 16) - MJUM9BYTES; 3029 sc->rx_bd_mbuf_data_len = 3030 sc->rx_bd_mbuf_alloc_size - 3031 sc->rx_bd_mbuf_align_pad; 3032 } else { 3033 /* Setup for standard RX buffer allocations. */ 3034 sc->rx_bd_mbuf_alloc_size = MCLBYTES; 3035 sc->rx_bd_mbuf_align_pad = 3036 roundup2(MCLBYTES, 16) - MCLBYTES; 3037 sc->rx_bd_mbuf_data_len = 3038 sc->rx_bd_mbuf_alloc_size - 3039 sc->rx_bd_mbuf_align_pad; 3040 } 3041 } 3042 3043// DBPRINT(sc, BCE_INFO_LOAD, 3044 DBPRINT(sc, BCE_WARN, 3045 "%s(): rx_bd_mbuf_alloc_size = %d, rx_bd_mbuf_data_len = %d, " 3046 "rx_bd_mbuf_align_pad = %d\n", __FUNCTION__, 3047 sc->rx_bd_mbuf_alloc_size, sc->rx_bd_mbuf_data_len, 3048 sc->rx_bd_mbuf_align_pad); 3049 3050 DBEXIT(BCE_VERBOSE_LOAD); 3051} 3052 3053/****************************************************************************/ 3054/* Identifies the current media type of the controller and sets the PHY */ 3055/* address. */ 3056/* */ 3057/* Returns: */ 3058/* Nothing. */ 3059/****************************************************************************/ 3060static void 3061bce_get_media(struct bce_softc *sc) 3062{ 3063 u32 val; 3064 3065 DBENTER(BCE_VERBOSE_PHY); 3066 3067 /* Assume PHY address for copper controllers. */ 3068 sc->bce_phy_addr = 1; 3069 3070 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 3071 u32 val = REG_RD(sc, BCE_MISC_DUAL_MEDIA_CTRL); 3072 u32 bond_id = val & BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID; 3073 u32 strap; 3074 3075 /* 3076 * The BCM5709S is software configurable 3077 * for Copper or SerDes operation. 3078 */ 3079 if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) { 3080 DBPRINT(sc, BCE_INFO_LOAD, "5709 bonded " 3081 "for copper.\n"); 3082 goto bce_get_media_exit; 3083 } else if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) { 3084 DBPRINT(sc, BCE_INFO_LOAD, "5709 bonded " 3085 "for dual media.\n"); 3086 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 3087 goto bce_get_media_exit; 3088 } 3089 3090 if (val & BCE_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE) 3091 strap = (val & 3092 BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21; 3093 else 3094 strap = (val & 3095 BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8; 3096 3097 if (pci_get_function(sc->bce_dev) == 0) { 3098 switch (strap) { 3099 case 0x4: 3100 case 0x5: 3101 case 0x6: 3102 DBPRINT(sc, BCE_INFO_LOAD, 3103 "BCM5709 s/w configured for SerDes.\n"); 3104 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 3105 break; 3106 default: 3107 DBPRINT(sc, BCE_INFO_LOAD, 3108 "BCM5709 s/w configured for Copper.\n"); 3109 break; 3110 } 3111 } else { 3112 switch (strap) { 3113 case 0x1: 3114 case 0x2: 3115 case 0x4: 3116 DBPRINT(sc, BCE_INFO_LOAD, 3117 "BCM5709 s/w configured for SerDes.\n"); 3118 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 3119 break; 3120 default: 3121 DBPRINT(sc, BCE_INFO_LOAD, 3122 "BCM5709 s/w configured for Copper.\n"); 3123 break; 3124 } 3125 } 3126 3127 } else if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT) 3128 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 3129 3130 if (sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) { 3131 3132 sc->bce_flags |= BCE_NO_WOL_FLAG; 3133 3134 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) 3135 sc->bce_phy_flags |= BCE_PHY_IEEE_CLAUSE_45_FLAG; 3136 3137 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) { 3138 /* 5708S/09S/16S use a separate PHY for SerDes. */ 3139 sc->bce_phy_addr = 2; 3140 3141 val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG); 3142 if (val & BCE_SHARED_HW_CFG_PHY_2_5G) { 3143 sc->bce_phy_flags |= 3144 BCE_PHY_2_5G_CAPABLE_FLAG; 3145 DBPRINT(sc, BCE_INFO_LOAD, "Found 2.5Gb " 3146 "capable adapter\n"); 3147 } 3148 } 3149 } else if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) || 3150 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)) 3151 sc->bce_phy_flags |= BCE_PHY_CRC_FIX_FLAG; 3152 3153bce_get_media_exit: 3154 DBPRINT(sc, (BCE_INFO_LOAD | BCE_INFO_PHY), 3155 "Using PHY address %d.\n", sc->bce_phy_addr); 3156 3157 DBEXIT(BCE_VERBOSE_PHY); 3158} 3159 3160 3161/****************************************************************************/ 3162/* Performs PHY initialization required before MII drivers access the */ 3163/* device. */ 3164/* */ 3165/* Returns: */ 3166/* Nothing. */ 3167/****************************************************************************/ 3168static void 3169bce_init_media(struct bce_softc *sc) 3170{ 3171 if ((sc->bce_phy_flags & (BCE_PHY_IEEE_CLAUSE_45_FLAG | 3172 BCE_PHY_REMOTE_CAP_FLAG)) == BCE_PHY_IEEE_CLAUSE_45_FLAG) { 3173 /* 3174 * Configure 5709S/5716S PHYs to use traditional IEEE 3175 * Clause 22 method. Otherwise we have no way to attach 3176 * the PHY in mii(4) layer. PHY specific configuration 3177 * is done in mii layer. 3178 */ 3179 3180 /* Select auto-negotiation MMD of the PHY. */ 3181 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr, 3182 BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_ADDR_EXT); 3183 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr, 3184 BRGPHY_ADDR_EXT, BRGPHY_ADDR_EXT_AN_MMD); 3185 3186 /* Set IEEE0 block of AN MMD (assumed in brgphy(4) code). */ 3187 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr, 3188 BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 3189 } 3190} 3191 3192 3193/****************************************************************************/ 3194/* Free any DMA memory owned by the driver. */ 3195/* */ 3196/* Scans through each data structre that requires DMA memory and frees */ 3197/* the memory if allocated. */ 3198/* */ 3199/* Returns: */ 3200/* Nothing. */ 3201/****************************************************************************/ 3202static void 3203bce_dma_free(struct bce_softc *sc) 3204{ 3205 int i; 3206 3207 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_UNLOAD | BCE_VERBOSE_CTX); 3208 3209 /* Free, unmap, and destroy the status block. */ 3210 if (sc->status_block != NULL) { 3211 bus_dmamem_free( 3212 sc->status_tag, 3213 sc->status_block, 3214 sc->status_map); 3215 sc->status_block = NULL; 3216 } 3217 3218 if (sc->status_map != NULL) { 3219 bus_dmamap_unload( 3220 sc->status_tag, 3221 sc->status_map); 3222 bus_dmamap_destroy(sc->status_tag, 3223 sc->status_map); 3224 sc->status_map = NULL; 3225 } 3226 3227 if (sc->status_tag != NULL) { 3228 bus_dma_tag_destroy(sc->status_tag); 3229 sc->status_tag = NULL; 3230 } 3231 3232 3233 /* Free, unmap, and destroy the statistics block. */ 3234 if (sc->stats_block != NULL) { 3235 bus_dmamem_free( 3236 sc->stats_tag, 3237 sc->stats_block, 3238 sc->stats_map); 3239 sc->stats_block = NULL; 3240 } 3241 3242 if (sc->stats_map != NULL) { 3243 bus_dmamap_unload( 3244 sc->stats_tag, 3245 sc->stats_map); 3246 bus_dmamap_destroy(sc->stats_tag, 3247 sc->stats_map); 3248 sc->stats_map = NULL; 3249 } 3250 3251 if (sc->stats_tag != NULL) { 3252 bus_dma_tag_destroy(sc->stats_tag); 3253 sc->stats_tag = NULL; 3254 } 3255 3256 3257 /* Free, unmap and destroy all context memory pages. */ 3258 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 3259 for (i = 0; i < sc->ctx_pages; i++ ) { 3260 if (sc->ctx_block[i] != NULL) { 3261 bus_dmamem_free( 3262 sc->ctx_tag, 3263 sc->ctx_block[i], 3264 sc->ctx_map[i]); 3265 sc->ctx_block[i] = NULL; 3266 } 3267 3268 if (sc->ctx_map[i] != NULL) { 3269 bus_dmamap_unload( 3270 sc->ctx_tag, 3271 sc->ctx_map[i]); 3272 bus_dmamap_destroy( 3273 sc->ctx_tag, 3274 sc->ctx_map[i]); 3275 sc->ctx_map[i] = NULL; 3276 } 3277 } 3278 3279 /* Destroy the context memory tag. */ 3280 if (sc->ctx_tag != NULL) { 3281 bus_dma_tag_destroy(sc->ctx_tag); 3282 sc->ctx_tag = NULL; 3283 } 3284 } 3285 3286 3287 /* Free, unmap and destroy all TX buffer descriptor chain pages. */ 3288 for (i = 0; i < sc->tx_pages; i++ ) { 3289 if (sc->tx_bd_chain[i] != NULL) { 3290 bus_dmamem_free( 3291 sc->tx_bd_chain_tag, 3292 sc->tx_bd_chain[i], 3293 sc->tx_bd_chain_map[i]); 3294 sc->tx_bd_chain[i] = NULL; 3295 } 3296 3297 if (sc->tx_bd_chain_map[i] != NULL) { 3298 bus_dmamap_unload( 3299 sc->tx_bd_chain_tag, 3300 sc->tx_bd_chain_map[i]); 3301 bus_dmamap_destroy( 3302 sc->tx_bd_chain_tag, 3303 sc->tx_bd_chain_map[i]); 3304 sc->tx_bd_chain_map[i] = NULL; 3305 } 3306 } 3307 3308 /* Destroy the TX buffer descriptor tag. */ 3309 if (sc->tx_bd_chain_tag != NULL) { 3310 bus_dma_tag_destroy(sc->tx_bd_chain_tag); 3311 sc->tx_bd_chain_tag = NULL; 3312 } 3313 3314 3315 /* Free, unmap and destroy all RX buffer descriptor chain pages. */ 3316 for (i = 0; i < sc->rx_pages; i++ ) { 3317 if (sc->rx_bd_chain[i] != NULL) { 3318 bus_dmamem_free( 3319 sc->rx_bd_chain_tag, 3320 sc->rx_bd_chain[i], 3321 sc->rx_bd_chain_map[i]); 3322 sc->rx_bd_chain[i] = NULL; 3323 } 3324 3325 if (sc->rx_bd_chain_map[i] != NULL) { 3326 bus_dmamap_unload( 3327 sc->rx_bd_chain_tag, 3328 sc->rx_bd_chain_map[i]); 3329 bus_dmamap_destroy( 3330 sc->rx_bd_chain_tag, 3331 sc->rx_bd_chain_map[i]); 3332 sc->rx_bd_chain_map[i] = NULL; 3333 } 3334 } 3335 3336 /* Destroy the RX buffer descriptor tag. */ 3337 if (sc->rx_bd_chain_tag != NULL) { 3338 bus_dma_tag_destroy(sc->rx_bd_chain_tag); 3339 sc->rx_bd_chain_tag = NULL; 3340 } 3341 3342 3343 /* Free, unmap and destroy all page buffer descriptor chain pages. */ 3344 if (bce_hdr_split == TRUE) { 3345 for (i = 0; i < sc->pg_pages; i++ ) { 3346 if (sc->pg_bd_chain[i] != NULL) { 3347 bus_dmamem_free( 3348 sc->pg_bd_chain_tag, 3349 sc->pg_bd_chain[i], 3350 sc->pg_bd_chain_map[i]); 3351 sc->pg_bd_chain[i] = NULL; 3352 } 3353 3354 if (sc->pg_bd_chain_map[i] != NULL) { 3355 bus_dmamap_unload( 3356 sc->pg_bd_chain_tag, 3357 sc->pg_bd_chain_map[i]); 3358 bus_dmamap_destroy( 3359 sc->pg_bd_chain_tag, 3360 sc->pg_bd_chain_map[i]); 3361 sc->pg_bd_chain_map[i] = NULL; 3362 } 3363 } 3364 3365 /* Destroy the page buffer descriptor tag. */ 3366 if (sc->pg_bd_chain_tag != NULL) { 3367 bus_dma_tag_destroy(sc->pg_bd_chain_tag); 3368 sc->pg_bd_chain_tag = NULL; 3369 } 3370 } 3371 3372 3373 /* Unload and destroy the TX mbuf maps. */ 3374 for (i = 0; i < MAX_TX_BD_AVAIL; i++) { 3375 if (sc->tx_mbuf_map[i] != NULL) { 3376 bus_dmamap_unload(sc->tx_mbuf_tag, 3377 sc->tx_mbuf_map[i]); 3378 bus_dmamap_destroy(sc->tx_mbuf_tag, 3379 sc->tx_mbuf_map[i]); 3380 sc->tx_mbuf_map[i] = NULL; 3381 } 3382 } 3383 3384 /* Destroy the TX mbuf tag. */ 3385 if (sc->tx_mbuf_tag != NULL) { 3386 bus_dma_tag_destroy(sc->tx_mbuf_tag); 3387 sc->tx_mbuf_tag = NULL; 3388 } 3389 3390 /* Unload and destroy the RX mbuf maps. */ 3391 for (i = 0; i < MAX_RX_BD_AVAIL; i++) { 3392 if (sc->rx_mbuf_map[i] != NULL) { 3393 bus_dmamap_unload(sc->rx_mbuf_tag, 3394 sc->rx_mbuf_map[i]); 3395 bus_dmamap_destroy(sc->rx_mbuf_tag, 3396 sc->rx_mbuf_map[i]); 3397 sc->rx_mbuf_map[i] = NULL; 3398 } 3399 } 3400 3401 /* Destroy the RX mbuf tag. */ 3402 if (sc->rx_mbuf_tag != NULL) { 3403 bus_dma_tag_destroy(sc->rx_mbuf_tag); 3404 sc->rx_mbuf_tag = NULL; 3405 } 3406 3407 /* Unload and destroy the page mbuf maps. */ 3408 if (bce_hdr_split == TRUE) { 3409 for (i = 0; i < MAX_PG_BD_AVAIL; i++) { 3410 if (sc->pg_mbuf_map[i] != NULL) { 3411 bus_dmamap_unload(sc->pg_mbuf_tag, 3412 sc->pg_mbuf_map[i]); 3413 bus_dmamap_destroy(sc->pg_mbuf_tag, 3414 sc->pg_mbuf_map[i]); 3415 sc->pg_mbuf_map[i] = NULL; 3416 } 3417 } 3418 3419 /* Destroy the page mbuf tag. */ 3420 if (sc->pg_mbuf_tag != NULL) { 3421 bus_dma_tag_destroy(sc->pg_mbuf_tag); 3422 sc->pg_mbuf_tag = NULL; 3423 } 3424 } 3425 3426 /* Destroy the parent tag */ 3427 if (sc->parent_tag != NULL) { 3428 bus_dma_tag_destroy(sc->parent_tag); 3429 sc->parent_tag = NULL; 3430 } 3431 3432 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_UNLOAD | BCE_VERBOSE_CTX); 3433} 3434 3435 3436/****************************************************************************/ 3437/* Get DMA memory from the OS. */ 3438/* */ 3439/* Validates that the OS has provided DMA buffers in response to a */ 3440/* bus_dmamap_load() call and saves the physical address of those buffers. */ 3441/* When the callback is used the OS will return 0 for the mapping function */ 3442/* (bus_dmamap_load()) so we use the value of map_arg->maxsegs to pass any */ 3443/* failures back to the caller. */ 3444/* */ 3445/* Returns: */ 3446/* Nothing. */ 3447/****************************************************************************/ 3448static void 3449bce_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 3450{ 3451 bus_addr_t *busaddr = arg; 3452 3453 KASSERT(nseg == 1, ("%s(): Too many segments returned (%d)!", 3454 __FUNCTION__, nseg)); 3455 /* Simulate a mapping failure. */ 3456 DBRUNIF(DB_RANDOMTRUE(dma_map_addr_failed_sim_control), 3457 error = ENOMEM); 3458 3459 /* ToDo: How to increment debug sim_count variable here? */ 3460 3461 /* Check for an error and signal the caller that an error occurred. */ 3462 if (error) { 3463 *busaddr = 0; 3464 } else { 3465 *busaddr = segs->ds_addr; 3466 } 3467} 3468 3469 3470/****************************************************************************/ 3471/* Allocate any DMA memory needed by the driver. */ 3472/* */ 3473/* Allocates DMA memory needed for the various global structures needed by */ 3474/* hardware. */ 3475/* */ 3476/* Memory alignment requirements: */ 3477/* +-----------------+----------+----------+----------+----------+ */ 3478/* | | 5706 | 5708 | 5709 | 5716 | */ 3479/* +-----------------+----------+----------+----------+----------+ */ 3480/* |Status Block | 8 bytes | 8 bytes | 16 bytes | 16 bytes | */ 3481/* |Statistics Block | 8 bytes | 8 bytes | 16 bytes | 16 bytes | */ 3482/* |RX Buffers | 16 bytes | 16 bytes | 16 bytes | 16 bytes | */ 3483/* |PG Buffers | none | none | none | none | */ 3484/* |TX Buffers | none | none | none | none | */ 3485/* |Chain Pages(1) | 4KiB | 4KiB | 4KiB | 4KiB | */ 3486/* |Context Memory | | | | | */ 3487/* +-----------------+----------+----------+----------+----------+ */ 3488/* */ 3489/* (1) Must align with CPU page size (BCM_PAGE_SZIE). */ 3490/* */ 3491/* Returns: */ 3492/* 0 for success, positive value for failure. */ 3493/****************************************************************************/ 3494static int 3495bce_dma_alloc(device_t dev) 3496{ 3497 struct bce_softc *sc; 3498 int i, error, rc = 0; 3499 bus_size_t max_size, max_seg_size; 3500 int max_segments; 3501 3502 sc = device_get_softc(dev); 3503 3504 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 3505 3506 /* 3507 * Allocate the parent bus DMA tag appropriate for PCI. 3508 */ 3509 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1, BCE_DMA_BOUNDARY, 3510 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, 3511 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, 3512 &sc->parent_tag)) { 3513 BCE_PRINTF("%s(%d): Could not allocate parent DMA tag!\n", 3514 __FILE__, __LINE__); 3515 rc = ENOMEM; 3516 goto bce_dma_alloc_exit; 3517 } 3518 3519 /* 3520 * Create a DMA tag for the status block, allocate and clear the 3521 * memory, map the memory into DMA space, and fetch the physical 3522 * address of the block. 3523 */ 3524 if (bus_dma_tag_create(sc->parent_tag, BCE_DMA_ALIGN, 3525 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, 3526 NULL, NULL, BCE_STATUS_BLK_SZ, 1, BCE_STATUS_BLK_SZ, 3527 0, NULL, NULL, &sc->status_tag)) { 3528 BCE_PRINTF("%s(%d): Could not allocate status block " 3529 "DMA tag!\n", __FILE__, __LINE__); 3530 rc = ENOMEM; 3531 goto bce_dma_alloc_exit; 3532 } 3533 3534 if(bus_dmamem_alloc(sc->status_tag, (void **)&sc->status_block, 3535 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3536 &sc->status_map)) { 3537 BCE_PRINTF("%s(%d): Could not allocate status block " 3538 "DMA memory!\n", __FILE__, __LINE__); 3539 rc = ENOMEM; 3540 goto bce_dma_alloc_exit; 3541 } 3542 3543 error = bus_dmamap_load(sc->status_tag, sc->status_map, 3544 sc->status_block, BCE_STATUS_BLK_SZ, bce_dma_map_addr, 3545 &sc->status_block_paddr, BUS_DMA_NOWAIT); 3546 3547 if (error || sc->status_block_paddr == 0) { 3548 BCE_PRINTF("%s(%d): Could not map status block " 3549 "DMA memory!\n", __FILE__, __LINE__); 3550 rc = ENOMEM; 3551 goto bce_dma_alloc_exit; 3552 } 3553 3554 DBPRINT(sc, BCE_INFO_LOAD, "%s(): status_block_paddr = 0x%jX\n", 3555 __FUNCTION__, (uintmax_t) sc->status_block_paddr); 3556 3557 /* 3558 * Create a DMA tag for the statistics block, allocate and clear the 3559 * memory, map the memory into DMA space, and fetch the physical 3560 * address of the block. 3561 */ 3562 if (bus_dma_tag_create(sc->parent_tag, BCE_DMA_ALIGN, 3563 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, 3564 NULL, NULL, BCE_STATS_BLK_SZ, 1, BCE_STATS_BLK_SZ, 3565 0, NULL, NULL, &sc->stats_tag)) { 3566 BCE_PRINTF("%s(%d): Could not allocate statistics block " 3567 "DMA tag!\n", __FILE__, __LINE__); 3568 rc = ENOMEM; 3569 goto bce_dma_alloc_exit; 3570 } 3571 3572 if (bus_dmamem_alloc(sc->stats_tag, (void **)&sc->stats_block, 3573 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->stats_map)) { 3574 BCE_PRINTF("%s(%d): Could not allocate statistics block " 3575 "DMA memory!\n", __FILE__, __LINE__); 3576 rc = ENOMEM; 3577 goto bce_dma_alloc_exit; 3578 } 3579 3580 error = bus_dmamap_load(sc->stats_tag, sc->stats_map, 3581 sc->stats_block, BCE_STATS_BLK_SZ, bce_dma_map_addr, 3582 &sc->stats_block_paddr, BUS_DMA_NOWAIT); 3583 3584 if (error || sc->stats_block_paddr == 0) { 3585 BCE_PRINTF("%s(%d): Could not map statistics block " 3586 "DMA memory!\n", __FILE__, __LINE__); 3587 rc = ENOMEM; 3588 goto bce_dma_alloc_exit; 3589 } 3590 3591 DBPRINT(sc, BCE_INFO_LOAD, "%s(): stats_block_paddr = 0x%jX\n", 3592 __FUNCTION__, (uintmax_t) sc->stats_block_paddr); 3593 3594 /* BCM5709 uses host memory as cache for context memory. */ 3595 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 3596 sc->ctx_pages = 0x2000 / BCM_PAGE_SIZE; 3597 if (sc->ctx_pages == 0) 3598 sc->ctx_pages = 1; 3599 3600 DBRUNIF((sc->ctx_pages > 512), 3601 BCE_PRINTF("%s(%d): Too many CTX pages! %d > 512\n", 3602 __FILE__, __LINE__, sc->ctx_pages)); 3603 3604 /* 3605 * Create a DMA tag for the context pages, 3606 * allocate and clear the memory, map the 3607 * memory into DMA space, and fetch the 3608 * physical address of the block. 3609 */ 3610 if(bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 3611 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, 3612 NULL, NULL, BCM_PAGE_SIZE, 1, BCM_PAGE_SIZE, 3613 0, NULL, NULL, &sc->ctx_tag)) { 3614 BCE_PRINTF("%s(%d): Could not allocate CTX " 3615 "DMA tag!\n", __FILE__, __LINE__); 3616 rc = ENOMEM; 3617 goto bce_dma_alloc_exit; 3618 } 3619 3620 for (i = 0; i < sc->ctx_pages; i++) { 3621 3622 if(bus_dmamem_alloc(sc->ctx_tag, 3623 (void **)&sc->ctx_block[i], 3624 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3625 &sc->ctx_map[i])) { 3626 BCE_PRINTF("%s(%d): Could not allocate CTX " 3627 "DMA memory!\n", __FILE__, __LINE__); 3628 rc = ENOMEM; 3629 goto bce_dma_alloc_exit; 3630 } 3631 3632 error = bus_dmamap_load(sc->ctx_tag, sc->ctx_map[i], 3633 sc->ctx_block[i], BCM_PAGE_SIZE, bce_dma_map_addr, 3634 &sc->ctx_paddr[i], BUS_DMA_NOWAIT); 3635 3636 if (error || sc->ctx_paddr[i] == 0) { 3637 BCE_PRINTF("%s(%d): Could not map CTX " 3638 "DMA memory!\n", __FILE__, __LINE__); 3639 rc = ENOMEM; 3640 goto bce_dma_alloc_exit; 3641 } 3642 3643 DBPRINT(sc, BCE_INFO_LOAD, "%s(): ctx_paddr[%d] " 3644 "= 0x%jX\n", __FUNCTION__, i, 3645 (uintmax_t) sc->ctx_paddr[i]); 3646 } 3647 } 3648 3649 /* 3650 * Create a DMA tag for the TX buffer descriptor chain, 3651 * allocate and clear the memory, and fetch the 3652 * physical address of the block. 3653 */ 3654 if(bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, BCE_DMA_BOUNDARY, 3655 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, 3656 BCE_TX_CHAIN_PAGE_SZ, 1, BCE_TX_CHAIN_PAGE_SZ, 0, 3657 NULL, NULL, &sc->tx_bd_chain_tag)) { 3658 BCE_PRINTF("%s(%d): Could not allocate TX descriptor " 3659 "chain DMA tag!\n", __FILE__, __LINE__); 3660 rc = ENOMEM; 3661 goto bce_dma_alloc_exit; 3662 } 3663 3664 for (i = 0; i < sc->tx_pages; i++) { 3665 3666 if(bus_dmamem_alloc(sc->tx_bd_chain_tag, 3667 (void **)&sc->tx_bd_chain[i], 3668 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3669 &sc->tx_bd_chain_map[i])) { 3670 BCE_PRINTF("%s(%d): Could not allocate TX descriptor " 3671 "chain DMA memory!\n", __FILE__, __LINE__); 3672 rc = ENOMEM; 3673 goto bce_dma_alloc_exit; 3674 } 3675 3676 error = bus_dmamap_load(sc->tx_bd_chain_tag, 3677 sc->tx_bd_chain_map[i], sc->tx_bd_chain[i], 3678 BCE_TX_CHAIN_PAGE_SZ, bce_dma_map_addr, 3679 &sc->tx_bd_chain_paddr[i], BUS_DMA_NOWAIT); 3680 3681 if (error || sc->tx_bd_chain_paddr[i] == 0) { 3682 BCE_PRINTF("%s(%d): Could not map TX descriptor " 3683 "chain DMA memory!\n", __FILE__, __LINE__); 3684 rc = ENOMEM; 3685 goto bce_dma_alloc_exit; 3686 } 3687 3688 DBPRINT(sc, BCE_INFO_LOAD, "%s(): tx_bd_chain_paddr[%d] = " 3689 "0x%jX\n", __FUNCTION__, i, 3690 (uintmax_t) sc->tx_bd_chain_paddr[i]); 3691 } 3692 3693 /* Check the required size before mapping to conserve resources. */ 3694 if (bce_tso_enable) { 3695 max_size = BCE_TSO_MAX_SIZE; 3696 max_segments = BCE_MAX_SEGMENTS; 3697 max_seg_size = BCE_TSO_MAX_SEG_SIZE; 3698 } else { 3699 max_size = MCLBYTES * BCE_MAX_SEGMENTS; 3700 max_segments = BCE_MAX_SEGMENTS; 3701 max_seg_size = MCLBYTES; 3702 } 3703 3704 /* Create a DMA tag for TX mbufs. */ 3705 if (bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY, 3706 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, max_size, 3707 max_segments, max_seg_size, 0, NULL, NULL, &sc->tx_mbuf_tag)) { 3708 BCE_PRINTF("%s(%d): Could not allocate TX mbuf DMA tag!\n", 3709 __FILE__, __LINE__); 3710 rc = ENOMEM; 3711 goto bce_dma_alloc_exit; 3712 } 3713 3714 /* Create DMA maps for the TX mbufs clusters. */ 3715 for (i = 0; i < TOTAL_TX_BD_ALLOC; i++) { 3716 if (bus_dmamap_create(sc->tx_mbuf_tag, BUS_DMA_NOWAIT, 3717 &sc->tx_mbuf_map[i])) { 3718 BCE_PRINTF("%s(%d): Unable to create TX mbuf DMA " 3719 "map!\n", __FILE__, __LINE__); 3720 rc = ENOMEM; 3721 goto bce_dma_alloc_exit; 3722 } 3723 } 3724 3725 /* 3726 * Create a DMA tag for the RX buffer descriptor chain, 3727 * allocate and clear the memory, and fetch the physical 3728 * address of the blocks. 3729 */ 3730 if (bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 3731 BCE_DMA_BOUNDARY, BUS_SPACE_MAXADDR, 3732 sc->max_bus_addr, NULL, NULL, 3733 BCE_RX_CHAIN_PAGE_SZ, 1, BCE_RX_CHAIN_PAGE_SZ, 3734 0, NULL, NULL, &sc->rx_bd_chain_tag)) { 3735 BCE_PRINTF("%s(%d): Could not allocate RX descriptor chain " 3736 "DMA tag!\n", __FILE__, __LINE__); 3737 rc = ENOMEM; 3738 goto bce_dma_alloc_exit; 3739 } 3740 3741 for (i = 0; i < sc->rx_pages; i++) { 3742 3743 if (bus_dmamem_alloc(sc->rx_bd_chain_tag, 3744 (void **)&sc->rx_bd_chain[i], 3745 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3746 &sc->rx_bd_chain_map[i])) { 3747 BCE_PRINTF("%s(%d): Could not allocate RX descriptor " 3748 "chain DMA memory!\n", __FILE__, __LINE__); 3749 rc = ENOMEM; 3750 goto bce_dma_alloc_exit; 3751 } 3752 3753 error = bus_dmamap_load(sc->rx_bd_chain_tag, 3754 sc->rx_bd_chain_map[i], sc->rx_bd_chain[i], 3755 BCE_RX_CHAIN_PAGE_SZ, bce_dma_map_addr, 3756 &sc->rx_bd_chain_paddr[i], BUS_DMA_NOWAIT); 3757 3758 if (error || sc->rx_bd_chain_paddr[i] == 0) { 3759 BCE_PRINTF("%s(%d): Could not map RX descriptor " 3760 "chain DMA memory!\n", __FILE__, __LINE__); 3761 rc = ENOMEM; 3762 goto bce_dma_alloc_exit; 3763 } 3764 3765 DBPRINT(sc, BCE_INFO_LOAD, "%s(): rx_bd_chain_paddr[%d] = " 3766 "0x%jX\n", __FUNCTION__, i, 3767 (uintmax_t) sc->rx_bd_chain_paddr[i]); 3768 } 3769 3770 /* 3771 * Create a DMA tag for RX mbufs. 3772 */ 3773 if (bce_hdr_split == TRUE) 3774 max_size = ((sc->rx_bd_mbuf_alloc_size < MCLBYTES) ? 3775 MCLBYTES : sc->rx_bd_mbuf_alloc_size); 3776 else 3777 max_size = MJUM9BYTES; 3778 3779 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Creating rx_mbuf_tag " 3780 "(max size = 0x%jX)\n", __FUNCTION__, (uintmax_t)max_size); 3781 3782 if (bus_dma_tag_create(sc->parent_tag, BCE_RX_BUF_ALIGN, 3783 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, 3784 max_size, 1, max_size, 0, NULL, NULL, &sc->rx_mbuf_tag)) { 3785 BCE_PRINTF("%s(%d): Could not allocate RX mbuf DMA tag!\n", 3786 __FILE__, __LINE__); 3787 rc = ENOMEM; 3788 goto bce_dma_alloc_exit; 3789 } 3790 3791 /* Create DMA maps for the RX mbuf clusters. */ 3792 for (i = 0; i < TOTAL_RX_BD_ALLOC; i++) { 3793 if (bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_NOWAIT, 3794 &sc->rx_mbuf_map[i])) { 3795 BCE_PRINTF("%s(%d): Unable to create RX mbuf " 3796 "DMA map!\n", __FILE__, __LINE__); 3797 rc = ENOMEM; 3798 goto bce_dma_alloc_exit; 3799 } 3800 } 3801 3802 if (bce_hdr_split == TRUE) { 3803 /* 3804 * Create a DMA tag for the page buffer descriptor chain, 3805 * allocate and clear the memory, and fetch the physical 3806 * address of the blocks. 3807 */ 3808 if (bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 3809 BCE_DMA_BOUNDARY, BUS_SPACE_MAXADDR, sc->max_bus_addr, 3810 NULL, NULL, BCE_PG_CHAIN_PAGE_SZ, 1, BCE_PG_CHAIN_PAGE_SZ, 3811 0, NULL, NULL, &sc->pg_bd_chain_tag)) { 3812 BCE_PRINTF("%s(%d): Could not allocate page descriptor " 3813 "chain DMA tag!\n", __FILE__, __LINE__); 3814 rc = ENOMEM; 3815 goto bce_dma_alloc_exit; 3816 } 3817 3818 for (i = 0; i < sc->pg_pages; i++) { 3819 if (bus_dmamem_alloc(sc->pg_bd_chain_tag, 3820 (void **)&sc->pg_bd_chain[i], 3821 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3822 &sc->pg_bd_chain_map[i])) { 3823 BCE_PRINTF("%s(%d): Could not allocate page " 3824 "descriptor chain DMA memory!\n", 3825 __FILE__, __LINE__); 3826 rc = ENOMEM; 3827 goto bce_dma_alloc_exit; 3828 } 3829 3830 error = bus_dmamap_load(sc->pg_bd_chain_tag, 3831 sc->pg_bd_chain_map[i], sc->pg_bd_chain[i], 3832 BCE_PG_CHAIN_PAGE_SZ, bce_dma_map_addr, 3833 &sc->pg_bd_chain_paddr[i], BUS_DMA_NOWAIT); 3834 3835 if (error || sc->pg_bd_chain_paddr[i] == 0) { 3836 BCE_PRINTF("%s(%d): Could not map page descriptor " 3837 "chain DMA memory!\n", __FILE__, __LINE__); 3838 rc = ENOMEM; 3839 goto bce_dma_alloc_exit; 3840 } 3841 3842 DBPRINT(sc, BCE_INFO_LOAD, "%s(): pg_bd_chain_paddr[%d] = " 3843 "0x%jX\n", __FUNCTION__, i, 3844 (uintmax_t) sc->pg_bd_chain_paddr[i]); 3845 } 3846 3847 /* 3848 * Create a DMA tag for page mbufs. 3849 */ 3850 if (bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY, 3851 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 3852 1, MCLBYTES, 0, NULL, NULL, &sc->pg_mbuf_tag)) { 3853 BCE_PRINTF("%s(%d): Could not allocate page mbuf " 3854 "DMA tag!\n", __FILE__, __LINE__); 3855 rc = ENOMEM; 3856 goto bce_dma_alloc_exit; 3857 } 3858 3859 /* Create DMA maps for the page mbuf clusters. */ 3860 for (i = 0; i < TOTAL_PG_BD_ALLOC; i++) { 3861 if (bus_dmamap_create(sc->pg_mbuf_tag, BUS_DMA_NOWAIT, 3862 &sc->pg_mbuf_map[i])) { 3863 BCE_PRINTF("%s(%d): Unable to create page mbuf " 3864 "DMA map!\n", __FILE__, __LINE__); 3865 rc = ENOMEM; 3866 goto bce_dma_alloc_exit; 3867 } 3868 } 3869 } 3870 3871bce_dma_alloc_exit: 3872 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 3873 return(rc); 3874} 3875 3876 3877/****************************************************************************/ 3878/* Release all resources used by the driver. */ 3879/* */ 3880/* Releases all resources acquired by the driver including interrupts, */ 3881/* interrupt handler, interfaces, mutexes, and DMA memory. */ 3882/* */ 3883/* Returns: */ 3884/* Nothing. */ 3885/****************************************************************************/ 3886static void 3887bce_release_resources(struct bce_softc *sc) 3888{ 3889 device_t dev; 3890 3891 DBENTER(BCE_VERBOSE_RESET); 3892 3893 dev = sc->bce_dev; 3894 3895 bce_dma_free(sc); 3896 3897 if (sc->bce_intrhand != NULL) { 3898 DBPRINT(sc, BCE_INFO_RESET, "Removing interrupt handler.\n"); 3899 bus_teardown_intr(dev, sc->bce_res_irq, sc->bce_intrhand); 3900 } 3901 3902 if (sc->bce_res_irq != NULL) { 3903 DBPRINT(sc, BCE_INFO_RESET, "Releasing IRQ.\n"); 3904 bus_release_resource(dev, SYS_RES_IRQ, 3905 rman_get_rid(sc->bce_res_irq), sc->bce_res_irq); 3906 } 3907 3908 if (sc->bce_flags & (BCE_USING_MSI_FLAG | BCE_USING_MSIX_FLAG)) { 3909 DBPRINT(sc, BCE_INFO_RESET, "Releasing MSI/MSI-X vector.\n"); 3910 pci_release_msi(dev); 3911 } 3912 3913 if (sc->bce_res_mem != NULL) { 3914 DBPRINT(sc, BCE_INFO_RESET, "Releasing PCI memory.\n"); 3915 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0), 3916 sc->bce_res_mem); 3917 } 3918 3919 if (sc->bce_ifp != NULL) { 3920 DBPRINT(sc, BCE_INFO_RESET, "Releasing IF.\n"); 3921 if_free(sc->bce_ifp); 3922 } 3923 3924 if (mtx_initialized(&sc->bce_mtx)) 3925 BCE_LOCK_DESTROY(sc); 3926 3927 DBEXIT(BCE_VERBOSE_RESET); 3928} 3929 3930 3931/****************************************************************************/ 3932/* Firmware synchronization. */ 3933/* */ 3934/* Before performing certain events such as a chip reset, synchronize with */ 3935/* the firmware first. */ 3936/* */ 3937/* Returns: */ 3938/* 0 for success, positive value for failure. */ 3939/****************************************************************************/ 3940static int 3941bce_fw_sync(struct bce_softc *sc, u32 msg_data) 3942{ 3943 int i, rc = 0; 3944 u32 val; 3945 3946 DBENTER(BCE_VERBOSE_RESET); 3947 3948 /* Don't waste any time if we've timed out before. */ 3949 if (sc->bce_fw_timed_out == TRUE) { 3950 rc = EBUSY; 3951 goto bce_fw_sync_exit; 3952 } 3953 3954 /* Increment the message sequence number. */ 3955 sc->bce_fw_wr_seq++; 3956 msg_data |= sc->bce_fw_wr_seq; 3957 3958 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "bce_fw_sync(): msg_data = " 3959 "0x%08X\n", msg_data); 3960 3961 /* Send the message to the bootcode driver mailbox. */ 3962 bce_shmem_wr(sc, BCE_DRV_MB, msg_data); 3963 3964 /* Wait for the bootcode to acknowledge the message. */ 3965 for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) { 3966 /* Check for a response in the bootcode firmware mailbox. */ 3967 val = bce_shmem_rd(sc, BCE_FW_MB); 3968 if ((val & BCE_FW_MSG_ACK) == (msg_data & BCE_DRV_MSG_SEQ)) 3969 break; 3970 DELAY(1000); 3971 } 3972 3973 /* If we've timed out, tell bootcode that we've stopped waiting. */ 3974 if (((val & BCE_FW_MSG_ACK) != (msg_data & BCE_DRV_MSG_SEQ)) && 3975 ((msg_data & BCE_DRV_MSG_DATA) != BCE_DRV_MSG_DATA_WAIT0)) { 3976 3977 BCE_PRINTF("%s(%d): Firmware synchronization timeout! " 3978 "msg_data = 0x%08X\n", __FILE__, __LINE__, msg_data); 3979 3980 msg_data &= ~BCE_DRV_MSG_CODE; 3981 msg_data |= BCE_DRV_MSG_CODE_FW_TIMEOUT; 3982 3983 bce_shmem_wr(sc, BCE_DRV_MB, msg_data); 3984 3985 sc->bce_fw_timed_out = TRUE; 3986 rc = EBUSY; 3987 } 3988 3989bce_fw_sync_exit: 3990 DBEXIT(BCE_VERBOSE_RESET); 3991 return (rc); 3992} 3993 3994 3995/****************************************************************************/ 3996/* Load Receive Virtual 2 Physical (RV2P) processor firmware. */ 3997/* */ 3998/* Returns: */ 3999/* Nothing. */ 4000/****************************************************************************/ 4001static void 4002bce_load_rv2p_fw(struct bce_softc *sc, const u32 *rv2p_code, 4003 u32 rv2p_code_len, u32 rv2p_proc) 4004{ 4005 int i; 4006 u32 val; 4007 4008 DBENTER(BCE_VERBOSE_RESET); 4009 4010 /* Set the page size used by RV2P. */ 4011 if (rv2p_proc == RV2P_PROC2) { 4012 BCE_RV2P_PROC2_CHG_MAX_BD_PAGE(USABLE_RX_BD_PER_PAGE); 4013 } 4014 4015 for (i = 0; i < rv2p_code_len; i += 8) { 4016 REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code); 4017 rv2p_code++; 4018 REG_WR(sc, BCE_RV2P_INSTR_LOW, *rv2p_code); 4019 rv2p_code++; 4020 4021 if (rv2p_proc == RV2P_PROC1) { 4022 val = (i / 8) | BCE_RV2P_PROC1_ADDR_CMD_RDWR; 4023 REG_WR(sc, BCE_RV2P_PROC1_ADDR_CMD, val); 4024 } 4025 else { 4026 val = (i / 8) | BCE_RV2P_PROC2_ADDR_CMD_RDWR; 4027 REG_WR(sc, BCE_RV2P_PROC2_ADDR_CMD, val); 4028 } 4029 } 4030 4031 /* Reset the processor, un-stall is done later. */ 4032 if (rv2p_proc == RV2P_PROC1) { 4033 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET); 4034 } 4035 else { 4036 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET); 4037 } 4038 4039 DBEXIT(BCE_VERBOSE_RESET); 4040} 4041 4042 4043/****************************************************************************/ 4044/* Load RISC processor firmware. */ 4045/* */ 4046/* Loads firmware from the file if_bcefw.h into the scratchpad memory */ 4047/* associated with a particular processor. */ 4048/* */ 4049/* Returns: */ 4050/* Nothing. */ 4051/****************************************************************************/ 4052static void 4053bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg, 4054 struct fw_info *fw) 4055{ 4056 u32 offset; 4057 4058 DBENTER(BCE_VERBOSE_RESET); 4059 4060 bce_halt_cpu(sc, cpu_reg); 4061 4062 /* Load the Text area. */ 4063 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base); 4064 if (fw->text) { 4065 int j; 4066 4067 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) { 4068 REG_WR_IND(sc, offset, fw->text[j]); 4069 } 4070 } 4071 4072 /* Load the Data area. */ 4073 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base); 4074 if (fw->data) { 4075 int j; 4076 4077 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) { 4078 REG_WR_IND(sc, offset, fw->data[j]); 4079 } 4080 } 4081 4082 /* Load the SBSS area. */ 4083 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base); 4084 if (fw->sbss) { 4085 int j; 4086 4087 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) { 4088 REG_WR_IND(sc, offset, fw->sbss[j]); 4089 } 4090 } 4091 4092 /* Load the BSS area. */ 4093 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base); 4094 if (fw->bss) { 4095 int j; 4096 4097 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) { 4098 REG_WR_IND(sc, offset, fw->bss[j]); 4099 } 4100 } 4101 4102 /* Load the Read-Only area. */ 4103 offset = cpu_reg->spad_base + 4104 (fw->rodata_addr - cpu_reg->mips_view_base); 4105 if (fw->rodata) { 4106 int j; 4107 4108 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) { 4109 REG_WR_IND(sc, offset, fw->rodata[j]); 4110 } 4111 } 4112 4113 /* Clear the pre-fetch instruction and set the FW start address. */ 4114 REG_WR_IND(sc, cpu_reg->inst, 0); 4115 REG_WR_IND(sc, cpu_reg->pc, fw->start_addr); 4116 4117 DBEXIT(BCE_VERBOSE_RESET); 4118} 4119 4120 4121/****************************************************************************/ 4122/* Starts the RISC processor. */ 4123/* */ 4124/* Assumes the CPU starting address has already been set. */ 4125/* */ 4126/* Returns: */ 4127/* Nothing. */ 4128/****************************************************************************/ 4129static void 4130bce_start_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg) 4131{ 4132 u32 val; 4133 4134 DBENTER(BCE_VERBOSE_RESET); 4135 4136 /* Start the CPU. */ 4137 val = REG_RD_IND(sc, cpu_reg->mode); 4138 val &= ~cpu_reg->mode_value_halt; 4139 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 4140 REG_WR_IND(sc, cpu_reg->mode, val); 4141 4142 DBEXIT(BCE_VERBOSE_RESET); 4143} 4144 4145 4146/****************************************************************************/ 4147/* Halts the RISC processor. */ 4148/* */ 4149/* Returns: */ 4150/* Nothing. */ 4151/****************************************************************************/ 4152static void 4153bce_halt_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg) 4154{ 4155 u32 val; 4156 4157 DBENTER(BCE_VERBOSE_RESET); 4158 4159 /* Halt the CPU. */ 4160 val = REG_RD_IND(sc, cpu_reg->mode); 4161 val |= cpu_reg->mode_value_halt; 4162 REG_WR_IND(sc, cpu_reg->mode, val); 4163 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 4164 4165 DBEXIT(BCE_VERBOSE_RESET); 4166} 4167 4168 4169/****************************************************************************/ 4170/* Initialize the RX CPU. */ 4171/* */ 4172/* Returns: */ 4173/* Nothing. */ 4174/****************************************************************************/ 4175static void 4176bce_start_rxp_cpu(struct bce_softc *sc) 4177{ 4178 struct cpu_reg cpu_reg; 4179 4180 DBENTER(BCE_VERBOSE_RESET); 4181 4182 cpu_reg.mode = BCE_RXP_CPU_MODE; 4183 cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT; 4184 cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA; 4185 cpu_reg.state = BCE_RXP_CPU_STATE; 4186 cpu_reg.state_value_clear = 0xffffff; 4187 cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE; 4188 cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK; 4189 cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER; 4190 cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION; 4191 cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT; 4192 cpu_reg.spad_base = BCE_RXP_SCRATCH; 4193 cpu_reg.mips_view_base = 0x8000000; 4194 4195 DBPRINT(sc, BCE_INFO_RESET, "Starting RX firmware.\n"); 4196 bce_start_cpu(sc, &cpu_reg); 4197 4198 DBEXIT(BCE_VERBOSE_RESET); 4199} 4200 4201 4202/****************************************************************************/ 4203/* Initialize the RX CPU. */ 4204/* */ 4205/* Returns: */ 4206/* Nothing. */ 4207/****************************************************************************/ 4208static void 4209bce_init_rxp_cpu(struct bce_softc *sc) 4210{ 4211 struct cpu_reg cpu_reg; 4212 struct fw_info fw; 4213 4214 DBENTER(BCE_VERBOSE_RESET); 4215 4216 cpu_reg.mode = BCE_RXP_CPU_MODE; 4217 cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT; 4218 cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA; 4219 cpu_reg.state = BCE_RXP_CPU_STATE; 4220 cpu_reg.state_value_clear = 0xffffff; 4221 cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE; 4222 cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK; 4223 cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER; 4224 cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION; 4225 cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT; 4226 cpu_reg.spad_base = BCE_RXP_SCRATCH; 4227 cpu_reg.mips_view_base = 0x8000000; 4228 4229 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4230 fw.ver_major = bce_RXP_b09FwReleaseMajor; 4231 fw.ver_minor = bce_RXP_b09FwReleaseMinor; 4232 fw.ver_fix = bce_RXP_b09FwReleaseFix; 4233 fw.start_addr = bce_RXP_b09FwStartAddr; 4234 4235 fw.text_addr = bce_RXP_b09FwTextAddr; 4236 fw.text_len = bce_RXP_b09FwTextLen; 4237 fw.text_index = 0; 4238 fw.text = bce_RXP_b09FwText; 4239 4240 fw.data_addr = bce_RXP_b09FwDataAddr; 4241 fw.data_len = bce_RXP_b09FwDataLen; 4242 fw.data_index = 0; 4243 fw.data = bce_RXP_b09FwData; 4244 4245 fw.sbss_addr = bce_RXP_b09FwSbssAddr; 4246 fw.sbss_len = bce_RXP_b09FwSbssLen; 4247 fw.sbss_index = 0; 4248 fw.sbss = bce_RXP_b09FwSbss; 4249 4250 fw.bss_addr = bce_RXP_b09FwBssAddr; 4251 fw.bss_len = bce_RXP_b09FwBssLen; 4252 fw.bss_index = 0; 4253 fw.bss = bce_RXP_b09FwBss; 4254 4255 fw.rodata_addr = bce_RXP_b09FwRodataAddr; 4256 fw.rodata_len = bce_RXP_b09FwRodataLen; 4257 fw.rodata_index = 0; 4258 fw.rodata = bce_RXP_b09FwRodata; 4259 } else { 4260 fw.ver_major = bce_RXP_b06FwReleaseMajor; 4261 fw.ver_minor = bce_RXP_b06FwReleaseMinor; 4262 fw.ver_fix = bce_RXP_b06FwReleaseFix; 4263 fw.start_addr = bce_RXP_b06FwStartAddr; 4264 4265 fw.text_addr = bce_RXP_b06FwTextAddr; 4266 fw.text_len = bce_RXP_b06FwTextLen; 4267 fw.text_index = 0; 4268 fw.text = bce_RXP_b06FwText; 4269 4270 fw.data_addr = bce_RXP_b06FwDataAddr; 4271 fw.data_len = bce_RXP_b06FwDataLen; 4272 fw.data_index = 0; 4273 fw.data = bce_RXP_b06FwData; 4274 4275 fw.sbss_addr = bce_RXP_b06FwSbssAddr; 4276 fw.sbss_len = bce_RXP_b06FwSbssLen; 4277 fw.sbss_index = 0; 4278 fw.sbss = bce_RXP_b06FwSbss; 4279 4280 fw.bss_addr = bce_RXP_b06FwBssAddr; 4281 fw.bss_len = bce_RXP_b06FwBssLen; 4282 fw.bss_index = 0; 4283 fw.bss = bce_RXP_b06FwBss; 4284 4285 fw.rodata_addr = bce_RXP_b06FwRodataAddr; 4286 fw.rodata_len = bce_RXP_b06FwRodataLen; 4287 fw.rodata_index = 0; 4288 fw.rodata = bce_RXP_b06FwRodata; 4289 } 4290 4291 DBPRINT(sc, BCE_INFO_RESET, "Loading RX firmware.\n"); 4292 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4293 4294 /* Delay RXP start until initialization is complete. */ 4295 4296 DBEXIT(BCE_VERBOSE_RESET); 4297} 4298 4299 4300/****************************************************************************/ 4301/* Initialize the TX CPU. */ 4302/* */ 4303/* Returns: */ 4304/* Nothing. */ 4305/****************************************************************************/ 4306static void 4307bce_init_txp_cpu(struct bce_softc *sc) 4308{ 4309 struct cpu_reg cpu_reg; 4310 struct fw_info fw; 4311 4312 DBENTER(BCE_VERBOSE_RESET); 4313 4314 cpu_reg.mode = BCE_TXP_CPU_MODE; 4315 cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT; 4316 cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA; 4317 cpu_reg.state = BCE_TXP_CPU_STATE; 4318 cpu_reg.state_value_clear = 0xffffff; 4319 cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE; 4320 cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK; 4321 cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER; 4322 cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION; 4323 cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT; 4324 cpu_reg.spad_base = BCE_TXP_SCRATCH; 4325 cpu_reg.mips_view_base = 0x8000000; 4326 4327 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4328 fw.ver_major = bce_TXP_b09FwReleaseMajor; 4329 fw.ver_minor = bce_TXP_b09FwReleaseMinor; 4330 fw.ver_fix = bce_TXP_b09FwReleaseFix; 4331 fw.start_addr = bce_TXP_b09FwStartAddr; 4332 4333 fw.text_addr = bce_TXP_b09FwTextAddr; 4334 fw.text_len = bce_TXP_b09FwTextLen; 4335 fw.text_index = 0; 4336 fw.text = bce_TXP_b09FwText; 4337 4338 fw.data_addr = bce_TXP_b09FwDataAddr; 4339 fw.data_len = bce_TXP_b09FwDataLen; 4340 fw.data_index = 0; 4341 fw.data = bce_TXP_b09FwData; 4342 4343 fw.sbss_addr = bce_TXP_b09FwSbssAddr; 4344 fw.sbss_len = bce_TXP_b09FwSbssLen; 4345 fw.sbss_index = 0; 4346 fw.sbss = bce_TXP_b09FwSbss; 4347 4348 fw.bss_addr = bce_TXP_b09FwBssAddr; 4349 fw.bss_len = bce_TXP_b09FwBssLen; 4350 fw.bss_index = 0; 4351 fw.bss = bce_TXP_b09FwBss; 4352 4353 fw.rodata_addr = bce_TXP_b09FwRodataAddr; 4354 fw.rodata_len = bce_TXP_b09FwRodataLen; 4355 fw.rodata_index = 0; 4356 fw.rodata = bce_TXP_b09FwRodata; 4357 } else { 4358 fw.ver_major = bce_TXP_b06FwReleaseMajor; 4359 fw.ver_minor = bce_TXP_b06FwReleaseMinor; 4360 fw.ver_fix = bce_TXP_b06FwReleaseFix; 4361 fw.start_addr = bce_TXP_b06FwStartAddr; 4362 4363 fw.text_addr = bce_TXP_b06FwTextAddr; 4364 fw.text_len = bce_TXP_b06FwTextLen; 4365 fw.text_index = 0; 4366 fw.text = bce_TXP_b06FwText; 4367 4368 fw.data_addr = bce_TXP_b06FwDataAddr; 4369 fw.data_len = bce_TXP_b06FwDataLen; 4370 fw.data_index = 0; 4371 fw.data = bce_TXP_b06FwData; 4372 4373 fw.sbss_addr = bce_TXP_b06FwSbssAddr; 4374 fw.sbss_len = bce_TXP_b06FwSbssLen; 4375 fw.sbss_index = 0; 4376 fw.sbss = bce_TXP_b06FwSbss; 4377 4378 fw.bss_addr = bce_TXP_b06FwBssAddr; 4379 fw.bss_len = bce_TXP_b06FwBssLen; 4380 fw.bss_index = 0; 4381 fw.bss = bce_TXP_b06FwBss; 4382 4383 fw.rodata_addr = bce_TXP_b06FwRodataAddr; 4384 fw.rodata_len = bce_TXP_b06FwRodataLen; 4385 fw.rodata_index = 0; 4386 fw.rodata = bce_TXP_b06FwRodata; 4387 } 4388 4389 DBPRINT(sc, BCE_INFO_RESET, "Loading TX firmware.\n"); 4390 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4391 bce_start_cpu(sc, &cpu_reg); 4392 4393 DBEXIT(BCE_VERBOSE_RESET); 4394} 4395 4396 4397/****************************************************************************/ 4398/* Initialize the TPAT CPU. */ 4399/* */ 4400/* Returns: */ 4401/* Nothing. */ 4402/****************************************************************************/ 4403static void 4404bce_init_tpat_cpu(struct bce_softc *sc) 4405{ 4406 struct cpu_reg cpu_reg; 4407 struct fw_info fw; 4408 4409 DBENTER(BCE_VERBOSE_RESET); 4410 4411 cpu_reg.mode = BCE_TPAT_CPU_MODE; 4412 cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT; 4413 cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA; 4414 cpu_reg.state = BCE_TPAT_CPU_STATE; 4415 cpu_reg.state_value_clear = 0xffffff; 4416 cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE; 4417 cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK; 4418 cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER; 4419 cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION; 4420 cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT; 4421 cpu_reg.spad_base = BCE_TPAT_SCRATCH; 4422 cpu_reg.mips_view_base = 0x8000000; 4423 4424 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4425 fw.ver_major = bce_TPAT_b09FwReleaseMajor; 4426 fw.ver_minor = bce_TPAT_b09FwReleaseMinor; 4427 fw.ver_fix = bce_TPAT_b09FwReleaseFix; 4428 fw.start_addr = bce_TPAT_b09FwStartAddr; 4429 4430 fw.text_addr = bce_TPAT_b09FwTextAddr; 4431 fw.text_len = bce_TPAT_b09FwTextLen; 4432 fw.text_index = 0; 4433 fw.text = bce_TPAT_b09FwText; 4434 4435 fw.data_addr = bce_TPAT_b09FwDataAddr; 4436 fw.data_len = bce_TPAT_b09FwDataLen; 4437 fw.data_index = 0; 4438 fw.data = bce_TPAT_b09FwData; 4439 4440 fw.sbss_addr = bce_TPAT_b09FwSbssAddr; 4441 fw.sbss_len = bce_TPAT_b09FwSbssLen; 4442 fw.sbss_index = 0; 4443 fw.sbss = bce_TPAT_b09FwSbss; 4444 4445 fw.bss_addr = bce_TPAT_b09FwBssAddr; 4446 fw.bss_len = bce_TPAT_b09FwBssLen; 4447 fw.bss_index = 0; 4448 fw.bss = bce_TPAT_b09FwBss; 4449 4450 fw.rodata_addr = bce_TPAT_b09FwRodataAddr; 4451 fw.rodata_len = bce_TPAT_b09FwRodataLen; 4452 fw.rodata_index = 0; 4453 fw.rodata = bce_TPAT_b09FwRodata; 4454 } else { 4455 fw.ver_major = bce_TPAT_b06FwReleaseMajor; 4456 fw.ver_minor = bce_TPAT_b06FwReleaseMinor; 4457 fw.ver_fix = bce_TPAT_b06FwReleaseFix; 4458 fw.start_addr = bce_TPAT_b06FwStartAddr; 4459 4460 fw.text_addr = bce_TPAT_b06FwTextAddr; 4461 fw.text_len = bce_TPAT_b06FwTextLen; 4462 fw.text_index = 0; 4463 fw.text = bce_TPAT_b06FwText; 4464 4465 fw.data_addr = bce_TPAT_b06FwDataAddr; 4466 fw.data_len = bce_TPAT_b06FwDataLen; 4467 fw.data_index = 0; 4468 fw.data = bce_TPAT_b06FwData; 4469 4470 fw.sbss_addr = bce_TPAT_b06FwSbssAddr; 4471 fw.sbss_len = bce_TPAT_b06FwSbssLen; 4472 fw.sbss_index = 0; 4473 fw.sbss = bce_TPAT_b06FwSbss; 4474 4475 fw.bss_addr = bce_TPAT_b06FwBssAddr; 4476 fw.bss_len = bce_TPAT_b06FwBssLen; 4477 fw.bss_index = 0; 4478 fw.bss = bce_TPAT_b06FwBss; 4479 4480 fw.rodata_addr = bce_TPAT_b06FwRodataAddr; 4481 fw.rodata_len = bce_TPAT_b06FwRodataLen; 4482 fw.rodata_index = 0; 4483 fw.rodata = bce_TPAT_b06FwRodata; 4484 } 4485 4486 DBPRINT(sc, BCE_INFO_RESET, "Loading TPAT firmware.\n"); 4487 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4488 bce_start_cpu(sc, &cpu_reg); 4489 4490 DBEXIT(BCE_VERBOSE_RESET); 4491} 4492 4493 4494/****************************************************************************/ 4495/* Initialize the CP CPU. */ 4496/* */ 4497/* Returns: */ 4498/* Nothing. */ 4499/****************************************************************************/ 4500static void 4501bce_init_cp_cpu(struct bce_softc *sc) 4502{ 4503 struct cpu_reg cpu_reg; 4504 struct fw_info fw; 4505 4506 DBENTER(BCE_VERBOSE_RESET); 4507 4508 cpu_reg.mode = BCE_CP_CPU_MODE; 4509 cpu_reg.mode_value_halt = BCE_CP_CPU_MODE_SOFT_HALT; 4510 cpu_reg.mode_value_sstep = BCE_CP_CPU_MODE_STEP_ENA; 4511 cpu_reg.state = BCE_CP_CPU_STATE; 4512 cpu_reg.state_value_clear = 0xffffff; 4513 cpu_reg.gpr0 = BCE_CP_CPU_REG_FILE; 4514 cpu_reg.evmask = BCE_CP_CPU_EVENT_MASK; 4515 cpu_reg.pc = BCE_CP_CPU_PROGRAM_COUNTER; 4516 cpu_reg.inst = BCE_CP_CPU_INSTRUCTION; 4517 cpu_reg.bp = BCE_CP_CPU_HW_BREAKPOINT; 4518 cpu_reg.spad_base = BCE_CP_SCRATCH; 4519 cpu_reg.mips_view_base = 0x8000000; 4520 4521 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4522 fw.ver_major = bce_CP_b09FwReleaseMajor; 4523 fw.ver_minor = bce_CP_b09FwReleaseMinor; 4524 fw.ver_fix = bce_CP_b09FwReleaseFix; 4525 fw.start_addr = bce_CP_b09FwStartAddr; 4526 4527 fw.text_addr = bce_CP_b09FwTextAddr; 4528 fw.text_len = bce_CP_b09FwTextLen; 4529 fw.text_index = 0; 4530 fw.text = bce_CP_b09FwText; 4531 4532 fw.data_addr = bce_CP_b09FwDataAddr; 4533 fw.data_len = bce_CP_b09FwDataLen; 4534 fw.data_index = 0; 4535 fw.data = bce_CP_b09FwData; 4536 4537 fw.sbss_addr = bce_CP_b09FwSbssAddr; 4538 fw.sbss_len = bce_CP_b09FwSbssLen; 4539 fw.sbss_index = 0; 4540 fw.sbss = bce_CP_b09FwSbss; 4541 4542 fw.bss_addr = bce_CP_b09FwBssAddr; 4543 fw.bss_len = bce_CP_b09FwBssLen; 4544 fw.bss_index = 0; 4545 fw.bss = bce_CP_b09FwBss; 4546 4547 fw.rodata_addr = bce_CP_b09FwRodataAddr; 4548 fw.rodata_len = bce_CP_b09FwRodataLen; 4549 fw.rodata_index = 0; 4550 fw.rodata = bce_CP_b09FwRodata; 4551 } else { 4552 fw.ver_major = bce_CP_b06FwReleaseMajor; 4553 fw.ver_minor = bce_CP_b06FwReleaseMinor; 4554 fw.ver_fix = bce_CP_b06FwReleaseFix; 4555 fw.start_addr = bce_CP_b06FwStartAddr; 4556 4557 fw.text_addr = bce_CP_b06FwTextAddr; 4558 fw.text_len = bce_CP_b06FwTextLen; 4559 fw.text_index = 0; 4560 fw.text = bce_CP_b06FwText; 4561 4562 fw.data_addr = bce_CP_b06FwDataAddr; 4563 fw.data_len = bce_CP_b06FwDataLen; 4564 fw.data_index = 0; 4565 fw.data = bce_CP_b06FwData; 4566 4567 fw.sbss_addr = bce_CP_b06FwSbssAddr; 4568 fw.sbss_len = bce_CP_b06FwSbssLen; 4569 fw.sbss_index = 0; 4570 fw.sbss = bce_CP_b06FwSbss; 4571 4572 fw.bss_addr = bce_CP_b06FwBssAddr; 4573 fw.bss_len = bce_CP_b06FwBssLen; 4574 fw.bss_index = 0; 4575 fw.bss = bce_CP_b06FwBss; 4576 4577 fw.rodata_addr = bce_CP_b06FwRodataAddr; 4578 fw.rodata_len = bce_CP_b06FwRodataLen; 4579 fw.rodata_index = 0; 4580 fw.rodata = bce_CP_b06FwRodata; 4581 } 4582 4583 DBPRINT(sc, BCE_INFO_RESET, "Loading CP firmware.\n"); 4584 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4585 bce_start_cpu(sc, &cpu_reg); 4586 4587 DBEXIT(BCE_VERBOSE_RESET); 4588} 4589 4590 4591/****************************************************************************/ 4592/* Initialize the COM CPU. */ 4593/* */ 4594/* Returns: */ 4595/* Nothing. */ 4596/****************************************************************************/ 4597static void 4598bce_init_com_cpu(struct bce_softc *sc) 4599{ 4600 struct cpu_reg cpu_reg; 4601 struct fw_info fw; 4602 4603 DBENTER(BCE_VERBOSE_RESET); 4604 4605 cpu_reg.mode = BCE_COM_CPU_MODE; 4606 cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT; 4607 cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA; 4608 cpu_reg.state = BCE_COM_CPU_STATE; 4609 cpu_reg.state_value_clear = 0xffffff; 4610 cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE; 4611 cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK; 4612 cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER; 4613 cpu_reg.inst = BCE_COM_CPU_INSTRUCTION; 4614 cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT; 4615 cpu_reg.spad_base = BCE_COM_SCRATCH; 4616 cpu_reg.mips_view_base = 0x8000000; 4617 4618 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4619 fw.ver_major = bce_COM_b09FwReleaseMajor; 4620 fw.ver_minor = bce_COM_b09FwReleaseMinor; 4621 fw.ver_fix = bce_COM_b09FwReleaseFix; 4622 fw.start_addr = bce_COM_b09FwStartAddr; 4623 4624 fw.text_addr = bce_COM_b09FwTextAddr; 4625 fw.text_len = bce_COM_b09FwTextLen; 4626 fw.text_index = 0; 4627 fw.text = bce_COM_b09FwText; 4628 4629 fw.data_addr = bce_COM_b09FwDataAddr; 4630 fw.data_len = bce_COM_b09FwDataLen; 4631 fw.data_index = 0; 4632 fw.data = bce_COM_b09FwData; 4633 4634 fw.sbss_addr = bce_COM_b09FwSbssAddr; 4635 fw.sbss_len = bce_COM_b09FwSbssLen; 4636 fw.sbss_index = 0; 4637 fw.sbss = bce_COM_b09FwSbss; 4638 4639 fw.bss_addr = bce_COM_b09FwBssAddr; 4640 fw.bss_len = bce_COM_b09FwBssLen; 4641 fw.bss_index = 0; 4642 fw.bss = bce_COM_b09FwBss; 4643 4644 fw.rodata_addr = bce_COM_b09FwRodataAddr; 4645 fw.rodata_len = bce_COM_b09FwRodataLen; 4646 fw.rodata_index = 0; 4647 fw.rodata = bce_COM_b09FwRodata; 4648 } else { 4649 fw.ver_major = bce_COM_b06FwReleaseMajor; 4650 fw.ver_minor = bce_COM_b06FwReleaseMinor; 4651 fw.ver_fix = bce_COM_b06FwReleaseFix; 4652 fw.start_addr = bce_COM_b06FwStartAddr; 4653 4654 fw.text_addr = bce_COM_b06FwTextAddr; 4655 fw.text_len = bce_COM_b06FwTextLen; 4656 fw.text_index = 0; 4657 fw.text = bce_COM_b06FwText; 4658 4659 fw.data_addr = bce_COM_b06FwDataAddr; 4660 fw.data_len = bce_COM_b06FwDataLen; 4661 fw.data_index = 0; 4662 fw.data = bce_COM_b06FwData; 4663 4664 fw.sbss_addr = bce_COM_b06FwSbssAddr; 4665 fw.sbss_len = bce_COM_b06FwSbssLen; 4666 fw.sbss_index = 0; 4667 fw.sbss = bce_COM_b06FwSbss; 4668 4669 fw.bss_addr = bce_COM_b06FwBssAddr; 4670 fw.bss_len = bce_COM_b06FwBssLen; 4671 fw.bss_index = 0; 4672 fw.bss = bce_COM_b06FwBss; 4673 4674 fw.rodata_addr = bce_COM_b06FwRodataAddr; 4675 fw.rodata_len = bce_COM_b06FwRodataLen; 4676 fw.rodata_index = 0; 4677 fw.rodata = bce_COM_b06FwRodata; 4678 } 4679 4680 DBPRINT(sc, BCE_INFO_RESET, "Loading COM firmware.\n"); 4681 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4682 bce_start_cpu(sc, &cpu_reg); 4683 4684 DBEXIT(BCE_VERBOSE_RESET); 4685} 4686 4687 4688/****************************************************************************/ 4689/* Initialize the RV2P, RX, TX, TPAT, COM, and CP CPUs. */ 4690/* */ 4691/* Loads the firmware for each CPU and starts the CPU. */ 4692/* */ 4693/* Returns: */ 4694/* Nothing. */ 4695/****************************************************************************/ 4696static void 4697bce_init_cpus(struct bce_softc *sc) 4698{ 4699 DBENTER(BCE_VERBOSE_RESET); 4700 4701 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4702 4703 if ((BCE_CHIP_REV(sc) == BCE_CHIP_REV_Ax)) { 4704 bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc1, 4705 sizeof(bce_xi90_rv2p_proc1), RV2P_PROC1); 4706 bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc2, 4707 sizeof(bce_xi90_rv2p_proc2), RV2P_PROC2); 4708 } else { 4709 bce_load_rv2p_fw(sc, bce_xi_rv2p_proc1, 4710 sizeof(bce_xi_rv2p_proc1), RV2P_PROC1); 4711 bce_load_rv2p_fw(sc, bce_xi_rv2p_proc2, 4712 sizeof(bce_xi_rv2p_proc2), RV2P_PROC2); 4713 } 4714 4715 } else { 4716 bce_load_rv2p_fw(sc, bce_rv2p_proc1, 4717 sizeof(bce_rv2p_proc1), RV2P_PROC1); 4718 bce_load_rv2p_fw(sc, bce_rv2p_proc2, 4719 sizeof(bce_rv2p_proc2), RV2P_PROC2); 4720 } 4721 4722 bce_init_rxp_cpu(sc); 4723 bce_init_txp_cpu(sc); 4724 bce_init_tpat_cpu(sc); 4725 bce_init_com_cpu(sc); 4726 bce_init_cp_cpu(sc); 4727 4728 DBEXIT(BCE_VERBOSE_RESET); 4729} 4730 4731 4732/****************************************************************************/ 4733/* Initialize context memory. */ 4734/* */ 4735/* Clears the memory associated with each Context ID (CID). */ 4736/* */ 4737/* Returns: */ 4738/* Nothing. */ 4739/****************************************************************************/ 4740static int 4741bce_init_ctx(struct bce_softc *sc) 4742{ 4743 u32 offset, val, vcid_addr; 4744 int i, j, rc, retry_cnt; 4745 4746 rc = 0; 4747 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 4748 4749 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4750 retry_cnt = CTX_INIT_RETRY_COUNT; 4751 4752 DBPRINT(sc, BCE_INFO_CTX, "Initializing 5709 context.\n"); 4753 4754 /* 4755 * BCM5709 context memory may be cached 4756 * in host memory so prepare the host memory 4757 * for access. 4758 */ 4759 val = BCE_CTX_COMMAND_ENABLED | 4760 BCE_CTX_COMMAND_MEM_INIT | (1 << 12); 4761 val |= (BCM_PAGE_BITS - 8) << 16; 4762 REG_WR(sc, BCE_CTX_COMMAND, val); 4763 4764 /* Wait for mem init command to complete. */ 4765 for (i = 0; i < retry_cnt; i++) { 4766 val = REG_RD(sc, BCE_CTX_COMMAND); 4767 if (!(val & BCE_CTX_COMMAND_MEM_INIT)) 4768 break; 4769 DELAY(2); 4770 } 4771 if ((val & BCE_CTX_COMMAND_MEM_INIT) != 0) { 4772 BCE_PRINTF("%s(): Context memory initialization failed!\n", 4773 __FUNCTION__); 4774 rc = EBUSY; 4775 goto init_ctx_fail; 4776 } 4777 4778 for (i = 0; i < sc->ctx_pages; i++) { 4779 /* Set the physical address of the context memory. */ 4780 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA0, 4781 BCE_ADDR_LO(sc->ctx_paddr[i] & 0xfffffff0) | 4782 BCE_CTX_HOST_PAGE_TBL_DATA0_VALID); 4783 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA1, 4784 BCE_ADDR_HI(sc->ctx_paddr[i])); 4785 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_CTRL, i | 4786 BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ); 4787 4788 /* Verify the context memory write was successful. */ 4789 for (j = 0; j < retry_cnt; j++) { 4790 val = REG_RD(sc, BCE_CTX_HOST_PAGE_TBL_CTRL); 4791 if ((val & 4792 BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0) 4793 break; 4794 DELAY(5); 4795 } 4796 if ((val & BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) != 0) { 4797 BCE_PRINTF("%s(): Failed to initialize " 4798 "context page %d!\n", __FUNCTION__, i); 4799 rc = EBUSY; 4800 goto init_ctx_fail; 4801 } 4802 } 4803 } else { 4804 4805 DBPRINT(sc, BCE_INFO, "Initializing 5706/5708 context.\n"); 4806 4807 /* 4808 * For the 5706/5708, context memory is local to 4809 * the controller, so initialize the controller 4810 * context memory. 4811 */ 4812 4813 vcid_addr = GET_CID_ADDR(96); 4814 while (vcid_addr) { 4815 4816 vcid_addr -= PHY_CTX_SIZE; 4817 4818 REG_WR(sc, BCE_CTX_VIRT_ADDR, 0); 4819 REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr); 4820 4821 for(offset = 0; offset < PHY_CTX_SIZE; offset += 4) { 4822 CTX_WR(sc, 0x00, offset, 0); 4823 } 4824 4825 REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr); 4826 REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr); 4827 } 4828 4829 } 4830init_ctx_fail: 4831 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 4832 return (rc); 4833} 4834 4835 4836/****************************************************************************/ 4837/* Fetch the permanent MAC address of the controller. */ 4838/* */ 4839/* Returns: */ 4840/* Nothing. */ 4841/****************************************************************************/ 4842static void 4843bce_get_mac_addr(struct bce_softc *sc) 4844{ 4845 u32 mac_lo = 0, mac_hi = 0; 4846 4847 DBENTER(BCE_VERBOSE_RESET); 4848 4849 /* 4850 * The NetXtreme II bootcode populates various NIC 4851 * power-on and runtime configuration items in a 4852 * shared memory area. The factory configured MAC 4853 * address is available from both NVRAM and the 4854 * shared memory area so we'll read the value from 4855 * shared memory for speed. 4856 */ 4857 4858 mac_hi = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_UPPER); 4859 mac_lo = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_LOWER); 4860 4861 if ((mac_lo == 0) && (mac_hi == 0)) { 4862 BCE_PRINTF("%s(%d): Invalid Ethernet address!\n", 4863 __FILE__, __LINE__); 4864 } else { 4865 sc->eaddr[0] = (u_char)(mac_hi >> 8); 4866 sc->eaddr[1] = (u_char)(mac_hi >> 0); 4867 sc->eaddr[2] = (u_char)(mac_lo >> 24); 4868 sc->eaddr[3] = (u_char)(mac_lo >> 16); 4869 sc->eaddr[4] = (u_char)(mac_lo >> 8); 4870 sc->eaddr[5] = (u_char)(mac_lo >> 0); 4871 } 4872 4873 DBPRINT(sc, BCE_INFO_MISC, "Permanent Ethernet " 4874 "address = %6D\n", sc->eaddr, ":"); 4875 DBEXIT(BCE_VERBOSE_RESET); 4876} 4877 4878 4879/****************************************************************************/ 4880/* Program the MAC address. */ 4881/* */ 4882/* Returns: */ 4883/* Nothing. */ 4884/****************************************************************************/ 4885static void 4886bce_set_mac_addr(struct bce_softc *sc) 4887{ 4888 u32 val; 4889 u8 *mac_addr = sc->eaddr; 4890 4891 /* ToDo: Add support for setting multiple MAC addresses. */ 4892 4893 DBENTER(BCE_VERBOSE_RESET); 4894 DBPRINT(sc, BCE_INFO_MISC, "Setting Ethernet address = " 4895 "%6D\n", sc->eaddr, ":"); 4896 4897 val = (mac_addr[0] << 8) | mac_addr[1]; 4898 4899 REG_WR(sc, BCE_EMAC_MAC_MATCH0, val); 4900 4901 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 4902 (mac_addr[4] << 8) | mac_addr[5]; 4903 4904 REG_WR(sc, BCE_EMAC_MAC_MATCH1, val); 4905 4906 DBEXIT(BCE_VERBOSE_RESET); 4907} 4908 4909 4910/****************************************************************************/ 4911/* Stop the controller. */ 4912/* */ 4913/* Returns: */ 4914/* Nothing. */ 4915/****************************************************************************/ 4916static void 4917bce_stop(struct bce_softc *sc) 4918{ 4919 struct ifnet *ifp; 4920 4921 DBENTER(BCE_VERBOSE_RESET); 4922 4923 BCE_LOCK_ASSERT(sc); 4924 4925 ifp = sc->bce_ifp; 4926 4927 callout_stop(&sc->bce_tick_callout); 4928 4929 /* Disable the transmit/receive blocks. */ 4930 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, BCE_MISC_ENABLE_CLR_DEFAULT); 4931 REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS); 4932 DELAY(20); 4933 4934 bce_disable_intr(sc); 4935 4936 /* Free RX buffers. */ 4937 if (bce_hdr_split == TRUE) { 4938 bce_free_pg_chain(sc); 4939 } 4940 bce_free_rx_chain(sc); 4941 4942 /* Free TX buffers. */ 4943 bce_free_tx_chain(sc); 4944 4945 sc->watchdog_timer = 0; 4946 4947 sc->bce_link_up = FALSE; 4948 4949 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 4950 4951 DBEXIT(BCE_VERBOSE_RESET); 4952} 4953 4954 4955static int 4956bce_reset(struct bce_softc *sc, u32 reset_code) 4957{ 4958 u32 emac_mode_save, val; 4959 int i, rc = 0; 4960 static const u32 emac_mode_mask = BCE_EMAC_MODE_PORT | 4961 BCE_EMAC_MODE_HALF_DUPLEX | BCE_EMAC_MODE_25G; 4962 4963 DBENTER(BCE_VERBOSE_RESET); 4964 4965 DBPRINT(sc, BCE_VERBOSE_RESET, "%s(): reset_code = 0x%08X\n", 4966 __FUNCTION__, reset_code); 4967 4968 /* 4969 * If ASF/IPMI is operational, then the EMAC Mode register already 4970 * contains appropriate values for the link settings that have 4971 * been auto-negotiated. Resetting the chip will clobber those 4972 * values. Save the important bits so we can restore them after 4973 * the reset. 4974 */ 4975 emac_mode_save = REG_RD(sc, BCE_EMAC_MODE) & emac_mode_mask; 4976 4977 /* Wait for pending PCI transactions to complete. */ 4978 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, 4979 BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE | 4980 BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE | 4981 BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE | 4982 BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE); 4983 val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS); 4984 DELAY(5); 4985 4986 /* Disable DMA */ 4987 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4988 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL); 4989 val &= ~BCE_MISC_NEW_CORE_CTL_DMA_ENABLE; 4990 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val); 4991 } 4992 4993 /* Assume bootcode is running. */ 4994 sc->bce_fw_timed_out = FALSE; 4995 sc->bce_drv_cardiac_arrest = FALSE; 4996 4997 /* Give the firmware a chance to prepare for the reset. */ 4998 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT0 | reset_code); 4999 if (rc) 5000 goto bce_reset_exit; 5001 5002 /* Set a firmware reminder that this is a soft reset. */ 5003 bce_shmem_wr(sc, BCE_DRV_RESET_SIGNATURE, BCE_DRV_RESET_SIGNATURE_MAGIC); 5004 5005 /* Dummy read to force the chip to complete all current transactions. */ 5006 val = REG_RD(sc, BCE_MISC_ID); 5007 5008 /* Chip reset. */ 5009 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5010 REG_WR(sc, BCE_MISC_COMMAND, BCE_MISC_COMMAND_SW_RESET); 5011 REG_RD(sc, BCE_MISC_COMMAND); 5012 DELAY(5); 5013 5014 val = BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 5015 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 5016 5017 pci_write_config(sc->bce_dev, BCE_PCICFG_MISC_CONFIG, val, 4); 5018 } else { 5019 val = BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 5020 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 5021 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 5022 REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val); 5023 5024 /* Allow up to 30us for reset to complete. */ 5025 for (i = 0; i < 10; i++) { 5026 val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG); 5027 if ((val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 5028 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) { 5029 break; 5030 } 5031 DELAY(10); 5032 } 5033 5034 /* Check that reset completed successfully. */ 5035 if (val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 5036 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) { 5037 BCE_PRINTF("%s(%d): Reset failed!\n", 5038 __FILE__, __LINE__); 5039 rc = EBUSY; 5040 goto bce_reset_exit; 5041 } 5042 } 5043 5044 /* Make sure byte swapping is properly configured. */ 5045 val = REG_RD(sc, BCE_PCI_SWAP_DIAG0); 5046 if (val != 0x01020304) { 5047 BCE_PRINTF("%s(%d): Byte swap is incorrect!\n", 5048 __FILE__, __LINE__); 5049 rc = ENODEV; 5050 goto bce_reset_exit; 5051 } 5052 5053 /* Just completed a reset, assume that firmware is running again. */ 5054 sc->bce_fw_timed_out = FALSE; 5055 sc->bce_drv_cardiac_arrest = FALSE; 5056 5057 /* Wait for the firmware to finish its initialization. */ 5058 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT1 | reset_code); 5059 if (rc) 5060 BCE_PRINTF("%s(%d): Firmware did not complete " 5061 "initialization!\n", __FILE__, __LINE__); 5062 /* Get firmware capabilities. */ 5063 bce_fw_cap_init(sc); 5064 5065bce_reset_exit: 5066 /* Restore EMAC Mode bits needed to keep ASF/IPMI running. */ 5067 val = REG_RD(sc, BCE_EMAC_MODE); 5068 val = (val & ~emac_mode_mask) | emac_mode_save; 5069 REG_WR(sc, BCE_EMAC_MODE, val); 5070 5071 DBEXIT(BCE_VERBOSE_RESET); 5072 return (rc); 5073} 5074 5075 5076static int 5077bce_chipinit(struct bce_softc *sc) 5078{ 5079 u32 val; 5080 int rc = 0; 5081 5082 DBENTER(BCE_VERBOSE_RESET); 5083 5084 bce_disable_intr(sc); 5085 5086 /* 5087 * Initialize DMA byte/word swapping, configure the number of DMA 5088 * channels and PCI clock compensation delay. 5089 */ 5090 val = BCE_DMA_CONFIG_DATA_BYTE_SWAP | 5091 BCE_DMA_CONFIG_DATA_WORD_SWAP | 5092#if BYTE_ORDER == BIG_ENDIAN 5093 BCE_DMA_CONFIG_CNTL_BYTE_SWAP | 5094#endif 5095 BCE_DMA_CONFIG_CNTL_WORD_SWAP | 5096 DMA_READ_CHANS << 12 | 5097 DMA_WRITE_CHANS << 16; 5098 5099 val |= (0x2 << 20) | BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY; 5100 5101 if ((sc->bce_flags & BCE_PCIX_FLAG) && (sc->bus_speed_mhz == 133)) 5102 val |= BCE_DMA_CONFIG_PCI_FAST_CLK_CMP; 5103 5104 /* 5105 * This setting resolves a problem observed on certain Intel PCI 5106 * chipsets that cannot handle multiple outstanding DMA operations. 5107 * See errata E9_5706A1_65. 5108 */ 5109 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) && 5110 (BCE_CHIP_ID(sc) != BCE_CHIP_ID_5706_A0) && 5111 !(sc->bce_flags & BCE_PCIX_FLAG)) 5112 val |= BCE_DMA_CONFIG_CNTL_PING_PONG_DMA; 5113 5114 REG_WR(sc, BCE_DMA_CONFIG, val); 5115 5116 /* Enable the RX_V2P and Context state machines before access. */ 5117 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 5118 BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE | 5119 BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE | 5120 BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE); 5121 5122 /* Initialize context mapping and zero out the quick contexts. */ 5123 if ((rc = bce_init_ctx(sc)) != 0) 5124 goto bce_chipinit_exit; 5125 5126 /* Initialize the on-boards CPUs */ 5127 bce_init_cpus(sc); 5128 5129 /* Enable management frames (NC-SI) to flow to the MCP. */ 5130 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 5131 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) | BCE_RPM_MGMT_PKT_CTRL_MGMT_EN; 5132 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val); 5133 } 5134 5135 /* Prepare NVRAM for access. */ 5136 if ((rc = bce_init_nvram(sc)) != 0) 5137 goto bce_chipinit_exit; 5138 5139 /* Set the kernel bypass block size */ 5140 val = REG_RD(sc, BCE_MQ_CONFIG); 5141 val &= ~BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE; 5142 val |= BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256; 5143 5144 /* Enable bins used on the 5709. */ 5145 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5146 val |= BCE_MQ_CONFIG_BIN_MQ_MODE; 5147 if (BCE_CHIP_ID(sc) == BCE_CHIP_ID_5709_A1) 5148 val |= BCE_MQ_CONFIG_HALT_DIS; 5149 } 5150 5151 REG_WR(sc, BCE_MQ_CONFIG, val); 5152 5153 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE); 5154 REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val); 5155 REG_WR(sc, BCE_MQ_KNL_WIND_END, val); 5156 5157 /* Set the page size and clear the RV2P processor stall bits. */ 5158 val = (BCM_PAGE_BITS - 8) << 24; 5159 REG_WR(sc, BCE_RV2P_CONFIG, val); 5160 5161 /* Configure page size. */ 5162 val = REG_RD(sc, BCE_TBDR_CONFIG); 5163 val &= ~BCE_TBDR_CONFIG_PAGE_SIZE; 5164 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40; 5165 REG_WR(sc, BCE_TBDR_CONFIG, val); 5166 5167 /* Set the perfect match control register to default. */ 5168 REG_WR_IND(sc, BCE_RXP_PM_CTRL, 0); 5169 5170bce_chipinit_exit: 5171 DBEXIT(BCE_VERBOSE_RESET); 5172 5173 return(rc); 5174} 5175 5176 5177/****************************************************************************/ 5178/* Initialize the controller in preparation to send/receive traffic. */ 5179/* */ 5180/* Returns: */ 5181/* 0 for success, positive value for failure. */ 5182/****************************************************************************/ 5183static int 5184bce_blockinit(struct bce_softc *sc) 5185{ 5186 u32 reg, val; 5187 int rc = 0; 5188 5189 DBENTER(BCE_VERBOSE_RESET); 5190 5191 /* Load the hardware default MAC address. */ 5192 bce_set_mac_addr(sc); 5193 5194 /* Set the Ethernet backoff seed value */ 5195 val = sc->eaddr[0] + (sc->eaddr[1] << 8) + 5196 (sc->eaddr[2] << 16) + (sc->eaddr[3] ) + 5197 (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16); 5198 REG_WR(sc, BCE_EMAC_BACKOFF_SEED, val); 5199 5200 sc->last_status_idx = 0; 5201 sc->rx_mode = BCE_EMAC_RX_MODE_SORT_MODE; 5202 5203 /* Set up link change interrupt generation. */ 5204 REG_WR(sc, BCE_EMAC_ATTENTION_ENA, BCE_EMAC_ATTENTION_ENA_LINK); 5205 5206 /* Program the physical address of the status block. */ 5207 REG_WR(sc, BCE_HC_STATUS_ADDR_L, 5208 BCE_ADDR_LO(sc->status_block_paddr)); 5209 REG_WR(sc, BCE_HC_STATUS_ADDR_H, 5210 BCE_ADDR_HI(sc->status_block_paddr)); 5211 5212 /* Program the physical address of the statistics block. */ 5213 REG_WR(sc, BCE_HC_STATISTICS_ADDR_L, 5214 BCE_ADDR_LO(sc->stats_block_paddr)); 5215 REG_WR(sc, BCE_HC_STATISTICS_ADDR_H, 5216 BCE_ADDR_HI(sc->stats_block_paddr)); 5217 5218 /* 5219 * Program various host coalescing parameters. 5220 * Trip points control how many BDs should be ready before generating 5221 * an interrupt while ticks control how long a BD can sit in the chain 5222 * before generating an interrupt. 5223 */ 5224 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP, 5225 (sc->bce_tx_quick_cons_trip_int << 16) | 5226 sc->bce_tx_quick_cons_trip); 5227 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP, 5228 (sc->bce_rx_quick_cons_trip_int << 16) | 5229 sc->bce_rx_quick_cons_trip); 5230 REG_WR(sc, BCE_HC_TX_TICKS, 5231 (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks); 5232 REG_WR(sc, BCE_HC_RX_TICKS, 5233 (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks); 5234 REG_WR(sc, BCE_HC_STATS_TICKS, sc->bce_stats_ticks & 0xffff00); 5235 REG_WR(sc, BCE_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */ 5236 /* Not used for L2. */ 5237 REG_WR(sc, BCE_HC_COMP_PROD_TRIP, 0); 5238 REG_WR(sc, BCE_HC_COM_TICKS, 0); 5239 REG_WR(sc, BCE_HC_CMD_TICKS, 0); 5240 5241 /* Configure the Host Coalescing block. */ 5242 val = BCE_HC_CONFIG_RX_TMR_MODE | BCE_HC_CONFIG_TX_TMR_MODE | 5243 BCE_HC_CONFIG_COLLECT_STATS; 5244 5245#if 0 5246 /* ToDo: Add MSI-X support. */ 5247 if (sc->bce_flags & BCE_USING_MSIX_FLAG) { 5248 u32 base = ((BCE_TX_VEC - 1) * BCE_HC_SB_CONFIG_SIZE) + 5249 BCE_HC_SB_CONFIG_1; 5250 5251 REG_WR(sc, BCE_HC_MSIX_BIT_VECTOR, BCE_HC_MSIX_BIT_VECTOR_VAL); 5252 5253 REG_WR(sc, base, BCE_HC_SB_CONFIG_1_TX_TMR_MODE | 5254 BCE_HC_SB_CONFIG_1_ONE_SHOT); 5255 5256 REG_WR(sc, base + BCE_HC_TX_QUICK_CONS_TRIP_OFF, 5257 (sc->tx_quick_cons_trip_int << 16) | 5258 sc->tx_quick_cons_trip); 5259 5260 REG_WR(sc, base + BCE_HC_TX_TICKS_OFF, 5261 (sc->tx_ticks_int << 16) | sc->tx_ticks); 5262 5263 val |= BCE_HC_CONFIG_SB_ADDR_INC_128B; 5264 } 5265 5266 /* 5267 * Tell the HC block to automatically set the 5268 * INT_MASK bit after an MSI/MSI-X interrupt 5269 * is generated so the driver doesn't have to. 5270 */ 5271 if (sc->bce_flags & BCE_ONE_SHOT_MSI_FLAG) 5272 val |= BCE_HC_CONFIG_ONE_SHOT; 5273 5274 /* Set the MSI-X status blocks to 128 byte boundaries. */ 5275 if (sc->bce_flags & BCE_USING_MSIX_FLAG) 5276 val |= BCE_HC_CONFIG_SB_ADDR_INC_128B; 5277#endif 5278 5279 REG_WR(sc, BCE_HC_CONFIG, val); 5280 5281 /* Clear the internal statistics counters. */ 5282 REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW); 5283 5284 /* Verify that bootcode is running. */ 5285 reg = bce_shmem_rd(sc, BCE_DEV_INFO_SIGNATURE); 5286 5287 DBRUNIF(DB_RANDOMTRUE(bootcode_running_failure_sim_control), 5288 BCE_PRINTF("%s(%d): Simulating bootcode failure.\n", 5289 __FILE__, __LINE__); 5290 reg = 0); 5291 5292 if ((reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK) != 5293 BCE_DEV_INFO_SIGNATURE_MAGIC) { 5294 BCE_PRINTF("%s(%d): Bootcode not running! Found: 0x%08X, " 5295 "Expected: 08%08X\n", __FILE__, __LINE__, 5296 (reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK), 5297 BCE_DEV_INFO_SIGNATURE_MAGIC); 5298 rc = ENODEV; 5299 goto bce_blockinit_exit; 5300 } 5301 5302 /* Enable DMA */ 5303 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5304 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL); 5305 val |= BCE_MISC_NEW_CORE_CTL_DMA_ENABLE; 5306 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val); 5307 } 5308 5309 /* Allow bootcode to apply additional fixes before enabling MAC. */ 5310 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT2 | 5311 BCE_DRV_MSG_CODE_RESET); 5312 5313 /* Enable link state change interrupt generation. */ 5314 REG_WR(sc, BCE_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE); 5315 5316 /* Enable the RXP. */ 5317 bce_start_rxp_cpu(sc); 5318 5319 /* Disable management frames (NC-SI) from flowing to the MCP. */ 5320 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 5321 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) & 5322 ~BCE_RPM_MGMT_PKT_CTRL_MGMT_EN; 5323 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val); 5324 } 5325 5326 /* Enable all remaining blocks in the MAC. */ 5327 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) 5328 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 5329 BCE_MISC_ENABLE_DEFAULT_XI); 5330 else 5331 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 5332 BCE_MISC_ENABLE_DEFAULT); 5333 5334 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS); 5335 DELAY(20); 5336 5337 /* Save the current host coalescing block settings. */ 5338 sc->hc_command = REG_RD(sc, BCE_HC_COMMAND); 5339 5340bce_blockinit_exit: 5341 DBEXIT(BCE_VERBOSE_RESET); 5342 5343 return (rc); 5344} 5345 5346 5347/****************************************************************************/ 5348/* Encapsulate an mbuf into the rx_bd chain. */ 5349/* */ 5350/* Returns: */ 5351/* 0 for success, positive value for failure. */ 5352/****************************************************************************/ 5353static int 5354bce_get_rx_buf(struct bce_softc *sc, u16 prod, u16 chain_prod, u32 *prod_bseq) 5355{ 5356 bus_dma_segment_t segs[1]; 5357 struct mbuf *m_new = NULL; 5358 struct rx_bd *rxbd; 5359 int nsegs, error, rc = 0; 5360#ifdef BCE_DEBUG 5361 u16 debug_chain_prod = chain_prod; 5362#endif 5363 5364 DBENTER(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5365 5366 /* Make sure the inputs are valid. */ 5367 DBRUNIF((chain_prod > MAX_RX_BD_ALLOC), 5368 BCE_PRINTF("%s(%d): RX producer out of range: " 5369 "0x%04X > 0x%04X\n", __FILE__, __LINE__, 5370 chain_prod, (u16)MAX_RX_BD_ALLOC)); 5371 5372 DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): prod = 0x%04X, " 5373 "chain_prod = 0x%04X, prod_bseq = 0x%08X\n", __FUNCTION__, 5374 prod, chain_prod, *prod_bseq); 5375 5376 /* Update some debug statistic counters */ 5377 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 5378 sc->rx_low_watermark = sc->free_rx_bd); 5379 DBRUNIF((sc->free_rx_bd == sc->max_rx_bd), 5380 sc->rx_empty_count++); 5381 5382 /* Simulate an mbuf allocation failure. */ 5383 DBRUNIF(DB_RANDOMTRUE(mbuf_alloc_failed_sim_control), 5384 sc->mbuf_alloc_failed_count++; 5385 sc->mbuf_alloc_failed_sim_count++; 5386 rc = ENOBUFS; 5387 goto bce_get_rx_buf_exit); 5388 5389 /* This is a new mbuf allocation. */ 5390 if (bce_hdr_split == TRUE) 5391 MGETHDR(m_new, M_NOWAIT, MT_DATA); 5392 else 5393 m_new = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, 5394 sc->rx_bd_mbuf_alloc_size); 5395 5396 if (m_new == NULL) { 5397 sc->mbuf_alloc_failed_count++; 5398 rc = ENOBUFS; 5399 goto bce_get_rx_buf_exit; 5400 } 5401 5402 DBRUN(sc->debug_rx_mbuf_alloc++); 5403 5404 /* Make sure we have a valid packet header. */ 5405 M_ASSERTPKTHDR(m_new); 5406 5407 /* Initialize the mbuf size and pad if necessary for alignment. */ 5408 m_new->m_pkthdr.len = m_new->m_len = sc->rx_bd_mbuf_alloc_size; 5409 m_adj(m_new, sc->rx_bd_mbuf_align_pad); 5410 5411 /* ToDo: Consider calling m_fragment() to test error handling. */ 5412 5413 /* Map the mbuf cluster into device memory. */ 5414 error = bus_dmamap_load_mbuf_sg(sc->rx_mbuf_tag, 5415 sc->rx_mbuf_map[chain_prod], m_new, segs, &nsegs, BUS_DMA_NOWAIT); 5416 5417 /* Handle any mapping errors. */ 5418 if (error) { 5419 BCE_PRINTF("%s(%d): Error mapping mbuf into RX " 5420 "chain (%d)!\n", __FILE__, __LINE__, error); 5421 5422 sc->dma_map_addr_rx_failed_count++; 5423 m_freem(m_new); 5424 5425 DBRUN(sc->debug_rx_mbuf_alloc--); 5426 5427 rc = ENOBUFS; 5428 goto bce_get_rx_buf_exit; 5429 } 5430 5431 /* All mbufs must map to a single segment. */ 5432 KASSERT(nsegs == 1, ("%s(): Too many segments returned (%d)!", 5433 __FUNCTION__, nsegs)); 5434 5435 /* Setup the rx_bd for the segment. */ 5436 rxbd = &sc->rx_bd_chain[RX_PAGE(chain_prod)][RX_IDX(chain_prod)]; 5437 5438 rxbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[0].ds_addr)); 5439 rxbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[0].ds_addr)); 5440 rxbd->rx_bd_len = htole32(segs[0].ds_len); 5441 rxbd->rx_bd_flags = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END); 5442 *prod_bseq += segs[0].ds_len; 5443 5444 /* Save the mbuf and update our counter. */ 5445 sc->rx_mbuf_ptr[chain_prod] = m_new; 5446 sc->free_rx_bd -= nsegs; 5447 5448 DBRUNMSG(BCE_INSANE_RECV, 5449 bce_dump_rx_mbuf_chain(sc, debug_chain_prod, nsegs)); 5450 5451 DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): prod = 0x%04X, " 5452 "chain_prod = 0x%04X, prod_bseq = 0x%08X\n", __FUNCTION__, prod, 5453 chain_prod, *prod_bseq); 5454 5455bce_get_rx_buf_exit: 5456 DBEXIT(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5457 5458 return(rc); 5459} 5460 5461 5462/****************************************************************************/ 5463/* Encapsulate an mbuf cluster into the page chain. */ 5464/* */ 5465/* Returns: */ 5466/* 0 for success, positive value for failure. */ 5467/****************************************************************************/ 5468static int 5469bce_get_pg_buf(struct bce_softc *sc, u16 prod, u16 prod_idx) 5470{ 5471 bus_dma_segment_t segs[1]; 5472 struct mbuf *m_new = NULL; 5473 struct rx_bd *pgbd; 5474 int error, nsegs, rc = 0; 5475#ifdef BCE_DEBUG 5476 u16 debug_prod_idx = prod_idx; 5477#endif 5478 5479 DBENTER(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5480 5481 /* Make sure the inputs are valid. */ 5482 DBRUNIF((prod_idx > MAX_PG_BD_ALLOC), 5483 BCE_PRINTF("%s(%d): page producer out of range: " 5484 "0x%04X > 0x%04X\n", __FILE__, __LINE__, 5485 prod_idx, (u16)MAX_PG_BD_ALLOC)); 5486 5487 DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): prod = 0x%04X, " 5488 "chain_prod = 0x%04X\n", __FUNCTION__, prod, prod_idx); 5489 5490 /* Update counters if we've hit a new low or run out of pages. */ 5491 DBRUNIF((sc->free_pg_bd < sc->pg_low_watermark), 5492 sc->pg_low_watermark = sc->free_pg_bd); 5493 DBRUNIF((sc->free_pg_bd == sc->max_pg_bd), sc->pg_empty_count++); 5494 5495 /* Simulate an mbuf allocation failure. */ 5496 DBRUNIF(DB_RANDOMTRUE(mbuf_alloc_failed_sim_control), 5497 sc->mbuf_alloc_failed_count++; 5498 sc->mbuf_alloc_failed_sim_count++; 5499 rc = ENOBUFS; 5500 goto bce_get_pg_buf_exit); 5501 5502 /* This is a new mbuf allocation. */ 5503 m_new = m_getcl(M_NOWAIT, MT_DATA, 0); 5504 if (m_new == NULL) { 5505 sc->mbuf_alloc_failed_count++; 5506 rc = ENOBUFS; 5507 goto bce_get_pg_buf_exit; 5508 } 5509 5510 DBRUN(sc->debug_pg_mbuf_alloc++); 5511 5512 m_new->m_len = MCLBYTES; 5513 5514 /* ToDo: Consider calling m_fragment() to test error handling. */ 5515 5516 /* Map the mbuf cluster into device memory. */ 5517 error = bus_dmamap_load_mbuf_sg(sc->pg_mbuf_tag, 5518 sc->pg_mbuf_map[prod_idx], m_new, segs, &nsegs, BUS_DMA_NOWAIT); 5519 5520 /* Handle any mapping errors. */ 5521 if (error) { 5522 BCE_PRINTF("%s(%d): Error mapping mbuf into page chain!\n", 5523 __FILE__, __LINE__); 5524 5525 m_freem(m_new); 5526 DBRUN(sc->debug_pg_mbuf_alloc--); 5527 5528 rc = ENOBUFS; 5529 goto bce_get_pg_buf_exit; 5530 } 5531 5532 /* All mbufs must map to a single segment. */ 5533 KASSERT(nsegs == 1, ("%s(): Too many segments returned (%d)!", 5534 __FUNCTION__, nsegs)); 5535 5536 /* ToDo: Do we need bus_dmamap_sync(,,BUS_DMASYNC_PREREAD) here? */ 5537 5538 /* 5539 * The page chain uses the same rx_bd data structure 5540 * as the receive chain but doesn't require a byte sequence (bseq). 5541 */ 5542 pgbd = &sc->pg_bd_chain[PG_PAGE(prod_idx)][PG_IDX(prod_idx)]; 5543 5544 pgbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[0].ds_addr)); 5545 pgbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[0].ds_addr)); 5546 pgbd->rx_bd_len = htole32(MCLBYTES); 5547 pgbd->rx_bd_flags = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END); 5548 5549 /* Save the mbuf and update our counter. */ 5550 sc->pg_mbuf_ptr[prod_idx] = m_new; 5551 sc->free_pg_bd--; 5552 5553 DBRUNMSG(BCE_INSANE_RECV, 5554 bce_dump_pg_mbuf_chain(sc, debug_prod_idx, 1)); 5555 5556 DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): prod = 0x%04X, " 5557 "prod_idx = 0x%04X\n", __FUNCTION__, prod, prod_idx); 5558 5559bce_get_pg_buf_exit: 5560 DBEXIT(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5561 5562 return(rc); 5563} 5564 5565 5566/****************************************************************************/ 5567/* Initialize the TX context memory. */ 5568/* */ 5569/* Returns: */ 5570/* Nothing */ 5571/****************************************************************************/ 5572static void 5573bce_init_tx_context(struct bce_softc *sc) 5574{ 5575 u32 val; 5576 5577 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 5578 5579 /* Initialize the context ID for an L2 TX chain. */ 5580 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5581 /* Set the CID type to support an L2 connection. */ 5582 val = BCE_L2CTX_TX_TYPE_TYPE_L2_XI | 5583 BCE_L2CTX_TX_TYPE_SIZE_L2_XI; 5584 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE_XI, val); 5585 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2_XI | (8 << 16); 5586 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5587 BCE_L2CTX_TX_CMD_TYPE_XI, val); 5588 5589 /* Point the hardware to the first page in the chain. */ 5590 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]); 5591 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5592 BCE_L2CTX_TX_TBDR_BHADDR_HI_XI, val); 5593 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]); 5594 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5595 BCE_L2CTX_TX_TBDR_BHADDR_LO_XI, val); 5596 } else { 5597 /* Set the CID type to support an L2 connection. */ 5598 val = BCE_L2CTX_TX_TYPE_TYPE_L2 | BCE_L2CTX_TX_TYPE_SIZE_L2; 5599 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE, val); 5600 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2 | (8 << 16); 5601 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_CMD_TYPE, val); 5602 5603 /* Point the hardware to the first page in the chain. */ 5604 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]); 5605 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5606 BCE_L2CTX_TX_TBDR_BHADDR_HI, val); 5607 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]); 5608 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5609 BCE_L2CTX_TX_TBDR_BHADDR_LO, val); 5610 } 5611 5612 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 5613} 5614 5615 5616/****************************************************************************/ 5617/* Allocate memory and initialize the TX data structures. */ 5618/* */ 5619/* Returns: */ 5620/* 0 for success, positive value for failure. */ 5621/****************************************************************************/ 5622static int 5623bce_init_tx_chain(struct bce_softc *sc) 5624{ 5625 struct tx_bd *txbd; 5626 int i, rc = 0; 5627 5628 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_LOAD); 5629 5630 /* Set the initial TX producer/consumer indices. */ 5631 sc->tx_prod = 0; 5632 sc->tx_cons = 0; 5633 sc->tx_prod_bseq = 0; 5634 sc->used_tx_bd = 0; 5635 sc->max_tx_bd = USABLE_TX_BD_ALLOC; 5636 DBRUN(sc->tx_hi_watermark = 0); 5637 DBRUN(sc->tx_full_count = 0); 5638 5639 /* 5640 * The NetXtreme II supports a linked-list structre called 5641 * a Buffer Descriptor Chain (or BD chain). A BD chain 5642 * consists of a series of 1 or more chain pages, each of which 5643 * consists of a fixed number of BD entries. 5644 * The last BD entry on each page is a pointer to the next page 5645 * in the chain, and the last pointer in the BD chain 5646 * points back to the beginning of the chain. 5647 */ 5648 5649 /* Set the TX next pointer chain entries. */ 5650 for (i = 0; i < sc->tx_pages; i++) { 5651 int j; 5652 5653 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE]; 5654 5655 /* Check if we've reached the last page. */ 5656 if (i == (sc->tx_pages - 1)) 5657 j = 0; 5658 else 5659 j = i + 1; 5660 5661 txbd->tx_bd_haddr_hi = 5662 htole32(BCE_ADDR_HI(sc->tx_bd_chain_paddr[j])); 5663 txbd->tx_bd_haddr_lo = 5664 htole32(BCE_ADDR_LO(sc->tx_bd_chain_paddr[j])); 5665 } 5666 5667 bce_init_tx_context(sc); 5668 5669 DBRUNMSG(BCE_INSANE_SEND, bce_dump_tx_chain(sc, 0, TOTAL_TX_BD_ALLOC)); 5670 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_LOAD); 5671 5672 return(rc); 5673} 5674 5675 5676/****************************************************************************/ 5677/* Free memory and clear the TX data structures. */ 5678/* */ 5679/* Returns: */ 5680/* Nothing. */ 5681/****************************************************************************/ 5682static void 5683bce_free_tx_chain(struct bce_softc *sc) 5684{ 5685 int i; 5686 5687 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_UNLOAD); 5688 5689 /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */ 5690 for (i = 0; i < MAX_TX_BD_AVAIL; i++) { 5691 if (sc->tx_mbuf_ptr[i] != NULL) { 5692 if (sc->tx_mbuf_map[i] != NULL) 5693 bus_dmamap_sync(sc->tx_mbuf_tag, 5694 sc->tx_mbuf_map[i], 5695 BUS_DMASYNC_POSTWRITE); 5696 m_freem(sc->tx_mbuf_ptr[i]); 5697 sc->tx_mbuf_ptr[i] = NULL; 5698 DBRUN(sc->debug_tx_mbuf_alloc--); 5699 } 5700 } 5701 5702 /* Clear each TX chain page. */ 5703 for (i = 0; i < sc->tx_pages; i++) 5704 bzero((char *)sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ); 5705 5706 sc->used_tx_bd = 0; 5707 5708 /* Check if we lost any mbufs in the process. */ 5709 DBRUNIF((sc->debug_tx_mbuf_alloc), 5710 BCE_PRINTF("%s(%d): Memory leak! Lost %d mbufs " 5711 "from tx chain!\n", __FILE__, __LINE__, 5712 sc->debug_tx_mbuf_alloc)); 5713 5714 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_UNLOAD); 5715} 5716 5717 5718/****************************************************************************/ 5719/* Initialize the RX context memory. */ 5720/* */ 5721/* Returns: */ 5722/* Nothing */ 5723/****************************************************************************/ 5724static void 5725bce_init_rx_context(struct bce_softc *sc) 5726{ 5727 u32 val; 5728 5729 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_CTX); 5730 5731 /* Init the type, size, and BD cache levels for the RX context. */ 5732 val = BCE_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE | 5733 BCE_L2CTX_RX_CTX_TYPE_SIZE_L2 | 5734 (0x02 << BCE_L2CTX_RX_BD_PRE_READ_SHIFT); 5735 5736 /* 5737 * Set the level for generating pause frames 5738 * when the number of available rx_bd's gets 5739 * too low (the low watermark) and the level 5740 * when pause frames can be stopped (the high 5741 * watermark). 5742 */ 5743 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5744 u32 lo_water, hi_water; 5745 5746 if (sc->bce_flags & BCE_USING_TX_FLOW_CONTROL) { 5747 lo_water = BCE_L2CTX_RX_LO_WATER_MARK_DEFAULT; 5748 } else { 5749 lo_water = 0; 5750 } 5751 5752 if (lo_water >= USABLE_RX_BD_ALLOC) { 5753 lo_water = 0; 5754 } 5755 5756 hi_water = USABLE_RX_BD_ALLOC / 4; 5757 5758 if (hi_water <= lo_water) { 5759 lo_water = 0; 5760 } 5761 5762 lo_water /= BCE_L2CTX_RX_LO_WATER_MARK_SCALE; 5763 hi_water /= BCE_L2CTX_RX_HI_WATER_MARK_SCALE; 5764 5765 if (hi_water > 0xf) 5766 hi_water = 0xf; 5767 else if (hi_water == 0) 5768 lo_water = 0; 5769 5770 val |= (lo_water << BCE_L2CTX_RX_LO_WATER_MARK_SHIFT) | 5771 (hi_water << BCE_L2CTX_RX_HI_WATER_MARK_SHIFT); 5772 } 5773 5774 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_CTX_TYPE, val); 5775 5776 /* Setup the MQ BIN mapping for l2_ctx_host_bseq. */ 5777 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5778 val = REG_RD(sc, BCE_MQ_MAP_L2_5); 5779 REG_WR(sc, BCE_MQ_MAP_L2_5, val | BCE_MQ_MAP_L2_5_ARM); 5780 } 5781 5782 /* Point the hardware to the first page in the chain. */ 5783 val = BCE_ADDR_HI(sc->rx_bd_chain_paddr[0]); 5784 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_HI, val); 5785 val = BCE_ADDR_LO(sc->rx_bd_chain_paddr[0]); 5786 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_LO, val); 5787 5788 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_CTX); 5789} 5790 5791 5792/****************************************************************************/ 5793/* Allocate memory and initialize the RX data structures. */ 5794/* */ 5795/* Returns: */ 5796/* 0 for success, positive value for failure. */ 5797/****************************************************************************/ 5798static int 5799bce_init_rx_chain(struct bce_softc *sc) 5800{ 5801 struct rx_bd *rxbd; 5802 int i, rc = 0; 5803 5804 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 5805 BCE_VERBOSE_CTX); 5806 5807 /* Initialize the RX producer and consumer indices. */ 5808 sc->rx_prod = 0; 5809 sc->rx_cons = 0; 5810 sc->rx_prod_bseq = 0; 5811 sc->free_rx_bd = USABLE_RX_BD_ALLOC; 5812 sc->max_rx_bd = USABLE_RX_BD_ALLOC; 5813 5814 /* Initialize the RX next pointer chain entries. */ 5815 for (i = 0; i < sc->rx_pages; i++) { 5816 int j; 5817 5818 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE]; 5819 5820 /* Check if we've reached the last page. */ 5821 if (i == (sc->rx_pages - 1)) 5822 j = 0; 5823 else 5824 j = i + 1; 5825 5826 /* Setup the chain page pointers. */ 5827 rxbd->rx_bd_haddr_hi = 5828 htole32(BCE_ADDR_HI(sc->rx_bd_chain_paddr[j])); 5829 rxbd->rx_bd_haddr_lo = 5830 htole32(BCE_ADDR_LO(sc->rx_bd_chain_paddr[j])); 5831 } 5832 5833 /* Fill up the RX chain. */ 5834 bce_fill_rx_chain(sc); 5835 5836 DBRUN(sc->rx_low_watermark = USABLE_RX_BD_ALLOC); 5837 DBRUN(sc->rx_empty_count = 0); 5838 for (i = 0; i < sc->rx_pages; i++) { 5839 bus_dmamap_sync(sc->rx_bd_chain_tag, sc->rx_bd_chain_map[i], 5840 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 5841 } 5842 5843 bce_init_rx_context(sc); 5844 5845 DBRUNMSG(BCE_EXTREME_RECV, 5846 bce_dump_rx_bd_chain(sc, 0, TOTAL_RX_BD_ALLOC)); 5847 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 5848 BCE_VERBOSE_CTX); 5849 5850 /* ToDo: Are there possible failure modes here? */ 5851 5852 return(rc); 5853} 5854 5855 5856/****************************************************************************/ 5857/* Add mbufs to the RX chain until its full or an mbuf allocation error */ 5858/* occurs. */ 5859/* */ 5860/* Returns: */ 5861/* Nothing */ 5862/****************************************************************************/ 5863static void 5864bce_fill_rx_chain(struct bce_softc *sc) 5865{ 5866 u16 prod, prod_idx; 5867 u32 prod_bseq; 5868 5869 DBENTER(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 5870 BCE_VERBOSE_CTX); 5871 5872 /* Get the RX chain producer indices. */ 5873 prod = sc->rx_prod; 5874 prod_bseq = sc->rx_prod_bseq; 5875 5876 /* Keep filling the RX chain until it's full. */ 5877 while (sc->free_rx_bd > 0) { 5878 prod_idx = RX_CHAIN_IDX(prod); 5879 if (bce_get_rx_buf(sc, prod, prod_idx, &prod_bseq)) { 5880 /* Bail out if we can't add an mbuf to the chain. */ 5881 break; 5882 } 5883 prod = NEXT_RX_BD(prod); 5884 } 5885 5886 /* Save the RX chain producer indices. */ 5887 sc->rx_prod = prod; 5888 sc->rx_prod_bseq = prod_bseq; 5889 5890 /* We should never end up pointing to a next page pointer. */ 5891 DBRUNIF(((prod & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE), 5892 BCE_PRINTF("%s(): Invalid rx_prod value: 0x%04X\n", 5893 __FUNCTION__, rx_prod)); 5894 5895 /* Write the mailbox and tell the chip about the waiting rx_bd's. */ 5896 REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BDIDX, prod); 5897 REG_WR(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BSEQ, prod_bseq); 5898 5899 DBEXIT(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 5900 BCE_VERBOSE_CTX); 5901} 5902 5903 5904/****************************************************************************/ 5905/* Free memory and clear the RX data structures. */ 5906/* */ 5907/* Returns: */ 5908/* Nothing. */ 5909/****************************************************************************/ 5910static void 5911bce_free_rx_chain(struct bce_softc *sc) 5912{ 5913 int i; 5914 5915 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 5916 5917 /* Free any mbufs still in the RX mbuf chain. */ 5918 for (i = 0; i < MAX_RX_BD_AVAIL; i++) { 5919 if (sc->rx_mbuf_ptr[i] != NULL) { 5920 if (sc->rx_mbuf_map[i] != NULL) 5921 bus_dmamap_sync(sc->rx_mbuf_tag, 5922 sc->rx_mbuf_map[i], 5923 BUS_DMASYNC_POSTREAD); 5924 m_freem(sc->rx_mbuf_ptr[i]); 5925 sc->rx_mbuf_ptr[i] = NULL; 5926 DBRUN(sc->debug_rx_mbuf_alloc--); 5927 } 5928 } 5929 5930 /* Clear each RX chain page. */ 5931 for (i = 0; i < sc->rx_pages; i++) 5932 if (sc->rx_bd_chain[i] != NULL) 5933 bzero((char *)sc->rx_bd_chain[i], 5934 BCE_RX_CHAIN_PAGE_SZ); 5935 5936 sc->free_rx_bd = sc->max_rx_bd; 5937 5938 /* Check if we lost any mbufs in the process. */ 5939 DBRUNIF((sc->debug_rx_mbuf_alloc), 5940 BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from rx chain!\n", 5941 __FUNCTION__, sc->debug_rx_mbuf_alloc)); 5942 5943 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 5944} 5945 5946 5947/****************************************************************************/ 5948/* Allocate memory and initialize the page data structures. */ 5949/* Assumes that bce_init_rx_chain() has not already been called. */ 5950/* */ 5951/* Returns: */ 5952/* 0 for success, positive value for failure. */ 5953/****************************************************************************/ 5954static int 5955bce_init_pg_chain(struct bce_softc *sc) 5956{ 5957 struct rx_bd *pgbd; 5958 int i, rc = 0; 5959 u32 val; 5960 5961 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 5962 BCE_VERBOSE_CTX); 5963 5964 /* Initialize the page producer and consumer indices. */ 5965 sc->pg_prod = 0; 5966 sc->pg_cons = 0; 5967 sc->free_pg_bd = USABLE_PG_BD_ALLOC; 5968 sc->max_pg_bd = USABLE_PG_BD_ALLOC; 5969 DBRUN(sc->pg_low_watermark = sc->max_pg_bd); 5970 DBRUN(sc->pg_empty_count = 0); 5971 5972 /* Initialize the page next pointer chain entries. */ 5973 for (i = 0; i < sc->pg_pages; i++) { 5974 int j; 5975 5976 pgbd = &sc->pg_bd_chain[i][USABLE_PG_BD_PER_PAGE]; 5977 5978 /* Check if we've reached the last page. */ 5979 if (i == (sc->pg_pages - 1)) 5980 j = 0; 5981 else 5982 j = i + 1; 5983 5984 /* Setup the chain page pointers. */ 5985 pgbd->rx_bd_haddr_hi = 5986 htole32(BCE_ADDR_HI(sc->pg_bd_chain_paddr[j])); 5987 pgbd->rx_bd_haddr_lo = 5988 htole32(BCE_ADDR_LO(sc->pg_bd_chain_paddr[j])); 5989 } 5990 5991 /* Setup the MQ BIN mapping for host_pg_bidx. */ 5992 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) 5993 REG_WR(sc, BCE_MQ_MAP_L2_3, BCE_MQ_MAP_L2_3_DEFAULT); 5994 5995 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_PG_BUF_SIZE, 0); 5996 5997 /* Configure the rx_bd and page chain mbuf cluster size. */ 5998 val = (sc->rx_bd_mbuf_data_len << 16) | MCLBYTES; 5999 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_PG_BUF_SIZE, val); 6000 6001 /* Configure the context reserved for jumbo support. */ 6002 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_RBDC_KEY, 6003 BCE_L2CTX_RX_RBDC_JUMBO_KEY); 6004 6005 /* Point the hardware to the first page in the page chain. */ 6006 val = BCE_ADDR_HI(sc->pg_bd_chain_paddr[0]); 6007 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_PG_BDHADDR_HI, val); 6008 val = BCE_ADDR_LO(sc->pg_bd_chain_paddr[0]); 6009 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_PG_BDHADDR_LO, val); 6010 6011 /* Fill up the page chain. */ 6012 bce_fill_pg_chain(sc); 6013 6014 for (i = 0; i < sc->pg_pages; i++) { 6015 bus_dmamap_sync(sc->pg_bd_chain_tag, sc->pg_bd_chain_map[i], 6016 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 6017 } 6018 6019 DBRUNMSG(BCE_EXTREME_RECV, 6020 bce_dump_pg_chain(sc, 0, TOTAL_PG_BD_ALLOC)); 6021 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 6022 BCE_VERBOSE_CTX); 6023 return(rc); 6024} 6025 6026 6027/****************************************************************************/ 6028/* Add mbufs to the page chain until its full or an mbuf allocation error */ 6029/* occurs. */ 6030/* */ 6031/* Returns: */ 6032/* Nothing */ 6033/****************************************************************************/ 6034static void 6035bce_fill_pg_chain(struct bce_softc *sc) 6036{ 6037 u16 prod, prod_idx; 6038 6039 DBENTER(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 6040 BCE_VERBOSE_CTX); 6041 6042 /* Get the page chain prodcuer index. */ 6043 prod = sc->pg_prod; 6044 6045 /* Keep filling the page chain until it's full. */ 6046 while (sc->free_pg_bd > 0) { 6047 prod_idx = PG_CHAIN_IDX(prod); 6048 if (bce_get_pg_buf(sc, prod, prod_idx)) { 6049 /* Bail out if we can't add an mbuf to the chain. */ 6050 break; 6051 } 6052 prod = NEXT_PG_BD(prod); 6053 } 6054 6055 /* Save the page chain producer index. */ 6056 sc->pg_prod = prod; 6057 6058 DBRUNIF(((prod & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE), 6059 BCE_PRINTF("%s(): Invalid pg_prod value: 0x%04X\n", 6060 __FUNCTION__, pg_prod)); 6061 6062 /* 6063 * Write the mailbox and tell the chip about 6064 * the new rx_bd's in the page chain. 6065 */ 6066 REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_PG_BDIDX, 6067 prod); 6068 6069 DBEXIT(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 6070 BCE_VERBOSE_CTX); 6071} 6072 6073 6074/****************************************************************************/ 6075/* Free memory and clear the RX data structures. */ 6076/* */ 6077/* Returns: */ 6078/* Nothing. */ 6079/****************************************************************************/ 6080static void 6081bce_free_pg_chain(struct bce_softc *sc) 6082{ 6083 int i; 6084 6085 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 6086 6087 /* Free any mbufs still in the mbuf page chain. */ 6088 for (i = 0; i < MAX_PG_BD_AVAIL; i++) { 6089 if (sc->pg_mbuf_ptr[i] != NULL) { 6090 if (sc->pg_mbuf_map[i] != NULL) 6091 bus_dmamap_sync(sc->pg_mbuf_tag, 6092 sc->pg_mbuf_map[i], 6093 BUS_DMASYNC_POSTREAD); 6094 m_freem(sc->pg_mbuf_ptr[i]); 6095 sc->pg_mbuf_ptr[i] = NULL; 6096 DBRUN(sc->debug_pg_mbuf_alloc--); 6097 } 6098 } 6099 6100 /* Clear each page chain pages. */ 6101 for (i = 0; i < sc->pg_pages; i++) 6102 bzero((char *)sc->pg_bd_chain[i], BCE_PG_CHAIN_PAGE_SZ); 6103 6104 sc->free_pg_bd = sc->max_pg_bd; 6105 6106 /* Check if we lost any mbufs in the process. */ 6107 DBRUNIF((sc->debug_pg_mbuf_alloc), 6108 BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from page chain!\n", 6109 __FUNCTION__, sc->debug_pg_mbuf_alloc)); 6110 6111 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 6112} 6113 6114 6115static u32 6116bce_get_rphy_link(struct bce_softc *sc) 6117{ 6118 u32 advertise, link; 6119 int fdpx; 6120 6121 advertise = 0; 6122 fdpx = 0; 6123 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) != 0) 6124 link = bce_shmem_rd(sc, BCE_RPHY_SERDES_LINK); 6125 else 6126 link = bce_shmem_rd(sc, BCE_RPHY_COPPER_LINK); 6127 if (link & BCE_NETLINK_ANEG_ENB) 6128 advertise |= BCE_NETLINK_ANEG_ENB; 6129 if (link & BCE_NETLINK_SPEED_10HALF) 6130 advertise |= BCE_NETLINK_SPEED_10HALF; 6131 if (link & BCE_NETLINK_SPEED_10FULL) { 6132 advertise |= BCE_NETLINK_SPEED_10FULL; 6133 fdpx++; 6134 } 6135 if (link & BCE_NETLINK_SPEED_100HALF) 6136 advertise |= BCE_NETLINK_SPEED_100HALF; 6137 if (link & BCE_NETLINK_SPEED_100FULL) { 6138 advertise |= BCE_NETLINK_SPEED_100FULL; 6139 fdpx++; 6140 } 6141 if (link & BCE_NETLINK_SPEED_1000HALF) 6142 advertise |= BCE_NETLINK_SPEED_1000HALF; 6143 if (link & BCE_NETLINK_SPEED_1000FULL) { 6144 advertise |= BCE_NETLINK_SPEED_1000FULL; 6145 fdpx++; 6146 } 6147 if (link & BCE_NETLINK_SPEED_2500HALF) 6148 advertise |= BCE_NETLINK_SPEED_2500HALF; 6149 if (link & BCE_NETLINK_SPEED_2500FULL) { 6150 advertise |= BCE_NETLINK_SPEED_2500FULL; 6151 fdpx++; 6152 } 6153 if (fdpx) 6154 advertise |= BCE_NETLINK_FC_PAUSE_SYM | 6155 BCE_NETLINK_FC_PAUSE_ASYM; 6156 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) 6157 advertise |= BCE_NETLINK_PHY_APP_REMOTE | 6158 BCE_NETLINK_ETH_AT_WIRESPEED; 6159 6160 return (advertise); 6161} 6162 6163 6164/****************************************************************************/ 6165/* Set media options. */ 6166/* */ 6167/* Returns: */ 6168/* 0 for success, positive value for failure. */ 6169/****************************************************************************/ 6170static int 6171bce_ifmedia_upd(struct ifnet *ifp) 6172{ 6173 struct bce_softc *sc = ifp->if_softc; 6174 int error; 6175 6176 DBENTER(BCE_VERBOSE); 6177 6178 BCE_LOCK(sc); 6179 error = bce_ifmedia_upd_locked(ifp); 6180 BCE_UNLOCK(sc); 6181 6182 DBEXIT(BCE_VERBOSE); 6183 return (error); 6184} 6185 6186 6187/****************************************************************************/ 6188/* Set media options. */ 6189/* */ 6190/* Returns: */ 6191/* Nothing. */ 6192/****************************************************************************/ 6193static int 6194bce_ifmedia_upd_locked(struct ifnet *ifp) 6195{ 6196 struct bce_softc *sc = ifp->if_softc; 6197 struct mii_data *mii; 6198 struct mii_softc *miisc; 6199 struct ifmedia *ifm; 6200 u32 link; 6201 int error, fdx; 6202 6203 DBENTER(BCE_VERBOSE_PHY); 6204 6205 error = 0; 6206 BCE_LOCK_ASSERT(sc); 6207 6208 sc->bce_link_up = FALSE; 6209 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) { 6210 ifm = &sc->bce_ifmedia; 6211 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 6212 return (EINVAL); 6213 link = 0; 6214 fdx = IFM_OPTIONS(ifm->ifm_media) & IFM_FDX; 6215 switch(IFM_SUBTYPE(ifm->ifm_media)) { 6216 case IFM_AUTO: 6217 /* 6218 * Check advertised link of remote PHY by reading 6219 * BCE_RPHY_SERDES_LINK or BCE_RPHY_COPPER_LINK. 6220 * Always use the same link type of remote PHY. 6221 */ 6222 link = bce_get_rphy_link(sc); 6223 break; 6224 case IFM_2500_SX: 6225 if ((sc->bce_phy_flags & 6226 (BCE_PHY_REMOTE_PORT_FIBER_FLAG | 6227 BCE_PHY_2_5G_CAPABLE_FLAG)) == 0) 6228 return (EINVAL); 6229 /* 6230 * XXX 6231 * Have to enable forced 2.5Gbps configuration. 6232 */ 6233 if (fdx != 0) 6234 link |= BCE_NETLINK_SPEED_2500FULL; 6235 else 6236 link |= BCE_NETLINK_SPEED_2500HALF; 6237 break; 6238 case IFM_1000_SX: 6239 if ((sc->bce_phy_flags & 6240 BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) 6241 return (EINVAL); 6242 /* 6243 * XXX 6244 * Have to disable 2.5Gbps configuration. 6245 */ 6246 if (fdx != 0) 6247 link = BCE_NETLINK_SPEED_1000FULL; 6248 else 6249 link = BCE_NETLINK_SPEED_1000HALF; 6250 break; 6251 case IFM_1000_T: 6252 if (sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) 6253 return (EINVAL); 6254 if (fdx != 0) 6255 link = BCE_NETLINK_SPEED_1000FULL; 6256 else 6257 link = BCE_NETLINK_SPEED_1000HALF; 6258 break; 6259 case IFM_100_TX: 6260 if (sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) 6261 return (EINVAL); 6262 if (fdx != 0) 6263 link = BCE_NETLINK_SPEED_100FULL; 6264 else 6265 link = BCE_NETLINK_SPEED_100HALF; 6266 break; 6267 case IFM_10_T: 6268 if (sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) 6269 return (EINVAL); 6270 if (fdx != 0) 6271 link = BCE_NETLINK_SPEED_10FULL; 6272 else 6273 link = BCE_NETLINK_SPEED_10HALF; 6274 break; 6275 default: 6276 return (EINVAL); 6277 } 6278 if (IFM_SUBTYPE(ifm->ifm_media) != IFM_AUTO) { 6279 /* 6280 * XXX 6281 * Advertise pause capability for full-duplex media. 6282 */ 6283 if (fdx != 0) 6284 link |= BCE_NETLINK_FC_PAUSE_SYM | 6285 BCE_NETLINK_FC_PAUSE_ASYM; 6286 if ((sc->bce_phy_flags & 6287 BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) 6288 link |= BCE_NETLINK_PHY_APP_REMOTE | 6289 BCE_NETLINK_ETH_AT_WIRESPEED; 6290 } 6291 6292 bce_shmem_wr(sc, BCE_MB_ARGS_0, link); 6293 error = bce_fw_sync(sc, BCE_DRV_MSG_CODE_CMD_SET_LINK); 6294 } else { 6295 mii = device_get_softc(sc->bce_miibus); 6296 6297 /* Make sure the MII bus has been enumerated. */ 6298 if (mii) { 6299 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 6300 PHY_RESET(miisc); 6301 error = mii_mediachg(mii); 6302 } 6303 } 6304 6305 DBEXIT(BCE_VERBOSE_PHY); 6306 return (error); 6307} 6308 6309 6310static void 6311bce_ifmedia_sts_rphy(struct bce_softc *sc, struct ifmediareq *ifmr) 6312{ 6313 struct ifnet *ifp; 6314 u32 link; 6315 6316 ifp = sc->bce_ifp; 6317 BCE_LOCK_ASSERT(sc); 6318 6319 ifmr->ifm_status = IFM_AVALID; 6320 ifmr->ifm_active = IFM_ETHER; 6321 link = bce_shmem_rd(sc, BCE_LINK_STATUS); 6322 /* XXX Handle heart beat status? */ 6323 if ((link & BCE_LINK_STATUS_LINK_UP) != 0) 6324 ifmr->ifm_status |= IFM_ACTIVE; 6325 else { 6326 ifmr->ifm_active |= IFM_NONE; 6327 ifp->if_baudrate = 0; 6328 return; 6329 } 6330 switch (link & BCE_LINK_STATUS_SPEED_MASK) { 6331 case BCE_LINK_STATUS_10HALF: 6332 ifmr->ifm_active |= IFM_10_T | IFM_HDX; 6333 ifp->if_baudrate = IF_Mbps(10UL); 6334 break; 6335 case BCE_LINK_STATUS_10FULL: 6336 ifmr->ifm_active |= IFM_10_T | IFM_FDX; 6337 ifp->if_baudrate = IF_Mbps(10UL); 6338 break; 6339 case BCE_LINK_STATUS_100HALF: 6340 ifmr->ifm_active |= IFM_100_TX | IFM_HDX; 6341 ifp->if_baudrate = IF_Mbps(100UL); 6342 break; 6343 case BCE_LINK_STATUS_100FULL: 6344 ifmr->ifm_active |= IFM_100_TX | IFM_FDX; 6345 ifp->if_baudrate = IF_Mbps(100UL); 6346 break; 6347 case BCE_LINK_STATUS_1000HALF: 6348 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) 6349 ifmr->ifm_active |= IFM_1000_T | IFM_HDX; 6350 else 6351 ifmr->ifm_active |= IFM_1000_SX | IFM_HDX; 6352 ifp->if_baudrate = IF_Mbps(1000UL); 6353 break; 6354 case BCE_LINK_STATUS_1000FULL: 6355 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) 6356 ifmr->ifm_active |= IFM_1000_T | IFM_FDX; 6357 else 6358 ifmr->ifm_active |= IFM_1000_SX | IFM_FDX; 6359 ifp->if_baudrate = IF_Mbps(1000UL); 6360 break; 6361 case BCE_LINK_STATUS_2500HALF: 6362 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) { 6363 ifmr->ifm_active |= IFM_NONE; 6364 return; 6365 } else 6366 ifmr->ifm_active |= IFM_2500_SX | IFM_HDX; 6367 ifp->if_baudrate = IF_Mbps(2500UL); 6368 break; 6369 case BCE_LINK_STATUS_2500FULL: 6370 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) { 6371 ifmr->ifm_active |= IFM_NONE; 6372 return; 6373 } else 6374 ifmr->ifm_active |= IFM_2500_SX | IFM_FDX; 6375 ifp->if_baudrate = IF_Mbps(2500UL); 6376 break; 6377 default: 6378 ifmr->ifm_active |= IFM_NONE; 6379 return; 6380 } 6381 6382 if ((link & BCE_LINK_STATUS_RX_FC_ENABLED) != 0) 6383 ifmr->ifm_active |= IFM_ETH_RXPAUSE; 6384 if ((link & BCE_LINK_STATUS_TX_FC_ENABLED) != 0) 6385 ifmr->ifm_active |= IFM_ETH_TXPAUSE; 6386} 6387 6388 6389/****************************************************************************/ 6390/* Reports current media status. */ 6391/* */ 6392/* Returns: */ 6393/* Nothing. */ 6394/****************************************************************************/ 6395static void 6396bce_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 6397{ 6398 struct bce_softc *sc = ifp->if_softc; 6399 struct mii_data *mii; 6400 6401 DBENTER(BCE_VERBOSE_PHY); 6402 6403 BCE_LOCK(sc); 6404 6405 if ((ifp->if_flags & IFF_UP) == 0) { 6406 BCE_UNLOCK(sc); 6407 return; 6408 } 6409 6410 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) 6411 bce_ifmedia_sts_rphy(sc, ifmr); 6412 else { 6413 mii = device_get_softc(sc->bce_miibus); 6414 mii_pollstat(mii); 6415 ifmr->ifm_active = mii->mii_media_active; 6416 ifmr->ifm_status = mii->mii_media_status; 6417 } 6418 6419 BCE_UNLOCK(sc); 6420 6421 DBEXIT(BCE_VERBOSE_PHY); 6422} 6423 6424 6425/****************************************************************************/ 6426/* Handles PHY generated interrupt events. */ 6427/* */ 6428/* Returns: */ 6429/* Nothing. */ 6430/****************************************************************************/ 6431static void 6432bce_phy_intr(struct bce_softc *sc) 6433{ 6434 u32 new_link_state, old_link_state; 6435 6436 DBENTER(BCE_VERBOSE_PHY | BCE_VERBOSE_INTR); 6437 6438 DBRUN(sc->phy_interrupts++); 6439 6440 new_link_state = sc->status_block->status_attn_bits & 6441 STATUS_ATTN_BITS_LINK_STATE; 6442 old_link_state = sc->status_block->status_attn_bits_ack & 6443 STATUS_ATTN_BITS_LINK_STATE; 6444 6445 /* Handle any changes if the link state has changed. */ 6446 if (new_link_state != old_link_state) { 6447 6448 /* Update the status_attn_bits_ack field. */ 6449 if (new_link_state) { 6450 REG_WR(sc, BCE_PCICFG_STATUS_BIT_SET_CMD, 6451 STATUS_ATTN_BITS_LINK_STATE); 6452 DBPRINT(sc, BCE_INFO_PHY, "%s(): Link is now UP.\n", 6453 __FUNCTION__); 6454 } else { 6455 REG_WR(sc, BCE_PCICFG_STATUS_BIT_CLEAR_CMD, 6456 STATUS_ATTN_BITS_LINK_STATE); 6457 DBPRINT(sc, BCE_INFO_PHY, "%s(): Link is now DOWN.\n", 6458 __FUNCTION__); 6459 } 6460 6461 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) { 6462 if (new_link_state) { 6463 if (bootverbose) 6464 if_printf(sc->bce_ifp, "link UP\n"); 6465 if_link_state_change(sc->bce_ifp, 6466 LINK_STATE_UP); 6467 } else { 6468 if (bootverbose) 6469 if_printf(sc->bce_ifp, "link DOWN\n"); 6470 if_link_state_change(sc->bce_ifp, 6471 LINK_STATE_DOWN); 6472 } 6473 } 6474 /* 6475 * Assume link is down and allow 6476 * tick routine to update the state 6477 * based on the actual media state. 6478 */ 6479 sc->bce_link_up = FALSE; 6480 callout_stop(&sc->bce_tick_callout); 6481 bce_tick(sc); 6482 } 6483 6484 /* Acknowledge the link change interrupt. */ 6485 REG_WR(sc, BCE_EMAC_STATUS, BCE_EMAC_STATUS_LINK_CHANGE); 6486 6487 DBEXIT(BCE_VERBOSE_PHY | BCE_VERBOSE_INTR); 6488} 6489 6490 6491/****************************************************************************/ 6492/* Reads the receive consumer value from the status block (skipping over */ 6493/* chain page pointer if necessary). */ 6494/* */ 6495/* Returns: */ 6496/* hw_cons */ 6497/****************************************************************************/ 6498static inline u16 6499bce_get_hw_rx_cons(struct bce_softc *sc) 6500{ 6501 u16 hw_cons; 6502 6503 rmb(); 6504 hw_cons = sc->status_block->status_rx_quick_consumer_index0; 6505 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 6506 hw_cons++; 6507 6508 return hw_cons; 6509} 6510 6511/****************************************************************************/ 6512/* Handles received frame interrupt events. */ 6513/* */ 6514/* Returns: */ 6515/* Nothing. */ 6516/****************************************************************************/ 6517static void 6518bce_rx_intr(struct bce_softc *sc) 6519{ 6520 struct ifnet *ifp = sc->bce_ifp; 6521 struct l2_fhdr *l2fhdr; 6522 struct ether_vlan_header *vh; 6523 unsigned int pkt_len; 6524 u16 sw_rx_cons, sw_rx_cons_idx, hw_rx_cons; 6525 u32 status; 6526 unsigned int rem_len; 6527 u16 sw_pg_cons, sw_pg_cons_idx; 6528 6529 DBENTER(BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 6530 DBRUN(sc->interrupts_rx++); 6531 DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): rx_prod = 0x%04X, " 6532 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n", 6533 __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq); 6534 6535 /* Prepare the RX chain pages to be accessed by the host CPU. */ 6536 for (int i = 0; i < sc->rx_pages; i++) 6537 bus_dmamap_sync(sc->rx_bd_chain_tag, 6538 sc->rx_bd_chain_map[i], BUS_DMASYNC_POSTREAD); 6539 6540 /* Prepare the page chain pages to be accessed by the host CPU. */ 6541 if (bce_hdr_split == TRUE) { 6542 for (int i = 0; i < sc->pg_pages; i++) 6543 bus_dmamap_sync(sc->pg_bd_chain_tag, 6544 sc->pg_bd_chain_map[i], BUS_DMASYNC_POSTREAD); 6545 } 6546 6547 /* Get the hardware's view of the RX consumer index. */ 6548 hw_rx_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc); 6549 6550 /* Get working copies of the driver's view of the consumer indices. */ 6551 sw_rx_cons = sc->rx_cons; 6552 sw_pg_cons = sc->pg_cons; 6553 6554 /* Update some debug statistics counters */ 6555 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 6556 sc->rx_low_watermark = sc->free_rx_bd); 6557 DBRUNIF((sc->free_rx_bd == sc->max_rx_bd), 6558 sc->rx_empty_count++); 6559 6560 /* Scan through the receive chain as long as there is work to do */ 6561 /* ToDo: Consider setting a limit on the number of packets processed. */ 6562 rmb(); 6563 while (sw_rx_cons != hw_rx_cons) { 6564 struct mbuf *m0; 6565 6566 /* Convert the producer/consumer indices to an actual rx_bd index. */ 6567 sw_rx_cons_idx = RX_CHAIN_IDX(sw_rx_cons); 6568 6569 /* Unmap the mbuf from DMA space. */ 6570 bus_dmamap_sync(sc->rx_mbuf_tag, 6571 sc->rx_mbuf_map[sw_rx_cons_idx], 6572 BUS_DMASYNC_POSTREAD); 6573 bus_dmamap_unload(sc->rx_mbuf_tag, 6574 sc->rx_mbuf_map[sw_rx_cons_idx]); 6575 6576 /* Remove the mbuf from the RX chain. */ 6577 m0 = sc->rx_mbuf_ptr[sw_rx_cons_idx]; 6578 sc->rx_mbuf_ptr[sw_rx_cons_idx] = NULL; 6579 DBRUN(sc->debug_rx_mbuf_alloc--); 6580 sc->free_rx_bd++; 6581 6582 /* 6583 * Frames received on the NetXteme II are prepended 6584 * with an l2_fhdr structure which provides status 6585 * information about the received frame (including 6586 * VLAN tags and checksum info). The frames are 6587 * also automatically adjusted to word align the IP 6588 * header (i.e. two null bytes are inserted before 6589 * the Ethernet header). As a result the data 6590 * DMA'd by the controller into the mbuf looks 6591 * like this: 6592 * 6593 * +---------+-----+---------------------+-----+ 6594 * | l2_fhdr | pad | packet data | FCS | 6595 * +---------+-----+---------------------+-----+ 6596 * 6597 * The l2_fhdr needs to be checked and skipped and 6598 * the FCS needs to be stripped before sending the 6599 * packet up the stack. 6600 */ 6601 l2fhdr = mtod(m0, struct l2_fhdr *); 6602 6603 /* Get the packet data + FCS length and the status. */ 6604 pkt_len = l2fhdr->l2_fhdr_pkt_len; 6605 status = l2fhdr->l2_fhdr_status; 6606 6607 /* 6608 * Skip over the l2_fhdr and pad, resulting in the 6609 * following data in the mbuf: 6610 * +---------------------+-----+ 6611 * | packet data | FCS | 6612 * +---------------------+-----+ 6613 */ 6614 m_adj(m0, sizeof(struct l2_fhdr) + ETHER_ALIGN); 6615 6616 /* 6617 * When split header mode is used, an ethernet frame 6618 * may be split across the receive chain and the 6619 * page chain. If that occurs an mbuf cluster must be 6620 * reassembled from the individual mbuf pieces. 6621 */ 6622 if (bce_hdr_split == TRUE) { 6623 /* 6624 * Check whether the received frame fits in a single 6625 * mbuf or not (i.e. packet data + FCS <= 6626 * sc->rx_bd_mbuf_data_len bytes). 6627 */ 6628 if (pkt_len > m0->m_len) { 6629 /* 6630 * The received frame is larger than a single mbuf. 6631 * If the frame was a TCP frame then only the TCP 6632 * header is placed in the mbuf, the remaining 6633 * payload (including FCS) is placed in the page 6634 * chain, the SPLIT flag is set, and the header 6635 * length is placed in the IP checksum field. 6636 * If the frame is not a TCP frame then the mbuf 6637 * is filled and the remaining bytes are placed 6638 * in the page chain. 6639 */ 6640 6641 DBPRINT(sc, BCE_INFO_RECV, "%s(): Found a large " 6642 "packet.\n", __FUNCTION__); 6643 DBRUN(sc->split_header_frames_rcvd++); 6644 6645 /* 6646 * When the page chain is enabled and the TCP 6647 * header has been split from the TCP payload, 6648 * the ip_xsum structure will reflect the length 6649 * of the TCP header, not the IP checksum. Set 6650 * the packet length of the mbuf accordingly. 6651 */ 6652 if (status & L2_FHDR_STATUS_SPLIT) { 6653 m0->m_len = l2fhdr->l2_fhdr_ip_xsum; 6654 DBRUN(sc->split_header_tcp_frames_rcvd++); 6655 } 6656 6657 rem_len = pkt_len - m0->m_len; 6658 6659 /* Pull mbufs off the page chain for any remaining data. */ 6660 while (rem_len > 0) { 6661 struct mbuf *m_pg; 6662 6663 sw_pg_cons_idx = PG_CHAIN_IDX(sw_pg_cons); 6664 6665 /* Remove the mbuf from the page chain. */ 6666 m_pg = sc->pg_mbuf_ptr[sw_pg_cons_idx]; 6667 sc->pg_mbuf_ptr[sw_pg_cons_idx] = NULL; 6668 DBRUN(sc->debug_pg_mbuf_alloc--); 6669 sc->free_pg_bd++; 6670 6671 /* Unmap the page chain mbuf from DMA space. */ 6672 bus_dmamap_sync(sc->pg_mbuf_tag, 6673 sc->pg_mbuf_map[sw_pg_cons_idx], 6674 BUS_DMASYNC_POSTREAD); 6675 bus_dmamap_unload(sc->pg_mbuf_tag, 6676 sc->pg_mbuf_map[sw_pg_cons_idx]); 6677 6678 /* Adjust the mbuf length. */ 6679 if (rem_len < m_pg->m_len) { 6680 /* The mbuf chain is complete. */ 6681 m_pg->m_len = rem_len; 6682 rem_len = 0; 6683 } else { 6684 /* More packet data is waiting. */ 6685 rem_len -= m_pg->m_len; 6686 } 6687 6688 /* Concatenate the mbuf cluster to the mbuf. */ 6689 m_cat(m0, m_pg); 6690 6691 sw_pg_cons = NEXT_PG_BD(sw_pg_cons); 6692 } 6693 6694 /* Set the total packet length. */ 6695 m0->m_pkthdr.len = pkt_len; 6696 6697 } else { 6698 /* 6699 * The received packet is small and fits in a 6700 * single mbuf (i.e. the l2_fhdr + pad + packet + 6701 * FCS <= MHLEN). In other words, the packet is 6702 * 154 bytes or less in size. 6703 */ 6704 6705 DBPRINT(sc, BCE_INFO_RECV, "%s(): Found a small " 6706 "packet.\n", __FUNCTION__); 6707 6708 /* Set the total packet length. */ 6709 m0->m_pkthdr.len = m0->m_len = pkt_len; 6710 } 6711 } else 6712 /* Set the total packet length. */ 6713 m0->m_pkthdr.len = m0->m_len = pkt_len; 6714 6715 /* Remove the trailing Ethernet FCS. */ 6716 m_adj(m0, -ETHER_CRC_LEN); 6717 6718 /* Check that the resulting mbuf chain is valid. */ 6719 DBRUN(m_sanity(m0, FALSE)); 6720 DBRUNIF(((m0->m_len < ETHER_HDR_LEN) | 6721 (m0->m_pkthdr.len > BCE_MAX_JUMBO_ETHER_MTU_VLAN)), 6722 BCE_PRINTF("Invalid Ethernet frame size!\n"); 6723 m_print(m0, 128)); 6724 6725 DBRUNIF(DB_RANDOMTRUE(l2fhdr_error_sim_control), 6726 sc->l2fhdr_error_sim_count++; 6727 status = status | L2_FHDR_ERRORS_PHY_DECODE); 6728 6729 /* Check the received frame for errors. */ 6730 if (status & (L2_FHDR_ERRORS_BAD_CRC | 6731 L2_FHDR_ERRORS_PHY_DECODE | L2_FHDR_ERRORS_ALIGNMENT | 6732 L2_FHDR_ERRORS_TOO_SHORT | L2_FHDR_ERRORS_GIANT_FRAME)) { 6733 6734 /* Log the error and release the mbuf. */ 6735 ifp->if_ierrors++; 6736 sc->l2fhdr_error_count++; 6737 6738 m_freem(m0); 6739 m0 = NULL; 6740 goto bce_rx_intr_next_rx; 6741 } 6742 6743 /* Send the packet to the appropriate interface. */ 6744 m0->m_pkthdr.rcvif = ifp; 6745 6746 /* Assume no hardware checksum. */ 6747 m0->m_pkthdr.csum_flags = 0; 6748 6749 /* Validate the checksum if offload enabled. */ 6750 if (ifp->if_capenable & IFCAP_RXCSUM) { 6751 /* Check for an IP datagram. */ 6752 if (!(status & L2_FHDR_STATUS_SPLIT) && 6753 (status & L2_FHDR_STATUS_IP_DATAGRAM)) { 6754 m0->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 6755 DBRUN(sc->csum_offload_ip++); 6756 /* Check if the IP checksum is valid. */ 6757 if ((l2fhdr->l2_fhdr_ip_xsum ^ 0xffff) == 0) 6758 m0->m_pkthdr.csum_flags |= 6759 CSUM_IP_VALID; 6760 } 6761 6762 /* Check for a valid TCP/UDP frame. */ 6763 if (status & (L2_FHDR_STATUS_TCP_SEGMENT | 6764 L2_FHDR_STATUS_UDP_DATAGRAM)) { 6765 6766 /* Check for a good TCP/UDP checksum. */ 6767 if ((status & (L2_FHDR_ERRORS_TCP_XSUM | 6768 L2_FHDR_ERRORS_UDP_XSUM)) == 0) { 6769 DBRUN(sc->csum_offload_tcp_udp++); 6770 m0->m_pkthdr.csum_data = 6771 l2fhdr->l2_fhdr_tcp_udp_xsum; 6772 m0->m_pkthdr.csum_flags |= 6773 (CSUM_DATA_VALID 6774 | CSUM_PSEUDO_HDR); 6775 } 6776 } 6777 } 6778 6779 /* Attach the VLAN tag. */ 6780 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && 6781 !(sc->rx_mode & BCE_EMAC_RX_MODE_KEEP_VLAN_TAG)) { 6782 DBRUN(sc->vlan_tagged_frames_rcvd++); 6783 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) { 6784 DBRUN(sc->vlan_tagged_frames_stripped++); 6785#if __FreeBSD_version < 700000 6786 VLAN_INPUT_TAG(ifp, m0, 6787 l2fhdr->l2_fhdr_vlan_tag, continue); 6788#else 6789 m0->m_pkthdr.ether_vtag = 6790 l2fhdr->l2_fhdr_vlan_tag; 6791 m0->m_flags |= M_VLANTAG; 6792#endif 6793 } else { 6794 /* 6795 * bce(4) controllers can't disable VLAN 6796 * tag stripping if management firmware 6797 * (ASF/IPMI/UMP) is running. So we always 6798 * strip VLAN tag and manually reconstruct 6799 * the VLAN frame by appending stripped 6800 * VLAN tag in driver if VLAN tag stripping 6801 * was disabled. 6802 * 6803 * TODO: LLC SNAP handling. 6804 */ 6805 bcopy(mtod(m0, uint8_t *), 6806 mtod(m0, uint8_t *) - ETHER_VLAN_ENCAP_LEN, 6807 ETHER_ADDR_LEN * 2); 6808 m0->m_data -= ETHER_VLAN_ENCAP_LEN; 6809 vh = mtod(m0, struct ether_vlan_header *); 6810 vh->evl_encap_proto = htons(ETHERTYPE_VLAN); 6811 vh->evl_tag = htons(l2fhdr->l2_fhdr_vlan_tag); 6812 m0->m_pkthdr.len += ETHER_VLAN_ENCAP_LEN; 6813 m0->m_len += ETHER_VLAN_ENCAP_LEN; 6814 } 6815 } 6816 6817 /* Increment received packet statistics. */ 6818 ifp->if_ipackets++; 6819 6820bce_rx_intr_next_rx: 6821 sw_rx_cons = NEXT_RX_BD(sw_rx_cons); 6822 6823 /* If we have a packet, pass it up the stack */ 6824 if (m0) { 6825 /* Make sure we don't lose our place when we release the lock. */ 6826 sc->rx_cons = sw_rx_cons; 6827 sc->pg_cons = sw_pg_cons; 6828 6829 BCE_UNLOCK(sc); 6830 (*ifp->if_input)(ifp, m0); 6831 BCE_LOCK(sc); 6832 6833 /* Recover our place. */ 6834 sw_rx_cons = sc->rx_cons; 6835 sw_pg_cons = sc->pg_cons; 6836 } 6837 6838 /* Refresh hw_cons to see if there's new work */ 6839 if (sw_rx_cons == hw_rx_cons) 6840 hw_rx_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc); 6841 } 6842 6843 /* No new packets. Refill the page chain. */ 6844 if (bce_hdr_split == TRUE) { 6845 sc->pg_cons = sw_pg_cons; 6846 bce_fill_pg_chain(sc); 6847 } 6848 6849 /* No new packets. Refill the RX chain. */ 6850 sc->rx_cons = sw_rx_cons; 6851 bce_fill_rx_chain(sc); 6852 6853 /* Prepare the page chain pages to be accessed by the NIC. */ 6854 for (int i = 0; i < sc->rx_pages; i++) 6855 bus_dmamap_sync(sc->rx_bd_chain_tag, 6856 sc->rx_bd_chain_map[i], BUS_DMASYNC_PREWRITE); 6857 6858 if (bce_hdr_split == TRUE) { 6859 for (int i = 0; i < sc->pg_pages; i++) 6860 bus_dmamap_sync(sc->pg_bd_chain_tag, 6861 sc->pg_bd_chain_map[i], BUS_DMASYNC_PREWRITE); 6862 } 6863 6864 DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): rx_prod = 0x%04X, " 6865 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n", 6866 __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq); 6867 DBEXIT(BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 6868} 6869 6870 6871/****************************************************************************/ 6872/* Reads the transmit consumer value from the status block (skipping over */ 6873/* chain page pointer if necessary). */ 6874/* */ 6875/* Returns: */ 6876/* hw_cons */ 6877/****************************************************************************/ 6878static inline u16 6879bce_get_hw_tx_cons(struct bce_softc *sc) 6880{ 6881 u16 hw_cons; 6882 6883 mb(); 6884 hw_cons = sc->status_block->status_tx_quick_consumer_index0; 6885 if ((hw_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 6886 hw_cons++; 6887 6888 return hw_cons; 6889} 6890 6891 6892/****************************************************************************/ 6893/* Handles transmit completion interrupt events. */ 6894/* */ 6895/* Returns: */ 6896/* Nothing. */ 6897/****************************************************************************/ 6898static void 6899bce_tx_intr(struct bce_softc *sc) 6900{ 6901 struct ifnet *ifp = sc->bce_ifp; 6902 u16 hw_tx_cons, sw_tx_cons, sw_tx_chain_cons; 6903 6904 DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_INTR); 6905 DBRUN(sc->interrupts_tx++); 6906 DBPRINT(sc, BCE_EXTREME_SEND, "%s(enter): tx_prod = 0x%04X, " 6907 "tx_cons = 0x%04X, tx_prod_bseq = 0x%08X\n", 6908 __FUNCTION__, sc->tx_prod, sc->tx_cons, sc->tx_prod_bseq); 6909 6910 BCE_LOCK_ASSERT(sc); 6911 6912 /* Get the hardware's view of the TX consumer index. */ 6913 hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc); 6914 sw_tx_cons = sc->tx_cons; 6915 6916 /* Prevent speculative reads of the status block. */ 6917 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 6918 BUS_SPACE_BARRIER_READ); 6919 6920 /* Cycle through any completed TX chain page entries. */ 6921 while (sw_tx_cons != hw_tx_cons) { 6922#ifdef BCE_DEBUG 6923 struct tx_bd *txbd = NULL; 6924#endif 6925 sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons); 6926 6927 DBPRINT(sc, BCE_INFO_SEND, 6928 "%s(): hw_tx_cons = 0x%04X, sw_tx_cons = 0x%04X, " 6929 "sw_tx_chain_cons = 0x%04X\n", 6930 __FUNCTION__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons); 6931 6932 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD_ALLOC), 6933 BCE_PRINTF("%s(%d): TX chain consumer out of range! " 6934 " 0x%04X > 0x%04X\n", __FILE__, __LINE__, sw_tx_chain_cons, 6935 (int) MAX_TX_BD_ALLOC); 6936 bce_breakpoint(sc)); 6937 6938 DBRUN(txbd = &sc->tx_bd_chain[TX_PAGE(sw_tx_chain_cons)] 6939 [TX_IDX(sw_tx_chain_cons)]); 6940 6941 DBRUNIF((txbd == NULL), 6942 BCE_PRINTF("%s(%d): Unexpected NULL tx_bd[0x%04X]!\n", 6943 __FILE__, __LINE__, sw_tx_chain_cons); 6944 bce_breakpoint(sc)); 6945 6946 DBRUNMSG(BCE_INFO_SEND, BCE_PRINTF("%s(): ", __FUNCTION__); 6947 bce_dump_txbd(sc, sw_tx_chain_cons, txbd)); 6948 6949 /* 6950 * Free the associated mbuf. Remember 6951 * that only the last tx_bd of a packet 6952 * has an mbuf pointer and DMA map. 6953 */ 6954 if (sc->tx_mbuf_ptr[sw_tx_chain_cons] != NULL) { 6955 6956 /* Validate that this is the last tx_bd. */ 6957 DBRUNIF((!(txbd->tx_bd_flags & TX_BD_FLAGS_END)), 6958 BCE_PRINTF("%s(%d): tx_bd END flag not set but " 6959 "txmbuf == NULL!\n", __FILE__, __LINE__); 6960 bce_breakpoint(sc)); 6961 6962 DBRUNMSG(BCE_INFO_SEND, 6963 BCE_PRINTF("%s(): Unloading map/freeing mbuf " 6964 "from tx_bd[0x%04X]\n", __FUNCTION__, 6965 sw_tx_chain_cons)); 6966 6967 /* Unmap the mbuf. */ 6968 bus_dmamap_unload(sc->tx_mbuf_tag, 6969 sc->tx_mbuf_map[sw_tx_chain_cons]); 6970 6971 /* Free the mbuf. */ 6972 m_freem(sc->tx_mbuf_ptr[sw_tx_chain_cons]); 6973 sc->tx_mbuf_ptr[sw_tx_chain_cons] = NULL; 6974 DBRUN(sc->debug_tx_mbuf_alloc--); 6975 6976 ifp->if_opackets++; 6977 } 6978 6979 sc->used_tx_bd--; 6980 sw_tx_cons = NEXT_TX_BD(sw_tx_cons); 6981 6982 /* Refresh hw_cons to see if there's new work. */ 6983 hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc); 6984 6985 /* Prevent speculative reads of the status block. */ 6986 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 6987 BUS_SPACE_BARRIER_READ); 6988 } 6989 6990 /* Clear the TX timeout timer. */ 6991 sc->watchdog_timer = 0; 6992 6993 /* Clear the tx hardware queue full flag. */ 6994 if (sc->used_tx_bd < sc->max_tx_bd) { 6995 DBRUNIF((ifp->if_drv_flags & IFF_DRV_OACTIVE), 6996 DBPRINT(sc, BCE_INFO_SEND, 6997 "%s(): Open TX chain! %d/%d (used/total)\n", 6998 __FUNCTION__, sc->used_tx_bd, sc->max_tx_bd)); 6999 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 7000 } 7001 7002 sc->tx_cons = sw_tx_cons; 7003 7004 DBPRINT(sc, BCE_EXTREME_SEND, "%s(exit): tx_prod = 0x%04X, " 7005 "tx_cons = 0x%04X, tx_prod_bseq = 0x%08X\n", 7006 __FUNCTION__, sc->tx_prod, sc->tx_cons, sc->tx_prod_bseq); 7007 DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_INTR); 7008} 7009 7010 7011/****************************************************************************/ 7012/* Disables interrupt generation. */ 7013/* */ 7014/* Returns: */ 7015/* Nothing. */ 7016/****************************************************************************/ 7017static void 7018bce_disable_intr(struct bce_softc *sc) 7019{ 7020 DBENTER(BCE_VERBOSE_INTR); 7021 7022 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT); 7023 REG_RD(sc, BCE_PCICFG_INT_ACK_CMD); 7024 7025 DBEXIT(BCE_VERBOSE_INTR); 7026} 7027 7028 7029/****************************************************************************/ 7030/* Enables interrupt generation. */ 7031/* */ 7032/* Returns: */ 7033/* Nothing. */ 7034/****************************************************************************/ 7035static void 7036bce_enable_intr(struct bce_softc *sc, int coal_now) 7037{ 7038 DBENTER(BCE_VERBOSE_INTR); 7039 7040 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 7041 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | 7042 BCE_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx); 7043 7044 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 7045 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx); 7046 7047 /* Force an immediate interrupt (whether there is new data or not). */ 7048 if (coal_now) 7049 REG_WR(sc, BCE_HC_COMMAND, sc->hc_command | BCE_HC_COMMAND_COAL_NOW); 7050 7051 DBEXIT(BCE_VERBOSE_INTR); 7052} 7053 7054 7055/****************************************************************************/ 7056/* Handles controller initialization. */ 7057/* */ 7058/* Returns: */ 7059/* Nothing. */ 7060/****************************************************************************/ 7061static void 7062bce_init_locked(struct bce_softc *sc) 7063{ 7064 struct ifnet *ifp; 7065 u32 ether_mtu = 0; 7066 7067 DBENTER(BCE_VERBOSE_RESET); 7068 7069 BCE_LOCK_ASSERT(sc); 7070 7071 ifp = sc->bce_ifp; 7072 7073 /* Check if the driver is still running and bail out if it is. */ 7074 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 7075 goto bce_init_locked_exit; 7076 7077 bce_stop(sc); 7078 7079 if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) { 7080 BCE_PRINTF("%s(%d): Controller reset failed!\n", 7081 __FILE__, __LINE__); 7082 goto bce_init_locked_exit; 7083 } 7084 7085 if (bce_chipinit(sc)) { 7086 BCE_PRINTF("%s(%d): Controller initialization failed!\n", 7087 __FILE__, __LINE__); 7088 goto bce_init_locked_exit; 7089 } 7090 7091 if (bce_blockinit(sc)) { 7092 BCE_PRINTF("%s(%d): Block initialization failed!\n", 7093 __FILE__, __LINE__); 7094 goto bce_init_locked_exit; 7095 } 7096 7097 /* Load our MAC address. */ 7098 bcopy(IF_LLADDR(sc->bce_ifp), sc->eaddr, ETHER_ADDR_LEN); 7099 bce_set_mac_addr(sc); 7100 7101 if (bce_hdr_split == FALSE) 7102 bce_get_rx_buffer_sizes(sc, ifp->if_mtu); 7103 /* 7104 * Calculate and program the hardware Ethernet MTU 7105 * size. Be generous on the receive if we have room 7106 * and allowed by the user. 7107 */ 7108 if (bce_strict_rx_mtu == TRUE) 7109 ether_mtu = ifp->if_mtu; 7110 else { 7111 if (bce_hdr_split == TRUE) { 7112 if (ifp->if_mtu <= sc->rx_bd_mbuf_data_len + MCLBYTES) 7113 ether_mtu = sc->rx_bd_mbuf_data_len + 7114 MCLBYTES; 7115 else 7116 ether_mtu = ifp->if_mtu; 7117 } else { 7118 if (ifp->if_mtu <= sc->rx_bd_mbuf_data_len) 7119 ether_mtu = sc->rx_bd_mbuf_data_len; 7120 else 7121 ether_mtu = ifp->if_mtu; 7122 } 7123 } 7124 7125 ether_mtu += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN; 7126 7127 DBPRINT(sc, BCE_INFO_MISC, "%s(): setting h/w mtu = %d\n", 7128 __FUNCTION__, ether_mtu); 7129 7130 /* Program the mtu, enabling jumbo frame support if necessary. */ 7131 if (ether_mtu > (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN)) 7132 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, 7133 min(ether_mtu, BCE_MAX_JUMBO_ETHER_MTU) | 7134 BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA); 7135 else 7136 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, ether_mtu); 7137 7138 /* Program appropriate promiscuous/multicast filtering. */ 7139 bce_set_rx_mode(sc); 7140 7141 if (bce_hdr_split == TRUE) { 7142 /* Init page buffer descriptor chain. */ 7143 bce_init_pg_chain(sc); 7144 } 7145 7146 /* Init RX buffer descriptor chain. */ 7147 bce_init_rx_chain(sc); 7148 7149 /* Init TX buffer descriptor chain. */ 7150 bce_init_tx_chain(sc); 7151 7152 /* Enable host interrupts. */ 7153 bce_enable_intr(sc, 1); 7154 7155 bce_ifmedia_upd_locked(ifp); 7156 7157 /* Let the OS know the driver is up and running. */ 7158 ifp->if_drv_flags |= IFF_DRV_RUNNING; 7159 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 7160 7161 callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc); 7162 7163bce_init_locked_exit: 7164 DBEXIT(BCE_VERBOSE_RESET); 7165} 7166 7167 7168/****************************************************************************/ 7169/* Initialize the controller just enough so that any management firmware */ 7170/* running on the device will continue to operate correctly. */ 7171/* */ 7172/* Returns: */ 7173/* Nothing. */ 7174/****************************************************************************/ 7175static void 7176bce_mgmt_init_locked(struct bce_softc *sc) 7177{ 7178 struct ifnet *ifp; 7179 7180 DBENTER(BCE_VERBOSE_RESET); 7181 7182 BCE_LOCK_ASSERT(sc); 7183 7184 /* Bail out if management firmware is not running. */ 7185 if (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG)) { 7186 DBPRINT(sc, BCE_VERBOSE_SPECIAL, 7187 "No management firmware running...\n"); 7188 goto bce_mgmt_init_locked_exit; 7189 } 7190 7191 ifp = sc->bce_ifp; 7192 7193 /* Enable all critical blocks in the MAC. */ 7194 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT); 7195 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS); 7196 DELAY(20); 7197 7198 bce_ifmedia_upd_locked(ifp); 7199 7200bce_mgmt_init_locked_exit: 7201 DBEXIT(BCE_VERBOSE_RESET); 7202} 7203 7204 7205/****************************************************************************/ 7206/* Handles controller initialization when called from an unlocked routine. */ 7207/* */ 7208/* Returns: */ 7209/* Nothing. */ 7210/****************************************************************************/ 7211static void 7212bce_init(void *xsc) 7213{ 7214 struct bce_softc *sc = xsc; 7215 7216 DBENTER(BCE_VERBOSE_RESET); 7217 7218 BCE_LOCK(sc); 7219 bce_init_locked(sc); 7220 BCE_UNLOCK(sc); 7221 7222 DBEXIT(BCE_VERBOSE_RESET); 7223} 7224 7225 7226/****************************************************************************/ 7227/* Modifies an mbuf for TSO on the hardware. */ 7228/* */ 7229/* Returns: */ 7230/* Pointer to a modified mbuf. */ 7231/****************************************************************************/ 7232static struct mbuf * 7233bce_tso_setup(struct bce_softc *sc, struct mbuf **m_head, u16 *flags) 7234{ 7235 struct mbuf *m; 7236 struct ether_header *eh; 7237 struct ip *ip; 7238 struct tcphdr *th; 7239 u16 etype; 7240 int hdr_len, ip_hlen = 0, tcp_hlen = 0, ip_len = 0; 7241 7242 DBRUN(sc->tso_frames_requested++); 7243 7244 /* Controller may modify mbuf chains. */ 7245 if (M_WRITABLE(*m_head) == 0) { 7246 m = m_dup(*m_head, M_NOWAIT); 7247 m_freem(*m_head); 7248 if (m == NULL) { 7249 sc->mbuf_alloc_failed_count++; 7250 *m_head = NULL; 7251 return (NULL); 7252 } 7253 *m_head = m; 7254 } 7255 7256 /* 7257 * For TSO the controller needs two pieces of info, 7258 * the MSS and the IP+TCP options length. 7259 */ 7260 m = m_pullup(*m_head, sizeof(struct ether_header) + sizeof(struct ip)); 7261 if (m == NULL) { 7262 *m_head = NULL; 7263 return (NULL); 7264 } 7265 eh = mtod(m, struct ether_header *); 7266 etype = ntohs(eh->ether_type); 7267 7268 /* Check for supported TSO Ethernet types (only IPv4 for now) */ 7269 switch (etype) { 7270 case ETHERTYPE_IP: 7271 ip = (struct ip *)(m->m_data + sizeof(struct ether_header)); 7272 /* TSO only supported for TCP protocol. */ 7273 if (ip->ip_p != IPPROTO_TCP) { 7274 BCE_PRINTF("%s(%d): TSO enabled for non-TCP frame!.\n", 7275 __FILE__, __LINE__); 7276 m_freem(*m_head); 7277 *m_head = NULL; 7278 return (NULL); 7279 } 7280 7281 /* Get IP header length in bytes (min 20) */ 7282 ip_hlen = ip->ip_hl << 2; 7283 m = m_pullup(*m_head, sizeof(struct ether_header) + ip_hlen + 7284 sizeof(struct tcphdr)); 7285 if (m == NULL) { 7286 *m_head = NULL; 7287 return (NULL); 7288 } 7289 7290 /* Get the TCP header length in bytes (min 20) */ 7291 ip = (struct ip *)(m->m_data + sizeof(struct ether_header)); 7292 th = (struct tcphdr *)((caddr_t)ip + ip_hlen); 7293 tcp_hlen = (th->th_off << 2); 7294 7295 /* Make sure all IP/TCP options live in the same buffer. */ 7296 m = m_pullup(*m_head, sizeof(struct ether_header)+ ip_hlen + 7297 tcp_hlen); 7298 if (m == NULL) { 7299 *m_head = NULL; 7300 return (NULL); 7301 } 7302 7303 /* Clear IP header length and checksum, will be calc'd by h/w. */ 7304 ip = (struct ip *)(m->m_data + sizeof(struct ether_header)); 7305 ip_len = ip->ip_len; 7306 ip->ip_len = 0; 7307 ip->ip_sum = 0; 7308 break; 7309 case ETHERTYPE_IPV6: 7310 BCE_PRINTF("%s(%d): TSO over IPv6 not supported!.\n", 7311 __FILE__, __LINE__); 7312 m_freem(*m_head); 7313 *m_head = NULL; 7314 return (NULL); 7315 /* NOT REACHED */ 7316 default: 7317 BCE_PRINTF("%s(%d): TSO enabled for unsupported protocol!.\n", 7318 __FILE__, __LINE__); 7319 m_freem(*m_head); 7320 *m_head = NULL; 7321 return (NULL); 7322 } 7323 7324 hdr_len = sizeof(struct ether_header) + ip_hlen + tcp_hlen; 7325 7326 DBPRINT(sc, BCE_EXTREME_SEND, "%s(): hdr_len = %d, e_hlen = %d, " 7327 "ip_hlen = %d, tcp_hlen = %d, ip_len = %d\n", 7328 __FUNCTION__, hdr_len, (int) sizeof(struct ether_header), ip_hlen, 7329 tcp_hlen, ip_len); 7330 7331 /* Set the LSO flag in the TX BD */ 7332 *flags |= TX_BD_FLAGS_SW_LSO; 7333 7334 /* Set the length of IP + TCP options (in 32 bit words) */ 7335 *flags |= (((ip_hlen + tcp_hlen - sizeof(struct ip) - 7336 sizeof(struct tcphdr)) >> 2) << 8); 7337 7338 DBRUN(sc->tso_frames_completed++); 7339 return (*m_head); 7340} 7341 7342 7343/****************************************************************************/ 7344/* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */ 7345/* memory visible to the controller. */ 7346/* */ 7347/* Returns: */ 7348/* 0 for success, positive value for failure. */ 7349/* Modified: */ 7350/* m_head: May be set to NULL if MBUF is excessively fragmented. */ 7351/****************************************************************************/ 7352static int 7353bce_tx_encap(struct bce_softc *sc, struct mbuf **m_head) 7354{ 7355 bus_dma_segment_t segs[BCE_MAX_SEGMENTS]; 7356 bus_dmamap_t map; 7357 struct tx_bd *txbd = NULL; 7358 struct mbuf *m0; 7359 u16 prod, chain_prod, mss = 0, vlan_tag = 0, flags = 0; 7360 u32 prod_bseq; 7361 7362#ifdef BCE_DEBUG 7363 u16 debug_prod; 7364#endif 7365 7366 int i, error, nsegs, rc = 0; 7367 7368 DBENTER(BCE_VERBOSE_SEND); 7369 7370 /* Make sure we have room in the TX chain. */ 7371 if (sc->used_tx_bd >= sc->max_tx_bd) 7372 goto bce_tx_encap_exit; 7373 7374 /* Transfer any checksum offload flags to the bd. */ 7375 m0 = *m_head; 7376 if (m0->m_pkthdr.csum_flags) { 7377 if (m0->m_pkthdr.csum_flags & CSUM_TSO) { 7378 m0 = bce_tso_setup(sc, m_head, &flags); 7379 if (m0 == NULL) { 7380 DBRUN(sc->tso_frames_failed++); 7381 goto bce_tx_encap_exit; 7382 } 7383 mss = htole16(m0->m_pkthdr.tso_segsz); 7384 } else { 7385 if (m0->m_pkthdr.csum_flags & CSUM_IP) 7386 flags |= TX_BD_FLAGS_IP_CKSUM; 7387 if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 7388 flags |= TX_BD_FLAGS_TCP_UDP_CKSUM; 7389 } 7390 } 7391 7392 /* Transfer any VLAN tags to the bd. */ 7393 if (m0->m_flags & M_VLANTAG) { 7394 flags |= TX_BD_FLAGS_VLAN_TAG; 7395 vlan_tag = m0->m_pkthdr.ether_vtag; 7396 } 7397 7398 /* Map the mbuf into DMAable memory. */ 7399 prod = sc->tx_prod; 7400 chain_prod = TX_CHAIN_IDX(prod); 7401 map = sc->tx_mbuf_map[chain_prod]; 7402 7403 /* Map the mbuf into our DMA address space. */ 7404 error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag, map, m0, 7405 segs, &nsegs, BUS_DMA_NOWAIT); 7406 7407 /* Check if the DMA mapping was successful */ 7408 if (error == EFBIG) { 7409 sc->mbuf_frag_count++; 7410 7411 /* Try to defrag the mbuf. */ 7412 m0 = m_collapse(*m_head, M_NOWAIT, BCE_MAX_SEGMENTS); 7413 if (m0 == NULL) { 7414 /* Defrag was unsuccessful */ 7415 m_freem(*m_head); 7416 *m_head = NULL; 7417 sc->mbuf_alloc_failed_count++; 7418 rc = ENOBUFS; 7419 goto bce_tx_encap_exit; 7420 } 7421 7422 /* Defrag was successful, try mapping again */ 7423 *m_head = m0; 7424 error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag, 7425 map, m0, segs, &nsegs, BUS_DMA_NOWAIT); 7426 7427 /* Still getting an error after a defrag. */ 7428 if (error == ENOMEM) { 7429 /* Insufficient DMA buffers available. */ 7430 sc->dma_map_addr_tx_failed_count++; 7431 rc = error; 7432 goto bce_tx_encap_exit; 7433 } else if (error != 0) { 7434 /* Release it and return an error. */ 7435 BCE_PRINTF("%s(%d): Unknown error mapping mbuf into " 7436 "TX chain!\n", __FILE__, __LINE__); 7437 m_freem(m0); 7438 *m_head = NULL; 7439 sc->dma_map_addr_tx_failed_count++; 7440 rc = ENOBUFS; 7441 goto bce_tx_encap_exit; 7442 } 7443 } else if (error == ENOMEM) { 7444 /* Insufficient DMA buffers available. */ 7445 sc->dma_map_addr_tx_failed_count++; 7446 rc = error; 7447 goto bce_tx_encap_exit; 7448 } else if (error != 0) { 7449 m_freem(m0); 7450 *m_head = NULL; 7451 sc->dma_map_addr_tx_failed_count++; 7452 rc = error; 7453 goto bce_tx_encap_exit; 7454 } 7455 7456 /* Make sure there's room in the chain */ 7457 if (nsegs > (sc->max_tx_bd - sc->used_tx_bd)) { 7458 bus_dmamap_unload(sc->tx_mbuf_tag, map); 7459 rc = ENOBUFS; 7460 goto bce_tx_encap_exit; 7461 } 7462 7463 /* prod points to an empty tx_bd at this point. */ 7464 prod_bseq = sc->tx_prod_bseq; 7465 7466#ifdef BCE_DEBUG 7467 debug_prod = chain_prod; 7468#endif 7469 7470 DBPRINT(sc, BCE_INFO_SEND, 7471 "%s(start): prod = 0x%04X, chain_prod = 0x%04X, " 7472 "prod_bseq = 0x%08X\n", 7473 __FUNCTION__, prod, chain_prod, prod_bseq); 7474 7475 /* 7476 * Cycle through each mbuf segment that makes up 7477 * the outgoing frame, gathering the mapping info 7478 * for that segment and creating a tx_bd for 7479 * the mbuf. 7480 */ 7481 for (i = 0; i < nsegs ; i++) { 7482 7483 chain_prod = TX_CHAIN_IDX(prod); 7484 txbd= &sc->tx_bd_chain[TX_PAGE(chain_prod)] 7485 [TX_IDX(chain_prod)]; 7486 7487 txbd->tx_bd_haddr_lo = 7488 htole32(BCE_ADDR_LO(segs[i].ds_addr)); 7489 txbd->tx_bd_haddr_hi = 7490 htole32(BCE_ADDR_HI(segs[i].ds_addr)); 7491 txbd->tx_bd_mss_nbytes = htole32(mss << 16) | 7492 htole16(segs[i].ds_len); 7493 txbd->tx_bd_vlan_tag = htole16(vlan_tag); 7494 txbd->tx_bd_flags = htole16(flags); 7495 prod_bseq += segs[i].ds_len; 7496 if (i == 0) 7497 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_START); 7498 prod = NEXT_TX_BD(prod); 7499 } 7500 7501 /* Set the END flag on the last TX buffer descriptor. */ 7502 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_END); 7503 7504 DBRUNMSG(BCE_EXTREME_SEND, 7505 bce_dump_tx_chain(sc, debug_prod, nsegs)); 7506 7507 /* 7508 * Ensure that the mbuf pointer for this transmission 7509 * is placed at the array index of the last 7510 * descriptor in this chain. This is done 7511 * because a single map is used for all 7512 * segments of the mbuf and we don't want to 7513 * unload the map before all of the segments 7514 * have been freed. 7515 */ 7516 sc->tx_mbuf_ptr[chain_prod] = m0; 7517 sc->used_tx_bd += nsegs; 7518 7519 /* Update some debug statistic counters */ 7520 DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark), 7521 sc->tx_hi_watermark = sc->used_tx_bd); 7522 DBRUNIF((sc->used_tx_bd == sc->max_tx_bd), sc->tx_full_count++); 7523 DBRUNIF(sc->debug_tx_mbuf_alloc++); 7524 7525 DBRUNMSG(BCE_EXTREME_SEND, bce_dump_tx_mbuf_chain(sc, chain_prod, 1)); 7526 7527 /* prod points to the next free tx_bd at this point. */ 7528 sc->tx_prod = prod; 7529 sc->tx_prod_bseq = prod_bseq; 7530 7531 /* Tell the chip about the waiting TX frames. */ 7532 REG_WR16(sc, MB_GET_CID_ADDR(TX_CID) + 7533 BCE_L2MQ_TX_HOST_BIDX, sc->tx_prod); 7534 REG_WR(sc, MB_GET_CID_ADDR(TX_CID) + 7535 BCE_L2MQ_TX_HOST_BSEQ, sc->tx_prod_bseq); 7536 7537bce_tx_encap_exit: 7538 DBEXIT(BCE_VERBOSE_SEND); 7539 return(rc); 7540} 7541 7542 7543/****************************************************************************/ 7544/* Main transmit routine when called from another routine with a lock. */ 7545/* */ 7546/* Returns: */ 7547/* Nothing. */ 7548/****************************************************************************/ 7549static void 7550bce_start_locked(struct ifnet *ifp) 7551{ 7552 struct bce_softc *sc = ifp->if_softc; 7553 struct mbuf *m_head = NULL; 7554 int count = 0; 7555 u16 tx_prod, tx_chain_prod; 7556 7557 DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 7558 7559 BCE_LOCK_ASSERT(sc); 7560 7561 /* prod points to the next free tx_bd. */ 7562 tx_prod = sc->tx_prod; 7563 tx_chain_prod = TX_CHAIN_IDX(tx_prod); 7564 7565 DBPRINT(sc, BCE_INFO_SEND, 7566 "%s(enter): tx_prod = 0x%04X, tx_chain_prod = 0x%04X, " 7567 "tx_prod_bseq = 0x%08X\n", 7568 __FUNCTION__, tx_prod, tx_chain_prod, sc->tx_prod_bseq); 7569 7570 /* If there's no link or the transmit queue is empty then just exit. */ 7571 if (sc->bce_link_up == FALSE) { 7572 DBPRINT(sc, BCE_INFO_SEND, "%s(): No link.\n", 7573 __FUNCTION__); 7574 goto bce_start_locked_exit; 7575 } 7576 7577 if (IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 7578 DBPRINT(sc, BCE_INFO_SEND, "%s(): Transmit queue empty.\n", 7579 __FUNCTION__); 7580 goto bce_start_locked_exit; 7581 } 7582 7583 /* 7584 * Keep adding entries while there is space in the ring. 7585 */ 7586 while (sc->used_tx_bd < sc->max_tx_bd) { 7587 7588 /* Check for any frames to send. */ 7589 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 7590 7591 /* Stop when the transmit queue is empty. */ 7592 if (m_head == NULL) 7593 break; 7594 7595 /* 7596 * Pack the data into the transmit ring. If we 7597 * don't have room, place the mbuf back at the 7598 * head of the queue and set the OACTIVE flag 7599 * to wait for the NIC to drain the chain. 7600 */ 7601 if (bce_tx_encap(sc, &m_head)) { 7602 if (m_head != NULL) 7603 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 7604 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 7605 DBPRINT(sc, BCE_INFO_SEND, 7606 "TX chain is closed for business! Total " 7607 "tx_bd used = %d\n", sc->used_tx_bd); 7608 break; 7609 } 7610 7611 count++; 7612 7613 /* Send a copy of the frame to any BPF listeners. */ 7614 ETHER_BPF_MTAP(ifp, m_head); 7615 } 7616 7617 /* Exit if no packets were dequeued. */ 7618 if (count == 0) { 7619 DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): No packets were " 7620 "dequeued\n", __FUNCTION__); 7621 goto bce_start_locked_exit; 7622 } 7623 7624 DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): Inserted %d frames into " 7625 "send queue.\n", __FUNCTION__, count); 7626 7627 /* Set the tx timeout. */ 7628 sc->watchdog_timer = BCE_TX_TIMEOUT; 7629 7630 DBRUNMSG(BCE_VERBOSE_SEND, bce_dump_ctx(sc, TX_CID)); 7631 DBRUNMSG(BCE_VERBOSE_SEND, bce_dump_mq_regs(sc)); 7632 7633bce_start_locked_exit: 7634 DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 7635} 7636 7637 7638/****************************************************************************/ 7639/* Main transmit routine when called from another routine without a lock. */ 7640/* */ 7641/* Returns: */ 7642/* Nothing. */ 7643/****************************************************************************/ 7644static void 7645bce_start(struct ifnet *ifp) 7646{ 7647 struct bce_softc *sc = ifp->if_softc; 7648 7649 DBENTER(BCE_VERBOSE_SEND); 7650 7651 BCE_LOCK(sc); 7652 bce_start_locked(ifp); 7653 BCE_UNLOCK(sc); 7654 7655 DBEXIT(BCE_VERBOSE_SEND); 7656} 7657 7658 7659/****************************************************************************/ 7660/* Handles any IOCTL calls from the operating system. */ 7661/* */ 7662/* Returns: */ 7663/* 0 for success, positive value for failure. */ 7664/****************************************************************************/ 7665static int 7666bce_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 7667{ 7668 struct bce_softc *sc = ifp->if_softc; 7669 struct ifreq *ifr = (struct ifreq *) data; 7670 struct mii_data *mii; 7671 int mask, error = 0; 7672 7673 DBENTER(BCE_VERBOSE_MISC); 7674 7675 switch(command) { 7676 7677 /* Set the interface MTU. */ 7678 case SIOCSIFMTU: 7679 /* Check that the MTU setting is supported. */ 7680 if ((ifr->ifr_mtu < BCE_MIN_MTU) || 7681 (ifr->ifr_mtu > BCE_MAX_JUMBO_MTU)) { 7682 error = EINVAL; 7683 break; 7684 } 7685 7686 DBPRINT(sc, BCE_INFO_MISC, 7687 "SIOCSIFMTU: Changing MTU from %d to %d\n", 7688 (int) ifp->if_mtu, (int) ifr->ifr_mtu); 7689 7690 BCE_LOCK(sc); 7691 ifp->if_mtu = ifr->ifr_mtu; 7692 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 7693 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 7694 bce_init_locked(sc); 7695 } 7696 BCE_UNLOCK(sc); 7697 break; 7698 7699 /* Set interface flags. */ 7700 case SIOCSIFFLAGS: 7701 DBPRINT(sc, BCE_VERBOSE_SPECIAL, "Received SIOCSIFFLAGS\n"); 7702 7703 BCE_LOCK(sc); 7704 7705 /* Check if the interface is up. */ 7706 if (ifp->if_flags & IFF_UP) { 7707 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 7708 /* Change promiscuous/multicast flags as necessary. */ 7709 bce_set_rx_mode(sc); 7710 } else { 7711 /* Start the HW */ 7712 bce_init_locked(sc); 7713 } 7714 } else { 7715 /* The interface is down, check if driver is running. */ 7716 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 7717 bce_stop(sc); 7718 7719 /* If MFW is running, restart the controller a bit. */ 7720 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 7721 bce_reset(sc, BCE_DRV_MSG_CODE_RESET); 7722 bce_chipinit(sc); 7723 bce_mgmt_init_locked(sc); 7724 } 7725 } 7726 } 7727 7728 BCE_UNLOCK(sc); 7729 break; 7730 7731 /* Add/Delete multicast address */ 7732 case SIOCADDMULTI: 7733 case SIOCDELMULTI: 7734 DBPRINT(sc, BCE_VERBOSE_MISC, 7735 "Received SIOCADDMULTI/SIOCDELMULTI\n"); 7736 7737 BCE_LOCK(sc); 7738 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 7739 bce_set_rx_mode(sc); 7740 BCE_UNLOCK(sc); 7741 7742 break; 7743 7744 /* Set/Get Interface media */ 7745 case SIOCSIFMEDIA: 7746 case SIOCGIFMEDIA: 7747 DBPRINT(sc, BCE_VERBOSE_MISC, 7748 "Received SIOCSIFMEDIA/SIOCGIFMEDIA\n"); 7749 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) 7750 error = ifmedia_ioctl(ifp, ifr, &sc->bce_ifmedia, 7751 command); 7752 else { 7753 mii = device_get_softc(sc->bce_miibus); 7754 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 7755 command); 7756 } 7757 break; 7758 7759 /* Set interface capability */ 7760 case SIOCSIFCAP: 7761 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 7762 DBPRINT(sc, BCE_INFO_MISC, 7763 "Received SIOCSIFCAP = 0x%08X\n", (u32) mask); 7764 7765 /* Toggle the TX checksum capabilities enable flag. */ 7766 if (mask & IFCAP_TXCSUM && 7767 ifp->if_capabilities & IFCAP_TXCSUM) { 7768 ifp->if_capenable ^= IFCAP_TXCSUM; 7769 if (IFCAP_TXCSUM & ifp->if_capenable) 7770 ifp->if_hwassist |= BCE_IF_HWASSIST; 7771 else 7772 ifp->if_hwassist &= ~BCE_IF_HWASSIST; 7773 } 7774 7775 /* Toggle the RX checksum capabilities enable flag. */ 7776 if (mask & IFCAP_RXCSUM && 7777 ifp->if_capabilities & IFCAP_RXCSUM) 7778 ifp->if_capenable ^= IFCAP_RXCSUM; 7779 7780 /* Toggle the TSO capabilities enable flag. */ 7781 if (bce_tso_enable && (mask & IFCAP_TSO4) && 7782 ifp->if_capabilities & IFCAP_TSO4) { 7783 ifp->if_capenable ^= IFCAP_TSO4; 7784 if (IFCAP_TSO4 & ifp->if_capenable) 7785 ifp->if_hwassist |= CSUM_TSO; 7786 else 7787 ifp->if_hwassist &= ~CSUM_TSO; 7788 } 7789 7790 if (mask & IFCAP_VLAN_HWCSUM && 7791 ifp->if_capabilities & IFCAP_VLAN_HWCSUM) 7792 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 7793 7794 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 7795 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 7796 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 7797 /* 7798 * Don't actually disable VLAN tag stripping as 7799 * management firmware (ASF/IPMI/UMP) requires the 7800 * feature. If VLAN tag stripping is disabled driver 7801 * will manually reconstruct the VLAN frame by 7802 * appending stripped VLAN tag. 7803 */ 7804 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 7805 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING)) { 7806 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 7807 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 7808 == 0) 7809 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 7810 } 7811 VLAN_CAPABILITIES(ifp); 7812 break; 7813 default: 7814 /* We don't know how to handle the IOCTL, pass it on. */ 7815 error = ether_ioctl(ifp, command, data); 7816 break; 7817 } 7818 7819 DBEXIT(BCE_VERBOSE_MISC); 7820 return(error); 7821} 7822 7823 7824/****************************************************************************/ 7825/* Transmit timeout handler. */ 7826/* */ 7827/* Returns: */ 7828/* Nothing. */ 7829/****************************************************************************/ 7830static void 7831bce_watchdog(struct bce_softc *sc) 7832{ 7833 uint32_t status; 7834 7835 DBENTER(BCE_EXTREME_SEND); 7836 7837 BCE_LOCK_ASSERT(sc); 7838 7839 status = 0; 7840 /* If the watchdog timer hasn't expired then just exit. */ 7841 if (sc->watchdog_timer == 0 || --sc->watchdog_timer) 7842 goto bce_watchdog_exit; 7843 7844 status = REG_RD(sc, BCE_EMAC_RX_STATUS); 7845 /* If pause frames are active then don't reset the hardware. */ 7846 if ((sc->bce_flags & BCE_USING_RX_FLOW_CONTROL) != 0) { 7847 if ((status & BCE_EMAC_RX_STATUS_FFED) != 0) { 7848 /* 7849 * If link partner has us in XOFF state then wait for 7850 * the condition to clear. 7851 */ 7852 sc->watchdog_timer = BCE_TX_TIMEOUT; 7853 goto bce_watchdog_exit; 7854 } else if ((status & BCE_EMAC_RX_STATUS_FF_RECEIVED) != 0 && 7855 (status & BCE_EMAC_RX_STATUS_N_RECEIVED) != 0) { 7856 /* 7857 * If we're not currently XOFF'ed but have recently 7858 * been XOFF'd/XON'd then assume that's delaying TX 7859 * this time around. 7860 */ 7861 sc->watchdog_timer = BCE_TX_TIMEOUT; 7862 goto bce_watchdog_exit; 7863 } 7864 /* 7865 * Any other condition is unexpected and the controller 7866 * should be reset. 7867 */ 7868 } 7869 7870 BCE_PRINTF("%s(%d): Watchdog timeout occurred, resetting!\n", 7871 __FILE__, __LINE__); 7872 7873 DBRUNMSG(BCE_INFO, 7874 bce_dump_driver_state(sc); 7875 bce_dump_status_block(sc); 7876 bce_dump_stats_block(sc); 7877 bce_dump_ftqs(sc); 7878 bce_dump_txp_state(sc, 0); 7879 bce_dump_rxp_state(sc, 0); 7880 bce_dump_tpat_state(sc, 0); 7881 bce_dump_cp_state(sc, 0); 7882 bce_dump_com_state(sc, 0)); 7883 7884 DBRUN(bce_breakpoint(sc)); 7885 7886 sc->bce_ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 7887 7888 bce_init_locked(sc); 7889 sc->bce_ifp->if_oerrors++; 7890 7891bce_watchdog_exit: 7892 REG_WR(sc, BCE_EMAC_RX_STATUS, status); 7893 DBEXIT(BCE_EXTREME_SEND); 7894} 7895 7896 7897/* 7898 * Interrupt handler. 7899 */ 7900/****************************************************************************/ 7901/* Main interrupt entry point. Verifies that the controller generated the */ 7902/* interrupt and then calls a separate routine for handle the various */ 7903/* interrupt causes (PHY, TX, RX). */ 7904/* */ 7905/* Returns: */ 7906/* Nothing. */ 7907/****************************************************************************/ 7908static void 7909bce_intr(void *xsc) 7910{ 7911 struct bce_softc *sc; 7912 struct ifnet *ifp; 7913 u32 status_attn_bits; 7914 u16 hw_rx_cons, hw_tx_cons; 7915 7916 sc = xsc; 7917 ifp = sc->bce_ifp; 7918 7919 DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 7920 DBRUNMSG(BCE_VERBOSE_INTR, bce_dump_status_block(sc)); 7921 DBRUNMSG(BCE_VERBOSE_INTR, bce_dump_stats_block(sc)); 7922 7923 BCE_LOCK(sc); 7924 7925 DBRUN(sc->interrupts_generated++); 7926 7927 /* Synchnorize before we read from interface's status block */ 7928 bus_dmamap_sync(sc->status_tag, sc->status_map, BUS_DMASYNC_POSTREAD); 7929 7930 /* 7931 * If the hardware status block index matches the last value read 7932 * by the driver and we haven't asserted our interrupt then there's 7933 * nothing to do. This may only happen in case of INTx due to the 7934 * interrupt arriving at the CPU before the status block is updated. 7935 */ 7936 if ((sc->bce_flags & (BCE_USING_MSI_FLAG | BCE_USING_MSIX_FLAG)) == 0 && 7937 sc->status_block->status_idx == sc->last_status_idx && 7938 (REG_RD(sc, BCE_PCICFG_MISC_STATUS) & 7939 BCE_PCICFG_MISC_STATUS_INTA_VALUE)) { 7940 DBPRINT(sc, BCE_VERBOSE_INTR, "%s(): Spurious interrupt.\n", 7941 __FUNCTION__); 7942 goto bce_intr_exit; 7943 } 7944 7945 /* Ack the interrupt and stop others from occuring. */ 7946 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 7947 BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM | 7948 BCE_PCICFG_INT_ACK_CMD_MASK_INT); 7949 7950 /* Check if the hardware has finished any work. */ 7951 hw_rx_cons = bce_get_hw_rx_cons(sc); 7952 hw_tx_cons = bce_get_hw_tx_cons(sc); 7953 7954 /* Keep processing data as long as there is work to do. */ 7955 for (;;) { 7956 7957 status_attn_bits = sc->status_block->status_attn_bits; 7958 7959 DBRUNIF(DB_RANDOMTRUE(unexpected_attention_sim_control), 7960 BCE_PRINTF("Simulating unexpected status attention " 7961 "bit set."); 7962 sc->unexpected_attention_sim_count++; 7963 status_attn_bits = status_attn_bits | 7964 STATUS_ATTN_BITS_PARITY_ERROR); 7965 7966 /* Was it a link change interrupt? */ 7967 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != 7968 (sc->status_block->status_attn_bits_ack & 7969 STATUS_ATTN_BITS_LINK_STATE)) { 7970 bce_phy_intr(sc); 7971 7972 /* Clear transient updates during link state change. */ 7973 REG_WR(sc, BCE_HC_COMMAND, sc->hc_command | 7974 BCE_HC_COMMAND_COAL_NOW_WO_INT); 7975 REG_RD(sc, BCE_HC_COMMAND); 7976 } 7977 7978 /* If any other attention is asserted, the chip is toast. */ 7979 if (((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) != 7980 (sc->status_block->status_attn_bits_ack & 7981 ~STATUS_ATTN_BITS_LINK_STATE))) { 7982 7983 sc->unexpected_attention_count++; 7984 7985 BCE_PRINTF("%s(%d): Fatal attention detected: " 7986 "0x%08X\n", __FILE__, __LINE__, 7987 sc->status_block->status_attn_bits); 7988 7989 DBRUNMSG(BCE_FATAL, 7990 if (unexpected_attention_sim_control == 0) 7991 bce_breakpoint(sc)); 7992 7993 bce_init_locked(sc); 7994 goto bce_intr_exit; 7995 } 7996 7997 /* Check for any completed RX frames. */ 7998 if (hw_rx_cons != sc->hw_rx_cons) 7999 bce_rx_intr(sc); 8000 8001 /* Check for any completed TX frames. */ 8002 if (hw_tx_cons != sc->hw_tx_cons) 8003 bce_tx_intr(sc); 8004 8005 /* Save status block index value for the next interrupt. */ 8006 sc->last_status_idx = sc->status_block->status_idx; 8007 8008 /* 8009 * Prevent speculative reads from getting 8010 * ahead of the status block. 8011 */ 8012 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 8013 BUS_SPACE_BARRIER_READ); 8014 8015 /* 8016 * If there's no work left then exit the 8017 * interrupt service routine. 8018 */ 8019 hw_rx_cons = bce_get_hw_rx_cons(sc); 8020 hw_tx_cons = bce_get_hw_tx_cons(sc); 8021 8022 if ((hw_rx_cons == sc->hw_rx_cons) && 8023 (hw_tx_cons == sc->hw_tx_cons)) 8024 break; 8025 } 8026 8027 bus_dmamap_sync(sc->status_tag, sc->status_map, BUS_DMASYNC_PREREAD); 8028 8029 /* Re-enable interrupts. */ 8030 bce_enable_intr(sc, 0); 8031 8032 /* Handle any frames that arrived while handling the interrupt. */ 8033 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 8034 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 8035 bce_start_locked(ifp); 8036 8037bce_intr_exit: 8038 BCE_UNLOCK(sc); 8039 8040 DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 8041} 8042 8043 8044/****************************************************************************/ 8045/* Programs the various packet receive modes (broadcast and multicast). */ 8046/* */ 8047/* Returns: */ 8048/* Nothing. */ 8049/****************************************************************************/ 8050static void 8051bce_set_rx_mode(struct bce_softc *sc) 8052{ 8053 struct ifnet *ifp; 8054 struct ifmultiaddr *ifma; 8055 u32 hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 8056 u32 rx_mode, sort_mode; 8057 int h, i; 8058 8059 DBENTER(BCE_VERBOSE_MISC); 8060 8061 BCE_LOCK_ASSERT(sc); 8062 8063 ifp = sc->bce_ifp; 8064 8065 /* Initialize receive mode default settings. */ 8066 rx_mode = sc->rx_mode & ~(BCE_EMAC_RX_MODE_PROMISCUOUS | 8067 BCE_EMAC_RX_MODE_KEEP_VLAN_TAG); 8068 sort_mode = 1 | BCE_RPM_SORT_USER0_BC_EN; 8069 8070 /* 8071 * ASF/IPMI/UMP firmware requires that VLAN tag stripping 8072 * be enbled. 8073 */ 8074 if (!(BCE_IF_CAPABILITIES & IFCAP_VLAN_HWTAGGING) && 8075 (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG))) 8076 rx_mode |= BCE_EMAC_RX_MODE_KEEP_VLAN_TAG; 8077 8078 /* 8079 * Check for promiscuous, all multicast, or selected 8080 * multicast address filtering. 8081 */ 8082 if (ifp->if_flags & IFF_PROMISC) { 8083 DBPRINT(sc, BCE_INFO_MISC, "Enabling promiscuous mode.\n"); 8084 8085 /* Enable promiscuous mode. */ 8086 rx_mode |= BCE_EMAC_RX_MODE_PROMISCUOUS; 8087 sort_mode |= BCE_RPM_SORT_USER0_PROM_EN; 8088 } else if (ifp->if_flags & IFF_ALLMULTI) { 8089 DBPRINT(sc, BCE_INFO_MISC, "Enabling all multicast mode.\n"); 8090 8091 /* Enable all multicast addresses. */ 8092 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) { 8093 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), 8094 0xffffffff); 8095 } 8096 sort_mode |= BCE_RPM_SORT_USER0_MC_EN; 8097 } else { 8098 /* Accept one or more multicast(s). */ 8099 DBPRINT(sc, BCE_INFO_MISC, "Enabling selective multicast mode.\n"); 8100 8101 if_maddr_rlock(ifp); 8102 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 8103 if (ifma->ifma_addr->sa_family != AF_LINK) 8104 continue; 8105 h = ether_crc32_le(LLADDR((struct sockaddr_dl *) 8106 ifma->ifma_addr), ETHER_ADDR_LEN) & 0xFF; 8107 hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F); 8108 } 8109 if_maddr_runlock(ifp); 8110 8111 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) 8112 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), hashes[i]); 8113 8114 sort_mode |= BCE_RPM_SORT_USER0_MC_HSH_EN; 8115 } 8116 8117 /* Only make changes if the recive mode has actually changed. */ 8118 if (rx_mode != sc->rx_mode) { 8119 DBPRINT(sc, BCE_VERBOSE_MISC, "Enabling new receive mode: " 8120 "0x%08X\n", rx_mode); 8121 8122 sc->rx_mode = rx_mode; 8123 REG_WR(sc, BCE_EMAC_RX_MODE, rx_mode); 8124 } 8125 8126 /* Disable and clear the exisitng sort before enabling a new sort. */ 8127 REG_WR(sc, BCE_RPM_SORT_USER0, 0x0); 8128 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode); 8129 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode | BCE_RPM_SORT_USER0_ENA); 8130 8131 DBEXIT(BCE_VERBOSE_MISC); 8132} 8133 8134 8135/****************************************************************************/ 8136/* Called periodically to updates statistics from the controllers */ 8137/* statistics block. */ 8138/* */ 8139/* Returns: */ 8140/* Nothing. */ 8141/****************************************************************************/ 8142static void 8143bce_stats_update(struct bce_softc *sc) 8144{ 8145 struct ifnet *ifp; 8146 struct statistics_block *stats; 8147 8148 DBENTER(BCE_EXTREME_MISC); 8149 8150 ifp = sc->bce_ifp; 8151 8152 bus_dmamap_sync(sc->stats_tag, sc->stats_map, BUS_DMASYNC_POSTREAD); 8153 8154 stats = (struct statistics_block *) sc->stats_block; 8155 8156 /* 8157 * Certain controllers don't report 8158 * carrier sense errors correctly. 8159 * See errata E11_5708CA0_1165. 8160 */ 8161 if (!(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) && 8162 !(BCE_CHIP_ID(sc) == BCE_CHIP_ID_5708_A0)) 8163 ifp->if_oerrors += 8164 (u_long) stats->stat_Dot3StatsCarrierSenseErrors; 8165 8166 /* 8167 * Update the sysctl statistics from the 8168 * hardware statistics. 8169 */ 8170 sc->stat_IfHCInOctets = 8171 ((u64) stats->stat_IfHCInOctets_hi << 32) + 8172 (u64) stats->stat_IfHCInOctets_lo; 8173 8174 sc->stat_IfHCInBadOctets = 8175 ((u64) stats->stat_IfHCInBadOctets_hi << 32) + 8176 (u64) stats->stat_IfHCInBadOctets_lo; 8177 8178 sc->stat_IfHCOutOctets = 8179 ((u64) stats->stat_IfHCOutOctets_hi << 32) + 8180 (u64) stats->stat_IfHCOutOctets_lo; 8181 8182 sc->stat_IfHCOutBadOctets = 8183 ((u64) stats->stat_IfHCOutBadOctets_hi << 32) + 8184 (u64) stats->stat_IfHCOutBadOctets_lo; 8185 8186 sc->stat_IfHCInUcastPkts = 8187 ((u64) stats->stat_IfHCInUcastPkts_hi << 32) + 8188 (u64) stats->stat_IfHCInUcastPkts_lo; 8189 8190 sc->stat_IfHCInMulticastPkts = 8191 ((u64) stats->stat_IfHCInMulticastPkts_hi << 32) + 8192 (u64) stats->stat_IfHCInMulticastPkts_lo; 8193 8194 sc->stat_IfHCInBroadcastPkts = 8195 ((u64) stats->stat_IfHCInBroadcastPkts_hi << 32) + 8196 (u64) stats->stat_IfHCInBroadcastPkts_lo; 8197 8198 sc->stat_IfHCOutUcastPkts = 8199 ((u64) stats->stat_IfHCOutUcastPkts_hi << 32) + 8200 (u64) stats->stat_IfHCOutUcastPkts_lo; 8201 8202 sc->stat_IfHCOutMulticastPkts = 8203 ((u64) stats->stat_IfHCOutMulticastPkts_hi << 32) + 8204 (u64) stats->stat_IfHCOutMulticastPkts_lo; 8205 8206 sc->stat_IfHCOutBroadcastPkts = 8207 ((u64) stats->stat_IfHCOutBroadcastPkts_hi << 32) + 8208 (u64) stats->stat_IfHCOutBroadcastPkts_lo; 8209 8210 /* ToDo: Preserve counters beyond 32 bits? */ 8211 /* ToDo: Read the statistics from auto-clear regs? */ 8212 8213 sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors = 8214 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors; 8215 8216 sc->stat_Dot3StatsCarrierSenseErrors = 8217 stats->stat_Dot3StatsCarrierSenseErrors; 8218 8219 sc->stat_Dot3StatsFCSErrors = 8220 stats->stat_Dot3StatsFCSErrors; 8221 8222 sc->stat_Dot3StatsAlignmentErrors = 8223 stats->stat_Dot3StatsAlignmentErrors; 8224 8225 sc->stat_Dot3StatsSingleCollisionFrames = 8226 stats->stat_Dot3StatsSingleCollisionFrames; 8227 8228 sc->stat_Dot3StatsMultipleCollisionFrames = 8229 stats->stat_Dot3StatsMultipleCollisionFrames; 8230 8231 sc->stat_Dot3StatsDeferredTransmissions = 8232 stats->stat_Dot3StatsDeferredTransmissions; 8233 8234 sc->stat_Dot3StatsExcessiveCollisions = 8235 stats->stat_Dot3StatsExcessiveCollisions; 8236 8237 sc->stat_Dot3StatsLateCollisions = 8238 stats->stat_Dot3StatsLateCollisions; 8239 8240 sc->stat_EtherStatsCollisions = 8241 stats->stat_EtherStatsCollisions; 8242 8243 sc->stat_EtherStatsFragments = 8244 stats->stat_EtherStatsFragments; 8245 8246 sc->stat_EtherStatsJabbers = 8247 stats->stat_EtherStatsJabbers; 8248 8249 sc->stat_EtherStatsUndersizePkts = 8250 stats->stat_EtherStatsUndersizePkts; 8251 8252 sc->stat_EtherStatsOversizePkts = 8253 stats->stat_EtherStatsOversizePkts; 8254 8255 sc->stat_EtherStatsPktsRx64Octets = 8256 stats->stat_EtherStatsPktsRx64Octets; 8257 8258 sc->stat_EtherStatsPktsRx65Octetsto127Octets = 8259 stats->stat_EtherStatsPktsRx65Octetsto127Octets; 8260 8261 sc->stat_EtherStatsPktsRx128Octetsto255Octets = 8262 stats->stat_EtherStatsPktsRx128Octetsto255Octets; 8263 8264 sc->stat_EtherStatsPktsRx256Octetsto511Octets = 8265 stats->stat_EtherStatsPktsRx256Octetsto511Octets; 8266 8267 sc->stat_EtherStatsPktsRx512Octetsto1023Octets = 8268 stats->stat_EtherStatsPktsRx512Octetsto1023Octets; 8269 8270 sc->stat_EtherStatsPktsRx1024Octetsto1522Octets = 8271 stats->stat_EtherStatsPktsRx1024Octetsto1522Octets; 8272 8273 sc->stat_EtherStatsPktsRx1523Octetsto9022Octets = 8274 stats->stat_EtherStatsPktsRx1523Octetsto9022Octets; 8275 8276 sc->stat_EtherStatsPktsTx64Octets = 8277 stats->stat_EtherStatsPktsTx64Octets; 8278 8279 sc->stat_EtherStatsPktsTx65Octetsto127Octets = 8280 stats->stat_EtherStatsPktsTx65Octetsto127Octets; 8281 8282 sc->stat_EtherStatsPktsTx128Octetsto255Octets = 8283 stats->stat_EtherStatsPktsTx128Octetsto255Octets; 8284 8285 sc->stat_EtherStatsPktsTx256Octetsto511Octets = 8286 stats->stat_EtherStatsPktsTx256Octetsto511Octets; 8287 8288 sc->stat_EtherStatsPktsTx512Octetsto1023Octets = 8289 stats->stat_EtherStatsPktsTx512Octetsto1023Octets; 8290 8291 sc->stat_EtherStatsPktsTx1024Octetsto1522Octets = 8292 stats->stat_EtherStatsPktsTx1024Octetsto1522Octets; 8293 8294 sc->stat_EtherStatsPktsTx1523Octetsto9022Octets = 8295 stats->stat_EtherStatsPktsTx1523Octetsto9022Octets; 8296 8297 sc->stat_XonPauseFramesReceived = 8298 stats->stat_XonPauseFramesReceived; 8299 8300 sc->stat_XoffPauseFramesReceived = 8301 stats->stat_XoffPauseFramesReceived; 8302 8303 sc->stat_OutXonSent = 8304 stats->stat_OutXonSent; 8305 8306 sc->stat_OutXoffSent = 8307 stats->stat_OutXoffSent; 8308 8309 sc->stat_FlowControlDone = 8310 stats->stat_FlowControlDone; 8311 8312 sc->stat_MacControlFramesReceived = 8313 stats->stat_MacControlFramesReceived; 8314 8315 sc->stat_XoffStateEntered = 8316 stats->stat_XoffStateEntered; 8317 8318 sc->stat_IfInFramesL2FilterDiscards = 8319 stats->stat_IfInFramesL2FilterDiscards; 8320 8321 sc->stat_IfInRuleCheckerDiscards = 8322 stats->stat_IfInRuleCheckerDiscards; 8323 8324 sc->stat_IfInFTQDiscards = 8325 stats->stat_IfInFTQDiscards; 8326 8327 sc->stat_IfInMBUFDiscards = 8328 stats->stat_IfInMBUFDiscards; 8329 8330 sc->stat_IfInRuleCheckerP4Hit = 8331 stats->stat_IfInRuleCheckerP4Hit; 8332 8333 sc->stat_CatchupInRuleCheckerDiscards = 8334 stats->stat_CatchupInRuleCheckerDiscards; 8335 8336 sc->stat_CatchupInFTQDiscards = 8337 stats->stat_CatchupInFTQDiscards; 8338 8339 sc->stat_CatchupInMBUFDiscards = 8340 stats->stat_CatchupInMBUFDiscards; 8341 8342 sc->stat_CatchupInRuleCheckerP4Hit = 8343 stats->stat_CatchupInRuleCheckerP4Hit; 8344 8345 sc->com_no_buffers = REG_RD_IND(sc, 0x120084); 8346 8347 /* 8348 * Update the interface statistics from the 8349 * hardware statistics. 8350 */ 8351 ifp->if_collisions = 8352 (u_long) sc->stat_EtherStatsCollisions; 8353 8354 /* ToDo: This method loses soft errors. */ 8355 ifp->if_ierrors = 8356 (u_long) sc->stat_EtherStatsUndersizePkts + 8357 (u_long) sc->stat_EtherStatsOversizePkts + 8358 (u_long) sc->stat_IfInMBUFDiscards + 8359 (u_long) sc->stat_Dot3StatsAlignmentErrors + 8360 (u_long) sc->stat_Dot3StatsFCSErrors + 8361 (u_long) sc->stat_IfInRuleCheckerDiscards + 8362 (u_long) sc->stat_IfInFTQDiscards + 8363 (u_long) sc->com_no_buffers; 8364 8365 /* ToDo: This method loses soft errors. */ 8366 ifp->if_oerrors = 8367 (u_long) sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors + 8368 (u_long) sc->stat_Dot3StatsExcessiveCollisions + 8369 (u_long) sc->stat_Dot3StatsLateCollisions; 8370 8371 /* ToDo: Add additional statistics? */ 8372 8373 DBEXIT(BCE_EXTREME_MISC); 8374} 8375 8376 8377/****************************************************************************/ 8378/* Periodic function to notify the bootcode that the driver is still */ 8379/* present. */ 8380/* */ 8381/* Returns: */ 8382/* Nothing. */ 8383/****************************************************************************/ 8384static void 8385bce_pulse(void *xsc) 8386{ 8387 struct bce_softc *sc = xsc; 8388 u32 msg; 8389 8390 DBENTER(BCE_EXTREME_MISC); 8391 8392 BCE_LOCK_ASSERT(sc); 8393 8394 /* Tell the firmware that the driver is still running. */ 8395 msg = (u32) ++sc->bce_fw_drv_pulse_wr_seq; 8396 bce_shmem_wr(sc, BCE_DRV_PULSE_MB, msg); 8397 8398 /* Update the bootcode condition. */ 8399 sc->bc_state = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); 8400 8401 /* Report whether the bootcode still knows the driver is running. */ 8402 if (bce_verbose || bootverbose) { 8403 if (sc->bce_drv_cardiac_arrest == FALSE) { 8404 if (!(sc->bc_state & BCE_CONDITION_DRV_PRESENT)) { 8405 sc->bce_drv_cardiac_arrest = TRUE; 8406 BCE_PRINTF("%s(): Warning: bootcode " 8407 "thinks driver is absent! " 8408 "(bc_state = 0x%08X)\n", 8409 __FUNCTION__, sc->bc_state); 8410 } 8411 } else { 8412 /* 8413 * Not supported by all bootcode versions. 8414 * (v5.0.11+ and v5.2.1+) Older bootcode 8415 * will require the driver to reset the 8416 * controller to clear this condition. 8417 */ 8418 if (sc->bc_state & BCE_CONDITION_DRV_PRESENT) { 8419 sc->bce_drv_cardiac_arrest = FALSE; 8420 BCE_PRINTF("%s(): Bootcode found the " 8421 "driver pulse! (bc_state = 0x%08X)\n", 8422 __FUNCTION__, sc->bc_state); 8423 } 8424 } 8425 } 8426 8427 8428 /* Schedule the next pulse. */ 8429 callout_reset(&sc->bce_pulse_callout, hz, bce_pulse, sc); 8430 8431 DBEXIT(BCE_EXTREME_MISC); 8432} 8433 8434 8435/****************************************************************************/ 8436/* Periodic function to perform maintenance tasks. */ 8437/* */ 8438/* Returns: */ 8439/* Nothing. */ 8440/****************************************************************************/ 8441static void 8442bce_tick(void *xsc) 8443{ 8444 struct bce_softc *sc = xsc; 8445 struct mii_data *mii; 8446 struct ifnet *ifp; 8447 struct ifmediareq ifmr; 8448 8449 ifp = sc->bce_ifp; 8450 8451 DBENTER(BCE_EXTREME_MISC); 8452 8453 BCE_LOCK_ASSERT(sc); 8454 8455 /* Schedule the next tick. */ 8456 callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc); 8457 8458 /* Update the statistics from the hardware statistics block. */ 8459 bce_stats_update(sc); 8460 8461 /* Ensure page and RX chains get refilled in low-memory situations. */ 8462 if (bce_hdr_split == TRUE) 8463 bce_fill_pg_chain(sc); 8464 bce_fill_rx_chain(sc); 8465 8466 /* Check that chip hasn't hung. */ 8467 bce_watchdog(sc); 8468 8469 /* If link is up already up then we're done. */ 8470 if (sc->bce_link_up == TRUE) 8471 goto bce_tick_exit; 8472 8473 /* Link is down. Check what the PHY's doing. */ 8474 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) { 8475 bzero(&ifmr, sizeof(ifmr)); 8476 bce_ifmedia_sts_rphy(sc, &ifmr); 8477 if ((ifmr.ifm_status & (IFM_ACTIVE | IFM_AVALID)) == 8478 (IFM_ACTIVE | IFM_AVALID)) { 8479 sc->bce_link_up = TRUE; 8480 bce_miibus_statchg(sc->bce_dev); 8481 } 8482 } else { 8483 mii = device_get_softc(sc->bce_miibus); 8484 mii_tick(mii); 8485 /* Check if the link has come up. */ 8486 if ((mii->mii_media_status & IFM_ACTIVE) && 8487 (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)) { 8488 DBPRINT(sc, BCE_VERBOSE_MISC, "%s(): Link up!\n", 8489 __FUNCTION__); 8490 sc->bce_link_up = TRUE; 8491 if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 8492 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX || 8493 IFM_SUBTYPE(mii->mii_media_active) == IFM_2500_SX) && 8494 (bce_verbose || bootverbose)) 8495 BCE_PRINTF("Gigabit link up!\n"); 8496 } 8497 8498 } 8499 if (sc->bce_link_up == TRUE) { 8500 /* Now that link is up, handle any outstanding TX traffic. */ 8501 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 8502 DBPRINT(sc, BCE_VERBOSE_MISC, "%s(): Found " 8503 "pending TX traffic.\n", __FUNCTION__); 8504 bce_start_locked(ifp); 8505 } 8506 } 8507 8508bce_tick_exit: 8509 DBEXIT(BCE_EXTREME_MISC); 8510} 8511 8512static void 8513bce_fw_cap_init(struct bce_softc *sc) 8514{ 8515 u32 ack, cap, link; 8516 8517 ack = 0; 8518 cap = bce_shmem_rd(sc, BCE_FW_CAP_MB); 8519 if ((cap & BCE_FW_CAP_SIGNATURE_MAGIC_MASK) != 8520 BCE_FW_CAP_SIGNATURE_MAGIC) 8521 return; 8522 if ((cap & (BCE_FW_CAP_MFW_KEEP_VLAN | BCE_FW_CAP_BC_KEEP_VLAN)) == 8523 (BCE_FW_CAP_MFW_KEEP_VLAN | BCE_FW_CAP_BC_KEEP_VLAN)) 8524 ack |= BCE_DRV_ACK_CAP_SIGNATURE_MAGIC | 8525 BCE_FW_CAP_MFW_KEEP_VLAN | BCE_FW_CAP_BC_KEEP_VLAN; 8526 if ((sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) != 0 && 8527 (cap & BCE_FW_CAP_REMOTE_PHY_CAP) != 0) { 8528 sc->bce_phy_flags &= ~BCE_PHY_REMOTE_PORT_FIBER_FLAG; 8529 sc->bce_phy_flags |= BCE_PHY_REMOTE_CAP_FLAG; 8530 link = bce_shmem_rd(sc, BCE_LINK_STATUS); 8531 if ((link & BCE_LINK_STATUS_SERDES_LINK) != 0) 8532 sc->bce_phy_flags |= BCE_PHY_REMOTE_PORT_FIBER_FLAG; 8533 ack |= BCE_DRV_ACK_CAP_SIGNATURE_MAGIC | 8534 BCE_FW_CAP_REMOTE_PHY_CAP; 8535 } 8536 8537 if (ack != 0) 8538 bce_shmem_wr(sc, BCE_DRV_ACK_CAP_MB, ack); 8539} 8540 8541 8542#ifdef BCE_DEBUG 8543/****************************************************************************/ 8544/* Allows the driver state to be dumped through the sysctl interface. */ 8545/* */ 8546/* Returns: */ 8547/* 0 for success, positive value for failure. */ 8548/****************************************************************************/ 8549static int 8550bce_sysctl_driver_state(SYSCTL_HANDLER_ARGS) 8551{ 8552 int error; 8553 int result; 8554 struct bce_softc *sc; 8555 8556 result = -1; 8557 error = sysctl_handle_int(oidp, &result, 0, req); 8558 8559 if (error || !req->newptr) 8560 return (error); 8561 8562 if (result == 1) { 8563 sc = (struct bce_softc *)arg1; 8564 bce_dump_driver_state(sc); 8565 } 8566 8567 return error; 8568} 8569 8570 8571/****************************************************************************/ 8572/* Allows the hardware state to be dumped through the sysctl interface. */ 8573/* */ 8574/* Returns: */ 8575/* 0 for success, positive value for failure. */ 8576/****************************************************************************/ 8577static int 8578bce_sysctl_hw_state(SYSCTL_HANDLER_ARGS) 8579{ 8580 int error; 8581 int result; 8582 struct bce_softc *sc; 8583 8584 result = -1; 8585 error = sysctl_handle_int(oidp, &result, 0, req); 8586 8587 if (error || !req->newptr) 8588 return (error); 8589 8590 if (result == 1) { 8591 sc = (struct bce_softc *)arg1; 8592 bce_dump_hw_state(sc); 8593 } 8594 8595 return error; 8596} 8597 8598 8599/****************************************************************************/ 8600/* Allows the status block to be dumped through the sysctl interface. */ 8601/* */ 8602/* Returns: */ 8603/* 0 for success, positive value for failure. */ 8604/****************************************************************************/ 8605static int 8606bce_sysctl_status_block(SYSCTL_HANDLER_ARGS) 8607{ 8608 int error; 8609 int result; 8610 struct bce_softc *sc; 8611 8612 result = -1; 8613 error = sysctl_handle_int(oidp, &result, 0, req); 8614 8615 if (error || !req->newptr) 8616 return (error); 8617 8618 if (result == 1) { 8619 sc = (struct bce_softc *)arg1; 8620 bce_dump_status_block(sc); 8621 } 8622 8623 return error; 8624} 8625 8626 8627/****************************************************************************/ 8628/* Allows the stats block to be dumped through the sysctl interface. */ 8629/* */ 8630/* Returns: */ 8631/* 0 for success, positive value for failure. */ 8632/****************************************************************************/ 8633static int 8634bce_sysctl_stats_block(SYSCTL_HANDLER_ARGS) 8635{ 8636 int error; 8637 int result; 8638 struct bce_softc *sc; 8639 8640 result = -1; 8641 error = sysctl_handle_int(oidp, &result, 0, req); 8642 8643 if (error || !req->newptr) 8644 return (error); 8645 8646 if (result == 1) { 8647 sc = (struct bce_softc *)arg1; 8648 bce_dump_stats_block(sc); 8649 } 8650 8651 return error; 8652} 8653 8654 8655/****************************************************************************/ 8656/* Allows the stat counters to be cleared without unloading/reloading the */ 8657/* driver. */ 8658/* */ 8659/* Returns: */ 8660/* 0 for success, positive value for failure. */ 8661/****************************************************************************/ 8662static int 8663bce_sysctl_stats_clear(SYSCTL_HANDLER_ARGS) 8664{ 8665 int error; 8666 int result; 8667 struct bce_softc *sc; 8668 8669 result = -1; 8670 error = sysctl_handle_int(oidp, &result, 0, req); 8671 8672 if (error || !req->newptr) 8673 return (error); 8674 8675 if (result == 1) { 8676 sc = (struct bce_softc *)arg1; 8677 struct statistics_block *stats; 8678 8679 stats = (struct statistics_block *) sc->stats_block; 8680 bzero(stats, sizeof(struct statistics_block)); 8681 bus_dmamap_sync(sc->stats_tag, sc->stats_map, 8682 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 8683 8684 /* Clear the internal H/W statistics counters. */ 8685 REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW); 8686 8687 /* Reset the driver maintained statistics. */ 8688 sc->interrupts_rx = 8689 sc->interrupts_tx = 0; 8690 sc->tso_frames_requested = 8691 sc->tso_frames_completed = 8692 sc->tso_frames_failed = 0; 8693 sc->rx_empty_count = 8694 sc->tx_full_count = 0; 8695 sc->rx_low_watermark = USABLE_RX_BD_ALLOC; 8696 sc->tx_hi_watermark = 0; 8697 sc->l2fhdr_error_count = 8698 sc->l2fhdr_error_sim_count = 0; 8699 sc->mbuf_alloc_failed_count = 8700 sc->mbuf_alloc_failed_sim_count = 0; 8701 sc->dma_map_addr_rx_failed_count = 8702 sc->dma_map_addr_tx_failed_count = 0; 8703 sc->mbuf_frag_count = 0; 8704 sc->csum_offload_tcp_udp = 8705 sc->csum_offload_ip = 0; 8706 sc->vlan_tagged_frames_rcvd = 8707 sc->vlan_tagged_frames_stripped = 0; 8708 sc->split_header_frames_rcvd = 8709 sc->split_header_tcp_frames_rcvd = 0; 8710 8711 /* Clear firmware maintained statistics. */ 8712 REG_WR_IND(sc, 0x120084, 0); 8713 } 8714 8715 return error; 8716} 8717 8718 8719/****************************************************************************/ 8720/* Allows the shared memory contents to be dumped through the sysctl . */ 8721/* interface. */ 8722/* */ 8723/* Returns: */ 8724/* 0 for success, positive value for failure. */ 8725/****************************************************************************/ 8726static int 8727bce_sysctl_shmem_state(SYSCTL_HANDLER_ARGS) 8728{ 8729 int error; 8730 int result; 8731 struct bce_softc *sc; 8732 8733 result = -1; 8734 error = sysctl_handle_int(oidp, &result, 0, req); 8735 8736 if (error || !req->newptr) 8737 return (error); 8738 8739 if (result == 1) { 8740 sc = (struct bce_softc *)arg1; 8741 bce_dump_shmem_state(sc); 8742 } 8743 8744 return error; 8745} 8746 8747 8748/****************************************************************************/ 8749/* Allows the bootcode state to be dumped through the sysctl interface. */ 8750/* */ 8751/* Returns: */ 8752/* 0 for success, positive value for failure. */ 8753/****************************************************************************/ 8754static int 8755bce_sysctl_bc_state(SYSCTL_HANDLER_ARGS) 8756{ 8757 int error; 8758 int result; 8759 struct bce_softc *sc; 8760 8761 result = -1; 8762 error = sysctl_handle_int(oidp, &result, 0, req); 8763 8764 if (error || !req->newptr) 8765 return (error); 8766 8767 if (result == 1) { 8768 sc = (struct bce_softc *)arg1; 8769 bce_dump_bc_state(sc); 8770 } 8771 8772 return error; 8773} 8774 8775 8776/****************************************************************************/ 8777/* Provides a sysctl interface to allow dumping the RX BD chain. */ 8778/* */ 8779/* Returns: */ 8780/* 0 for success, positive value for failure. */ 8781/****************************************************************************/ 8782static int 8783bce_sysctl_dump_rx_bd_chain(SYSCTL_HANDLER_ARGS) 8784{ 8785 int error; 8786 int result; 8787 struct bce_softc *sc; 8788 8789 result = -1; 8790 error = sysctl_handle_int(oidp, &result, 0, req); 8791 8792 if (error || !req->newptr) 8793 return (error); 8794 8795 if (result == 1) { 8796 sc = (struct bce_softc *)arg1; 8797 bce_dump_rx_bd_chain(sc, 0, TOTAL_RX_BD_ALLOC); 8798 } 8799 8800 return error; 8801} 8802 8803 8804/****************************************************************************/ 8805/* Provides a sysctl interface to allow dumping the RX MBUF chain. */ 8806/* */ 8807/* Returns: */ 8808/* 0 for success, positive value for failure. */ 8809/****************************************************************************/ 8810static int 8811bce_sysctl_dump_rx_mbuf_chain(SYSCTL_HANDLER_ARGS) 8812{ 8813 int error; 8814 int result; 8815 struct bce_softc *sc; 8816 8817 result = -1; 8818 error = sysctl_handle_int(oidp, &result, 0, req); 8819 8820 if (error || !req->newptr) 8821 return (error); 8822 8823 if (result == 1) { 8824 sc = (struct bce_softc *)arg1; 8825 bce_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD_ALLOC); 8826 } 8827 8828 return error; 8829} 8830 8831 8832/****************************************************************************/ 8833/* Provides a sysctl interface to allow dumping the TX chain. */ 8834/* */ 8835/* Returns: */ 8836/* 0 for success, positive value for failure. */ 8837/****************************************************************************/ 8838static int 8839bce_sysctl_dump_tx_chain(SYSCTL_HANDLER_ARGS) 8840{ 8841 int error; 8842 int result; 8843 struct bce_softc *sc; 8844 8845 result = -1; 8846 error = sysctl_handle_int(oidp, &result, 0, req); 8847 8848 if (error || !req->newptr) 8849 return (error); 8850 8851 if (result == 1) { 8852 sc = (struct bce_softc *)arg1; 8853 bce_dump_tx_chain(sc, 0, TOTAL_TX_BD_ALLOC); 8854 } 8855 8856 return error; 8857} 8858 8859 8860/****************************************************************************/ 8861/* Provides a sysctl interface to allow dumping the page chain. */ 8862/* */ 8863/* Returns: */ 8864/* 0 for success, positive value for failure. */ 8865/****************************************************************************/ 8866static int 8867bce_sysctl_dump_pg_chain(SYSCTL_HANDLER_ARGS) 8868{ 8869 int error; 8870 int result; 8871 struct bce_softc *sc; 8872 8873 result = -1; 8874 error = sysctl_handle_int(oidp, &result, 0, req); 8875 8876 if (error || !req->newptr) 8877 return (error); 8878 8879 if (result == 1) { 8880 sc = (struct bce_softc *)arg1; 8881 bce_dump_pg_chain(sc, 0, TOTAL_PG_BD_ALLOC); 8882 } 8883 8884 return error; 8885} 8886 8887/****************************************************************************/ 8888/* Provides a sysctl interface to allow reading arbitrary NVRAM offsets in */ 8889/* the device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8890/* */ 8891/* Returns: */ 8892/* 0 for success, positive value for failure. */ 8893/****************************************************************************/ 8894static int 8895bce_sysctl_nvram_read(SYSCTL_HANDLER_ARGS) 8896{ 8897 struct bce_softc *sc = (struct bce_softc *)arg1; 8898 int error; 8899 u32 result; 8900 u32 val[1]; 8901 u8 *data = (u8 *) val; 8902 8903 result = -1; 8904 error = sysctl_handle_int(oidp, &result, 0, req); 8905 if (error || (req->newptr == NULL)) 8906 return (error); 8907 8908 error = bce_nvram_read(sc, result, data, 4); 8909 8910 BCE_PRINTF("offset 0x%08X = 0x%08X\n", result, bce_be32toh(val[0])); 8911 8912 return (error); 8913} 8914 8915 8916/****************************************************************************/ 8917/* Provides a sysctl interface to allow reading arbitrary registers in the */ 8918/* device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8919/* */ 8920/* Returns: */ 8921/* 0 for success, positive value for failure. */ 8922/****************************************************************************/ 8923static int 8924bce_sysctl_reg_read(SYSCTL_HANDLER_ARGS) 8925{ 8926 struct bce_softc *sc = (struct bce_softc *)arg1; 8927 int error; 8928 u32 val, result; 8929 8930 result = -1; 8931 error = sysctl_handle_int(oidp, &result, 0, req); 8932 if (error || (req->newptr == NULL)) 8933 return (error); 8934 8935 /* Make sure the register is accessible. */ 8936 if (result < 0x8000) { 8937 val = REG_RD(sc, result); 8938 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val); 8939 } else if (result < 0x0280000) { 8940 val = REG_RD_IND(sc, result); 8941 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val); 8942 } 8943 8944 return (error); 8945} 8946 8947 8948/****************************************************************************/ 8949/* Provides a sysctl interface to allow reading arbitrary PHY registers in */ 8950/* the device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8951/* */ 8952/* Returns: */ 8953/* 0 for success, positive value for failure. */ 8954/****************************************************************************/ 8955static int 8956bce_sysctl_phy_read(SYSCTL_HANDLER_ARGS) 8957{ 8958 struct bce_softc *sc; 8959 device_t dev; 8960 int error, result; 8961 u16 val; 8962 8963 result = -1; 8964 error = sysctl_handle_int(oidp, &result, 0, req); 8965 if (error || (req->newptr == NULL)) 8966 return (error); 8967 8968 /* Make sure the register is accessible. */ 8969 if (result < 0x20) { 8970 sc = (struct bce_softc *)arg1; 8971 dev = sc->bce_dev; 8972 val = bce_miibus_read_reg(dev, sc->bce_phy_addr, result); 8973 BCE_PRINTF("phy 0x%02X = 0x%04X\n", result, val); 8974 } 8975 return (error); 8976} 8977 8978 8979/****************************************************************************/ 8980/* Provides a sysctl interface for dumping the nvram contents. */ 8981/* DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8982/* */ 8983/* Returns: */ 8984/* 0 for success, positive errno for failure. */ 8985/****************************************************************************/ 8986static int 8987bce_sysctl_nvram_dump(SYSCTL_HANDLER_ARGS) 8988{ 8989 struct bce_softc *sc = (struct bce_softc *)arg1; 8990 int error, i; 8991 8992 if (sc->nvram_buf == NULL) 8993 sc->nvram_buf = malloc(sc->bce_flash_size, 8994 M_TEMP, M_ZERO | M_WAITOK); 8995 8996 error = 0; 8997 if (req->oldlen == sc->bce_flash_size) { 8998 for (i = 0; i < sc->bce_flash_size && error == 0; i++) 8999 error = bce_nvram_read(sc, i, &sc->nvram_buf[i], 1); 9000 } 9001 9002 if (error == 0) 9003 error = SYSCTL_OUT(req, sc->nvram_buf, sc->bce_flash_size); 9004 9005 return error; 9006} 9007 9008#ifdef BCE_NVRAM_WRITE_SUPPORT 9009/****************************************************************************/ 9010/* Provides a sysctl interface for writing to nvram. */ 9011/* DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 9012/* */ 9013/* Returns: */ 9014/* 0 for success, positive errno for failure. */ 9015/****************************************************************************/ 9016static int 9017bce_sysctl_nvram_write(SYSCTL_HANDLER_ARGS) 9018{ 9019 struct bce_softc *sc = (struct bce_softc *)arg1; 9020 int error; 9021 9022 if (sc->nvram_buf == NULL) 9023 sc->nvram_buf = malloc(sc->bce_flash_size, 9024 M_TEMP, M_ZERO | M_WAITOK); 9025 else 9026 bzero(sc->nvram_buf, sc->bce_flash_size); 9027 9028 error = SYSCTL_IN(req, sc->nvram_buf, sc->bce_flash_size); 9029 if (error == 0) 9030 return (error); 9031 9032 if (req->newlen == sc->bce_flash_size) 9033 error = bce_nvram_write(sc, 0, sc->nvram_buf, 9034 sc->bce_flash_size); 9035 9036 9037 return error; 9038} 9039#endif 9040 9041 9042/****************************************************************************/ 9043/* Provides a sysctl interface to allow reading a CID. */ 9044/* */ 9045/* Returns: */ 9046/* 0 for success, positive value for failure. */ 9047/****************************************************************************/ 9048static int 9049bce_sysctl_dump_ctx(SYSCTL_HANDLER_ARGS) 9050{ 9051 struct bce_softc *sc; 9052 int error, result; 9053 9054 result = -1; 9055 error = sysctl_handle_int(oidp, &result, 0, req); 9056 if (error || (req->newptr == NULL)) 9057 return (error); 9058 9059 /* Make sure the register is accessible. */ 9060 if (result <= TX_CID) { 9061 sc = (struct bce_softc *)arg1; 9062 bce_dump_ctx(sc, result); 9063 } 9064 9065 return (error); 9066} 9067 9068 9069/****************************************************************************/ 9070/* Provides a sysctl interface to forcing the driver to dump state and */ 9071/* enter the debugger. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 9072/* */ 9073/* Returns: */ 9074/* 0 for success, positive value for failure. */ 9075/****************************************************************************/ 9076static int 9077bce_sysctl_breakpoint(SYSCTL_HANDLER_ARGS) 9078{ 9079 int error; 9080 int result; 9081 struct bce_softc *sc; 9082 9083 result = -1; 9084 error = sysctl_handle_int(oidp, &result, 0, req); 9085 9086 if (error || !req->newptr) 9087 return (error); 9088 9089 if (result == 1) { 9090 sc = (struct bce_softc *)arg1; 9091 bce_breakpoint(sc); 9092 } 9093 9094 return error; 9095} 9096#endif 9097 9098/****************************************************************************/ 9099/* Adds any sysctl parameters for tuning or debugging purposes. */ 9100/* */ 9101/* Returns: */ 9102/* 0 for success, positive value for failure. */ 9103/****************************************************************************/ 9104static void 9105bce_add_sysctls(struct bce_softc *sc) 9106{ 9107 struct sysctl_ctx_list *ctx; 9108 struct sysctl_oid_list *children; 9109 9110 DBENTER(BCE_VERBOSE_MISC); 9111 9112 ctx = device_get_sysctl_ctx(sc->bce_dev); 9113 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bce_dev)); 9114 9115#ifdef BCE_DEBUG 9116 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 9117 "l2fhdr_error_sim_control", 9118 CTLFLAG_RW, &l2fhdr_error_sim_control, 9119 0, "Debug control to force l2fhdr errors"); 9120 9121 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 9122 "l2fhdr_error_sim_count", 9123 CTLFLAG_RD, &sc->l2fhdr_error_sim_count, 9124 0, "Number of simulated l2_fhdr errors"); 9125#endif 9126 9127 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9128 "l2fhdr_error_count", 9129 CTLFLAG_RD, &sc->l2fhdr_error_count, 9130 0, "Number of l2_fhdr errors"); 9131 9132#ifdef BCE_DEBUG 9133 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 9134 "mbuf_alloc_failed_sim_control", 9135 CTLFLAG_RW, &mbuf_alloc_failed_sim_control, 9136 0, "Debug control to force mbuf allocation failures"); 9137 9138 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9139 "mbuf_alloc_failed_sim_count", 9140 CTLFLAG_RD, &sc->mbuf_alloc_failed_sim_count, 9141 0, "Number of simulated mbuf cluster allocation failures"); 9142#endif 9143 9144 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9145 "mbuf_alloc_failed_count", 9146 CTLFLAG_RD, &sc->mbuf_alloc_failed_count, 9147 0, "Number of mbuf allocation failures"); 9148 9149 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9150 "mbuf_frag_count", 9151 CTLFLAG_RD, &sc->mbuf_frag_count, 9152 0, "Number of fragmented mbufs"); 9153 9154#ifdef BCE_DEBUG 9155 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 9156 "dma_map_addr_failed_sim_control", 9157 CTLFLAG_RW, &dma_map_addr_failed_sim_control, 9158 0, "Debug control to force DMA mapping failures"); 9159 9160 /* ToDo: Figure out how to update this value in bce_dma_map_addr(). */ 9161 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9162 "dma_map_addr_failed_sim_count", 9163 CTLFLAG_RD, &sc->dma_map_addr_failed_sim_count, 9164 0, "Number of simulated DMA mapping failures"); 9165 9166#endif 9167 9168 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9169 "dma_map_addr_rx_failed_count", 9170 CTLFLAG_RD, &sc->dma_map_addr_rx_failed_count, 9171 0, "Number of RX DMA mapping failures"); 9172 9173 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9174 "dma_map_addr_tx_failed_count", 9175 CTLFLAG_RD, &sc->dma_map_addr_tx_failed_count, 9176 0, "Number of TX DMA mapping failures"); 9177 9178#ifdef BCE_DEBUG 9179 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 9180 "unexpected_attention_sim_control", 9181 CTLFLAG_RW, &unexpected_attention_sim_control, 9182 0, "Debug control to simulate unexpected attentions"); 9183 9184 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9185 "unexpected_attention_sim_count", 9186 CTLFLAG_RW, &sc->unexpected_attention_sim_count, 9187 0, "Number of simulated unexpected attentions"); 9188#endif 9189 9190 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9191 "unexpected_attention_count", 9192 CTLFLAG_RW, &sc->unexpected_attention_count, 9193 0, "Number of unexpected attentions"); 9194 9195#ifdef BCE_DEBUG 9196 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 9197 "debug_bootcode_running_failure", 9198 CTLFLAG_RW, &bootcode_running_failure_sim_control, 9199 0, "Debug control to force bootcode running failures"); 9200 9201 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 9202 "rx_low_watermark", 9203 CTLFLAG_RD, &sc->rx_low_watermark, 9204 0, "Lowest level of free rx_bd's"); 9205 9206 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9207 "rx_empty_count", 9208 CTLFLAG_RD, &sc->rx_empty_count, 9209 "Number of times the RX chain was empty"); 9210 9211 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 9212 "tx_hi_watermark", 9213 CTLFLAG_RD, &sc->tx_hi_watermark, 9214 0, "Highest level of used tx_bd's"); 9215 9216 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9217 "tx_full_count", 9218 CTLFLAG_RD, &sc->tx_full_count, 9219 "Number of times the TX chain was full"); 9220 9221 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9222 "tso_frames_requested", 9223 CTLFLAG_RD, &sc->tso_frames_requested, 9224 "Number of TSO frames requested"); 9225 9226 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9227 "tso_frames_completed", 9228 CTLFLAG_RD, &sc->tso_frames_completed, 9229 "Number of TSO frames completed"); 9230 9231 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9232 "tso_frames_failed", 9233 CTLFLAG_RD, &sc->tso_frames_failed, 9234 "Number of TSO frames failed"); 9235 9236 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9237 "csum_offload_ip", 9238 CTLFLAG_RD, &sc->csum_offload_ip, 9239 "Number of IP checksum offload frames"); 9240 9241 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9242 "csum_offload_tcp_udp", 9243 CTLFLAG_RD, &sc->csum_offload_tcp_udp, 9244 "Number of TCP/UDP checksum offload frames"); 9245 9246 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9247 "vlan_tagged_frames_rcvd", 9248 CTLFLAG_RD, &sc->vlan_tagged_frames_rcvd, 9249 "Number of VLAN tagged frames received"); 9250 9251 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9252 "vlan_tagged_frames_stripped", 9253 CTLFLAG_RD, &sc->vlan_tagged_frames_stripped, 9254 "Number of VLAN tagged frames stripped"); 9255 9256 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9257 "interrupts_rx", 9258 CTLFLAG_RD, &sc->interrupts_rx, 9259 "Number of RX interrupts"); 9260 9261 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9262 "interrupts_tx", 9263 CTLFLAG_RD, &sc->interrupts_tx, 9264 "Number of TX interrupts"); 9265 9266 if (bce_hdr_split == TRUE) { 9267 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9268 "split_header_frames_rcvd", 9269 CTLFLAG_RD, &sc->split_header_frames_rcvd, 9270 "Number of split header frames received"); 9271 9272 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9273 "split_header_tcp_frames_rcvd", 9274 CTLFLAG_RD, &sc->split_header_tcp_frames_rcvd, 9275 "Number of split header TCP frames received"); 9276 } 9277 9278 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9279 "nvram_dump", CTLTYPE_OPAQUE | CTLFLAG_RD, 9280 (void *)sc, 0, 9281 bce_sysctl_nvram_dump, "S", ""); 9282 9283#ifdef BCE_NVRAM_WRITE_SUPPORT 9284 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9285 "nvram_write", CTLTYPE_OPAQUE | CTLFLAG_WR, 9286 (void *)sc, 0, 9287 bce_sysctl_nvram_write, "S", ""); 9288#endif 9289#endif /* BCE_DEBUG */ 9290 9291 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9292 "stat_IfHcInOctets", 9293 CTLFLAG_RD, &sc->stat_IfHCInOctets, 9294 "Bytes received"); 9295 9296 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9297 "stat_IfHCInBadOctets", 9298 CTLFLAG_RD, &sc->stat_IfHCInBadOctets, 9299 "Bad bytes received"); 9300 9301 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9302 "stat_IfHCOutOctets", 9303 CTLFLAG_RD, &sc->stat_IfHCOutOctets, 9304 "Bytes sent"); 9305 9306 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9307 "stat_IfHCOutBadOctets", 9308 CTLFLAG_RD, &sc->stat_IfHCOutBadOctets, 9309 "Bad bytes sent"); 9310 9311 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9312 "stat_IfHCInUcastPkts", 9313 CTLFLAG_RD, &sc->stat_IfHCInUcastPkts, 9314 "Unicast packets received"); 9315 9316 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9317 "stat_IfHCInMulticastPkts", 9318 CTLFLAG_RD, &sc->stat_IfHCInMulticastPkts, 9319 "Multicast packets received"); 9320 9321 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9322 "stat_IfHCInBroadcastPkts", 9323 CTLFLAG_RD, &sc->stat_IfHCInBroadcastPkts, 9324 "Broadcast packets received"); 9325 9326 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9327 "stat_IfHCOutUcastPkts", 9328 CTLFLAG_RD, &sc->stat_IfHCOutUcastPkts, 9329 "Unicast packets sent"); 9330 9331 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9332 "stat_IfHCOutMulticastPkts", 9333 CTLFLAG_RD, &sc->stat_IfHCOutMulticastPkts, 9334 "Multicast packets sent"); 9335 9336 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9337 "stat_IfHCOutBroadcastPkts", 9338 CTLFLAG_RD, &sc->stat_IfHCOutBroadcastPkts, 9339 "Broadcast packets sent"); 9340 9341 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9342 "stat_emac_tx_stat_dot3statsinternalmactransmiterrors", 9343 CTLFLAG_RD, &sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors, 9344 0, "Internal MAC transmit errors"); 9345 9346 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9347 "stat_Dot3StatsCarrierSenseErrors", 9348 CTLFLAG_RD, &sc->stat_Dot3StatsCarrierSenseErrors, 9349 0, "Carrier sense errors"); 9350 9351 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9352 "stat_Dot3StatsFCSErrors", 9353 CTLFLAG_RD, &sc->stat_Dot3StatsFCSErrors, 9354 0, "Frame check sequence errors"); 9355 9356 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9357 "stat_Dot3StatsAlignmentErrors", 9358 CTLFLAG_RD, &sc->stat_Dot3StatsAlignmentErrors, 9359 0, "Alignment errors"); 9360 9361 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9362 "stat_Dot3StatsSingleCollisionFrames", 9363 CTLFLAG_RD, &sc->stat_Dot3StatsSingleCollisionFrames, 9364 0, "Single Collision Frames"); 9365 9366 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9367 "stat_Dot3StatsMultipleCollisionFrames", 9368 CTLFLAG_RD, &sc->stat_Dot3StatsMultipleCollisionFrames, 9369 0, "Multiple Collision Frames"); 9370 9371 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9372 "stat_Dot3StatsDeferredTransmissions", 9373 CTLFLAG_RD, &sc->stat_Dot3StatsDeferredTransmissions, 9374 0, "Deferred Transmissions"); 9375 9376 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9377 "stat_Dot3StatsExcessiveCollisions", 9378 CTLFLAG_RD, &sc->stat_Dot3StatsExcessiveCollisions, 9379 0, "Excessive Collisions"); 9380 9381 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9382 "stat_Dot3StatsLateCollisions", 9383 CTLFLAG_RD, &sc->stat_Dot3StatsLateCollisions, 9384 0, "Late Collisions"); 9385 9386 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9387 "stat_EtherStatsCollisions", 9388 CTLFLAG_RD, &sc->stat_EtherStatsCollisions, 9389 0, "Collisions"); 9390 9391 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9392 "stat_EtherStatsFragments", 9393 CTLFLAG_RD, &sc->stat_EtherStatsFragments, 9394 0, "Fragments"); 9395 9396 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9397 "stat_EtherStatsJabbers", 9398 CTLFLAG_RD, &sc->stat_EtherStatsJabbers, 9399 0, "Jabbers"); 9400 9401 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9402 "stat_EtherStatsUndersizePkts", 9403 CTLFLAG_RD, &sc->stat_EtherStatsUndersizePkts, 9404 0, "Undersize packets"); 9405 9406 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9407 "stat_EtherStatsOversizePkts", 9408 CTLFLAG_RD, &sc->stat_EtherStatsOversizePkts, 9409 0, "stat_EtherStatsOversizePkts"); 9410 9411 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9412 "stat_EtherStatsPktsRx64Octets", 9413 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx64Octets, 9414 0, "Bytes received in 64 byte packets"); 9415 9416 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9417 "stat_EtherStatsPktsRx65Octetsto127Octets", 9418 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx65Octetsto127Octets, 9419 0, "Bytes received in 65 to 127 byte packets"); 9420 9421 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9422 "stat_EtherStatsPktsRx128Octetsto255Octets", 9423 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx128Octetsto255Octets, 9424 0, "Bytes received in 128 to 255 byte packets"); 9425 9426 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9427 "stat_EtherStatsPktsRx256Octetsto511Octets", 9428 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx256Octetsto511Octets, 9429 0, "Bytes received in 256 to 511 byte packets"); 9430 9431 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9432 "stat_EtherStatsPktsRx512Octetsto1023Octets", 9433 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx512Octetsto1023Octets, 9434 0, "Bytes received in 512 to 1023 byte packets"); 9435 9436 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9437 "stat_EtherStatsPktsRx1024Octetsto1522Octets", 9438 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1024Octetsto1522Octets, 9439 0, "Bytes received in 1024 t0 1522 byte packets"); 9440 9441 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9442 "stat_EtherStatsPktsRx1523Octetsto9022Octets", 9443 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1523Octetsto9022Octets, 9444 0, "Bytes received in 1523 to 9022 byte packets"); 9445 9446 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9447 "stat_EtherStatsPktsTx64Octets", 9448 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx64Octets, 9449 0, "Bytes sent in 64 byte packets"); 9450 9451 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9452 "stat_EtherStatsPktsTx65Octetsto127Octets", 9453 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx65Octetsto127Octets, 9454 0, "Bytes sent in 65 to 127 byte packets"); 9455 9456 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9457 "stat_EtherStatsPktsTx128Octetsto255Octets", 9458 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx128Octetsto255Octets, 9459 0, "Bytes sent in 128 to 255 byte packets"); 9460 9461 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9462 "stat_EtherStatsPktsTx256Octetsto511Octets", 9463 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx256Octetsto511Octets, 9464 0, "Bytes sent in 256 to 511 byte packets"); 9465 9466 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9467 "stat_EtherStatsPktsTx512Octetsto1023Octets", 9468 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx512Octetsto1023Octets, 9469 0, "Bytes sent in 512 to 1023 byte packets"); 9470 9471 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9472 "stat_EtherStatsPktsTx1024Octetsto1522Octets", 9473 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1024Octetsto1522Octets, 9474 0, "Bytes sent in 1024 to 1522 byte packets"); 9475 9476 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9477 "stat_EtherStatsPktsTx1523Octetsto9022Octets", 9478 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1523Octetsto9022Octets, 9479 0, "Bytes sent in 1523 to 9022 byte packets"); 9480 9481 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9482 "stat_XonPauseFramesReceived", 9483 CTLFLAG_RD, &sc->stat_XonPauseFramesReceived, 9484 0, "XON pause frames receved"); 9485 9486 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9487 "stat_XoffPauseFramesReceived", 9488 CTLFLAG_RD, &sc->stat_XoffPauseFramesReceived, 9489 0, "XOFF pause frames received"); 9490 9491 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9492 "stat_OutXonSent", 9493 CTLFLAG_RD, &sc->stat_OutXonSent, 9494 0, "XON pause frames sent"); 9495 9496 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9497 "stat_OutXoffSent", 9498 CTLFLAG_RD, &sc->stat_OutXoffSent, 9499 0, "XOFF pause frames sent"); 9500 9501 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9502 "stat_FlowControlDone", 9503 CTLFLAG_RD, &sc->stat_FlowControlDone, 9504 0, "Flow control done"); 9505 9506 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9507 "stat_MacControlFramesReceived", 9508 CTLFLAG_RD, &sc->stat_MacControlFramesReceived, 9509 0, "MAC control frames received"); 9510 9511 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9512 "stat_XoffStateEntered", 9513 CTLFLAG_RD, &sc->stat_XoffStateEntered, 9514 0, "XOFF state entered"); 9515 9516 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9517 "stat_IfInFramesL2FilterDiscards", 9518 CTLFLAG_RD, &sc->stat_IfInFramesL2FilterDiscards, 9519 0, "Received L2 packets discarded"); 9520 9521 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9522 "stat_IfInRuleCheckerDiscards", 9523 CTLFLAG_RD, &sc->stat_IfInRuleCheckerDiscards, 9524 0, "Received packets discarded by rule"); 9525 9526 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9527 "stat_IfInFTQDiscards", 9528 CTLFLAG_RD, &sc->stat_IfInFTQDiscards, 9529 0, "Received packet FTQ discards"); 9530 9531 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9532 "stat_IfInMBUFDiscards", 9533 CTLFLAG_RD, &sc->stat_IfInMBUFDiscards, 9534 0, "Received packets discarded due to lack " 9535 "of controller buffer memory"); 9536 9537 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9538 "stat_IfInRuleCheckerP4Hit", 9539 CTLFLAG_RD, &sc->stat_IfInRuleCheckerP4Hit, 9540 0, "Received packets rule checker hits"); 9541 9542 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9543 "stat_CatchupInRuleCheckerDiscards", 9544 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerDiscards, 9545 0, "Received packets discarded in Catchup path"); 9546 9547 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9548 "stat_CatchupInFTQDiscards", 9549 CTLFLAG_RD, &sc->stat_CatchupInFTQDiscards, 9550 0, "Received packets discarded in FTQ in Catchup path"); 9551 9552 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9553 "stat_CatchupInMBUFDiscards", 9554 CTLFLAG_RD, &sc->stat_CatchupInMBUFDiscards, 9555 0, "Received packets discarded in controller " 9556 "buffer memory in Catchup path"); 9557 9558 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9559 "stat_CatchupInRuleCheckerP4Hit", 9560 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerP4Hit, 9561 0, "Received packets rule checker hits in Catchup path"); 9562 9563 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9564 "com_no_buffers", 9565 CTLFLAG_RD, &sc->com_no_buffers, 9566 0, "Valid packets received but no RX buffers available"); 9567 9568#ifdef BCE_DEBUG 9569 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9570 "driver_state", CTLTYPE_INT | CTLFLAG_RW, 9571 (void *)sc, 0, 9572 bce_sysctl_driver_state, "I", "Drive state information"); 9573 9574 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9575 "hw_state", CTLTYPE_INT | CTLFLAG_RW, 9576 (void *)sc, 0, 9577 bce_sysctl_hw_state, "I", "Hardware state information"); 9578 9579 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9580 "status_block", CTLTYPE_INT | CTLFLAG_RW, 9581 (void *)sc, 0, 9582 bce_sysctl_status_block, "I", "Dump status block"); 9583 9584 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9585 "stats_block", CTLTYPE_INT | CTLFLAG_RW, 9586 (void *)sc, 0, 9587 bce_sysctl_stats_block, "I", "Dump statistics block"); 9588 9589 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9590 "stats_clear", CTLTYPE_INT | CTLFLAG_RW, 9591 (void *)sc, 0, 9592 bce_sysctl_stats_clear, "I", "Clear statistics block"); 9593 9594 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9595 "shmem_state", CTLTYPE_INT | CTLFLAG_RW, 9596 (void *)sc, 0, 9597 bce_sysctl_shmem_state, "I", "Shared memory state information"); 9598 9599 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9600 "bc_state", CTLTYPE_INT | CTLFLAG_RW, 9601 (void *)sc, 0, 9602 bce_sysctl_bc_state, "I", "Bootcode state information"); 9603 9604 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9605 "dump_rx_bd_chain", CTLTYPE_INT | CTLFLAG_RW, 9606 (void *)sc, 0, 9607 bce_sysctl_dump_rx_bd_chain, "I", "Dump RX BD chain"); 9608 9609 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9610 "dump_rx_mbuf_chain", CTLTYPE_INT | CTLFLAG_RW, 9611 (void *)sc, 0, 9612 bce_sysctl_dump_rx_mbuf_chain, "I", "Dump RX MBUF chain"); 9613 9614 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9615 "dump_tx_chain", CTLTYPE_INT | CTLFLAG_RW, 9616 (void *)sc, 0, 9617 bce_sysctl_dump_tx_chain, "I", "Dump tx_bd chain"); 9618 9619 if (bce_hdr_split == TRUE) { 9620 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9621 "dump_pg_chain", CTLTYPE_INT | CTLFLAG_RW, 9622 (void *)sc, 0, 9623 bce_sysctl_dump_pg_chain, "I", "Dump page chain"); 9624 } 9625 9626 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9627 "dump_ctx", CTLTYPE_INT | CTLFLAG_RW, 9628 (void *)sc, 0, 9629 bce_sysctl_dump_ctx, "I", "Dump context memory"); 9630 9631 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9632 "breakpoint", CTLTYPE_INT | CTLFLAG_RW, 9633 (void *)sc, 0, 9634 bce_sysctl_breakpoint, "I", "Driver breakpoint"); 9635 9636 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9637 "reg_read", CTLTYPE_INT | CTLFLAG_RW, 9638 (void *)sc, 0, 9639 bce_sysctl_reg_read, "I", "Register read"); 9640 9641 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9642 "nvram_read", CTLTYPE_INT | CTLFLAG_RW, 9643 (void *)sc, 0, 9644 bce_sysctl_nvram_read, "I", "NVRAM read"); 9645 9646 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9647 "phy_read", CTLTYPE_INT | CTLFLAG_RW, 9648 (void *)sc, 0, 9649 bce_sysctl_phy_read, "I", "PHY register read"); 9650 9651#endif 9652 9653 DBEXIT(BCE_VERBOSE_MISC); 9654} 9655 9656 9657/****************************************************************************/ 9658/* BCE Debug Routines */ 9659/****************************************************************************/ 9660#ifdef BCE_DEBUG 9661 9662/****************************************************************************/ 9663/* Freezes the controller to allow for a cohesive state dump. */ 9664/* */ 9665/* Returns: */ 9666/* Nothing. */ 9667/****************************************************************************/ 9668static __attribute__ ((noinline)) void 9669bce_freeze_controller(struct bce_softc *sc) 9670{ 9671 u32 val; 9672 val = REG_RD(sc, BCE_MISC_COMMAND); 9673 val |= BCE_MISC_COMMAND_DISABLE_ALL; 9674 REG_WR(sc, BCE_MISC_COMMAND, val); 9675} 9676 9677 9678/****************************************************************************/ 9679/* Unfreezes the controller after a freeze operation. This may not always */ 9680/* work and the controller will require a reset! */ 9681/* */ 9682/* Returns: */ 9683/* Nothing. */ 9684/****************************************************************************/ 9685static __attribute__ ((noinline)) void 9686bce_unfreeze_controller(struct bce_softc *sc) 9687{ 9688 u32 val; 9689 val = REG_RD(sc, BCE_MISC_COMMAND); 9690 val |= BCE_MISC_COMMAND_ENABLE_ALL; 9691 REG_WR(sc, BCE_MISC_COMMAND, val); 9692} 9693 9694 9695/****************************************************************************/ 9696/* Prints out Ethernet frame information from an mbuf. */ 9697/* */ 9698/* Partially decode an Ethernet frame to look at some important headers. */ 9699/* */ 9700/* Returns: */ 9701/* Nothing. */ 9702/****************************************************************************/ 9703static __attribute__ ((noinline)) void 9704bce_dump_enet(struct bce_softc *sc, struct mbuf *m) 9705{ 9706 struct ether_vlan_header *eh; 9707 u16 etype; 9708 int ehlen; 9709 struct ip *ip; 9710 struct tcphdr *th; 9711 struct udphdr *uh; 9712 struct arphdr *ah; 9713 9714 BCE_PRINTF( 9715 "-----------------------------" 9716 " Frame Decode " 9717 "-----------------------------\n"); 9718 9719 eh = mtod(m, struct ether_vlan_header *); 9720 9721 /* Handle VLAN encapsulation if present. */ 9722 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 9723 etype = ntohs(eh->evl_proto); 9724 ehlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 9725 } else { 9726 etype = ntohs(eh->evl_encap_proto); 9727 ehlen = ETHER_HDR_LEN; 9728 } 9729 9730 /* ToDo: Add VLAN output. */ 9731 BCE_PRINTF("enet: dest = %6D, src = %6D, type = 0x%04X, hlen = %d\n", 9732 eh->evl_dhost, ":", eh->evl_shost, ":", etype, ehlen); 9733 9734 switch (etype) { 9735 case ETHERTYPE_IP: 9736 ip = (struct ip *)(m->m_data + ehlen); 9737 BCE_PRINTF("--ip: dest = 0x%08X , src = 0x%08X, " 9738 "len = %d bytes, protocol = 0x%02X, xsum = 0x%04X\n", 9739 ntohl(ip->ip_dst.s_addr), ntohl(ip->ip_src.s_addr), 9740 ntohs(ip->ip_len), ip->ip_p, ntohs(ip->ip_sum)); 9741 9742 switch (ip->ip_p) { 9743 case IPPROTO_TCP: 9744 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 9745 BCE_PRINTF("-tcp: dest = %d, src = %d, hlen = " 9746 "%d bytes, flags = 0x%b, csum = 0x%04X\n", 9747 ntohs(th->th_dport), ntohs(th->th_sport), 9748 (th->th_off << 2), th->th_flags, 9749 "\20\10CWR\07ECE\06URG\05ACK\04PSH\03RST" 9750 "\02SYN\01FIN", ntohs(th->th_sum)); 9751 break; 9752 case IPPROTO_UDP: 9753 uh = (struct udphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 9754 BCE_PRINTF("-udp: dest = %d, src = %d, len = %d " 9755 "bytes, csum = 0x%04X\n", ntohs(uh->uh_dport), 9756 ntohs(uh->uh_sport), ntohs(uh->uh_ulen), 9757 ntohs(uh->uh_sum)); 9758 break; 9759 case IPPROTO_ICMP: 9760 BCE_PRINTF("icmp:\n"); 9761 break; 9762 default: 9763 BCE_PRINTF("----: Other IP protocol.\n"); 9764 } 9765 break; 9766 case ETHERTYPE_IPV6: 9767 BCE_PRINTF("ipv6: No decode supported.\n"); 9768 break; 9769 case ETHERTYPE_ARP: 9770 BCE_PRINTF("-arp: "); 9771 ah = (struct arphdr *) (m->m_data + ehlen); 9772 switch (ntohs(ah->ar_op)) { 9773 case ARPOP_REVREQUEST: 9774 printf("reverse ARP request\n"); 9775 break; 9776 case ARPOP_REVREPLY: 9777 printf("reverse ARP reply\n"); 9778 break; 9779 case ARPOP_REQUEST: 9780 printf("ARP request\n"); 9781 break; 9782 case ARPOP_REPLY: 9783 printf("ARP reply\n"); 9784 break; 9785 default: 9786 printf("other ARP operation\n"); 9787 } 9788 break; 9789 default: 9790 BCE_PRINTF("----: Other protocol.\n"); 9791 } 9792 9793 BCE_PRINTF( 9794 "-----------------------------" 9795 "--------------" 9796 "-----------------------------\n"); 9797} 9798 9799 9800/****************************************************************************/ 9801/* Prints out information about an mbuf. */ 9802/* */ 9803/* Returns: */ 9804/* Nothing. */ 9805/****************************************************************************/ 9806static __attribute__ ((noinline)) void 9807bce_dump_mbuf(struct bce_softc *sc, struct mbuf *m) 9808{ 9809 struct mbuf *mp = m; 9810 9811 if (m == NULL) { 9812 BCE_PRINTF("mbuf: null pointer\n"); 9813 return; 9814 } 9815 9816 while (mp) { 9817 BCE_PRINTF("mbuf: %p, m_len = %d, m_flags = 0x%b, " 9818 "m_data = %p\n", mp, mp->m_len, mp->m_flags, 9819 "\20\1M_EXT\2M_PKTHDR\3M_EOR\4M_RDONLY", mp->m_data); 9820 9821 if (mp->m_flags & M_PKTHDR) { 9822 BCE_PRINTF("- m_pkthdr: len = %d, flags = 0x%b, " 9823 "csum_flags = %b\n", mp->m_pkthdr.len, 9824 mp->m_flags, M_FLAG_PRINTF, 9825 mp->m_pkthdr.csum_flags, 9826 "\20\1CSUM_IP\2CSUM_TCP\3CSUM_UDP" 9827 "\5CSUM_FRAGMENT\6CSUM_TSO\11CSUM_IP_CHECKED" 9828 "\12CSUM_IP_VALID\13CSUM_DATA_VALID" 9829 "\14CSUM_PSEUDO_HDR"); 9830 } 9831 9832 if (mp->m_flags & M_EXT) { 9833 BCE_PRINTF("- m_ext: %p, ext_size = %d, type = ", 9834 mp->m_ext.ext_buf, mp->m_ext.ext_size); 9835 switch (mp->m_ext.ext_type) { 9836 case EXT_CLUSTER: 9837 printf("EXT_CLUSTER\n"); break; 9838 case EXT_SFBUF: 9839 printf("EXT_SFBUF\n"); break; 9840 case EXT_JUMBO9: 9841 printf("EXT_JUMBO9\n"); break; 9842 case EXT_JUMBO16: 9843 printf("EXT_JUMBO16\n"); break; 9844 case EXT_PACKET: 9845 printf("EXT_PACKET\n"); break; 9846 case EXT_MBUF: 9847 printf("EXT_MBUF\n"); break; 9848 case EXT_NET_DRV: 9849 printf("EXT_NET_DRV\n"); break; 9850 case EXT_MOD_TYPE: 9851 printf("EXT_MDD_TYPE\n"); break; 9852 case EXT_DISPOSABLE: 9853 printf("EXT_DISPOSABLE\n"); break; 9854 case EXT_EXTREF: 9855 printf("EXT_EXTREF\n"); break; 9856 default: 9857 printf("UNKNOWN\n"); 9858 } 9859 } 9860 9861 mp = mp->m_next; 9862 } 9863} 9864 9865 9866/****************************************************************************/ 9867/* Prints out the mbufs in the TX mbuf chain. */ 9868/* */ 9869/* Returns: */ 9870/* Nothing. */ 9871/****************************************************************************/ 9872static __attribute__ ((noinline)) void 9873bce_dump_tx_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count) 9874{ 9875 struct mbuf *m; 9876 9877 BCE_PRINTF( 9878 "----------------------------" 9879 " tx mbuf data " 9880 "----------------------------\n"); 9881 9882 for (int i = 0; i < count; i++) { 9883 m = sc->tx_mbuf_ptr[chain_prod]; 9884 BCE_PRINTF("txmbuf[0x%04X]\n", chain_prod); 9885 bce_dump_mbuf(sc, m); 9886 chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod)); 9887 } 9888 9889 BCE_PRINTF( 9890 "----------------------------" 9891 "----------------" 9892 "----------------------------\n"); 9893} 9894 9895 9896/****************************************************************************/ 9897/* Prints out the mbufs in the RX mbuf chain. */ 9898/* */ 9899/* Returns: */ 9900/* Nothing. */ 9901/****************************************************************************/ 9902static __attribute__ ((noinline)) void 9903bce_dump_rx_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count) 9904{ 9905 struct mbuf *m; 9906 9907 BCE_PRINTF( 9908 "----------------------------" 9909 " rx mbuf data " 9910 "----------------------------\n"); 9911 9912 for (int i = 0; i < count; i++) { 9913 m = sc->rx_mbuf_ptr[chain_prod]; 9914 BCE_PRINTF("rxmbuf[0x%04X]\n", chain_prod); 9915 bce_dump_mbuf(sc, m); 9916 chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod)); 9917 } 9918 9919 9920 BCE_PRINTF( 9921 "----------------------------" 9922 "----------------" 9923 "----------------------------\n"); 9924} 9925 9926 9927/****************************************************************************/ 9928/* Prints out the mbufs in the mbuf page chain. */ 9929/* */ 9930/* Returns: */ 9931/* Nothing. */ 9932/****************************************************************************/ 9933static __attribute__ ((noinline)) void 9934bce_dump_pg_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count) 9935{ 9936 struct mbuf *m; 9937 9938 BCE_PRINTF( 9939 "----------------------------" 9940 " pg mbuf data " 9941 "----------------------------\n"); 9942 9943 for (int i = 0; i < count; i++) { 9944 m = sc->pg_mbuf_ptr[chain_prod]; 9945 BCE_PRINTF("pgmbuf[0x%04X]\n", chain_prod); 9946 bce_dump_mbuf(sc, m); 9947 chain_prod = PG_CHAIN_IDX(NEXT_PG_BD(chain_prod)); 9948 } 9949 9950 9951 BCE_PRINTF( 9952 "----------------------------" 9953 "----------------" 9954 "----------------------------\n"); 9955} 9956 9957 9958/****************************************************************************/ 9959/* Prints out a tx_bd structure. */ 9960/* */ 9961/* Returns: */ 9962/* Nothing. */ 9963/****************************************************************************/ 9964static __attribute__ ((noinline)) void 9965bce_dump_txbd(struct bce_softc *sc, int idx, struct tx_bd *txbd) 9966{ 9967 int i = 0; 9968 9969 if (idx > MAX_TX_BD_ALLOC) 9970 /* Index out of range. */ 9971 BCE_PRINTF("tx_bd[0x%04X]: Invalid tx_bd index!\n", idx); 9972 else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 9973 /* TX Chain page pointer. */ 9974 BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page " 9975 "pointer\n", idx, txbd->tx_bd_haddr_hi, 9976 txbd->tx_bd_haddr_lo); 9977 else { 9978 /* Normal tx_bd entry. */ 9979 BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, " 9980 "mss_nbytes = 0x%08X, vlan tag = 0x%04X, flags = " 9981 "0x%04X (", idx, txbd->tx_bd_haddr_hi, 9982 txbd->tx_bd_haddr_lo, txbd->tx_bd_mss_nbytes, 9983 txbd->tx_bd_vlan_tag, txbd->tx_bd_flags); 9984 9985 if (txbd->tx_bd_flags & TX_BD_FLAGS_CONN_FAULT) { 9986 if (i>0) 9987 printf("|"); 9988 printf("CONN_FAULT"); 9989 i++; 9990 } 9991 9992 if (txbd->tx_bd_flags & TX_BD_FLAGS_TCP_UDP_CKSUM) { 9993 if (i>0) 9994 printf("|"); 9995 printf("TCP_UDP_CKSUM"); 9996 i++; 9997 } 9998 9999 if (txbd->tx_bd_flags & TX_BD_FLAGS_IP_CKSUM) { 10000 if (i>0) 10001 printf("|"); 10002 printf("IP_CKSUM"); 10003 i++; 10004 } 10005 10006 if (txbd->tx_bd_flags & TX_BD_FLAGS_VLAN_TAG) { 10007 if (i>0) 10008 printf("|"); 10009 printf("VLAN"); 10010 i++; 10011 } 10012 10013 if (txbd->tx_bd_flags & TX_BD_FLAGS_COAL_NOW) { 10014 if (i>0) 10015 printf("|"); 10016 printf("COAL_NOW"); 10017 i++; 10018 } 10019 10020 if (txbd->tx_bd_flags & TX_BD_FLAGS_DONT_GEN_CRC) { 10021 if (i>0) 10022 printf("|"); 10023 printf("DONT_GEN_CRC"); 10024 i++; 10025 } 10026 10027 if (txbd->tx_bd_flags & TX_BD_FLAGS_START) { 10028 if (i>0) 10029 printf("|"); 10030 printf("START"); 10031 i++; 10032 } 10033 10034 if (txbd->tx_bd_flags & TX_BD_FLAGS_END) { 10035 if (i>0) 10036 printf("|"); 10037 printf("END"); 10038 i++; 10039 } 10040 10041 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_LSO) { 10042 if (i>0) 10043 printf("|"); 10044 printf("LSO"); 10045 i++; 10046 } 10047 10048 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_OPTION_WORD) { 10049 if (i>0) 10050 printf("|"); 10051 printf("SW_OPTION=%d", ((txbd->tx_bd_flags & 10052 TX_BD_FLAGS_SW_OPTION_WORD) >> 8)); i++; 10053 } 10054 10055 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_FLAGS) { 10056 if (i>0) 10057 printf("|"); 10058 printf("SW_FLAGS"); 10059 i++; 10060 } 10061 10062 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_SNAP) { 10063 if (i>0) 10064 printf("|"); 10065 printf("SNAP)"); 10066 } else { 10067 printf(")\n"); 10068 } 10069 } 10070} 10071 10072 10073/****************************************************************************/ 10074/* Prints out a rx_bd structure. */ 10075/* */ 10076/* Returns: */ 10077/* Nothing. */ 10078/****************************************************************************/ 10079static __attribute__ ((noinline)) void 10080bce_dump_rxbd(struct bce_softc *sc, int idx, struct rx_bd *rxbd) 10081{ 10082 if (idx > MAX_RX_BD_ALLOC) 10083 /* Index out of range. */ 10084 BCE_PRINTF("rx_bd[0x%04X]: Invalid rx_bd index!\n", idx); 10085 else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 10086 /* RX Chain page pointer. */ 10087 BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page " 10088 "pointer\n", idx, rxbd->rx_bd_haddr_hi, 10089 rxbd->rx_bd_haddr_lo); 10090 else 10091 /* Normal rx_bd entry. */ 10092 BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = " 10093 "0x%08X, flags = 0x%08X\n", idx, rxbd->rx_bd_haddr_hi, 10094 rxbd->rx_bd_haddr_lo, rxbd->rx_bd_len, 10095 rxbd->rx_bd_flags); 10096} 10097 10098 10099/****************************************************************************/ 10100/* Prints out a rx_bd structure in the page chain. */ 10101/* */ 10102/* Returns: */ 10103/* Nothing. */ 10104/****************************************************************************/ 10105static __attribute__ ((noinline)) void 10106bce_dump_pgbd(struct bce_softc *sc, int idx, struct rx_bd *pgbd) 10107{ 10108 if (idx > MAX_PG_BD_ALLOC) 10109 /* Index out of range. */ 10110 BCE_PRINTF("pg_bd[0x%04X]: Invalid pg_bd index!\n", idx); 10111 else if ((idx & USABLE_PG_BD_PER_PAGE) == USABLE_PG_BD_PER_PAGE) 10112 /* Page Chain page pointer. */ 10113 BCE_PRINTF("px_bd[0x%04X]: haddr = 0x%08X:%08X, chain page pointer\n", 10114 idx, pgbd->rx_bd_haddr_hi, pgbd->rx_bd_haddr_lo); 10115 else 10116 /* Normal rx_bd entry. */ 10117 BCE_PRINTF("pg_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = 0x%08X, " 10118 "flags = 0x%08X\n", idx, 10119 pgbd->rx_bd_haddr_hi, pgbd->rx_bd_haddr_lo, 10120 pgbd->rx_bd_len, pgbd->rx_bd_flags); 10121} 10122 10123 10124/****************************************************************************/ 10125/* Prints out a l2_fhdr structure. */ 10126/* */ 10127/* Returns: */ 10128/* Nothing. */ 10129/****************************************************************************/ 10130static __attribute__ ((noinline)) void 10131bce_dump_l2fhdr(struct bce_softc *sc, int idx, struct l2_fhdr *l2fhdr) 10132{ 10133 BCE_PRINTF("l2_fhdr[0x%04X]: status = 0x%b, " 10134 "pkt_len = %d, vlan = 0x%04x, ip_xsum/hdr_len = 0x%04X, " 10135 "tcp_udp_xsum = 0x%04X\n", idx, 10136 l2fhdr->l2_fhdr_status, BCE_L2FHDR_PRINTFB, 10137 l2fhdr->l2_fhdr_pkt_len, l2fhdr->l2_fhdr_vlan_tag, 10138 l2fhdr->l2_fhdr_ip_xsum, l2fhdr->l2_fhdr_tcp_udp_xsum); 10139} 10140 10141 10142/****************************************************************************/ 10143/* Prints out context memory info. (Only useful for CID 0 to 16.) */ 10144/* */ 10145/* Returns: */ 10146/* Nothing. */ 10147/****************************************************************************/ 10148static __attribute__ ((noinline)) void 10149bce_dump_ctx(struct bce_softc *sc, u16 cid) 10150{ 10151 if (cid > TX_CID) { 10152 BCE_PRINTF(" Unknown CID\n"); 10153 return; 10154 } 10155 10156 BCE_PRINTF( 10157 "----------------------------" 10158 " CTX Data " 10159 "----------------------------\n"); 10160 10161 BCE_PRINTF(" 0x%04X - (CID) Context ID\n", cid); 10162 10163 if (cid == RX_CID) { 10164 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_BDIDX) host rx " 10165 "producer index\n", 10166 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_HOST_BDIDX)); 10167 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_BSEQ) host " 10168 "byte sequence\n", CTX_RD(sc, GET_CID_ADDR(cid), 10169 BCE_L2CTX_RX_HOST_BSEQ)); 10170 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BSEQ) h/w byte sequence\n", 10171 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BSEQ)); 10172 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDHADDR_HI) h/w buffer " 10173 "descriptor address\n", 10174 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BDHADDR_HI)); 10175 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDHADDR_LO) h/w buffer " 10176 "descriptor address\n", 10177 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BDHADDR_LO)); 10178 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDIDX) h/w rx consumer " 10179 "index\n", CTX_RD(sc, GET_CID_ADDR(cid), 10180 BCE_L2CTX_RX_NX_BDIDX)); 10181 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_PG_BDIDX) host page " 10182 "producer index\n", CTX_RD(sc, GET_CID_ADDR(cid), 10183 BCE_L2CTX_RX_HOST_PG_BDIDX)); 10184 BCE_PRINTF(" 0x%08X - (L2CTX_RX_PG_BUF_SIZE) host rx_bd/page " 10185 "buffer size\n", CTX_RD(sc, GET_CID_ADDR(cid), 10186 BCE_L2CTX_RX_PG_BUF_SIZE)); 10187 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDHADDR_HI) h/w page " 10188 "chain address\n", CTX_RD(sc, GET_CID_ADDR(cid), 10189 BCE_L2CTX_RX_NX_PG_BDHADDR_HI)); 10190 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDHADDR_LO) h/w page " 10191 "chain address\n", CTX_RD(sc, GET_CID_ADDR(cid), 10192 BCE_L2CTX_RX_NX_PG_BDHADDR_LO)); 10193 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDIDX) h/w page " 10194 "consumer index\n", CTX_RD(sc, GET_CID_ADDR(cid), 10195 BCE_L2CTX_RX_NX_PG_BDIDX)); 10196 } else if (cid == TX_CID) { 10197 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 10198 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TYPE_XI) ctx type\n", 10199 CTX_RD(sc, GET_CID_ADDR(cid), 10200 BCE_L2CTX_TX_TYPE_XI)); 10201 BCE_PRINTF(" 0x%08X - (L2CTX_CMD_TX_TYPE_XI) ctx " 10202 "cmd\n", CTX_RD(sc, GET_CID_ADDR(cid), 10203 BCE_L2CTX_TX_CMD_TYPE_XI)); 10204 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BDHADDR_HI_XI) " 10205 "h/w buffer descriptor address\n", 10206 CTX_RD(sc, GET_CID_ADDR(cid), 10207 BCE_L2CTX_TX_TBDR_BHADDR_HI_XI)); 10208 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BHADDR_LO_XI) " 10209 "h/w buffer descriptor address\n", 10210 CTX_RD(sc, GET_CID_ADDR(cid), 10211 BCE_L2CTX_TX_TBDR_BHADDR_LO_XI)); 10212 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BIDX_XI) " 10213 "host producer index\n", 10214 CTX_RD(sc, GET_CID_ADDR(cid), 10215 BCE_L2CTX_TX_HOST_BIDX_XI)); 10216 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BSEQ_XI) " 10217 "host byte sequence\n", 10218 CTX_RD(sc, GET_CID_ADDR(cid), 10219 BCE_L2CTX_TX_HOST_BSEQ_XI)); 10220 } else { 10221 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TYPE) ctx type\n", 10222 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_TX_TYPE)); 10223 BCE_PRINTF(" 0x%08X - (L2CTX_TX_CMD_TYPE) ctx cmd\n", 10224 CTX_RD(sc, GET_CID_ADDR(cid), 10225 BCE_L2CTX_TX_CMD_TYPE)); 10226 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BDHADDR_HI) " 10227 "h/w buffer descriptor address\n", 10228 CTX_RD(sc, GET_CID_ADDR(cid), 10229 BCE_L2CTX_TX_TBDR_BHADDR_HI)); 10230 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BHADDR_LO) " 10231 "h/w buffer descriptor address\n", 10232 CTX_RD(sc, GET_CID_ADDR(cid), 10233 BCE_L2CTX_TX_TBDR_BHADDR_LO)); 10234 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BIDX) host " 10235 "producer index\n", CTX_RD(sc, GET_CID_ADDR(cid), 10236 BCE_L2CTX_TX_HOST_BIDX)); 10237 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BSEQ) host byte " 10238 "sequence\n", CTX_RD(sc, GET_CID_ADDR(cid), 10239 BCE_L2CTX_TX_HOST_BSEQ)); 10240 } 10241 } 10242 10243 BCE_PRINTF( 10244 "----------------------------" 10245 " Raw CTX " 10246 "----------------------------\n"); 10247 10248 for (int i = 0x0; i < 0x300; i += 0x10) { 10249 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", i, 10250 CTX_RD(sc, GET_CID_ADDR(cid), i), 10251 CTX_RD(sc, GET_CID_ADDR(cid), i + 0x4), 10252 CTX_RD(sc, GET_CID_ADDR(cid), i + 0x8), 10253 CTX_RD(sc, GET_CID_ADDR(cid), i + 0xc)); 10254 } 10255 10256 10257 BCE_PRINTF( 10258 "----------------------------" 10259 "----------------" 10260 "----------------------------\n"); 10261} 10262 10263 10264/****************************************************************************/ 10265/* Prints out the FTQ data. */ 10266/* */ 10267/* Returns: */ 10268/* Nothing. */ 10269/****************************************************************************/ 10270static __attribute__ ((noinline)) void 10271bce_dump_ftqs(struct bce_softc *sc) 10272{ 10273 u32 cmd, ctl, cur_depth, max_depth, valid_cnt, val; 10274 10275 BCE_PRINTF( 10276 "----------------------------" 10277 " FTQ Data " 10278 "----------------------------\n"); 10279 10280 BCE_PRINTF(" FTQ Command Control Depth_Now " 10281 "Max_Depth Valid_Cnt \n"); 10282 BCE_PRINTF(" ------- ---------- ---------- ---------- " 10283 "---------- ----------\n"); 10284 10285 /* Setup the generic statistic counters for the FTQ valid count. */ 10286 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT << 24) | 10287 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT << 16) | 10288 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT << 8) | 10289 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT); 10290 REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val); 10291 10292 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT << 24) | 10293 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT << 16) | 10294 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT << 8) | 10295 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT); 10296 REG_WR(sc, BCE_HC_STAT_GEN_SEL_1, val); 10297 10298 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT << 24) | 10299 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT << 16) | 10300 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT << 8) | 10301 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT); 10302 REG_WR(sc, BCE_HC_STAT_GEN_SEL_2, val); 10303 10304 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT << 24) | 10305 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT << 16) | 10306 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT << 8) | 10307 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT); 10308 REG_WR(sc, BCE_HC_STAT_GEN_SEL_3, val); 10309 10310 /* Input queue to the Receive Lookup state machine */ 10311 cmd = REG_RD(sc, BCE_RLUP_FTQ_CMD); 10312 ctl = REG_RD(sc, BCE_RLUP_FTQ_CTL); 10313 cur_depth = (ctl & BCE_RLUP_FTQ_CTL_CUR_DEPTH) >> 22; 10314 max_depth = (ctl & BCE_RLUP_FTQ_CTL_MAX_DEPTH) >> 12; 10315 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0); 10316 BCE_PRINTF(" RLUP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10317 cmd, ctl, cur_depth, max_depth, valid_cnt); 10318 10319 /* Input queue to the Receive Processor */ 10320 cmd = REG_RD_IND(sc, BCE_RXP_FTQ_CMD); 10321 ctl = REG_RD_IND(sc, BCE_RXP_FTQ_CTL); 10322 cur_depth = (ctl & BCE_RXP_FTQ_CTL_CUR_DEPTH) >> 22; 10323 max_depth = (ctl & BCE_RXP_FTQ_CTL_MAX_DEPTH) >> 12; 10324 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1); 10325 BCE_PRINTF(" RXP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10326 cmd, ctl, cur_depth, max_depth, valid_cnt); 10327 10328 /* Input queue to the Recevie Processor */ 10329 cmd = REG_RD_IND(sc, BCE_RXP_CFTQ_CMD); 10330 ctl = REG_RD_IND(sc, BCE_RXP_CFTQ_CTL); 10331 cur_depth = (ctl & BCE_RXP_CFTQ_CTL_CUR_DEPTH) >> 22; 10332 max_depth = (ctl & BCE_RXP_CFTQ_CTL_MAX_DEPTH) >> 12; 10333 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2); 10334 BCE_PRINTF(" RXPC 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10335 cmd, ctl, cur_depth, max_depth, valid_cnt); 10336 10337 /* Input queue to the Receive Virtual to Physical state machine */ 10338 cmd = REG_RD(sc, BCE_RV2P_PFTQ_CMD); 10339 ctl = REG_RD(sc, BCE_RV2P_PFTQ_CTL); 10340 cur_depth = (ctl & BCE_RV2P_PFTQ_CTL_CUR_DEPTH) >> 22; 10341 max_depth = (ctl & BCE_RV2P_PFTQ_CTL_MAX_DEPTH) >> 12; 10342 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT3); 10343 BCE_PRINTF(" RV2PP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10344 cmd, ctl, cur_depth, max_depth, valid_cnt); 10345 10346 /* Input queue to the Recevie Virtual to Physical state machine */ 10347 cmd = REG_RD(sc, BCE_RV2P_MFTQ_CMD); 10348 ctl = REG_RD(sc, BCE_RV2P_MFTQ_CTL); 10349 cur_depth = (ctl & BCE_RV2P_MFTQ_CTL_CUR_DEPTH) >> 22; 10350 max_depth = (ctl & BCE_RV2P_MFTQ_CTL_MAX_DEPTH) >> 12; 10351 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT4); 10352 BCE_PRINTF(" RV2PM 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10353 cmd, ctl, cur_depth, max_depth, valid_cnt); 10354 10355 /* Input queue to the Receive Virtual to Physical state machine */ 10356 cmd = REG_RD(sc, BCE_RV2P_TFTQ_CMD); 10357 ctl = REG_RD(sc, BCE_RV2P_TFTQ_CTL); 10358 cur_depth = (ctl & BCE_RV2P_TFTQ_CTL_CUR_DEPTH) >> 22; 10359 max_depth = (ctl & BCE_RV2P_TFTQ_CTL_MAX_DEPTH) >> 12; 10360 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT5); 10361 BCE_PRINTF(" RV2PT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10362 cmd, ctl, cur_depth, max_depth, valid_cnt); 10363 10364 /* Input queue to the Receive DMA state machine */ 10365 cmd = REG_RD(sc, BCE_RDMA_FTQ_CMD); 10366 ctl = REG_RD(sc, BCE_RDMA_FTQ_CTL); 10367 cur_depth = (ctl & BCE_RDMA_FTQ_CTL_CUR_DEPTH) >> 22; 10368 max_depth = (ctl & BCE_RDMA_FTQ_CTL_MAX_DEPTH) >> 12; 10369 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT6); 10370 BCE_PRINTF(" RDMA 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10371 cmd, ctl, cur_depth, max_depth, valid_cnt); 10372 10373 /* Input queue to the Transmit Scheduler state machine */ 10374 cmd = REG_RD(sc, BCE_TSCH_FTQ_CMD); 10375 ctl = REG_RD(sc, BCE_TSCH_FTQ_CTL); 10376 cur_depth = (ctl & BCE_TSCH_FTQ_CTL_CUR_DEPTH) >> 22; 10377 max_depth = (ctl & BCE_TSCH_FTQ_CTL_MAX_DEPTH) >> 12; 10378 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT7); 10379 BCE_PRINTF(" TSCH 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10380 cmd, ctl, cur_depth, max_depth, valid_cnt); 10381 10382 /* Input queue to the Transmit Buffer Descriptor state machine */ 10383 cmd = REG_RD(sc, BCE_TBDR_FTQ_CMD); 10384 ctl = REG_RD(sc, BCE_TBDR_FTQ_CTL); 10385 cur_depth = (ctl & BCE_TBDR_FTQ_CTL_CUR_DEPTH) >> 22; 10386 max_depth = (ctl & BCE_TBDR_FTQ_CTL_MAX_DEPTH) >> 12; 10387 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT8); 10388 BCE_PRINTF(" TBDR 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10389 cmd, ctl, cur_depth, max_depth, valid_cnt); 10390 10391 /* Input queue to the Transmit Processor */ 10392 cmd = REG_RD_IND(sc, BCE_TXP_FTQ_CMD); 10393 ctl = REG_RD_IND(sc, BCE_TXP_FTQ_CTL); 10394 cur_depth = (ctl & BCE_TXP_FTQ_CTL_CUR_DEPTH) >> 22; 10395 max_depth = (ctl & BCE_TXP_FTQ_CTL_MAX_DEPTH) >> 12; 10396 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT9); 10397 BCE_PRINTF(" TXP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10398 cmd, ctl, cur_depth, max_depth, valid_cnt); 10399 10400 /* Input queue to the Transmit DMA state machine */ 10401 cmd = REG_RD(sc, BCE_TDMA_FTQ_CMD); 10402 ctl = REG_RD(sc, BCE_TDMA_FTQ_CTL); 10403 cur_depth = (ctl & BCE_TDMA_FTQ_CTL_CUR_DEPTH) >> 22; 10404 max_depth = (ctl & BCE_TDMA_FTQ_CTL_MAX_DEPTH) >> 12; 10405 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT10); 10406 BCE_PRINTF(" TDMA 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10407 cmd, ctl, cur_depth, max_depth, valid_cnt); 10408 10409 /* Input queue to the Transmit Patch-Up Processor */ 10410 cmd = REG_RD_IND(sc, BCE_TPAT_FTQ_CMD); 10411 ctl = REG_RD_IND(sc, BCE_TPAT_FTQ_CTL); 10412 cur_depth = (ctl & BCE_TPAT_FTQ_CTL_CUR_DEPTH) >> 22; 10413 max_depth = (ctl & BCE_TPAT_FTQ_CTL_MAX_DEPTH) >> 12; 10414 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT11); 10415 BCE_PRINTF(" TPAT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10416 cmd, ctl, cur_depth, max_depth, valid_cnt); 10417 10418 /* Input queue to the Transmit Assembler state machine */ 10419 cmd = REG_RD_IND(sc, BCE_TAS_FTQ_CMD); 10420 ctl = REG_RD_IND(sc, BCE_TAS_FTQ_CTL); 10421 cur_depth = (ctl & BCE_TAS_FTQ_CTL_CUR_DEPTH) >> 22; 10422 max_depth = (ctl & BCE_TAS_FTQ_CTL_MAX_DEPTH) >> 12; 10423 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT12); 10424 BCE_PRINTF(" TAS 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10425 cmd, ctl, cur_depth, max_depth, valid_cnt); 10426 10427 /* Input queue to the Completion Processor */ 10428 cmd = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CMD); 10429 ctl = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CTL); 10430 cur_depth = (ctl & BCE_COM_COMXQ_FTQ_CTL_CUR_DEPTH) >> 22; 10431 max_depth = (ctl & BCE_COM_COMXQ_FTQ_CTL_MAX_DEPTH) >> 12; 10432 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT13); 10433 BCE_PRINTF(" COMX 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10434 cmd, ctl, cur_depth, max_depth, valid_cnt); 10435 10436 /* Input queue to the Completion Processor */ 10437 cmd = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CMD); 10438 ctl = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CTL); 10439 cur_depth = (ctl & BCE_COM_COMTQ_FTQ_CTL_CUR_DEPTH) >> 22; 10440 max_depth = (ctl & BCE_COM_COMTQ_FTQ_CTL_MAX_DEPTH) >> 12; 10441 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT14); 10442 BCE_PRINTF(" COMT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10443 cmd, ctl, cur_depth, max_depth, valid_cnt); 10444 10445 /* Input queue to the Completion Processor */ 10446 cmd = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CMD); 10447 ctl = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CTL); 10448 cur_depth = (ctl & BCE_COM_COMQ_FTQ_CTL_CUR_DEPTH) >> 22; 10449 max_depth = (ctl & BCE_COM_COMQ_FTQ_CTL_MAX_DEPTH) >> 12; 10450 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT15); 10451 BCE_PRINTF(" COMX 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10452 cmd, ctl, cur_depth, max_depth, valid_cnt); 10453 10454 /* Setup the generic statistic counters for the FTQ valid count. */ 10455 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT << 16) | 10456 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT << 8) | 10457 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT); 10458 10459 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) 10460 val = val | 10461 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCSQ_VALID_CNT_XI << 10462 24); 10463 REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val); 10464 10465 /* Input queue to the Management Control Processor */ 10466 cmd = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CMD); 10467 ctl = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CTL); 10468 cur_depth = (ctl & BCE_MCP_MCPQ_FTQ_CTL_CUR_DEPTH) >> 22; 10469 max_depth = (ctl & BCE_MCP_MCPQ_FTQ_CTL_MAX_DEPTH) >> 12; 10470 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0); 10471 BCE_PRINTF(" MCP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10472 cmd, ctl, cur_depth, max_depth, valid_cnt); 10473 10474 /* Input queue to the Command Processor */ 10475 cmd = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CMD); 10476 ctl = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CTL); 10477 cur_depth = (ctl & BCE_CP_CPQ_FTQ_CTL_CUR_DEPTH) >> 22; 10478 max_depth = (ctl & BCE_CP_CPQ_FTQ_CTL_MAX_DEPTH) >> 12; 10479 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1); 10480 BCE_PRINTF(" CP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10481 cmd, ctl, cur_depth, max_depth, valid_cnt); 10482 10483 /* Input queue to the Completion Scheduler state machine */ 10484 cmd = REG_RD(sc, BCE_CSCH_CH_FTQ_CMD); 10485 ctl = REG_RD(sc, BCE_CSCH_CH_FTQ_CTL); 10486 cur_depth = (ctl & BCE_CSCH_CH_FTQ_CTL_CUR_DEPTH) >> 22; 10487 max_depth = (ctl & BCE_CSCH_CH_FTQ_CTL_MAX_DEPTH) >> 12; 10488 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2); 10489 BCE_PRINTF(" CS 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10490 cmd, ctl, cur_depth, max_depth, valid_cnt); 10491 10492 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 10493 /* Input queue to the RV2P Command Scheduler */ 10494 cmd = REG_RD(sc, BCE_RV2PCSR_FTQ_CMD); 10495 ctl = REG_RD(sc, BCE_RV2PCSR_FTQ_CTL); 10496 cur_depth = (ctl & 0xFFC00000) >> 22; 10497 max_depth = (ctl & 0x003FF000) >> 12; 10498 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT3); 10499 BCE_PRINTF(" RV2PCSR 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10500 cmd, ctl, cur_depth, max_depth, valid_cnt); 10501 } 10502 10503 BCE_PRINTF( 10504 "----------------------------" 10505 "----------------" 10506 "----------------------------\n"); 10507} 10508 10509 10510/****************************************************************************/ 10511/* Prints out the TX chain. */ 10512/* */ 10513/* Returns: */ 10514/* Nothing. */ 10515/****************************************************************************/ 10516static __attribute__ ((noinline)) void 10517bce_dump_tx_chain(struct bce_softc *sc, u16 tx_prod, int count) 10518{ 10519 struct tx_bd *txbd; 10520 10521 /* First some info about the tx_bd chain structure. */ 10522 BCE_PRINTF( 10523 "----------------------------" 10524 " tx_bd chain " 10525 "----------------------------\n"); 10526 10527 BCE_PRINTF("page size = 0x%08X, tx chain pages = 0x%08X\n", 10528 (u32) BCM_PAGE_SIZE, (u32) sc->tx_pages); 10529 BCE_PRINTF("tx_bd per page = 0x%08X, usable tx_bd per page = 0x%08X\n", 10530 (u32) TOTAL_TX_BD_PER_PAGE, (u32) USABLE_TX_BD_PER_PAGE); 10531 BCE_PRINTF("total tx_bd = 0x%08X\n", (u32) TOTAL_TX_BD_ALLOC); 10532 10533 BCE_PRINTF( 10534 "----------------------------" 10535 " tx_bd data " 10536 "----------------------------\n"); 10537 10538 /* Now print out a decoded list of TX buffer descriptors. */ 10539 for (int i = 0; i < count; i++) { 10540 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)]; 10541 bce_dump_txbd(sc, tx_prod, txbd); 10542 tx_prod++; 10543 } 10544 10545 BCE_PRINTF( 10546 "----------------------------" 10547 "----------------" 10548 "----------------------------\n"); 10549} 10550 10551 10552/****************************************************************************/ 10553/* Prints out the RX chain. */ 10554/* */ 10555/* Returns: */ 10556/* Nothing. */ 10557/****************************************************************************/ 10558static __attribute__ ((noinline)) void 10559bce_dump_rx_bd_chain(struct bce_softc *sc, u16 rx_prod, int count) 10560{ 10561 struct rx_bd *rxbd; 10562 10563 /* First some info about the rx_bd chain structure. */ 10564 BCE_PRINTF( 10565 "----------------------------" 10566 " rx_bd chain " 10567 "----------------------------\n"); 10568 10569 BCE_PRINTF("page size = 0x%08X, rx chain pages = 0x%08X\n", 10570 (u32) BCM_PAGE_SIZE, (u32) sc->rx_pages); 10571 10572 BCE_PRINTF("rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n", 10573 (u32) TOTAL_RX_BD_PER_PAGE, (u32) USABLE_RX_BD_PER_PAGE); 10574 10575 BCE_PRINTF("total rx_bd = 0x%08X\n", (u32) TOTAL_RX_BD_ALLOC); 10576 10577 BCE_PRINTF( 10578 "----------------------------" 10579 " rx_bd data " 10580 "----------------------------\n"); 10581 10582 /* Now print out the rx_bd's themselves. */ 10583 for (int i = 0; i < count; i++) { 10584 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)]; 10585 bce_dump_rxbd(sc, rx_prod, rxbd); 10586 rx_prod = RX_CHAIN_IDX(rx_prod + 1); 10587 } 10588 10589 BCE_PRINTF( 10590 "----------------------------" 10591 "----------------" 10592 "----------------------------\n"); 10593} 10594 10595 10596/****************************************************************************/ 10597/* Prints out the page chain. */ 10598/* */ 10599/* Returns: */ 10600/* Nothing. */ 10601/****************************************************************************/ 10602static __attribute__ ((noinline)) void 10603bce_dump_pg_chain(struct bce_softc *sc, u16 pg_prod, int count) 10604{ 10605 struct rx_bd *pgbd; 10606 10607 /* First some info about the page chain structure. */ 10608 BCE_PRINTF( 10609 "----------------------------" 10610 " page chain " 10611 "----------------------------\n"); 10612 10613 BCE_PRINTF("page size = 0x%08X, pg chain pages = 0x%08X\n", 10614 (u32) BCM_PAGE_SIZE, (u32) sc->pg_pages); 10615 10616 BCE_PRINTF("rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n", 10617 (u32) TOTAL_PG_BD_PER_PAGE, (u32) USABLE_PG_BD_PER_PAGE); 10618 10619 BCE_PRINTF("total pg_bd = 0x%08X\n", (u32) TOTAL_PG_BD_ALLOC); 10620 10621 BCE_PRINTF( 10622 "----------------------------" 10623 " page data " 10624 "----------------------------\n"); 10625 10626 /* Now print out the rx_bd's themselves. */ 10627 for (int i = 0; i < count; i++) { 10628 pgbd = &sc->pg_bd_chain[PG_PAGE(pg_prod)][PG_IDX(pg_prod)]; 10629 bce_dump_pgbd(sc, pg_prod, pgbd); 10630 pg_prod = PG_CHAIN_IDX(pg_prod + 1); 10631 } 10632 10633 BCE_PRINTF( 10634 "----------------------------" 10635 "----------------" 10636 "----------------------------\n"); 10637} 10638 10639 10640#define BCE_PRINT_RX_CONS(arg) \ 10641if (sblk->status_rx_quick_consumer_index##arg) \ 10642 BCE_PRINTF("0x%04X(0x%04X) - rx_quick_consumer_index%d\n", \ 10643 sblk->status_rx_quick_consumer_index##arg, (u16) \ 10644 RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index##arg), \ 10645 arg); 10646 10647 10648#define BCE_PRINT_TX_CONS(arg) \ 10649if (sblk->status_tx_quick_consumer_index##arg) \ 10650 BCE_PRINTF("0x%04X(0x%04X) - tx_quick_consumer_index%d\n", \ 10651 sblk->status_tx_quick_consumer_index##arg, (u16) \ 10652 TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index##arg), \ 10653 arg); 10654 10655/****************************************************************************/ 10656/* Prints out the status block from host memory. */ 10657/* */ 10658/* Returns: */ 10659/* Nothing. */ 10660/****************************************************************************/ 10661static __attribute__ ((noinline)) void 10662bce_dump_status_block(struct bce_softc *sc) 10663{ 10664 struct status_block *sblk; 10665 10666 bus_dmamap_sync(sc->status_tag, sc->status_map, BUS_DMASYNC_POSTREAD); 10667 10668 sblk = sc->status_block; 10669 10670 BCE_PRINTF( 10671 "----------------------------" 10672 " Status Block " 10673 "----------------------------\n"); 10674 10675 /* Theses indices are used for normal L2 drivers. */ 10676 BCE_PRINTF(" 0x%08X - attn_bits\n", 10677 sblk->status_attn_bits); 10678 10679 BCE_PRINTF(" 0x%08X - attn_bits_ack\n", 10680 sblk->status_attn_bits_ack); 10681 10682 BCE_PRINT_RX_CONS(0); 10683 BCE_PRINT_TX_CONS(0) 10684 10685 BCE_PRINTF(" 0x%04X - status_idx\n", sblk->status_idx); 10686 10687 /* Theses indices are not used for normal L2 drivers. */ 10688 BCE_PRINT_RX_CONS(1); BCE_PRINT_RX_CONS(2); BCE_PRINT_RX_CONS(3); 10689 BCE_PRINT_RX_CONS(4); BCE_PRINT_RX_CONS(5); BCE_PRINT_RX_CONS(6); 10690 BCE_PRINT_RX_CONS(7); BCE_PRINT_RX_CONS(8); BCE_PRINT_RX_CONS(9); 10691 BCE_PRINT_RX_CONS(10); BCE_PRINT_RX_CONS(11); BCE_PRINT_RX_CONS(12); 10692 BCE_PRINT_RX_CONS(13); BCE_PRINT_RX_CONS(14); BCE_PRINT_RX_CONS(15); 10693 10694 BCE_PRINT_TX_CONS(1); BCE_PRINT_TX_CONS(2); BCE_PRINT_TX_CONS(3); 10695 10696 if (sblk->status_completion_producer_index || 10697 sblk->status_cmd_consumer_index) 10698 BCE_PRINTF("com_prod = 0x%08X, cmd_cons = 0x%08X\n", 10699 sblk->status_completion_producer_index, 10700 sblk->status_cmd_consumer_index); 10701 10702 BCE_PRINTF( 10703 "----------------------------" 10704 "----------------" 10705 "----------------------------\n"); 10706} 10707 10708 10709#define BCE_PRINT_64BIT_STAT(arg) \ 10710if (sblk->arg##_lo || sblk->arg##_hi) \ 10711 BCE_PRINTF("0x%08X:%08X : %s\n", sblk->arg##_hi, \ 10712 sblk->arg##_lo, #arg); 10713 10714#define BCE_PRINT_32BIT_STAT(arg) \ 10715if (sblk->arg) \ 10716 BCE_PRINTF(" 0x%08X : %s\n", \ 10717 sblk->arg, #arg); 10718 10719/****************************************************************************/ 10720/* Prints out the statistics block from host memory. */ 10721/* */ 10722/* Returns: */ 10723/* Nothing. */ 10724/****************************************************************************/ 10725static __attribute__ ((noinline)) void 10726bce_dump_stats_block(struct bce_softc *sc) 10727{ 10728 struct statistics_block *sblk; 10729 10730 bus_dmamap_sync(sc->stats_tag, sc->stats_map, BUS_DMASYNC_POSTREAD); 10731 10732 sblk = sc->stats_block; 10733 10734 BCE_PRINTF( 10735 "---------------" 10736 " Stats Block (All Stats Not Shown Are 0) " 10737 "---------------\n"); 10738 10739 BCE_PRINT_64BIT_STAT(stat_IfHCInOctets); 10740 BCE_PRINT_64BIT_STAT(stat_IfHCInBadOctets); 10741 BCE_PRINT_64BIT_STAT(stat_IfHCOutOctets); 10742 BCE_PRINT_64BIT_STAT(stat_IfHCOutBadOctets); 10743 BCE_PRINT_64BIT_STAT(stat_IfHCInUcastPkts); 10744 BCE_PRINT_64BIT_STAT(stat_IfHCInBroadcastPkts); 10745 BCE_PRINT_64BIT_STAT(stat_IfHCInMulticastPkts); 10746 BCE_PRINT_64BIT_STAT(stat_IfHCOutUcastPkts); 10747 BCE_PRINT_64BIT_STAT(stat_IfHCOutBroadcastPkts); 10748 BCE_PRINT_64BIT_STAT(stat_IfHCOutMulticastPkts); 10749 BCE_PRINT_32BIT_STAT( 10750 stat_emac_tx_stat_dot3statsinternalmactransmiterrors); 10751 BCE_PRINT_32BIT_STAT(stat_Dot3StatsCarrierSenseErrors); 10752 BCE_PRINT_32BIT_STAT(stat_Dot3StatsFCSErrors); 10753 BCE_PRINT_32BIT_STAT(stat_Dot3StatsAlignmentErrors); 10754 BCE_PRINT_32BIT_STAT(stat_Dot3StatsSingleCollisionFrames); 10755 BCE_PRINT_32BIT_STAT(stat_Dot3StatsMultipleCollisionFrames); 10756 BCE_PRINT_32BIT_STAT(stat_Dot3StatsDeferredTransmissions); 10757 BCE_PRINT_32BIT_STAT(stat_Dot3StatsExcessiveCollisions); 10758 BCE_PRINT_32BIT_STAT(stat_Dot3StatsLateCollisions); 10759 BCE_PRINT_32BIT_STAT(stat_EtherStatsCollisions); 10760 BCE_PRINT_32BIT_STAT(stat_EtherStatsFragments); 10761 BCE_PRINT_32BIT_STAT(stat_EtherStatsJabbers); 10762 BCE_PRINT_32BIT_STAT(stat_EtherStatsUndersizePkts); 10763 BCE_PRINT_32BIT_STAT(stat_EtherStatsOversizePkts); 10764 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx64Octets); 10765 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx65Octetsto127Octets); 10766 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx128Octetsto255Octets); 10767 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx256Octetsto511Octets); 10768 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx512Octetsto1023Octets); 10769 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx1024Octetsto1522Octets); 10770 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx1523Octetsto9022Octets); 10771 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx64Octets); 10772 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx65Octetsto127Octets); 10773 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx128Octetsto255Octets); 10774 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx256Octetsto511Octets); 10775 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx512Octetsto1023Octets); 10776 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx1024Octetsto1522Octets); 10777 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx1523Octetsto9022Octets); 10778 BCE_PRINT_32BIT_STAT(stat_XonPauseFramesReceived); 10779 BCE_PRINT_32BIT_STAT(stat_XoffPauseFramesReceived); 10780 BCE_PRINT_32BIT_STAT(stat_OutXonSent); 10781 BCE_PRINT_32BIT_STAT(stat_OutXoffSent); 10782 BCE_PRINT_32BIT_STAT(stat_FlowControlDone); 10783 BCE_PRINT_32BIT_STAT(stat_MacControlFramesReceived); 10784 BCE_PRINT_32BIT_STAT(stat_XoffStateEntered); 10785 BCE_PRINT_32BIT_STAT(stat_IfInFramesL2FilterDiscards); 10786 BCE_PRINT_32BIT_STAT(stat_IfInRuleCheckerDiscards); 10787 BCE_PRINT_32BIT_STAT(stat_IfInFTQDiscards); 10788 BCE_PRINT_32BIT_STAT(stat_IfInMBUFDiscards); 10789 BCE_PRINT_32BIT_STAT(stat_IfInRuleCheckerP4Hit); 10790 BCE_PRINT_32BIT_STAT(stat_CatchupInRuleCheckerDiscards); 10791 BCE_PRINT_32BIT_STAT(stat_CatchupInFTQDiscards); 10792 BCE_PRINT_32BIT_STAT(stat_CatchupInMBUFDiscards); 10793 BCE_PRINT_32BIT_STAT(stat_CatchupInRuleCheckerP4Hit); 10794 10795 BCE_PRINTF( 10796 "----------------------------" 10797 "----------------" 10798 "----------------------------\n"); 10799} 10800 10801 10802/****************************************************************************/ 10803/* Prints out a summary of the driver state. */ 10804/* */ 10805/* Returns: */ 10806/* Nothing. */ 10807/****************************************************************************/ 10808static __attribute__ ((noinline)) void 10809bce_dump_driver_state(struct bce_softc *sc) 10810{ 10811 u32 val_hi, val_lo; 10812 10813 BCE_PRINTF( 10814 "-----------------------------" 10815 " Driver State " 10816 "-----------------------------\n"); 10817 10818 val_hi = BCE_ADDR_HI(sc); 10819 val_lo = BCE_ADDR_LO(sc); 10820 BCE_PRINTF("0x%08X:%08X - (sc) driver softc structure virtual " 10821 "address\n", val_hi, val_lo); 10822 10823 val_hi = BCE_ADDR_HI(sc->bce_vhandle); 10824 val_lo = BCE_ADDR_LO(sc->bce_vhandle); 10825 BCE_PRINTF("0x%08X:%08X - (sc->bce_vhandle) PCI BAR virtual " 10826 "address\n", val_hi, val_lo); 10827 10828 val_hi = BCE_ADDR_HI(sc->status_block); 10829 val_lo = BCE_ADDR_LO(sc->status_block); 10830 BCE_PRINTF("0x%08X:%08X - (sc->status_block) status block " 10831 "virtual address\n", val_hi, val_lo); 10832 10833 val_hi = BCE_ADDR_HI(sc->stats_block); 10834 val_lo = BCE_ADDR_LO(sc->stats_block); 10835 BCE_PRINTF("0x%08X:%08X - (sc->stats_block) statistics block " 10836 "virtual address\n", val_hi, val_lo); 10837 10838 val_hi = BCE_ADDR_HI(sc->tx_bd_chain); 10839 val_lo = BCE_ADDR_LO(sc->tx_bd_chain); 10840 BCE_PRINTF("0x%08X:%08X - (sc->tx_bd_chain) tx_bd chain " 10841 "virtual adddress\n", val_hi, val_lo); 10842 10843 val_hi = BCE_ADDR_HI(sc->rx_bd_chain); 10844 val_lo = BCE_ADDR_LO(sc->rx_bd_chain); 10845 BCE_PRINTF("0x%08X:%08X - (sc->rx_bd_chain) rx_bd chain " 10846 "virtual address\n", val_hi, val_lo); 10847 10848 if (bce_hdr_split == TRUE) { 10849 val_hi = BCE_ADDR_HI(sc->pg_bd_chain); 10850 val_lo = BCE_ADDR_LO(sc->pg_bd_chain); 10851 BCE_PRINTF("0x%08X:%08X - (sc->pg_bd_chain) page chain " 10852 "virtual address\n", val_hi, val_lo); 10853 } 10854 10855 val_hi = BCE_ADDR_HI(sc->tx_mbuf_ptr); 10856 val_lo = BCE_ADDR_LO(sc->tx_mbuf_ptr); 10857 BCE_PRINTF("0x%08X:%08X - (sc->tx_mbuf_ptr) tx mbuf chain " 10858 "virtual address\n", val_hi, val_lo); 10859 10860 val_hi = BCE_ADDR_HI(sc->rx_mbuf_ptr); 10861 val_lo = BCE_ADDR_LO(sc->rx_mbuf_ptr); 10862 BCE_PRINTF("0x%08X:%08X - (sc->rx_mbuf_ptr) rx mbuf chain " 10863 "virtual address\n", val_hi, val_lo); 10864 10865 if (bce_hdr_split == TRUE) { 10866 val_hi = BCE_ADDR_HI(sc->pg_mbuf_ptr); 10867 val_lo = BCE_ADDR_LO(sc->pg_mbuf_ptr); 10868 BCE_PRINTF("0x%08X:%08X - (sc->pg_mbuf_ptr) page mbuf chain " 10869 "virtual address\n", val_hi, val_lo); 10870 } 10871 10872 BCE_PRINTF(" 0x%016llX - (sc->interrupts_generated) " 10873 "h/w intrs\n", 10874 (long long unsigned int) sc->interrupts_generated); 10875 10876 BCE_PRINTF(" 0x%016llX - (sc->interrupts_rx) " 10877 "rx interrupts handled\n", 10878 (long long unsigned int) sc->interrupts_rx); 10879 10880 BCE_PRINTF(" 0x%016llX - (sc->interrupts_tx) " 10881 "tx interrupts handled\n", 10882 (long long unsigned int) sc->interrupts_tx); 10883 10884 BCE_PRINTF(" 0x%016llX - (sc->phy_interrupts) " 10885 "phy interrupts handled\n", 10886 (long long unsigned int) sc->phy_interrupts); 10887 10888 BCE_PRINTF(" 0x%08X - (sc->last_status_idx) " 10889 "status block index\n", sc->last_status_idx); 10890 10891 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->tx_prod) tx producer " 10892 "index\n", sc->tx_prod, (u16) TX_CHAIN_IDX(sc->tx_prod)); 10893 10894 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->tx_cons) tx consumer " 10895 "index\n", sc->tx_cons, (u16) TX_CHAIN_IDX(sc->tx_cons)); 10896 10897 BCE_PRINTF(" 0x%08X - (sc->tx_prod_bseq) tx producer " 10898 "byte seq index\n", sc->tx_prod_bseq); 10899 10900 BCE_PRINTF(" 0x%08X - (sc->debug_tx_mbuf_alloc) tx " 10901 "mbufs allocated\n", sc->debug_tx_mbuf_alloc); 10902 10903 BCE_PRINTF(" 0x%08X - (sc->used_tx_bd) used " 10904 "tx_bd's\n", sc->used_tx_bd); 10905 10906 BCE_PRINTF(" 0x%04X/0x%04X - (sc->tx_hi_watermark)/" 10907 "(sc->max_tx_bd)\n", sc->tx_hi_watermark, sc->max_tx_bd); 10908 10909 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->rx_prod) rx producer " 10910 "index\n", sc->rx_prod, (u16) RX_CHAIN_IDX(sc->rx_prod)); 10911 10912 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->rx_cons) rx consumer " 10913 "index\n", sc->rx_cons, (u16) RX_CHAIN_IDX(sc->rx_cons)); 10914 10915 BCE_PRINTF(" 0x%08X - (sc->rx_prod_bseq) rx producer " 10916 "byte seq index\n", sc->rx_prod_bseq); 10917 10918 BCE_PRINTF(" 0x%04X/0x%04X - (sc->rx_low_watermark)/" 10919 "(sc->max_rx_bd)\n", sc->rx_low_watermark, sc->max_rx_bd); 10920 10921 BCE_PRINTF(" 0x%08X - (sc->debug_rx_mbuf_alloc) rx " 10922 "mbufs allocated\n", sc->debug_rx_mbuf_alloc); 10923 10924 BCE_PRINTF(" 0x%08X - (sc->free_rx_bd) free " 10925 "rx_bd's\n", sc->free_rx_bd); 10926 10927 if (bce_hdr_split == TRUE) { 10928 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->pg_prod) page producer " 10929 "index\n", sc->pg_prod, (u16) PG_CHAIN_IDX(sc->pg_prod)); 10930 10931 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->pg_cons) page consumer " 10932 "index\n", sc->pg_cons, (u16) PG_CHAIN_IDX(sc->pg_cons)); 10933 10934 BCE_PRINTF(" 0x%08X - (sc->debug_pg_mbuf_alloc) page " 10935 "mbufs allocated\n", sc->debug_pg_mbuf_alloc); 10936 } 10937 10938 BCE_PRINTF(" 0x%08X - (sc->free_pg_bd) free page " 10939 "rx_bd's\n", sc->free_pg_bd); 10940 10941 BCE_PRINTF(" 0x%04X/0x%04X - (sc->pg_low_watermark)/" 10942 "(sc->max_pg_bd)\n", sc->pg_low_watermark, sc->max_pg_bd); 10943 10944 BCE_PRINTF(" 0x%08X - (sc->mbuf_alloc_failed_count) " 10945 "mbuf alloc failures\n", sc->mbuf_alloc_failed_count); 10946 10947 BCE_PRINTF(" 0x%08X - (sc->bce_flags) " 10948 "bce mac flags\n", sc->bce_flags); 10949 10950 BCE_PRINTF(" 0x%08X - (sc->bce_phy_flags) " 10951 "bce phy flags\n", sc->bce_phy_flags); 10952 10953 BCE_PRINTF( 10954 "----------------------------" 10955 "----------------" 10956 "----------------------------\n"); 10957} 10958 10959 10960/****************************************************************************/ 10961/* Prints out the hardware state through a summary of important register, */ 10962/* followed by a complete register dump. */ 10963/* */ 10964/* Returns: */ 10965/* Nothing. */ 10966/****************************************************************************/ 10967static __attribute__ ((noinline)) void 10968bce_dump_hw_state(struct bce_softc *sc) 10969{ 10970 u32 val; 10971 10972 BCE_PRINTF( 10973 "----------------------------" 10974 " Hardware State " 10975 "----------------------------\n"); 10976 10977 BCE_PRINTF("%s - bootcode version\n", sc->bce_bc_ver); 10978 10979 val = REG_RD(sc, BCE_MISC_ENABLE_STATUS_BITS); 10980 BCE_PRINTF("0x%08X - (0x%06X) misc_enable_status_bits\n", 10981 val, BCE_MISC_ENABLE_STATUS_BITS); 10982 10983 val = REG_RD(sc, BCE_DMA_STATUS); 10984 BCE_PRINTF("0x%08X - (0x%06X) dma_status\n", 10985 val, BCE_DMA_STATUS); 10986 10987 val = REG_RD(sc, BCE_CTX_STATUS); 10988 BCE_PRINTF("0x%08X - (0x%06X) ctx_status\n", 10989 val, BCE_CTX_STATUS); 10990 10991 val = REG_RD(sc, BCE_EMAC_STATUS); 10992 BCE_PRINTF("0x%08X - (0x%06X) emac_status\n", 10993 val, BCE_EMAC_STATUS); 10994 10995 val = REG_RD(sc, BCE_RPM_STATUS); 10996 BCE_PRINTF("0x%08X - (0x%06X) rpm_status\n", 10997 val, BCE_RPM_STATUS); 10998 10999 /* ToDo: Create a #define for this constant. */ 11000 val = REG_RD(sc, 0x2004); 11001 BCE_PRINTF("0x%08X - (0x%06X) rlup_status\n", 11002 val, 0x2004); 11003 11004 val = REG_RD(sc, BCE_RV2P_STATUS); 11005 BCE_PRINTF("0x%08X - (0x%06X) rv2p_status\n", 11006 val, BCE_RV2P_STATUS); 11007 11008 /* ToDo: Create a #define for this constant. */ 11009 val = REG_RD(sc, 0x2c04); 11010 BCE_PRINTF("0x%08X - (0x%06X) rdma_status\n", 11011 val, 0x2c04); 11012 11013 val = REG_RD(sc, BCE_TBDR_STATUS); 11014 BCE_PRINTF("0x%08X - (0x%06X) tbdr_status\n", 11015 val, BCE_TBDR_STATUS); 11016 11017 val = REG_RD(sc, BCE_TDMA_STATUS); 11018 BCE_PRINTF("0x%08X - (0x%06X) tdma_status\n", 11019 val, BCE_TDMA_STATUS); 11020 11021 val = REG_RD(sc, BCE_HC_STATUS); 11022 BCE_PRINTF("0x%08X - (0x%06X) hc_status\n", 11023 val, BCE_HC_STATUS); 11024 11025 val = REG_RD_IND(sc, BCE_TXP_CPU_STATE); 11026 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n", 11027 val, BCE_TXP_CPU_STATE); 11028 11029 val = REG_RD_IND(sc, BCE_TPAT_CPU_STATE); 11030 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n", 11031 val, BCE_TPAT_CPU_STATE); 11032 11033 val = REG_RD_IND(sc, BCE_RXP_CPU_STATE); 11034 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n", 11035 val, BCE_RXP_CPU_STATE); 11036 11037 val = REG_RD_IND(sc, BCE_COM_CPU_STATE); 11038 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n", 11039 val, BCE_COM_CPU_STATE); 11040 11041 val = REG_RD_IND(sc, BCE_MCP_CPU_STATE); 11042 BCE_PRINTF("0x%08X - (0x%06X) mcp_cpu_state\n", 11043 val, BCE_MCP_CPU_STATE); 11044 11045 val = REG_RD_IND(sc, BCE_CP_CPU_STATE); 11046 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n", 11047 val, BCE_CP_CPU_STATE); 11048 11049 BCE_PRINTF( 11050 "----------------------------" 11051 "----------------" 11052 "----------------------------\n"); 11053 11054 BCE_PRINTF( 11055 "----------------------------" 11056 " Register Dump " 11057 "----------------------------\n"); 11058 11059 for (int i = 0x400; i < 0x8000; i += 0x10) { 11060 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 11061 i, REG_RD(sc, i), REG_RD(sc, i + 0x4), 11062 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC)); 11063 } 11064 11065 BCE_PRINTF( 11066 "----------------------------" 11067 "----------------" 11068 "----------------------------\n"); 11069} 11070 11071 11072/****************************************************************************/ 11073/* Prints out the contentst of shared memory which is used for host driver */ 11074/* to bootcode firmware communication. */ 11075/* */ 11076/* Returns: */ 11077/* Nothing. */ 11078/****************************************************************************/ 11079static __attribute__ ((noinline)) void 11080bce_dump_shmem_state(struct bce_softc *sc) 11081{ 11082 BCE_PRINTF( 11083 "----------------------------" 11084 " Hardware State " 11085 "----------------------------\n"); 11086 11087 BCE_PRINTF("0x%08X - Shared memory base address\n", 11088 sc->bce_shmem_base); 11089 BCE_PRINTF("%s - bootcode version\n", 11090 sc->bce_bc_ver); 11091 11092 BCE_PRINTF( 11093 "----------------------------" 11094 " Shared Mem " 11095 "----------------------------\n"); 11096 11097 for (int i = 0x0; i < 0x200; i += 0x10) { 11098 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 11099 i, bce_shmem_rd(sc, i), bce_shmem_rd(sc, i + 0x4), 11100 bce_shmem_rd(sc, i + 0x8), bce_shmem_rd(sc, i + 0xC)); 11101 } 11102 11103 BCE_PRINTF( 11104 "----------------------------" 11105 "----------------" 11106 "----------------------------\n"); 11107} 11108 11109 11110/****************************************************************************/ 11111/* Prints out the mailbox queue registers. */ 11112/* */ 11113/* Returns: */ 11114/* Nothing. */ 11115/****************************************************************************/ 11116static __attribute__ ((noinline)) void 11117bce_dump_mq_regs(struct bce_softc *sc) 11118{ 11119 BCE_PRINTF( 11120 "----------------------------" 11121 " MQ Regs " 11122 "----------------------------\n"); 11123 11124 BCE_PRINTF( 11125 "----------------------------" 11126 "----------------" 11127 "----------------------------\n"); 11128 11129 for (int i = 0x3c00; i < 0x4000; i += 0x10) { 11130 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 11131 i, REG_RD(sc, i), REG_RD(sc, i + 0x4), 11132 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC)); 11133 } 11134 11135 BCE_PRINTF( 11136 "----------------------------" 11137 "----------------" 11138 "----------------------------\n"); 11139} 11140 11141 11142/****************************************************************************/ 11143/* Prints out the bootcode state. */ 11144/* */ 11145/* Returns: */ 11146/* Nothing. */ 11147/****************************************************************************/ 11148static __attribute__ ((noinline)) void 11149bce_dump_bc_state(struct bce_softc *sc) 11150{ 11151 u32 val; 11152 11153 BCE_PRINTF( 11154 "----------------------------" 11155 " Bootcode State " 11156 "----------------------------\n"); 11157 11158 BCE_PRINTF("%s - bootcode version\n", sc->bce_bc_ver); 11159 11160 val = bce_shmem_rd(sc, BCE_BC_RESET_TYPE); 11161 BCE_PRINTF("0x%08X - (0x%06X) reset_type\n", 11162 val, BCE_BC_RESET_TYPE); 11163 11164 val = bce_shmem_rd(sc, BCE_BC_STATE); 11165 BCE_PRINTF("0x%08X - (0x%06X) state\n", 11166 val, BCE_BC_STATE); 11167 11168 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); 11169 BCE_PRINTF("0x%08X - (0x%06X) condition\n", 11170 val, BCE_BC_STATE_CONDITION); 11171 11172 val = bce_shmem_rd(sc, BCE_BC_STATE_DEBUG_CMD); 11173 BCE_PRINTF("0x%08X - (0x%06X) debug_cmd\n", 11174 val, BCE_BC_STATE_DEBUG_CMD); 11175 11176 BCE_PRINTF( 11177 "----------------------------" 11178 "----------------" 11179 "----------------------------\n"); 11180} 11181 11182 11183/****************************************************************************/ 11184/* Prints out the TXP processor state. */ 11185/* */ 11186/* Returns: */ 11187/* Nothing. */ 11188/****************************************************************************/ 11189static __attribute__ ((noinline)) void 11190bce_dump_txp_state(struct bce_softc *sc, int regs) 11191{ 11192 u32 val; 11193 u32 fw_version[3]; 11194 11195 BCE_PRINTF( 11196 "----------------------------" 11197 " TXP State " 11198 "----------------------------\n"); 11199 11200 for (int i = 0; i < 3; i++) 11201 fw_version[i] = htonl(REG_RD_IND(sc, 11202 (BCE_TXP_SCRATCH + 0x10 + i * 4))); 11203 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 11204 11205 val = REG_RD_IND(sc, BCE_TXP_CPU_MODE); 11206 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_mode\n", 11207 val, BCE_TXP_CPU_MODE); 11208 11209 val = REG_RD_IND(sc, BCE_TXP_CPU_STATE); 11210 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n", 11211 val, BCE_TXP_CPU_STATE); 11212 11213 val = REG_RD_IND(sc, BCE_TXP_CPU_EVENT_MASK); 11214 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_event_mask\n", 11215 val, BCE_TXP_CPU_EVENT_MASK); 11216 11217 if (regs) { 11218 BCE_PRINTF( 11219 "----------------------------" 11220 " Register Dump " 11221 "----------------------------\n"); 11222 11223 for (int i = BCE_TXP_CPU_MODE; i < 0x68000; i += 0x10) { 11224 /* Skip the big blank spaces */ 11225 if (i < 0x454000 && i > 0x5ffff) 11226 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 11227 "0x%08X 0x%08X\n", i, 11228 REG_RD_IND(sc, i), 11229 REG_RD_IND(sc, i + 0x4), 11230 REG_RD_IND(sc, i + 0x8), 11231 REG_RD_IND(sc, i + 0xC)); 11232 } 11233 } 11234 11235 BCE_PRINTF( 11236 "----------------------------" 11237 "----------------" 11238 "----------------------------\n"); 11239} 11240 11241 11242/****************************************************************************/ 11243/* Prints out the RXP processor state. */ 11244/* */ 11245/* Returns: */ 11246/* Nothing. */ 11247/****************************************************************************/ 11248static __attribute__ ((noinline)) void 11249bce_dump_rxp_state(struct bce_softc *sc, int regs) 11250{ 11251 u32 val; 11252 u32 fw_version[3]; 11253 11254 BCE_PRINTF( 11255 "----------------------------" 11256 " RXP State " 11257 "----------------------------\n"); 11258 11259 for (int i = 0; i < 3; i++) 11260 fw_version[i] = htonl(REG_RD_IND(sc, 11261 (BCE_RXP_SCRATCH + 0x10 + i * 4))); 11262 11263 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 11264 11265 val = REG_RD_IND(sc, BCE_RXP_CPU_MODE); 11266 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_mode\n", 11267 val, BCE_RXP_CPU_MODE); 11268 11269 val = REG_RD_IND(sc, BCE_RXP_CPU_STATE); 11270 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n", 11271 val, BCE_RXP_CPU_STATE); 11272 11273 val = REG_RD_IND(sc, BCE_RXP_CPU_EVENT_MASK); 11274 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_event_mask\n", 11275 val, BCE_RXP_CPU_EVENT_MASK); 11276 11277 if (regs) { 11278 BCE_PRINTF( 11279 "----------------------------" 11280 " Register Dump " 11281 "----------------------------\n"); 11282 11283 for (int i = BCE_RXP_CPU_MODE; i < 0xe8fff; i += 0x10) { 11284 /* Skip the big blank sapces */ 11285 if (i < 0xc5400 && i > 0xdffff) 11286 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 11287 "0x%08X 0x%08X\n", i, 11288 REG_RD_IND(sc, i), 11289 REG_RD_IND(sc, i + 0x4), 11290 REG_RD_IND(sc, i + 0x8), 11291 REG_RD_IND(sc, i + 0xC)); 11292 } 11293 } 11294 11295 BCE_PRINTF( 11296 "----------------------------" 11297 "----------------" 11298 "----------------------------\n"); 11299} 11300 11301 11302/****************************************************************************/ 11303/* Prints out the TPAT processor state. */ 11304/* */ 11305/* Returns: */ 11306/* Nothing. */ 11307/****************************************************************************/ 11308static __attribute__ ((noinline)) void 11309bce_dump_tpat_state(struct bce_softc *sc, int regs) 11310{ 11311 u32 val; 11312 u32 fw_version[3]; 11313 11314 BCE_PRINTF( 11315 "----------------------------" 11316 " TPAT State " 11317 "----------------------------\n"); 11318 11319 for (int i = 0; i < 3; i++) 11320 fw_version[i] = htonl(REG_RD_IND(sc, 11321 (BCE_TPAT_SCRATCH + 0x410 + i * 4))); 11322 11323 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 11324 11325 val = REG_RD_IND(sc, BCE_TPAT_CPU_MODE); 11326 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_mode\n", 11327 val, BCE_TPAT_CPU_MODE); 11328 11329 val = REG_RD_IND(sc, BCE_TPAT_CPU_STATE); 11330 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n", 11331 val, BCE_TPAT_CPU_STATE); 11332 11333 val = REG_RD_IND(sc, BCE_TPAT_CPU_EVENT_MASK); 11334 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_event_mask\n", 11335 val, BCE_TPAT_CPU_EVENT_MASK); 11336 11337 if (regs) { 11338 BCE_PRINTF( 11339 "----------------------------" 11340 " Register Dump " 11341 "----------------------------\n"); 11342 11343 for (int i = BCE_TPAT_CPU_MODE; i < 0xa3fff; i += 0x10) { 11344 /* Skip the big blank spaces */ 11345 if (i < 0x854000 && i > 0x9ffff) 11346 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 11347 "0x%08X 0x%08X\n", i, 11348 REG_RD_IND(sc, i), 11349 REG_RD_IND(sc, i + 0x4), 11350 REG_RD_IND(sc, i + 0x8), 11351 REG_RD_IND(sc, i + 0xC)); 11352 } 11353 } 11354 11355 BCE_PRINTF( 11356 "----------------------------" 11357 "----------------" 11358 "----------------------------\n"); 11359} 11360 11361 11362/****************************************************************************/ 11363/* Prints out the Command Procesor (CP) state. */ 11364/* */ 11365/* Returns: */ 11366/* Nothing. */ 11367/****************************************************************************/ 11368static __attribute__ ((noinline)) void 11369bce_dump_cp_state(struct bce_softc *sc, int regs) 11370{ 11371 u32 val; 11372 u32 fw_version[3]; 11373 11374 BCE_PRINTF( 11375 "----------------------------" 11376 " CP State " 11377 "----------------------------\n"); 11378 11379 for (int i = 0; i < 3; i++) 11380 fw_version[i] = htonl(REG_RD_IND(sc, 11381 (BCE_CP_SCRATCH + 0x10 + i * 4))); 11382 11383 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 11384 11385 val = REG_RD_IND(sc, BCE_CP_CPU_MODE); 11386 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_mode\n", 11387 val, BCE_CP_CPU_MODE); 11388 11389 val = REG_RD_IND(sc, BCE_CP_CPU_STATE); 11390 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n", 11391 val, BCE_CP_CPU_STATE); 11392 11393 val = REG_RD_IND(sc, BCE_CP_CPU_EVENT_MASK); 11394 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_event_mask\n", val, 11395 BCE_CP_CPU_EVENT_MASK); 11396 11397 if (regs) { 11398 BCE_PRINTF( 11399 "----------------------------" 11400 " Register Dump " 11401 "----------------------------\n"); 11402 11403 for (int i = BCE_CP_CPU_MODE; i < 0x1aa000; i += 0x10) { 11404 /* Skip the big blank spaces */ 11405 if (i < 0x185400 && i > 0x19ffff) 11406 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 11407 "0x%08X 0x%08X\n", i, 11408 REG_RD_IND(sc, i), 11409 REG_RD_IND(sc, i + 0x4), 11410 REG_RD_IND(sc, i + 0x8), 11411 REG_RD_IND(sc, i + 0xC)); 11412 } 11413 } 11414 11415 BCE_PRINTF( 11416 "----------------------------" 11417 "----------------" 11418 "----------------------------\n"); 11419} 11420 11421 11422/****************************************************************************/ 11423/* Prints out the Completion Procesor (COM) state. */ 11424/* */ 11425/* Returns: */ 11426/* Nothing. */ 11427/****************************************************************************/ 11428static __attribute__ ((noinline)) void 11429bce_dump_com_state(struct bce_softc *sc, int regs) 11430{ 11431 u32 val; 11432 u32 fw_version[4]; 11433 11434 BCE_PRINTF( 11435 "----------------------------" 11436 " COM State " 11437 "----------------------------\n"); 11438 11439 for (int i = 0; i < 3; i++) 11440 fw_version[i] = htonl(REG_RD_IND(sc, 11441 (BCE_COM_SCRATCH + 0x10 + i * 4))); 11442 11443 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 11444 11445 val = REG_RD_IND(sc, BCE_COM_CPU_MODE); 11446 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_mode\n", 11447 val, BCE_COM_CPU_MODE); 11448 11449 val = REG_RD_IND(sc, BCE_COM_CPU_STATE); 11450 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n", 11451 val, BCE_COM_CPU_STATE); 11452 11453 val = REG_RD_IND(sc, BCE_COM_CPU_EVENT_MASK); 11454 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_event_mask\n", val, 11455 BCE_COM_CPU_EVENT_MASK); 11456 11457 if (regs) { 11458 BCE_PRINTF( 11459 "----------------------------" 11460 " Register Dump " 11461 "----------------------------\n"); 11462 11463 for (int i = BCE_COM_CPU_MODE; i < 0x1053e8; i += 0x10) { 11464 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 11465 "0x%08X 0x%08X\n", i, 11466 REG_RD_IND(sc, i), 11467 REG_RD_IND(sc, i + 0x4), 11468 REG_RD_IND(sc, i + 0x8), 11469 REG_RD_IND(sc, i + 0xC)); 11470 } 11471 } 11472 11473 BCE_PRINTF( 11474 "----------------------------" 11475 "----------------" 11476 "----------------------------\n"); 11477} 11478 11479 11480/****************************************************************************/ 11481/* Prints out the Receive Virtual 2 Physical (RV2P) state. */ 11482/* */ 11483/* Returns: */ 11484/* Nothing. */ 11485/****************************************************************************/ 11486static __attribute__ ((noinline)) void 11487bce_dump_rv2p_state(struct bce_softc *sc) 11488{ 11489 u32 val, pc1, pc2, fw_ver_high, fw_ver_low; 11490 11491 BCE_PRINTF( 11492 "----------------------------" 11493 " RV2P State " 11494 "----------------------------\n"); 11495 11496 /* Stall the RV2P processors. */ 11497 val = REG_RD_IND(sc, BCE_RV2P_CONFIG); 11498 val |= BCE_RV2P_CONFIG_STALL_PROC1 | BCE_RV2P_CONFIG_STALL_PROC2; 11499 REG_WR_IND(sc, BCE_RV2P_CONFIG, val); 11500 11501 /* Read the firmware version. */ 11502 val = 0x00000001; 11503 REG_WR_IND(sc, BCE_RV2P_PROC1_ADDR_CMD, val); 11504 fw_ver_low = REG_RD_IND(sc, BCE_RV2P_INSTR_LOW); 11505 fw_ver_high = REG_RD_IND(sc, BCE_RV2P_INSTR_HIGH) & 11506 BCE_RV2P_INSTR_HIGH_HIGH; 11507 BCE_PRINTF("RV2P1 Firmware version - 0x%08X:0x%08X\n", 11508 fw_ver_high, fw_ver_low); 11509 11510 val = 0x00000001; 11511 REG_WR_IND(sc, BCE_RV2P_PROC2_ADDR_CMD, val); 11512 fw_ver_low = REG_RD_IND(sc, BCE_RV2P_INSTR_LOW); 11513 fw_ver_high = REG_RD_IND(sc, BCE_RV2P_INSTR_HIGH) & 11514 BCE_RV2P_INSTR_HIGH_HIGH; 11515 BCE_PRINTF("RV2P2 Firmware version - 0x%08X:0x%08X\n", 11516 fw_ver_high, fw_ver_low); 11517 11518 /* Resume the RV2P processors. */ 11519 val = REG_RD_IND(sc, BCE_RV2P_CONFIG); 11520 val &= ~(BCE_RV2P_CONFIG_STALL_PROC1 | BCE_RV2P_CONFIG_STALL_PROC2); 11521 REG_WR_IND(sc, BCE_RV2P_CONFIG, val); 11522 11523 /* Fetch the program counter value. */ 11524 val = 0x68007800; 11525 REG_WR_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK, val); 11526 val = REG_RD_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK); 11527 pc1 = (val & BCE_RV2P_DEBUG_VECT_PEEK_1_VALUE); 11528 pc2 = (val & BCE_RV2P_DEBUG_VECT_PEEK_2_VALUE) >> 16; 11529 BCE_PRINTF("0x%08X - RV2P1 program counter (1st read)\n", pc1); 11530 BCE_PRINTF("0x%08X - RV2P2 program counter (1st read)\n", pc2); 11531 11532 /* Fetch the program counter value again to see if it is advancing. */ 11533 val = 0x68007800; 11534 REG_WR_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK, val); 11535 val = REG_RD_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK); 11536 pc1 = (val & BCE_RV2P_DEBUG_VECT_PEEK_1_VALUE); 11537 pc2 = (val & BCE_RV2P_DEBUG_VECT_PEEK_2_VALUE) >> 16; 11538 BCE_PRINTF("0x%08X - RV2P1 program counter (2nd read)\n", pc1); 11539 BCE_PRINTF("0x%08X - RV2P2 program counter (2nd read)\n", pc2); 11540 11541 BCE_PRINTF( 11542 "----------------------------" 11543 "----------------" 11544 "----------------------------\n"); 11545} 11546 11547 11548/****************************************************************************/ 11549/* Prints out the driver state and then enters the debugger. */ 11550/* */ 11551/* Returns: */ 11552/* Nothing. */ 11553/****************************************************************************/ 11554static __attribute__ ((noinline)) void 11555bce_breakpoint(struct bce_softc *sc) 11556{ 11557 11558 /* 11559 * Unreachable code to silence compiler warnings 11560 * about unused functions. 11561 */ 11562 if (0) { 11563 bce_freeze_controller(sc); 11564 bce_unfreeze_controller(sc); 11565 bce_dump_enet(sc, NULL); 11566 bce_dump_txbd(sc, 0, NULL); 11567 bce_dump_rxbd(sc, 0, NULL); 11568 bce_dump_tx_mbuf_chain(sc, 0, USABLE_TX_BD_ALLOC); 11569 bce_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD_ALLOC); 11570 bce_dump_pg_mbuf_chain(sc, 0, USABLE_PG_BD_ALLOC); 11571 bce_dump_l2fhdr(sc, 0, NULL); 11572 bce_dump_ctx(sc, RX_CID); 11573 bce_dump_ftqs(sc); 11574 bce_dump_tx_chain(sc, 0, USABLE_TX_BD_ALLOC); 11575 bce_dump_rx_bd_chain(sc, 0, USABLE_RX_BD_ALLOC); 11576 bce_dump_pg_chain(sc, 0, USABLE_PG_BD_ALLOC); 11577 bce_dump_status_block(sc); 11578 bce_dump_stats_block(sc); 11579 bce_dump_driver_state(sc); 11580 bce_dump_hw_state(sc); 11581 bce_dump_bc_state(sc); 11582 bce_dump_txp_state(sc, 0); 11583 bce_dump_rxp_state(sc, 0); 11584 bce_dump_tpat_state(sc, 0); 11585 bce_dump_cp_state(sc, 0); 11586 bce_dump_com_state(sc, 0); 11587 bce_dump_rv2p_state(sc); 11588 bce_dump_pgbd(sc, 0, NULL); 11589 } 11590 11591 bce_dump_status_block(sc); 11592 bce_dump_driver_state(sc); 11593 11594 /* Call the debugger. */ 11595 breakpoint(); 11596} 11597#endif 11598