if_bce.c revision 207761
1/*- 2 * Copyright (c) 2006-2010 Broadcom Corporation 3 * David Christensen <davidch@broadcom.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. Neither the name of Broadcom Corporation nor the name of its contributors 15 * may be used to endorse or promote products derived from this software 16 * without specific prior written consent. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 28 * THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#include <sys/cdefs.h> 32__FBSDID("$FreeBSD: head/sys/dev/bce/if_bce.c 207761 2010-05-07 22:09:17Z fabient $"); 33 34/* 35 * The following controllers are supported by this driver: 36 * BCM5706C A2, A3 37 * BCM5706S A2, A3 38 * BCM5708C B1, B2 39 * BCM5708S B1, B2 40 * BCM5709C A1, C0 41 * BCM5709S A1, C0 42 * BCM5716C C0 43 * BCM5716S C0 44 * 45 * The following controllers are not supported by this driver: 46 * BCM5706C A0, A1 (pre-production) 47 * BCM5706S A0, A1 (pre-production) 48 * BCM5708C A0, B0 (pre-production) 49 * BCM5708S A0, B0 (pre-production) 50 * BCM5709C A0 B0, B1, B2 (pre-production) 51 * BCM5709S A0, B0, B1, B2 (pre-production) 52 */ 53 54#include "opt_bce.h" 55 56#include <dev/bce/if_bcereg.h> 57#include <dev/bce/if_bcefw.h> 58 59/****************************************************************************/ 60/* BCE Debug Options */ 61/****************************************************************************/ 62#ifdef BCE_DEBUG 63 u32 bce_debug = BCE_WARN; 64 65 /* 0 = Never */ 66 /* 1 = 1 in 2,147,483,648 */ 67 /* 256 = 1 in 8,388,608 */ 68 /* 2048 = 1 in 1,048,576 */ 69 /* 65536 = 1 in 32,768 */ 70 /* 1048576 = 1 in 2,048 */ 71 /* 268435456 = 1 in 8 */ 72 /* 536870912 = 1 in 4 */ 73 /* 1073741824 = 1 in 2 */ 74 75 /* Controls how often the l2_fhdr frame error check will fail. */ 76 int l2fhdr_error_sim_control = 0; 77 78 /* Controls how often the unexpected attention check will fail. */ 79 int unexpected_attention_sim_control = 0; 80 81 /* Controls how often to simulate an mbuf allocation failure. */ 82 int mbuf_alloc_failed_sim_control = 0; 83 84 /* Controls how often to simulate a DMA mapping failure. */ 85 int dma_map_addr_failed_sim_control = 0; 86 87 /* Controls how often to simulate a bootcode failure. */ 88 int bootcode_running_failure_sim_control = 0; 89#endif 90 91/****************************************************************************/ 92/* BCE Build Time Options */ 93/****************************************************************************/ 94/* #define BCE_NVRAM_WRITE_SUPPORT 1 */ 95 96 97/****************************************************************************/ 98/* PCI Device ID Table */ 99/* */ 100/* Used by bce_probe() to identify the devices supported by this driver. */ 101/****************************************************************************/ 102#define BCE_DEVDESC_MAX 64 103 104static struct bce_type bce_devs[] = { 105 /* BCM5706C Controllers and OEM boards. */ 106 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3101, 107 "HP NC370T Multifunction Gigabit Server Adapter" }, 108 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3106, 109 "HP NC370i Multifunction Gigabit Server Adapter" }, 110 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3070, 111 "HP NC380T PCIe DP Multifunc Gig Server Adapter" }, 112 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x1709, 113 "HP NC371i Multifunction Gigabit Server Adapter" }, 114 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, PCI_ANY_ID, PCI_ANY_ID, 115 "Broadcom NetXtreme II BCM5706 1000Base-T" }, 116 117 /* BCM5706S controllers and OEM boards. */ 118 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, HP_VENDORID, 0x3102, 119 "HP NC370F Multifunction Gigabit Server Adapter" }, 120 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, PCI_ANY_ID, PCI_ANY_ID, 121 "Broadcom NetXtreme II BCM5706 1000Base-SX" }, 122 123 /* BCM5708C controllers and OEM boards. */ 124 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7037, 125 "HP NC373T PCIe Multifunction Gig Server Adapter" }, 126 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7038, 127 "HP NC373i Multifunction Gigabit Server Adapter" }, 128 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7045, 129 "HP NC374m PCIe Multifunction Adapter" }, 130 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, PCI_ANY_ID, PCI_ANY_ID, 131 "Broadcom NetXtreme II BCM5708 1000Base-T" }, 132 133 /* BCM5708S controllers and OEM boards. */ 134 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x1706, 135 "HP NC373m Multifunction Gigabit Server Adapter" }, 136 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x703b, 137 "HP NC373i Multifunction Gigabit Server Adapter" }, 138 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x703d, 139 "HP NC373F PCIe Multifunc Giga Server Adapter" }, 140 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, PCI_ANY_ID, PCI_ANY_ID, 141 "Broadcom NetXtreme II BCM5708 1000Base-SX" }, 142 143 /* BCM5709C controllers and OEM boards. */ 144 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, HP_VENDORID, 0x7055, 145 "HP NC382i DP Multifunction Gigabit Server Adapter" }, 146 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, HP_VENDORID, 0x7059, 147 "HP NC382T PCIe DP Multifunction Gigabit Server Adapter" }, 148 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, PCI_ANY_ID, PCI_ANY_ID, 149 "Broadcom NetXtreme II BCM5709 1000Base-T" }, 150 151 /* BCM5709S controllers and OEM boards. */ 152 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, HP_VENDORID, 0x171d, 153 "HP NC382m DP 1GbE Multifunction BL-c Adapter" }, 154 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, HP_VENDORID, 0x7056, 155 "HP NC382i DP Multifunction Gigabit Server Adapter" }, 156 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, PCI_ANY_ID, PCI_ANY_ID, 157 "Broadcom NetXtreme II BCM5709 1000Base-SX" }, 158 159 /* BCM5716 controllers and OEM boards. */ 160 { BRCM_VENDORID, BRCM_DEVICEID_BCM5716, PCI_ANY_ID, PCI_ANY_ID, 161 "Broadcom NetXtreme II BCM5716 1000Base-T" }, 162 163 { 0, 0, 0, 0, NULL } 164}; 165 166 167/****************************************************************************/ 168/* Supported Flash NVRAM device data. */ 169/****************************************************************************/ 170static struct flash_spec flash_table[] = 171{ 172#define BUFFERED_FLAGS (BCE_NV_BUFFERED | BCE_NV_TRANSLATE) 173#define NONBUFFERED_FLAGS (BCE_NV_WREN) 174 175 /* Slow EEPROM */ 176 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400, 177 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 178 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 179 "EEPROM - slow"}, 180 /* Expansion entry 0001 */ 181 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406, 182 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 183 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 184 "Entry 0001"}, 185 /* Saifun SA25F010 (non-buffered flash) */ 186 /* strap, cfg1, & write1 need updates */ 187 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406, 188 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 189 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2, 190 "Non-buffered flash (128kB)"}, 191 /* Saifun SA25F020 (non-buffered flash) */ 192 /* strap, cfg1, & write1 need updates */ 193 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406, 194 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 195 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4, 196 "Non-buffered flash (256kB)"}, 197 /* Expansion entry 0100 */ 198 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406, 199 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 200 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 201 "Entry 0100"}, 202 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */ 203 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406, 204 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 205 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2, 206 "Entry 0101: ST M45PE10 (128kB non-bufferred)"}, 207 /* Entry 0110: ST M45PE20 (non-buffered flash)*/ 208 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406, 209 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 210 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4, 211 "Entry 0110: ST M45PE20 (256kB non-bufferred)"}, 212 /* Saifun SA25F005 (non-buffered flash) */ 213 /* strap, cfg1, & write1 need updates */ 214 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406, 215 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 216 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE, 217 "Non-buffered flash (64kB)"}, 218 /* Fast EEPROM */ 219 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400, 220 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 221 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 222 "EEPROM - fast"}, 223 /* Expansion entry 1001 */ 224 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406, 225 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 226 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 227 "Entry 1001"}, 228 /* Expansion entry 1010 */ 229 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406, 230 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 231 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 232 "Entry 1010"}, 233 /* ATMEL AT45DB011B (buffered flash) */ 234 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400, 235 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 236 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE, 237 "Buffered flash (128kB)"}, 238 /* Expansion entry 1100 */ 239 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406, 240 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 241 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 242 "Entry 1100"}, 243 /* Expansion entry 1101 */ 244 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406, 245 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 246 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 247 "Entry 1101"}, 248 /* Ateml Expansion entry 1110 */ 249 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400, 250 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 251 BUFFERED_FLASH_BYTE_ADDR_MASK, 0, 252 "Entry 1110 (Atmel)"}, 253 /* ATMEL AT45DB021B (buffered flash) */ 254 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400, 255 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 256 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2, 257 "Buffered flash (256kB)"}, 258}; 259 260/* 261 * The BCM5709 controllers transparently handle the 262 * differences between Atmel 264 byte pages and all 263 * flash devices which use 256 byte pages, so no 264 * logical-to-physical mapping is required in the 265 * driver. 266 */ 267static struct flash_spec flash_5709 = { 268 .flags = BCE_NV_BUFFERED, 269 .page_bits = BCM5709_FLASH_PAGE_BITS, 270 .page_size = BCM5709_FLASH_PAGE_SIZE, 271 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK, 272 .total_size = BUFFERED_FLASH_TOTAL_SIZE * 2, 273 .name = "5709/5716 buffered flash (256kB)", 274}; 275 276 277/****************************************************************************/ 278/* FreeBSD device entry points. */ 279/****************************************************************************/ 280static int bce_probe (device_t); 281static int bce_attach (device_t); 282static int bce_detach (device_t); 283static int bce_shutdown (device_t); 284 285 286/****************************************************************************/ 287/* BCE Debug Data Structure Dump Routines */ 288/****************************************************************************/ 289#ifdef BCE_DEBUG 290static u32 bce_reg_rd (struct bce_softc *, u32); 291static void bce_reg_wr (struct bce_softc *, u32, u32); 292static void bce_reg_wr16 (struct bce_softc *, u32, u16); 293static u32 bce_ctx_rd (struct bce_softc *, u32, u32); 294static void bce_dump_enet (struct bce_softc *, struct mbuf *); 295static void bce_dump_mbuf (struct bce_softc *, struct mbuf *); 296static void bce_dump_tx_mbuf_chain (struct bce_softc *, u16, int); 297static void bce_dump_rx_mbuf_chain (struct bce_softc *, u16, int); 298#ifdef BCE_JUMBO_HDRSPLIT 299static void bce_dump_pg_mbuf_chain (struct bce_softc *, u16, int); 300#endif 301static void bce_dump_txbd (struct bce_softc *, 302 int, struct tx_bd *); 303static void bce_dump_rxbd (struct bce_softc *, 304 int, struct rx_bd *); 305#ifdef BCE_JUMBO_HDRSPLIT 306static void bce_dump_pgbd (struct bce_softc *, 307 int, struct rx_bd *); 308#endif 309static void bce_dump_l2fhdr (struct bce_softc *, 310 int, struct l2_fhdr *); 311static void bce_dump_ctx (struct bce_softc *, u16); 312static void bce_dump_ftqs (struct bce_softc *); 313static void bce_dump_tx_chain (struct bce_softc *, u16, int); 314static void bce_dump_rx_bd_chain (struct bce_softc *, u16, int); 315#ifdef BCE_JUMBO_HDRSPLIT 316static void bce_dump_pg_chain (struct bce_softc *, u16, int); 317#endif 318static void bce_dump_status_block (struct bce_softc *); 319static void bce_dump_stats_block (struct bce_softc *); 320static void bce_dump_driver_state (struct bce_softc *); 321static void bce_dump_hw_state (struct bce_softc *); 322static void bce_dump_mq_regs (struct bce_softc *); 323static void bce_dump_bc_state (struct bce_softc *); 324static void bce_dump_txp_state (struct bce_softc *, int); 325static void bce_dump_rxp_state (struct bce_softc *, int); 326static void bce_dump_tpat_state (struct bce_softc *, int); 327static void bce_dump_cp_state (struct bce_softc *, int); 328static void bce_dump_com_state (struct bce_softc *, int); 329static void bce_dump_rv2p_state (struct bce_softc *); 330static void bce_breakpoint (struct bce_softc *); 331#endif 332 333 334/****************************************************************************/ 335/* BCE Register/Memory Access Routines */ 336/****************************************************************************/ 337static u32 bce_reg_rd_ind (struct bce_softc *, u32); 338static void bce_reg_wr_ind (struct bce_softc *, u32, u32); 339static void bce_shmem_wr (struct bce_softc *, u32, u32); 340static u32 bce_shmem_rd (struct bce_softc *, u32); 341static void bce_ctx_wr (struct bce_softc *, u32, u32, u32); 342static int bce_miibus_read_reg (device_t, int, int); 343static int bce_miibus_write_reg (device_t, int, int, int); 344static void bce_miibus_statchg (device_t); 345 346 347/****************************************************************************/ 348/* BCE NVRAM Access Routines */ 349/****************************************************************************/ 350static int bce_acquire_nvram_lock (struct bce_softc *); 351static int bce_release_nvram_lock (struct bce_softc *); 352static void bce_enable_nvram_access (struct bce_softc *); 353static void bce_disable_nvram_access (struct bce_softc *); 354static int bce_nvram_read_dword (struct bce_softc *, u32, u8 *, u32); 355static int bce_init_nvram (struct bce_softc *); 356static int bce_nvram_read (struct bce_softc *, u32, u8 *, int); 357static int bce_nvram_test (struct bce_softc *); 358#ifdef BCE_NVRAM_WRITE_SUPPORT 359static int bce_enable_nvram_write (struct bce_softc *); 360static void bce_disable_nvram_write (struct bce_softc *); 361static int bce_nvram_erase_page (struct bce_softc *, u32); 362static int bce_nvram_write_dword (struct bce_softc *, u32, u8 *, u32); 363static int bce_nvram_write (struct bce_softc *, u32, u8 *, int); 364#endif 365 366/****************************************************************************/ 367/* */ 368/****************************************************************************/ 369static void bce_get_media (struct bce_softc *); 370static void bce_init_media (struct bce_softc *); 371static void bce_dma_map_addr (void *, 372 bus_dma_segment_t *, int, int); 373static int bce_dma_alloc (device_t); 374static void bce_dma_free (struct bce_softc *); 375static void bce_release_resources (struct bce_softc *); 376 377/****************************************************************************/ 378/* BCE Firmware Synchronization and Load */ 379/****************************************************************************/ 380static int bce_fw_sync (struct bce_softc *, u32); 381static void bce_load_rv2p_fw (struct bce_softc *, u32 *, u32, u32); 382static void bce_load_cpu_fw (struct bce_softc *, 383 struct cpu_reg *, struct fw_info *); 384static void bce_start_cpu (struct bce_softc *, struct cpu_reg *); 385static void bce_halt_cpu (struct bce_softc *, struct cpu_reg *); 386static void bce_start_rxp_cpu (struct bce_softc *); 387static void bce_init_rxp_cpu (struct bce_softc *); 388static void bce_init_txp_cpu (struct bce_softc *); 389static void bce_init_tpat_cpu (struct bce_softc *); 390static void bce_init_cp_cpu (struct bce_softc *); 391static void bce_init_com_cpu (struct bce_softc *); 392static void bce_init_cpus (struct bce_softc *); 393 394static void bce_print_adapter_info (struct bce_softc *); 395static void bce_probe_pci_caps (device_t, struct bce_softc *); 396static void bce_stop (struct bce_softc *); 397static int bce_reset (struct bce_softc *, u32); 398static int bce_chipinit (struct bce_softc *); 399static int bce_blockinit (struct bce_softc *); 400 401static int bce_init_tx_chain (struct bce_softc *); 402static void bce_free_tx_chain (struct bce_softc *); 403 404static int bce_get_rx_buf (struct bce_softc *, 405 struct mbuf *, u16 *, u16 *, u32 *); 406static int bce_init_rx_chain (struct bce_softc *); 407static void bce_fill_rx_chain (struct bce_softc *); 408static void bce_free_rx_chain (struct bce_softc *); 409 410#ifdef BCE_JUMBO_HDRSPLIT 411static int bce_get_pg_buf (struct bce_softc *, 412 struct mbuf *, u16 *, u16 *); 413static int bce_init_pg_chain (struct bce_softc *); 414static void bce_fill_pg_chain (struct bce_softc *); 415static void bce_free_pg_chain (struct bce_softc *); 416#endif 417 418static struct mbuf *bce_tso_setup (struct bce_softc *, 419 struct mbuf **, u16 *); 420static int bce_tx_encap (struct bce_softc *, struct mbuf **); 421static void bce_start_locked (struct ifnet *); 422static void bce_start (struct ifnet *); 423static int bce_ioctl (struct ifnet *, u_long, caddr_t); 424static void bce_watchdog (struct bce_softc *); 425static int bce_ifmedia_upd (struct ifnet *); 426static void bce_ifmedia_upd_locked (struct ifnet *); 427static void bce_ifmedia_sts (struct ifnet *, struct ifmediareq *); 428static void bce_init_locked (struct bce_softc *); 429static void bce_init (void *); 430static void bce_mgmt_init_locked (struct bce_softc *sc); 431 432static void bce_init_ctx (struct bce_softc *); 433static void bce_get_mac_addr (struct bce_softc *); 434static void bce_set_mac_addr (struct bce_softc *); 435static void bce_phy_intr (struct bce_softc *); 436static inline u16 bce_get_hw_rx_cons (struct bce_softc *); 437static void bce_rx_intr (struct bce_softc *); 438static void bce_tx_intr (struct bce_softc *); 439static void bce_disable_intr (struct bce_softc *); 440static void bce_enable_intr (struct bce_softc *, int); 441 442static void bce_intr (void *); 443static void bce_set_rx_mode (struct bce_softc *); 444static void bce_stats_update (struct bce_softc *); 445static void bce_tick (void *); 446static void bce_pulse (void *); 447static void bce_add_sysctls (struct bce_softc *); 448 449 450/****************************************************************************/ 451/* FreeBSD device dispatch table. */ 452/****************************************************************************/ 453static device_method_t bce_methods[] = { 454 /* Device interface (device_if.h) */ 455 DEVMETHOD(device_probe, bce_probe), 456 DEVMETHOD(device_attach, bce_attach), 457 DEVMETHOD(device_detach, bce_detach), 458 DEVMETHOD(device_shutdown, bce_shutdown), 459/* Supported by device interface but not used here. */ 460/* DEVMETHOD(device_identify, bce_identify), */ 461/* DEVMETHOD(device_suspend, bce_suspend), */ 462/* DEVMETHOD(device_resume, bce_resume), */ 463/* DEVMETHOD(device_quiesce, bce_quiesce), */ 464 465 /* Bus interface (bus_if.h) */ 466 DEVMETHOD(bus_print_child, bus_generic_print_child), 467 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 468 469 /* MII interface (miibus_if.h) */ 470 DEVMETHOD(miibus_readreg, bce_miibus_read_reg), 471 DEVMETHOD(miibus_writereg, bce_miibus_write_reg), 472 DEVMETHOD(miibus_statchg, bce_miibus_statchg), 473/* Supported by MII interface but not used here. */ 474/* DEVMETHOD(miibus_linkchg, bce_miibus_linkchg), */ 475/* DEVMETHOD(miibus_mediainit, bce_miibus_mediainit), */ 476 477 { 0, 0 } 478}; 479 480static driver_t bce_driver = { 481 "bce", 482 bce_methods, 483 sizeof(struct bce_softc) 484}; 485 486static devclass_t bce_devclass; 487 488MODULE_DEPEND(bce, pci, 1, 1, 1); 489MODULE_DEPEND(bce, ether, 1, 1, 1); 490MODULE_DEPEND(bce, miibus, 1, 1, 1); 491 492DRIVER_MODULE(bce, pci, bce_driver, bce_devclass, 0, 0); 493DRIVER_MODULE(miibus, bce, miibus_driver, miibus_devclass, 0, 0); 494 495 496/****************************************************************************/ 497/* Tunable device values */ 498/****************************************************************************/ 499SYSCTL_NODE(_hw, OID_AUTO, bce, CTLFLAG_RD, 0, "bce driver parameters"); 500 501/* Allowable values are TRUE or FALSE */ 502static int bce_tso_enable = TRUE; 503TUNABLE_INT("hw.bce.tso_enable", &bce_tso_enable); 504SYSCTL_UINT(_hw_bce, OID_AUTO, tso_enable, CTLFLAG_RDTUN, &bce_tso_enable, 0, 505"TSO Enable/Disable"); 506 507/* Allowable values are 0 (IRQ), 1 (MSI/IRQ), and 2 (MSI-X/MSI/IRQ) */ 508/* ToDo: Add MSI-X support. */ 509static int bce_msi_enable = 1; 510TUNABLE_INT("hw.bce.msi_enable", &bce_msi_enable); 511SYSCTL_UINT(_hw_bce, OID_AUTO, msi_enable, CTLFLAG_RDTUN, &bce_msi_enable, 0, 512"MSI-X|MSI|INTx selector"); 513 514/* ToDo: Add tunable to enable/disable strict MTU handling. */ 515/* Currently allows "loose" RX MTU checking (i.e. sets the */ 516/* H/W RX MTU to the size of the largest receive buffer, or */ 517/* 2048 bytes). This will cause a UNH failure but is more */ 518/* desireable from a functional perspective. */ 519 520 521/****************************************************************************/ 522/* Device probe function. */ 523/* */ 524/* Compares the device to the driver's list of supported devices and */ 525/* reports back to the OS whether this is the right driver for the device. */ 526/* */ 527/* Returns: */ 528/* BUS_PROBE_DEFAULT on success, positive value on failure. */ 529/****************************************************************************/ 530static int 531bce_probe(device_t dev) 532{ 533 struct bce_type *t; 534 struct bce_softc *sc; 535 char *descbuf; 536 u16 vid = 0, did = 0, svid = 0, sdid = 0; 537 538 t = bce_devs; 539 540 sc = device_get_softc(dev); 541 bzero(sc, sizeof(struct bce_softc)); 542 sc->bce_unit = device_get_unit(dev); 543 sc->bce_dev = dev; 544 545 /* Get the data for the device to be probed. */ 546 vid = pci_get_vendor(dev); 547 did = pci_get_device(dev); 548 svid = pci_get_subvendor(dev); 549 sdid = pci_get_subdevice(dev); 550 551 DBPRINT(sc, BCE_EXTREME_LOAD, 552 "%s(); VID = 0x%04X, DID = 0x%04X, SVID = 0x%04X, " 553 "SDID = 0x%04X\n", __FUNCTION__, vid, did, svid, sdid); 554 555 /* Look through the list of known devices for a match. */ 556 while(t->bce_name != NULL) { 557 558 if ((vid == t->bce_vid) && (did == t->bce_did) && 559 ((svid == t->bce_svid) || (t->bce_svid == PCI_ANY_ID)) && 560 ((sdid == t->bce_sdid) || (t->bce_sdid == PCI_ANY_ID))) { 561 562 descbuf = malloc(BCE_DEVDESC_MAX, M_TEMP, M_NOWAIT); 563 564 if (descbuf == NULL) 565 return(ENOMEM); 566 567 /* Print out the device identity. */ 568 snprintf(descbuf, BCE_DEVDESC_MAX, "%s (%c%d)", 569 t->bce_name, (((pci_read_config(dev, 570 PCIR_REVID, 4) & 0xf0) >> 4) + 'A'), 571 (pci_read_config(dev, PCIR_REVID, 4) & 0xf)); 572 573 device_set_desc_copy(dev, descbuf); 574 free(descbuf, M_TEMP); 575 return(BUS_PROBE_DEFAULT); 576 } 577 t++; 578 } 579 580 return(ENXIO); 581} 582 583 584/****************************************************************************/ 585/* PCI Capabilities Probe Function. */ 586/* */ 587/* Walks the PCI capabiites list for the device to find what features are */ 588/* supported. */ 589/* */ 590/* Returns: */ 591/* None. */ 592/****************************************************************************/ 593static void 594bce_print_adapter_info(struct bce_softc *sc) 595{ 596 int i = 0; 597 598 DBENTER(BCE_VERBOSE_LOAD); 599 600 if (bootverbose) { 601 BCE_PRINTF("ASIC (0x%08X); ", sc->bce_chipid); 602 printf("Rev (%c%d); ", ((BCE_CHIP_ID(sc) & 0xf000) >> 603 12) + 'A', ((BCE_CHIP_ID(sc) & 0x0ff0) >> 4)); 604 605 606 /* Bus info. */ 607 if (sc->bce_flags & BCE_PCIE_FLAG) { 608 printf("Bus (PCIe x%d, ", sc->link_width); 609 switch (sc->link_speed) { 610 case 1: printf("2.5Gbps); "); break; 611 case 2: printf("5Gbps); "); break; 612 default: printf("Unknown link speed); "); 613 } 614 } else { 615 printf("Bus (PCI%s, %s, %dMHz); ", 616 ((sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : ""), 617 ((sc->bce_flags & BCE_PCI_32BIT_FLAG) ? 618 "32-bit" : "64-bit"), sc->bus_speed_mhz); 619 } 620 621 /* Firmware version and device features. */ 622 printf("B/C (%s); Flags (", sc->bce_bc_ver); 623 624 #ifdef BCE_JUMBO_HDRSPLIT 625 printf("SPLT"); 626 i++; 627 #endif 628 629 if (sc->bce_flags & BCE_USING_MSI_FLAG) { 630 if (i > 0) printf("|"); 631 printf("MSI"); i++; 632 } 633 634 if (sc->bce_flags & BCE_USING_MSIX_FLAG) { 635 if (i > 0) printf("|"); 636 printf("MSI-X"); i++; 637 } 638 639 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) { 640 if (i > 0) printf("|"); 641 printf("2.5G"); i++; 642 } 643 644 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 645 if (i > 0) printf("|"); 646 printf("MFW); MFW (%s)\n", sc->bce_mfw_ver); 647 } else { 648 printf(")\n"); 649 } 650 } 651 652 DBEXIT(BCE_VERBOSE_LOAD); 653} 654 655 656/****************************************************************************/ 657/* PCI Capabilities Probe Function. */ 658/* */ 659/* Walks the PCI capabiites list for the device to find what features are */ 660/* supported. */ 661/* */ 662/* Returns: */ 663/* None. */ 664/****************************************************************************/ 665static void 666bce_probe_pci_caps(device_t dev, struct bce_softc *sc) 667{ 668 u32 reg; 669 670 DBENTER(BCE_VERBOSE_LOAD); 671 672 /* Check if PCI-X capability is enabled. */ 673 if (pci_find_extcap(dev, PCIY_PCIX, ®) == 0) { 674 if (reg != 0) 675 sc->bce_cap_flags |= BCE_PCIX_CAPABLE_FLAG; 676 } 677 678 /* Check if PCIe capability is enabled. */ 679 if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { 680 if (reg != 0) { 681 u16 link_status = pci_read_config(dev, reg + 0x12, 2); 682 DBPRINT(sc, BCE_INFO_LOAD, "PCIe link_status = " 683 "0x%08X\n", link_status); 684 sc->link_speed = link_status & 0xf; 685 sc->link_width = (link_status >> 4) & 0x3f; 686 sc->bce_cap_flags |= BCE_PCIE_CAPABLE_FLAG; 687 sc->bce_flags |= BCE_PCIE_FLAG; 688 } 689 } 690 691 /* Check if MSI capability is enabled. */ 692 if (pci_find_extcap(dev, PCIY_MSI, ®) == 0) { 693 if (reg != 0) 694 sc->bce_cap_flags |= BCE_MSI_CAPABLE_FLAG; 695 } 696 697 /* Check if MSI-X capability is enabled. */ 698 if (pci_find_extcap(dev, PCIY_MSIX, ®) == 0) { 699 if (reg != 0) 700 sc->bce_cap_flags |= BCE_MSIX_CAPABLE_FLAG; 701 } 702 703 DBEXIT(BCE_VERBOSE_LOAD); 704} 705 706 707/****************************************************************************/ 708/* Device attach function. */ 709/* */ 710/* Allocates device resources, performs secondary chip identification, */ 711/* resets and initializes the hardware, and initializes driver instance */ 712/* variables. */ 713/* */ 714/* Returns: */ 715/* 0 on success, positive value on failure. */ 716/****************************************************************************/ 717static int 718bce_attach(device_t dev) 719{ 720 struct bce_softc *sc; 721 struct ifnet *ifp; 722 u32 val; 723 int error, rid, rc = 0; 724 725 sc = device_get_softc(dev); 726 sc->bce_dev = dev; 727 728 DBENTER(BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 729 730 sc->bce_unit = device_get_unit(dev); 731 732 /* Set initial device and PHY flags */ 733 sc->bce_flags = 0; 734 sc->bce_phy_flags = 0; 735 736 pci_enable_busmaster(dev); 737 738 /* Allocate PCI memory resources. */ 739 rid = PCIR_BAR(0); 740 sc->bce_res_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 741 &rid, RF_ACTIVE); 742 743 if (sc->bce_res_mem == NULL) { 744 BCE_PRINTF("%s(%d): PCI memory allocation failed\n", 745 __FILE__, __LINE__); 746 rc = ENXIO; 747 goto bce_attach_fail; 748 } 749 750 /* Get various resource handles. */ 751 sc->bce_btag = rman_get_bustag(sc->bce_res_mem); 752 sc->bce_bhandle = rman_get_bushandle(sc->bce_res_mem); 753 sc->bce_vhandle = (vm_offset_t) rman_get_virtual(sc->bce_res_mem); 754 755 bce_probe_pci_caps(dev, sc); 756 757 rid = 1; 758#if 0 759 /* Try allocating MSI-X interrupts. */ 760 if ((sc->bce_cap_flags & BCE_MSIX_CAPABLE_FLAG) && 761 (bce_msi_enable >= 2) && 762 ((sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 763 &rid, RF_ACTIVE)) != NULL)) { 764 765 msi_needed = sc->bce_msi_count = 1; 766 767 if (((error = pci_alloc_msix(dev, &sc->bce_msi_count)) != 0) || 768 (sc->bce_msi_count != msi_needed)) { 769 BCE_PRINTF("%s(%d): MSI-X allocation failed! Requested = %d," 770 "Received = %d, error = %d\n", __FILE__, __LINE__, 771 msi_needed, sc->bce_msi_count, error); 772 sc->bce_msi_count = 0; 773 pci_release_msi(dev); 774 bus_release_resource(dev, SYS_RES_MEMORY, rid, 775 sc->bce_res_irq); 776 sc->bce_res_irq = NULL; 777 } else { 778 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using MSI-X interrupt.\n", 779 __FUNCTION__); 780 sc->bce_flags |= BCE_USING_MSIX_FLAG; 781 sc->bce_intr = bce_intr; 782 } 783 } 784#endif 785 786 /* Try allocating a MSI interrupt. */ 787 if ((sc->bce_cap_flags & BCE_MSI_CAPABLE_FLAG) && 788 (bce_msi_enable >= 1) && (sc->bce_msi_count == 0)) { 789 sc->bce_msi_count = 1; 790 if ((error = pci_alloc_msi(dev, &sc->bce_msi_count)) != 0) { 791 BCE_PRINTF("%s(%d): MSI allocation failed! " 792 "error = %d\n", __FILE__, __LINE__, error); 793 sc->bce_msi_count = 0; 794 pci_release_msi(dev); 795 } else { 796 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using MSI " 797 "interrupt.\n", __FUNCTION__); 798 sc->bce_flags |= BCE_USING_MSI_FLAG; 799 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 800 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) 801 sc->bce_flags |= BCE_ONE_SHOT_MSI_FLAG; 802 sc->bce_irq_rid = 1; 803 sc->bce_intr = bce_intr; 804 } 805 } 806 807 /* Try allocating a legacy interrupt. */ 808 if (sc->bce_msi_count == 0) { 809 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using INTx interrupt.\n", 810 __FUNCTION__); 811 rid = 0; 812 sc->bce_intr = bce_intr; 813 } 814 815 sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 816 &rid, RF_SHAREABLE | RF_ACTIVE); 817 818 sc->bce_irq_rid = rid; 819 820 /* Report any IRQ allocation errors. */ 821 if (sc->bce_res_irq == NULL) { 822 BCE_PRINTF("%s(%d): PCI map interrupt failed!\n", 823 __FILE__, __LINE__); 824 rc = ENXIO; 825 goto bce_attach_fail; 826 } 827 828 /* Initialize mutex for the current device instance. */ 829 BCE_LOCK_INIT(sc, device_get_nameunit(dev)); 830 831 /* 832 * Configure byte swap and enable indirect register access. 833 * Rely on CPU to do target byte swapping on big endian systems. 834 * Access to registers outside of PCI configurtion space are not 835 * valid until this is done. 836 */ 837 pci_write_config(dev, BCE_PCICFG_MISC_CONFIG, 838 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 839 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP, 4); 840 841 /* Save ASIC revsion info. */ 842 sc->bce_chipid = REG_RD(sc, BCE_MISC_ID); 843 844 /* Weed out any non-production controller revisions. */ 845 switch(BCE_CHIP_ID(sc)) { 846 case BCE_CHIP_ID_5706_A0: 847 case BCE_CHIP_ID_5706_A1: 848 case BCE_CHIP_ID_5708_A0: 849 case BCE_CHIP_ID_5708_B0: 850 case BCE_CHIP_ID_5709_A0: 851 case BCE_CHIP_ID_5709_B0: 852 case BCE_CHIP_ID_5709_B1: 853 case BCE_CHIP_ID_5709_B2: 854 BCE_PRINTF("%s(%d): Unsupported controller " 855 "revision (%c%d)!\n", __FILE__, __LINE__, 856 (((pci_read_config(dev, PCIR_REVID, 4) & 857 0xf0) >> 4) + 'A'), (pci_read_config(dev, 858 PCIR_REVID, 4) & 0xf)); 859 rc = ENODEV; 860 goto bce_attach_fail; 861 } 862 863 /* 864 * The embedded PCIe to PCI-X bridge (EPB) 865 * in the 5708 cannot address memory above 866 * 40 bits (E7_5708CB1_23043 & E6_5708SB1_23043). 867 */ 868 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708) 869 sc->max_bus_addr = BCE_BUS_SPACE_MAXADDR; 870 else 871 sc->max_bus_addr = BUS_SPACE_MAXADDR; 872 873 /* 874 * Find the base address for shared memory access. 875 * Newer versions of bootcode use a signature and offset 876 * while older versions use a fixed address. 877 */ 878 val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE); 879 if ((val & BCE_SHM_HDR_SIGNATURE_SIG_MASK) == BCE_SHM_HDR_SIGNATURE_SIG) 880 /* Multi-port devices use different offsets in shared memory. */ 881 sc->bce_shmem_base = REG_RD_IND(sc, BCE_SHM_HDR_ADDR_0 + 882 (pci_get_function(sc->bce_dev) << 2)); 883 else 884 sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE; 885 886 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): bce_shmem_base = 0x%08X\n", 887 __FUNCTION__, sc->bce_shmem_base); 888 889 /* Fetch the bootcode revision. */ 890 val = bce_shmem_rd(sc, BCE_DEV_INFO_BC_REV); 891 for (int i = 0, j = 0; i < 3; i++) { 892 u8 num; 893 894 num = (u8) (val >> (24 - (i * 8))); 895 for (int k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) { 896 if (num >= k || !skip0 || k == 1) { 897 sc->bce_bc_ver[j++] = (num / k) + '0'; 898 skip0 = 0; 899 } 900 } 901 902 if (i != 2) 903 sc->bce_bc_ver[j++] = '.'; 904 } 905 906 /* Check if any management firwmare is enabled. */ 907 val = bce_shmem_rd(sc, BCE_PORT_FEATURE); 908 if (val & BCE_PORT_FEATURE_ASF_ENABLED) { 909 sc->bce_flags |= BCE_MFW_ENABLE_FLAG; 910 911 /* Allow time for firmware to enter the running state. */ 912 for (int i = 0; i < 30; i++) { 913 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); 914 if (val & BCE_CONDITION_MFW_RUN_MASK) 915 break; 916 DELAY(10000); 917 } 918 919 /* Check if management firmware is running. */ 920 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); 921 val &= BCE_CONDITION_MFW_RUN_MASK; 922 if ((val != BCE_CONDITION_MFW_RUN_UNKNOWN) && 923 (val != BCE_CONDITION_MFW_RUN_NONE)) { 924 u32 addr = bce_shmem_rd(sc, BCE_MFW_VER_PTR); 925 int i = 0; 926 927 /* Read the management firmware version string. */ 928 for (int j = 0; j < 3; j++) { 929 val = bce_reg_rd_ind(sc, addr + j * 4); 930 val = bswap32(val); 931 memcpy(&sc->bce_mfw_ver[i], &val, 4); 932 i += 4; 933 } 934 } else { 935 /* May cause firmware synchronization timeouts. */ 936 BCE_PRINTF("%s(%d): Management firmware enabled " 937 "but not running!\n", __FILE__, __LINE__); 938 strcpy(sc->bce_mfw_ver, "NOT RUNNING!"); 939 940 /* ToDo: Any action the driver should take? */ 941 } 942 } 943 944 /* Get PCI bus information (speed and type). */ 945 val = REG_RD(sc, BCE_PCICFG_MISC_STATUS); 946 if (val & BCE_PCICFG_MISC_STATUS_PCIX_DET) { 947 u32 clkreg; 948 949 sc->bce_flags |= BCE_PCIX_FLAG; 950 951 clkreg = REG_RD(sc, BCE_PCICFG_PCI_CLOCK_CONTROL_BITS); 952 953 clkreg &= BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET; 954 switch (clkreg) { 955 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ: 956 sc->bus_speed_mhz = 133; 957 break; 958 959 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ: 960 sc->bus_speed_mhz = 100; 961 break; 962 963 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ: 964 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ: 965 sc->bus_speed_mhz = 66; 966 break; 967 968 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ: 969 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ: 970 sc->bus_speed_mhz = 50; 971 break; 972 973 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW: 974 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ: 975 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ: 976 sc->bus_speed_mhz = 33; 977 break; 978 } 979 } else { 980 if (val & BCE_PCICFG_MISC_STATUS_M66EN) 981 sc->bus_speed_mhz = 66; 982 else 983 sc->bus_speed_mhz = 33; 984 } 985 986 if (val & BCE_PCICFG_MISC_STATUS_32BIT_DET) 987 sc->bce_flags |= BCE_PCI_32BIT_FLAG; 988 989 /* Reset controller and announce to bootcode that driver is present. */ 990 if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) { 991 BCE_PRINTF("%s(%d): Controller reset failed!\n", 992 __FILE__, __LINE__); 993 rc = ENXIO; 994 goto bce_attach_fail; 995 } 996 997 /* Initialize the controller. */ 998 if (bce_chipinit(sc)) { 999 BCE_PRINTF("%s(%d): Controller initialization failed!\n", 1000 __FILE__, __LINE__); 1001 rc = ENXIO; 1002 goto bce_attach_fail; 1003 } 1004 1005 /* Perform NVRAM test. */ 1006 if (bce_nvram_test(sc)) { 1007 BCE_PRINTF("%s(%d): NVRAM test failed!\n", 1008 __FILE__, __LINE__); 1009 rc = ENXIO; 1010 goto bce_attach_fail; 1011 } 1012 1013 /* Fetch the permanent Ethernet MAC address. */ 1014 bce_get_mac_addr(sc); 1015 1016 /* 1017 * Trip points control how many BDs 1018 * should be ready before generating an 1019 * interrupt while ticks control how long 1020 * a BD can sit in the chain before 1021 * generating an interrupt. Set the default 1022 * values for the RX and TX chains. 1023 */ 1024 1025#ifdef BCE_DEBUG 1026 /* Force more frequent interrupts. */ 1027 sc->bce_tx_quick_cons_trip_int = 1; 1028 sc->bce_tx_quick_cons_trip = 1; 1029 sc->bce_tx_ticks_int = 0; 1030 sc->bce_tx_ticks = 0; 1031 1032 sc->bce_rx_quick_cons_trip_int = 1; 1033 sc->bce_rx_quick_cons_trip = 1; 1034 sc->bce_rx_ticks_int = 0; 1035 sc->bce_rx_ticks = 0; 1036#else 1037 /* Improve throughput at the expense of increased latency. */ 1038 sc->bce_tx_quick_cons_trip_int = 20; 1039 sc->bce_tx_quick_cons_trip = 20; 1040 sc->bce_tx_ticks_int = 80; 1041 sc->bce_tx_ticks = 80; 1042 1043 sc->bce_rx_quick_cons_trip_int = 6; 1044 sc->bce_rx_quick_cons_trip = 6; 1045 sc->bce_rx_ticks_int = 18; 1046 sc->bce_rx_ticks = 18; 1047#endif 1048 1049 /* Not used for L2. */ 1050 sc->bce_comp_prod_trip_int = 0; 1051 sc->bce_comp_prod_trip = 0; 1052 sc->bce_com_ticks_int = 0; 1053 sc->bce_com_ticks = 0; 1054 sc->bce_cmd_ticks_int = 0; 1055 sc->bce_cmd_ticks = 0; 1056 1057 /* Update statistics once every second. */ 1058 sc->bce_stats_ticks = 1000000 & 0xffff00; 1059 1060 /* Find the media type for the adapter. */ 1061 bce_get_media(sc); 1062 1063 /* Store data needed by PHY driver for backplane applications */ 1064 sc->bce_shared_hw_cfg = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG); 1065 sc->bce_port_hw_cfg = bce_shmem_rd(sc, BCE_PORT_HW_CFG_CONFIG); 1066 1067 /* Allocate DMA memory resources. */ 1068 if (bce_dma_alloc(dev)) { 1069 BCE_PRINTF("%s(%d): DMA resource allocation failed!\n", 1070 __FILE__, __LINE__); 1071 rc = ENXIO; 1072 goto bce_attach_fail; 1073 } 1074 1075 /* Allocate an ifnet structure. */ 1076 ifp = sc->bce_ifp = if_alloc(IFT_ETHER); 1077 if (ifp == NULL) { 1078 BCE_PRINTF("%s(%d): Interface allocation failed!\n", 1079 __FILE__, __LINE__); 1080 rc = ENXIO; 1081 goto bce_attach_fail; 1082 } 1083 1084 /* Initialize the ifnet interface. */ 1085 ifp->if_softc = sc; 1086 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1087 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1088 ifp->if_ioctl = bce_ioctl; 1089 ifp->if_start = bce_start; 1090 ifp->if_init = bce_init; 1091 ifp->if_mtu = ETHERMTU; 1092 1093 if (bce_tso_enable) { 1094 ifp->if_hwassist = BCE_IF_HWASSIST | CSUM_TSO; 1095 ifp->if_capabilities = BCE_IF_CAPABILITIES | IFCAP_TSO4 | 1096 IFCAP_VLAN_HWTSO; 1097 } else { 1098 ifp->if_hwassist = BCE_IF_HWASSIST; 1099 ifp->if_capabilities = BCE_IF_CAPABILITIES; 1100 } 1101 1102 ifp->if_capenable = ifp->if_capabilities; 1103 1104 /* 1105 * Assume standard mbuf sizes for buffer allocation. 1106 * This may change later if the MTU size is set to 1107 * something other than 1500. 1108 */ 1109#ifdef BCE_JUMBO_HDRSPLIT 1110 sc->rx_bd_mbuf_alloc_size = MHLEN; 1111 /* Make sure offset is 16 byte aligned for hardware. */ 1112 sc->rx_bd_mbuf_align_pad = 1113 roundup2((MSIZE - MHLEN), 16) - (MSIZE - MHLEN); 1114 sc->rx_bd_mbuf_data_len = sc->rx_bd_mbuf_alloc_size - 1115 sc->rx_bd_mbuf_align_pad; 1116 sc->pg_bd_mbuf_alloc_size = MCLBYTES; 1117#else 1118 sc->rx_bd_mbuf_alloc_size = MCLBYTES; 1119 sc->rx_bd_mbuf_align_pad = 1120 roundup2(MCLBYTES, 16) - MCLBYTES; 1121 sc->rx_bd_mbuf_data_len = sc->rx_bd_mbuf_alloc_size - 1122 sc->rx_bd_mbuf_align_pad; 1123#endif 1124 1125 ifp->if_snd.ifq_drv_maxlen = USABLE_TX_BD; 1126 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 1127 IFQ_SET_READY(&ifp->if_snd); 1128 1129 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) 1130 ifp->if_baudrate = IF_Mbps(2500ULL); 1131 else 1132 ifp->if_baudrate = IF_Mbps(1000); 1133 1134 /* Handle any special PHY initialization for SerDes PHYs. */ 1135 bce_init_media(sc); 1136 1137 /* MII child bus by probing the PHY. */ 1138 if (mii_phy_probe(dev, &sc->bce_miibus, bce_ifmedia_upd, 1139 bce_ifmedia_sts)) { 1140 BCE_PRINTF("%s(%d): No PHY found on child MII bus!\n", 1141 __FILE__, __LINE__); 1142 rc = ENXIO; 1143 goto bce_attach_fail; 1144 } 1145 1146 /* Attach to the Ethernet interface list. */ 1147 ether_ifattach(ifp, sc->eaddr); 1148 1149#if __FreeBSD_version < 500000 1150 callout_init(&sc->bce_tick_callout); 1151 callout_init(&sc->bce_pulse_callout); 1152#else 1153 callout_init_mtx(&sc->bce_tick_callout, &sc->bce_mtx, 0); 1154 callout_init_mtx(&sc->bce_pulse_callout, &sc->bce_mtx, 0); 1155#endif 1156 1157 /* Hookup IRQ last. */ 1158 rc = bus_setup_intr(dev, sc->bce_res_irq, INTR_TYPE_NET | INTR_MPSAFE, 1159 NULL, bce_intr, sc, &sc->bce_intrhand); 1160 1161 if (rc) { 1162 BCE_PRINTF("%s(%d): Failed to setup IRQ!\n", 1163 __FILE__, __LINE__); 1164 bce_detach(dev); 1165 goto bce_attach_exit; 1166 } 1167 1168 /* 1169 * At this point we've acquired all the resources 1170 * we need to run so there's no turning back, we're 1171 * cleared for launch. 1172 */ 1173 1174 /* Print some important debugging info. */ 1175 DBRUNMSG(BCE_INFO, bce_dump_driver_state(sc)); 1176 1177 /* Add the supported sysctls to the kernel. */ 1178 bce_add_sysctls(sc); 1179 1180 BCE_LOCK(sc); 1181 1182 /* 1183 * The chip reset earlier notified the bootcode that 1184 * a driver is present. We now need to start our pulse 1185 * routine so that the bootcode is reminded that we're 1186 * still running. 1187 */ 1188 bce_pulse(sc); 1189 1190 bce_mgmt_init_locked(sc); 1191 BCE_UNLOCK(sc); 1192 1193 /* Finally, print some useful adapter info */ 1194 bce_print_adapter_info(sc); 1195 DBPRINT(sc, BCE_FATAL, "%s(): sc = %p\n", 1196 __FUNCTION__, sc); 1197 1198 goto bce_attach_exit; 1199 1200bce_attach_fail: 1201 bce_release_resources(sc); 1202 1203bce_attach_exit: 1204 1205 DBEXIT(BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 1206 1207 return(rc); 1208} 1209 1210 1211/****************************************************************************/ 1212/* Device detach function. */ 1213/* */ 1214/* Stops the controller, resets the controller, and releases resources. */ 1215/* */ 1216/* Returns: */ 1217/* 0 on success, positive value on failure. */ 1218/****************************************************************************/ 1219static int 1220bce_detach(device_t dev) 1221{ 1222 struct bce_softc *sc = device_get_softc(dev); 1223 struct ifnet *ifp; 1224 u32 msg; 1225 1226 DBENTER(BCE_VERBOSE_UNLOAD | BCE_VERBOSE_RESET); 1227 1228 ifp = sc->bce_ifp; 1229 1230 /* Stop and reset the controller. */ 1231 BCE_LOCK(sc); 1232 1233 /* Stop the pulse so the bootcode can go to driver absent state. */ 1234 callout_stop(&sc->bce_pulse_callout); 1235 1236 bce_stop(sc); 1237 if (sc->bce_flags & BCE_NO_WOL_FLAG) 1238 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN; 1239 else 1240 msg = BCE_DRV_MSG_CODE_UNLOAD; 1241 bce_reset(sc, msg); 1242 1243 BCE_UNLOCK(sc); 1244 1245 ether_ifdetach(ifp); 1246 1247 /* If we have a child device on the MII bus remove it too. */ 1248 bus_generic_detach(dev); 1249 device_delete_child(dev, sc->bce_miibus); 1250 1251 /* Release all remaining resources. */ 1252 bce_release_resources(sc); 1253 1254 DBEXIT(BCE_VERBOSE_UNLOAD | BCE_VERBOSE_RESET); 1255 1256 return(0); 1257} 1258 1259 1260/****************************************************************************/ 1261/* Device shutdown function. */ 1262/* */ 1263/* Stops and resets the controller. */ 1264/* */ 1265/* Returns: */ 1266/* 0 on success, positive value on failure. */ 1267/****************************************************************************/ 1268static int 1269bce_shutdown(device_t dev) 1270{ 1271 struct bce_softc *sc = device_get_softc(dev); 1272 u32 msg; 1273 1274 DBENTER(BCE_VERBOSE); 1275 1276 BCE_LOCK(sc); 1277 bce_stop(sc); 1278 if (sc->bce_flags & BCE_NO_WOL_FLAG) 1279 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN; 1280 else 1281 msg = BCE_DRV_MSG_CODE_UNLOAD; 1282 bce_reset(sc, msg); 1283 BCE_UNLOCK(sc); 1284 1285 DBEXIT(BCE_VERBOSE); 1286 1287 return (0); 1288} 1289 1290 1291#ifdef BCE_DEBUG 1292/****************************************************************************/ 1293/* Register read. */ 1294/* */ 1295/* Returns: */ 1296/* The value of the register. */ 1297/****************************************************************************/ 1298static u32 1299bce_reg_rd(struct bce_softc *sc, u32 offset) 1300{ 1301 u32 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, offset); 1302 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1303 __FUNCTION__, offset, val); 1304 return val; 1305} 1306 1307 1308/****************************************************************************/ 1309/* Register write (16 bit). */ 1310/* */ 1311/* Returns: */ 1312/* Nothing. */ 1313/****************************************************************************/ 1314static void 1315bce_reg_wr16(struct bce_softc *sc, u32 offset, u16 val) 1316{ 1317 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%04X\n", 1318 __FUNCTION__, offset, val); 1319 bus_space_write_2(sc->bce_btag, sc->bce_bhandle, offset, val); 1320} 1321 1322 1323/****************************************************************************/ 1324/* Register write. */ 1325/* */ 1326/* Returns: */ 1327/* Nothing. */ 1328/****************************************************************************/ 1329static void 1330bce_reg_wr(struct bce_softc *sc, u32 offset, u32 val) 1331{ 1332 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1333 __FUNCTION__, offset, val); 1334 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, offset, val); 1335} 1336#endif 1337 1338/****************************************************************************/ 1339/* Indirect register read. */ 1340/* */ 1341/* Reads NetXtreme II registers using an index/data register pair in PCI */ 1342/* configuration space. Using this mechanism avoids issues with posted */ 1343/* reads but is much slower than memory-mapped I/O. */ 1344/* */ 1345/* Returns: */ 1346/* The value of the register. */ 1347/****************************************************************************/ 1348static u32 1349bce_reg_rd_ind(struct bce_softc *sc, u32 offset) 1350{ 1351 device_t dev; 1352 dev = sc->bce_dev; 1353 1354 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4); 1355#ifdef BCE_DEBUG 1356 { 1357 u32 val; 1358 val = pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4); 1359 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1360 __FUNCTION__, offset, val); 1361 return val; 1362 } 1363#else 1364 return pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4); 1365#endif 1366} 1367 1368 1369/****************************************************************************/ 1370/* Indirect register write. */ 1371/* */ 1372/* Writes NetXtreme II registers using an index/data register pair in PCI */ 1373/* configuration space. Using this mechanism avoids issues with posted */ 1374/* writes but is muchh slower than memory-mapped I/O. */ 1375/* */ 1376/* Returns: */ 1377/* Nothing. */ 1378/****************************************************************************/ 1379static void 1380bce_reg_wr_ind(struct bce_softc *sc, u32 offset, u32 val) 1381{ 1382 device_t dev; 1383 dev = sc->bce_dev; 1384 1385 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1386 __FUNCTION__, offset, val); 1387 1388 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4); 1389 pci_write_config(dev, BCE_PCICFG_REG_WINDOW, val, 4); 1390} 1391 1392 1393/****************************************************************************/ 1394/* Shared memory write. */ 1395/* */ 1396/* Writes NetXtreme II shared memory region. */ 1397/* */ 1398/* Returns: */ 1399/* Nothing. */ 1400/****************************************************************************/ 1401static void 1402bce_shmem_wr(struct bce_softc *sc, u32 offset, u32 val) 1403{ 1404 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): Writing 0x%08X to " 1405 "0x%08X\n", __FUNCTION__, val, offset); 1406 1407 bce_reg_wr_ind(sc, sc->bce_shmem_base + offset, val); 1408} 1409 1410 1411/****************************************************************************/ 1412/* Shared memory read. */ 1413/* */ 1414/* Reads NetXtreme II shared memory region. */ 1415/* */ 1416/* Returns: */ 1417/* The 32 bit value read. */ 1418/****************************************************************************/ 1419static u32 1420bce_shmem_rd(struct bce_softc *sc, u32 offset) 1421{ 1422 u32 val = bce_reg_rd_ind(sc, sc->bce_shmem_base + offset); 1423 1424 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): Reading 0x%08X from " 1425 "0x%08X\n", __FUNCTION__, val, offset); 1426 1427 return val; 1428} 1429 1430 1431#ifdef BCE_DEBUG 1432/****************************************************************************/ 1433/* Context memory read. */ 1434/* */ 1435/* The NetXtreme II controller uses context memory to track connection */ 1436/* information for L2 and higher network protocols. */ 1437/* */ 1438/* Returns: */ 1439/* The requested 32 bit value of context memory. */ 1440/****************************************************************************/ 1441static u32 1442bce_ctx_rd(struct bce_softc *sc, u32 cid_addr, u32 ctx_offset) 1443{ 1444 u32 idx, offset, retry_cnt = 5, val; 1445 1446 DBRUNIF((cid_addr > MAX_CID_ADDR || ctx_offset & 0x3 || 1447 cid_addr & CTX_MASK), BCE_PRINTF("%s(): Invalid CID " 1448 "address: 0x%08X.\n", __FUNCTION__, cid_addr)); 1449 1450 offset = ctx_offset + cid_addr; 1451 1452 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 1453 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 1454 1455 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_READ_REQ)); 1456 1457 for (idx = 0; idx < retry_cnt; idx++) { 1458 val = REG_RD(sc, BCE_CTX_CTX_CTRL); 1459 if ((val & BCE_CTX_CTX_CTRL_READ_REQ) == 0) 1460 break; 1461 DELAY(5); 1462 } 1463 1464 if (val & BCE_CTX_CTX_CTRL_READ_REQ) 1465 BCE_PRINTF("%s(%d); Unable to read CTX memory: " 1466 "cid_addr = 0x%08X, offset = 0x%08X!\n", 1467 __FILE__, __LINE__, cid_addr, ctx_offset); 1468 1469 val = REG_RD(sc, BCE_CTX_CTX_DATA); 1470 } else { 1471 REG_WR(sc, BCE_CTX_DATA_ADR, offset); 1472 val = REG_RD(sc, BCE_CTX_DATA); 1473 } 1474 1475 DBPRINT(sc, BCE_EXTREME_CTX, "%s(); cid_addr = 0x%08X, offset = 0x%08X, " 1476 "val = 0x%08X\n", __FUNCTION__, cid_addr, ctx_offset, val); 1477 1478 return(val); 1479} 1480#endif 1481 1482 1483/****************************************************************************/ 1484/* Context memory write. */ 1485/* */ 1486/* The NetXtreme II controller uses context memory to track connection */ 1487/* information for L2 and higher network protocols. */ 1488/* */ 1489/* Returns: */ 1490/* Nothing. */ 1491/****************************************************************************/ 1492static void 1493bce_ctx_wr(struct bce_softc *sc, u32 cid_addr, u32 ctx_offset, u32 ctx_val) 1494{ 1495 u32 idx, offset = ctx_offset + cid_addr; 1496 u32 val, retry_cnt = 5; 1497 1498 DBPRINT(sc, BCE_EXTREME_CTX, "%s(); cid_addr = 0x%08X, offset = 0x%08X, " 1499 "val = 0x%08X\n", __FUNCTION__, cid_addr, ctx_offset, ctx_val); 1500 1501 DBRUNIF((cid_addr > MAX_CID_ADDR || ctx_offset & 0x3 || cid_addr & CTX_MASK), 1502 BCE_PRINTF("%s(): Invalid CID address: 0x%08X.\n", 1503 __FUNCTION__, cid_addr)); 1504 1505 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 1506 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 1507 1508 REG_WR(sc, BCE_CTX_CTX_DATA, ctx_val); 1509 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_WRITE_REQ)); 1510 1511 for (idx = 0; idx < retry_cnt; idx++) { 1512 val = REG_RD(sc, BCE_CTX_CTX_CTRL); 1513 if ((val & BCE_CTX_CTX_CTRL_WRITE_REQ) == 0) 1514 break; 1515 DELAY(5); 1516 } 1517 1518 if (val & BCE_CTX_CTX_CTRL_WRITE_REQ) 1519 BCE_PRINTF("%s(%d); Unable to write CTX memory: " 1520 "cid_addr = 0x%08X, offset = 0x%08X!\n", 1521 __FILE__, __LINE__, cid_addr, ctx_offset); 1522 1523 } else { 1524 REG_WR(sc, BCE_CTX_DATA_ADR, offset); 1525 REG_WR(sc, BCE_CTX_DATA, ctx_val); 1526 } 1527} 1528 1529 1530/****************************************************************************/ 1531/* PHY register read. */ 1532/* */ 1533/* Implements register reads on the MII bus. */ 1534/* */ 1535/* Returns: */ 1536/* The value of the register. */ 1537/****************************************************************************/ 1538static int 1539bce_miibus_read_reg(device_t dev, int phy, int reg) 1540{ 1541 struct bce_softc *sc; 1542 u32 val; 1543 int i; 1544 1545 sc = device_get_softc(dev); 1546 1547 /* Make sure we are accessing the correct PHY address. */ 1548 if (phy != sc->bce_phy_addr) { 1549 DBPRINT(sc, BCE_INSANE_PHY, "Invalid PHY address %d " 1550 "for PHY read!\n", phy); 1551 return(0); 1552 } 1553 1554 /* 1555 * The 5709S PHY is an IEEE Clause 45 PHY 1556 * with special mappings to work with IEEE 1557 * Clause 22 register accesses. 1558 */ 1559 if ((sc->bce_phy_flags & BCE_PHY_IEEE_CLAUSE_45_FLAG) != 0) { 1560 if (reg >= MII_BMCR && reg <= MII_ANLPRNP) 1561 reg += 0x10; 1562 } 1563 1564 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1565 val = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1566 val &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL; 1567 1568 REG_WR(sc, BCE_EMAC_MDIO_MODE, val); 1569 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1570 1571 DELAY(40); 1572 } 1573 1574 1575 val = BCE_MIPHY(phy) | BCE_MIREG(reg) | 1576 BCE_EMAC_MDIO_COMM_COMMAND_READ | BCE_EMAC_MDIO_COMM_DISEXT | 1577 BCE_EMAC_MDIO_COMM_START_BUSY; 1578 REG_WR(sc, BCE_EMAC_MDIO_COMM, val); 1579 1580 for (i = 0; i < BCE_PHY_TIMEOUT; i++) { 1581 DELAY(10); 1582 1583 val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1584 if (!(val & BCE_EMAC_MDIO_COMM_START_BUSY)) { 1585 DELAY(5); 1586 1587 val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1588 val &= BCE_EMAC_MDIO_COMM_DATA; 1589 1590 break; 1591 } 1592 } 1593 1594 if (val & BCE_EMAC_MDIO_COMM_START_BUSY) { 1595 BCE_PRINTF("%s(%d): Error: PHY read timeout! phy = %d, " 1596 "reg = 0x%04X\n", __FILE__, __LINE__, phy, reg); 1597 val = 0x0; 1598 } else { 1599 val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1600 } 1601 1602 1603 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1604 val = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1605 val |= BCE_EMAC_MDIO_MODE_AUTO_POLL; 1606 1607 REG_WR(sc, BCE_EMAC_MDIO_MODE, val); 1608 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1609 1610 DELAY(40); 1611 } 1612 1613 DB_PRINT_PHY_REG(reg, val); 1614 return (val & 0xffff); 1615 1616} 1617 1618 1619/****************************************************************************/ 1620/* PHY register write. */ 1621/* */ 1622/* Implements register writes on the MII bus. */ 1623/* */ 1624/* Returns: */ 1625/* The value of the register. */ 1626/****************************************************************************/ 1627static int 1628bce_miibus_write_reg(device_t dev, int phy, int reg, int val) 1629{ 1630 struct bce_softc *sc; 1631 u32 val1; 1632 int i; 1633 1634 sc = device_get_softc(dev); 1635 1636 /* Make sure we are accessing the correct PHY address. */ 1637 if (phy != sc->bce_phy_addr) { 1638 DBPRINT(sc, BCE_INSANE_PHY, "Invalid PHY address %d " 1639 "for PHY write!\n", phy); 1640 return(0); 1641 } 1642 1643 DB_PRINT_PHY_REG(reg, val); 1644 1645 /* 1646 * The 5709S PHY is an IEEE Clause 45 PHY 1647 * with special mappings to work with IEEE 1648 * Clause 22 register accesses. 1649 */ 1650 if ((sc->bce_phy_flags & BCE_PHY_IEEE_CLAUSE_45_FLAG) != 0) { 1651 if (reg >= MII_BMCR && reg <= MII_ANLPRNP) 1652 reg += 0x10; 1653 } 1654 1655 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1656 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1657 val1 &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL; 1658 1659 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1); 1660 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1661 1662 DELAY(40); 1663 } 1664 1665 val1 = BCE_MIPHY(phy) | BCE_MIREG(reg) | val | 1666 BCE_EMAC_MDIO_COMM_COMMAND_WRITE | 1667 BCE_EMAC_MDIO_COMM_START_BUSY | BCE_EMAC_MDIO_COMM_DISEXT; 1668 REG_WR(sc, BCE_EMAC_MDIO_COMM, val1); 1669 1670 for (i = 0; i < BCE_PHY_TIMEOUT; i++) { 1671 DELAY(10); 1672 1673 val1 = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1674 if (!(val1 & BCE_EMAC_MDIO_COMM_START_BUSY)) { 1675 DELAY(5); 1676 break; 1677 } 1678 } 1679 1680 if (val1 & BCE_EMAC_MDIO_COMM_START_BUSY) 1681 BCE_PRINTF("%s(%d): PHY write timeout!\n", 1682 __FILE__, __LINE__); 1683 1684 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1685 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1686 val1 |= BCE_EMAC_MDIO_MODE_AUTO_POLL; 1687 1688 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1); 1689 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1690 1691 DELAY(40); 1692 } 1693 1694 return 0; 1695} 1696 1697 1698/****************************************************************************/ 1699/* MII bus status change. */ 1700/* */ 1701/* Called by the MII bus driver when the PHY establishes link to set the */ 1702/* MAC interface registers. */ 1703/* */ 1704/* Returns: */ 1705/* Nothing. */ 1706/****************************************************************************/ 1707static void 1708bce_miibus_statchg(device_t dev) 1709{ 1710 struct bce_softc *sc; 1711 struct mii_data *mii; 1712 int val; 1713 1714 sc = device_get_softc(dev); 1715 1716 DBENTER(BCE_VERBOSE_PHY); 1717 1718 mii = device_get_softc(sc->bce_miibus); 1719 1720 val = REG_RD(sc, BCE_EMAC_MODE); 1721 val &= ~(BCE_EMAC_MODE_PORT | BCE_EMAC_MODE_HALF_DUPLEX | 1722 BCE_EMAC_MODE_MAC_LOOP | BCE_EMAC_MODE_FORCE_LINK | 1723 BCE_EMAC_MODE_25G); 1724 1725 /* Set MII or GMII interface based on the PHY speed. */ 1726 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1727 case IFM_10_T: 1728 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) { 1729 DBPRINT(sc, BCE_INFO_PHY, 1730 "Enabling 10Mb interface.\n"); 1731 val |= BCE_EMAC_MODE_PORT_MII_10; 1732 break; 1733 } 1734 /* fall-through */ 1735 case IFM_100_TX: 1736 DBPRINT(sc, BCE_INFO_PHY, "Enabling MII interface.\n"); 1737 val |= BCE_EMAC_MODE_PORT_MII; 1738 break; 1739 case IFM_2500_SX: 1740 DBPRINT(sc, BCE_INFO_PHY, "Enabling 2.5G MAC mode.\n"); 1741 val |= BCE_EMAC_MODE_25G; 1742 /* fall-through */ 1743 case IFM_1000_T: 1744 case IFM_1000_SX: 1745 DBPRINT(sc, BCE_INFO_PHY, "Enabling GMII interface.\n"); 1746 val |= BCE_EMAC_MODE_PORT_GMII; 1747 break; 1748 default: 1749 DBPRINT(sc, BCE_INFO_PHY, "Unknown link speed, enabling " 1750 "default GMII interface.\n"); 1751 val |= BCE_EMAC_MODE_PORT_GMII; 1752 } 1753 1754 /* Set half or full duplex based on PHY settings. */ 1755 if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) { 1756 DBPRINT(sc, BCE_INFO_PHY, 1757 "Setting Half-Duplex interface.\n"); 1758 val |= BCE_EMAC_MODE_HALF_DUPLEX; 1759 } else 1760 DBPRINT(sc, BCE_INFO_PHY, 1761 "Setting Full-Duplex interface.\n"); 1762 1763 REG_WR(sc, BCE_EMAC_MODE, val); 1764 1765 /* FLAG0 is set if RX is enabled and FLAG1 if TX is enabled */ 1766 if (mii->mii_media_active & IFM_FLAG0) { 1767 DBPRINT(sc, BCE_INFO_PHY, 1768 "%s(): Enabling RX flow control.\n", __FUNCTION__); 1769 BCE_SETBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_RX_MODE_FLOW_EN); 1770 } else { 1771 DBPRINT(sc, BCE_INFO_PHY, 1772 "%s(): Disabling RX flow control.\n", __FUNCTION__); 1773 BCE_CLRBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_RX_MODE_FLOW_EN); 1774 } 1775 1776 if (mii->mii_media_active & IFM_FLAG1) { 1777 DBPRINT(sc, BCE_INFO_PHY, 1778 "%s(): Enabling TX flow control.\n", __FUNCTION__); 1779 BCE_SETBIT(sc, BCE_EMAC_TX_MODE, BCE_EMAC_TX_MODE_FLOW_EN); 1780 sc->bce_flags |= BCE_USING_TX_FLOW_CONTROL; 1781 } else { 1782 DBPRINT(sc, BCE_INFO_PHY, 1783 "%s(): Disabling TX flow control.\n", __FUNCTION__); 1784 BCE_CLRBIT(sc, BCE_EMAC_TX_MODE, BCE_EMAC_TX_MODE_FLOW_EN); 1785 sc->bce_flags &= ~BCE_USING_TX_FLOW_CONTROL; 1786 } 1787 1788 /* ToDo: Update watermarks in bce_init_rx_context(). */ 1789 1790 DBEXIT(BCE_VERBOSE_PHY); 1791} 1792 1793 1794/****************************************************************************/ 1795/* Acquire NVRAM lock. */ 1796/* */ 1797/* Before the NVRAM can be accessed the caller must acquire an NVRAM lock. */ 1798/* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 1799/* for use by the driver. */ 1800/* */ 1801/* Returns: */ 1802/* 0 on success, positive value on failure. */ 1803/****************************************************************************/ 1804static int 1805bce_acquire_nvram_lock(struct bce_softc *sc) 1806{ 1807 u32 val; 1808 int j, rc = 0; 1809 1810 DBENTER(BCE_VERBOSE_NVRAM); 1811 1812 /* Request access to the flash interface. */ 1813 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2); 1814 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1815 val = REG_RD(sc, BCE_NVM_SW_ARB); 1816 if (val & BCE_NVM_SW_ARB_ARB_ARB2) 1817 break; 1818 1819 DELAY(5); 1820 } 1821 1822 if (j >= NVRAM_TIMEOUT_COUNT) { 1823 DBPRINT(sc, BCE_WARN, "Timeout acquiring NVRAM lock!\n"); 1824 rc = EBUSY; 1825 } 1826 1827 DBEXIT(BCE_VERBOSE_NVRAM); 1828 return (rc); 1829} 1830 1831 1832/****************************************************************************/ 1833/* Release NVRAM lock. */ 1834/* */ 1835/* When the caller is finished accessing NVRAM the lock must be released. */ 1836/* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 1837/* for use by the driver. */ 1838/* */ 1839/* Returns: */ 1840/* 0 on success, positive value on failure. */ 1841/****************************************************************************/ 1842static int 1843bce_release_nvram_lock(struct bce_softc *sc) 1844{ 1845 u32 val; 1846 int j, rc = 0; 1847 1848 DBENTER(BCE_VERBOSE_NVRAM); 1849 1850 /* 1851 * Relinquish nvram interface. 1852 */ 1853 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2); 1854 1855 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1856 val = REG_RD(sc, BCE_NVM_SW_ARB); 1857 if (!(val & BCE_NVM_SW_ARB_ARB_ARB2)) 1858 break; 1859 1860 DELAY(5); 1861 } 1862 1863 if (j >= NVRAM_TIMEOUT_COUNT) { 1864 DBPRINT(sc, BCE_WARN, "Timeout releasing NVRAM lock!\n"); 1865 rc = EBUSY; 1866 } 1867 1868 DBEXIT(BCE_VERBOSE_NVRAM); 1869 return (rc); 1870} 1871 1872 1873#ifdef BCE_NVRAM_WRITE_SUPPORT 1874/****************************************************************************/ 1875/* Enable NVRAM write access. */ 1876/* */ 1877/* Before writing to NVRAM the caller must enable NVRAM writes. */ 1878/* */ 1879/* Returns: */ 1880/* 0 on success, positive value on failure. */ 1881/****************************************************************************/ 1882static int 1883bce_enable_nvram_write(struct bce_softc *sc) 1884{ 1885 u32 val; 1886 int rc = 0; 1887 1888 DBENTER(BCE_VERBOSE_NVRAM); 1889 1890 val = REG_RD(sc, BCE_MISC_CFG); 1891 REG_WR(sc, BCE_MISC_CFG, val | BCE_MISC_CFG_NVM_WR_EN_PCI); 1892 1893 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 1894 int j; 1895 1896 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 1897 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_WREN | BCE_NVM_COMMAND_DOIT); 1898 1899 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1900 DELAY(5); 1901 1902 val = REG_RD(sc, BCE_NVM_COMMAND); 1903 if (val & BCE_NVM_COMMAND_DONE) 1904 break; 1905 } 1906 1907 if (j >= NVRAM_TIMEOUT_COUNT) { 1908 DBPRINT(sc, BCE_WARN, "Timeout writing NVRAM!\n"); 1909 rc = EBUSY; 1910 } 1911 } 1912 1913 DBENTER(BCE_VERBOSE_NVRAM); 1914 return (rc); 1915} 1916 1917 1918/****************************************************************************/ 1919/* Disable NVRAM write access. */ 1920/* */ 1921/* When the caller is finished writing to NVRAM write access must be */ 1922/* disabled. */ 1923/* */ 1924/* Returns: */ 1925/* Nothing. */ 1926/****************************************************************************/ 1927static void 1928bce_disable_nvram_write(struct bce_softc *sc) 1929{ 1930 u32 val; 1931 1932 DBENTER(BCE_VERBOSE_NVRAM); 1933 1934 val = REG_RD(sc, BCE_MISC_CFG); 1935 REG_WR(sc, BCE_MISC_CFG, val & ~BCE_MISC_CFG_NVM_WR_EN); 1936 1937 DBEXIT(BCE_VERBOSE_NVRAM); 1938 1939} 1940#endif 1941 1942 1943/****************************************************************************/ 1944/* Enable NVRAM access. */ 1945/* */ 1946/* Before accessing NVRAM for read or write operations the caller must */ 1947/* enabled NVRAM access. */ 1948/* */ 1949/* Returns: */ 1950/* Nothing. */ 1951/****************************************************************************/ 1952static void 1953bce_enable_nvram_access(struct bce_softc *sc) 1954{ 1955 u32 val; 1956 1957 DBENTER(BCE_VERBOSE_NVRAM); 1958 1959 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE); 1960 /* Enable both bits, even on read. */ 1961 REG_WR(sc, BCE_NVM_ACCESS_ENABLE, val | 1962 BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN); 1963 1964 DBEXIT(BCE_VERBOSE_NVRAM); 1965} 1966 1967 1968/****************************************************************************/ 1969/* Disable NVRAM access. */ 1970/* */ 1971/* When the caller is finished accessing NVRAM access must be disabled. */ 1972/* */ 1973/* Returns: */ 1974/* Nothing. */ 1975/****************************************************************************/ 1976static void 1977bce_disable_nvram_access(struct bce_softc *sc) 1978{ 1979 u32 val; 1980 1981 DBENTER(BCE_VERBOSE_NVRAM); 1982 1983 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE); 1984 1985 /* Disable both bits, even after read. */ 1986 REG_WR(sc, BCE_NVM_ACCESS_ENABLE, val & 1987 ~(BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN)); 1988 1989 DBEXIT(BCE_VERBOSE_NVRAM); 1990} 1991 1992 1993#ifdef BCE_NVRAM_WRITE_SUPPORT 1994/****************************************************************************/ 1995/* Erase NVRAM page before writing. */ 1996/* */ 1997/* Non-buffered flash parts require that a page be erased before it is */ 1998/* written. */ 1999/* */ 2000/* Returns: */ 2001/* 0 on success, positive value on failure. */ 2002/****************************************************************************/ 2003static int 2004bce_nvram_erase_page(struct bce_softc *sc, u32 offset) 2005{ 2006 u32 cmd; 2007 int j, rc = 0; 2008 2009 DBENTER(BCE_VERBOSE_NVRAM); 2010 2011 /* Buffered flash doesn't require an erase. */ 2012 if (sc->bce_flash_info->flags & BCE_NV_BUFFERED) 2013 goto bce_nvram_erase_page_exit; 2014 2015 /* Build an erase command. */ 2016 cmd = BCE_NVM_COMMAND_ERASE | BCE_NVM_COMMAND_WR | 2017 BCE_NVM_COMMAND_DOIT; 2018 2019 /* 2020 * Clear the DONE bit separately, set the NVRAM adress to erase, 2021 * and issue the erase command. 2022 */ 2023 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 2024 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 2025 REG_WR(sc, BCE_NVM_COMMAND, cmd); 2026 2027 /* Wait for completion. */ 2028 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2029 u32 val; 2030 2031 DELAY(5); 2032 2033 val = REG_RD(sc, BCE_NVM_COMMAND); 2034 if (val & BCE_NVM_COMMAND_DONE) 2035 break; 2036 } 2037 2038 if (j >= NVRAM_TIMEOUT_COUNT) { 2039 DBPRINT(sc, BCE_WARN, "Timeout erasing NVRAM.\n"); 2040 rc = EBUSY; 2041 } 2042 2043bce_nvram_erase_page_exit: 2044 DBEXIT(BCE_VERBOSE_NVRAM); 2045 return (rc); 2046} 2047#endif /* BCE_NVRAM_WRITE_SUPPORT */ 2048 2049 2050/****************************************************************************/ 2051/* Read a dword (32 bits) from NVRAM. */ 2052/* */ 2053/* Read a 32 bit word from NVRAM. The caller is assumed to have already */ 2054/* obtained the NVRAM lock and enabled the controller for NVRAM access. */ 2055/* */ 2056/* Returns: */ 2057/* 0 on success and the 32 bit value read, positive value on failure. */ 2058/****************************************************************************/ 2059static int 2060bce_nvram_read_dword(struct bce_softc *sc, 2061 u32 offset, u8 *ret_val, u32 cmd_flags) 2062{ 2063 u32 cmd; 2064 int i, rc = 0; 2065 2066 DBENTER(BCE_EXTREME_NVRAM); 2067 2068 /* Build the command word. */ 2069 cmd = BCE_NVM_COMMAND_DOIT | cmd_flags; 2070 2071 /* Calculate the offset for buffered flash if translation is used. */ 2072 if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) { 2073 offset = ((offset / sc->bce_flash_info->page_size) << 2074 sc->bce_flash_info->page_bits) + 2075 (offset % sc->bce_flash_info->page_size); 2076 } 2077 2078 /* 2079 * Clear the DONE bit separately, set the address to read, 2080 * and issue the read. 2081 */ 2082 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 2083 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 2084 REG_WR(sc, BCE_NVM_COMMAND, cmd); 2085 2086 /* Wait for completion. */ 2087 for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) { 2088 u32 val; 2089 2090 DELAY(5); 2091 2092 val = REG_RD(sc, BCE_NVM_COMMAND); 2093 if (val & BCE_NVM_COMMAND_DONE) { 2094 val = REG_RD(sc, BCE_NVM_READ); 2095 2096 val = bce_be32toh(val); 2097 memcpy(ret_val, &val, 4); 2098 break; 2099 } 2100 } 2101 2102 /* Check for errors. */ 2103 if (i >= NVRAM_TIMEOUT_COUNT) { 2104 BCE_PRINTF("%s(%d): Timeout error reading NVRAM at " 2105 "offset 0x%08X!\n", __FILE__, __LINE__, offset); 2106 rc = EBUSY; 2107 } 2108 2109 DBEXIT(BCE_EXTREME_NVRAM); 2110 return(rc); 2111} 2112 2113 2114#ifdef BCE_NVRAM_WRITE_SUPPORT 2115/****************************************************************************/ 2116/* Write a dword (32 bits) to NVRAM. */ 2117/* */ 2118/* Write a 32 bit word to NVRAM. The caller is assumed to have already */ 2119/* obtained the NVRAM lock, enabled the controller for NVRAM access, and */ 2120/* enabled NVRAM write access. */ 2121/* */ 2122/* Returns: */ 2123/* 0 on success, positive value on failure. */ 2124/****************************************************************************/ 2125static int 2126bce_nvram_write_dword(struct bce_softc *sc, u32 offset, u8 *val, 2127 u32 cmd_flags) 2128{ 2129 u32 cmd, val32; 2130 int j, rc = 0; 2131 2132 DBENTER(BCE_VERBOSE_NVRAM); 2133 2134 /* Build the command word. */ 2135 cmd = BCE_NVM_COMMAND_DOIT | BCE_NVM_COMMAND_WR | cmd_flags; 2136 2137 /* Calculate the offset for buffered flash if translation is used. */ 2138 if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) { 2139 offset = ((offset / sc->bce_flash_info->page_size) << 2140 sc->bce_flash_info->page_bits) + 2141 (offset % sc->bce_flash_info->page_size); 2142 } 2143 2144 /* 2145 * Clear the DONE bit separately, convert NVRAM data to big-endian, 2146 * set the NVRAM address to write, and issue the write command 2147 */ 2148 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 2149 memcpy(&val32, val, 4); 2150 val32 = htobe32(val32); 2151 REG_WR(sc, BCE_NVM_WRITE, val32); 2152 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 2153 REG_WR(sc, BCE_NVM_COMMAND, cmd); 2154 2155 /* Wait for completion. */ 2156 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2157 DELAY(5); 2158 2159 if (REG_RD(sc, BCE_NVM_COMMAND) & BCE_NVM_COMMAND_DONE) 2160 break; 2161 } 2162 if (j >= NVRAM_TIMEOUT_COUNT) { 2163 BCE_PRINTF("%s(%d): Timeout error writing NVRAM at " 2164 "offset 0x%08X\n", __FILE__, __LINE__, offset); 2165 rc = EBUSY; 2166 } 2167 2168 DBEXIT(BCE_VERBOSE_NVRAM); 2169 return (rc); 2170} 2171#endif /* BCE_NVRAM_WRITE_SUPPORT */ 2172 2173 2174/****************************************************************************/ 2175/* Initialize NVRAM access. */ 2176/* */ 2177/* Identify the NVRAM device in use and prepare the NVRAM interface to */ 2178/* access that device. */ 2179/* */ 2180/* Returns: */ 2181/* 0 on success, positive value on failure. */ 2182/****************************************************************************/ 2183static int 2184bce_init_nvram(struct bce_softc *sc) 2185{ 2186 u32 val; 2187 int j, entry_count, rc = 0; 2188 struct flash_spec *flash; 2189 2190 DBENTER(BCE_VERBOSE_NVRAM); 2191 2192 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 2193 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 2194 sc->bce_flash_info = &flash_5709; 2195 goto bce_init_nvram_get_flash_size; 2196 } 2197 2198 /* Determine the selected interface. */ 2199 val = REG_RD(sc, BCE_NVM_CFG1); 2200 2201 entry_count = sizeof(flash_table) / sizeof(struct flash_spec); 2202 2203 /* 2204 * Flash reconfiguration is required to support additional 2205 * NVRAM devices not directly supported in hardware. 2206 * Check if the flash interface was reconfigured 2207 * by the bootcode. 2208 */ 2209 2210 if (val & 0x40000000) { 2211 /* Flash interface reconfigured by bootcode. */ 2212 2213 DBPRINT(sc,BCE_INFO_LOAD, 2214 "bce_init_nvram(): Flash WAS reconfigured.\n"); 2215 2216 for (j = 0, flash = &flash_table[0]; j < entry_count; 2217 j++, flash++) { 2218 if ((val & FLASH_BACKUP_STRAP_MASK) == 2219 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) { 2220 sc->bce_flash_info = flash; 2221 break; 2222 } 2223 } 2224 } else { 2225 /* Flash interface not yet reconfigured. */ 2226 u32 mask; 2227 2228 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Flash was NOT reconfigured.\n", 2229 __FUNCTION__); 2230 2231 if (val & (1 << 23)) 2232 mask = FLASH_BACKUP_STRAP_MASK; 2233 else 2234 mask = FLASH_STRAP_MASK; 2235 2236 /* Look for the matching NVRAM device configuration data. */ 2237 for (j = 0, flash = &flash_table[0]; j < entry_count; j++, flash++) { 2238 2239 /* Check if the device matches any of the known devices. */ 2240 if ((val & mask) == (flash->strapping & mask)) { 2241 /* Found a device match. */ 2242 sc->bce_flash_info = flash; 2243 2244 /* Request access to the flash interface. */ 2245 if ((rc = bce_acquire_nvram_lock(sc)) != 0) 2246 return rc; 2247 2248 /* Reconfigure the flash interface. */ 2249 bce_enable_nvram_access(sc); 2250 REG_WR(sc, BCE_NVM_CFG1, flash->config1); 2251 REG_WR(sc, BCE_NVM_CFG2, flash->config2); 2252 REG_WR(sc, BCE_NVM_CFG3, flash->config3); 2253 REG_WR(sc, BCE_NVM_WRITE1, flash->write1); 2254 bce_disable_nvram_access(sc); 2255 bce_release_nvram_lock(sc); 2256 2257 break; 2258 } 2259 } 2260 } 2261 2262 /* Check if a matching device was found. */ 2263 if (j == entry_count) { 2264 sc->bce_flash_info = NULL; 2265 BCE_PRINTF("%s(%d): Unknown Flash NVRAM found!\n", 2266 __FILE__, __LINE__); 2267 rc = ENODEV; 2268 } 2269 2270bce_init_nvram_get_flash_size: 2271 /* Write the flash config data to the shared memory interface. */ 2272 val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG2); 2273 val &= BCE_SHARED_HW_CFG2_NVM_SIZE_MASK; 2274 if (val) 2275 sc->bce_flash_size = val; 2276 else 2277 sc->bce_flash_size = sc->bce_flash_info->total_size; 2278 2279 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Found %s, size = 0x%08X\n", 2280 __FUNCTION__, sc->bce_flash_info->name, 2281 sc->bce_flash_info->total_size); 2282 2283 DBEXIT(BCE_VERBOSE_NVRAM); 2284 return rc; 2285} 2286 2287 2288/****************************************************************************/ 2289/* Read an arbitrary range of data from NVRAM. */ 2290/* */ 2291/* Prepares the NVRAM interface for access and reads the requested data */ 2292/* into the supplied buffer. */ 2293/* */ 2294/* Returns: */ 2295/* 0 on success and the data read, positive value on failure. */ 2296/****************************************************************************/ 2297static int 2298bce_nvram_read(struct bce_softc *sc, u32 offset, u8 *ret_buf, 2299 int buf_size) 2300{ 2301 int rc = 0; 2302 u32 cmd_flags, offset32, len32, extra; 2303 2304 DBENTER(BCE_VERBOSE_NVRAM); 2305 2306 if (buf_size == 0) 2307 goto bce_nvram_read_exit; 2308 2309 /* Request access to the flash interface. */ 2310 if ((rc = bce_acquire_nvram_lock(sc)) != 0) 2311 goto bce_nvram_read_exit; 2312 2313 /* Enable access to flash interface */ 2314 bce_enable_nvram_access(sc); 2315 2316 len32 = buf_size; 2317 offset32 = offset; 2318 extra = 0; 2319 2320 cmd_flags = 0; 2321 2322 if (offset32 & 3) { 2323 u8 buf[4]; 2324 u32 pre_len; 2325 2326 offset32 &= ~3; 2327 pre_len = 4 - (offset & 3); 2328 2329 if (pre_len >= len32) { 2330 pre_len = len32; 2331 cmd_flags = BCE_NVM_COMMAND_FIRST | BCE_NVM_COMMAND_LAST; 2332 } 2333 else { 2334 cmd_flags = BCE_NVM_COMMAND_FIRST; 2335 } 2336 2337 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 2338 2339 if (rc) 2340 return rc; 2341 2342 memcpy(ret_buf, buf + (offset & 3), pre_len); 2343 2344 offset32 += 4; 2345 ret_buf += pre_len; 2346 len32 -= pre_len; 2347 } 2348 2349 if (len32 & 3) { 2350 extra = 4 - (len32 & 3); 2351 len32 = (len32 + 4) & ~3; 2352 } 2353 2354 if (len32 == 4) { 2355 u8 buf[4]; 2356 2357 if (cmd_flags) 2358 cmd_flags = BCE_NVM_COMMAND_LAST; 2359 else 2360 cmd_flags = BCE_NVM_COMMAND_FIRST | 2361 BCE_NVM_COMMAND_LAST; 2362 2363 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 2364 2365 memcpy(ret_buf, buf, 4 - extra); 2366 } 2367 else if (len32 > 0) { 2368 u8 buf[4]; 2369 2370 /* Read the first word. */ 2371 if (cmd_flags) 2372 cmd_flags = 0; 2373 else 2374 cmd_flags = BCE_NVM_COMMAND_FIRST; 2375 2376 rc = bce_nvram_read_dword(sc, offset32, ret_buf, cmd_flags); 2377 2378 /* Advance to the next dword. */ 2379 offset32 += 4; 2380 ret_buf += 4; 2381 len32 -= 4; 2382 2383 while (len32 > 4 && rc == 0) { 2384 rc = bce_nvram_read_dword(sc, offset32, ret_buf, 0); 2385 2386 /* Advance to the next dword. */ 2387 offset32 += 4; 2388 ret_buf += 4; 2389 len32 -= 4; 2390 } 2391 2392 if (rc) 2393 goto bce_nvram_read_locked_exit; 2394 2395 cmd_flags = BCE_NVM_COMMAND_LAST; 2396 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 2397 2398 memcpy(ret_buf, buf, 4 - extra); 2399 } 2400 2401bce_nvram_read_locked_exit: 2402 /* Disable access to flash interface and release the lock. */ 2403 bce_disable_nvram_access(sc); 2404 bce_release_nvram_lock(sc); 2405 2406bce_nvram_read_exit: 2407 DBEXIT(BCE_VERBOSE_NVRAM); 2408 return rc; 2409} 2410 2411 2412#ifdef BCE_NVRAM_WRITE_SUPPORT 2413/****************************************************************************/ 2414/* Write an arbitrary range of data from NVRAM. */ 2415/* */ 2416/* Prepares the NVRAM interface for write access and writes the requested */ 2417/* data from the supplied buffer. The caller is responsible for */ 2418/* calculating any appropriate CRCs. */ 2419/* */ 2420/* Returns: */ 2421/* 0 on success, positive value on failure. */ 2422/****************************************************************************/ 2423static int 2424bce_nvram_write(struct bce_softc *sc, u32 offset, u8 *data_buf, 2425 int buf_size) 2426{ 2427 u32 written, offset32, len32; 2428 u8 *buf, start[4], end[4]; 2429 int rc = 0; 2430 int align_start, align_end; 2431 2432 DBENTER(BCE_VERBOSE_NVRAM); 2433 2434 buf = data_buf; 2435 offset32 = offset; 2436 len32 = buf_size; 2437 align_start = align_end = 0; 2438 2439 if ((align_start = (offset32 & 3))) { 2440 offset32 &= ~3; 2441 len32 += align_start; 2442 if ((rc = bce_nvram_read(sc, offset32, start, 4))) 2443 goto bce_nvram_write_exit; 2444 } 2445 2446 if (len32 & 3) { 2447 if ((len32 > 4) || !align_start) { 2448 align_end = 4 - (len32 & 3); 2449 len32 += align_end; 2450 if ((rc = bce_nvram_read(sc, offset32 + len32 - 4, 2451 end, 4))) { 2452 goto bce_nvram_write_exit; 2453 } 2454 } 2455 } 2456 2457 if (align_start || align_end) { 2458 buf = malloc(len32, M_DEVBUF, M_NOWAIT); 2459 if (buf == 0) { 2460 rc = ENOMEM; 2461 goto bce_nvram_write_exit; 2462 } 2463 2464 if (align_start) { 2465 memcpy(buf, start, 4); 2466 } 2467 2468 if (align_end) { 2469 memcpy(buf + len32 - 4, end, 4); 2470 } 2471 memcpy(buf + align_start, data_buf, buf_size); 2472 } 2473 2474 written = 0; 2475 while ((written < len32) && (rc == 0)) { 2476 u32 page_start, page_end, data_start, data_end; 2477 u32 addr, cmd_flags; 2478 int i; 2479 u8 flash_buffer[264]; 2480 2481 /* Find the page_start addr */ 2482 page_start = offset32 + written; 2483 page_start -= (page_start % sc->bce_flash_info->page_size); 2484 /* Find the page_end addr */ 2485 page_end = page_start + sc->bce_flash_info->page_size; 2486 /* Find the data_start addr */ 2487 data_start = (written == 0) ? offset32 : page_start; 2488 /* Find the data_end addr */ 2489 data_end = (page_end > offset32 + len32) ? 2490 (offset32 + len32) : page_end; 2491 2492 /* Request access to the flash interface. */ 2493 if ((rc = bce_acquire_nvram_lock(sc)) != 0) 2494 goto bce_nvram_write_exit; 2495 2496 /* Enable access to flash interface */ 2497 bce_enable_nvram_access(sc); 2498 2499 cmd_flags = BCE_NVM_COMMAND_FIRST; 2500 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2501 int j; 2502 2503 /* Read the whole page into the buffer 2504 * (non-buffer flash only) */ 2505 for (j = 0; j < sc->bce_flash_info->page_size; j += 4) { 2506 if (j == (sc->bce_flash_info->page_size - 4)) { 2507 cmd_flags |= BCE_NVM_COMMAND_LAST; 2508 } 2509 rc = bce_nvram_read_dword(sc, 2510 page_start + j, 2511 &flash_buffer[j], 2512 cmd_flags); 2513 2514 if (rc) 2515 goto bce_nvram_write_locked_exit; 2516 2517 cmd_flags = 0; 2518 } 2519 } 2520 2521 /* Enable writes to flash interface (unlock write-protect) */ 2522 if ((rc = bce_enable_nvram_write(sc)) != 0) 2523 goto bce_nvram_write_locked_exit; 2524 2525 /* Erase the page */ 2526 if ((rc = bce_nvram_erase_page(sc, page_start)) != 0) 2527 goto bce_nvram_write_locked_exit; 2528 2529 /* Re-enable the write again for the actual write */ 2530 bce_enable_nvram_write(sc); 2531 2532 /* Loop to write back the buffer data from page_start to 2533 * data_start */ 2534 i = 0; 2535 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2536 for (addr = page_start; addr < data_start; 2537 addr += 4, i += 4) { 2538 2539 rc = bce_nvram_write_dword(sc, addr, 2540 &flash_buffer[i], cmd_flags); 2541 2542 if (rc != 0) 2543 goto bce_nvram_write_locked_exit; 2544 2545 cmd_flags = 0; 2546 } 2547 } 2548 2549 /* Loop to write the new data from data_start to data_end */ 2550 for (addr = data_start; addr < data_end; addr += 4, i++) { 2551 if ((addr == page_end - 4) || 2552 ((sc->bce_flash_info->flags & BCE_NV_BUFFERED) && 2553 (addr == data_end - 4))) { 2554 2555 cmd_flags |= BCE_NVM_COMMAND_LAST; 2556 } 2557 rc = bce_nvram_write_dword(sc, addr, buf, 2558 cmd_flags); 2559 2560 if (rc != 0) 2561 goto bce_nvram_write_locked_exit; 2562 2563 cmd_flags = 0; 2564 buf += 4; 2565 } 2566 2567 /* Loop to write back the buffer data from data_end 2568 * to page_end */ 2569 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2570 for (addr = data_end; addr < page_end; 2571 addr += 4, i += 4) { 2572 2573 if (addr == page_end-4) { 2574 cmd_flags = BCE_NVM_COMMAND_LAST; 2575 } 2576 rc = bce_nvram_write_dword(sc, addr, 2577 &flash_buffer[i], cmd_flags); 2578 2579 if (rc != 0) 2580 goto bce_nvram_write_locked_exit; 2581 2582 cmd_flags = 0; 2583 } 2584 } 2585 2586 /* Disable writes to flash interface (lock write-protect) */ 2587 bce_disable_nvram_write(sc); 2588 2589 /* Disable access to flash interface */ 2590 bce_disable_nvram_access(sc); 2591 bce_release_nvram_lock(sc); 2592 2593 /* Increment written */ 2594 written += data_end - data_start; 2595 } 2596 2597 goto bce_nvram_write_exit; 2598 2599bce_nvram_write_locked_exit: 2600 bce_disable_nvram_write(sc); 2601 bce_disable_nvram_access(sc); 2602 bce_release_nvram_lock(sc); 2603 2604bce_nvram_write_exit: 2605 if (align_start || align_end) 2606 free(buf, M_DEVBUF); 2607 2608 DBEXIT(BCE_VERBOSE_NVRAM); 2609 return (rc); 2610} 2611#endif /* BCE_NVRAM_WRITE_SUPPORT */ 2612 2613 2614/****************************************************************************/ 2615/* Verifies that NVRAM is accessible and contains valid data. */ 2616/* */ 2617/* Reads the configuration data from NVRAM and verifies that the CRC is */ 2618/* correct. */ 2619/* */ 2620/* Returns: */ 2621/* 0 on success, positive value on failure. */ 2622/****************************************************************************/ 2623static int 2624bce_nvram_test(struct bce_softc *sc) 2625{ 2626 u32 buf[BCE_NVRAM_SIZE / 4]; 2627 u8 *data = (u8 *) buf; 2628 int rc = 0; 2629 u32 magic, csum; 2630 2631 DBENTER(BCE_VERBOSE_NVRAM | BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 2632 2633 /* 2634 * Check that the device NVRAM is valid by reading 2635 * the magic value at offset 0. 2636 */ 2637 if ((rc = bce_nvram_read(sc, 0, data, 4)) != 0) { 2638 BCE_PRINTF("%s(%d): Unable to read NVRAM!\n", 2639 __FILE__, __LINE__); 2640 goto bce_nvram_test_exit; 2641 } 2642 2643 /* 2644 * Verify that offset 0 of the NVRAM contains 2645 * a valid magic number. 2646 */ 2647 magic = bce_be32toh(buf[0]); 2648 if (magic != BCE_NVRAM_MAGIC) { 2649 rc = ENODEV; 2650 BCE_PRINTF("%s(%d): Invalid NVRAM magic value! " 2651 "Expected: 0x%08X, Found: 0x%08X\n", 2652 __FILE__, __LINE__, BCE_NVRAM_MAGIC, magic); 2653 goto bce_nvram_test_exit; 2654 } 2655 2656 /* 2657 * Verify that the device NVRAM includes valid 2658 * configuration data. 2659 */ 2660 if ((rc = bce_nvram_read(sc, 0x100, data, BCE_NVRAM_SIZE)) != 0) { 2661 BCE_PRINTF("%s(%d): Unable to read manufacturing " 2662 "Information from NVRAM!\n", __FILE__, __LINE__); 2663 goto bce_nvram_test_exit; 2664 } 2665 2666 csum = ether_crc32_le(data, 0x100); 2667 if (csum != BCE_CRC32_RESIDUAL) { 2668 rc = ENODEV; 2669 BCE_PRINTF("%s(%d): Invalid manufacturing information " 2670 "NVRAM CRC! Expected: 0x%08X, Found: 0x%08X\n", 2671 __FILE__, __LINE__, BCE_CRC32_RESIDUAL, csum); 2672 goto bce_nvram_test_exit; 2673 } 2674 2675 csum = ether_crc32_le(data + 0x100, 0x100); 2676 if (csum != BCE_CRC32_RESIDUAL) { 2677 rc = ENODEV; 2678 BCE_PRINTF("%s(%d): Invalid feature configuration " 2679 "information NVRAM CRC! Expected: 0x%08X, " 2680 "Found: 08%08X\n", __FILE__, __LINE__, 2681 BCE_CRC32_RESIDUAL, csum); 2682 } 2683 2684bce_nvram_test_exit: 2685 DBEXIT(BCE_VERBOSE_NVRAM | BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 2686 return rc; 2687} 2688 2689 2690/****************************************************************************/ 2691/* Identifies the current media type of the controller and sets the PHY */ 2692/* address. */ 2693/* */ 2694/* Returns: */ 2695/* Nothing. */ 2696/****************************************************************************/ 2697static void 2698bce_get_media(struct bce_softc *sc) 2699{ 2700 u32 val; 2701 2702 DBENTER(BCE_VERBOSE_PHY); 2703 2704 /* Assume PHY address for copper controllers. */ 2705 sc->bce_phy_addr = 1; 2706 2707 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 2708 u32 val = REG_RD(sc, BCE_MISC_DUAL_MEDIA_CTRL); 2709 u32 bond_id = val & BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID; 2710 u32 strap; 2711 2712 /* 2713 * The BCM5709S is software configurable 2714 * for Copper or SerDes operation. 2715 */ 2716 if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) { 2717 DBPRINT(sc, BCE_INFO_LOAD, "5709 bonded " 2718 "for copper.\n"); 2719 goto bce_get_media_exit; 2720 } else if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) { 2721 DBPRINT(sc, BCE_INFO_LOAD, "5709 bonded " 2722 "for dual media.\n"); 2723 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 2724 goto bce_get_media_exit; 2725 } 2726 2727 if (val & BCE_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE) 2728 strap = (val & 2729 BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21; 2730 else 2731 strap = (val & 2732 BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8; 2733 2734 if (pci_get_function(sc->bce_dev) == 0) { 2735 switch (strap) { 2736 case 0x4: 2737 case 0x5: 2738 case 0x6: 2739 DBPRINT(sc, BCE_INFO_LOAD, 2740 "BCM5709 s/w configured for SerDes.\n"); 2741 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 2742 break; 2743 default: 2744 DBPRINT(sc, BCE_INFO_LOAD, 2745 "BCM5709 s/w configured for Copper.\n"); 2746 break; 2747 } 2748 } else { 2749 switch (strap) { 2750 case 0x1: 2751 case 0x2: 2752 case 0x4: 2753 DBPRINT(sc, BCE_INFO_LOAD, 2754 "BCM5709 s/w configured for SerDes.\n"); 2755 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 2756 break; 2757 default: 2758 DBPRINT(sc, BCE_INFO_LOAD, 2759 "BCM5709 s/w configured for Copper.\n"); 2760 break; 2761 } 2762 } 2763 2764 } else if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT) 2765 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 2766 2767 if (sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) { 2768 2769 sc->bce_flags |= BCE_NO_WOL_FLAG; 2770 2771 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) 2772 sc->bce_phy_flags |= BCE_PHY_IEEE_CLAUSE_45_FLAG; 2773 2774 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) { 2775 /* 5708S/09S/16S use a separate PHY for SerDes. */ 2776 sc->bce_phy_addr = 2; 2777 2778 val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG); 2779 if (val & BCE_SHARED_HW_CFG_PHY_2_5G) { 2780 sc->bce_phy_flags |= 2781 BCE_PHY_2_5G_CAPABLE_FLAG; 2782 DBPRINT(sc, BCE_INFO_LOAD, "Found 2.5Gb " 2783 "capable adapter\n"); 2784 } 2785 } 2786 } else if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) || 2787 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)) 2788 sc->bce_phy_flags |= BCE_PHY_CRC_FIX_FLAG; 2789 2790bce_get_media_exit: 2791 DBPRINT(sc, (BCE_INFO_LOAD | BCE_INFO_PHY), 2792 "Using PHY address %d.\n", sc->bce_phy_addr); 2793 2794 DBEXIT(BCE_VERBOSE_PHY); 2795} 2796 2797 2798/****************************************************************************/ 2799/* Performs PHY initialization required before MII drivers access the */ 2800/* device. */ 2801/* */ 2802/* Returns: */ 2803/* Nothing. */ 2804/****************************************************************************/ 2805static void 2806bce_init_media(struct bce_softc *sc) 2807{ 2808 if ((sc->bce_phy_flags & BCE_PHY_IEEE_CLAUSE_45_FLAG) != 0) { 2809 /* 2810 * Configure 5709S/5716S PHYs to use traditional IEEE 2811 * Clause 22 method. Otherwise we have no way to attach 2812 * the PHY in mii(4) layer. PHY specific configuration 2813 * is done in mii layer. 2814 */ 2815 2816 /* Select auto-negotiation MMD of the PHY. */ 2817 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr, 2818 BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_ADDR_EXT); 2819 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr, 2820 BRGPHY_ADDR_EXT, BRGPHY_ADDR_EXT_AN_MMD); 2821 2822 /* Set IEEE0 block of AN MMD (assumed in brgphy(4) code). */ 2823 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr, 2824 BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 2825 } 2826} 2827 2828 2829/****************************************************************************/ 2830/* Free any DMA memory owned by the driver. */ 2831/* */ 2832/* Scans through each data structre that requires DMA memory and frees */ 2833/* the memory if allocated. */ 2834/* */ 2835/* Returns: */ 2836/* Nothing. */ 2837/****************************************************************************/ 2838static void 2839bce_dma_free(struct bce_softc *sc) 2840{ 2841 int i; 2842 2843 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_UNLOAD | BCE_VERBOSE_CTX); 2844 2845 /* Free, unmap, and destroy the status block. */ 2846 if (sc->status_block != NULL) { 2847 bus_dmamem_free( 2848 sc->status_tag, 2849 sc->status_block, 2850 sc->status_map); 2851 sc->status_block = NULL; 2852 } 2853 2854 if (sc->status_map != NULL) { 2855 bus_dmamap_unload( 2856 sc->status_tag, 2857 sc->status_map); 2858 bus_dmamap_destroy(sc->status_tag, 2859 sc->status_map); 2860 sc->status_map = NULL; 2861 } 2862 2863 if (sc->status_tag != NULL) { 2864 bus_dma_tag_destroy(sc->status_tag); 2865 sc->status_tag = NULL; 2866 } 2867 2868 2869 /* Free, unmap, and destroy the statistics block. */ 2870 if (sc->stats_block != NULL) { 2871 bus_dmamem_free( 2872 sc->stats_tag, 2873 sc->stats_block, 2874 sc->stats_map); 2875 sc->stats_block = NULL; 2876 } 2877 2878 if (sc->stats_map != NULL) { 2879 bus_dmamap_unload( 2880 sc->stats_tag, 2881 sc->stats_map); 2882 bus_dmamap_destroy(sc->stats_tag, 2883 sc->stats_map); 2884 sc->stats_map = NULL; 2885 } 2886 2887 if (sc->stats_tag != NULL) { 2888 bus_dma_tag_destroy(sc->stats_tag); 2889 sc->stats_tag = NULL; 2890 } 2891 2892 2893 /* Free, unmap and destroy all context memory pages. */ 2894 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 2895 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 2896 for (i = 0; i < sc->ctx_pages; i++ ) { 2897 if (sc->ctx_block[i] != NULL) { 2898 bus_dmamem_free( 2899 sc->ctx_tag, 2900 sc->ctx_block[i], 2901 sc->ctx_map[i]); 2902 sc->ctx_block[i] = NULL; 2903 } 2904 2905 if (sc->ctx_map[i] != NULL) { 2906 bus_dmamap_unload( 2907 sc->ctx_tag, 2908 sc->ctx_map[i]); 2909 bus_dmamap_destroy( 2910 sc->ctx_tag, 2911 sc->ctx_map[i]); 2912 sc->ctx_map[i] = NULL; 2913 } 2914 } 2915 2916 /* Destroy the context memory tag. */ 2917 if (sc->ctx_tag != NULL) { 2918 bus_dma_tag_destroy(sc->ctx_tag); 2919 sc->ctx_tag = NULL; 2920 } 2921 } 2922 2923 2924 /* Free, unmap and destroy all TX buffer descriptor chain pages. */ 2925 for (i = 0; i < TX_PAGES; i++ ) { 2926 if (sc->tx_bd_chain[i] != NULL) { 2927 bus_dmamem_free( 2928 sc->tx_bd_chain_tag, 2929 sc->tx_bd_chain[i], 2930 sc->tx_bd_chain_map[i]); 2931 sc->tx_bd_chain[i] = NULL; 2932 } 2933 2934 if (sc->tx_bd_chain_map[i] != NULL) { 2935 bus_dmamap_unload( 2936 sc->tx_bd_chain_tag, 2937 sc->tx_bd_chain_map[i]); 2938 bus_dmamap_destroy( 2939 sc->tx_bd_chain_tag, 2940 sc->tx_bd_chain_map[i]); 2941 sc->tx_bd_chain_map[i] = NULL; 2942 } 2943 } 2944 2945 /* Destroy the TX buffer descriptor tag. */ 2946 if (sc->tx_bd_chain_tag != NULL) { 2947 bus_dma_tag_destroy(sc->tx_bd_chain_tag); 2948 sc->tx_bd_chain_tag = NULL; 2949 } 2950 2951 2952 /* Free, unmap and destroy all RX buffer descriptor chain pages. */ 2953 for (i = 0; i < RX_PAGES; i++ ) { 2954 if (sc->rx_bd_chain[i] != NULL) { 2955 bus_dmamem_free( 2956 sc->rx_bd_chain_tag, 2957 sc->rx_bd_chain[i], 2958 sc->rx_bd_chain_map[i]); 2959 sc->rx_bd_chain[i] = NULL; 2960 } 2961 2962 if (sc->rx_bd_chain_map[i] != NULL) { 2963 bus_dmamap_unload( 2964 sc->rx_bd_chain_tag, 2965 sc->rx_bd_chain_map[i]); 2966 bus_dmamap_destroy( 2967 sc->rx_bd_chain_tag, 2968 sc->rx_bd_chain_map[i]); 2969 sc->rx_bd_chain_map[i] = NULL; 2970 } 2971 } 2972 2973 /* Destroy the RX buffer descriptor tag. */ 2974 if (sc->rx_bd_chain_tag != NULL) { 2975 bus_dma_tag_destroy(sc->rx_bd_chain_tag); 2976 sc->rx_bd_chain_tag = NULL; 2977 } 2978 2979 2980#ifdef BCE_JUMBO_HDRSPLIT 2981 /* Free, unmap and destroy all page buffer descriptor chain pages. */ 2982 for (i = 0; i < PG_PAGES; i++ ) { 2983 if (sc->pg_bd_chain[i] != NULL) { 2984 bus_dmamem_free( 2985 sc->pg_bd_chain_tag, 2986 sc->pg_bd_chain[i], 2987 sc->pg_bd_chain_map[i]); 2988 sc->pg_bd_chain[i] = NULL; 2989 } 2990 2991 if (sc->pg_bd_chain_map[i] != NULL) { 2992 bus_dmamap_unload( 2993 sc->pg_bd_chain_tag, 2994 sc->pg_bd_chain_map[i]); 2995 bus_dmamap_destroy( 2996 sc->pg_bd_chain_tag, 2997 sc->pg_bd_chain_map[i]); 2998 sc->pg_bd_chain_map[i] = NULL; 2999 } 3000 } 3001 3002 /* Destroy the page buffer descriptor tag. */ 3003 if (sc->pg_bd_chain_tag != NULL) { 3004 bus_dma_tag_destroy(sc->pg_bd_chain_tag); 3005 sc->pg_bd_chain_tag = NULL; 3006 } 3007#endif 3008 3009 3010 /* Unload and destroy the TX mbuf maps. */ 3011 for (i = 0; i < TOTAL_TX_BD; i++) { 3012 if (sc->tx_mbuf_map[i] != NULL) { 3013 bus_dmamap_unload(sc->tx_mbuf_tag, 3014 sc->tx_mbuf_map[i]); 3015 bus_dmamap_destroy(sc->tx_mbuf_tag, 3016 sc->tx_mbuf_map[i]); 3017 sc->tx_mbuf_map[i] = NULL; 3018 } 3019 } 3020 3021 /* Destroy the TX mbuf tag. */ 3022 if (sc->tx_mbuf_tag != NULL) { 3023 bus_dma_tag_destroy(sc->tx_mbuf_tag); 3024 sc->tx_mbuf_tag = NULL; 3025 } 3026 3027 /* Unload and destroy the RX mbuf maps. */ 3028 for (i = 0; i < TOTAL_RX_BD; i++) { 3029 if (sc->rx_mbuf_map[i] != NULL) { 3030 bus_dmamap_unload(sc->rx_mbuf_tag, 3031 sc->rx_mbuf_map[i]); 3032 bus_dmamap_destroy(sc->rx_mbuf_tag, 3033 sc->rx_mbuf_map[i]); 3034 sc->rx_mbuf_map[i] = NULL; 3035 } 3036 } 3037 3038 /* Destroy the RX mbuf tag. */ 3039 if (sc->rx_mbuf_tag != NULL) { 3040 bus_dma_tag_destroy(sc->rx_mbuf_tag); 3041 sc->rx_mbuf_tag = NULL; 3042 } 3043 3044#ifdef BCE_JUMBO_HDRSPLIT 3045 /* Unload and destroy the page mbuf maps. */ 3046 for (i = 0; i < TOTAL_PG_BD; i++) { 3047 if (sc->pg_mbuf_map[i] != NULL) { 3048 bus_dmamap_unload(sc->pg_mbuf_tag, 3049 sc->pg_mbuf_map[i]); 3050 bus_dmamap_destroy(sc->pg_mbuf_tag, 3051 sc->pg_mbuf_map[i]); 3052 sc->pg_mbuf_map[i] = NULL; 3053 } 3054 } 3055 3056 /* Destroy the page mbuf tag. */ 3057 if (sc->pg_mbuf_tag != NULL) { 3058 bus_dma_tag_destroy(sc->pg_mbuf_tag); 3059 sc->pg_mbuf_tag = NULL; 3060 } 3061#endif 3062 3063 /* Destroy the parent tag */ 3064 if (sc->parent_tag != NULL) { 3065 bus_dma_tag_destroy(sc->parent_tag); 3066 sc->parent_tag = NULL; 3067 } 3068 3069 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_UNLOAD | BCE_VERBOSE_CTX); 3070} 3071 3072 3073/****************************************************************************/ 3074/* Get DMA memory from the OS. */ 3075/* */ 3076/* Validates that the OS has provided DMA buffers in response to a */ 3077/* bus_dmamap_load() call and saves the physical address of those buffers. */ 3078/* When the callback is used the OS will return 0 for the mapping function */ 3079/* (bus_dmamap_load()) so we use the value of map_arg->maxsegs to pass any */ 3080/* failures back to the caller. */ 3081/* */ 3082/* Returns: */ 3083/* Nothing. */ 3084/****************************************************************************/ 3085static void 3086bce_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 3087{ 3088 bus_addr_t *busaddr = arg; 3089 3090 /* Simulate a mapping failure. */ 3091 DBRUNIF(DB_RANDOMTRUE(dma_map_addr_failed_sim_control), 3092 error = ENOMEM); 3093 3094 /* ToDo: How to increment debug sim_count variable here? */ 3095 3096 /* Check for an error and signal the caller that an error occurred. */ 3097 if (error) { 3098 *busaddr = 0; 3099 } else { 3100 *busaddr = segs->ds_addr; 3101 } 3102 3103 return; 3104} 3105 3106 3107/****************************************************************************/ 3108/* Allocate any DMA memory needed by the driver. */ 3109/* */ 3110/* Allocates DMA memory needed for the various global structures needed by */ 3111/* hardware. */ 3112/* */ 3113/* Memory alignment requirements: */ 3114/* +-----------------+----------+----------+----------+----------+ */ 3115/* | | 5706 | 5708 | 5709 | 5716 | */ 3116/* +-----------------+----------+----------+----------+----------+ */ 3117/* |Status Block | 8 bytes | 8 bytes | 16 bytes | 16 bytes | */ 3118/* |Statistics Block | 8 bytes | 8 bytes | 16 bytes | 16 bytes | */ 3119/* |RX Buffers | 16 bytes | 16 bytes | 16 bytes | 16 bytes | */ 3120/* |PG Buffers | none | none | none | none | */ 3121/* |TX Buffers | none | none | none | none | */ 3122/* |Chain Pages(1) | 4KiB | 4KiB | 4KiB | 4KiB | */ 3123/* |Context Memory | | | | | */ 3124/* +-----------------+----------+----------+----------+----------+ */ 3125/* */ 3126/* (1) Must align with CPU page size (BCM_PAGE_SZIE). */ 3127/* */ 3128/* Returns: */ 3129/* 0 for success, positive value for failure. */ 3130/****************************************************************************/ 3131static int 3132bce_dma_alloc(device_t dev) 3133{ 3134 struct bce_softc *sc; 3135 int i, error, rc = 0; 3136 bus_size_t max_size, max_seg_size; 3137 int max_segments; 3138 3139 sc = device_get_softc(dev); 3140 3141 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 3142 3143 /* 3144 * Allocate the parent bus DMA tag appropriate for PCI. 3145 */ 3146 if (bus_dma_tag_create(NULL, 1, BCE_DMA_BOUNDARY, 3147 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, 3148 MAXBSIZE, BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE_32BIT, 3149 0, NULL, NULL, &sc->parent_tag)) { 3150 BCE_PRINTF("%s(%d): Could not allocate parent DMA tag!\n", 3151 __FILE__, __LINE__); 3152 rc = ENOMEM; 3153 goto bce_dma_alloc_exit; 3154 } 3155 3156 /* 3157 * Create a DMA tag for the status block, allocate and clear the 3158 * memory, map the memory into DMA space, and fetch the physical 3159 * address of the block. 3160 */ 3161 if (bus_dma_tag_create(sc->parent_tag, BCE_DMA_ALIGN, 3162 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, 3163 NULL, NULL, BCE_STATUS_BLK_SZ, 1, BCE_STATUS_BLK_SZ, 3164 0, NULL, NULL, &sc->status_tag)) { 3165 BCE_PRINTF("%s(%d): Could not allocate status block " 3166 "DMA tag!\n", __FILE__, __LINE__); 3167 rc = ENOMEM; 3168 goto bce_dma_alloc_exit; 3169 } 3170 3171 if(bus_dmamem_alloc(sc->status_tag, (void **)&sc->status_block, 3172 BUS_DMA_NOWAIT, &sc->status_map)) { 3173 BCE_PRINTF("%s(%d): Could not allocate status block " 3174 "DMA memory!\n", __FILE__, __LINE__); 3175 rc = ENOMEM; 3176 goto bce_dma_alloc_exit; 3177 } 3178 3179 bzero((char *)sc->status_block, BCE_STATUS_BLK_SZ); 3180 3181 error = bus_dmamap_load(sc->status_tag, sc->status_map, 3182 sc->status_block, BCE_STATUS_BLK_SZ, bce_dma_map_addr, 3183 &sc->status_block_paddr, BUS_DMA_NOWAIT); 3184 3185 if (error) { 3186 BCE_PRINTF("%s(%d): Could not map status block " 3187 "DMA memory!\n", __FILE__, __LINE__); 3188 rc = ENOMEM; 3189 goto bce_dma_alloc_exit; 3190 } 3191 3192 DBPRINT(sc, BCE_INFO_LOAD, "%s(): status_block_paddr = 0x%jX\n", 3193 __FUNCTION__, (uintmax_t) sc->status_block_paddr); 3194 3195 /* 3196 * Create a DMA tag for the statistics block, allocate and clear the 3197 * memory, map the memory into DMA space, and fetch the physical 3198 * address of the block. 3199 */ 3200 if (bus_dma_tag_create(sc->parent_tag, BCE_DMA_ALIGN, 3201 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, 3202 NULL, NULL, BCE_STATS_BLK_SZ, 1, BCE_STATS_BLK_SZ, 3203 0, NULL, NULL, &sc->stats_tag)) { 3204 BCE_PRINTF("%s(%d): Could not allocate statistics block " 3205 "DMA tag!\n", __FILE__, __LINE__); 3206 rc = ENOMEM; 3207 goto bce_dma_alloc_exit; 3208 } 3209 3210 if (bus_dmamem_alloc(sc->stats_tag, (void **)&sc->stats_block, 3211 BUS_DMA_NOWAIT, &sc->stats_map)) { 3212 BCE_PRINTF("%s(%d): Could not allocate statistics block " 3213 "DMA memory!\n", __FILE__, __LINE__); 3214 rc = ENOMEM; 3215 goto bce_dma_alloc_exit; 3216 } 3217 3218 bzero((char *)sc->stats_block, BCE_STATS_BLK_SZ); 3219 3220 error = bus_dmamap_load(sc->stats_tag, sc->stats_map, 3221 sc->stats_block, BCE_STATS_BLK_SZ, bce_dma_map_addr, 3222 &sc->stats_block_paddr, BUS_DMA_NOWAIT); 3223 3224 if(error) { 3225 BCE_PRINTF("%s(%d): Could not map statistics block " 3226 "DMA memory!\n", __FILE__, __LINE__); 3227 rc = ENOMEM; 3228 goto bce_dma_alloc_exit; 3229 } 3230 3231 DBPRINT(sc, BCE_INFO_LOAD, "%s(): stats_block_paddr = 0x%jX\n", 3232 __FUNCTION__, (uintmax_t) sc->stats_block_paddr); 3233 3234 /* BCM5709 uses host memory as cache for context memory. */ 3235 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 3236 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 3237 sc->ctx_pages = 0x2000 / BCM_PAGE_SIZE; 3238 if (sc->ctx_pages == 0) 3239 sc->ctx_pages = 1; 3240 3241 DBRUNIF((sc->ctx_pages > 512), 3242 BCE_PRINTF("%s(%d): Too many CTX pages! %d > 512\n", 3243 __FILE__, __LINE__, sc->ctx_pages)); 3244 3245 /* 3246 * Create a DMA tag for the context pages, 3247 * allocate and clear the memory, map the 3248 * memory into DMA space, and fetch the 3249 * physical address of the block. 3250 */ 3251 if(bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 3252 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, 3253 NULL, NULL, BCM_PAGE_SIZE, 1, BCM_PAGE_SIZE, 3254 0, NULL, NULL, &sc->ctx_tag)) { 3255 BCE_PRINTF("%s(%d): Could not allocate CTX " 3256 "DMA tag!\n", __FILE__, __LINE__); 3257 rc = ENOMEM; 3258 goto bce_dma_alloc_exit; 3259 } 3260 3261 for (i = 0; i < sc->ctx_pages; i++) { 3262 3263 if(bus_dmamem_alloc(sc->ctx_tag, 3264 (void **)&sc->ctx_block[i], 3265 BUS_DMA_NOWAIT, 3266 &sc->ctx_map[i])) { 3267 BCE_PRINTF("%s(%d): Could not allocate CTX " 3268 "DMA memory!\n", __FILE__, __LINE__); 3269 rc = ENOMEM; 3270 goto bce_dma_alloc_exit; 3271 } 3272 3273 bzero((char *)sc->ctx_block[i], BCM_PAGE_SIZE); 3274 3275 error = bus_dmamap_load(sc->ctx_tag, sc->ctx_map[i], 3276 sc->ctx_block[i], BCM_PAGE_SIZE, bce_dma_map_addr, 3277 &sc->ctx_paddr[i], BUS_DMA_NOWAIT); 3278 3279 if (error) { 3280 BCE_PRINTF("%s(%d): Could not map CTX " 3281 "DMA memory!\n", __FILE__, __LINE__); 3282 rc = ENOMEM; 3283 goto bce_dma_alloc_exit; 3284 } 3285 3286 DBPRINT(sc, BCE_INFO_LOAD, "%s(): ctx_paddr[%d] " 3287 "= 0x%jX\n", __FUNCTION__, i, 3288 (uintmax_t) sc->ctx_paddr[i]); 3289 } 3290 } 3291 3292 /* 3293 * Create a DMA tag for the TX buffer descriptor chain, 3294 * allocate and clear the memory, and fetch the 3295 * physical address of the block. 3296 */ 3297 if(bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, BCE_DMA_BOUNDARY, 3298 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, 3299 BCE_TX_CHAIN_PAGE_SZ, 1, BCE_TX_CHAIN_PAGE_SZ, 0, 3300 NULL, NULL, &sc->tx_bd_chain_tag)) { 3301 BCE_PRINTF("%s(%d): Could not allocate TX descriptor " 3302 "chain DMA tag!\n", __FILE__, __LINE__); 3303 rc = ENOMEM; 3304 goto bce_dma_alloc_exit; 3305 } 3306 3307 for (i = 0; i < TX_PAGES; i++) { 3308 3309 if(bus_dmamem_alloc(sc->tx_bd_chain_tag, 3310 (void **)&sc->tx_bd_chain[i], BUS_DMA_NOWAIT, 3311 &sc->tx_bd_chain_map[i])) { 3312 BCE_PRINTF("%s(%d): Could not allocate TX descriptor " 3313 "chain DMA memory!\n", __FILE__, __LINE__); 3314 rc = ENOMEM; 3315 goto bce_dma_alloc_exit; 3316 } 3317 3318 error = bus_dmamap_load(sc->tx_bd_chain_tag, 3319 sc->tx_bd_chain_map[i], sc->tx_bd_chain[i], 3320 BCE_TX_CHAIN_PAGE_SZ, bce_dma_map_addr, 3321 &sc->tx_bd_chain_paddr[i], BUS_DMA_NOWAIT); 3322 3323 if (error) { 3324 BCE_PRINTF("%s(%d): Could not map TX descriptor " 3325 "chain DMA memory!\n", __FILE__, __LINE__); 3326 rc = ENOMEM; 3327 goto bce_dma_alloc_exit; 3328 } 3329 3330 DBPRINT(sc, BCE_INFO_LOAD, "%s(): tx_bd_chain_paddr[%d] = " 3331 "0x%jX\n", __FUNCTION__, i, 3332 (uintmax_t) sc->tx_bd_chain_paddr[i]); 3333 } 3334 3335 /* Check the required size before mapping to conserve resources. */ 3336 if (bce_tso_enable) { 3337 max_size = BCE_TSO_MAX_SIZE; 3338 max_segments = BCE_MAX_SEGMENTS; 3339 max_seg_size = BCE_TSO_MAX_SEG_SIZE; 3340 } else { 3341 max_size = MCLBYTES * BCE_MAX_SEGMENTS; 3342 max_segments = BCE_MAX_SEGMENTS; 3343 max_seg_size = MCLBYTES; 3344 } 3345 3346 /* Create a DMA tag for TX mbufs. */ 3347 if (bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY, 3348 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, max_size, 3349 max_segments, max_seg_size, 0, NULL, NULL, &sc->tx_mbuf_tag)) { 3350 BCE_PRINTF("%s(%d): Could not allocate TX mbuf DMA tag!\n", 3351 __FILE__, __LINE__); 3352 rc = ENOMEM; 3353 goto bce_dma_alloc_exit; 3354 } 3355 3356 /* Create DMA maps for the TX mbufs clusters. */ 3357 for (i = 0; i < TOTAL_TX_BD; i++) { 3358 if (bus_dmamap_create(sc->tx_mbuf_tag, BUS_DMA_NOWAIT, 3359 &sc->tx_mbuf_map[i])) { 3360 BCE_PRINTF("%s(%d): Unable to create TX mbuf DMA " 3361 "map!\n", __FILE__, __LINE__); 3362 rc = ENOMEM; 3363 goto bce_dma_alloc_exit; 3364 } 3365 } 3366 3367 /* 3368 * Create a DMA tag for the RX buffer descriptor chain, 3369 * allocate and clear the memory, and fetch the physical 3370 * address of the blocks. 3371 */ 3372 if (bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 3373 BCE_DMA_BOUNDARY, BUS_SPACE_MAXADDR, 3374 sc->max_bus_addr, NULL, NULL, 3375 BCE_RX_CHAIN_PAGE_SZ, 1, BCE_RX_CHAIN_PAGE_SZ, 3376 0, NULL, NULL, &sc->rx_bd_chain_tag)) { 3377 BCE_PRINTF("%s(%d): Could not allocate RX descriptor chain " 3378 "DMA tag!\n", __FILE__, __LINE__); 3379 rc = ENOMEM; 3380 goto bce_dma_alloc_exit; 3381 } 3382 3383 for (i = 0; i < RX_PAGES; i++) { 3384 3385 if (bus_dmamem_alloc(sc->rx_bd_chain_tag, 3386 (void **)&sc->rx_bd_chain[i], BUS_DMA_NOWAIT, 3387 &sc->rx_bd_chain_map[i])) { 3388 BCE_PRINTF("%s(%d): Could not allocate RX descriptor " 3389 "chain DMA memory!\n", __FILE__, __LINE__); 3390 rc = ENOMEM; 3391 goto bce_dma_alloc_exit; 3392 } 3393 3394 bzero((char *)sc->rx_bd_chain[i], BCE_RX_CHAIN_PAGE_SZ); 3395 3396 error = bus_dmamap_load(sc->rx_bd_chain_tag, 3397 sc->rx_bd_chain_map[i], sc->rx_bd_chain[i], 3398 BCE_RX_CHAIN_PAGE_SZ, bce_dma_map_addr, 3399 &sc->rx_bd_chain_paddr[i], BUS_DMA_NOWAIT); 3400 3401 if (error) { 3402 BCE_PRINTF("%s(%d): Could not map RX descriptor " 3403 "chain DMA memory!\n", __FILE__, __LINE__); 3404 rc = ENOMEM; 3405 goto bce_dma_alloc_exit; 3406 } 3407 3408 DBPRINT(sc, BCE_INFO_LOAD, "%s(): rx_bd_chain_paddr[%d] = " 3409 "0x%jX\n", __FUNCTION__, i, 3410 (uintmax_t) sc->rx_bd_chain_paddr[i]); 3411 } 3412 3413 /* 3414 * Create a DMA tag for RX mbufs. 3415 */ 3416#ifdef BCE_JUMBO_HDRSPLIT 3417 max_size = max_seg_size = ((sc->rx_bd_mbuf_alloc_size < MCLBYTES) ? 3418 MCLBYTES : sc->rx_bd_mbuf_alloc_size); 3419#else 3420 max_size = max_seg_size = MJUM9BYTES; 3421#endif 3422 max_segments = 1; 3423 3424 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Creating rx_mbuf_tag " 3425 "(max size = 0x%jX max segments = %d, max segment " 3426 "size = 0x%jX)\n", __FUNCTION__, (uintmax_t) max_size, 3427 max_segments, (uintmax_t) max_seg_size); 3428 3429 if (bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY, 3430 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, max_size, 3431 max_segments, max_seg_size, 0, NULL, NULL, &sc->rx_mbuf_tag)) { 3432 BCE_PRINTF("%s(%d): Could not allocate RX mbuf DMA tag!\n", 3433 __FILE__, __LINE__); 3434 rc = ENOMEM; 3435 goto bce_dma_alloc_exit; 3436 } 3437 3438 /* Create DMA maps for the RX mbuf clusters. */ 3439 for (i = 0; i < TOTAL_RX_BD; i++) { 3440 if (bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_NOWAIT, 3441 &sc->rx_mbuf_map[i])) { 3442 BCE_PRINTF("%s(%d): Unable to create RX mbuf " 3443 "DMA map!\n", __FILE__, __LINE__); 3444 rc = ENOMEM; 3445 goto bce_dma_alloc_exit; 3446 } 3447 } 3448 3449#ifdef BCE_JUMBO_HDRSPLIT 3450 /* 3451 * Create a DMA tag for the page buffer descriptor chain, 3452 * allocate and clear the memory, and fetch the physical 3453 * address of the blocks. 3454 */ 3455 if (bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 3456 BCE_DMA_BOUNDARY, BUS_SPACE_MAXADDR, sc->max_bus_addr, 3457 NULL, NULL, BCE_PG_CHAIN_PAGE_SZ, 1, BCE_PG_CHAIN_PAGE_SZ, 3458 0, NULL, NULL, &sc->pg_bd_chain_tag)) { 3459 BCE_PRINTF("%s(%d): Could not allocate page descriptor " 3460 "chain DMA tag!\n", __FILE__, __LINE__); 3461 rc = ENOMEM; 3462 goto bce_dma_alloc_exit; 3463 } 3464 3465 for (i = 0; i < PG_PAGES; i++) { 3466 3467 if (bus_dmamem_alloc(sc->pg_bd_chain_tag, 3468 (void **)&sc->pg_bd_chain[i], BUS_DMA_NOWAIT, 3469 &sc->pg_bd_chain_map[i])) { 3470 BCE_PRINTF("%s(%d): Could not allocate page " 3471 "descriptor chain DMA memory!\n", 3472 __FILE__, __LINE__); 3473 rc = ENOMEM; 3474 goto bce_dma_alloc_exit; 3475 } 3476 3477 bzero((char *)sc->pg_bd_chain[i], BCE_PG_CHAIN_PAGE_SZ); 3478 3479 error = bus_dmamap_load(sc->pg_bd_chain_tag, 3480 sc->pg_bd_chain_map[i], sc->pg_bd_chain[i], 3481 BCE_PG_CHAIN_PAGE_SZ, bce_dma_map_addr, 3482 &sc->pg_bd_chain_paddr[i], BUS_DMA_NOWAIT); 3483 3484 if (error) { 3485 BCE_PRINTF("%s(%d): Could not map page descriptor " 3486 "chain DMA memory!\n", __FILE__, __LINE__); 3487 rc = ENOMEM; 3488 goto bce_dma_alloc_exit; 3489 } 3490 3491 DBPRINT(sc, BCE_INFO_LOAD, "%s(): pg_bd_chain_paddr[%d] = " 3492 "0x%jX\n", __FUNCTION__, i, 3493 (uintmax_t) sc->pg_bd_chain_paddr[i]); 3494 } 3495 3496 /* 3497 * Create a DMA tag for page mbufs. 3498 */ 3499 max_size = max_seg_size = ((sc->pg_bd_mbuf_alloc_size < MCLBYTES) ? 3500 MCLBYTES : sc->pg_bd_mbuf_alloc_size); 3501 3502 if (bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY, 3503 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, 3504 max_size, 1, max_seg_size, 0, NULL, NULL, &sc->pg_mbuf_tag)) { 3505 BCE_PRINTF("%s(%d): Could not allocate page mbuf " 3506 "DMA tag!\n", __FILE__, __LINE__); 3507 rc = ENOMEM; 3508 goto bce_dma_alloc_exit; 3509 } 3510 3511 /* Create DMA maps for the page mbuf clusters. */ 3512 for (i = 0; i < TOTAL_PG_BD; i++) { 3513 if (bus_dmamap_create(sc->pg_mbuf_tag, BUS_DMA_NOWAIT, 3514 &sc->pg_mbuf_map[i])) { 3515 BCE_PRINTF("%s(%d): Unable to create page mbuf " 3516 "DMA map!\n", __FILE__, __LINE__); 3517 rc = ENOMEM; 3518 goto bce_dma_alloc_exit; 3519 } 3520 } 3521#endif 3522 3523bce_dma_alloc_exit: 3524 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 3525 return(rc); 3526} 3527 3528 3529/****************************************************************************/ 3530/* Release all resources used by the driver. */ 3531/* */ 3532/* Releases all resources acquired by the driver including interrupts, */ 3533/* interrupt handler, interfaces, mutexes, and DMA memory. */ 3534/* */ 3535/* Returns: */ 3536/* Nothing. */ 3537/****************************************************************************/ 3538static void 3539bce_release_resources(struct bce_softc *sc) 3540{ 3541 device_t dev; 3542 3543 DBENTER(BCE_VERBOSE_RESET); 3544 3545 dev = sc->bce_dev; 3546 3547 bce_dma_free(sc); 3548 3549 if (sc->bce_intrhand != NULL) { 3550 DBPRINT(sc, BCE_INFO_RESET, "Removing interrupt handler.\n"); 3551 bus_teardown_intr(dev, sc->bce_res_irq, sc->bce_intrhand); 3552 } 3553 3554 if (sc->bce_res_irq != NULL) { 3555 DBPRINT(sc, BCE_INFO_RESET, "Releasing IRQ.\n"); 3556 bus_release_resource(dev, SYS_RES_IRQ, sc->bce_irq_rid, 3557 sc->bce_res_irq); 3558 } 3559 3560 if (sc->bce_flags & (BCE_USING_MSI_FLAG | BCE_USING_MSIX_FLAG)) { 3561 DBPRINT(sc, BCE_INFO_RESET, "Releasing MSI/MSI-X vector.\n"); 3562 pci_release_msi(dev); 3563 } 3564 3565 if (sc->bce_res_mem != NULL) { 3566 DBPRINT(sc, BCE_INFO_RESET, "Releasing PCI memory.\n"); 3567 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0), 3568 sc->bce_res_mem); 3569 } 3570 3571 if (sc->bce_ifp != NULL) { 3572 DBPRINT(sc, BCE_INFO_RESET, "Releasing IF.\n"); 3573 if_free(sc->bce_ifp); 3574 } 3575 3576 if (mtx_initialized(&sc->bce_mtx)) 3577 BCE_LOCK_DESTROY(sc); 3578 3579 DBEXIT(BCE_VERBOSE_RESET); 3580} 3581 3582 3583/****************************************************************************/ 3584/* Firmware synchronization. */ 3585/* */ 3586/* Before performing certain events such as a chip reset, synchronize with */ 3587/* the firmware first. */ 3588/* */ 3589/* Returns: */ 3590/* 0 for success, positive value for failure. */ 3591/****************************************************************************/ 3592static int 3593bce_fw_sync(struct bce_softc *sc, u32 msg_data) 3594{ 3595 int i, rc = 0; 3596 u32 val; 3597 3598 DBENTER(BCE_VERBOSE_RESET); 3599 3600 /* Don't waste any time if we've timed out before. */ 3601 if (sc->bce_fw_timed_out == TRUE) { 3602 rc = EBUSY; 3603 goto bce_fw_sync_exit; 3604 } 3605 3606 /* Increment the message sequence number. */ 3607 sc->bce_fw_wr_seq++; 3608 msg_data |= sc->bce_fw_wr_seq; 3609 3610 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "bce_fw_sync(): msg_data = " 3611 "0x%08X\n", msg_data); 3612 3613 /* Send the message to the bootcode driver mailbox. */ 3614 bce_shmem_wr(sc, BCE_DRV_MB, msg_data); 3615 3616 /* Wait for the bootcode to acknowledge the message. */ 3617 for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) { 3618 /* Check for a response in the bootcode firmware mailbox. */ 3619 val = bce_shmem_rd(sc, BCE_FW_MB); 3620 if ((val & BCE_FW_MSG_ACK) == (msg_data & BCE_DRV_MSG_SEQ)) 3621 break; 3622 DELAY(1000); 3623 } 3624 3625 /* If we've timed out, tell bootcode that we've stopped waiting. */ 3626 if (((val & BCE_FW_MSG_ACK) != (msg_data & BCE_DRV_MSG_SEQ)) && 3627 ((msg_data & BCE_DRV_MSG_DATA) != BCE_DRV_MSG_DATA_WAIT0)) { 3628 3629 BCE_PRINTF("%s(%d): Firmware synchronization timeout! " 3630 "msg_data = 0x%08X\n", __FILE__, __LINE__, msg_data); 3631 3632 msg_data &= ~BCE_DRV_MSG_CODE; 3633 msg_data |= BCE_DRV_MSG_CODE_FW_TIMEOUT; 3634 3635 bce_shmem_wr(sc, BCE_DRV_MB, msg_data); 3636 3637 sc->bce_fw_timed_out = TRUE; 3638 rc = EBUSY; 3639 } 3640 3641bce_fw_sync_exit: 3642 DBEXIT(BCE_VERBOSE_RESET); 3643 return (rc); 3644} 3645 3646 3647/****************************************************************************/ 3648/* Load Receive Virtual 2 Physical (RV2P) processor firmware. */ 3649/* */ 3650/* Returns: */ 3651/* Nothing. */ 3652/****************************************************************************/ 3653static void 3654bce_load_rv2p_fw(struct bce_softc *sc, u32 *rv2p_code, 3655 u32 rv2p_code_len, u32 rv2p_proc) 3656{ 3657 int i; 3658 u32 val; 3659 3660 DBENTER(BCE_VERBOSE_RESET); 3661 3662 /* Set the page size used by RV2P. */ 3663 if (rv2p_proc == RV2P_PROC2) { 3664 BCE_RV2P_PROC2_CHG_MAX_BD_PAGE(USABLE_RX_BD_PER_PAGE); 3665 } 3666 3667 for (i = 0; i < rv2p_code_len; i += 8) { 3668 REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code); 3669 rv2p_code++; 3670 REG_WR(sc, BCE_RV2P_INSTR_LOW, *rv2p_code); 3671 rv2p_code++; 3672 3673 if (rv2p_proc == RV2P_PROC1) { 3674 val = (i / 8) | BCE_RV2P_PROC1_ADDR_CMD_RDWR; 3675 REG_WR(sc, BCE_RV2P_PROC1_ADDR_CMD, val); 3676 } 3677 else { 3678 val = (i / 8) | BCE_RV2P_PROC2_ADDR_CMD_RDWR; 3679 REG_WR(sc, BCE_RV2P_PROC2_ADDR_CMD, val); 3680 } 3681 } 3682 3683 /* Reset the processor, un-stall is done later. */ 3684 if (rv2p_proc == RV2P_PROC1) { 3685 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET); 3686 } 3687 else { 3688 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET); 3689 } 3690 3691 DBEXIT(BCE_VERBOSE_RESET); 3692} 3693 3694 3695/****************************************************************************/ 3696/* Load RISC processor firmware. */ 3697/* */ 3698/* Loads firmware from the file if_bcefw.h into the scratchpad memory */ 3699/* associated with a particular processor. */ 3700/* */ 3701/* Returns: */ 3702/* Nothing. */ 3703/****************************************************************************/ 3704static void 3705bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg, 3706 struct fw_info *fw) 3707{ 3708 u32 offset; 3709 3710 DBENTER(BCE_VERBOSE_RESET); 3711 3712 bce_halt_cpu(sc, cpu_reg); 3713 3714 /* Load the Text area. */ 3715 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base); 3716 if (fw->text) { 3717 int j; 3718 3719 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) { 3720 REG_WR_IND(sc, offset, fw->text[j]); 3721 } 3722 } 3723 3724 /* Load the Data area. */ 3725 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base); 3726 if (fw->data) { 3727 int j; 3728 3729 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) { 3730 REG_WR_IND(sc, offset, fw->data[j]); 3731 } 3732 } 3733 3734 /* Load the SBSS area. */ 3735 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base); 3736 if (fw->sbss) { 3737 int j; 3738 3739 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) { 3740 REG_WR_IND(sc, offset, fw->sbss[j]); 3741 } 3742 } 3743 3744 /* Load the BSS area. */ 3745 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base); 3746 if (fw->bss) { 3747 int j; 3748 3749 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) { 3750 REG_WR_IND(sc, offset, fw->bss[j]); 3751 } 3752 } 3753 3754 /* Load the Read-Only area. */ 3755 offset = cpu_reg->spad_base + 3756 (fw->rodata_addr - cpu_reg->mips_view_base); 3757 if (fw->rodata) { 3758 int j; 3759 3760 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) { 3761 REG_WR_IND(sc, offset, fw->rodata[j]); 3762 } 3763 } 3764 3765 /* Clear the pre-fetch instruction and set the FW start address. */ 3766 REG_WR_IND(sc, cpu_reg->inst, 0); 3767 REG_WR_IND(sc, cpu_reg->pc, fw->start_addr); 3768 3769 DBEXIT(BCE_VERBOSE_RESET); 3770} 3771 3772 3773/****************************************************************************/ 3774/* Starts the RISC processor. */ 3775/* */ 3776/* Assumes the CPU starting address has already been set. */ 3777/* */ 3778/* Returns: */ 3779/* Nothing. */ 3780/****************************************************************************/ 3781static void 3782bce_start_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg) 3783{ 3784 u32 val; 3785 3786 DBENTER(BCE_VERBOSE_RESET); 3787 3788 /* Start the CPU. */ 3789 val = REG_RD_IND(sc, cpu_reg->mode); 3790 val &= ~cpu_reg->mode_value_halt; 3791 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 3792 REG_WR_IND(sc, cpu_reg->mode, val); 3793 3794 DBEXIT(BCE_VERBOSE_RESET); 3795} 3796 3797 3798/****************************************************************************/ 3799/* Halts the RISC processor. */ 3800/* */ 3801/* Returns: */ 3802/* Nothing. */ 3803/****************************************************************************/ 3804static void 3805bce_halt_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg) 3806{ 3807 u32 val; 3808 3809 DBENTER(BCE_VERBOSE_RESET); 3810 3811 /* Halt the CPU. */ 3812 val = REG_RD_IND(sc, cpu_reg->mode); 3813 val |= cpu_reg->mode_value_halt; 3814 REG_WR_IND(sc, cpu_reg->mode, val); 3815 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 3816 3817 DBEXIT(BCE_VERBOSE_RESET); 3818} 3819 3820 3821/****************************************************************************/ 3822/* Initialize the RX CPU. */ 3823/* */ 3824/* Returns: */ 3825/* Nothing. */ 3826/****************************************************************************/ 3827static void 3828bce_start_rxp_cpu(struct bce_softc *sc) 3829{ 3830 struct cpu_reg cpu_reg; 3831 3832 DBENTER(BCE_VERBOSE_RESET); 3833 3834 cpu_reg.mode = BCE_RXP_CPU_MODE; 3835 cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT; 3836 cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA; 3837 cpu_reg.state = BCE_RXP_CPU_STATE; 3838 cpu_reg.state_value_clear = 0xffffff; 3839 cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE; 3840 cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK; 3841 cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER; 3842 cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION; 3843 cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT; 3844 cpu_reg.spad_base = BCE_RXP_SCRATCH; 3845 cpu_reg.mips_view_base = 0x8000000; 3846 3847 DBPRINT(sc, BCE_INFO_RESET, "Starting RX firmware.\n"); 3848 bce_start_cpu(sc, &cpu_reg); 3849 3850 DBEXIT(BCE_VERBOSE_RESET); 3851} 3852 3853 3854/****************************************************************************/ 3855/* Initialize the RX CPU. */ 3856/* */ 3857/* Returns: */ 3858/* Nothing. */ 3859/****************************************************************************/ 3860static void 3861bce_init_rxp_cpu(struct bce_softc *sc) 3862{ 3863 struct cpu_reg cpu_reg; 3864 struct fw_info fw; 3865 3866 DBENTER(BCE_VERBOSE_RESET); 3867 3868 cpu_reg.mode = BCE_RXP_CPU_MODE; 3869 cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT; 3870 cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA; 3871 cpu_reg.state = BCE_RXP_CPU_STATE; 3872 cpu_reg.state_value_clear = 0xffffff; 3873 cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE; 3874 cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK; 3875 cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER; 3876 cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION; 3877 cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT; 3878 cpu_reg.spad_base = BCE_RXP_SCRATCH; 3879 cpu_reg.mips_view_base = 0x8000000; 3880 3881 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 3882 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 3883 fw.ver_major = bce_RXP_b09FwReleaseMajor; 3884 fw.ver_minor = bce_RXP_b09FwReleaseMinor; 3885 fw.ver_fix = bce_RXP_b09FwReleaseFix; 3886 fw.start_addr = bce_RXP_b09FwStartAddr; 3887 3888 fw.text_addr = bce_RXP_b09FwTextAddr; 3889 fw.text_len = bce_RXP_b09FwTextLen; 3890 fw.text_index = 0; 3891 fw.text = bce_RXP_b09FwText; 3892 3893 fw.data_addr = bce_RXP_b09FwDataAddr; 3894 fw.data_len = bce_RXP_b09FwDataLen; 3895 fw.data_index = 0; 3896 fw.data = bce_RXP_b09FwData; 3897 3898 fw.sbss_addr = bce_RXP_b09FwSbssAddr; 3899 fw.sbss_len = bce_RXP_b09FwSbssLen; 3900 fw.sbss_index = 0; 3901 fw.sbss = bce_RXP_b09FwSbss; 3902 3903 fw.bss_addr = bce_RXP_b09FwBssAddr; 3904 fw.bss_len = bce_RXP_b09FwBssLen; 3905 fw.bss_index = 0; 3906 fw.bss = bce_RXP_b09FwBss; 3907 3908 fw.rodata_addr = bce_RXP_b09FwRodataAddr; 3909 fw.rodata_len = bce_RXP_b09FwRodataLen; 3910 fw.rodata_index = 0; 3911 fw.rodata = bce_RXP_b09FwRodata; 3912 } else { 3913 fw.ver_major = bce_RXP_b06FwReleaseMajor; 3914 fw.ver_minor = bce_RXP_b06FwReleaseMinor; 3915 fw.ver_fix = bce_RXP_b06FwReleaseFix; 3916 fw.start_addr = bce_RXP_b06FwStartAddr; 3917 3918 fw.text_addr = bce_RXP_b06FwTextAddr; 3919 fw.text_len = bce_RXP_b06FwTextLen; 3920 fw.text_index = 0; 3921 fw.text = bce_RXP_b06FwText; 3922 3923 fw.data_addr = bce_RXP_b06FwDataAddr; 3924 fw.data_len = bce_RXP_b06FwDataLen; 3925 fw.data_index = 0; 3926 fw.data = bce_RXP_b06FwData; 3927 3928 fw.sbss_addr = bce_RXP_b06FwSbssAddr; 3929 fw.sbss_len = bce_RXP_b06FwSbssLen; 3930 fw.sbss_index = 0; 3931 fw.sbss = bce_RXP_b06FwSbss; 3932 3933 fw.bss_addr = bce_RXP_b06FwBssAddr; 3934 fw.bss_len = bce_RXP_b06FwBssLen; 3935 fw.bss_index = 0; 3936 fw.bss = bce_RXP_b06FwBss; 3937 3938 fw.rodata_addr = bce_RXP_b06FwRodataAddr; 3939 fw.rodata_len = bce_RXP_b06FwRodataLen; 3940 fw.rodata_index = 0; 3941 fw.rodata = bce_RXP_b06FwRodata; 3942 } 3943 3944 DBPRINT(sc, BCE_INFO_RESET, "Loading RX firmware.\n"); 3945 bce_load_cpu_fw(sc, &cpu_reg, &fw); 3946 3947 /* Delay RXP start until initialization is complete. */ 3948 3949 DBEXIT(BCE_VERBOSE_RESET); 3950} 3951 3952 3953/****************************************************************************/ 3954/* Initialize the TX CPU. */ 3955/* */ 3956/* Returns: */ 3957/* Nothing. */ 3958/****************************************************************************/ 3959static void 3960bce_init_txp_cpu(struct bce_softc *sc) 3961{ 3962 struct cpu_reg cpu_reg; 3963 struct fw_info fw; 3964 3965 DBENTER(BCE_VERBOSE_RESET); 3966 3967 cpu_reg.mode = BCE_TXP_CPU_MODE; 3968 cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT; 3969 cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA; 3970 cpu_reg.state = BCE_TXP_CPU_STATE; 3971 cpu_reg.state_value_clear = 0xffffff; 3972 cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE; 3973 cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK; 3974 cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER; 3975 cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION; 3976 cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT; 3977 cpu_reg.spad_base = BCE_TXP_SCRATCH; 3978 cpu_reg.mips_view_base = 0x8000000; 3979 3980 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 3981 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 3982 fw.ver_major = bce_TXP_b09FwReleaseMajor; 3983 fw.ver_minor = bce_TXP_b09FwReleaseMinor; 3984 fw.ver_fix = bce_TXP_b09FwReleaseFix; 3985 fw.start_addr = bce_TXP_b09FwStartAddr; 3986 3987 fw.text_addr = bce_TXP_b09FwTextAddr; 3988 fw.text_len = bce_TXP_b09FwTextLen; 3989 fw.text_index = 0; 3990 fw.text = bce_TXP_b09FwText; 3991 3992 fw.data_addr = bce_TXP_b09FwDataAddr; 3993 fw.data_len = bce_TXP_b09FwDataLen; 3994 fw.data_index = 0; 3995 fw.data = bce_TXP_b09FwData; 3996 3997 fw.sbss_addr = bce_TXP_b09FwSbssAddr; 3998 fw.sbss_len = bce_TXP_b09FwSbssLen; 3999 fw.sbss_index = 0; 4000 fw.sbss = bce_TXP_b09FwSbss; 4001 4002 fw.bss_addr = bce_TXP_b09FwBssAddr; 4003 fw.bss_len = bce_TXP_b09FwBssLen; 4004 fw.bss_index = 0; 4005 fw.bss = bce_TXP_b09FwBss; 4006 4007 fw.rodata_addr = bce_TXP_b09FwRodataAddr; 4008 fw.rodata_len = bce_TXP_b09FwRodataLen; 4009 fw.rodata_index = 0; 4010 fw.rodata = bce_TXP_b09FwRodata; 4011 } else { 4012 fw.ver_major = bce_TXP_b06FwReleaseMajor; 4013 fw.ver_minor = bce_TXP_b06FwReleaseMinor; 4014 fw.ver_fix = bce_TXP_b06FwReleaseFix; 4015 fw.start_addr = bce_TXP_b06FwStartAddr; 4016 4017 fw.text_addr = bce_TXP_b06FwTextAddr; 4018 fw.text_len = bce_TXP_b06FwTextLen; 4019 fw.text_index = 0; 4020 fw.text = bce_TXP_b06FwText; 4021 4022 fw.data_addr = bce_TXP_b06FwDataAddr; 4023 fw.data_len = bce_TXP_b06FwDataLen; 4024 fw.data_index = 0; 4025 fw.data = bce_TXP_b06FwData; 4026 4027 fw.sbss_addr = bce_TXP_b06FwSbssAddr; 4028 fw.sbss_len = bce_TXP_b06FwSbssLen; 4029 fw.sbss_index = 0; 4030 fw.sbss = bce_TXP_b06FwSbss; 4031 4032 fw.bss_addr = bce_TXP_b06FwBssAddr; 4033 fw.bss_len = bce_TXP_b06FwBssLen; 4034 fw.bss_index = 0; 4035 fw.bss = bce_TXP_b06FwBss; 4036 4037 fw.rodata_addr = bce_TXP_b06FwRodataAddr; 4038 fw.rodata_len = bce_TXP_b06FwRodataLen; 4039 fw.rodata_index = 0; 4040 fw.rodata = bce_TXP_b06FwRodata; 4041 } 4042 4043 DBPRINT(sc, BCE_INFO_RESET, "Loading TX firmware.\n"); 4044 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4045 bce_start_cpu(sc, &cpu_reg); 4046 4047 DBEXIT(BCE_VERBOSE_RESET); 4048} 4049 4050 4051/****************************************************************************/ 4052/* Initialize the TPAT CPU. */ 4053/* */ 4054/* Returns: */ 4055/* Nothing. */ 4056/****************************************************************************/ 4057static void 4058bce_init_tpat_cpu(struct bce_softc *sc) 4059{ 4060 struct cpu_reg cpu_reg; 4061 struct fw_info fw; 4062 4063 DBENTER(BCE_VERBOSE_RESET); 4064 4065 cpu_reg.mode = BCE_TPAT_CPU_MODE; 4066 cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT; 4067 cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA; 4068 cpu_reg.state = BCE_TPAT_CPU_STATE; 4069 cpu_reg.state_value_clear = 0xffffff; 4070 cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE; 4071 cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK; 4072 cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER; 4073 cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION; 4074 cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT; 4075 cpu_reg.spad_base = BCE_TPAT_SCRATCH; 4076 cpu_reg.mips_view_base = 0x8000000; 4077 4078 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 4079 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 4080 fw.ver_major = bce_TPAT_b09FwReleaseMajor; 4081 fw.ver_minor = bce_TPAT_b09FwReleaseMinor; 4082 fw.ver_fix = bce_TPAT_b09FwReleaseFix; 4083 fw.start_addr = bce_TPAT_b09FwStartAddr; 4084 4085 fw.text_addr = bce_TPAT_b09FwTextAddr; 4086 fw.text_len = bce_TPAT_b09FwTextLen; 4087 fw.text_index = 0; 4088 fw.text = bce_TPAT_b09FwText; 4089 4090 fw.data_addr = bce_TPAT_b09FwDataAddr; 4091 fw.data_len = bce_TPAT_b09FwDataLen; 4092 fw.data_index = 0; 4093 fw.data = bce_TPAT_b09FwData; 4094 4095 fw.sbss_addr = bce_TPAT_b09FwSbssAddr; 4096 fw.sbss_len = bce_TPAT_b09FwSbssLen; 4097 fw.sbss_index = 0; 4098 fw.sbss = bce_TPAT_b09FwSbss; 4099 4100 fw.bss_addr = bce_TPAT_b09FwBssAddr; 4101 fw.bss_len = bce_TPAT_b09FwBssLen; 4102 fw.bss_index = 0; 4103 fw.bss = bce_TPAT_b09FwBss; 4104 4105 fw.rodata_addr = bce_TPAT_b09FwRodataAddr; 4106 fw.rodata_len = bce_TPAT_b09FwRodataLen; 4107 fw.rodata_index = 0; 4108 fw.rodata = bce_TPAT_b09FwRodata; 4109 } else { 4110 fw.ver_major = bce_TPAT_b06FwReleaseMajor; 4111 fw.ver_minor = bce_TPAT_b06FwReleaseMinor; 4112 fw.ver_fix = bce_TPAT_b06FwReleaseFix; 4113 fw.start_addr = bce_TPAT_b06FwStartAddr; 4114 4115 fw.text_addr = bce_TPAT_b06FwTextAddr; 4116 fw.text_len = bce_TPAT_b06FwTextLen; 4117 fw.text_index = 0; 4118 fw.text = bce_TPAT_b06FwText; 4119 4120 fw.data_addr = bce_TPAT_b06FwDataAddr; 4121 fw.data_len = bce_TPAT_b06FwDataLen; 4122 fw.data_index = 0; 4123 fw.data = bce_TPAT_b06FwData; 4124 4125 fw.sbss_addr = bce_TPAT_b06FwSbssAddr; 4126 fw.sbss_len = bce_TPAT_b06FwSbssLen; 4127 fw.sbss_index = 0; 4128 fw.sbss = bce_TPAT_b06FwSbss; 4129 4130 fw.bss_addr = bce_TPAT_b06FwBssAddr; 4131 fw.bss_len = bce_TPAT_b06FwBssLen; 4132 fw.bss_index = 0; 4133 fw.bss = bce_TPAT_b06FwBss; 4134 4135 fw.rodata_addr = bce_TPAT_b06FwRodataAddr; 4136 fw.rodata_len = bce_TPAT_b06FwRodataLen; 4137 fw.rodata_index = 0; 4138 fw.rodata = bce_TPAT_b06FwRodata; 4139 } 4140 4141 DBPRINT(sc, BCE_INFO_RESET, "Loading TPAT firmware.\n"); 4142 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4143 bce_start_cpu(sc, &cpu_reg); 4144 4145 DBEXIT(BCE_VERBOSE_RESET); 4146} 4147 4148 4149/****************************************************************************/ 4150/* Initialize the CP CPU. */ 4151/* */ 4152/* Returns: */ 4153/* Nothing. */ 4154/****************************************************************************/ 4155static void 4156bce_init_cp_cpu(struct bce_softc *sc) 4157{ 4158 struct cpu_reg cpu_reg; 4159 struct fw_info fw; 4160 4161 DBENTER(BCE_VERBOSE_RESET); 4162 4163 cpu_reg.mode = BCE_CP_CPU_MODE; 4164 cpu_reg.mode_value_halt = BCE_CP_CPU_MODE_SOFT_HALT; 4165 cpu_reg.mode_value_sstep = BCE_CP_CPU_MODE_STEP_ENA; 4166 cpu_reg.state = BCE_CP_CPU_STATE; 4167 cpu_reg.state_value_clear = 0xffffff; 4168 cpu_reg.gpr0 = BCE_CP_CPU_REG_FILE; 4169 cpu_reg.evmask = BCE_CP_CPU_EVENT_MASK; 4170 cpu_reg.pc = BCE_CP_CPU_PROGRAM_COUNTER; 4171 cpu_reg.inst = BCE_CP_CPU_INSTRUCTION; 4172 cpu_reg.bp = BCE_CP_CPU_HW_BREAKPOINT; 4173 cpu_reg.spad_base = BCE_CP_SCRATCH; 4174 cpu_reg.mips_view_base = 0x8000000; 4175 4176 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 4177 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 4178 fw.ver_major = bce_CP_b09FwReleaseMajor; 4179 fw.ver_minor = bce_CP_b09FwReleaseMinor; 4180 fw.ver_fix = bce_CP_b09FwReleaseFix; 4181 fw.start_addr = bce_CP_b09FwStartAddr; 4182 4183 fw.text_addr = bce_CP_b09FwTextAddr; 4184 fw.text_len = bce_CP_b09FwTextLen; 4185 fw.text_index = 0; 4186 fw.text = bce_CP_b09FwText; 4187 4188 fw.data_addr = bce_CP_b09FwDataAddr; 4189 fw.data_len = bce_CP_b09FwDataLen; 4190 fw.data_index = 0; 4191 fw.data = bce_CP_b09FwData; 4192 4193 fw.sbss_addr = bce_CP_b09FwSbssAddr; 4194 fw.sbss_len = bce_CP_b09FwSbssLen; 4195 fw.sbss_index = 0; 4196 fw.sbss = bce_CP_b09FwSbss; 4197 4198 fw.bss_addr = bce_CP_b09FwBssAddr; 4199 fw.bss_len = bce_CP_b09FwBssLen; 4200 fw.bss_index = 0; 4201 fw.bss = bce_CP_b09FwBss; 4202 4203 fw.rodata_addr = bce_CP_b09FwRodataAddr; 4204 fw.rodata_len = bce_CP_b09FwRodataLen; 4205 fw.rodata_index = 0; 4206 fw.rodata = bce_CP_b09FwRodata; 4207 } else { 4208 fw.ver_major = bce_CP_b06FwReleaseMajor; 4209 fw.ver_minor = bce_CP_b06FwReleaseMinor; 4210 fw.ver_fix = bce_CP_b06FwReleaseFix; 4211 fw.start_addr = bce_CP_b06FwStartAddr; 4212 4213 fw.text_addr = bce_CP_b06FwTextAddr; 4214 fw.text_len = bce_CP_b06FwTextLen; 4215 fw.text_index = 0; 4216 fw.text = bce_CP_b06FwText; 4217 4218 fw.data_addr = bce_CP_b06FwDataAddr; 4219 fw.data_len = bce_CP_b06FwDataLen; 4220 fw.data_index = 0; 4221 fw.data = bce_CP_b06FwData; 4222 4223 fw.sbss_addr = bce_CP_b06FwSbssAddr; 4224 fw.sbss_len = bce_CP_b06FwSbssLen; 4225 fw.sbss_index = 0; 4226 fw.sbss = bce_CP_b06FwSbss; 4227 4228 fw.bss_addr = bce_CP_b06FwBssAddr; 4229 fw.bss_len = bce_CP_b06FwBssLen; 4230 fw.bss_index = 0; 4231 fw.bss = bce_CP_b06FwBss; 4232 4233 fw.rodata_addr = bce_CP_b06FwRodataAddr; 4234 fw.rodata_len = bce_CP_b06FwRodataLen; 4235 fw.rodata_index = 0; 4236 fw.rodata = bce_CP_b06FwRodata; 4237 } 4238 4239 DBPRINT(sc, BCE_INFO_RESET, "Loading CP firmware.\n"); 4240 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4241 bce_start_cpu(sc, &cpu_reg); 4242 4243 DBEXIT(BCE_VERBOSE_RESET); 4244} 4245 4246 4247/****************************************************************************/ 4248/* Initialize the COM CPU. */ 4249/* */ 4250/* Returns: */ 4251/* Nothing. */ 4252/****************************************************************************/ 4253static void 4254bce_init_com_cpu(struct bce_softc *sc) 4255{ 4256 struct cpu_reg cpu_reg; 4257 struct fw_info fw; 4258 4259 DBENTER(BCE_VERBOSE_RESET); 4260 4261 cpu_reg.mode = BCE_COM_CPU_MODE; 4262 cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT; 4263 cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA; 4264 cpu_reg.state = BCE_COM_CPU_STATE; 4265 cpu_reg.state_value_clear = 0xffffff; 4266 cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE; 4267 cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK; 4268 cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER; 4269 cpu_reg.inst = BCE_COM_CPU_INSTRUCTION; 4270 cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT; 4271 cpu_reg.spad_base = BCE_COM_SCRATCH; 4272 cpu_reg.mips_view_base = 0x8000000; 4273 4274 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 4275 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 4276 fw.ver_major = bce_COM_b09FwReleaseMajor; 4277 fw.ver_minor = bce_COM_b09FwReleaseMinor; 4278 fw.ver_fix = bce_COM_b09FwReleaseFix; 4279 fw.start_addr = bce_COM_b09FwStartAddr; 4280 4281 fw.text_addr = bce_COM_b09FwTextAddr; 4282 fw.text_len = bce_COM_b09FwTextLen; 4283 fw.text_index = 0; 4284 fw.text = bce_COM_b09FwText; 4285 4286 fw.data_addr = bce_COM_b09FwDataAddr; 4287 fw.data_len = bce_COM_b09FwDataLen; 4288 fw.data_index = 0; 4289 fw.data = bce_COM_b09FwData; 4290 4291 fw.sbss_addr = bce_COM_b09FwSbssAddr; 4292 fw.sbss_len = bce_COM_b09FwSbssLen; 4293 fw.sbss_index = 0; 4294 fw.sbss = bce_COM_b09FwSbss; 4295 4296 fw.bss_addr = bce_COM_b09FwBssAddr; 4297 fw.bss_len = bce_COM_b09FwBssLen; 4298 fw.bss_index = 0; 4299 fw.bss = bce_COM_b09FwBss; 4300 4301 fw.rodata_addr = bce_COM_b09FwRodataAddr; 4302 fw.rodata_len = bce_COM_b09FwRodataLen; 4303 fw.rodata_index = 0; 4304 fw.rodata = bce_COM_b09FwRodata; 4305 } else { 4306 fw.ver_major = bce_COM_b06FwReleaseMajor; 4307 fw.ver_minor = bce_COM_b06FwReleaseMinor; 4308 fw.ver_fix = bce_COM_b06FwReleaseFix; 4309 fw.start_addr = bce_COM_b06FwStartAddr; 4310 4311 fw.text_addr = bce_COM_b06FwTextAddr; 4312 fw.text_len = bce_COM_b06FwTextLen; 4313 fw.text_index = 0; 4314 fw.text = bce_COM_b06FwText; 4315 4316 fw.data_addr = bce_COM_b06FwDataAddr; 4317 fw.data_len = bce_COM_b06FwDataLen; 4318 fw.data_index = 0; 4319 fw.data = bce_COM_b06FwData; 4320 4321 fw.sbss_addr = bce_COM_b06FwSbssAddr; 4322 fw.sbss_len = bce_COM_b06FwSbssLen; 4323 fw.sbss_index = 0; 4324 fw.sbss = bce_COM_b06FwSbss; 4325 4326 fw.bss_addr = bce_COM_b06FwBssAddr; 4327 fw.bss_len = bce_COM_b06FwBssLen; 4328 fw.bss_index = 0; 4329 fw.bss = bce_COM_b06FwBss; 4330 4331 fw.rodata_addr = bce_COM_b06FwRodataAddr; 4332 fw.rodata_len = bce_COM_b06FwRodataLen; 4333 fw.rodata_index = 0; 4334 fw.rodata = bce_COM_b06FwRodata; 4335 } 4336 4337 DBPRINT(sc, BCE_INFO_RESET, "Loading COM firmware.\n"); 4338 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4339 bce_start_cpu(sc, &cpu_reg); 4340 4341 DBEXIT(BCE_VERBOSE_RESET); 4342} 4343 4344 4345/****************************************************************************/ 4346/* Initialize the RV2P, RX, TX, TPAT, COM, and CP CPUs. */ 4347/* */ 4348/* Loads the firmware for each CPU and starts the CPU. */ 4349/* */ 4350/* Returns: */ 4351/* Nothing. */ 4352/****************************************************************************/ 4353static void 4354bce_init_cpus(struct bce_softc *sc) 4355{ 4356 DBENTER(BCE_VERBOSE_RESET); 4357 4358 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 4359 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 4360 4361 if ((BCE_CHIP_REV(sc) == BCE_CHIP_REV_Ax)) { 4362 bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc1, 4363 sizeof(bce_xi90_rv2p_proc1), RV2P_PROC1); 4364 bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc2, 4365 sizeof(bce_xi90_rv2p_proc2), RV2P_PROC2); 4366 } else { 4367 bce_load_rv2p_fw(sc, bce_xi_rv2p_proc1, 4368 sizeof(bce_xi_rv2p_proc1), RV2P_PROC1); 4369 bce_load_rv2p_fw(sc, bce_xi_rv2p_proc2, 4370 sizeof(bce_xi_rv2p_proc2), RV2P_PROC2); 4371 } 4372 4373 } else { 4374 bce_load_rv2p_fw(sc, bce_rv2p_proc1, 4375 sizeof(bce_rv2p_proc1), RV2P_PROC1); 4376 bce_load_rv2p_fw(sc, bce_rv2p_proc2, 4377 sizeof(bce_rv2p_proc2), RV2P_PROC2); 4378 } 4379 4380 bce_init_rxp_cpu(sc); 4381 bce_init_txp_cpu(sc); 4382 bce_init_tpat_cpu(sc); 4383 bce_init_com_cpu(sc); 4384 bce_init_cp_cpu(sc); 4385 4386 DBEXIT(BCE_VERBOSE_RESET); 4387} 4388 4389 4390/****************************************************************************/ 4391/* Initialize context memory. */ 4392/* */ 4393/* Clears the memory associated with each Context ID (CID). */ 4394/* */ 4395/* Returns: */ 4396/* Nothing. */ 4397/****************************************************************************/ 4398static void 4399bce_init_ctx(struct bce_softc *sc) 4400{ 4401 4402 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 4403 4404 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 4405 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 4406 int i, retry_cnt = CTX_INIT_RETRY_COUNT; 4407 u32 val; 4408 4409 DBPRINT(sc, BCE_INFO_CTX, "Initializing 5709 context.\n"); 4410 4411 /* 4412 * BCM5709 context memory may be cached 4413 * in host memory so prepare the host memory 4414 * for access. 4415 */ 4416 val = BCE_CTX_COMMAND_ENABLED | 4417 BCE_CTX_COMMAND_MEM_INIT | (1 << 12); 4418 val |= (BCM_PAGE_BITS - 8) << 16; 4419 REG_WR(sc, BCE_CTX_COMMAND, val); 4420 4421 /* Wait for mem init command to complete. */ 4422 for (i = 0; i < retry_cnt; i++) { 4423 val = REG_RD(sc, BCE_CTX_COMMAND); 4424 if (!(val & BCE_CTX_COMMAND_MEM_INIT)) 4425 break; 4426 DELAY(2); 4427 } 4428 4429 /* ToDo: Consider returning an error here. */ 4430 DBRUNIF((val & BCE_CTX_COMMAND_MEM_INIT), 4431 BCE_PRINTF("%s(): Context memory initialization " 4432 "failed!\n", __FUNCTION__)); 4433 4434 for (i = 0; i < sc->ctx_pages; i++) { 4435 int j; 4436 4437 /* Set the physical address of the context memory. */ 4438 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA0, 4439 BCE_ADDR_LO(sc->ctx_paddr[i] & 0xfffffff0) | 4440 BCE_CTX_HOST_PAGE_TBL_DATA0_VALID); 4441 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA1, 4442 BCE_ADDR_HI(sc->ctx_paddr[i])); 4443 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_CTRL, i | 4444 BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ); 4445 4446 /* Verify the context memory write was successful. */ 4447 for (j = 0; j < retry_cnt; j++) { 4448 val = REG_RD(sc, BCE_CTX_HOST_PAGE_TBL_CTRL); 4449 if ((val & 4450 BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0) 4451 break; 4452 DELAY(5); 4453 } 4454 4455 /* ToDo: Consider returning an error here. */ 4456 DBRUNIF((val & BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ), 4457 BCE_PRINTF("%s(): Failed to initialize " 4458 "context page %d!\n", __FUNCTION__, i)); 4459 } 4460 } else { 4461 u32 vcid_addr, offset; 4462 4463 DBPRINT(sc, BCE_INFO, "Initializing 5706/5708 context.\n"); 4464 4465 /* 4466 * For the 5706/5708, context memory is local to 4467 * the controller, so initialize the controller 4468 * context memory. 4469 */ 4470 4471 vcid_addr = GET_CID_ADDR(96); 4472 while (vcid_addr) { 4473 4474 vcid_addr -= PHY_CTX_SIZE; 4475 4476 REG_WR(sc, BCE_CTX_VIRT_ADDR, 0); 4477 REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr); 4478 4479 for(offset = 0; offset < PHY_CTX_SIZE; offset += 4) { 4480 CTX_WR(sc, 0x00, offset, 0); 4481 } 4482 4483 REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr); 4484 REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr); 4485 } 4486 4487 } 4488 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 4489} 4490 4491 4492/****************************************************************************/ 4493/* Fetch the permanent MAC address of the controller. */ 4494/* */ 4495/* Returns: */ 4496/* Nothing. */ 4497/****************************************************************************/ 4498static void 4499bce_get_mac_addr(struct bce_softc *sc) 4500{ 4501 u32 mac_lo = 0, mac_hi = 0; 4502 4503 DBENTER(BCE_VERBOSE_RESET); 4504 4505 /* 4506 * The NetXtreme II bootcode populates various NIC 4507 * power-on and runtime configuration items in a 4508 * shared memory area. The factory configured MAC 4509 * address is available from both NVRAM and the 4510 * shared memory area so we'll read the value from 4511 * shared memory for speed. 4512 */ 4513 4514 mac_hi = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_UPPER); 4515 mac_lo = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_LOWER); 4516 4517 if ((mac_lo == 0) && (mac_hi == 0)) { 4518 BCE_PRINTF("%s(%d): Invalid Ethernet address!\n", 4519 __FILE__, __LINE__); 4520 } else { 4521 sc->eaddr[0] = (u_char)(mac_hi >> 8); 4522 sc->eaddr[1] = (u_char)(mac_hi >> 0); 4523 sc->eaddr[2] = (u_char)(mac_lo >> 24); 4524 sc->eaddr[3] = (u_char)(mac_lo >> 16); 4525 sc->eaddr[4] = (u_char)(mac_lo >> 8); 4526 sc->eaddr[5] = (u_char)(mac_lo >> 0); 4527 } 4528 4529 DBPRINT(sc, BCE_INFO_MISC, "Permanent Ethernet " 4530 "address = %6D\n", sc->eaddr, ":"); 4531 DBEXIT(BCE_VERBOSE_RESET); 4532} 4533 4534 4535/****************************************************************************/ 4536/* Program the MAC address. */ 4537/* */ 4538/* Returns: */ 4539/* Nothing. */ 4540/****************************************************************************/ 4541static void 4542bce_set_mac_addr(struct bce_softc *sc) 4543{ 4544 u32 val; 4545 u8 *mac_addr = sc->eaddr; 4546 4547 /* ToDo: Add support for setting multiple MAC addresses. */ 4548 4549 DBENTER(BCE_VERBOSE_RESET); 4550 DBPRINT(sc, BCE_INFO_MISC, "Setting Ethernet address = " 4551 "%6D\n", sc->eaddr, ":"); 4552 4553 val = (mac_addr[0] << 8) | mac_addr[1]; 4554 4555 REG_WR(sc, BCE_EMAC_MAC_MATCH0, val); 4556 4557 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 4558 (mac_addr[4] << 8) | mac_addr[5]; 4559 4560 REG_WR(sc, BCE_EMAC_MAC_MATCH1, val); 4561 4562 DBEXIT(BCE_VERBOSE_RESET); 4563} 4564 4565 4566/****************************************************************************/ 4567/* Stop the controller. */ 4568/* */ 4569/* Returns: */ 4570/* Nothing. */ 4571/****************************************************************************/ 4572static void 4573bce_stop(struct bce_softc *sc) 4574{ 4575 struct ifnet *ifp; 4576 struct ifmedia_entry *ifm; 4577 struct mii_data *mii = NULL; 4578 int mtmp, itmp; 4579 4580 DBENTER(BCE_VERBOSE_RESET); 4581 4582 BCE_LOCK_ASSERT(sc); 4583 4584 ifp = sc->bce_ifp; 4585 4586 mii = device_get_softc(sc->bce_miibus); 4587 4588 callout_stop(&sc->bce_tick_callout); 4589 4590 /* Disable the transmit/receive blocks. */ 4591 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, BCE_MISC_ENABLE_CLR_DEFAULT); 4592 REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS); 4593 DELAY(20); 4594 4595 bce_disable_intr(sc); 4596 4597 /* Free RX buffers. */ 4598#ifdef BCE_JUMBO_HDRSPLIT 4599 bce_free_pg_chain(sc); 4600#endif 4601 bce_free_rx_chain(sc); 4602 4603 /* Free TX buffers. */ 4604 bce_free_tx_chain(sc); 4605 4606 /* 4607 * Isolate/power down the PHY, but leave the media selection 4608 * unchanged so that things will be put back to normal when 4609 * we bring the interface back up. 4610 */ 4611 4612 itmp = ifp->if_flags; 4613 ifp->if_flags |= IFF_UP; 4614 4615 /* If we are called from bce_detach(), mii is already NULL. */ 4616 if (mii != NULL) { 4617 ifm = mii->mii_media.ifm_cur; 4618 mtmp = ifm->ifm_media; 4619 ifm->ifm_media = IFM_ETHER | IFM_NONE; 4620 mii_mediachg(mii); 4621 ifm->ifm_media = mtmp; 4622 } 4623 4624 ifp->if_flags = itmp; 4625 sc->watchdog_timer = 0; 4626 4627 sc->bce_link_up = FALSE; 4628 4629 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 4630 4631 DBEXIT(BCE_VERBOSE_RESET); 4632} 4633 4634 4635static int 4636bce_reset(struct bce_softc *sc, u32 reset_code) 4637{ 4638 u32 val; 4639 int i, rc = 0; 4640 4641 DBENTER(BCE_VERBOSE_RESET); 4642 4643 DBPRINT(sc, BCE_VERBOSE_RESET, "%s(): reset_code = 0x%08X\n", 4644 __FUNCTION__, reset_code); 4645 4646 /* Wait for pending PCI transactions to complete. */ 4647 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, 4648 BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE | 4649 BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE | 4650 BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE | 4651 BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE); 4652 val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS); 4653 DELAY(5); 4654 4655 /* Disable DMA */ 4656 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 4657 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 4658 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL); 4659 val &= ~BCE_MISC_NEW_CORE_CTL_DMA_ENABLE; 4660 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val); 4661 } 4662 4663 /* Assume bootcode is running. */ 4664 sc->bce_fw_timed_out = FALSE; 4665 sc->bce_drv_cardiac_arrest = FALSE; 4666 4667 /* Give the firmware a chance to prepare for the reset. */ 4668 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT0 | reset_code); 4669 if (rc) 4670 goto bce_reset_exit; 4671 4672 /* Set a firmware reminder that this is a soft reset. */ 4673 bce_shmem_wr(sc, BCE_DRV_RESET_SIGNATURE, BCE_DRV_RESET_SIGNATURE_MAGIC); 4674 4675 /* Dummy read to force the chip to complete all current transactions. */ 4676 val = REG_RD(sc, BCE_MISC_ID); 4677 4678 /* Chip reset. */ 4679 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 4680 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 4681 REG_WR(sc, BCE_MISC_COMMAND, BCE_MISC_COMMAND_SW_RESET); 4682 REG_RD(sc, BCE_MISC_COMMAND); 4683 DELAY(5); 4684 4685 val = BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 4686 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 4687 4688 pci_write_config(sc->bce_dev, BCE_PCICFG_MISC_CONFIG, val, 4); 4689 } else { 4690 val = BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 4691 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 4692 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 4693 REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val); 4694 4695 /* Allow up to 30us for reset to complete. */ 4696 for (i = 0; i < 10; i++) { 4697 val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG); 4698 if ((val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 4699 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) { 4700 break; 4701 } 4702 DELAY(10); 4703 } 4704 4705 /* Check that reset completed successfully. */ 4706 if (val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 4707 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) { 4708 BCE_PRINTF("%s(%d): Reset failed!\n", 4709 __FILE__, __LINE__); 4710 rc = EBUSY; 4711 goto bce_reset_exit; 4712 } 4713 } 4714 4715 /* Make sure byte swapping is properly configured. */ 4716 val = REG_RD(sc, BCE_PCI_SWAP_DIAG0); 4717 if (val != 0x01020304) { 4718 BCE_PRINTF("%s(%d): Byte swap is incorrect!\n", 4719 __FILE__, __LINE__); 4720 rc = ENODEV; 4721 goto bce_reset_exit; 4722 } 4723 4724 /* Just completed a reset, assume that firmware is running again. */ 4725 sc->bce_fw_timed_out = FALSE; 4726 sc->bce_drv_cardiac_arrest = FALSE; 4727 4728 /* Wait for the firmware to finish its initialization. */ 4729 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT1 | reset_code); 4730 if (rc) 4731 BCE_PRINTF("%s(%d): Firmware did not complete " 4732 "initialization!\n", __FILE__, __LINE__); 4733 4734bce_reset_exit: 4735 DBEXIT(BCE_VERBOSE_RESET); 4736 return (rc); 4737} 4738 4739 4740static int 4741bce_chipinit(struct bce_softc *sc) 4742{ 4743 u32 val; 4744 int rc = 0; 4745 4746 DBENTER(BCE_VERBOSE_RESET); 4747 4748 bce_disable_intr(sc); 4749 4750 /* 4751 * Initialize DMA byte/word swapping, configure the number of DMA 4752 * channels and PCI clock compensation delay. 4753 */ 4754 val = BCE_DMA_CONFIG_DATA_BYTE_SWAP | 4755 BCE_DMA_CONFIG_DATA_WORD_SWAP | 4756#if BYTE_ORDER == BIG_ENDIAN 4757 BCE_DMA_CONFIG_CNTL_BYTE_SWAP | 4758#endif 4759 BCE_DMA_CONFIG_CNTL_WORD_SWAP | 4760 DMA_READ_CHANS << 12 | 4761 DMA_WRITE_CHANS << 16; 4762 4763 val |= (0x2 << 20) | BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY; 4764 4765 if ((sc->bce_flags & BCE_PCIX_FLAG) && (sc->bus_speed_mhz == 133)) 4766 val |= BCE_DMA_CONFIG_PCI_FAST_CLK_CMP; 4767 4768 /* 4769 * This setting resolves a problem observed on certain Intel PCI 4770 * chipsets that cannot handle multiple outstanding DMA operations. 4771 * See errata E9_5706A1_65. 4772 */ 4773 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) && 4774 (BCE_CHIP_ID(sc) != BCE_CHIP_ID_5706_A0) && 4775 !(sc->bce_flags & BCE_PCIX_FLAG)) 4776 val |= BCE_DMA_CONFIG_CNTL_PING_PONG_DMA; 4777 4778 REG_WR(sc, BCE_DMA_CONFIG, val); 4779 4780 /* Enable the RX_V2P and Context state machines before access. */ 4781 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 4782 BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE | 4783 BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE | 4784 BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE); 4785 4786 /* Initialize context mapping and zero out the quick contexts. */ 4787 bce_init_ctx(sc); 4788 4789 /* Initialize the on-boards CPUs */ 4790 bce_init_cpus(sc); 4791 4792 /* Enable management frames (NC-SI) to flow to the MCP. */ 4793 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 4794 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) | BCE_RPM_MGMT_PKT_CTRL_MGMT_EN; 4795 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val); 4796 } 4797 4798 /* Prepare NVRAM for access. */ 4799 if (bce_init_nvram(sc)) { 4800 rc = ENODEV; 4801 goto bce_chipinit_exit; 4802 } 4803 4804 /* Set the kernel bypass block size */ 4805 val = REG_RD(sc, BCE_MQ_CONFIG); 4806 val &= ~BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE; 4807 val |= BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256; 4808 4809 /* Enable bins used on the 5709. */ 4810 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 4811 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 4812 val |= BCE_MQ_CONFIG_BIN_MQ_MODE; 4813 if (BCE_CHIP_ID(sc) == BCE_CHIP_ID_5709_A1) 4814 val |= BCE_MQ_CONFIG_HALT_DIS; 4815 } 4816 4817 REG_WR(sc, BCE_MQ_CONFIG, val); 4818 4819 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE); 4820 REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val); 4821 REG_WR(sc, BCE_MQ_KNL_WIND_END, val); 4822 4823 /* Set the page size and clear the RV2P processor stall bits. */ 4824 val = (BCM_PAGE_BITS - 8) << 24; 4825 REG_WR(sc, BCE_RV2P_CONFIG, val); 4826 4827 /* Configure page size. */ 4828 val = REG_RD(sc, BCE_TBDR_CONFIG); 4829 val &= ~BCE_TBDR_CONFIG_PAGE_SIZE; 4830 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40; 4831 REG_WR(sc, BCE_TBDR_CONFIG, val); 4832 4833 /* Set the perfect match control register to default. */ 4834 REG_WR_IND(sc, BCE_RXP_PM_CTRL, 0); 4835 4836bce_chipinit_exit: 4837 DBEXIT(BCE_VERBOSE_RESET); 4838 4839 return(rc); 4840} 4841 4842 4843/****************************************************************************/ 4844/* Initialize the controller in preparation to send/receive traffic. */ 4845/* */ 4846/* Returns: */ 4847/* 0 for success, positive value for failure. */ 4848/****************************************************************************/ 4849static int 4850bce_blockinit(struct bce_softc *sc) 4851{ 4852 u32 reg, val; 4853 int rc = 0; 4854 4855 DBENTER(BCE_VERBOSE_RESET); 4856 4857 /* Load the hardware default MAC address. */ 4858 bce_set_mac_addr(sc); 4859 4860 /* Set the Ethernet backoff seed value */ 4861 val = sc->eaddr[0] + (sc->eaddr[1] << 8) + 4862 (sc->eaddr[2] << 16) + (sc->eaddr[3] ) + 4863 (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16); 4864 REG_WR(sc, BCE_EMAC_BACKOFF_SEED, val); 4865 4866 sc->last_status_idx = 0; 4867 sc->rx_mode = BCE_EMAC_RX_MODE_SORT_MODE; 4868 4869 /* Set up link change interrupt generation. */ 4870 REG_WR(sc, BCE_EMAC_ATTENTION_ENA, BCE_EMAC_ATTENTION_ENA_LINK); 4871 4872 /* Program the physical address of the status block. */ 4873 REG_WR(sc, BCE_HC_STATUS_ADDR_L, 4874 BCE_ADDR_LO(sc->status_block_paddr)); 4875 REG_WR(sc, BCE_HC_STATUS_ADDR_H, 4876 BCE_ADDR_HI(sc->status_block_paddr)); 4877 4878 /* Program the physical address of the statistics block. */ 4879 REG_WR(sc, BCE_HC_STATISTICS_ADDR_L, 4880 BCE_ADDR_LO(sc->stats_block_paddr)); 4881 REG_WR(sc, BCE_HC_STATISTICS_ADDR_H, 4882 BCE_ADDR_HI(sc->stats_block_paddr)); 4883 4884 /* Program various host coalescing parameters. */ 4885 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP, 4886 (sc->bce_tx_quick_cons_trip_int << 16) | sc->bce_tx_quick_cons_trip); 4887 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP, 4888 (sc->bce_rx_quick_cons_trip_int << 16) | sc->bce_rx_quick_cons_trip); 4889 REG_WR(sc, BCE_HC_COMP_PROD_TRIP, 4890 (sc->bce_comp_prod_trip_int << 16) | sc->bce_comp_prod_trip); 4891 REG_WR(sc, BCE_HC_TX_TICKS, 4892 (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks); 4893 REG_WR(sc, BCE_HC_RX_TICKS, 4894 (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks); 4895 REG_WR(sc, BCE_HC_COM_TICKS, 4896 (sc->bce_com_ticks_int << 16) | sc->bce_com_ticks); 4897 REG_WR(sc, BCE_HC_CMD_TICKS, 4898 (sc->bce_cmd_ticks_int << 16) | sc->bce_cmd_ticks); 4899 REG_WR(sc, BCE_HC_STATS_TICKS, 4900 (sc->bce_stats_ticks & 0xffff00)); 4901 REG_WR(sc, BCE_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */ 4902 4903 /* Configure the Host Coalescing block. */ 4904 val = BCE_HC_CONFIG_RX_TMR_MODE | BCE_HC_CONFIG_TX_TMR_MODE | 4905 BCE_HC_CONFIG_COLLECT_STATS; 4906 4907#if 0 4908 /* ToDo: Add MSI-X support. */ 4909 if (sc->bce_flags & BCE_USING_MSIX_FLAG) { 4910 u32 base = ((BCE_TX_VEC - 1) * BCE_HC_SB_CONFIG_SIZE) + 4911 BCE_HC_SB_CONFIG_1; 4912 4913 REG_WR(sc, BCE_HC_MSIX_BIT_VECTOR, BCE_HC_MSIX_BIT_VECTOR_VAL); 4914 4915 REG_WR(sc, base, BCE_HC_SB_CONFIG_1_TX_TMR_MODE | 4916 BCE_HC_SB_CONFIG_1_ONE_SHOT); 4917 4918 REG_WR(sc, base + BCE_HC_TX_QUICK_CONS_TRIP_OFF, 4919 (sc->tx_quick_cons_trip_int << 16) | 4920 sc->tx_quick_cons_trip); 4921 4922 REG_WR(sc, base + BCE_HC_TX_TICKS_OFF, 4923 (sc->tx_ticks_int << 16) | sc->tx_ticks); 4924 4925 val |= BCE_HC_CONFIG_SB_ADDR_INC_128B; 4926 } 4927 4928 /* 4929 * Tell the HC block to automatically set the 4930 * INT_MASK bit after an MSI/MSI-X interrupt 4931 * is generated so the driver doesn't have to. 4932 */ 4933 if (sc->bce_flags & BCE_ONE_SHOT_MSI_FLAG) 4934 val |= BCE_HC_CONFIG_ONE_SHOT; 4935 4936 /* Set the MSI-X status blocks to 128 byte boundaries. */ 4937 if (sc->bce_flags & BCE_USING_MSIX_FLAG) 4938 val |= BCE_HC_CONFIG_SB_ADDR_INC_128B; 4939#endif 4940 4941 REG_WR(sc, BCE_HC_CONFIG, val); 4942 4943 /* Clear the internal statistics counters. */ 4944 REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW); 4945 4946 /* Verify that bootcode is running. */ 4947 reg = bce_shmem_rd(sc, BCE_DEV_INFO_SIGNATURE); 4948 4949 DBRUNIF(DB_RANDOMTRUE(bootcode_running_failure_sim_control), 4950 BCE_PRINTF("%s(%d): Simulating bootcode failure.\n", 4951 __FILE__, __LINE__); 4952 reg = 0); 4953 4954 if ((reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK) != 4955 BCE_DEV_INFO_SIGNATURE_MAGIC) { 4956 BCE_PRINTF("%s(%d): Bootcode not running! Found: 0x%08X, " 4957 "Expected: 08%08X\n", __FILE__, __LINE__, 4958 (reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK), 4959 BCE_DEV_INFO_SIGNATURE_MAGIC); 4960 rc = ENODEV; 4961 goto bce_blockinit_exit; 4962 } 4963 4964 /* Enable DMA */ 4965 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 4966 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 4967 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL); 4968 val |= BCE_MISC_NEW_CORE_CTL_DMA_ENABLE; 4969 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val); 4970 } 4971 4972 /* Allow bootcode to apply additional fixes before enabling MAC. */ 4973 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT2 | 4974 BCE_DRV_MSG_CODE_RESET); 4975 4976 /* Enable link state change interrupt generation. */ 4977 REG_WR(sc, BCE_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE); 4978 4979 /* Enable the RXP. */ 4980 bce_start_rxp_cpu(sc); 4981 4982 /* Disable management frames (NC-SI) from flowing to the MCP. */ 4983 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 4984 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) & 4985 ~BCE_RPM_MGMT_PKT_CTRL_MGMT_EN; 4986 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val); 4987 } 4988 4989 /* Enable all remaining blocks in the MAC. */ 4990 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 4991 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) 4992 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 4993 BCE_MISC_ENABLE_DEFAULT_XI); 4994 else 4995 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 4996 BCE_MISC_ENABLE_DEFAULT); 4997 4998 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS); 4999 DELAY(20); 5000 5001 /* Save the current host coalescing block settings. */ 5002 sc->hc_command = REG_RD(sc, BCE_HC_COMMAND); 5003 5004bce_blockinit_exit: 5005 DBEXIT(BCE_VERBOSE_RESET); 5006 5007 return (rc); 5008} 5009 5010 5011/****************************************************************************/ 5012/* Encapsulate an mbuf into the rx_bd chain. */ 5013/* */ 5014/* Returns: */ 5015/* 0 for success, positive value for failure. */ 5016/****************************************************************************/ 5017static int 5018bce_get_rx_buf(struct bce_softc *sc, struct mbuf *m, u16 *prod, 5019 u16 *chain_prod, u32 *prod_bseq) 5020{ 5021 bus_dmamap_t map; 5022 bus_dma_segment_t segs[BCE_MAX_SEGMENTS]; 5023 struct mbuf *m_new = NULL; 5024 struct rx_bd *rxbd; 5025 int nsegs, error, rc = 0; 5026#ifdef BCE_DEBUG 5027 u16 debug_chain_prod = *chain_prod; 5028#endif 5029 5030 DBENTER(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5031 5032 /* Make sure the inputs are valid. */ 5033 DBRUNIF((*chain_prod > MAX_RX_BD), 5034 BCE_PRINTF("%s(%d): RX producer out of range: " 5035 "0x%04X > 0x%04X\n", __FILE__, __LINE__, 5036 *chain_prod, (u16) MAX_RX_BD)); 5037 5038 DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): prod = 0x%04X, " 5039 "chain_prod = 0x%04X, prod_bseq = 0x%08X\n", __FUNCTION__, 5040 *prod, *chain_prod, *prod_bseq); 5041 5042 /* Update some debug statistic counters */ 5043 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 5044 sc->rx_low_watermark = sc->free_rx_bd); 5045 DBRUNIF((sc->free_rx_bd == sc->max_rx_bd), 5046 sc->rx_empty_count++); 5047 5048 /* Check whether this is a new mbuf allocation. */ 5049 if (m == NULL) { 5050 5051 /* Simulate an mbuf allocation failure. */ 5052 DBRUNIF(DB_RANDOMTRUE(mbuf_alloc_failed_sim_control), 5053 sc->mbuf_alloc_failed_count++; 5054 sc->mbuf_alloc_failed_sim_count++; 5055 rc = ENOBUFS; 5056 goto bce_get_rx_buf_exit); 5057 5058 /* This is a new mbuf allocation. */ 5059#ifdef BCE_JUMBO_HDRSPLIT 5060 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 5061#else 5062 m_new = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, 5063 sc->rx_bd_mbuf_alloc_size); 5064#endif 5065 5066 if (m_new == NULL) { 5067 sc->mbuf_alloc_failed_count++; 5068 rc = ENOBUFS; 5069 goto bce_get_rx_buf_exit; 5070 } 5071 5072 DBRUN(sc->debug_rx_mbuf_alloc++); 5073 } else { 5074 /* Reuse an existing mbuf. */ 5075 m_new = m; 5076 } 5077 5078 /* Make sure we have a valid packet header. */ 5079 M_ASSERTPKTHDR(m_new); 5080 5081 /* Initialize the mbuf size and pad if necessary for alignment. */ 5082 m_new->m_pkthdr.len = m_new->m_len = sc->rx_bd_mbuf_alloc_size; 5083 m_adj(m_new, sc->rx_bd_mbuf_align_pad); 5084 5085 /* ToDo: Consider calling m_fragment() to test error handling. */ 5086 5087 /* Map the mbuf cluster into device memory. */ 5088 map = sc->rx_mbuf_map[*chain_prod]; 5089 error = bus_dmamap_load_mbuf_sg(sc->rx_mbuf_tag, map, m_new, 5090 segs, &nsegs, BUS_DMA_NOWAIT); 5091 5092 /* Handle any mapping errors. */ 5093 if (error) { 5094 BCE_PRINTF("%s(%d): Error mapping mbuf into RX " 5095 "chain (%d)!\n", __FILE__, __LINE__, error); 5096 5097 sc->dma_map_addr_rx_failed_count++; 5098 m_freem(m_new); 5099 5100 DBRUN(sc->debug_rx_mbuf_alloc--); 5101 5102 rc = ENOBUFS; 5103 goto bce_get_rx_buf_exit; 5104 } 5105 5106 /* All mbufs must map to a single segment. */ 5107 KASSERT(nsegs == 1, ("%s(): Too many segments returned (%d)!", 5108 __FUNCTION__, nsegs)); 5109 5110 /* Setup the rx_bd for the segment. */ 5111 rxbd = &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)]; 5112 5113 rxbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[0].ds_addr)); 5114 rxbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[0].ds_addr)); 5115 rxbd->rx_bd_len = htole32(segs[0].ds_len); 5116 rxbd->rx_bd_flags = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END); 5117 *prod_bseq += segs[0].ds_len; 5118 5119 /* Save the mbuf and update our counter. */ 5120 sc->rx_mbuf_ptr[*chain_prod] = m_new; 5121 sc->free_rx_bd -= nsegs; 5122 5123 DBRUNMSG(BCE_INSANE_RECV, 5124 bce_dump_rx_mbuf_chain(sc, debug_chain_prod, nsegs)); 5125 5126 DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): prod = 0x%04X, " 5127 "chain_prod = 0x%04X, prod_bseq = 0x%08X\n", 5128 __FUNCTION__, *prod, *chain_prod, *prod_bseq); 5129 5130bce_get_rx_buf_exit: 5131 DBEXIT(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5132 5133 return(rc); 5134} 5135 5136 5137#ifdef BCE_JUMBO_HDRSPLIT 5138/****************************************************************************/ 5139/* Encapsulate an mbuf cluster into the page chain. */ 5140/* */ 5141/* Returns: */ 5142/* 0 for success, positive value for failure. */ 5143/****************************************************************************/ 5144static int 5145bce_get_pg_buf(struct bce_softc *sc, struct mbuf *m, u16 *prod, 5146 u16 *prod_idx) 5147{ 5148 bus_dmamap_t map; 5149 bus_addr_t busaddr; 5150 struct mbuf *m_new = NULL; 5151 struct rx_bd *pgbd; 5152 int error, rc = 0; 5153#ifdef BCE_DEBUG 5154 u16 debug_prod_idx = *prod_idx; 5155#endif 5156 5157 DBENTER(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5158 5159 /* Make sure the inputs are valid. */ 5160 DBRUNIF((*prod_idx > MAX_PG_BD), 5161 BCE_PRINTF("%s(%d): page producer out of range: " 5162 "0x%04X > 0x%04X\n", __FILE__, __LINE__, 5163 *prod_idx, (u16) MAX_PG_BD)); 5164 5165 DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): prod = 0x%04X, " 5166 "chain_prod = 0x%04X\n", __FUNCTION__, *prod, *prod_idx); 5167 5168 /* Update counters if we've hit a new low or run out of pages. */ 5169 DBRUNIF((sc->free_pg_bd < sc->pg_low_watermark), 5170 sc->pg_low_watermark = sc->free_pg_bd); 5171 DBRUNIF((sc->free_pg_bd == sc->max_pg_bd), sc->pg_empty_count++); 5172 5173 /* Check whether this is a new mbuf allocation. */ 5174 if (m == NULL) { 5175 5176 /* Simulate an mbuf allocation failure. */ 5177 DBRUNIF(DB_RANDOMTRUE(mbuf_alloc_failed_sim_control), 5178 sc->mbuf_alloc_failed_count++; 5179 sc->mbuf_alloc_failed_sim_count++; 5180 rc = ENOBUFS; 5181 goto bce_get_pg_buf_exit); 5182 5183 /* This is a new mbuf allocation. */ 5184 m_new = m_getcl(M_DONTWAIT, MT_DATA, 0); 5185 if (m_new == NULL) { 5186 sc->mbuf_alloc_failed_count++; 5187 rc = ENOBUFS; 5188 goto bce_get_pg_buf_exit; 5189 } 5190 5191 DBRUN(sc->debug_pg_mbuf_alloc++); 5192 } else { 5193 /* Reuse an existing mbuf. */ 5194 m_new = m; 5195 m_new->m_data = m_new->m_ext.ext_buf; 5196 } 5197 5198 m_new->m_len = sc->pg_bd_mbuf_alloc_size; 5199 5200 /* ToDo: Consider calling m_fragment() to test error handling. */ 5201 5202 /* Map the mbuf cluster into device memory. */ 5203 map = sc->pg_mbuf_map[*prod_idx]; 5204 error = bus_dmamap_load(sc->pg_mbuf_tag, map, mtod(m_new, void *), 5205 sc->pg_bd_mbuf_alloc_size, bce_dma_map_addr, 5206 &busaddr, BUS_DMA_NOWAIT); 5207 5208 /* Handle any mapping errors. */ 5209 if (error) { 5210 BCE_PRINTF("%s(%d): Error mapping mbuf into page chain!\n", 5211 __FILE__, __LINE__); 5212 5213 m_freem(m_new); 5214 DBRUN(sc->debug_pg_mbuf_alloc--); 5215 5216 rc = ENOBUFS; 5217 goto bce_get_pg_buf_exit; 5218 } 5219 5220 /* ToDo: Do we need bus_dmamap_sync(,,BUS_DMASYNC_PREREAD) here? */ 5221 5222 /* 5223 * The page chain uses the same rx_bd data structure 5224 * as the receive chain but doesn't require a byte sequence (bseq). 5225 */ 5226 pgbd = &sc->pg_bd_chain[PG_PAGE(*prod_idx)][PG_IDX(*prod_idx)]; 5227 5228 pgbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(busaddr)); 5229 pgbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(busaddr)); 5230 pgbd->rx_bd_len = htole32(sc->pg_bd_mbuf_alloc_size); 5231 pgbd->rx_bd_flags = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END); 5232 5233 /* Save the mbuf and update our counter. */ 5234 sc->pg_mbuf_ptr[*prod_idx] = m_new; 5235 sc->free_pg_bd--; 5236 5237 DBRUNMSG(BCE_INSANE_RECV, 5238 bce_dump_pg_mbuf_chain(sc, debug_prod_idx, 1)); 5239 5240 DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): prod = 0x%04X, " 5241 "prod_idx = 0x%04X\n", __FUNCTION__, *prod, *prod_idx); 5242 5243bce_get_pg_buf_exit: 5244 DBEXIT(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5245 5246 return(rc); 5247} 5248#endif /* BCE_JUMBO_HDRSPLIT */ 5249 5250 5251/****************************************************************************/ 5252/* Initialize the TX context memory. */ 5253/* */ 5254/* Returns: */ 5255/* Nothing */ 5256/****************************************************************************/ 5257static void 5258bce_init_tx_context(struct bce_softc *sc) 5259{ 5260 u32 val; 5261 5262 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 5263 5264 /* Initialize the context ID for an L2 TX chain. */ 5265 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 5266 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 5267 /* Set the CID type to support an L2 connection. */ 5268 val = BCE_L2CTX_TX_TYPE_TYPE_L2_XI | 5269 BCE_L2CTX_TX_TYPE_SIZE_L2_XI; 5270 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE_XI, val); 5271 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2_XI | (8 << 16); 5272 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5273 BCE_L2CTX_TX_CMD_TYPE_XI, val); 5274 5275 /* Point the hardware to the first page in the chain. */ 5276 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]); 5277 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5278 BCE_L2CTX_TX_TBDR_BHADDR_HI_XI, val); 5279 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]); 5280 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5281 BCE_L2CTX_TX_TBDR_BHADDR_LO_XI, val); 5282 } else { 5283 /* Set the CID type to support an L2 connection. */ 5284 val = BCE_L2CTX_TX_TYPE_TYPE_L2 | BCE_L2CTX_TX_TYPE_SIZE_L2; 5285 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE, val); 5286 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2 | (8 << 16); 5287 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_CMD_TYPE, val); 5288 5289 /* Point the hardware to the first page in the chain. */ 5290 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]); 5291 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5292 BCE_L2CTX_TX_TBDR_BHADDR_HI, val); 5293 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]); 5294 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5295 BCE_L2CTX_TX_TBDR_BHADDR_LO, val); 5296 } 5297 5298 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 5299} 5300 5301 5302/****************************************************************************/ 5303/* Allocate memory and initialize the TX data structures. */ 5304/* */ 5305/* Returns: */ 5306/* 0 for success, positive value for failure. */ 5307/****************************************************************************/ 5308static int 5309bce_init_tx_chain(struct bce_softc *sc) 5310{ 5311 struct tx_bd *txbd; 5312 int i, rc = 0; 5313 5314 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_LOAD); 5315 5316 /* Set the initial TX producer/consumer indices. */ 5317 sc->tx_prod = 0; 5318 sc->tx_cons = 0; 5319 sc->tx_prod_bseq = 0; 5320 sc->used_tx_bd = 0; 5321 sc->max_tx_bd = USABLE_TX_BD; 5322 DBRUN(sc->tx_hi_watermark = 0); 5323 DBRUN(sc->tx_full_count = 0); 5324 5325 /* 5326 * The NetXtreme II supports a linked-list structre called 5327 * a Buffer Descriptor Chain (or BD chain). A BD chain 5328 * consists of a series of 1 or more chain pages, each of which 5329 * consists of a fixed number of BD entries. 5330 * The last BD entry on each page is a pointer to the next page 5331 * in the chain, and the last pointer in the BD chain 5332 * points back to the beginning of the chain. 5333 */ 5334 5335 /* Set the TX next pointer chain entries. */ 5336 for (i = 0; i < TX_PAGES; i++) { 5337 int j; 5338 5339 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE]; 5340 5341 /* Check if we've reached the last page. */ 5342 if (i == (TX_PAGES - 1)) 5343 j = 0; 5344 else 5345 j = i + 1; 5346 5347 txbd->tx_bd_haddr_hi = htole32(BCE_ADDR_HI(sc->tx_bd_chain_paddr[j])); 5348 txbd->tx_bd_haddr_lo = htole32(BCE_ADDR_LO(sc->tx_bd_chain_paddr[j])); 5349 } 5350 5351 bce_init_tx_context(sc); 5352 5353 DBRUNMSG(BCE_INSANE_SEND, bce_dump_tx_chain(sc, 0, TOTAL_TX_BD)); 5354 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_LOAD); 5355 5356 return(rc); 5357} 5358 5359 5360/****************************************************************************/ 5361/* Free memory and clear the TX data structures. */ 5362/* */ 5363/* Returns: */ 5364/* Nothing. */ 5365/****************************************************************************/ 5366static void 5367bce_free_tx_chain(struct bce_softc *sc) 5368{ 5369 int i; 5370 5371 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_UNLOAD); 5372 5373 /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */ 5374 for (i = 0; i < TOTAL_TX_BD; i++) { 5375 if (sc->tx_mbuf_ptr[i] != NULL) { 5376 if (sc->tx_mbuf_map[i] != NULL) 5377 bus_dmamap_sync(sc->tx_mbuf_tag, 5378 sc->tx_mbuf_map[i], 5379 BUS_DMASYNC_POSTWRITE); 5380 m_freem(sc->tx_mbuf_ptr[i]); 5381 sc->tx_mbuf_ptr[i] = NULL; 5382 DBRUN(sc->debug_tx_mbuf_alloc--); 5383 } 5384 } 5385 5386 /* Clear each TX chain page. */ 5387 for (i = 0; i < TX_PAGES; i++) 5388 bzero((char *)sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ); 5389 5390 sc->used_tx_bd = 0; 5391 5392 /* Check if we lost any mbufs in the process. */ 5393 DBRUNIF((sc->debug_tx_mbuf_alloc), 5394 BCE_PRINTF("%s(%d): Memory leak! Lost %d mbufs " 5395 "from tx chain!\n", __FILE__, __LINE__, 5396 sc->debug_tx_mbuf_alloc)); 5397 5398 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_UNLOAD); 5399} 5400 5401 5402/****************************************************************************/ 5403/* Initialize the RX context memory. */ 5404/* */ 5405/* Returns: */ 5406/* Nothing */ 5407/****************************************************************************/ 5408static void 5409bce_init_rx_context(struct bce_softc *sc) 5410{ 5411 u32 val; 5412 5413 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_CTX); 5414 5415 /* Init the type, size, and BD cache levels for the RX context. */ 5416 val = BCE_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE | 5417 BCE_L2CTX_RX_CTX_TYPE_SIZE_L2 | 5418 (0x02 << BCE_L2CTX_RX_BD_PRE_READ_SHIFT); 5419 5420 /* 5421 * Set the level for generating pause frames 5422 * when the number of available rx_bd's gets 5423 * too low (the low watermark) and the level 5424 * when pause frames can be stopped (the high 5425 * watermark). 5426 */ 5427 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 5428 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 5429 u32 lo_water, hi_water; 5430 5431 if (sc->bce_flags && BCE_USING_TX_FLOW_CONTROL) { 5432 lo_water = BCE_L2CTX_RX_LO_WATER_MARK_DEFAULT; 5433 } else { 5434 lo_water = 0; 5435 } 5436 5437 if (lo_water >= USABLE_RX_BD) { 5438 lo_water = 0; 5439 } 5440 5441 hi_water = USABLE_RX_BD / 4; 5442 5443 if (hi_water <= lo_water) { 5444 lo_water = 0; 5445 } 5446 5447 lo_water /= BCE_L2CTX_RX_LO_WATER_MARK_SCALE; 5448 hi_water /= BCE_L2CTX_RX_HI_WATER_MARK_SCALE; 5449 5450 if (hi_water > 0xf) 5451 hi_water = 0xf; 5452 else if (hi_water == 0) 5453 lo_water = 0; 5454 5455 val |= (lo_water << BCE_L2CTX_RX_LO_WATER_MARK_SHIFT) | 5456 (hi_water << BCE_L2CTX_RX_HI_WATER_MARK_SHIFT); 5457 } 5458 5459 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_CTX_TYPE, val); 5460 5461 /* Setup the MQ BIN mapping for l2_ctx_host_bseq. */ 5462 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 5463 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 5464 val = REG_RD(sc, BCE_MQ_MAP_L2_5); 5465 REG_WR(sc, BCE_MQ_MAP_L2_5, val | BCE_MQ_MAP_L2_5_ARM); 5466 } 5467 5468 /* Point the hardware to the first page in the chain. */ 5469 val = BCE_ADDR_HI(sc->rx_bd_chain_paddr[0]); 5470 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_HI, val); 5471 val = BCE_ADDR_LO(sc->rx_bd_chain_paddr[0]); 5472 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_LO, val); 5473 5474 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_CTX); 5475} 5476 5477 5478/****************************************************************************/ 5479/* Allocate memory and initialize the RX data structures. */ 5480/* */ 5481/* Returns: */ 5482/* 0 for success, positive value for failure. */ 5483/****************************************************************************/ 5484static int 5485bce_init_rx_chain(struct bce_softc *sc) 5486{ 5487 struct rx_bd *rxbd; 5488 int i, rc = 0; 5489 5490 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 5491 BCE_VERBOSE_CTX); 5492 5493 /* Initialize the RX producer and consumer indices. */ 5494 sc->rx_prod = 0; 5495 sc->rx_cons = 0; 5496 sc->rx_prod_bseq = 0; 5497 sc->free_rx_bd = USABLE_RX_BD; 5498 sc->max_rx_bd = USABLE_RX_BD; 5499 5500 /* Initialize the RX next pointer chain entries. */ 5501 for (i = 0; i < RX_PAGES; i++) { 5502 int j; 5503 5504 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE]; 5505 5506 /* Check if we've reached the last page. */ 5507 if (i == (RX_PAGES - 1)) 5508 j = 0; 5509 else 5510 j = i + 1; 5511 5512 /* Setup the chain page pointers. */ 5513 rxbd->rx_bd_haddr_hi = 5514 htole32(BCE_ADDR_HI(sc->rx_bd_chain_paddr[j])); 5515 rxbd->rx_bd_haddr_lo = 5516 htole32(BCE_ADDR_LO(sc->rx_bd_chain_paddr[j])); 5517 } 5518 5519 /* Fill up the RX chain. */ 5520 bce_fill_rx_chain(sc); 5521 5522 DBRUN(sc->rx_low_watermark = USABLE_RX_BD); 5523 DBRUN(sc->rx_empty_count = 0); 5524 for (i = 0; i < RX_PAGES; i++) { 5525 bus_dmamap_sync(sc->rx_bd_chain_tag, sc->rx_bd_chain_map[i], 5526 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 5527 } 5528 5529 bce_init_rx_context(sc); 5530 5531 DBRUNMSG(BCE_EXTREME_RECV, bce_dump_rx_bd_chain(sc, 0, TOTAL_RX_BD)); 5532 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 5533 BCE_VERBOSE_CTX); 5534 5535 /* ToDo: Are there possible failure modes here? */ 5536 5537 return(rc); 5538} 5539 5540 5541/****************************************************************************/ 5542/* Add mbufs to the RX chain until its full or an mbuf allocation error */ 5543/* occurs. */ 5544/* */ 5545/* Returns: */ 5546/* Nothing */ 5547/****************************************************************************/ 5548static void 5549bce_fill_rx_chain(struct bce_softc *sc) 5550{ 5551 u16 prod, prod_idx; 5552 u32 prod_bseq; 5553 5554 DBENTER(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 5555 BCE_VERBOSE_CTX); 5556 5557 /* Get the RX chain producer indices. */ 5558 prod = sc->rx_prod; 5559 prod_bseq = sc->rx_prod_bseq; 5560 5561 /* Keep filling the RX chain until it's full. */ 5562 while (sc->free_rx_bd > 0) { 5563 prod_idx = RX_CHAIN_IDX(prod); 5564 if (bce_get_rx_buf(sc, NULL, &prod, &prod_idx, &prod_bseq)) { 5565 /* Bail out if we can't add an mbuf to the chain. */ 5566 break; 5567 } 5568 prod = NEXT_RX_BD(prod); 5569 } 5570 5571 /* Save the RX chain producer indices. */ 5572 sc->rx_prod = prod; 5573 sc->rx_prod_bseq = prod_bseq; 5574 5575 /* We should never end up pointing to a next page pointer. */ 5576 DBRUNIF(((prod & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE), 5577 BCE_PRINTF("%s(): Invalid rx_prod value: 0x%04X\n", 5578 __FUNCTION__, sc->rx_prod)); 5579 5580 /* Write the mailbox and tell the chip about the waiting rx_bd's. */ 5581 REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + 5582 BCE_L2MQ_RX_HOST_BDIDX, sc->rx_prod); 5583 REG_WR(sc, MB_GET_CID_ADDR(RX_CID) + 5584 BCE_L2MQ_RX_HOST_BSEQ, sc->rx_prod_bseq); 5585 5586 DBEXIT(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 5587 BCE_VERBOSE_CTX); 5588} 5589 5590 5591/****************************************************************************/ 5592/* Free memory and clear the RX data structures. */ 5593/* */ 5594/* Returns: */ 5595/* Nothing. */ 5596/****************************************************************************/ 5597static void 5598bce_free_rx_chain(struct bce_softc *sc) 5599{ 5600 int i; 5601 5602 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 5603 5604 /* Free any mbufs still in the RX mbuf chain. */ 5605 for (i = 0; i < TOTAL_RX_BD; i++) { 5606 if (sc->rx_mbuf_ptr[i] != NULL) { 5607 if (sc->rx_mbuf_map[i] != NULL) 5608 bus_dmamap_sync(sc->rx_mbuf_tag, 5609 sc->rx_mbuf_map[i], 5610 BUS_DMASYNC_POSTREAD); 5611 m_freem(sc->rx_mbuf_ptr[i]); 5612 sc->rx_mbuf_ptr[i] = NULL; 5613 DBRUN(sc->debug_rx_mbuf_alloc--); 5614 } 5615 } 5616 5617 /* Clear each RX chain page. */ 5618 for (i = 0; i < RX_PAGES; i++) 5619 if (sc->rx_bd_chain[i] != NULL) { 5620 bzero((char *)sc->rx_bd_chain[i], 5621 BCE_RX_CHAIN_PAGE_SZ); 5622 } 5623 5624 sc->free_rx_bd = sc->max_rx_bd; 5625 5626 /* Check if we lost any mbufs in the process. */ 5627 DBRUNIF((sc->debug_rx_mbuf_alloc), 5628 BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from rx chain!\n", 5629 __FUNCTION__, sc->debug_rx_mbuf_alloc)); 5630 5631 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 5632} 5633 5634 5635#ifdef BCE_JUMBO_HDRSPLIT 5636/****************************************************************************/ 5637/* Allocate memory and initialize the page data structures. */ 5638/* Assumes that bce_init_rx_chain() has not already been called. */ 5639/* */ 5640/* Returns: */ 5641/* 0 for success, positive value for failure. */ 5642/****************************************************************************/ 5643static int 5644bce_init_pg_chain(struct bce_softc *sc) 5645{ 5646 struct rx_bd *pgbd; 5647 int i, rc = 0; 5648 u32 val; 5649 5650 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 5651 BCE_VERBOSE_CTX); 5652 5653 /* Initialize the page producer and consumer indices. */ 5654 sc->pg_prod = 0; 5655 sc->pg_cons = 0; 5656 sc->free_pg_bd = USABLE_PG_BD; 5657 sc->max_pg_bd = USABLE_PG_BD; 5658 DBRUN(sc->pg_low_watermark = sc->max_pg_bd); 5659 DBRUN(sc->pg_empty_count = 0); 5660 5661 /* Initialize the page next pointer chain entries. */ 5662 for (i = 0; i < PG_PAGES; i++) { 5663 int j; 5664 5665 pgbd = &sc->pg_bd_chain[i][USABLE_PG_BD_PER_PAGE]; 5666 5667 /* Check if we've reached the last page. */ 5668 if (i == (PG_PAGES - 1)) 5669 j = 0; 5670 else 5671 j = i + 1; 5672 5673 /* Setup the chain page pointers. */ 5674 pgbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(sc->pg_bd_chain_paddr[j])); 5675 pgbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(sc->pg_bd_chain_paddr[j])); 5676 } 5677 5678 /* Setup the MQ BIN mapping for host_pg_bidx. */ 5679 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 5680 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) 5681 REG_WR(sc, BCE_MQ_MAP_L2_3, BCE_MQ_MAP_L2_3_DEFAULT); 5682 5683 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_PG_BUF_SIZE, 0); 5684 5685 /* Configure the rx_bd and page chain mbuf cluster size. */ 5686 val = (sc->rx_bd_mbuf_data_len << 16) | sc->pg_bd_mbuf_alloc_size; 5687 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_PG_BUF_SIZE, val); 5688 5689 /* Configure the context reserved for jumbo support. */ 5690 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_RBDC_KEY, 5691 BCE_L2CTX_RX_RBDC_JUMBO_KEY); 5692 5693 /* Point the hardware to the first page in the page chain. */ 5694 val = BCE_ADDR_HI(sc->pg_bd_chain_paddr[0]); 5695 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_PG_BDHADDR_HI, val); 5696 val = BCE_ADDR_LO(sc->pg_bd_chain_paddr[0]); 5697 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_PG_BDHADDR_LO, val); 5698 5699 /* Fill up the page chain. */ 5700 bce_fill_pg_chain(sc); 5701 5702 for (i = 0; i < PG_PAGES; i++) { 5703 bus_dmamap_sync(sc->pg_bd_chain_tag, sc->pg_bd_chain_map[i], 5704 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 5705 } 5706 5707 DBRUNMSG(BCE_EXTREME_RECV, bce_dump_pg_chain(sc, 0, TOTAL_PG_BD)); 5708 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 5709 BCE_VERBOSE_CTX); 5710 return(rc); 5711} 5712 5713 5714/****************************************************************************/ 5715/* Add mbufs to the page chain until its full or an mbuf allocation error */ 5716/* occurs. */ 5717/* */ 5718/* Returns: */ 5719/* Nothing */ 5720/****************************************************************************/ 5721static void 5722bce_fill_pg_chain(struct bce_softc *sc) 5723{ 5724 u16 prod, prod_idx; 5725 5726 DBENTER(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 5727 BCE_VERBOSE_CTX); 5728 5729 /* Get the page chain prodcuer index. */ 5730 prod = sc->pg_prod; 5731 5732 /* Keep filling the page chain until it's full. */ 5733 while (sc->free_pg_bd > 0) { 5734 prod_idx = PG_CHAIN_IDX(prod); 5735 if (bce_get_pg_buf(sc, NULL, &prod, &prod_idx)) { 5736 /* Bail out if we can't add an mbuf to the chain. */ 5737 break; 5738 } 5739 prod = NEXT_PG_BD(prod); 5740 } 5741 5742 /* Save the page chain producer index. */ 5743 sc->pg_prod = prod; 5744 5745 DBRUNIF(((prod & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE), 5746 BCE_PRINTF("%s(): Invalid pg_prod value: 0x%04X\n", 5747 __FUNCTION__, sc->pg_prod)); 5748 5749 /* 5750 * Write the mailbox and tell the chip about 5751 * the new rx_bd's in the page chain. 5752 */ 5753 REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + 5754 BCE_L2MQ_RX_HOST_PG_BDIDX, sc->pg_prod); 5755 5756 DBEXIT(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 5757 BCE_VERBOSE_CTX); 5758} 5759 5760 5761/****************************************************************************/ 5762/* Free memory and clear the RX data structures. */ 5763/* */ 5764/* Returns: */ 5765/* Nothing. */ 5766/****************************************************************************/ 5767static void 5768bce_free_pg_chain(struct bce_softc *sc) 5769{ 5770 int i; 5771 5772 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 5773 5774 /* Free any mbufs still in the mbuf page chain. */ 5775 for (i = 0; i < TOTAL_PG_BD; i++) { 5776 if (sc->pg_mbuf_ptr[i] != NULL) { 5777 if (sc->pg_mbuf_map[i] != NULL) 5778 bus_dmamap_sync(sc->pg_mbuf_tag, 5779 sc->pg_mbuf_map[i], 5780 BUS_DMASYNC_POSTREAD); 5781 m_freem(sc->pg_mbuf_ptr[i]); 5782 sc->pg_mbuf_ptr[i] = NULL; 5783 DBRUN(sc->debug_pg_mbuf_alloc--); 5784 } 5785 } 5786 5787 /* Clear each page chain pages. */ 5788 for (i = 0; i < PG_PAGES; i++) 5789 bzero((char *)sc->pg_bd_chain[i], BCE_PG_CHAIN_PAGE_SZ); 5790 5791 sc->free_pg_bd = sc->max_pg_bd; 5792 5793 /* Check if we lost any mbufs in the process. */ 5794 DBRUNIF((sc->debug_pg_mbuf_alloc), 5795 BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from page chain!\n", 5796 __FUNCTION__, sc->debug_pg_mbuf_alloc)); 5797 5798 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 5799} 5800#endif /* BCE_JUMBO_HDRSPLIT */ 5801 5802 5803/****************************************************************************/ 5804/* Set media options. */ 5805/* */ 5806/* Returns: */ 5807/* 0 for success, positive value for failure. */ 5808/****************************************************************************/ 5809static int 5810bce_ifmedia_upd(struct ifnet *ifp) 5811{ 5812 struct bce_softc *sc = ifp->if_softc; 5813 5814 DBENTER(BCE_VERBOSE); 5815 5816 BCE_LOCK(sc); 5817 bce_ifmedia_upd_locked(ifp); 5818 BCE_UNLOCK(sc); 5819 5820 DBEXIT(BCE_VERBOSE); 5821 return (0); 5822} 5823 5824 5825/****************************************************************************/ 5826/* Set media options. */ 5827/* */ 5828/* Returns: */ 5829/* Nothing. */ 5830/****************************************************************************/ 5831static void 5832bce_ifmedia_upd_locked(struct ifnet *ifp) 5833{ 5834 struct bce_softc *sc = ifp->if_softc; 5835 struct mii_data *mii; 5836 5837 DBENTER(BCE_VERBOSE_PHY); 5838 5839 BCE_LOCK_ASSERT(sc); 5840 5841 mii = device_get_softc(sc->bce_miibus); 5842 5843 /* Make sure the MII bus has been enumerated. */ 5844 if (mii) { 5845 sc->bce_link_up = FALSE; 5846 if (mii->mii_instance) { 5847 struct mii_softc *miisc; 5848 5849 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 5850 mii_phy_reset(miisc); 5851 } 5852 mii_mediachg(mii); 5853 } 5854 5855 DBEXIT(BCE_VERBOSE_PHY); 5856} 5857 5858 5859/****************************************************************************/ 5860/* Reports current media status. */ 5861/* */ 5862/* Returns: */ 5863/* Nothing. */ 5864/****************************************************************************/ 5865static void 5866bce_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 5867{ 5868 struct bce_softc *sc = ifp->if_softc; 5869 struct mii_data *mii; 5870 5871 DBENTER(BCE_VERBOSE_PHY); 5872 5873 BCE_LOCK(sc); 5874 5875 mii = device_get_softc(sc->bce_miibus); 5876 5877 mii_pollstat(mii); 5878 ifmr->ifm_active = mii->mii_media_active; 5879 ifmr->ifm_status = mii->mii_media_status; 5880 5881 BCE_UNLOCK(sc); 5882 5883 DBEXIT(BCE_VERBOSE_PHY); 5884} 5885 5886 5887/****************************************************************************/ 5888/* Handles PHY generated interrupt events. */ 5889/* */ 5890/* Returns: */ 5891/* Nothing. */ 5892/****************************************************************************/ 5893static void 5894bce_phy_intr(struct bce_softc *sc) 5895{ 5896 u32 new_link_state, old_link_state; 5897 5898 DBENTER(BCE_VERBOSE_PHY | BCE_VERBOSE_INTR); 5899 5900 DBRUN(sc->phy_interrupts++); 5901 5902 new_link_state = sc->status_block->status_attn_bits & 5903 STATUS_ATTN_BITS_LINK_STATE; 5904 old_link_state = sc->status_block->status_attn_bits_ack & 5905 STATUS_ATTN_BITS_LINK_STATE; 5906 5907 /* Handle any changes if the link state has changed. */ 5908 if (new_link_state != old_link_state) { 5909 5910 /* Update the status_attn_bits_ack field. */ 5911 if (new_link_state) { 5912 REG_WR(sc, BCE_PCICFG_STATUS_BIT_SET_CMD, 5913 STATUS_ATTN_BITS_LINK_STATE); 5914 DBPRINT(sc, BCE_INFO_PHY, "%s(): Link is now UP.\n", 5915 __FUNCTION__); 5916 } 5917 else { 5918 REG_WR(sc, BCE_PCICFG_STATUS_BIT_CLEAR_CMD, 5919 STATUS_ATTN_BITS_LINK_STATE); 5920 DBPRINT(sc, BCE_INFO_PHY, "%s(): Link is now DOWN.\n", 5921 __FUNCTION__); 5922 } 5923 5924 /* 5925 * Assume link is down and allow 5926 * tick routine to update the state 5927 * based on the actual media state. 5928 */ 5929 sc->bce_link_up = FALSE; 5930 callout_stop(&sc->bce_tick_callout); 5931 bce_tick(sc); 5932 } 5933 5934 /* Acknowledge the link change interrupt. */ 5935 REG_WR(sc, BCE_EMAC_STATUS, BCE_EMAC_STATUS_LINK_CHANGE); 5936 5937 DBEXIT(BCE_VERBOSE_PHY | BCE_VERBOSE_INTR); 5938} 5939 5940 5941/****************************************************************************/ 5942/* Reads the receive consumer value from the status block (skipping over */ 5943/* chain page pointer if necessary). */ 5944/* */ 5945/* Returns: */ 5946/* hw_cons */ 5947/****************************************************************************/ 5948static inline u16 5949bce_get_hw_rx_cons(struct bce_softc *sc) 5950{ 5951 u16 hw_cons; 5952 5953 rmb(); 5954 hw_cons = sc->status_block->status_rx_quick_consumer_index0; 5955 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 5956 hw_cons++; 5957 5958 return hw_cons; 5959} 5960 5961/****************************************************************************/ 5962/* Handles received frame interrupt events. */ 5963/* */ 5964/* Returns: */ 5965/* Nothing. */ 5966/****************************************************************************/ 5967static void 5968bce_rx_intr(struct bce_softc *sc) 5969{ 5970 struct ifnet *ifp = sc->bce_ifp; 5971 struct l2_fhdr *l2fhdr; 5972 struct ether_vlan_header *vh; 5973 unsigned int pkt_len; 5974 u16 sw_rx_cons, sw_rx_cons_idx, hw_rx_cons; 5975 u32 status; 5976#ifdef BCE_JUMBO_HDRSPLIT 5977 unsigned int rem_len; 5978 u16 sw_pg_cons, sw_pg_cons_idx; 5979#endif 5980 5981 DBENTER(BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 5982 DBRUN(sc->interrupts_rx++); 5983 DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): rx_prod = 0x%04X, " 5984 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n", 5985 __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq); 5986 5987 /* Prepare the RX chain pages to be accessed by the host CPU. */ 5988 for (int i = 0; i < RX_PAGES; i++) 5989 bus_dmamap_sync(sc->rx_bd_chain_tag, 5990 sc->rx_bd_chain_map[i], BUS_DMASYNC_POSTREAD); 5991 5992#ifdef BCE_JUMBO_HDRSPLIT 5993 /* Prepare the page chain pages to be accessed by the host CPU. */ 5994 for (int i = 0; i < PG_PAGES; i++) 5995 bus_dmamap_sync(sc->pg_bd_chain_tag, 5996 sc->pg_bd_chain_map[i], BUS_DMASYNC_POSTREAD); 5997#endif 5998 5999 /* Get the hardware's view of the RX consumer index. */ 6000 hw_rx_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc); 6001 6002 /* Get working copies of the driver's view of the consumer indices. */ 6003 sw_rx_cons = sc->rx_cons; 6004 6005#ifdef BCE_JUMBO_HDRSPLIT 6006 sw_pg_cons = sc->pg_cons; 6007#endif 6008 6009 /* Update some debug statistics counters */ 6010 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 6011 sc->rx_low_watermark = sc->free_rx_bd); 6012 DBRUNIF((sc->free_rx_bd == sc->max_rx_bd), 6013 sc->rx_empty_count++); 6014 6015 /* Scan through the receive chain as long as there is work to do */ 6016 /* ToDo: Consider setting a limit on the number of packets processed. */ 6017 rmb(); 6018 while (sw_rx_cons != hw_rx_cons) { 6019 struct mbuf *m0; 6020 6021 /* Convert the producer/consumer indices to an actual rx_bd index. */ 6022 sw_rx_cons_idx = RX_CHAIN_IDX(sw_rx_cons); 6023 6024 /* Unmap the mbuf from DMA space. */ 6025 bus_dmamap_sync(sc->rx_mbuf_tag, 6026 sc->rx_mbuf_map[sw_rx_cons_idx], 6027 BUS_DMASYNC_POSTREAD); 6028 bus_dmamap_unload(sc->rx_mbuf_tag, 6029 sc->rx_mbuf_map[sw_rx_cons_idx]); 6030 6031 /* Remove the mbuf from the RX chain. */ 6032 m0 = sc->rx_mbuf_ptr[sw_rx_cons_idx]; 6033 sc->rx_mbuf_ptr[sw_rx_cons_idx] = NULL; 6034 DBRUN(sc->debug_rx_mbuf_alloc--); 6035 sc->free_rx_bd++; 6036 6037 if(m0 == NULL) { 6038 DBPRINT(sc, BCE_EXTREME_RECV, 6039 "%s(): Oops! Empty mbuf pointer " 6040 "found in sc->rx_mbuf_ptr[0x%04X]!\n", 6041 __FUNCTION__, sw_rx_cons_idx); 6042 goto bce_rx_int_next_rx; 6043 } 6044 6045 /* 6046 * Frames received on the NetXteme II are prepended 6047 * with an l2_fhdr structure which provides status 6048 * information about the received frame (including 6049 * VLAN tags and checksum info). The frames are 6050 * also automatically adjusted to align the IP 6051 * header (i.e. two null bytes are inserted before 6052 * the Ethernet header). As a result the data 6053 * DMA'd by the controller into the mbuf looks 6054 * like this: 6055 * 6056 * +---------+-----+---------------------+-----+ 6057 * | l2_fhdr | pad | packet data | FCS | 6058 * +---------+-----+---------------------+-----+ 6059 * 6060 * The l2_fhdr needs to be checked and skipped and 6061 * the FCS needs to be stripped before sending the 6062 * packet up the stack. 6063 */ 6064 l2fhdr = mtod(m0, struct l2_fhdr *); 6065 6066 /* Get the packet data + FCS length and the status. */ 6067 pkt_len = l2fhdr->l2_fhdr_pkt_len; 6068 status = l2fhdr->l2_fhdr_status; 6069 6070 /* 6071 * Skip over the l2_fhdr and pad, resulting in the 6072 * following data in the mbuf: 6073 * +---------------------+-----+ 6074 * | packet data | FCS | 6075 * +---------------------+-----+ 6076 */ 6077 m_adj(m0, sizeof(struct l2_fhdr) + ETHER_ALIGN); 6078 6079#ifdef BCE_JUMBO_HDRSPLIT 6080 /* 6081 * Check whether the received frame fits in a single 6082 * mbuf or not (i.e. packet data + FCS <= 6083 * sc->rx_bd_mbuf_data_len bytes). 6084 */ 6085 if (pkt_len > m0->m_len) { 6086 /* 6087 * The received frame is larger than a single mbuf. 6088 * If the frame was a TCP frame then only the TCP 6089 * header is placed in the mbuf, the remaining 6090 * payload (including FCS) is placed in the page 6091 * chain, the SPLIT flag is set, and the header 6092 * length is placed in the IP checksum field. 6093 * If the frame is not a TCP frame then the mbuf 6094 * is filled and the remaining bytes are placed 6095 * in the page chain. 6096 */ 6097 6098 DBPRINT(sc, BCE_INFO_RECV, "%s(): Found a large " 6099 "packet.\n", __FUNCTION__); 6100 6101 /* 6102 * When the page chain is enabled and the TCP 6103 * header has been split from the TCP payload, 6104 * the ip_xsum structure will reflect the length 6105 * of the TCP header, not the IP checksum. Set 6106 * the packet length of the mbuf accordingly. 6107 */ 6108 if (status & L2_FHDR_STATUS_SPLIT) 6109 m0->m_len = l2fhdr->l2_fhdr_ip_xsum; 6110 6111 rem_len = pkt_len - m0->m_len; 6112 6113 /* Pull mbufs off the page chain for the remaining data. */ 6114 while (rem_len > 0) { 6115 struct mbuf *m_pg; 6116 6117 sw_pg_cons_idx = PG_CHAIN_IDX(sw_pg_cons); 6118 6119 /* Remove the mbuf from the page chain. */ 6120 m_pg = sc->pg_mbuf_ptr[sw_pg_cons_idx]; 6121 sc->pg_mbuf_ptr[sw_pg_cons_idx] = NULL; 6122 DBRUN(sc->debug_pg_mbuf_alloc--); 6123 sc->free_pg_bd++; 6124 6125 /* Unmap the page chain mbuf from DMA space. */ 6126 bus_dmamap_sync(sc->pg_mbuf_tag, 6127 sc->pg_mbuf_map[sw_pg_cons_idx], 6128 BUS_DMASYNC_POSTREAD); 6129 bus_dmamap_unload(sc->pg_mbuf_tag, 6130 sc->pg_mbuf_map[sw_pg_cons_idx]); 6131 6132 /* Adjust the mbuf length. */ 6133 if (rem_len < m_pg->m_len) { 6134 /* The mbuf chain is complete. */ 6135 m_pg->m_len = rem_len; 6136 rem_len = 0; 6137 } else { 6138 /* More packet data is waiting. */ 6139 rem_len -= m_pg->m_len; 6140 } 6141 6142 /* Concatenate the mbuf cluster to the mbuf. */ 6143 m_cat(m0, m_pg); 6144 6145 sw_pg_cons = NEXT_PG_BD(sw_pg_cons); 6146 } 6147 6148 /* Set the total packet length. */ 6149 m0->m_pkthdr.len = pkt_len; 6150 6151 } else { 6152 /* 6153 * The received packet is small and fits in a 6154 * single mbuf (i.e. the l2_fhdr + pad + packet + 6155 * FCS <= MHLEN). In other words, the packet is 6156 * 154 bytes or less in size. 6157 */ 6158 6159 DBPRINT(sc, BCE_INFO_RECV, "%s(): Found a small " 6160 "packet.\n", __FUNCTION__); 6161 6162 /* Set the total packet length. */ 6163 m0->m_pkthdr.len = m0->m_len = pkt_len; 6164 } 6165#else 6166 /* Set the total packet length. */ 6167 m0->m_pkthdr.len = m0->m_len = pkt_len; 6168#endif 6169 6170 /* Remove the trailing Ethernet FCS. */ 6171 m_adj(m0, -ETHER_CRC_LEN); 6172 6173 /* Check that the resulting mbuf chain is valid. */ 6174 DBRUN(m_sanity(m0, FALSE)); 6175 DBRUNIF(((m0->m_len < ETHER_HDR_LEN) | 6176 (m0->m_pkthdr.len > BCE_MAX_JUMBO_ETHER_MTU_VLAN)), 6177 BCE_PRINTF("Invalid Ethernet frame size!\n"); 6178 m_print(m0, 128)); 6179 6180 DBRUNIF(DB_RANDOMTRUE(l2fhdr_error_sim_control), 6181 sc->l2fhdr_error_sim_count++; 6182 status = status | L2_FHDR_ERRORS_PHY_DECODE); 6183 6184 /* Check the received frame for errors. */ 6185 if (status & (L2_FHDR_ERRORS_BAD_CRC | 6186 L2_FHDR_ERRORS_PHY_DECODE | L2_FHDR_ERRORS_ALIGNMENT | 6187 L2_FHDR_ERRORS_TOO_SHORT | L2_FHDR_ERRORS_GIANT_FRAME)) { 6188 6189 /* Log the error and release the mbuf. */ 6190 ifp->if_ierrors++; 6191 sc->l2fhdr_error_count++; 6192 6193 m_freem(m0); 6194 m0 = NULL; 6195 goto bce_rx_int_next_rx; 6196 } 6197 6198 /* Send the packet to the appropriate interface. */ 6199 m0->m_pkthdr.rcvif = ifp; 6200 6201 /* Assume no hardware checksum. */ 6202 m0->m_pkthdr.csum_flags = 0; 6203 6204 /* Validate the checksum if offload enabled. */ 6205 if (ifp->if_capenable & IFCAP_RXCSUM) { 6206 6207 /* Check for an IP datagram. */ 6208 if (!(status & L2_FHDR_STATUS_SPLIT) && 6209 (status & L2_FHDR_STATUS_IP_DATAGRAM)) { 6210 m0->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 6211 DBRUN(sc->csum_offload_ip++); 6212 /* Check if the IP checksum is valid. */ 6213 if ((l2fhdr->l2_fhdr_ip_xsum ^ 0xffff) == 0) 6214 m0->m_pkthdr.csum_flags |= 6215 CSUM_IP_VALID; 6216 } 6217 6218 /* Check for a valid TCP/UDP frame. */ 6219 if (status & (L2_FHDR_STATUS_TCP_SEGMENT | 6220 L2_FHDR_STATUS_UDP_DATAGRAM)) { 6221 6222 /* Check for a good TCP/UDP checksum. */ 6223 if ((status & (L2_FHDR_ERRORS_TCP_XSUM | 6224 L2_FHDR_ERRORS_UDP_XSUM)) == 0) { 6225 DBRUN(sc->csum_offload_tcp_udp++); 6226 m0->m_pkthdr.csum_data = 6227 l2fhdr->l2_fhdr_tcp_udp_xsum; 6228 m0->m_pkthdr.csum_flags |= 6229 (CSUM_DATA_VALID 6230 | CSUM_PSEUDO_HDR); 6231 } 6232 } 6233 } 6234 6235 /* Attach the VLAN tag. */ 6236 if (status & L2_FHDR_STATUS_L2_VLAN_TAG) { 6237 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) { 6238#if __FreeBSD_version < 700000 6239 VLAN_INPUT_TAG(ifp, m0, 6240 l2fhdr->l2_fhdr_vlan_tag, continue); 6241#else 6242 m0->m_pkthdr.ether_vtag = 6243 l2fhdr->l2_fhdr_vlan_tag; 6244 m0->m_flags |= M_VLANTAG; 6245#endif 6246 } else { 6247 /* 6248 * bce(4) controllers can't disable VLAN 6249 * tag stripping if management firmware 6250 * (ASF/IPMI/UMP) is running. So we always 6251 * strip VLAN tag and manually reconstruct 6252 * the VLAN frame by appending stripped 6253 * VLAN tag in driver if VLAN tag stripping 6254 * was disabled. 6255 * 6256 * TODO: LLC SNAP handling. 6257 */ 6258 bcopy(mtod(m0, uint8_t *), 6259 mtod(m0, uint8_t *) - ETHER_VLAN_ENCAP_LEN, 6260 ETHER_ADDR_LEN * 2); 6261 m0->m_data -= ETHER_VLAN_ENCAP_LEN; 6262 vh = mtod(m0, struct ether_vlan_header *); 6263 vh->evl_encap_proto = htons(ETHERTYPE_VLAN); 6264 vh->evl_tag = htons(l2fhdr->l2_fhdr_vlan_tag); 6265 m0->m_pkthdr.len += ETHER_VLAN_ENCAP_LEN; 6266 m0->m_len += ETHER_VLAN_ENCAP_LEN; 6267 } 6268 } 6269 6270 /* Increment received packet statistics. */ 6271 ifp->if_ipackets++; 6272 6273bce_rx_int_next_rx: 6274 sw_rx_cons = NEXT_RX_BD(sw_rx_cons); 6275 6276 /* If we have a packet, pass it up the stack */ 6277 if (m0) { 6278 /* Make sure we don't lose our place when we release the lock. */ 6279 sc->rx_cons = sw_rx_cons; 6280#ifdef BCE_JUMBO_HDRSPLIT 6281 sc->pg_cons = sw_pg_cons; 6282#endif 6283 6284 BCE_UNLOCK(sc); 6285 (*ifp->if_input)(ifp, m0); 6286 BCE_LOCK(sc); 6287 6288 /* Recover our place. */ 6289 sw_rx_cons = sc->rx_cons; 6290#ifdef BCE_JUMBO_HDRSPLIT 6291 sw_pg_cons = sc->pg_cons; 6292#endif 6293 } 6294 6295 /* Refresh hw_cons to see if there's new work */ 6296 if (sw_rx_cons == hw_rx_cons) 6297 hw_rx_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc); 6298 } 6299 6300#ifdef BCE_JUMBO_HDRSPLIT 6301 /* No new packets. Refill the page chain. */ 6302 sc->pg_cons = sw_pg_cons; 6303 bce_fill_pg_chain(sc); 6304#endif 6305 6306 /* No new packets. Refill the RX chain. */ 6307 sc->rx_cons = sw_rx_cons; 6308 bce_fill_rx_chain(sc); 6309 6310 /* Prepare the page chain pages to be accessed by the NIC. */ 6311 for (int i = 0; i < RX_PAGES; i++) 6312 bus_dmamap_sync(sc->rx_bd_chain_tag, 6313 sc->rx_bd_chain_map[i], BUS_DMASYNC_PREWRITE); 6314 6315#ifdef BCE_JUMBO_HDRSPLIT 6316 for (int i = 0; i < PG_PAGES; i++) 6317 bus_dmamap_sync(sc->pg_bd_chain_tag, 6318 sc->pg_bd_chain_map[i], BUS_DMASYNC_PREWRITE); 6319#endif 6320 6321 DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): rx_prod = 0x%04X, " 6322 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n", 6323 __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq); 6324 DBEXIT(BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 6325} 6326 6327 6328/****************************************************************************/ 6329/* Reads the transmit consumer value from the status block (skipping over */ 6330/* chain page pointer if necessary). */ 6331/* */ 6332/* Returns: */ 6333/* hw_cons */ 6334/****************************************************************************/ 6335static inline u16 6336bce_get_hw_tx_cons(struct bce_softc *sc) 6337{ 6338 u16 hw_cons; 6339 6340 mb(); 6341 hw_cons = sc->status_block->status_tx_quick_consumer_index0; 6342 if ((hw_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 6343 hw_cons++; 6344 6345 return hw_cons; 6346} 6347 6348 6349/****************************************************************************/ 6350/* Handles transmit completion interrupt events. */ 6351/* */ 6352/* Returns: */ 6353/* Nothing. */ 6354/****************************************************************************/ 6355static void 6356bce_tx_intr(struct bce_softc *sc) 6357{ 6358 struct ifnet *ifp = sc->bce_ifp; 6359 u16 hw_tx_cons, sw_tx_cons, sw_tx_chain_cons; 6360 6361 DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_INTR); 6362 DBRUN(sc->interrupts_tx++); 6363 DBPRINT(sc, BCE_EXTREME_SEND, "%s(enter): tx_prod = 0x%04X, " 6364 "tx_cons = 0x%04X, tx_prod_bseq = 0x%08X\n", 6365 __FUNCTION__, sc->tx_prod, sc->tx_cons, sc->tx_prod_bseq); 6366 6367 BCE_LOCK_ASSERT(sc); 6368 6369 /* Get the hardware's view of the TX consumer index. */ 6370 hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc); 6371 sw_tx_cons = sc->tx_cons; 6372 6373 /* Prevent speculative reads of the status block. */ 6374 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 6375 BUS_SPACE_BARRIER_READ); 6376 6377 /* Cycle through any completed TX chain page entries. */ 6378 while (sw_tx_cons != hw_tx_cons) { 6379#ifdef BCE_DEBUG 6380 struct tx_bd *txbd = NULL; 6381#endif 6382 sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons); 6383 6384 DBPRINT(sc, BCE_INFO_SEND, 6385 "%s(): hw_tx_cons = 0x%04X, sw_tx_cons = 0x%04X, " 6386 "sw_tx_chain_cons = 0x%04X\n", 6387 __FUNCTION__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons); 6388 6389 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD), 6390 BCE_PRINTF("%s(%d): TX chain consumer out of range! " 6391 " 0x%04X > 0x%04X\n", __FILE__, __LINE__, sw_tx_chain_cons, 6392 (int) MAX_TX_BD); 6393 bce_breakpoint(sc)); 6394 6395 DBRUN(txbd = &sc->tx_bd_chain[TX_PAGE(sw_tx_chain_cons)] 6396 [TX_IDX(sw_tx_chain_cons)]); 6397 6398 DBRUNIF((txbd == NULL), 6399 BCE_PRINTF("%s(%d): Unexpected NULL tx_bd[0x%04X]!\n", 6400 __FILE__, __LINE__, sw_tx_chain_cons); 6401 bce_breakpoint(sc)); 6402 6403 DBRUNMSG(BCE_INFO_SEND, BCE_PRINTF("%s(): ", __FUNCTION__); 6404 bce_dump_txbd(sc, sw_tx_chain_cons, txbd)); 6405 6406 /* 6407 * Free the associated mbuf. Remember 6408 * that only the last tx_bd of a packet 6409 * has an mbuf pointer and DMA map. 6410 */ 6411 if (sc->tx_mbuf_ptr[sw_tx_chain_cons] != NULL) { 6412 6413 /* Validate that this is the last tx_bd. */ 6414 DBRUNIF((!(txbd->tx_bd_flags & TX_BD_FLAGS_END)), 6415 BCE_PRINTF("%s(%d): tx_bd END flag not set but " 6416 "txmbuf == NULL!\n", __FILE__, __LINE__); 6417 bce_breakpoint(sc)); 6418 6419 DBRUNMSG(BCE_INFO_SEND, 6420 BCE_PRINTF("%s(): Unloading map/freeing mbuf " 6421 "from tx_bd[0x%04X]\n", __FUNCTION__, 6422 sw_tx_chain_cons)); 6423 6424 /* Unmap the mbuf. */ 6425 bus_dmamap_unload(sc->tx_mbuf_tag, 6426 sc->tx_mbuf_map[sw_tx_chain_cons]); 6427 6428 /* Free the mbuf. */ 6429 m_freem(sc->tx_mbuf_ptr[sw_tx_chain_cons]); 6430 sc->tx_mbuf_ptr[sw_tx_chain_cons] = NULL; 6431 DBRUN(sc->debug_tx_mbuf_alloc--); 6432 6433 ifp->if_opackets++; 6434 } 6435 6436 sc->used_tx_bd--; 6437 sw_tx_cons = NEXT_TX_BD(sw_tx_cons); 6438 6439 /* Refresh hw_cons to see if there's new work. */ 6440 hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc); 6441 6442 /* Prevent speculative reads of the status block. */ 6443 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 6444 BUS_SPACE_BARRIER_READ); 6445 } 6446 6447 /* Clear the TX timeout timer. */ 6448 sc->watchdog_timer = 0; 6449 6450 /* Clear the tx hardware queue full flag. */ 6451 if (sc->used_tx_bd < sc->max_tx_bd) { 6452 DBRUNIF((ifp->if_drv_flags & IFF_DRV_OACTIVE), 6453 DBPRINT(sc, BCE_INFO_SEND, 6454 "%s(): Open TX chain! %d/%d (used/total)\n", 6455 __FUNCTION__, sc->used_tx_bd, sc->max_tx_bd)); 6456 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 6457 } 6458 6459 sc->tx_cons = sw_tx_cons; 6460 6461 DBPRINT(sc, BCE_EXTREME_SEND, "%s(exit): tx_prod = 0x%04X, " 6462 "tx_cons = 0x%04X, tx_prod_bseq = 0x%08X\n", 6463 __FUNCTION__, sc->tx_prod, sc->tx_cons, sc->tx_prod_bseq); 6464 DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_INTR); 6465} 6466 6467 6468/****************************************************************************/ 6469/* Disables interrupt generation. */ 6470/* */ 6471/* Returns: */ 6472/* Nothing. */ 6473/****************************************************************************/ 6474static void 6475bce_disable_intr(struct bce_softc *sc) 6476{ 6477 DBENTER(BCE_VERBOSE_INTR); 6478 6479 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT); 6480 REG_RD(sc, BCE_PCICFG_INT_ACK_CMD); 6481 6482 DBEXIT(BCE_VERBOSE_INTR); 6483} 6484 6485 6486/****************************************************************************/ 6487/* Enables interrupt generation. */ 6488/* */ 6489/* Returns: */ 6490/* Nothing. */ 6491/****************************************************************************/ 6492static void 6493bce_enable_intr(struct bce_softc *sc, int coal_now) 6494{ 6495 DBENTER(BCE_VERBOSE_INTR); 6496 6497 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 6498 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | 6499 BCE_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx); 6500 6501 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 6502 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx); 6503 6504 /* Force an immediate interrupt (whether there is new data or not). */ 6505 if (coal_now) 6506 REG_WR(sc, BCE_HC_COMMAND, sc->hc_command | BCE_HC_COMMAND_COAL_NOW); 6507 6508 DBEXIT(BCE_VERBOSE_INTR); 6509} 6510 6511 6512/****************************************************************************/ 6513/* Handles controller initialization. */ 6514/* */ 6515/* Returns: */ 6516/* Nothing. */ 6517/****************************************************************************/ 6518static void 6519bce_init_locked(struct bce_softc *sc) 6520{ 6521 struct ifnet *ifp; 6522 u32 ether_mtu = 0; 6523 6524 DBENTER(BCE_VERBOSE_RESET); 6525 6526 BCE_LOCK_ASSERT(sc); 6527 6528 ifp = sc->bce_ifp; 6529 6530 /* Check if the driver is still running and bail out if it is. */ 6531 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 6532 goto bce_init_locked_exit; 6533 6534 bce_stop(sc); 6535 6536 if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) { 6537 BCE_PRINTF("%s(%d): Controller reset failed!\n", 6538 __FILE__, __LINE__); 6539 goto bce_init_locked_exit; 6540 } 6541 6542 if (bce_chipinit(sc)) { 6543 BCE_PRINTF("%s(%d): Controller initialization failed!\n", 6544 __FILE__, __LINE__); 6545 goto bce_init_locked_exit; 6546 } 6547 6548 if (bce_blockinit(sc)) { 6549 BCE_PRINTF("%s(%d): Block initialization failed!\n", 6550 __FILE__, __LINE__); 6551 goto bce_init_locked_exit; 6552 } 6553 6554 /* Load our MAC address. */ 6555 bcopy(IF_LLADDR(sc->bce_ifp), sc->eaddr, ETHER_ADDR_LEN); 6556 bce_set_mac_addr(sc); 6557 6558 /* 6559 * Calculate and program the hardware Ethernet MTU 6560 * size. Be generous on the receive if we have room. 6561 */ 6562#ifdef BCE_JUMBO_HDRSPLIT 6563 if (ifp->if_mtu <= (sc->rx_bd_mbuf_data_len + 6564 sc->pg_bd_mbuf_alloc_size)) 6565 ether_mtu = sc->rx_bd_mbuf_data_len + 6566 sc->pg_bd_mbuf_alloc_size; 6567#else 6568 if (ifp->if_mtu <= sc->rx_bd_mbuf_data_len) 6569 ether_mtu = sc->rx_bd_mbuf_data_len; 6570#endif 6571 else 6572 ether_mtu = ifp->if_mtu; 6573 6574 ether_mtu += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN; 6575 6576 DBPRINT(sc, BCE_INFO_MISC, "%s(): setting h/w mtu = %d\n", 6577 __FUNCTION__, ether_mtu); 6578 6579 /* Program the mtu, enabling jumbo frame support if necessary. */ 6580 if (ether_mtu > (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN)) 6581 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, 6582 min(ether_mtu, BCE_MAX_JUMBO_ETHER_MTU) | 6583 BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA); 6584 else 6585 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, ether_mtu); 6586 6587 DBPRINT(sc, BCE_INFO_LOAD, 6588 "%s(): rx_bd_mbuf_alloc_size = %d, rx_bce_mbuf_data_len = %d, " 6589 "rx_bd_mbuf_align_pad = %d\n", __FUNCTION__, 6590 sc->rx_bd_mbuf_alloc_size, sc->rx_bd_mbuf_data_len, 6591 sc->rx_bd_mbuf_align_pad); 6592 6593 /* Program appropriate promiscuous/multicast filtering. */ 6594 bce_set_rx_mode(sc); 6595 6596#ifdef BCE_JUMBO_HDRSPLIT 6597 DBPRINT(sc, BCE_INFO_LOAD, "%s(): pg_bd_mbuf_alloc_size = %d\n", 6598 __FUNCTION__, sc->pg_bd_mbuf_alloc_size); 6599 6600 /* Init page buffer descriptor chain. */ 6601 bce_init_pg_chain(sc); 6602#endif 6603 6604 /* Init RX buffer descriptor chain. */ 6605 bce_init_rx_chain(sc); 6606 6607 /* Init TX buffer descriptor chain. */ 6608 bce_init_tx_chain(sc); 6609 6610 /* Enable host interrupts. */ 6611 bce_enable_intr(sc, 1); 6612 6613 bce_ifmedia_upd_locked(ifp); 6614 6615 /* Let the OS know the driver is up and running. */ 6616 ifp->if_drv_flags |= IFF_DRV_RUNNING; 6617 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 6618 6619 callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc); 6620 6621bce_init_locked_exit: 6622 DBEXIT(BCE_VERBOSE_RESET); 6623} 6624 6625 6626/****************************************************************************/ 6627/* Initialize the controller just enough so that any management firmware */ 6628/* running on the device will continue to operate correctly. */ 6629/* */ 6630/* Returns: */ 6631/* Nothing. */ 6632/****************************************************************************/ 6633static void 6634bce_mgmt_init_locked(struct bce_softc *sc) 6635{ 6636 struct ifnet *ifp; 6637 6638 DBENTER(BCE_VERBOSE_RESET); 6639 6640 BCE_LOCK_ASSERT(sc); 6641 6642 /* Bail out if management firmware is not running. */ 6643 if (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG)) { 6644 DBPRINT(sc, BCE_VERBOSE_SPECIAL, 6645 "No management firmware running...\n"); 6646 goto bce_mgmt_init_locked_exit; 6647 } 6648 6649 ifp = sc->bce_ifp; 6650 6651 /* Enable all critical blocks in the MAC. */ 6652 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT); 6653 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS); 6654 DELAY(20); 6655 6656 bce_ifmedia_upd_locked(ifp); 6657 6658bce_mgmt_init_locked_exit: 6659 DBEXIT(BCE_VERBOSE_RESET); 6660} 6661 6662 6663/****************************************************************************/ 6664/* Handles controller initialization when called from an unlocked routine. */ 6665/* */ 6666/* Returns: */ 6667/* Nothing. */ 6668/****************************************************************************/ 6669static void 6670bce_init(void *xsc) 6671{ 6672 struct bce_softc *sc = xsc; 6673 6674 DBENTER(BCE_VERBOSE_RESET); 6675 6676 BCE_LOCK(sc); 6677 bce_init_locked(sc); 6678 BCE_UNLOCK(sc); 6679 6680 DBEXIT(BCE_VERBOSE_RESET); 6681} 6682 6683 6684/****************************************************************************/ 6685/* Modifies an mbuf for TSO on the hardware. */ 6686/* */ 6687/* Returns: */ 6688/* Pointer to a modified mbuf. */ 6689/****************************************************************************/ 6690static struct mbuf * 6691bce_tso_setup(struct bce_softc *sc, struct mbuf **m_head, u16 *flags) 6692{ 6693 struct mbuf *m; 6694 struct ether_header *eh; 6695 struct ip *ip; 6696 struct tcphdr *th; 6697 u16 etype; 6698 int hdr_len, ip_hlen = 0, tcp_hlen = 0, ip_len = 0; 6699 6700 DBRUN(sc->tso_frames_requested++); 6701 6702 /* Controller may modify mbuf chains. */ 6703 if (M_WRITABLE(*m_head) == 0) { 6704 m = m_dup(*m_head, M_DONTWAIT); 6705 m_freem(*m_head); 6706 if (m == NULL) { 6707 sc->mbuf_alloc_failed_count++; 6708 *m_head = NULL; 6709 return (NULL); 6710 } 6711 *m_head = m; 6712 } 6713 6714 /* 6715 * For TSO the controller needs two pieces of info, 6716 * the MSS and the IP+TCP options length. 6717 */ 6718 m = m_pullup(*m_head, sizeof(struct ether_header) + sizeof(struct ip)); 6719 if (m == NULL) { 6720 *m_head = NULL; 6721 return (NULL); 6722 } 6723 eh = mtod(m, struct ether_header *); 6724 etype = ntohs(eh->ether_type); 6725 6726 /* Check for supported TSO Ethernet types (only IPv4 for now) */ 6727 switch (etype) { 6728 case ETHERTYPE_IP: 6729 ip = (struct ip *)(m->m_data + sizeof(struct ether_header)); 6730 /* TSO only supported for TCP protocol. */ 6731 if (ip->ip_p != IPPROTO_TCP) { 6732 BCE_PRINTF("%s(%d): TSO enabled for non-TCP frame!.\n", 6733 __FILE__, __LINE__); 6734 m_freem(*m_head); 6735 *m_head = NULL; 6736 return (NULL); 6737 } 6738 6739 /* Get IP header length in bytes (min 20) */ 6740 ip_hlen = ip->ip_hl << 2; 6741 m = m_pullup(*m_head, sizeof(struct ether_header) + ip_hlen + 6742 sizeof(struct tcphdr)); 6743 if (m == NULL) { 6744 *m_head = NULL; 6745 return (NULL); 6746 } 6747 6748 /* Get the TCP header length in bytes (min 20) */ 6749 th = (struct tcphdr *)((caddr_t)ip + ip_hlen); 6750 tcp_hlen = (th->th_off << 2); 6751 6752 /* Make sure all IP/TCP options live in the same buffer. */ 6753 m = m_pullup(*m_head, sizeof(struct ether_header)+ ip_hlen + 6754 tcp_hlen); 6755 if (m == NULL) { 6756 *m_head = NULL; 6757 return (NULL); 6758 } 6759 6760 /* IP header length and checksum will be calc'd by hardware */ 6761 ip_len = ip->ip_len; 6762 ip->ip_len = 0; 6763 ip->ip_sum = 0; 6764 break; 6765 case ETHERTYPE_IPV6: 6766 BCE_PRINTF("%s(%d): TSO over IPv6 not supported!.\n", 6767 __FILE__, __LINE__); 6768 m_freem(*m_head); 6769 *m_head = NULL; 6770 return (NULL); 6771 /* NOT REACHED */ 6772 default: 6773 BCE_PRINTF("%s(%d): TSO enabled for unsupported protocol!.\n", 6774 __FILE__, __LINE__); 6775 m_freem(*m_head); 6776 *m_head = NULL; 6777 return (NULL); 6778 } 6779 6780 hdr_len = sizeof(struct ether_header) + ip_hlen + tcp_hlen; 6781 6782 DBPRINT(sc, BCE_EXTREME_SEND, "%s(): hdr_len = %d, e_hlen = %d, " 6783 "ip_hlen = %d, tcp_hlen = %d, ip_len = %d\n", 6784 __FUNCTION__, hdr_len, (int) sizeof(struct ether_header), ip_hlen, 6785 tcp_hlen, ip_len); 6786 6787 /* Set the LSO flag in the TX BD */ 6788 *flags |= TX_BD_FLAGS_SW_LSO; 6789 6790 /* Set the length of IP + TCP options (in 32 bit words) */ 6791 *flags |= (((ip_hlen + tcp_hlen - sizeof(struct ip) - 6792 sizeof(struct tcphdr)) >> 2) << 8); 6793 6794 DBRUN(sc->tso_frames_completed++); 6795 return (*m_head); 6796} 6797 6798 6799/****************************************************************************/ 6800/* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */ 6801/* memory visible to the controller. */ 6802/* */ 6803/* Returns: */ 6804/* 0 for success, positive value for failure. */ 6805/* Modified: */ 6806/* m_head: May be set to NULL if MBUF is excessively fragmented. */ 6807/****************************************************************************/ 6808static int 6809bce_tx_encap(struct bce_softc *sc, struct mbuf **m_head) 6810{ 6811 bus_dma_segment_t segs[BCE_MAX_SEGMENTS]; 6812 bus_dmamap_t map; 6813 struct tx_bd *txbd = NULL; 6814 struct mbuf *m0; 6815 u16 prod, chain_prod, mss = 0, vlan_tag = 0, flags = 0; 6816 u32 prod_bseq; 6817 6818#ifdef BCE_DEBUG 6819 u16 debug_prod; 6820#endif 6821 6822 int i, error, nsegs, rc = 0; 6823 6824 DBENTER(BCE_VERBOSE_SEND); 6825 6826 /* Make sure we have room in the TX chain. */ 6827 if (sc->used_tx_bd >= sc->max_tx_bd) 6828 goto bce_tx_encap_exit; 6829 6830 /* Transfer any checksum offload flags to the bd. */ 6831 m0 = *m_head; 6832 if (m0->m_pkthdr.csum_flags) { 6833 if (m0->m_pkthdr.csum_flags & CSUM_TSO) { 6834 m0 = bce_tso_setup(sc, m_head, &flags); 6835 if (m0 == NULL) { 6836 DBRUN(sc->tso_frames_failed++); 6837 goto bce_tx_encap_exit; 6838 } 6839 mss = htole16(m0->m_pkthdr.tso_segsz); 6840 } else { 6841 if (m0->m_pkthdr.csum_flags & CSUM_IP) 6842 flags |= TX_BD_FLAGS_IP_CKSUM; 6843 if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 6844 flags |= TX_BD_FLAGS_TCP_UDP_CKSUM; 6845 } 6846 } 6847 6848 /* Transfer any VLAN tags to the bd. */ 6849 if (m0->m_flags & M_VLANTAG) { 6850 flags |= TX_BD_FLAGS_VLAN_TAG; 6851 vlan_tag = m0->m_pkthdr.ether_vtag; 6852 } 6853 6854 /* Map the mbuf into DMAable memory. */ 6855 prod = sc->tx_prod; 6856 chain_prod = TX_CHAIN_IDX(prod); 6857 map = sc->tx_mbuf_map[chain_prod]; 6858 6859 /* Map the mbuf into our DMA address space. */ 6860 error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag, map, m0, 6861 segs, &nsegs, BUS_DMA_NOWAIT); 6862 6863 /* Check if the DMA mapping was successful */ 6864 if (error == EFBIG) { 6865 sc->mbuf_frag_count++; 6866 6867 /* Try to defrag the mbuf. */ 6868 m0 = m_collapse(*m_head, M_DONTWAIT, BCE_MAX_SEGMENTS); 6869 if (m0 == NULL) { 6870 /* Defrag was unsuccessful */ 6871 m_freem(*m_head); 6872 *m_head = NULL; 6873 sc->mbuf_alloc_failed_count++; 6874 rc = ENOBUFS; 6875 goto bce_tx_encap_exit; 6876 } 6877 6878 /* Defrag was successful, try mapping again */ 6879 *m_head = m0; 6880 error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag, 6881 map, m0, segs, &nsegs, BUS_DMA_NOWAIT); 6882 6883 /* Still getting an error after a defrag. */ 6884 if (error == ENOMEM) { 6885 /* Insufficient DMA buffers available. */ 6886 sc->dma_map_addr_tx_failed_count++; 6887 rc = error; 6888 goto bce_tx_encap_exit; 6889 } else if (error != 0) { 6890 /* Release it and return an error. */ 6891 BCE_PRINTF("%s(%d): Unknown error mapping mbuf into " 6892 "TX chain!\n", __FILE__, __LINE__); 6893 m_freem(m0); 6894 *m_head = NULL; 6895 sc->dma_map_addr_tx_failed_count++; 6896 rc = ENOBUFS; 6897 goto bce_tx_encap_exit; 6898 } 6899 } else if (error == ENOMEM) { 6900 /* Insufficient DMA buffers available. */ 6901 sc->dma_map_addr_tx_failed_count++; 6902 rc = error; 6903 goto bce_tx_encap_exit; 6904 } else if (error != 0) { 6905 m_freem(m0); 6906 *m_head = NULL; 6907 sc->dma_map_addr_tx_failed_count++; 6908 rc = error; 6909 goto bce_tx_encap_exit; 6910 } 6911 6912 /* Make sure there's room in the chain */ 6913 if (nsegs > (sc->max_tx_bd - sc->used_tx_bd)) { 6914 bus_dmamap_unload(sc->tx_mbuf_tag, map); 6915 rc = ENOBUFS; 6916 goto bce_tx_encap_exit; 6917 } 6918 6919 /* prod points to an empty tx_bd at this point. */ 6920 prod_bseq = sc->tx_prod_bseq; 6921 6922#ifdef BCE_DEBUG 6923 debug_prod = chain_prod; 6924#endif 6925 6926 DBPRINT(sc, BCE_INFO_SEND, 6927 "%s(start): prod = 0x%04X, chain_prod = 0x%04X, " 6928 "prod_bseq = 0x%08X\n", 6929 __FUNCTION__, prod, chain_prod, prod_bseq); 6930 6931 /* 6932 * Cycle through each mbuf segment that makes up 6933 * the outgoing frame, gathering the mapping info 6934 * for that segment and creating a tx_bd for 6935 * the mbuf. 6936 */ 6937 for (i = 0; i < nsegs ; i++) { 6938 6939 chain_prod = TX_CHAIN_IDX(prod); 6940 txbd= &sc->tx_bd_chain[TX_PAGE(chain_prod)] 6941 [TX_IDX(chain_prod)]; 6942 6943 txbd->tx_bd_haddr_lo = 6944 htole32(BCE_ADDR_LO(segs[i].ds_addr)); 6945 txbd->tx_bd_haddr_hi = 6946 htole32(BCE_ADDR_HI(segs[i].ds_addr)); 6947 txbd->tx_bd_mss_nbytes = htole32(mss << 16) | 6948 htole16(segs[i].ds_len); 6949 txbd->tx_bd_vlan_tag = htole16(vlan_tag); 6950 txbd->tx_bd_flags = htole16(flags); 6951 prod_bseq += segs[i].ds_len; 6952 if (i == 0) 6953 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_START); 6954 prod = NEXT_TX_BD(prod); 6955 } 6956 6957 /* Set the END flag on the last TX buffer descriptor. */ 6958 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_END); 6959 6960 DBRUNMSG(BCE_EXTREME_SEND, 6961 bce_dump_tx_chain(sc, debug_prod, nsegs)); 6962 6963 /* 6964 * Ensure that the mbuf pointer for this transmission 6965 * is placed at the array index of the last 6966 * descriptor in this chain. This is done 6967 * because a single map is used for all 6968 * segments of the mbuf and we don't want to 6969 * unload the map before all of the segments 6970 * have been freed. 6971 */ 6972 sc->tx_mbuf_ptr[chain_prod] = m0; 6973 sc->used_tx_bd += nsegs; 6974 6975 /* Update some debug statistic counters */ 6976 DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark), 6977 sc->tx_hi_watermark = sc->used_tx_bd); 6978 DBRUNIF((sc->used_tx_bd == sc->max_tx_bd), sc->tx_full_count++); 6979 DBRUNIF(sc->debug_tx_mbuf_alloc++); 6980 6981 DBRUNMSG(BCE_EXTREME_SEND, bce_dump_tx_mbuf_chain(sc, chain_prod, 1)); 6982 6983 /* prod points to the next free tx_bd at this point. */ 6984 sc->tx_prod = prod; 6985 sc->tx_prod_bseq = prod_bseq; 6986 6987 /* Tell the chip about the waiting TX frames. */ 6988 REG_WR16(sc, MB_GET_CID_ADDR(TX_CID) + 6989 BCE_L2MQ_TX_HOST_BIDX, sc->tx_prod); 6990 REG_WR(sc, MB_GET_CID_ADDR(TX_CID) + 6991 BCE_L2MQ_TX_HOST_BSEQ, sc->tx_prod_bseq); 6992 6993bce_tx_encap_exit: 6994 DBEXIT(BCE_VERBOSE_SEND); 6995 return(rc); 6996} 6997 6998 6999/****************************************************************************/ 7000/* Main transmit routine when called from another routine with a lock. */ 7001/* */ 7002/* Returns: */ 7003/* Nothing. */ 7004/****************************************************************************/ 7005static void 7006bce_start_locked(struct ifnet *ifp) 7007{ 7008 struct bce_softc *sc = ifp->if_softc; 7009 struct mbuf *m_head = NULL; 7010 int count = 0; 7011 u16 tx_prod, tx_chain_prod; 7012 7013 DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 7014 7015 BCE_LOCK_ASSERT(sc); 7016 7017 /* prod points to the next free tx_bd. */ 7018 tx_prod = sc->tx_prod; 7019 tx_chain_prod = TX_CHAIN_IDX(tx_prod); 7020 7021 DBPRINT(sc, BCE_INFO_SEND, 7022 "%s(enter): tx_prod = 0x%04X, tx_chain_prod = 0x%04X, " 7023 "tx_prod_bseq = 0x%08X\n", 7024 __FUNCTION__, tx_prod, tx_chain_prod, sc->tx_prod_bseq); 7025 7026 /* If there's no link or the transmit queue is empty then just exit. */ 7027 if (sc->bce_link_up == FALSE) { 7028 DBPRINT(sc, BCE_INFO_SEND, "%s(): No link.\n", 7029 __FUNCTION__); 7030 goto bce_start_locked_exit; 7031 } 7032 7033 if (IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 7034 DBPRINT(sc, BCE_INFO_SEND, "%s(): Transmit queue empty.\n", 7035 __FUNCTION__); 7036 goto bce_start_locked_exit; 7037 } 7038 7039 /* 7040 * Keep adding entries while there is space in the ring. 7041 */ 7042 while (sc->used_tx_bd < sc->max_tx_bd) { 7043 7044 /* Check for any frames to send. */ 7045 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 7046 7047 /* Stop when the transmit queue is empty. */ 7048 if (m_head == NULL) 7049 break; 7050 7051 /* 7052 * Pack the data into the transmit ring. If we 7053 * don't have room, place the mbuf back at the 7054 * head of the queue and set the OACTIVE flag 7055 * to wait for the NIC to drain the chain. 7056 */ 7057 if (bce_tx_encap(sc, &m_head)) { 7058 if (m_head != NULL) 7059 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 7060 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 7061 DBPRINT(sc, BCE_INFO_SEND, 7062 "TX chain is closed for business! Total " 7063 "tx_bd used = %d\n", sc->used_tx_bd); 7064 break; 7065 } 7066 7067 count++; 7068 7069 /* Send a copy of the frame to any BPF listeners. */ 7070 ETHER_BPF_MTAP(ifp, m_head); 7071 } 7072 7073 /* Exit if no packets were dequeued. */ 7074 if (count == 0) { 7075 DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): No packets were " 7076 "dequeued\n", __FUNCTION__); 7077 goto bce_start_locked_exit; 7078 } 7079 7080 DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): Inserted %d frames into " 7081 "send queue.\n", __FUNCTION__, count); 7082 7083 /* Set the tx timeout. */ 7084 sc->watchdog_timer = BCE_TX_TIMEOUT; 7085 7086 DBRUNMSG(BCE_VERBOSE_SEND, bce_dump_ctx(sc, TX_CID)); 7087 DBRUNMSG(BCE_VERBOSE_SEND, bce_dump_mq_regs(sc)); 7088 7089bce_start_locked_exit: 7090 DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 7091 return; 7092} 7093 7094 7095/****************************************************************************/ 7096/* Main transmit routine when called from another routine without a lock. */ 7097/* */ 7098/* Returns: */ 7099/* Nothing. */ 7100/****************************************************************************/ 7101static void 7102bce_start(struct ifnet *ifp) 7103{ 7104 struct bce_softc *sc = ifp->if_softc; 7105 7106 DBENTER(BCE_VERBOSE_SEND); 7107 7108 BCE_LOCK(sc); 7109 bce_start_locked(ifp); 7110 BCE_UNLOCK(sc); 7111 7112 DBEXIT(BCE_VERBOSE_SEND); 7113} 7114 7115 7116/****************************************************************************/ 7117/* Handles any IOCTL calls from the operating system. */ 7118/* */ 7119/* Returns: */ 7120/* 0 for success, positive value for failure. */ 7121/****************************************************************************/ 7122static int 7123bce_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 7124{ 7125 struct bce_softc *sc = ifp->if_softc; 7126 struct ifreq *ifr = (struct ifreq *) data; 7127 struct mii_data *mii; 7128 int mask, error = 0, reinit; 7129 7130 DBENTER(BCE_VERBOSE_MISC); 7131 7132 switch(command) { 7133 7134 /* Set the interface MTU. */ 7135 case SIOCSIFMTU: 7136 /* Check that the MTU setting is supported. */ 7137 if ((ifr->ifr_mtu < BCE_MIN_MTU) || 7138 (ifr->ifr_mtu > BCE_MAX_JUMBO_MTU)) { 7139 error = EINVAL; 7140 break; 7141 } 7142 7143 DBPRINT(sc, BCE_INFO_MISC, 7144 "SIOCSIFMTU: Changing MTU from %d to %d\n", 7145 (int) ifp->if_mtu, (int) ifr->ifr_mtu); 7146 7147 BCE_LOCK(sc); 7148 ifp->if_mtu = ifr->ifr_mtu; 7149 reinit = 0; 7150 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 7151 /* 7152 * Because allocation size is used in RX 7153 * buffer allocation, stop controller if 7154 * it is already running. 7155 */ 7156 bce_stop(sc); 7157 reinit = 1; 7158 } 7159#ifdef BCE_JUMBO_HDRSPLIT 7160 /* No buffer allocation size changes are necessary. */ 7161#else 7162 /* Recalculate our buffer allocation sizes. */ 7163 if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + 7164 ETHER_CRC_LEN) > MCLBYTES) { 7165 sc->rx_bd_mbuf_alloc_size = MJUM9BYTES; 7166 sc->rx_bd_mbuf_align_pad = 7167 roundup2(MJUM9BYTES, 16) - MJUM9BYTES; 7168 sc->rx_bd_mbuf_data_len = 7169 sc->rx_bd_mbuf_alloc_size - 7170 sc->rx_bd_mbuf_align_pad; 7171 } else { 7172 sc->rx_bd_mbuf_alloc_size = MCLBYTES; 7173 sc->rx_bd_mbuf_align_pad = 7174 roundup2(MCLBYTES, 16) - MCLBYTES; 7175 sc->rx_bd_mbuf_data_len = 7176 sc->rx_bd_mbuf_alloc_size - 7177 sc->rx_bd_mbuf_align_pad; 7178 } 7179#endif 7180 7181 if (reinit != 0) 7182 bce_init_locked(sc); 7183 BCE_UNLOCK(sc); 7184 break; 7185 7186 /* Set interface flags. */ 7187 case SIOCSIFFLAGS: 7188 DBPRINT(sc, BCE_VERBOSE_SPECIAL, "Received SIOCSIFFLAGS\n"); 7189 7190 BCE_LOCK(sc); 7191 7192 /* Check if the interface is up. */ 7193 if (ifp->if_flags & IFF_UP) { 7194 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 7195 /* Change promiscuous/multicast flags as necessary. */ 7196 bce_set_rx_mode(sc); 7197 } else { 7198 /* Start the HW */ 7199 bce_init_locked(sc); 7200 } 7201 } else { 7202 /* The interface is down, check if driver is running. */ 7203 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 7204 bce_stop(sc); 7205 7206 /* If MFW is running, restart the controller a bit. */ 7207 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 7208 bce_reset(sc, BCE_DRV_MSG_CODE_RESET); 7209 bce_chipinit(sc); 7210 bce_mgmt_init_locked(sc); 7211 } 7212 } 7213 } 7214 7215 BCE_UNLOCK(sc); 7216 break; 7217 7218 /* Add/Delete multicast address */ 7219 case SIOCADDMULTI: 7220 case SIOCDELMULTI: 7221 DBPRINT(sc, BCE_VERBOSE_MISC, 7222 "Received SIOCADDMULTI/SIOCDELMULTI\n"); 7223 7224 BCE_LOCK(sc); 7225 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 7226 bce_set_rx_mode(sc); 7227 BCE_UNLOCK(sc); 7228 7229 break; 7230 7231 /* Set/Get Interface media */ 7232 case SIOCSIFMEDIA: 7233 case SIOCGIFMEDIA: 7234 DBPRINT(sc, BCE_VERBOSE_MISC, 7235 "Received SIOCSIFMEDIA/SIOCGIFMEDIA\n"); 7236 7237 mii = device_get_softc(sc->bce_miibus); 7238 error = ifmedia_ioctl(ifp, ifr, 7239 &mii->mii_media, command); 7240 break; 7241 7242 /* Set interface capability */ 7243 case SIOCSIFCAP: 7244 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 7245 DBPRINT(sc, BCE_INFO_MISC, 7246 "Received SIOCSIFCAP = 0x%08X\n", (u32) mask); 7247 7248 /* Toggle the TX checksum capabilities enable flag. */ 7249 if (mask & IFCAP_TXCSUM && 7250 ifp->if_capabilities & IFCAP_TXCSUM) { 7251 ifp->if_capenable ^= IFCAP_TXCSUM; 7252 if (IFCAP_TXCSUM & ifp->if_capenable) 7253 ifp->if_hwassist |= BCE_IF_HWASSIST; 7254 else 7255 ifp->if_hwassist &= ~BCE_IF_HWASSIST; 7256 } 7257 7258 /* Toggle the RX checksum capabilities enable flag. */ 7259 if (mask & IFCAP_RXCSUM && 7260 ifp->if_capabilities & IFCAP_RXCSUM) 7261 ifp->if_capenable ^= IFCAP_RXCSUM; 7262 7263 /* Toggle the TSO capabilities enable flag. */ 7264 if (bce_tso_enable && (mask & IFCAP_TSO4) && 7265 ifp->if_capabilities & IFCAP_TSO4) { 7266 ifp->if_capenable ^= IFCAP_TSO4; 7267 if (IFCAP_TSO4 & ifp->if_capenable) 7268 ifp->if_hwassist |= CSUM_TSO; 7269 else 7270 ifp->if_hwassist &= ~CSUM_TSO; 7271 } 7272 7273 if (mask & IFCAP_VLAN_HWCSUM && 7274 ifp->if_capabilities & IFCAP_VLAN_HWCSUM) 7275 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 7276 7277 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 7278 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 7279 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 7280 /* 7281 * Don't actually disable VLAN tag stripping as 7282 * management firmware (ASF/IPMI/UMP) requires the 7283 * feature. If VLAN tag stripping is disabled driver 7284 * will manually reconstruct the VLAN frame by 7285 * appending stripped VLAN tag. 7286 */ 7287 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 7288 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING)) { 7289 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 7290 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 7291 == 0) 7292 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 7293 } 7294 VLAN_CAPABILITIES(ifp); 7295 break; 7296 default: 7297 /* We don't know how to handle the IOCTL, pass it on. */ 7298 error = ether_ioctl(ifp, command, data); 7299 break; 7300 } 7301 7302 DBEXIT(BCE_VERBOSE_MISC); 7303 return(error); 7304} 7305 7306 7307/****************************************************************************/ 7308/* Transmit timeout handler. */ 7309/* */ 7310/* Returns: */ 7311/* Nothing. */ 7312/****************************************************************************/ 7313static void 7314bce_watchdog(struct bce_softc *sc) 7315{ 7316 DBENTER(BCE_EXTREME_SEND); 7317 7318 BCE_LOCK_ASSERT(sc); 7319 7320 /* If the watchdog timer hasn't expired then just exit. */ 7321 if (sc->watchdog_timer == 0 || --sc->watchdog_timer) 7322 goto bce_watchdog_exit; 7323 7324 /* If pause frames are active then don't reset the hardware. */ 7325 /* ToDo: Should we reset the timer here? */ 7326 if (REG_RD(sc, BCE_EMAC_TX_STATUS) & BCE_EMAC_TX_STATUS_XOFFED) 7327 goto bce_watchdog_exit; 7328 7329 BCE_PRINTF("%s(%d): Watchdog timeout occurred, resetting!\n", 7330 __FILE__, __LINE__); 7331 7332 DBRUNMSG(BCE_INFO, 7333 bce_dump_driver_state(sc); 7334 bce_dump_status_block(sc); 7335 bce_dump_stats_block(sc); 7336 bce_dump_ftqs(sc); 7337 bce_dump_txp_state(sc, 0); 7338 bce_dump_rxp_state(sc, 0); 7339 bce_dump_tpat_state(sc, 0); 7340 bce_dump_cp_state(sc, 0); 7341 bce_dump_com_state(sc, 0)); 7342 7343 DBRUN(bce_breakpoint(sc)); 7344 7345 sc->bce_ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 7346 7347 bce_init_locked(sc); 7348 sc->bce_ifp->if_oerrors++; 7349 7350bce_watchdog_exit: 7351 DBEXIT(BCE_EXTREME_SEND); 7352} 7353 7354 7355/* 7356 * Interrupt handler. 7357 */ 7358/****************************************************************************/ 7359/* Main interrupt entry point. Verifies that the controller generated the */ 7360/* interrupt and then calls a separate routine for handle the various */ 7361/* interrupt causes (PHY, TX, RX). */ 7362/* */ 7363/* Returns: */ 7364/* 0 for success, positive value for failure. */ 7365/****************************************************************************/ 7366static void 7367bce_intr(void *xsc) 7368{ 7369 struct bce_softc *sc; 7370 struct ifnet *ifp; 7371 u32 status_attn_bits; 7372 u16 hw_rx_cons, hw_tx_cons; 7373 7374 sc = xsc; 7375 ifp = sc->bce_ifp; 7376 7377 DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 7378 DBRUNMSG(BCE_VERBOSE_INTR, bce_dump_status_block(sc)); 7379 DBRUNMSG(BCE_VERBOSE_INTR, bce_dump_stats_block(sc)); 7380 7381 BCE_LOCK(sc); 7382 7383 DBRUN(sc->interrupts_generated++); 7384 7385 /* Synchnorize before we read from interface's status block */ 7386 bus_dmamap_sync(sc->status_tag, sc->status_map, 7387 BUS_DMASYNC_POSTREAD); 7388 7389 /* 7390 * If the hardware status block index 7391 * matches the last value read by the 7392 * driver and we haven't asserted our 7393 * interrupt then there's nothing to do. 7394 */ 7395 if ((sc->status_block->status_idx == sc->last_status_idx) && 7396 (REG_RD(sc, BCE_PCICFG_MISC_STATUS) & 7397 BCE_PCICFG_MISC_STATUS_INTA_VALUE)) { 7398 DBPRINT(sc, BCE_VERBOSE_INTR, "%s(): Spurious interrupt.\n", 7399 __FUNCTION__); 7400 goto bce_intr_exit; 7401 } 7402 7403 /* Ack the interrupt and stop others from occuring. */ 7404 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 7405 BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM | 7406 BCE_PCICFG_INT_ACK_CMD_MASK_INT); 7407 7408 /* Check if the hardware has finished any work. */ 7409 hw_rx_cons = bce_get_hw_rx_cons(sc); 7410 hw_tx_cons = bce_get_hw_tx_cons(sc); 7411 7412 /* Keep processing data as long as there is work to do. */ 7413 for (;;) { 7414 7415 status_attn_bits = sc->status_block->status_attn_bits; 7416 7417 DBRUNIF(DB_RANDOMTRUE(unexpected_attention_sim_control), 7418 BCE_PRINTF("Simulating unexpected status attention " 7419 "bit set."); 7420 sc->unexpected_attention_sim_count++; 7421 status_attn_bits = status_attn_bits | 7422 STATUS_ATTN_BITS_PARITY_ERROR); 7423 7424 /* Was it a link change interrupt? */ 7425 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != 7426 (sc->status_block->status_attn_bits_ack & 7427 STATUS_ATTN_BITS_LINK_STATE)) { 7428 bce_phy_intr(sc); 7429 7430 /* Clear transient updates during link state change. */ 7431 REG_WR(sc, BCE_HC_COMMAND, sc->hc_command | 7432 BCE_HC_COMMAND_COAL_NOW_WO_INT); 7433 REG_RD(sc, BCE_HC_COMMAND); 7434 } 7435 7436 /* If any other attention is asserted, the chip is toast. */ 7437 if (((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) != 7438 (sc->status_block->status_attn_bits_ack & 7439 ~STATUS_ATTN_BITS_LINK_STATE))) { 7440 7441 sc->unexpected_attention_count++; 7442 7443 BCE_PRINTF("%s(%d): Fatal attention detected: " 7444 "0x%08X\n", __FILE__, __LINE__, 7445 sc->status_block->status_attn_bits); 7446 7447 DBRUNMSG(BCE_FATAL, 7448 if (unexpected_attention_sim_control == 0) 7449 bce_breakpoint(sc)); 7450 7451 bce_init_locked(sc); 7452 goto bce_intr_exit; 7453 } 7454 7455 /* Check for any completed RX frames. */ 7456 if (hw_rx_cons != sc->hw_rx_cons) 7457 bce_rx_intr(sc); 7458 7459 /* Check for any completed TX frames. */ 7460 if (hw_tx_cons != sc->hw_tx_cons) 7461 bce_tx_intr(sc); 7462 7463 /* Save status block index value for the next interrupt. */ 7464 sc->last_status_idx = sc->status_block->status_idx; 7465 7466 /* 7467 * Prevent speculative reads from getting 7468 * ahead of the status block. 7469 */ 7470 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 7471 BUS_SPACE_BARRIER_READ); 7472 7473 /* 7474 * If there's no work left then exit the 7475 * interrupt service routine. 7476 */ 7477 hw_rx_cons = bce_get_hw_rx_cons(sc); 7478 hw_tx_cons = bce_get_hw_tx_cons(sc); 7479 7480 if ((hw_rx_cons == sc->hw_rx_cons) && 7481 (hw_tx_cons == sc->hw_tx_cons)) 7482 break; 7483 7484 } 7485 7486 bus_dmamap_sync(sc->status_tag, sc->status_map, 7487 BUS_DMASYNC_PREREAD); 7488 7489 /* Re-enable interrupts. */ 7490 bce_enable_intr(sc, 0); 7491 7492 /* Handle any frames that arrived while handling the interrupt. */ 7493 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 7494 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 7495 bce_start_locked(ifp); 7496 7497bce_intr_exit: 7498 BCE_UNLOCK(sc); 7499 7500 DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 7501} 7502 7503 7504/****************************************************************************/ 7505/* Programs the various packet receive modes (broadcast and multicast). */ 7506/* */ 7507/* Returns: */ 7508/* Nothing. */ 7509/****************************************************************************/ 7510static void 7511bce_set_rx_mode(struct bce_softc *sc) 7512{ 7513 struct ifnet *ifp; 7514 struct ifmultiaddr *ifma; 7515 u32 hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 7516 u32 rx_mode, sort_mode; 7517 int h, i; 7518 7519 DBENTER(BCE_VERBOSE_MISC); 7520 7521 BCE_LOCK_ASSERT(sc); 7522 7523 ifp = sc->bce_ifp; 7524 7525 /* Initialize receive mode default settings. */ 7526 rx_mode = sc->rx_mode & ~(BCE_EMAC_RX_MODE_PROMISCUOUS | 7527 BCE_EMAC_RX_MODE_KEEP_VLAN_TAG); 7528 sort_mode = 1 | BCE_RPM_SORT_USER0_BC_EN; 7529 7530 /* 7531 * ASF/IPMI/UMP firmware requires that VLAN tag stripping 7532 * be enbled. 7533 */ 7534 if (!(BCE_IF_CAPABILITIES & IFCAP_VLAN_HWTAGGING) && 7535 (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG))) 7536 rx_mode |= BCE_EMAC_RX_MODE_KEEP_VLAN_TAG; 7537 7538 /* 7539 * Check for promiscuous, all multicast, or selected 7540 * multicast address filtering. 7541 */ 7542 if (ifp->if_flags & IFF_PROMISC) { 7543 DBPRINT(sc, BCE_INFO_MISC, "Enabling promiscuous mode.\n"); 7544 7545 /* Enable promiscuous mode. */ 7546 rx_mode |= BCE_EMAC_RX_MODE_PROMISCUOUS; 7547 sort_mode |= BCE_RPM_SORT_USER0_PROM_EN; 7548 } else if (ifp->if_flags & IFF_ALLMULTI) { 7549 DBPRINT(sc, BCE_INFO_MISC, "Enabling all multicast mode.\n"); 7550 7551 /* Enable all multicast addresses. */ 7552 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) { 7553 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), 0xffffffff); 7554 } 7555 sort_mode |= BCE_RPM_SORT_USER0_MC_EN; 7556 } else { 7557 /* Accept one or more multicast(s). */ 7558 DBPRINT(sc, BCE_INFO_MISC, "Enabling selective multicast mode.\n"); 7559 7560 if_maddr_rlock(ifp); 7561 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 7562 if (ifma->ifma_addr->sa_family != AF_LINK) 7563 continue; 7564 h = ether_crc32_le(LLADDR((struct sockaddr_dl *) 7565 ifma->ifma_addr), ETHER_ADDR_LEN) & 0xFF; 7566 hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F); 7567 } 7568 if_maddr_runlock(ifp); 7569 7570 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) 7571 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), hashes[i]); 7572 7573 sort_mode |= BCE_RPM_SORT_USER0_MC_HSH_EN; 7574 } 7575 7576 /* Only make changes if the recive mode has actually changed. */ 7577 if (rx_mode != sc->rx_mode) { 7578 DBPRINT(sc, BCE_VERBOSE_MISC, "Enabling new receive mode: " 7579 "0x%08X\n", rx_mode); 7580 7581 sc->rx_mode = rx_mode; 7582 REG_WR(sc, BCE_EMAC_RX_MODE, rx_mode); 7583 } 7584 7585 /* Disable and clear the exisitng sort before enabling a new sort. */ 7586 REG_WR(sc, BCE_RPM_SORT_USER0, 0x0); 7587 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode); 7588 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode | BCE_RPM_SORT_USER0_ENA); 7589 7590 DBEXIT(BCE_VERBOSE_MISC); 7591} 7592 7593 7594/****************************************************************************/ 7595/* Called periodically to updates statistics from the controllers */ 7596/* statistics block. */ 7597/* */ 7598/* Returns: */ 7599/* Nothing. */ 7600/****************************************************************************/ 7601static void 7602bce_stats_update(struct bce_softc *sc) 7603{ 7604 struct ifnet *ifp; 7605 struct statistics_block *stats; 7606 7607 DBENTER(BCE_EXTREME_MISC); 7608 7609 ifp = sc->bce_ifp; 7610 7611 stats = (struct statistics_block *) sc->stats_block; 7612 7613 /* 7614 * Certain controllers don't report 7615 * carrier sense errors correctly. 7616 * See errata E11_5708CA0_1165. 7617 */ 7618 if (!(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) && 7619 !(BCE_CHIP_ID(sc) == BCE_CHIP_ID_5708_A0)) 7620 ifp->if_oerrors += 7621 (u_long) stats->stat_Dot3StatsCarrierSenseErrors; 7622 7623 /* 7624 * Update the sysctl statistics from the 7625 * hardware statistics. 7626 */ 7627 sc->stat_IfHCInOctets = 7628 ((u64) stats->stat_IfHCInOctets_hi << 32) + 7629 (u64) stats->stat_IfHCInOctets_lo; 7630 7631 sc->stat_IfHCInBadOctets = 7632 ((u64) stats->stat_IfHCInBadOctets_hi << 32) + 7633 (u64) stats->stat_IfHCInBadOctets_lo; 7634 7635 sc->stat_IfHCOutOctets = 7636 ((u64) stats->stat_IfHCOutOctets_hi << 32) + 7637 (u64) stats->stat_IfHCOutOctets_lo; 7638 7639 sc->stat_IfHCOutBadOctets = 7640 ((u64) stats->stat_IfHCOutBadOctets_hi << 32) + 7641 (u64) stats->stat_IfHCOutBadOctets_lo; 7642 7643 sc->stat_IfHCInUcastPkts = 7644 ((u64) stats->stat_IfHCInUcastPkts_hi << 32) + 7645 (u64) stats->stat_IfHCInUcastPkts_lo; 7646 7647 sc->stat_IfHCInMulticastPkts = 7648 ((u64) stats->stat_IfHCInMulticastPkts_hi << 32) + 7649 (u64) stats->stat_IfHCInMulticastPkts_lo; 7650 7651 sc->stat_IfHCInBroadcastPkts = 7652 ((u64) stats->stat_IfHCInBroadcastPkts_hi << 32) + 7653 (u64) stats->stat_IfHCInBroadcastPkts_lo; 7654 7655 sc->stat_IfHCOutUcastPkts = 7656 ((u64) stats->stat_IfHCOutUcastPkts_hi << 32) + 7657 (u64) stats->stat_IfHCOutUcastPkts_lo; 7658 7659 sc->stat_IfHCOutMulticastPkts = 7660 ((u64) stats->stat_IfHCOutMulticastPkts_hi << 32) + 7661 (u64) stats->stat_IfHCOutMulticastPkts_lo; 7662 7663 sc->stat_IfHCOutBroadcastPkts = 7664 ((u64) stats->stat_IfHCOutBroadcastPkts_hi << 32) + 7665 (u64) stats->stat_IfHCOutBroadcastPkts_lo; 7666 7667 /* ToDo: Preserve counters beyond 32 bits? */ 7668 /* ToDo: Read the statistics from auto-clear regs? */ 7669 7670 sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors = 7671 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors; 7672 7673 sc->stat_Dot3StatsCarrierSenseErrors = 7674 stats->stat_Dot3StatsCarrierSenseErrors; 7675 7676 sc->stat_Dot3StatsFCSErrors = 7677 stats->stat_Dot3StatsFCSErrors; 7678 7679 sc->stat_Dot3StatsAlignmentErrors = 7680 stats->stat_Dot3StatsAlignmentErrors; 7681 7682 sc->stat_Dot3StatsSingleCollisionFrames = 7683 stats->stat_Dot3StatsSingleCollisionFrames; 7684 7685 sc->stat_Dot3StatsMultipleCollisionFrames = 7686 stats->stat_Dot3StatsMultipleCollisionFrames; 7687 7688 sc->stat_Dot3StatsDeferredTransmissions = 7689 stats->stat_Dot3StatsDeferredTransmissions; 7690 7691 sc->stat_Dot3StatsExcessiveCollisions = 7692 stats->stat_Dot3StatsExcessiveCollisions; 7693 7694 sc->stat_Dot3StatsLateCollisions = 7695 stats->stat_Dot3StatsLateCollisions; 7696 7697 sc->stat_EtherStatsCollisions = 7698 stats->stat_EtherStatsCollisions; 7699 7700 sc->stat_EtherStatsFragments = 7701 stats->stat_EtherStatsFragments; 7702 7703 sc->stat_EtherStatsJabbers = 7704 stats->stat_EtherStatsJabbers; 7705 7706 sc->stat_EtherStatsUndersizePkts = 7707 stats->stat_EtherStatsUndersizePkts; 7708 7709 sc->stat_EtherStatsOversizePkts = 7710 stats->stat_EtherStatsOversizePkts; 7711 7712 sc->stat_EtherStatsPktsRx64Octets = 7713 stats->stat_EtherStatsPktsRx64Octets; 7714 7715 sc->stat_EtherStatsPktsRx65Octetsto127Octets = 7716 stats->stat_EtherStatsPktsRx65Octetsto127Octets; 7717 7718 sc->stat_EtherStatsPktsRx128Octetsto255Octets = 7719 stats->stat_EtherStatsPktsRx128Octetsto255Octets; 7720 7721 sc->stat_EtherStatsPktsRx256Octetsto511Octets = 7722 stats->stat_EtherStatsPktsRx256Octetsto511Octets; 7723 7724 sc->stat_EtherStatsPktsRx512Octetsto1023Octets = 7725 stats->stat_EtherStatsPktsRx512Octetsto1023Octets; 7726 7727 sc->stat_EtherStatsPktsRx1024Octetsto1522Octets = 7728 stats->stat_EtherStatsPktsRx1024Octetsto1522Octets; 7729 7730 sc->stat_EtherStatsPktsRx1523Octetsto9022Octets = 7731 stats->stat_EtherStatsPktsRx1523Octetsto9022Octets; 7732 7733 sc->stat_EtherStatsPktsTx64Octets = 7734 stats->stat_EtherStatsPktsTx64Octets; 7735 7736 sc->stat_EtherStatsPktsTx65Octetsto127Octets = 7737 stats->stat_EtherStatsPktsTx65Octetsto127Octets; 7738 7739 sc->stat_EtherStatsPktsTx128Octetsto255Octets = 7740 stats->stat_EtherStatsPktsTx128Octetsto255Octets; 7741 7742 sc->stat_EtherStatsPktsTx256Octetsto511Octets = 7743 stats->stat_EtherStatsPktsTx256Octetsto511Octets; 7744 7745 sc->stat_EtherStatsPktsTx512Octetsto1023Octets = 7746 stats->stat_EtherStatsPktsTx512Octetsto1023Octets; 7747 7748 sc->stat_EtherStatsPktsTx1024Octetsto1522Octets = 7749 stats->stat_EtherStatsPktsTx1024Octetsto1522Octets; 7750 7751 sc->stat_EtherStatsPktsTx1523Octetsto9022Octets = 7752 stats->stat_EtherStatsPktsTx1523Octetsto9022Octets; 7753 7754 sc->stat_XonPauseFramesReceived = 7755 stats->stat_XonPauseFramesReceived; 7756 7757 sc->stat_XoffPauseFramesReceived = 7758 stats->stat_XoffPauseFramesReceived; 7759 7760 sc->stat_OutXonSent = 7761 stats->stat_OutXonSent; 7762 7763 sc->stat_OutXoffSent = 7764 stats->stat_OutXoffSent; 7765 7766 sc->stat_FlowControlDone = 7767 stats->stat_FlowControlDone; 7768 7769 sc->stat_MacControlFramesReceived = 7770 stats->stat_MacControlFramesReceived; 7771 7772 sc->stat_XoffStateEntered = 7773 stats->stat_XoffStateEntered; 7774 7775 sc->stat_IfInFramesL2FilterDiscards = 7776 stats->stat_IfInFramesL2FilterDiscards; 7777 7778 sc->stat_IfInRuleCheckerDiscards = 7779 stats->stat_IfInRuleCheckerDiscards; 7780 7781 sc->stat_IfInFTQDiscards = 7782 stats->stat_IfInFTQDiscards; 7783 7784 sc->stat_IfInMBUFDiscards = 7785 stats->stat_IfInMBUFDiscards; 7786 7787 sc->stat_IfInRuleCheckerP4Hit = 7788 stats->stat_IfInRuleCheckerP4Hit; 7789 7790 sc->stat_CatchupInRuleCheckerDiscards = 7791 stats->stat_CatchupInRuleCheckerDiscards; 7792 7793 sc->stat_CatchupInFTQDiscards = 7794 stats->stat_CatchupInFTQDiscards; 7795 7796 sc->stat_CatchupInMBUFDiscards = 7797 stats->stat_CatchupInMBUFDiscards; 7798 7799 sc->stat_CatchupInRuleCheckerP4Hit = 7800 stats->stat_CatchupInRuleCheckerP4Hit; 7801 7802 sc->com_no_buffers = REG_RD_IND(sc, 0x120084); 7803 7804 /* 7805 * Update the interface statistics from the 7806 * hardware statistics. 7807 */ 7808 ifp->if_collisions = 7809 (u_long) sc->stat_EtherStatsCollisions; 7810 7811 /* ToDo: This method loses soft errors. */ 7812 ifp->if_ierrors = 7813 (u_long) sc->stat_EtherStatsUndersizePkts + 7814 (u_long) sc->stat_EtherStatsOversizePkts + 7815 (u_long) sc->stat_IfInMBUFDiscards + 7816 (u_long) sc->stat_Dot3StatsAlignmentErrors + 7817 (u_long) sc->stat_Dot3StatsFCSErrors + 7818 (u_long) sc->stat_IfInRuleCheckerDiscards + 7819 (u_long) sc->stat_IfInFTQDiscards + 7820 (u_long) sc->com_no_buffers; 7821 7822 /* ToDo: This method loses soft errors. */ 7823 ifp->if_oerrors = 7824 (u_long) sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors + 7825 (u_long) sc->stat_Dot3StatsExcessiveCollisions + 7826 (u_long) sc->stat_Dot3StatsLateCollisions; 7827 7828 /* ToDo: Add additional statistics? */ 7829 7830 DBEXIT(BCE_EXTREME_MISC); 7831} 7832 7833 7834/****************************************************************************/ 7835/* Periodic function to notify the bootcode that the driver is still */ 7836/* present. */ 7837/* */ 7838/* Returns: */ 7839/* Nothing. */ 7840/****************************************************************************/ 7841static void 7842bce_pulse(void *xsc) 7843{ 7844 struct bce_softc *sc = xsc; 7845 u32 msg; 7846 7847 DBENTER(BCE_EXTREME_MISC); 7848 7849 BCE_LOCK_ASSERT(sc); 7850 7851 /* Tell the firmware that the driver is still running. */ 7852 msg = (u32) ++sc->bce_fw_drv_pulse_wr_seq; 7853 bce_shmem_wr(sc, BCE_DRV_PULSE_MB, msg); 7854 7855 /* Update the bootcode condition. */ 7856 sc->bc_state = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); 7857 7858 /* Report whether the bootcode still knows the driver is running. */ 7859 if (bootverbose) { 7860 if (sc->bce_drv_cardiac_arrest == FALSE) { 7861 if (!(sc->bc_state & BCE_CONDITION_DRV_PRESENT)) { 7862 sc->bce_drv_cardiac_arrest = TRUE; 7863 BCE_PRINTF("%s(): Warning: bootcode " 7864 "thinks driver is absent! " 7865 "(bc_state = 0x%08X)\n", 7866 __FUNCTION__, sc->bc_state); 7867 } 7868 } else { 7869 /* 7870 * Not supported by all bootcode versions. 7871 * (v5.0.11+ and v5.2.1+) Older bootcode 7872 * will require the driver to reset the 7873 * controller to clear this condition. 7874 */ 7875 if (sc->bc_state & BCE_CONDITION_DRV_PRESENT) { 7876 sc->bce_drv_cardiac_arrest = FALSE; 7877 BCE_PRINTF("%s(): Bootcode found the " 7878 "driver pulse! (bc_state = 0x%08X)\n", 7879 __FUNCTION__, sc->bc_state); 7880 } 7881 } 7882 } 7883 7884 7885 /* Schedule the next pulse. */ 7886 callout_reset(&sc->bce_pulse_callout, hz, bce_pulse, sc); 7887 7888 DBEXIT(BCE_EXTREME_MISC); 7889} 7890 7891 7892/****************************************************************************/ 7893/* Periodic function to perform maintenance tasks. */ 7894/* */ 7895/* Returns: */ 7896/* Nothing. */ 7897/****************************************************************************/ 7898static void 7899bce_tick(void *xsc) 7900{ 7901 struct bce_softc *sc = xsc; 7902 struct mii_data *mii; 7903 struct ifnet *ifp; 7904 7905 ifp = sc->bce_ifp; 7906 7907 DBENTER(BCE_EXTREME_MISC); 7908 7909 BCE_LOCK_ASSERT(sc); 7910 7911 /* Schedule the next tick. */ 7912 callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc); 7913 7914 /* Update the statistics from the hardware statistics block. */ 7915 bce_stats_update(sc); 7916 7917 /* Top off the receive and page chains. */ 7918#ifdef BCE_JUMBO_HDRSPLIT 7919 bce_fill_pg_chain(sc); 7920#endif 7921 bce_fill_rx_chain(sc); 7922 7923 /* Check that chip hasn't hung. */ 7924 bce_watchdog(sc); 7925 7926 /* If link is up already up then we're done. */ 7927 if (sc->bce_link_up == TRUE) 7928 goto bce_tick_exit; 7929 7930 /* Link is down. Check what the PHY's doing. */ 7931 mii = device_get_softc(sc->bce_miibus); 7932 mii_tick(mii); 7933 7934 /* Check if the link has come up. */ 7935 if ((mii->mii_media_status & IFM_ACTIVE) && 7936 (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)) { 7937 DBPRINT(sc, BCE_VERBOSE_MISC, 7938 "%s(): Link up!\n", __FUNCTION__); 7939 sc->bce_link_up = TRUE; 7940 if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 7941 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX || 7942 IFM_SUBTYPE(mii->mii_media_active) == IFM_2500_SX) && 7943 bootverbose) 7944 BCE_PRINTF("Gigabit link up!\n"); 7945 7946 /* Now that link is up, handle any outstanding TX traffic. */ 7947 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 7948 DBPRINT(sc, BCE_VERBOSE_MISC, "%s(): Found " 7949 "pending TX traffic.\n", __FUNCTION__); 7950 bce_start_locked(ifp); 7951 } 7952 } 7953 7954bce_tick_exit: 7955 DBEXIT(BCE_EXTREME_MISC); 7956 return; 7957} 7958 7959 7960#ifdef BCE_DEBUG 7961/****************************************************************************/ 7962/* Allows the driver state to be dumped through the sysctl interface. */ 7963/* */ 7964/* Returns: */ 7965/* 0 for success, positive value for failure. */ 7966/****************************************************************************/ 7967static int 7968bce_sysctl_driver_state(SYSCTL_HANDLER_ARGS) 7969{ 7970 int error; 7971 int result; 7972 struct bce_softc *sc; 7973 7974 result = -1; 7975 error = sysctl_handle_int(oidp, &result, 0, req); 7976 7977 if (error || !req->newptr) 7978 return (error); 7979 7980 if (result == 1) { 7981 sc = (struct bce_softc *)arg1; 7982 bce_dump_driver_state(sc); 7983 } 7984 7985 return error; 7986} 7987 7988 7989/****************************************************************************/ 7990/* Allows the hardware state to be dumped through the sysctl interface. */ 7991/* */ 7992/* Returns: */ 7993/* 0 for success, positive value for failure. */ 7994/****************************************************************************/ 7995static int 7996bce_sysctl_hw_state(SYSCTL_HANDLER_ARGS) 7997{ 7998 int error; 7999 int result; 8000 struct bce_softc *sc; 8001 8002 result = -1; 8003 error = sysctl_handle_int(oidp, &result, 0, req); 8004 8005 if (error || !req->newptr) 8006 return (error); 8007 8008 if (result == 1) { 8009 sc = (struct bce_softc *)arg1; 8010 bce_dump_hw_state(sc); 8011 } 8012 8013 return error; 8014} 8015 8016 8017/****************************************************************************/ 8018/* Allows the status block to be dumped through the sysctl interface. */ 8019/* */ 8020/* Returns: */ 8021/* 0 for success, positive value for failure. */ 8022/****************************************************************************/ 8023static int 8024bce_sysctl_status_block(SYSCTL_HANDLER_ARGS) 8025{ 8026 int error; 8027 int result; 8028 struct bce_softc *sc; 8029 8030 result = -1; 8031 error = sysctl_handle_int(oidp, &result, 0, req); 8032 8033 if (error || !req->newptr) 8034 return (error); 8035 8036 if (result == 1) { 8037 sc = (struct bce_softc *)arg1; 8038 bce_dump_status_block(sc); 8039 } 8040 8041 return error; 8042} 8043 8044 8045/****************************************************************************/ 8046/* Allows the stats block to be dumped through the sysctl interface. */ 8047/* */ 8048/* Returns: */ 8049/* 0 for success, positive value for failure. */ 8050/****************************************************************************/ 8051static int 8052bce_sysctl_stats_block(SYSCTL_HANDLER_ARGS) 8053{ 8054 int error; 8055 int result; 8056 struct bce_softc *sc; 8057 8058 result = -1; 8059 error = sysctl_handle_int(oidp, &result, 0, req); 8060 8061 if (error || !req->newptr) 8062 return (error); 8063 8064 if (result == 1) { 8065 sc = (struct bce_softc *)arg1; 8066 bce_dump_stats_block(sc); 8067 } 8068 8069 return error; 8070} 8071 8072 8073/****************************************************************************/ 8074/* Allows the stat counters to be cleared without unloading/reloading the */ 8075/* driver. */ 8076/* */ 8077/* Returns: */ 8078/* 0 for success, positive value for failure. */ 8079/****************************************************************************/ 8080static int 8081bce_sysctl_stats_clear(SYSCTL_HANDLER_ARGS) 8082{ 8083 int error; 8084 int result; 8085 struct bce_softc *sc; 8086 8087 result = -1; 8088 error = sysctl_handle_int(oidp, &result, 0, req); 8089 8090 if (error || !req->newptr) 8091 return (error); 8092 8093 if (result == 1) { 8094 sc = (struct bce_softc *)arg1; 8095 8096 /* Clear the internal H/W statistics counters. */ 8097 REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW); 8098 8099 /* Reset the driver maintained statistics. */ 8100 sc->interrupts_rx = 8101 sc->interrupts_tx = 0; 8102 sc->tso_frames_requested = 8103 sc->tso_frames_completed = 8104 sc->tso_frames_failed = 0; 8105 sc->rx_empty_count = 8106 sc->tx_full_count = 0; 8107 sc->rx_low_watermark = USABLE_RX_BD; 8108 sc->tx_hi_watermark = 0; 8109 sc->l2fhdr_error_count = 8110 sc->l2fhdr_error_sim_count = 0; 8111 sc->mbuf_alloc_failed_count = 8112 sc->mbuf_alloc_failed_sim_count = 0; 8113 sc->dma_map_addr_rx_failed_count = 8114 sc->dma_map_addr_tx_failed_count = 0; 8115 sc->mbuf_frag_count = 0; 8116 sc->csum_offload_tcp_udp = 8117 sc->csum_offload_ip = 0; 8118 sc->vlan_tagged_frames_rcvd = 8119 sc->vlan_tagged_frames_stripped = 0; 8120 8121 /* Clear firmware maintained statistics. */ 8122 REG_WR_IND(sc, 0x120084, 0); 8123 } 8124 8125 return error; 8126} 8127 8128 8129/****************************************************************************/ 8130/* Allows the bootcode state to be dumped through the sysctl interface. */ 8131/* */ 8132/* Returns: */ 8133/* 0 for success, positive value for failure. */ 8134/****************************************************************************/ 8135static int 8136bce_sysctl_bc_state(SYSCTL_HANDLER_ARGS) 8137{ 8138 int error; 8139 int result; 8140 struct bce_softc *sc; 8141 8142 result = -1; 8143 error = sysctl_handle_int(oidp, &result, 0, req); 8144 8145 if (error || !req->newptr) 8146 return (error); 8147 8148 if (result == 1) { 8149 sc = (struct bce_softc *)arg1; 8150 bce_dump_bc_state(sc); 8151 } 8152 8153 return error; 8154} 8155 8156 8157/****************************************************************************/ 8158/* Provides a sysctl interface to allow dumping the RX BD chain. */ 8159/* */ 8160/* Returns: */ 8161/* 0 for success, positive value for failure. */ 8162/****************************************************************************/ 8163static int 8164bce_sysctl_dump_rx_bd_chain(SYSCTL_HANDLER_ARGS) 8165{ 8166 int error; 8167 int result; 8168 struct bce_softc *sc; 8169 8170 result = -1; 8171 error = sysctl_handle_int(oidp, &result, 0, req); 8172 8173 if (error || !req->newptr) 8174 return (error); 8175 8176 if (result == 1) { 8177 sc = (struct bce_softc *)arg1; 8178 bce_dump_rx_bd_chain(sc, 0, TOTAL_RX_BD); 8179 } 8180 8181 return error; 8182} 8183 8184 8185/****************************************************************************/ 8186/* Provides a sysctl interface to allow dumping the RX MBUF chain. */ 8187/* */ 8188/* Returns: */ 8189/* 0 for success, positive value for failure. */ 8190/****************************************************************************/ 8191static int 8192bce_sysctl_dump_rx_mbuf_chain(SYSCTL_HANDLER_ARGS) 8193{ 8194 int error; 8195 int result; 8196 struct bce_softc *sc; 8197 8198 result = -1; 8199 error = sysctl_handle_int(oidp, &result, 0, req); 8200 8201 if (error || !req->newptr) 8202 return (error); 8203 8204 if (result == 1) { 8205 sc = (struct bce_softc *)arg1; 8206 bce_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD); 8207 } 8208 8209 return error; 8210} 8211 8212 8213/****************************************************************************/ 8214/* Provides a sysctl interface to allow dumping the TX chain. */ 8215/* */ 8216/* Returns: */ 8217/* 0 for success, positive value for failure. */ 8218/****************************************************************************/ 8219static int 8220bce_sysctl_dump_tx_chain(SYSCTL_HANDLER_ARGS) 8221{ 8222 int error; 8223 int result; 8224 struct bce_softc *sc; 8225 8226 result = -1; 8227 error = sysctl_handle_int(oidp, &result, 0, req); 8228 8229 if (error || !req->newptr) 8230 return (error); 8231 8232 if (result == 1) { 8233 sc = (struct bce_softc *)arg1; 8234 bce_dump_tx_chain(sc, 0, TOTAL_TX_BD); 8235 } 8236 8237 return error; 8238} 8239 8240 8241#ifdef BCE_JUMBO_HDRSPLIT 8242/****************************************************************************/ 8243/* Provides a sysctl interface to allow dumping the page chain. */ 8244/* */ 8245/* Returns: */ 8246/* 0 for success, positive value for failure. */ 8247/****************************************************************************/ 8248static int 8249bce_sysctl_dump_pg_chain(SYSCTL_HANDLER_ARGS) 8250{ 8251 int error; 8252 int result; 8253 struct bce_softc *sc; 8254 8255 result = -1; 8256 error = sysctl_handle_int(oidp, &result, 0, req); 8257 8258 if (error || !req->newptr) 8259 return (error); 8260 8261 if (result == 1) { 8262 sc = (struct bce_softc *)arg1; 8263 bce_dump_pg_chain(sc, 0, TOTAL_PG_BD); 8264 } 8265 8266 return error; 8267} 8268#endif 8269 8270/****************************************************************************/ 8271/* Provides a sysctl interface to allow reading arbitrary NVRAM offsets in */ 8272/* the device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8273/* */ 8274/* Returns: */ 8275/* 0 for success, positive value for failure. */ 8276/****************************************************************************/ 8277static int 8278bce_sysctl_nvram_read(SYSCTL_HANDLER_ARGS) 8279{ 8280 struct bce_softc *sc = (struct bce_softc *)arg1; 8281 int error; 8282 u32 result; 8283 u32 val[1]; 8284 u8 *data = (u8 *) val; 8285 8286 result = -1; 8287 error = sysctl_handle_int(oidp, &result, 0, req); 8288 if (error || (req->newptr == NULL)) 8289 return (error); 8290 8291 bce_nvram_read(sc, result, data, 4); 8292 BCE_PRINTF("offset 0x%08X = 0x%08X\n", result, bce_be32toh(val[0])); 8293 8294 return (error); 8295} 8296 8297 8298/****************************************************************************/ 8299/* Provides a sysctl interface to allow reading arbitrary registers in the */ 8300/* device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8301/* */ 8302/* Returns: */ 8303/* 0 for success, positive value for failure. */ 8304/****************************************************************************/ 8305static int 8306bce_sysctl_reg_read(SYSCTL_HANDLER_ARGS) 8307{ 8308 struct bce_softc *sc = (struct bce_softc *)arg1; 8309 int error; 8310 u32 val, result; 8311 8312 result = -1; 8313 error = sysctl_handle_int(oidp, &result, 0, req); 8314 if (error || (req->newptr == NULL)) 8315 return (error); 8316 8317 /* Make sure the register is accessible. */ 8318 if (result < 0x8000) { 8319 val = REG_RD(sc, result); 8320 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val); 8321 } else if (result < 0x0280000) { 8322 val = REG_RD_IND(sc, result); 8323 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val); 8324 } 8325 8326 return (error); 8327} 8328 8329 8330/****************************************************************************/ 8331/* Provides a sysctl interface to allow reading arbitrary PHY registers in */ 8332/* the device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8333/* */ 8334/* Returns: */ 8335/* 0 for success, positive value for failure. */ 8336/****************************************************************************/ 8337static int 8338bce_sysctl_phy_read(SYSCTL_HANDLER_ARGS) 8339{ 8340 struct bce_softc *sc; 8341 device_t dev; 8342 int error, result; 8343 u16 val; 8344 8345 result = -1; 8346 error = sysctl_handle_int(oidp, &result, 0, req); 8347 if (error || (req->newptr == NULL)) 8348 return (error); 8349 8350 /* Make sure the register is accessible. */ 8351 if (result < 0x20) { 8352 sc = (struct bce_softc *)arg1; 8353 dev = sc->bce_dev; 8354 val = bce_miibus_read_reg(dev, sc->bce_phy_addr, result); 8355 BCE_PRINTF("phy 0x%02X = 0x%04X\n", result, val); 8356 } 8357 return (error); 8358} 8359 8360 8361/****************************************************************************/ 8362/* Provides a sysctl interface to allow reading a CID. */ 8363/* */ 8364/* Returns: */ 8365/* 0 for success, positive value for failure. */ 8366/****************************************************************************/ 8367static int 8368bce_sysctl_dump_ctx(SYSCTL_HANDLER_ARGS) 8369{ 8370 struct bce_softc *sc; 8371 int error, result; 8372 8373 result = -1; 8374 error = sysctl_handle_int(oidp, &result, 0, req); 8375 if (error || (req->newptr == NULL)) 8376 return (error); 8377 8378 /* Make sure the register is accessible. */ 8379 if (result <= TX_CID) { 8380 sc = (struct bce_softc *)arg1; 8381 bce_dump_ctx(sc, result); 8382 } 8383 8384 return (error); 8385} 8386 8387 8388 /****************************************************************************/ 8389/* Provides a sysctl interface to forcing the driver to dump state and */ 8390/* enter the debugger. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8391/* */ 8392/* Returns: */ 8393/* 0 for success, positive value for failure. */ 8394/****************************************************************************/ 8395static int 8396bce_sysctl_breakpoint(SYSCTL_HANDLER_ARGS) 8397{ 8398 int error; 8399 int result; 8400 struct bce_softc *sc; 8401 8402 result = -1; 8403 error = sysctl_handle_int(oidp, &result, 0, req); 8404 8405 if (error || !req->newptr) 8406 return (error); 8407 8408 if (result == 1) { 8409 sc = (struct bce_softc *)arg1; 8410 bce_breakpoint(sc); 8411 } 8412 8413 return error; 8414} 8415#endif 8416 8417 8418/****************************************************************************/ 8419/* Adds any sysctl parameters for tuning or debugging purposes. */ 8420/* */ 8421/* Returns: */ 8422/* 0 for success, positive value for failure. */ 8423/****************************************************************************/ 8424static void 8425bce_add_sysctls(struct bce_softc *sc) 8426{ 8427 struct sysctl_ctx_list *ctx; 8428 struct sysctl_oid_list *children; 8429 8430 DBENTER(BCE_VERBOSE_MISC); 8431 8432 ctx = device_get_sysctl_ctx(sc->bce_dev); 8433 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bce_dev)); 8434 8435#ifdef BCE_DEBUG 8436 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8437 "l2fhdr_error_sim_control", 8438 CTLFLAG_RW, &l2fhdr_error_sim_control, 8439 0, "Debug control to force l2fhdr errors"); 8440 8441 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8442 "l2fhdr_error_sim_count", 8443 CTLFLAG_RD, &sc->l2fhdr_error_sim_count, 8444 0, "Number of simulated l2_fhdr errors"); 8445#endif 8446 8447 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8448 "l2fhdr_error_count", 8449 CTLFLAG_RD, &sc->l2fhdr_error_count, 8450 0, "Number of l2_fhdr errors"); 8451 8452#ifdef BCE_DEBUG 8453 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8454 "mbuf_alloc_failed_sim_control", 8455 CTLFLAG_RW, &mbuf_alloc_failed_sim_control, 8456 0, "Debug control to force mbuf allocation failures"); 8457 8458 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8459 "mbuf_alloc_failed_sim_count", 8460 CTLFLAG_RD, &sc->mbuf_alloc_failed_sim_count, 8461 0, "Number of simulated mbuf cluster allocation failures"); 8462#endif 8463 8464 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8465 "mbuf_alloc_failed_count", 8466 CTLFLAG_RD, &sc->mbuf_alloc_failed_count, 8467 0, "Number of mbuf allocation failures"); 8468 8469 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8470 "mbuf_frag_count", 8471 CTLFLAG_RD, &sc->mbuf_frag_count, 8472 0, "Number of fragmented mbufs"); 8473 8474#ifdef BCE_DEBUG 8475 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8476 "dma_map_addr_failed_sim_control", 8477 CTLFLAG_RW, &dma_map_addr_failed_sim_control, 8478 0, "Debug control to force DMA mapping failures"); 8479 8480 /* ToDo: Figure out how to update this value in bce_dma_map_addr(). */ 8481 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8482 "dma_map_addr_failed_sim_count", 8483 CTLFLAG_RD, &sc->dma_map_addr_failed_sim_count, 8484 0, "Number of simulated DMA mapping failures"); 8485 8486#endif 8487 8488 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8489 "dma_map_addr_rx_failed_count", 8490 CTLFLAG_RD, &sc->dma_map_addr_rx_failed_count, 8491 0, "Number of RX DMA mapping failures"); 8492 8493 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8494 "dma_map_addr_tx_failed_count", 8495 CTLFLAG_RD, &sc->dma_map_addr_tx_failed_count, 8496 0, "Number of TX DMA mapping failures"); 8497 8498#ifdef BCE_DEBUG 8499 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8500 "unexpected_attention_sim_control", 8501 CTLFLAG_RW, &unexpected_attention_sim_control, 8502 0, "Debug control to simulate unexpected attentions"); 8503 8504 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8505 "unexpected_attention_sim_count", 8506 CTLFLAG_RW, &sc->unexpected_attention_sim_count, 8507 0, "Number of simulated unexpected attentions"); 8508#endif 8509 8510 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8511 "unexpected_attention_count", 8512 CTLFLAG_RW, &sc->unexpected_attention_count, 8513 0, "Number of unexpected attentions"); 8514 8515#ifdef BCE_DEBUG 8516 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8517 "debug_bootcode_running_failure", 8518 CTLFLAG_RW, &bootcode_running_failure_sim_control, 8519 0, "Debug control to force bootcode running failures"); 8520 8521 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8522 "rx_low_watermark", 8523 CTLFLAG_RD, &sc->rx_low_watermark, 8524 0, "Lowest level of free rx_bd's"); 8525 8526 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8527 "rx_empty_count", 8528 CTLFLAG_RD, &sc->rx_empty_count, 8529 0, "Number of times the RX chain was empty"); 8530 8531 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8532 "tx_hi_watermark", 8533 CTLFLAG_RD, &sc->tx_hi_watermark, 8534 0, "Highest level of used tx_bd's"); 8535 8536 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8537 "tx_full_count", 8538 CTLFLAG_RD, &sc->tx_full_count, 8539 0, "Number of times the TX chain was full"); 8540 8541 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8542 "tso_frames_requested", 8543 CTLFLAG_RD, &sc->tso_frames_requested, 8544 0, "Number of TSO frames requested"); 8545 8546 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8547 "tso_frames_completed", 8548 CTLFLAG_RD, &sc->tso_frames_completed, 8549 0, "Number of TSO frames completed"); 8550 8551 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8552 "tso_frames_failed", 8553 CTLFLAG_RD, &sc->tso_frames_failed, 8554 0, "Number of TSO frames failed"); 8555 8556 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8557 "csum_offload_ip", 8558 CTLFLAG_RD, &sc->csum_offload_ip, 8559 0, "Number of IP checksum offload frames"); 8560 8561 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8562 "csum_offload_tcp_udp", 8563 CTLFLAG_RD, &sc->csum_offload_tcp_udp, 8564 0, "Number of TCP/UDP checksum offload frames"); 8565 8566 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8567 "vlan_tagged_frames_rcvd", 8568 CTLFLAG_RD, &sc->vlan_tagged_frames_rcvd, 8569 0, "Number of VLAN tagged frames received"); 8570 8571 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8572 "vlan_tagged_frames_stripped", 8573 CTLFLAG_RD, &sc->vlan_tagged_frames_stripped, 8574 0, "Number of VLAN tagged frames stripped"); 8575 8576 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8577 "interrupts_rx", 8578 CTLFLAG_RD, &sc->interrupts_rx, 8579 0, "Number of RX interrupts"); 8580 8581 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8582 "interrupts_tx", 8583 CTLFLAG_RD, &sc->interrupts_tx, 8584 0, "Number of TX interrupts"); 8585#endif 8586 8587 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 8588 "stat_IfHcInOctets", 8589 CTLFLAG_RD, &sc->stat_IfHCInOctets, 8590 "Bytes received"); 8591 8592 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 8593 "stat_IfHCInBadOctets", 8594 CTLFLAG_RD, &sc->stat_IfHCInBadOctets, 8595 "Bad bytes received"); 8596 8597 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 8598 "stat_IfHCOutOctets", 8599 CTLFLAG_RD, &sc->stat_IfHCOutOctets, 8600 "Bytes sent"); 8601 8602 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 8603 "stat_IfHCOutBadOctets", 8604 CTLFLAG_RD, &sc->stat_IfHCOutBadOctets, 8605 "Bad bytes sent"); 8606 8607 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 8608 "stat_IfHCInUcastPkts", 8609 CTLFLAG_RD, &sc->stat_IfHCInUcastPkts, 8610 "Unicast packets received"); 8611 8612 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 8613 "stat_IfHCInMulticastPkts", 8614 CTLFLAG_RD, &sc->stat_IfHCInMulticastPkts, 8615 "Multicast packets received"); 8616 8617 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 8618 "stat_IfHCInBroadcastPkts", 8619 CTLFLAG_RD, &sc->stat_IfHCInBroadcastPkts, 8620 "Broadcast packets received"); 8621 8622 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 8623 "stat_IfHCOutUcastPkts", 8624 CTLFLAG_RD, &sc->stat_IfHCOutUcastPkts, 8625 "Unicast packets sent"); 8626 8627 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 8628 "stat_IfHCOutMulticastPkts", 8629 CTLFLAG_RD, &sc->stat_IfHCOutMulticastPkts, 8630 "Multicast packets sent"); 8631 8632 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 8633 "stat_IfHCOutBroadcastPkts", 8634 CTLFLAG_RD, &sc->stat_IfHCOutBroadcastPkts, 8635 "Broadcast packets sent"); 8636 8637 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8638 "stat_emac_tx_stat_dot3statsinternalmactransmiterrors", 8639 CTLFLAG_RD, &sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors, 8640 0, "Internal MAC transmit errors"); 8641 8642 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8643 "stat_Dot3StatsCarrierSenseErrors", 8644 CTLFLAG_RD, &sc->stat_Dot3StatsCarrierSenseErrors, 8645 0, "Carrier sense errors"); 8646 8647 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8648 "stat_Dot3StatsFCSErrors", 8649 CTLFLAG_RD, &sc->stat_Dot3StatsFCSErrors, 8650 0, "Frame check sequence errors"); 8651 8652 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8653 "stat_Dot3StatsAlignmentErrors", 8654 CTLFLAG_RD, &sc->stat_Dot3StatsAlignmentErrors, 8655 0, "Alignment errors"); 8656 8657 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8658 "stat_Dot3StatsSingleCollisionFrames", 8659 CTLFLAG_RD, &sc->stat_Dot3StatsSingleCollisionFrames, 8660 0, "Single Collision Frames"); 8661 8662 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8663 "stat_Dot3StatsMultipleCollisionFrames", 8664 CTLFLAG_RD, &sc->stat_Dot3StatsMultipleCollisionFrames, 8665 0, "Multiple Collision Frames"); 8666 8667 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8668 "stat_Dot3StatsDeferredTransmissions", 8669 CTLFLAG_RD, &sc->stat_Dot3StatsDeferredTransmissions, 8670 0, "Deferred Transmissions"); 8671 8672 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8673 "stat_Dot3StatsExcessiveCollisions", 8674 CTLFLAG_RD, &sc->stat_Dot3StatsExcessiveCollisions, 8675 0, "Excessive Collisions"); 8676 8677 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8678 "stat_Dot3StatsLateCollisions", 8679 CTLFLAG_RD, &sc->stat_Dot3StatsLateCollisions, 8680 0, "Late Collisions"); 8681 8682 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8683 "stat_EtherStatsCollisions", 8684 CTLFLAG_RD, &sc->stat_EtherStatsCollisions, 8685 0, "Collisions"); 8686 8687 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8688 "stat_EtherStatsFragments", 8689 CTLFLAG_RD, &sc->stat_EtherStatsFragments, 8690 0, "Fragments"); 8691 8692 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8693 "stat_EtherStatsJabbers", 8694 CTLFLAG_RD, &sc->stat_EtherStatsJabbers, 8695 0, "Jabbers"); 8696 8697 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8698 "stat_EtherStatsUndersizePkts", 8699 CTLFLAG_RD, &sc->stat_EtherStatsUndersizePkts, 8700 0, "Undersize packets"); 8701 8702 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8703 "stat_EtherStatsOversizePkts", 8704 CTLFLAG_RD, &sc->stat_EtherStatsOversizePkts, 8705 0, "stat_EtherStatsOversizePkts"); 8706 8707 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8708 "stat_EtherStatsPktsRx64Octets", 8709 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx64Octets, 8710 0, "Bytes received in 64 byte packets"); 8711 8712 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8713 "stat_EtherStatsPktsRx65Octetsto127Octets", 8714 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx65Octetsto127Octets, 8715 0, "Bytes received in 65 to 127 byte packets"); 8716 8717 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8718 "stat_EtherStatsPktsRx128Octetsto255Octets", 8719 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx128Octetsto255Octets, 8720 0, "Bytes received in 128 to 255 byte packets"); 8721 8722 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8723 "stat_EtherStatsPktsRx256Octetsto511Octets", 8724 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx256Octetsto511Octets, 8725 0, "Bytes received in 256 to 511 byte packets"); 8726 8727 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8728 "stat_EtherStatsPktsRx512Octetsto1023Octets", 8729 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx512Octetsto1023Octets, 8730 0, "Bytes received in 512 to 1023 byte packets"); 8731 8732 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8733 "stat_EtherStatsPktsRx1024Octetsto1522Octets", 8734 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1024Octetsto1522Octets, 8735 0, "Bytes received in 1024 t0 1522 byte packets"); 8736 8737 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8738 "stat_EtherStatsPktsRx1523Octetsto9022Octets", 8739 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1523Octetsto9022Octets, 8740 0, "Bytes received in 1523 to 9022 byte packets"); 8741 8742 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8743 "stat_EtherStatsPktsTx64Octets", 8744 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx64Octets, 8745 0, "Bytes sent in 64 byte packets"); 8746 8747 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8748 "stat_EtherStatsPktsTx65Octetsto127Octets", 8749 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx65Octetsto127Octets, 8750 0, "Bytes sent in 65 to 127 byte packets"); 8751 8752 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8753 "stat_EtherStatsPktsTx128Octetsto255Octets", 8754 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx128Octetsto255Octets, 8755 0, "Bytes sent in 128 to 255 byte packets"); 8756 8757 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8758 "stat_EtherStatsPktsTx256Octetsto511Octets", 8759 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx256Octetsto511Octets, 8760 0, "Bytes sent in 256 to 511 byte packets"); 8761 8762 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8763 "stat_EtherStatsPktsTx512Octetsto1023Octets", 8764 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx512Octetsto1023Octets, 8765 0, "Bytes sent in 512 to 1023 byte packets"); 8766 8767 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8768 "stat_EtherStatsPktsTx1024Octetsto1522Octets", 8769 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1024Octetsto1522Octets, 8770 0, "Bytes sent in 1024 to 1522 byte packets"); 8771 8772 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8773 "stat_EtherStatsPktsTx1523Octetsto9022Octets", 8774 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1523Octetsto9022Octets, 8775 0, "Bytes sent in 1523 to 9022 byte packets"); 8776 8777 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8778 "stat_XonPauseFramesReceived", 8779 CTLFLAG_RD, &sc->stat_XonPauseFramesReceived, 8780 0, "XON pause frames receved"); 8781 8782 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8783 "stat_XoffPauseFramesReceived", 8784 CTLFLAG_RD, &sc->stat_XoffPauseFramesReceived, 8785 0, "XOFF pause frames received"); 8786 8787 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8788 "stat_OutXonSent", 8789 CTLFLAG_RD, &sc->stat_OutXonSent, 8790 0, "XON pause frames sent"); 8791 8792 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8793 "stat_OutXoffSent", 8794 CTLFLAG_RD, &sc->stat_OutXoffSent, 8795 0, "XOFF pause frames sent"); 8796 8797 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8798 "stat_FlowControlDone", 8799 CTLFLAG_RD, &sc->stat_FlowControlDone, 8800 0, "Flow control done"); 8801 8802 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8803 "stat_MacControlFramesReceived", 8804 CTLFLAG_RD, &sc->stat_MacControlFramesReceived, 8805 0, "MAC control frames received"); 8806 8807 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8808 "stat_XoffStateEntered", 8809 CTLFLAG_RD, &sc->stat_XoffStateEntered, 8810 0, "XOFF state entered"); 8811 8812 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8813 "stat_IfInFramesL2FilterDiscards", 8814 CTLFLAG_RD, &sc->stat_IfInFramesL2FilterDiscards, 8815 0, "Received L2 packets discarded"); 8816 8817 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8818 "stat_IfInRuleCheckerDiscards", 8819 CTLFLAG_RD, &sc->stat_IfInRuleCheckerDiscards, 8820 0, "Received packets discarded by rule"); 8821 8822 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8823 "stat_IfInFTQDiscards", 8824 CTLFLAG_RD, &sc->stat_IfInFTQDiscards, 8825 0, "Received packet FTQ discards"); 8826 8827 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8828 "stat_IfInMBUFDiscards", 8829 CTLFLAG_RD, &sc->stat_IfInMBUFDiscards, 8830 0, "Received packets discarded due to lack " 8831 "of controller buffer memory"); 8832 8833 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8834 "stat_IfInRuleCheckerP4Hit", 8835 CTLFLAG_RD, &sc->stat_IfInRuleCheckerP4Hit, 8836 0, "Received packets rule checker hits"); 8837 8838 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8839 "stat_CatchupInRuleCheckerDiscards", 8840 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerDiscards, 8841 0, "Received packets discarded in Catchup path"); 8842 8843 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8844 "stat_CatchupInFTQDiscards", 8845 CTLFLAG_RD, &sc->stat_CatchupInFTQDiscards, 8846 0, "Received packets discarded in FTQ in Catchup path"); 8847 8848 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8849 "stat_CatchupInMBUFDiscards", 8850 CTLFLAG_RD, &sc->stat_CatchupInMBUFDiscards, 8851 0, "Received packets discarded in controller " 8852 "buffer memory in Catchup path"); 8853 8854 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8855 "stat_CatchupInRuleCheckerP4Hit", 8856 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerP4Hit, 8857 0, "Received packets rule checker hits in Catchup path"); 8858 8859 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8860 "com_no_buffers", 8861 CTLFLAG_RD, &sc->com_no_buffers, 8862 0, "Valid packets received but no RX buffers available"); 8863 8864#ifdef BCE_DEBUG 8865 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8866 "driver_state", CTLTYPE_INT | CTLFLAG_RW, 8867 (void *)sc, 0, 8868 bce_sysctl_driver_state, "I", "Drive state information"); 8869 8870 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8871 "hw_state", CTLTYPE_INT | CTLFLAG_RW, 8872 (void *)sc, 0, 8873 bce_sysctl_hw_state, "I", "Hardware state information"); 8874 8875 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8876 "status_block", CTLTYPE_INT | CTLFLAG_RW, 8877 (void *)sc, 0, 8878 bce_sysctl_status_block, "I", "Dump status block"); 8879 8880 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8881 "stats_block", CTLTYPE_INT | CTLFLAG_RW, 8882 (void *)sc, 0, 8883 bce_sysctl_stats_block, "I", "Dump statistics block"); 8884 8885 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8886 "stats_clear", CTLTYPE_INT | CTLFLAG_RW, 8887 (void *)sc, 0, 8888 bce_sysctl_stats_clear, "I", "Clear statistics block"); 8889 8890 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8891 "bc_state", CTLTYPE_INT | CTLFLAG_RW, 8892 (void *)sc, 0, 8893 bce_sysctl_bc_state, "I", "Bootcode state information"); 8894 8895 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8896 "dump_rx_bd_chain", CTLTYPE_INT | CTLFLAG_RW, 8897 (void *)sc, 0, 8898 bce_sysctl_dump_rx_bd_chain, "I", "Dump RX BD chain"); 8899 8900 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8901 "dump_rx_mbuf_chain", CTLTYPE_INT | CTLFLAG_RW, 8902 (void *)sc, 0, 8903 bce_sysctl_dump_rx_mbuf_chain, "I", "Dump RX MBUF chain"); 8904 8905 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8906 "dump_tx_chain", CTLTYPE_INT | CTLFLAG_RW, 8907 (void *)sc, 0, 8908 bce_sysctl_dump_tx_chain, "I", "Dump tx_bd chain"); 8909 8910#ifdef BCE_JUMBO_HDRSPLIT 8911 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8912 "dump_pg_chain", CTLTYPE_INT | CTLFLAG_RW, 8913 (void *)sc, 0, 8914 bce_sysctl_dump_pg_chain, "I", "Dump page chain"); 8915#endif 8916 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8917 "dump_ctx", CTLTYPE_INT | CTLFLAG_RW, 8918 (void *)sc, 0, 8919 bce_sysctl_dump_ctx, "I", "Dump context memory"); 8920 8921 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8922 "breakpoint", CTLTYPE_INT | CTLFLAG_RW, 8923 (void *)sc, 0, 8924 bce_sysctl_breakpoint, "I", "Driver breakpoint"); 8925 8926 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8927 "reg_read", CTLTYPE_INT | CTLFLAG_RW, 8928 (void *)sc, 0, 8929 bce_sysctl_reg_read, "I", "Register read"); 8930 8931 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8932 "nvram_read", CTLTYPE_INT | CTLFLAG_RW, 8933 (void *)sc, 0, 8934 bce_sysctl_nvram_read, "I", "NVRAM read"); 8935 8936 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8937 "phy_read", CTLTYPE_INT | CTLFLAG_RW, 8938 (void *)sc, 0, 8939 bce_sysctl_phy_read, "I", "PHY register read"); 8940 8941#endif 8942 8943 DBEXIT(BCE_VERBOSE_MISC); 8944} 8945 8946 8947/****************************************************************************/ 8948/* BCE Debug Routines */ 8949/****************************************************************************/ 8950#ifdef BCE_DEBUG 8951 8952/****************************************************************************/ 8953/* Freezes the controller to allow for a cohesive state dump. */ 8954/* */ 8955/* Returns: */ 8956/* Nothing. */ 8957/****************************************************************************/ 8958static __attribute__ ((noinline)) void 8959bce_freeze_controller(struct bce_softc *sc) 8960{ 8961 u32 val; 8962 val = REG_RD(sc, BCE_MISC_COMMAND); 8963 val |= BCE_MISC_COMMAND_DISABLE_ALL; 8964 REG_WR(sc, BCE_MISC_COMMAND, val); 8965} 8966 8967 8968/****************************************************************************/ 8969/* Unfreezes the controller after a freeze operation. This may not always */ 8970/* work and the controller will require a reset! */ 8971/* */ 8972/* Returns: */ 8973/* Nothing. */ 8974/****************************************************************************/ 8975static __attribute__ ((noinline)) void 8976bce_unfreeze_controller(struct bce_softc *sc) 8977{ 8978 u32 val; 8979 val = REG_RD(sc, BCE_MISC_COMMAND); 8980 val |= BCE_MISC_COMMAND_ENABLE_ALL; 8981 REG_WR(sc, BCE_MISC_COMMAND, val); 8982} 8983 8984 8985/****************************************************************************/ 8986/* Prints out Ethernet frame information from an mbuf. */ 8987/* */ 8988/* Partially decode an Ethernet frame to look at some important headers. */ 8989/* */ 8990/* Returns: */ 8991/* Nothing. */ 8992/****************************************************************************/ 8993static __attribute__ ((noinline)) void 8994bce_dump_enet(struct bce_softc *sc, struct mbuf *m) 8995{ 8996 struct ether_vlan_header *eh; 8997 u16 etype; 8998 int ehlen; 8999 struct ip *ip; 9000 struct tcphdr *th; 9001 struct udphdr *uh; 9002 struct arphdr *ah; 9003 9004 BCE_PRINTF( 9005 "-----------------------------" 9006 " Frame Decode " 9007 "-----------------------------\n"); 9008 9009 eh = mtod(m, struct ether_vlan_header *); 9010 9011 /* Handle VLAN encapsulation if present. */ 9012 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 9013 etype = ntohs(eh->evl_proto); 9014 ehlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 9015 } else { 9016 etype = ntohs(eh->evl_encap_proto); 9017 ehlen = ETHER_HDR_LEN; 9018 } 9019 9020 /* ToDo: Add VLAN output. */ 9021 BCE_PRINTF("enet: dest = %6D, src = %6D, type = 0x%04X, hlen = %d\n", 9022 eh->evl_dhost, ":", eh->evl_shost, ":", etype, ehlen); 9023 9024 switch (etype) { 9025 case ETHERTYPE_IP: 9026 ip = (struct ip *)(m->m_data + ehlen); 9027 BCE_PRINTF("--ip: dest = 0x%08X , src = 0x%08X, " 9028 "len = %d bytes, protocol = 0x%02X, xsum = 0x%04X\n", 9029 ntohl(ip->ip_dst.s_addr), ntohl(ip->ip_src.s_addr), 9030 ntohs(ip->ip_len), ip->ip_p, ntohs(ip->ip_sum)); 9031 9032 switch (ip->ip_p) { 9033 case IPPROTO_TCP: 9034 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 9035 BCE_PRINTF("-tcp: dest = %d, src = %d, hlen = " 9036 "%d bytes, flags = 0x%b, csum = 0x%04X\n", 9037 ntohs(th->th_dport), ntohs(th->th_sport), 9038 (th->th_off << 2), th->th_flags, 9039 "\20\10CWR\07ECE\06URG\05ACK\04PSH\03RST" 9040 "\02SYN\01FIN", ntohs(th->th_sum)); 9041 break; 9042 case IPPROTO_UDP: 9043 uh = (struct udphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 9044 BCE_PRINTF("-udp: dest = %d, src = %d, len = %d " 9045 "bytes, csum = 0x%04X\n", ntohs(uh->uh_dport), 9046 ntohs(uh->uh_sport), ntohs(uh->uh_ulen), 9047 ntohs(uh->uh_sum)); 9048 break; 9049 case IPPROTO_ICMP: 9050 BCE_PRINTF("icmp:\n"); 9051 break; 9052 default: 9053 BCE_PRINTF("----: Other IP protocol.\n"); 9054 } 9055 break; 9056 case ETHERTYPE_IPV6: 9057 BCE_PRINTF("ipv6: No decode supported.\n"); 9058 break; 9059 case ETHERTYPE_ARP: 9060 BCE_PRINTF("-arp: "); 9061 ah = (struct arphdr *) (m->m_data + ehlen); 9062 switch (ntohs(ah->ar_op)) { 9063 case ARPOP_REVREQUEST: 9064 printf("reverse ARP request\n"); 9065 break; 9066 case ARPOP_REVREPLY: 9067 printf("reverse ARP reply\n"); 9068 break; 9069 case ARPOP_REQUEST: 9070 printf("ARP request\n"); 9071 break; 9072 case ARPOP_REPLY: 9073 printf("ARP reply\n"); 9074 break; 9075 default: 9076 printf("other ARP operation\n"); 9077 } 9078 break; 9079 default: 9080 BCE_PRINTF("----: Other protocol.\n"); 9081 } 9082 9083 BCE_PRINTF( 9084 "-----------------------------" 9085 "--------------" 9086 "-----------------------------\n"); 9087} 9088 9089 9090/****************************************************************************/ 9091/* Prints out information about an mbuf. */ 9092/* */ 9093/* Returns: */ 9094/* Nothing. */ 9095/****************************************************************************/ 9096static __attribute__ ((noinline)) void 9097bce_dump_mbuf(struct bce_softc *sc, struct mbuf *m) 9098{ 9099 struct mbuf *mp = m; 9100 9101 if (m == NULL) { 9102 BCE_PRINTF("mbuf: null pointer\n"); 9103 return; 9104 } 9105 9106 while (mp) { 9107 BCE_PRINTF("mbuf: %p, m_len = %d, m_flags = 0x%b, " 9108 "m_data = %p\n", mp, mp->m_len, mp->m_flags, 9109 "\20\1M_EXT\2M_PKTHDR\3M_EOR\4M_RDONLY", mp->m_data); 9110 9111 if (mp->m_flags & M_PKTHDR) { 9112 BCE_PRINTF("- m_pkthdr: len = %d, flags = 0x%b, " 9113 "csum_flags = %b\n", mp->m_pkthdr.len, 9114 mp->m_flags, "\20\12M_BCAST\13M_MCAST\14M_FRAG" 9115 "\15M_FIRSTFRAG\16M_LASTFRAG\21M_VLANTAG" 9116 "\22M_PROMISC\23M_NOFREE", 9117 mp->m_pkthdr.csum_flags, 9118 "\20\1CSUM_IP\2CSUM_TCP\3CSUM_UDP\4CSUM_IP_FRAGS" 9119 "\5CSUM_FRAGMENT\6CSUM_TSO\11CSUM_IP_CHECKED" 9120 "\12CSUM_IP_VALID\13CSUM_DATA_VALID" 9121 "\14CSUM_PSEUDO_HDR"); 9122 } 9123 9124 if (mp->m_flags & M_EXT) { 9125 BCE_PRINTF("- m_ext: %p, ext_size = %d, type = ", 9126 mp->m_ext.ext_buf, mp->m_ext.ext_size); 9127 switch (mp->m_ext.ext_type) { 9128 case EXT_CLUSTER: 9129 printf("EXT_CLUSTER\n"); break; 9130 case EXT_SFBUF: 9131 printf("EXT_SFBUF\n"); break; 9132 case EXT_JUMBO9: 9133 printf("EXT_JUMBO9\n"); break; 9134 case EXT_JUMBO16: 9135 printf("EXT_JUMBO16\n"); break; 9136 case EXT_PACKET: 9137 printf("EXT_PACKET\n"); break; 9138 case EXT_MBUF: 9139 printf("EXT_MBUF\n"); break; 9140 case EXT_NET_DRV: 9141 printf("EXT_NET_DRV\n"); break; 9142 case EXT_MOD_TYPE: 9143 printf("EXT_MDD_TYPE\n"); break; 9144 case EXT_DISPOSABLE: 9145 printf("EXT_DISPOSABLE\n"); break; 9146 case EXT_EXTREF: 9147 printf("EXT_EXTREF\n"); break; 9148 default: 9149 printf("UNKNOWN\n"); 9150 } 9151 } 9152 9153 mp = mp->m_next; 9154 } 9155} 9156 9157 9158/****************************************************************************/ 9159/* Prints out the mbufs in the TX mbuf chain. */ 9160/* */ 9161/* Returns: */ 9162/* Nothing. */ 9163/****************************************************************************/ 9164static __attribute__ ((noinline)) void 9165bce_dump_tx_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count) 9166{ 9167 struct mbuf *m; 9168 9169 BCE_PRINTF( 9170 "----------------------------" 9171 " tx mbuf data " 9172 "----------------------------\n"); 9173 9174 for (int i = 0; i < count; i++) { 9175 m = sc->tx_mbuf_ptr[chain_prod]; 9176 BCE_PRINTF("txmbuf[0x%04X]\n", chain_prod); 9177 bce_dump_mbuf(sc, m); 9178 chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod)); 9179 } 9180 9181 BCE_PRINTF( 9182 "----------------------------" 9183 "----------------" 9184 "----------------------------\n"); 9185} 9186 9187 9188/****************************************************************************/ 9189/* Prints out the mbufs in the RX mbuf chain. */ 9190/* */ 9191/* Returns: */ 9192/* Nothing. */ 9193/****************************************************************************/ 9194static __attribute__ ((noinline)) void 9195bce_dump_rx_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count) 9196{ 9197 struct mbuf *m; 9198 9199 BCE_PRINTF( 9200 "----------------------------" 9201 " rx mbuf data " 9202 "----------------------------\n"); 9203 9204 for (int i = 0; i < count; i++) { 9205 m = sc->rx_mbuf_ptr[chain_prod]; 9206 BCE_PRINTF("rxmbuf[0x%04X]\n", chain_prod); 9207 bce_dump_mbuf(sc, m); 9208 chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod)); 9209 } 9210 9211 9212 BCE_PRINTF( 9213 "----------------------------" 9214 "----------------" 9215 "----------------------------\n"); 9216} 9217 9218 9219#ifdef BCE_JUMBO_HDRSPLIT 9220/****************************************************************************/ 9221/* Prints out the mbufs in the mbuf page chain. */ 9222/* */ 9223/* Returns: */ 9224/* Nothing. */ 9225/****************************************************************************/ 9226static __attribute__ ((noinline)) void 9227bce_dump_pg_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count) 9228{ 9229 struct mbuf *m; 9230 9231 BCE_PRINTF( 9232 "----------------------------" 9233 " pg mbuf data " 9234 "----------------------------\n"); 9235 9236 for (int i = 0; i < count; i++) { 9237 m = sc->pg_mbuf_ptr[chain_prod]; 9238 BCE_PRINTF("pgmbuf[0x%04X]\n", chain_prod); 9239 bce_dump_mbuf(sc, m); 9240 chain_prod = PG_CHAIN_IDX(NEXT_PG_BD(chain_prod)); 9241 } 9242 9243 9244 BCE_PRINTF( 9245 "----------------------------" 9246 "----------------" 9247 "----------------------------\n"); 9248} 9249#endif 9250 9251 9252/****************************************************************************/ 9253/* Prints out a tx_bd structure. */ 9254/* */ 9255/* Returns: */ 9256/* Nothing. */ 9257/****************************************************************************/ 9258static __attribute__ ((noinline)) void 9259bce_dump_txbd(struct bce_softc *sc, int idx, struct tx_bd *txbd) 9260{ 9261 int i = 0; 9262 9263 if (idx > MAX_TX_BD) 9264 /* Index out of range. */ 9265 BCE_PRINTF("tx_bd[0x%04X]: Invalid tx_bd index!\n", idx); 9266 else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 9267 /* TX Chain page pointer. */ 9268 BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page " 9269 "pointer\n", idx, txbd->tx_bd_haddr_hi, 9270 txbd->tx_bd_haddr_lo); 9271 else { 9272 /* Normal tx_bd entry. */ 9273 BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, " 9274 "mss_nbytes = 0x%08X, vlan tag = 0x%04X, flags = " 9275 "0x%04X (", idx, txbd->tx_bd_haddr_hi, 9276 txbd->tx_bd_haddr_lo, txbd->tx_bd_mss_nbytes, 9277 txbd->tx_bd_vlan_tag, txbd->tx_bd_flags); 9278 9279 if (txbd->tx_bd_flags & TX_BD_FLAGS_CONN_FAULT) { 9280 if (i>0) 9281 printf("|"); 9282 printf("CONN_FAULT"); 9283 i++; 9284 } 9285 9286 if (txbd->tx_bd_flags & TX_BD_FLAGS_TCP_UDP_CKSUM) { 9287 if (i>0) 9288 printf("|"); 9289 printf("TCP_UDP_CKSUM"); 9290 i++; 9291 } 9292 9293 if (txbd->tx_bd_flags & TX_BD_FLAGS_IP_CKSUM) { 9294 if (i>0) 9295 printf("|"); 9296 printf("IP_CKSUM"); 9297 i++; 9298 } 9299 9300 if (txbd->tx_bd_flags & TX_BD_FLAGS_VLAN_TAG) { 9301 if (i>0) 9302 printf("|"); 9303 printf("VLAN"); 9304 i++; 9305 } 9306 9307 if (txbd->tx_bd_flags & TX_BD_FLAGS_COAL_NOW) { 9308 if (i>0) 9309 printf("|"); 9310 printf("COAL_NOW"); 9311 i++; 9312 } 9313 9314 if (txbd->tx_bd_flags & TX_BD_FLAGS_DONT_GEN_CRC) { 9315 if (i>0) 9316 printf("|"); 9317 printf("DONT_GEN_CRC"); 9318 i++; 9319 } 9320 9321 if (txbd->tx_bd_flags & TX_BD_FLAGS_START) { 9322 if (i>0) 9323 printf("|"); 9324 printf("START"); 9325 i++; 9326 } 9327 9328 if (txbd->tx_bd_flags & TX_BD_FLAGS_END) { 9329 if (i>0) 9330 printf("|"); 9331 printf("END"); 9332 i++; 9333 } 9334 9335 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_LSO) { 9336 if (i>0) 9337 printf("|"); 9338 printf("LSO"); 9339 i++; 9340 } 9341 9342 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_OPTION_WORD) { 9343 if (i>0) 9344 printf("|"); 9345 printf("SW_OPTION=%d", ((txbd->tx_bd_flags & 9346 TX_BD_FLAGS_SW_OPTION_WORD) >> 8)); i++; 9347 } 9348 9349 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_FLAGS) { 9350 if (i>0) 9351 printf("|"); 9352 printf("SW_FLAGS"); 9353 i++; 9354 } 9355 9356 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_SNAP) { 9357 if (i>0) 9358 printf("|"); 9359 printf("SNAP)"); 9360 } else { 9361 printf(")\n"); 9362 } 9363 } 9364} 9365 9366 9367/****************************************************************************/ 9368/* Prints out a rx_bd structure. */ 9369/* */ 9370/* Returns: */ 9371/* Nothing. */ 9372/****************************************************************************/ 9373static __attribute__ ((noinline)) void 9374bce_dump_rxbd(struct bce_softc *sc, int idx, struct rx_bd *rxbd) 9375{ 9376 if (idx > MAX_RX_BD) 9377 /* Index out of range. */ 9378 BCE_PRINTF("rx_bd[0x%04X]: Invalid rx_bd index!\n", idx); 9379 else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 9380 /* RX Chain page pointer. */ 9381 BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page " 9382 "pointer\n", idx, rxbd->rx_bd_haddr_hi, 9383 rxbd->rx_bd_haddr_lo); 9384 else 9385 /* Normal rx_bd entry. */ 9386 BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = " 9387 "0x%08X, flags = 0x%08X\n", idx, rxbd->rx_bd_haddr_hi, 9388 rxbd->rx_bd_haddr_lo, rxbd->rx_bd_len, 9389 rxbd->rx_bd_flags); 9390} 9391 9392 9393#ifdef BCE_JUMBO_HDRSPLIT 9394/****************************************************************************/ 9395/* Prints out a rx_bd structure in the page chain. */ 9396/* */ 9397/* Returns: */ 9398/* Nothing. */ 9399/****************************************************************************/ 9400static __attribute__ ((noinline)) void 9401bce_dump_pgbd(struct bce_softc *sc, int idx, struct rx_bd *pgbd) 9402{ 9403 if (idx > MAX_PG_BD) 9404 /* Index out of range. */ 9405 BCE_PRINTF("pg_bd[0x%04X]: Invalid pg_bd index!\n", idx); 9406 else if ((idx & USABLE_PG_BD_PER_PAGE) == USABLE_PG_BD_PER_PAGE) 9407 /* Page Chain page pointer. */ 9408 BCE_PRINTF("px_bd[0x%04X]: haddr = 0x%08X:%08X, chain page pointer\n", 9409 idx, pgbd->rx_bd_haddr_hi, pgbd->rx_bd_haddr_lo); 9410 else 9411 /* Normal rx_bd entry. */ 9412 BCE_PRINTF("pg_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = 0x%08X, " 9413 "flags = 0x%08X\n", idx, 9414 pgbd->rx_bd_haddr_hi, pgbd->rx_bd_haddr_lo, 9415 pgbd->rx_bd_len, pgbd->rx_bd_flags); 9416} 9417#endif 9418 9419 9420/****************************************************************************/ 9421/* Prints out a l2_fhdr structure. */ 9422/* */ 9423/* Returns: */ 9424/* Nothing. */ 9425/****************************************************************************/ 9426static __attribute__ ((noinline)) void 9427bce_dump_l2fhdr(struct bce_softc *sc, int idx, struct l2_fhdr *l2fhdr) 9428{ 9429 BCE_PRINTF("l2_fhdr[0x%04X]: status = 0x%b, " 9430 "pkt_len = %d, vlan = 0x%04x, ip_xsum/hdr_len = 0x%04X, " 9431 "tcp_udp_xsum = 0x%04X\n", idx, 9432 l2fhdr->l2_fhdr_status, BCE_L2FHDR_PRINTFB, 9433 l2fhdr->l2_fhdr_pkt_len, l2fhdr->l2_fhdr_vlan_tag, 9434 l2fhdr->l2_fhdr_ip_xsum, l2fhdr->l2_fhdr_tcp_udp_xsum); 9435} 9436 9437 9438/****************************************************************************/ 9439/* Prints out context memory info. (Only useful for CID 0 to 16.) */ 9440/* */ 9441/* Returns: */ 9442/* Nothing. */ 9443/****************************************************************************/ 9444static __attribute__ ((noinline)) void 9445bce_dump_ctx(struct bce_softc *sc, u16 cid) 9446{ 9447 if (cid > TX_CID) { 9448 BCE_PRINTF(" Unknown CID\n"); 9449 return; 9450 } 9451 9452 BCE_PRINTF( 9453 "----------------------------" 9454 " CTX Data " 9455 "----------------------------\n"); 9456 9457 BCE_PRINTF(" 0x%04X - (CID) Context ID\n", cid); 9458 9459 if (cid == RX_CID) { 9460 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_BDIDX) host rx " 9461 "producer index\n", 9462 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_HOST_BDIDX)); 9463 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_BSEQ) host " 9464 "byte sequence\n", CTX_RD(sc, GET_CID_ADDR(cid), 9465 BCE_L2CTX_RX_HOST_BSEQ)); 9466 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BSEQ) h/w byte sequence\n", 9467 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BSEQ)); 9468 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDHADDR_HI) h/w buffer " 9469 "descriptor address\n", 9470 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BDHADDR_HI)); 9471 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDHADDR_LO) h/w buffer " 9472 "descriptor address\n", 9473 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BDHADDR_LO)); 9474 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDIDX) h/w rx consumer " 9475 "index\n", CTX_RD(sc, GET_CID_ADDR(cid), 9476 BCE_L2CTX_RX_NX_BDIDX)); 9477 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_PG_BDIDX) host page " 9478 "producer index\n", CTX_RD(sc, GET_CID_ADDR(cid), 9479 BCE_L2CTX_RX_HOST_PG_BDIDX)); 9480 BCE_PRINTF(" 0x%08X - (L2CTX_RX_PG_BUF_SIZE) host rx_bd/page " 9481 "buffer size\n", CTX_RD(sc, GET_CID_ADDR(cid), 9482 BCE_L2CTX_RX_PG_BUF_SIZE)); 9483 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDHADDR_HI) h/w page " 9484 "chain address\n", CTX_RD(sc, GET_CID_ADDR(cid), 9485 BCE_L2CTX_RX_NX_PG_BDHADDR_HI)); 9486 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDHADDR_LO) h/w page " 9487 "chain address\n", CTX_RD(sc, GET_CID_ADDR(cid), 9488 BCE_L2CTX_RX_NX_PG_BDHADDR_LO)); 9489 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDIDX) h/w page " 9490 "consumer index\n", CTX_RD(sc, GET_CID_ADDR(cid), 9491 BCE_L2CTX_RX_NX_PG_BDIDX)); 9492 } else if (cid == TX_CID) { 9493 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 9494 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 9495 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TYPE_XI) ctx type\n", 9496 CTX_RD(sc, GET_CID_ADDR(cid), 9497 BCE_L2CTX_TX_TYPE_XI)); 9498 BCE_PRINTF(" 0x%08X - (L2CTX_CMD_TX_TYPE_XI) ctx " 9499 "cmd\n", CTX_RD(sc, GET_CID_ADDR(cid), 9500 BCE_L2CTX_TX_CMD_TYPE_XI)); 9501 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BDHADDR_HI_XI) " 9502 "h/w buffer descriptor address\n", 9503 CTX_RD(sc, GET_CID_ADDR(cid), 9504 BCE_L2CTX_TX_TBDR_BHADDR_HI_XI)); 9505 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BHADDR_LO_XI) " 9506 "h/w buffer descriptor address\n", 9507 CTX_RD(sc, GET_CID_ADDR(cid), 9508 BCE_L2CTX_TX_TBDR_BHADDR_LO_XI)); 9509 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BIDX_XI) " 9510 "host producer index\n", 9511 CTX_RD(sc, GET_CID_ADDR(cid), 9512 BCE_L2CTX_TX_HOST_BIDX_XI)); 9513 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BSEQ_XI) " 9514 "host byte sequence\n", 9515 CTX_RD(sc, GET_CID_ADDR(cid), 9516 BCE_L2CTX_TX_HOST_BSEQ_XI)); 9517 } else { 9518 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TYPE) ctx type\n", 9519 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_TX_TYPE)); 9520 BCE_PRINTF(" 0x%08X - (L2CTX_TX_CMD_TYPE) ctx cmd\n", 9521 CTX_RD(sc, GET_CID_ADDR(cid), 9522 BCE_L2CTX_TX_CMD_TYPE)); 9523 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BDHADDR_HI) " 9524 "h/w buffer descriptor address\n", 9525 CTX_RD(sc, GET_CID_ADDR(cid), 9526 BCE_L2CTX_TX_TBDR_BHADDR_HI)); 9527 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BHADDR_LO) " 9528 "h/w buffer descriptor address\n", 9529 CTX_RD(sc, GET_CID_ADDR(cid), 9530 BCE_L2CTX_TX_TBDR_BHADDR_LO)); 9531 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BIDX) host " 9532 "producer index\n", CTX_RD(sc, GET_CID_ADDR(cid), 9533 BCE_L2CTX_TX_HOST_BIDX)); 9534 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BSEQ) host byte " 9535 "sequence\n", CTX_RD(sc, GET_CID_ADDR(cid), 9536 BCE_L2CTX_TX_HOST_BSEQ)); 9537 } 9538 } 9539 9540 BCE_PRINTF( 9541 "----------------------------" 9542 " Raw CTX " 9543 "----------------------------\n"); 9544 9545 for (int i = 0x0; i < 0x300; i += 0x10) { 9546 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", i, 9547 CTX_RD(sc, GET_CID_ADDR(cid), i), 9548 CTX_RD(sc, GET_CID_ADDR(cid), i + 0x4), 9549 CTX_RD(sc, GET_CID_ADDR(cid), i + 0x8), 9550 CTX_RD(sc, GET_CID_ADDR(cid), i + 0xc)); 9551 } 9552 9553 9554 BCE_PRINTF( 9555 "----------------------------" 9556 "----------------" 9557 "----------------------------\n"); 9558} 9559 9560 9561/****************************************************************************/ 9562/* Prints out the FTQ data. */ 9563/* */ 9564/* Returns: */ 9565/* Nothing. */ 9566/****************************************************************************/ 9567static __attribute__ ((noinline)) void 9568bce_dump_ftqs(struct bce_softc *sc) 9569{ 9570 u32 cmd, ctl, cur_depth, max_depth, valid_cnt, val; 9571 9572 BCE_PRINTF( 9573 "----------------------------" 9574 " FTQ Data " 9575 "----------------------------\n"); 9576 9577 BCE_PRINTF(" FTQ Command Control Depth_Now " 9578 "Max_Depth Valid_Cnt \n"); 9579 BCE_PRINTF(" ------- ---------- ---------- ---------- " 9580 "---------- ----------\n"); 9581 9582 /* Setup the generic statistic counters for the FTQ valid count. */ 9583 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT << 24) | 9584 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT << 16) | 9585 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT << 8) | 9586 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT); 9587 REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val); 9588 9589 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT << 24) | 9590 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT << 16) | 9591 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT << 8) | 9592 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT); 9593 REG_WR(sc, BCE_HC_STAT_GEN_SEL_1, val); 9594 9595 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT << 24) | 9596 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT << 16) | 9597 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT << 8) | 9598 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT); 9599 REG_WR(sc, BCE_HC_STAT_GEN_SEL_2, val); 9600 9601 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT << 24) | 9602 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT << 16) | 9603 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT << 8) | 9604 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT); 9605 REG_WR(sc, BCE_HC_STAT_GEN_SEL_3, val); 9606 9607 /* Input queue to the Receive Lookup state machine */ 9608 cmd = REG_RD(sc, BCE_RLUP_FTQ_CMD); 9609 ctl = REG_RD(sc, BCE_RLUP_FTQ_CTL); 9610 cur_depth = (ctl & BCE_RLUP_FTQ_CTL_CUR_DEPTH) >> 22; 9611 max_depth = (ctl & BCE_RLUP_FTQ_CTL_MAX_DEPTH) >> 12; 9612 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0); 9613 BCE_PRINTF(" RLUP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9614 cmd, ctl, cur_depth, max_depth, valid_cnt); 9615 9616 /* Input queue to the Receive Processor */ 9617 cmd = REG_RD_IND(sc, BCE_RXP_FTQ_CMD); 9618 ctl = REG_RD_IND(sc, BCE_RXP_FTQ_CTL); 9619 cur_depth = (ctl & BCE_RXP_FTQ_CTL_CUR_DEPTH) >> 22; 9620 max_depth = (ctl & BCE_RXP_FTQ_CTL_MAX_DEPTH) >> 12; 9621 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1); 9622 BCE_PRINTF(" RXP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9623 cmd, ctl, cur_depth, max_depth, valid_cnt); 9624 9625 /* Input queue to the Recevie Processor */ 9626 cmd = REG_RD_IND(sc, BCE_RXP_CFTQ_CMD); 9627 ctl = REG_RD_IND(sc, BCE_RXP_CFTQ_CTL); 9628 cur_depth = (ctl & BCE_RXP_CFTQ_CTL_CUR_DEPTH) >> 22; 9629 max_depth = (ctl & BCE_RXP_CFTQ_CTL_MAX_DEPTH) >> 12; 9630 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2); 9631 BCE_PRINTF(" RXPC 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9632 cmd, ctl, cur_depth, max_depth, valid_cnt); 9633 9634 /* Input queue to the Receive Virtual to Physical state machine */ 9635 cmd = REG_RD(sc, BCE_RV2P_PFTQ_CMD); 9636 ctl = REG_RD(sc, BCE_RV2P_PFTQ_CTL); 9637 cur_depth = (ctl & BCE_RV2P_PFTQ_CTL_CUR_DEPTH) >> 22; 9638 max_depth = (ctl & BCE_RV2P_PFTQ_CTL_MAX_DEPTH) >> 12; 9639 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT3); 9640 BCE_PRINTF(" RV2PP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9641 cmd, ctl, cur_depth, max_depth, valid_cnt); 9642 9643 /* Input queue to the Recevie Virtual to Physical state machine */ 9644 cmd = REG_RD(sc, BCE_RV2P_MFTQ_CMD); 9645 ctl = REG_RD(sc, BCE_RV2P_MFTQ_CTL); 9646 cur_depth = (ctl & BCE_RV2P_MFTQ_CTL_CUR_DEPTH) >> 22; 9647 max_depth = (ctl & BCE_RV2P_MFTQ_CTL_MAX_DEPTH) >> 12; 9648 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT4); 9649 BCE_PRINTF(" RV2PM 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9650 cmd, ctl, cur_depth, max_depth, valid_cnt); 9651 9652 /* Input queue to the Receive Virtual to Physical state machine */ 9653 cmd = REG_RD(sc, BCE_RV2P_TFTQ_CMD); 9654 ctl = REG_RD(sc, BCE_RV2P_TFTQ_CTL); 9655 cur_depth = (ctl & BCE_RV2P_TFTQ_CTL_CUR_DEPTH) >> 22; 9656 max_depth = (ctl & BCE_RV2P_TFTQ_CTL_MAX_DEPTH) >> 12; 9657 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT5); 9658 BCE_PRINTF(" RV2PT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9659 cmd, ctl, cur_depth, max_depth, valid_cnt); 9660 9661 /* Input queue to the Receive DMA state machine */ 9662 cmd = REG_RD(sc, BCE_RDMA_FTQ_CMD); 9663 ctl = REG_RD(sc, BCE_RDMA_FTQ_CTL); 9664 cur_depth = (ctl & BCE_RDMA_FTQ_CTL_CUR_DEPTH) >> 22; 9665 max_depth = (ctl & BCE_RDMA_FTQ_CTL_MAX_DEPTH) >> 12; 9666 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT6); 9667 BCE_PRINTF(" RDMA 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9668 cmd, ctl, cur_depth, max_depth, valid_cnt); 9669 9670 /* Input queue to the Transmit Scheduler state machine */ 9671 cmd = REG_RD(sc, BCE_TSCH_FTQ_CMD); 9672 ctl = REG_RD(sc, BCE_TSCH_FTQ_CTL); 9673 cur_depth = (ctl & BCE_TSCH_FTQ_CTL_CUR_DEPTH) >> 22; 9674 max_depth = (ctl & BCE_TSCH_FTQ_CTL_MAX_DEPTH) >> 12; 9675 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT7); 9676 BCE_PRINTF(" TSCH 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9677 cmd, ctl, cur_depth, max_depth, valid_cnt); 9678 9679 /* Input queue to the Transmit Buffer Descriptor state machine */ 9680 cmd = REG_RD(sc, BCE_TBDR_FTQ_CMD); 9681 ctl = REG_RD(sc, BCE_TBDR_FTQ_CTL); 9682 cur_depth = (ctl & BCE_TBDR_FTQ_CTL_CUR_DEPTH) >> 22; 9683 max_depth = (ctl & BCE_TBDR_FTQ_CTL_MAX_DEPTH) >> 12; 9684 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT8); 9685 BCE_PRINTF(" TBDR 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9686 cmd, ctl, cur_depth, max_depth, valid_cnt); 9687 9688 /* Input queue to the Transmit Processor */ 9689 cmd = REG_RD_IND(sc, BCE_TXP_FTQ_CMD); 9690 ctl = REG_RD_IND(sc, BCE_TXP_FTQ_CTL); 9691 cur_depth = (ctl & BCE_TXP_FTQ_CTL_CUR_DEPTH) >> 22; 9692 max_depth = (ctl & BCE_TXP_FTQ_CTL_MAX_DEPTH) >> 12; 9693 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT9); 9694 BCE_PRINTF(" TXP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9695 cmd, ctl, cur_depth, max_depth, valid_cnt); 9696 9697 /* Input queue to the Transmit DMA state machine */ 9698 cmd = REG_RD(sc, BCE_TDMA_FTQ_CMD); 9699 ctl = REG_RD(sc, BCE_TDMA_FTQ_CTL); 9700 cur_depth = (ctl & BCE_TDMA_FTQ_CTL_CUR_DEPTH) >> 22; 9701 max_depth = (ctl & BCE_TDMA_FTQ_CTL_MAX_DEPTH) >> 12; 9702 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT10); 9703 BCE_PRINTF(" TDMA 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9704 cmd, ctl, cur_depth, max_depth, valid_cnt); 9705 9706 /* Input queue to the Transmit Patch-Up Processor */ 9707 cmd = REG_RD_IND(sc, BCE_TPAT_FTQ_CMD); 9708 ctl = REG_RD_IND(sc, BCE_TPAT_FTQ_CTL); 9709 cur_depth = (ctl & BCE_TPAT_FTQ_CTL_CUR_DEPTH) >> 22; 9710 max_depth = (ctl & BCE_TPAT_FTQ_CTL_MAX_DEPTH) >> 12; 9711 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT11); 9712 BCE_PRINTF(" TPAT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9713 cmd, ctl, cur_depth, max_depth, valid_cnt); 9714 9715 /* Input queue to the Transmit Assembler state machine */ 9716 cmd = REG_RD_IND(sc, BCE_TAS_FTQ_CMD); 9717 ctl = REG_RD_IND(sc, BCE_TAS_FTQ_CTL); 9718 cur_depth = (ctl & BCE_TAS_FTQ_CTL_CUR_DEPTH) >> 22; 9719 max_depth = (ctl & BCE_TAS_FTQ_CTL_MAX_DEPTH) >> 12; 9720 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT12); 9721 BCE_PRINTF(" TAS 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9722 cmd, ctl, cur_depth, max_depth, valid_cnt); 9723 9724 /* Input queue to the Completion Processor */ 9725 cmd = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CMD); 9726 ctl = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CTL); 9727 cur_depth = (ctl & BCE_COM_COMXQ_FTQ_CTL_CUR_DEPTH) >> 22; 9728 max_depth = (ctl & BCE_COM_COMXQ_FTQ_CTL_MAX_DEPTH) >> 12; 9729 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT13); 9730 BCE_PRINTF(" COMX 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9731 cmd, ctl, cur_depth, max_depth, valid_cnt); 9732 9733 /* Input queue to the Completion Processor */ 9734 cmd = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CMD); 9735 ctl = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CTL); 9736 cur_depth = (ctl & BCE_COM_COMTQ_FTQ_CTL_CUR_DEPTH) >> 22; 9737 max_depth = (ctl & BCE_COM_COMTQ_FTQ_CTL_MAX_DEPTH) >> 12; 9738 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT14); 9739 BCE_PRINTF(" COMT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9740 cmd, ctl, cur_depth, max_depth, valid_cnt); 9741 9742 /* Input queue to the Completion Processor */ 9743 cmd = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CMD); 9744 ctl = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CTL); 9745 cur_depth = (ctl & BCE_COM_COMQ_FTQ_CTL_CUR_DEPTH) >> 22; 9746 max_depth = (ctl & BCE_COM_COMQ_FTQ_CTL_MAX_DEPTH) >> 12; 9747 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT15); 9748 BCE_PRINTF(" COMX 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9749 cmd, ctl, cur_depth, max_depth, valid_cnt); 9750 9751 /* Setup the generic statistic counters for the FTQ valid count. */ 9752 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT << 16) | 9753 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT << 8) | 9754 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT); 9755 9756 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 9757 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) 9758 val = val | 9759 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCSQ_VALID_CNT_XI << 9760 24); 9761 REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val); 9762 9763 /* Input queue to the Management Control Processor */ 9764 cmd = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CMD); 9765 ctl = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CTL); 9766 cur_depth = (ctl & BCE_MCP_MCPQ_FTQ_CTL_CUR_DEPTH) >> 22; 9767 max_depth = (ctl & BCE_MCP_MCPQ_FTQ_CTL_MAX_DEPTH) >> 12; 9768 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0); 9769 BCE_PRINTF(" MCP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9770 cmd, ctl, cur_depth, max_depth, valid_cnt); 9771 9772 /* Input queue to the Command Processor */ 9773 cmd = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CMD); 9774 ctl = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CTL); 9775 cur_depth = (ctl & BCE_CP_CPQ_FTQ_CTL_CUR_DEPTH) >> 22; 9776 max_depth = (ctl & BCE_CP_CPQ_FTQ_CTL_MAX_DEPTH) >> 12; 9777 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1); 9778 BCE_PRINTF(" CP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9779 cmd, ctl, cur_depth, max_depth, valid_cnt); 9780 9781 /* Input queue to the Completion Scheduler state machine */ 9782 cmd = REG_RD(sc, BCE_CSCH_CH_FTQ_CMD); 9783 ctl = REG_RD(sc, BCE_CSCH_CH_FTQ_CTL); 9784 cur_depth = (ctl & BCE_CSCH_CH_FTQ_CTL_CUR_DEPTH) >> 22; 9785 max_depth = (ctl & BCE_CSCH_CH_FTQ_CTL_MAX_DEPTH) >> 12; 9786 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2); 9787 BCE_PRINTF(" CS 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9788 cmd, ctl, cur_depth, max_depth, valid_cnt); 9789 9790 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 9791 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 9792 /* Input queue to the RV2P Command Scheduler */ 9793 cmd = REG_RD(sc, BCE_RV2PCSR_FTQ_CMD); 9794 ctl = REG_RD(sc, BCE_RV2PCSR_FTQ_CTL); 9795 cur_depth = (ctl & 0xFFC00000) >> 22; 9796 max_depth = (ctl & 0x003FF000) >> 12; 9797 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT3); 9798 BCE_PRINTF(" RV2PCSR 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9799 cmd, ctl, cur_depth, max_depth, valid_cnt); 9800 } 9801 9802 BCE_PRINTF( 9803 "----------------------------" 9804 "----------------" 9805 "----------------------------\n"); 9806} 9807 9808 9809/****************************************************************************/ 9810/* Prints out the TX chain. */ 9811/* */ 9812/* Returns: */ 9813/* Nothing. */ 9814/****************************************************************************/ 9815static __attribute__ ((noinline)) void 9816bce_dump_tx_chain(struct bce_softc *sc, u16 tx_prod, int count) 9817{ 9818 struct tx_bd *txbd; 9819 9820 /* First some info about the tx_bd chain structure. */ 9821 BCE_PRINTF( 9822 "----------------------------" 9823 " tx_bd chain " 9824 "----------------------------\n"); 9825 9826 BCE_PRINTF("page size = 0x%08X, tx chain pages = 0x%08X\n", 9827 (u32) BCM_PAGE_SIZE, (u32) TX_PAGES); 9828 BCE_PRINTF("tx_bd per page = 0x%08X, usable tx_bd per page = 0x%08X\n", 9829 (u32) TOTAL_TX_BD_PER_PAGE, (u32) USABLE_TX_BD_PER_PAGE); 9830 BCE_PRINTF("total tx_bd = 0x%08X\n", (u32) TOTAL_TX_BD); 9831 9832 BCE_PRINTF( 9833 "----------------------------" 9834 " tx_bd data " 9835 "----------------------------\n"); 9836 9837 /* Now print out a decoded list of TX buffer descriptors. */ 9838 for (int i = 0; i < count; i++) { 9839 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)]; 9840 bce_dump_txbd(sc, tx_prod, txbd); 9841 tx_prod++; 9842 } 9843 9844 BCE_PRINTF( 9845 "----------------------------" 9846 "----------------" 9847 "----------------------------\n"); 9848} 9849 9850 9851/****************************************************************************/ 9852/* Prints out the RX chain. */ 9853/* */ 9854/* Returns: */ 9855/* Nothing. */ 9856/****************************************************************************/ 9857static __attribute__ ((noinline)) void 9858bce_dump_rx_bd_chain(struct bce_softc *sc, u16 rx_prod, int count) 9859{ 9860 struct rx_bd *rxbd; 9861 9862 /* First some info about the rx_bd chain structure. */ 9863 BCE_PRINTF( 9864 "----------------------------" 9865 " rx_bd chain " 9866 "----------------------------\n"); 9867 9868 BCE_PRINTF("page size = 0x%08X, rx chain pages = 0x%08X\n", 9869 (u32) BCM_PAGE_SIZE, (u32) RX_PAGES); 9870 9871 BCE_PRINTF("rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n", 9872 (u32) TOTAL_RX_BD_PER_PAGE, (u32) USABLE_RX_BD_PER_PAGE); 9873 9874 BCE_PRINTF("total rx_bd = 0x%08X\n", (u32) TOTAL_RX_BD); 9875 9876 BCE_PRINTF( 9877 "----------------------------" 9878 " rx_bd data " 9879 "----------------------------\n"); 9880 9881 /* Now print out the rx_bd's themselves. */ 9882 for (int i = 0; i < count; i++) { 9883 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)]; 9884 bce_dump_rxbd(sc, rx_prod, rxbd); 9885 rx_prod = RX_CHAIN_IDX(rx_prod + 1); 9886 } 9887 9888 BCE_PRINTF( 9889 "----------------------------" 9890 "----------------" 9891 "----------------------------\n"); 9892} 9893 9894 9895#ifdef BCE_JUMBO_HDRSPLIT 9896/****************************************************************************/ 9897/* Prints out the page chain. */ 9898/* */ 9899/* Returns: */ 9900/* Nothing. */ 9901/****************************************************************************/ 9902static __attribute__ ((noinline)) void 9903bce_dump_pg_chain(struct bce_softc *sc, u16 pg_prod, int count) 9904{ 9905 struct rx_bd *pgbd; 9906 9907 /* First some info about the page chain structure. */ 9908 BCE_PRINTF( 9909 "----------------------------" 9910 " page chain " 9911 "----------------------------\n"); 9912 9913 BCE_PRINTF("page size = 0x%08X, pg chain pages = 0x%08X\n", 9914 (u32) BCM_PAGE_SIZE, (u32) PG_PAGES); 9915 9916 BCE_PRINTF("rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n", 9917 (u32) TOTAL_PG_BD_PER_PAGE, (u32) USABLE_PG_BD_PER_PAGE); 9918 9919 BCE_PRINTF("total rx_bd = 0x%08X, max_pg_bd = 0x%08X\n", 9920 (u32) TOTAL_PG_BD, (u32) MAX_PG_BD); 9921 9922 BCE_PRINTF( 9923 "----------------------------" 9924 " page data " 9925 "----------------------------\n"); 9926 9927 /* Now print out the rx_bd's themselves. */ 9928 for (int i = 0; i < count; i++) { 9929 pgbd = &sc->pg_bd_chain[PG_PAGE(pg_prod)][PG_IDX(pg_prod)]; 9930 bce_dump_pgbd(sc, pg_prod, pgbd); 9931 pg_prod = PG_CHAIN_IDX(pg_prod + 1); 9932 } 9933 9934 BCE_PRINTF( 9935 "----------------------------" 9936 "----------------" 9937 "----------------------------\n"); 9938} 9939#endif 9940 9941 9942#define BCE_PRINT_RX_CONS(arg) \ 9943if (sblk->status_rx_quick_consumer_index##arg) \ 9944 BCE_PRINTF("0x%04X(0x%04X) - rx_quick_consumer_index%d\n", \ 9945 sblk->status_rx_quick_consumer_index##arg, (u16) \ 9946 RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index##arg), \ 9947 arg); 9948 9949 9950#define BCE_PRINT_TX_CONS(arg) \ 9951if (sblk->status_tx_quick_consumer_index##arg) \ 9952 BCE_PRINTF("0x%04X(0x%04X) - tx_quick_consumer_index%d\n", \ 9953 sblk->status_tx_quick_consumer_index##arg, (u16) \ 9954 TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index##arg), \ 9955 arg); 9956 9957/****************************************************************************/ 9958/* Prints out the status block from host memory. */ 9959/* */ 9960/* Returns: */ 9961/* Nothing. */ 9962/****************************************************************************/ 9963static __attribute__ ((noinline)) void 9964bce_dump_status_block(struct bce_softc *sc) 9965{ 9966 struct status_block *sblk; 9967 9968 sblk = sc->status_block; 9969 9970 BCE_PRINTF( 9971 "----------------------------" 9972 " Status Block " 9973 "----------------------------\n"); 9974 9975 /* Theses indices are used for normal L2 drivers. */ 9976 BCE_PRINTF(" 0x%08X - attn_bits\n", 9977 sblk->status_attn_bits); 9978 9979 BCE_PRINTF(" 0x%08X - attn_bits_ack\n", 9980 sblk->status_attn_bits_ack); 9981 9982 BCE_PRINT_RX_CONS(0); 9983 BCE_PRINT_TX_CONS(0) 9984 9985 BCE_PRINTF(" 0x%04X - status_idx\n", sblk->status_idx); 9986 9987 /* Theses indices are not used for normal L2 drivers. */ 9988 BCE_PRINT_RX_CONS(1); BCE_PRINT_RX_CONS(2); BCE_PRINT_RX_CONS(3); 9989 BCE_PRINT_RX_CONS(4); BCE_PRINT_RX_CONS(5); BCE_PRINT_RX_CONS(6); 9990 BCE_PRINT_RX_CONS(7); BCE_PRINT_RX_CONS(8); BCE_PRINT_RX_CONS(9); 9991 BCE_PRINT_RX_CONS(10); BCE_PRINT_RX_CONS(11); BCE_PRINT_RX_CONS(12); 9992 BCE_PRINT_RX_CONS(13); BCE_PRINT_RX_CONS(14); BCE_PRINT_RX_CONS(15); 9993 9994 BCE_PRINT_TX_CONS(1); BCE_PRINT_TX_CONS(2); BCE_PRINT_TX_CONS(3); 9995 9996 if (sblk->status_completion_producer_index || 9997 sblk->status_cmd_consumer_index) 9998 BCE_PRINTF("com_prod = 0x%08X, cmd_cons = 0x%08X\n", 9999 sblk->status_completion_producer_index, 10000 sblk->status_cmd_consumer_index); 10001 10002 BCE_PRINTF( 10003 "----------------------------" 10004 "----------------" 10005 "----------------------------\n"); 10006} 10007 10008 10009#define BCE_PRINT_64BIT_STAT(arg) \ 10010if (sblk->arg##_lo || sblk->arg##_hi) \ 10011 BCE_PRINTF("0x%08X:%08X : %s\n", sblk->arg##_hi, \ 10012 sblk->arg##_lo, #arg); 10013 10014#define BCE_PRINT_32BIT_STAT(arg) \ 10015if (sblk->arg) \ 10016 BCE_PRINTF(" 0x%08X : %s\n", \ 10017 sblk->arg, #arg); 10018 10019/****************************************************************************/ 10020/* Prints out the statistics block from host memory. */ 10021/* */ 10022/* Returns: */ 10023/* Nothing. */ 10024/****************************************************************************/ 10025static __attribute__ ((noinline)) void 10026bce_dump_stats_block(struct bce_softc *sc) 10027{ 10028 struct statistics_block *sblk; 10029 10030 sblk = sc->stats_block; 10031 10032 BCE_PRINTF( 10033 "---------------" 10034 " Stats Block (All Stats Not Shown Are 0) " 10035 "---------------\n"); 10036 10037 BCE_PRINT_64BIT_STAT(stat_IfHCInOctets); 10038 BCE_PRINT_64BIT_STAT(stat_IfHCInBadOctets); 10039 BCE_PRINT_64BIT_STAT(stat_IfHCOutOctets); 10040 BCE_PRINT_64BIT_STAT(stat_IfHCOutBadOctets); 10041 BCE_PRINT_64BIT_STAT(stat_IfHCInUcastPkts); 10042 BCE_PRINT_64BIT_STAT(stat_IfHCInBroadcastPkts); 10043 BCE_PRINT_64BIT_STAT(stat_IfHCInMulticastPkts); 10044 BCE_PRINT_64BIT_STAT(stat_IfHCOutUcastPkts); 10045 BCE_PRINT_64BIT_STAT(stat_IfHCOutBroadcastPkts); 10046 BCE_PRINT_64BIT_STAT(stat_IfHCOutMulticastPkts); 10047 BCE_PRINT_32BIT_STAT( 10048 stat_emac_tx_stat_dot3statsinternalmactransmiterrors); 10049 BCE_PRINT_32BIT_STAT(stat_Dot3StatsCarrierSenseErrors); 10050 BCE_PRINT_32BIT_STAT(stat_Dot3StatsFCSErrors); 10051 BCE_PRINT_32BIT_STAT(stat_Dot3StatsAlignmentErrors); 10052 BCE_PRINT_32BIT_STAT(stat_Dot3StatsSingleCollisionFrames); 10053 BCE_PRINT_32BIT_STAT(stat_Dot3StatsMultipleCollisionFrames); 10054 BCE_PRINT_32BIT_STAT(stat_Dot3StatsDeferredTransmissions); 10055 BCE_PRINT_32BIT_STAT(stat_Dot3StatsExcessiveCollisions); 10056 BCE_PRINT_32BIT_STAT(stat_Dot3StatsLateCollisions); 10057 BCE_PRINT_32BIT_STAT(stat_EtherStatsCollisions); 10058 BCE_PRINT_32BIT_STAT(stat_EtherStatsFragments); 10059 BCE_PRINT_32BIT_STAT(stat_EtherStatsJabbers); 10060 BCE_PRINT_32BIT_STAT(stat_EtherStatsUndersizePkts); 10061 BCE_PRINT_32BIT_STAT(stat_EtherStatsOversizePkts); 10062 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx64Octets); 10063 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx65Octetsto127Octets); 10064 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx128Octetsto255Octets); 10065 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx256Octetsto511Octets); 10066 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx512Octetsto1023Octets); 10067 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx1024Octetsto1522Octets); 10068 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx1523Octetsto9022Octets); 10069 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx64Octets); 10070 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx65Octetsto127Octets); 10071 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx128Octetsto255Octets); 10072 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx256Octetsto511Octets); 10073 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx512Octetsto1023Octets); 10074 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx1024Octetsto1522Octets); 10075 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx1523Octetsto9022Octets); 10076 BCE_PRINT_32BIT_STAT(stat_XonPauseFramesReceived); 10077 BCE_PRINT_32BIT_STAT(stat_XoffPauseFramesReceived); 10078 BCE_PRINT_32BIT_STAT(stat_OutXonSent); 10079 BCE_PRINT_32BIT_STAT(stat_OutXoffSent); 10080 BCE_PRINT_32BIT_STAT(stat_FlowControlDone); 10081 BCE_PRINT_32BIT_STAT(stat_MacControlFramesReceived); 10082 BCE_PRINT_32BIT_STAT(stat_XoffStateEntered); 10083 BCE_PRINT_32BIT_STAT(stat_IfInFramesL2FilterDiscards); 10084 BCE_PRINT_32BIT_STAT(stat_IfInRuleCheckerDiscards); 10085 BCE_PRINT_32BIT_STAT(stat_IfInFTQDiscards); 10086 BCE_PRINT_32BIT_STAT(stat_IfInMBUFDiscards); 10087 BCE_PRINT_32BIT_STAT(stat_IfInRuleCheckerP4Hit); 10088 BCE_PRINT_32BIT_STAT(stat_CatchupInRuleCheckerDiscards); 10089 BCE_PRINT_32BIT_STAT(stat_CatchupInFTQDiscards); 10090 BCE_PRINT_32BIT_STAT(stat_CatchupInMBUFDiscards); 10091 BCE_PRINT_32BIT_STAT(stat_CatchupInRuleCheckerP4Hit); 10092 10093 BCE_PRINTF( 10094 "----------------------------" 10095 "----------------" 10096 "----------------------------\n"); 10097} 10098 10099 10100/****************************************************************************/ 10101/* Prints out a summary of the driver state. */ 10102/* */ 10103/* Returns: */ 10104/* Nothing. */ 10105/****************************************************************************/ 10106static __attribute__ ((noinline)) void 10107bce_dump_driver_state(struct bce_softc *sc) 10108{ 10109 u32 val_hi, val_lo; 10110 10111 BCE_PRINTF( 10112 "-----------------------------" 10113 " Driver State " 10114 "-----------------------------\n"); 10115 10116 val_hi = BCE_ADDR_HI(sc); 10117 val_lo = BCE_ADDR_LO(sc); 10118 BCE_PRINTF("0x%08X:%08X - (sc) driver softc structure virtual " 10119 "address\n", val_hi, val_lo); 10120 10121 val_hi = BCE_ADDR_HI(sc->bce_vhandle); 10122 val_lo = BCE_ADDR_LO(sc->bce_vhandle); 10123 BCE_PRINTF("0x%08X:%08X - (sc->bce_vhandle) PCI BAR virtual " 10124 "address\n", val_hi, val_lo); 10125 10126 val_hi = BCE_ADDR_HI(sc->status_block); 10127 val_lo = BCE_ADDR_LO(sc->status_block); 10128 BCE_PRINTF("0x%08X:%08X - (sc->status_block) status block " 10129 "virtual address\n", val_hi, val_lo); 10130 10131 val_hi = BCE_ADDR_HI(sc->stats_block); 10132 val_lo = BCE_ADDR_LO(sc->stats_block); 10133 BCE_PRINTF("0x%08X:%08X - (sc->stats_block) statistics block " 10134 "virtual address\n", val_hi, val_lo); 10135 10136 val_hi = BCE_ADDR_HI(sc->tx_bd_chain); 10137 val_lo = BCE_ADDR_LO(sc->tx_bd_chain); 10138 BCE_PRINTF("0x%08X:%08X - (sc->tx_bd_chain) tx_bd chain " 10139 "virtual adddress\n", val_hi, val_lo); 10140 10141 val_hi = BCE_ADDR_HI(sc->rx_bd_chain); 10142 val_lo = BCE_ADDR_LO(sc->rx_bd_chain); 10143 BCE_PRINTF("0x%08X:%08X - (sc->rx_bd_chain) rx_bd chain " 10144 "virtual address\n", val_hi, val_lo); 10145 10146#ifdef BCE_JUMBO_HDRSPLIT 10147 val_hi = BCE_ADDR_HI(sc->pg_bd_chain); 10148 val_lo = BCE_ADDR_LO(sc->pg_bd_chain); 10149 BCE_PRINTF("0x%08X:%08X - (sc->pg_bd_chain) page chain " 10150 "virtual address\n", val_hi, val_lo); 10151#endif 10152 10153 val_hi = BCE_ADDR_HI(sc->tx_mbuf_ptr); 10154 val_lo = BCE_ADDR_LO(sc->tx_mbuf_ptr); 10155 BCE_PRINTF("0x%08X:%08X - (sc->tx_mbuf_ptr) tx mbuf chain " 10156 "virtual address\n", val_hi, val_lo); 10157 10158 val_hi = BCE_ADDR_HI(sc->rx_mbuf_ptr); 10159 val_lo = BCE_ADDR_LO(sc->rx_mbuf_ptr); 10160 BCE_PRINTF("0x%08X:%08X - (sc->rx_mbuf_ptr) rx mbuf chain " 10161 "virtual address\n", val_hi, val_lo); 10162 10163#ifdef BCE_JUMBO_HDRSPLIT 10164 val_hi = BCE_ADDR_HI(sc->pg_mbuf_ptr); 10165 val_lo = BCE_ADDR_LO(sc->pg_mbuf_ptr); 10166 BCE_PRINTF("0x%08X:%08X - (sc->pg_mbuf_ptr) page mbuf chain " 10167 "virtual address\n", val_hi, val_lo); 10168#endif 10169 10170 BCE_PRINTF(" 0x%08X - (sc->interrupts_generated) " 10171 "h/w intrs\n", sc->interrupts_generated); 10172 10173 BCE_PRINTF(" 0x%08X - (sc->interrupts_rx) " 10174 "rx interrupts handled\n", sc->interrupts_rx); 10175 10176 BCE_PRINTF(" 0x%08X - (sc->interrupts_tx) " 10177 "tx interrupts handled\n", sc->interrupts_tx); 10178 10179 BCE_PRINTF(" 0x%08X - (sc->phy_interrupts) " 10180 "phy interrupts handled\n", sc->phy_interrupts); 10181 10182 BCE_PRINTF(" 0x%08X - (sc->last_status_idx) " 10183 "status block index\n", sc->last_status_idx); 10184 10185 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->tx_prod) tx producer " 10186 "index\n", sc->tx_prod, (u16) TX_CHAIN_IDX(sc->tx_prod)); 10187 10188 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->tx_cons) tx consumer " 10189 "index\n", sc->tx_cons, (u16) TX_CHAIN_IDX(sc->tx_cons)); 10190 10191 BCE_PRINTF(" 0x%08X - (sc->tx_prod_bseq) tx producer " 10192 "byte seq index\n", sc->tx_prod_bseq); 10193 10194 BCE_PRINTF(" 0x%08X - (sc->debug_tx_mbuf_alloc) tx " 10195 "mbufs allocated\n", sc->debug_tx_mbuf_alloc); 10196 10197 BCE_PRINTF(" 0x%08X - (sc->used_tx_bd) used " 10198 "tx_bd's\n", sc->used_tx_bd); 10199 10200 BCE_PRINTF("0x%08X/%08X - (sc->tx_hi_watermark) tx hi " 10201 "watermark\n", sc->tx_hi_watermark, sc->max_tx_bd); 10202 10203 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->rx_prod) rx producer " 10204 "index\n", sc->rx_prod, (u16) RX_CHAIN_IDX(sc->rx_prod)); 10205 10206 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->rx_cons) rx consumer " 10207 "index\n", sc->rx_cons, (u16) RX_CHAIN_IDX(sc->rx_cons)); 10208 10209 BCE_PRINTF(" 0x%08X - (sc->rx_prod_bseq) rx producer " 10210 "byte seq index\n", sc->rx_prod_bseq); 10211 10212 BCE_PRINTF(" 0x%08X - (sc->debug_rx_mbuf_alloc) rx " 10213 "mbufs allocated\n", sc->debug_rx_mbuf_alloc); 10214 10215 BCE_PRINTF(" 0x%08X - (sc->free_rx_bd) free " 10216 "rx_bd's\n", sc->free_rx_bd); 10217 10218#ifdef BCE_JUMBO_HDRSPLIT 10219 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->pg_prod) page producer " 10220 "index\n", sc->pg_prod, (u16) PG_CHAIN_IDX(sc->pg_prod)); 10221 10222 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->pg_cons) page consumer " 10223 "index\n", sc->pg_cons, (u16) PG_CHAIN_IDX(sc->pg_cons)); 10224 10225 BCE_PRINTF(" 0x%08X - (sc->debug_pg_mbuf_alloc) page " 10226 "mbufs allocated\n", sc->debug_pg_mbuf_alloc); 10227 10228 BCE_PRINTF(" 0x%08X - (sc->free_pg_bd) free page " 10229 "rx_bd's\n", sc->free_pg_bd); 10230 10231 BCE_PRINTF("0x%08X/%08X - (sc->pg_low_watermark) page low " 10232 "watermark\n", sc->pg_low_watermark, sc->max_pg_bd); 10233#endif 10234 10235 BCE_PRINTF(" 0x%08X - (sc->mbuf_alloc_failed_count) " 10236 "mbuf alloc failures\n", sc->mbuf_alloc_failed_count); 10237 10238 BCE_PRINTF(" 0x%08X - (sc->bce_flags) " 10239 "bce mac flags\n", sc->bce_flags); 10240 10241 BCE_PRINTF(" 0x%08X - (sc->bce_phy_flags) " 10242 "bce phy flags\n", sc->bce_phy_flags); 10243 10244 BCE_PRINTF( 10245 "----------------------------" 10246 "----------------" 10247 "----------------------------\n"); 10248} 10249 10250 10251/****************************************************************************/ 10252/* Prints out the hardware state through a summary of important register, */ 10253/* followed by a complete register dump. */ 10254/* */ 10255/* Returns: */ 10256/* Nothing. */ 10257/****************************************************************************/ 10258static __attribute__ ((noinline)) void 10259bce_dump_hw_state(struct bce_softc *sc) 10260{ 10261 u32 val; 10262 10263 BCE_PRINTF( 10264 "----------------------------" 10265 " Hardware State " 10266 "----------------------------\n"); 10267 10268 BCE_PRINTF("%s - bootcode version\n", sc->bce_bc_ver); 10269 10270 val = REG_RD(sc, BCE_MISC_ENABLE_STATUS_BITS); 10271 BCE_PRINTF("0x%08X - (0x%06X) misc_enable_status_bits\n", 10272 val, BCE_MISC_ENABLE_STATUS_BITS); 10273 10274 val = REG_RD(sc, BCE_DMA_STATUS); 10275 BCE_PRINTF("0x%08X - (0x%06X) dma_status\n", 10276 val, BCE_DMA_STATUS); 10277 10278 val = REG_RD(sc, BCE_CTX_STATUS); 10279 BCE_PRINTF("0x%08X - (0x%06X) ctx_status\n", 10280 val, BCE_CTX_STATUS); 10281 10282 val = REG_RD(sc, BCE_EMAC_STATUS); 10283 BCE_PRINTF("0x%08X - (0x%06X) emac_status\n", 10284 val, BCE_EMAC_STATUS); 10285 10286 val = REG_RD(sc, BCE_RPM_STATUS); 10287 BCE_PRINTF("0x%08X - (0x%06X) rpm_status\n", 10288 val, BCE_RPM_STATUS); 10289 10290 /* ToDo: Create a #define for this constant. */ 10291 val = REG_RD(sc, 0x2004); 10292 BCE_PRINTF("0x%08X - (0x%06X) rlup_status\n", 10293 val, 0x2004); 10294 10295 val = REG_RD(sc, BCE_RV2P_STATUS); 10296 BCE_PRINTF("0x%08X - (0x%06X) rv2p_status\n", 10297 val, BCE_RV2P_STATUS); 10298 10299 /* ToDo: Create a #define for this constant. */ 10300 val = REG_RD(sc, 0x2c04); 10301 BCE_PRINTF("0x%08X - (0x%06X) rdma_status\n", 10302 val, 0x2c04); 10303 10304 val = REG_RD(sc, BCE_TBDR_STATUS); 10305 BCE_PRINTF("0x%08X - (0x%06X) tbdr_status\n", 10306 val, BCE_TBDR_STATUS); 10307 10308 val = REG_RD(sc, BCE_TDMA_STATUS); 10309 BCE_PRINTF("0x%08X - (0x%06X) tdma_status\n", 10310 val, BCE_TDMA_STATUS); 10311 10312 val = REG_RD(sc, BCE_HC_STATUS); 10313 BCE_PRINTF("0x%08X - (0x%06X) hc_status\n", 10314 val, BCE_HC_STATUS); 10315 10316 val = REG_RD_IND(sc, BCE_TXP_CPU_STATE); 10317 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n", 10318 val, BCE_TXP_CPU_STATE); 10319 10320 val = REG_RD_IND(sc, BCE_TPAT_CPU_STATE); 10321 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n", 10322 val, BCE_TPAT_CPU_STATE); 10323 10324 val = REG_RD_IND(sc, BCE_RXP_CPU_STATE); 10325 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n", 10326 val, BCE_RXP_CPU_STATE); 10327 10328 val = REG_RD_IND(sc, BCE_COM_CPU_STATE); 10329 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n", 10330 val, BCE_COM_CPU_STATE); 10331 10332 val = REG_RD_IND(sc, BCE_MCP_CPU_STATE); 10333 BCE_PRINTF("0x%08X - (0x%06X) mcp_cpu_state\n", 10334 val, BCE_MCP_CPU_STATE); 10335 10336 val = REG_RD_IND(sc, BCE_CP_CPU_STATE); 10337 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n", 10338 val, BCE_CP_CPU_STATE); 10339 10340 BCE_PRINTF( 10341 "----------------------------" 10342 "----------------" 10343 "----------------------------\n"); 10344 10345 BCE_PRINTF( 10346 "----------------------------" 10347 " Register Dump " 10348 "----------------------------\n"); 10349 10350 for (int i = 0x400; i < 0x8000; i += 0x10) { 10351 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 10352 i, REG_RD(sc, i), REG_RD(sc, i + 0x4), 10353 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC)); 10354 } 10355 10356 BCE_PRINTF( 10357 "----------------------------" 10358 "----------------" 10359 "----------------------------\n"); 10360} 10361 10362 10363/****************************************************************************/ 10364/* Prints out the mailbox queue registers. */ 10365/* */ 10366/* Returns: */ 10367/* Nothing. */ 10368/****************************************************************************/ 10369static __attribute__ ((noinline)) void 10370bce_dump_mq_regs(struct bce_softc *sc) 10371{ 10372 BCE_PRINTF( 10373 "----------------------------" 10374 " MQ Regs " 10375 "----------------------------\n"); 10376 10377 BCE_PRINTF( 10378 "----------------------------" 10379 "----------------" 10380 "----------------------------\n"); 10381 10382 for (int i = 0x3c00; i < 0x4000; i += 0x10) { 10383 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 10384 i, REG_RD(sc, i), REG_RD(sc, i + 0x4), 10385 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC)); 10386 } 10387 10388 BCE_PRINTF( 10389 "----------------------------" 10390 "----------------" 10391 "----------------------------\n"); 10392} 10393 10394 10395/****************************************************************************/ 10396/* Prints out the bootcode state. */ 10397/* */ 10398/* Returns: */ 10399/* Nothing. */ 10400/****************************************************************************/ 10401static __attribute__ ((noinline)) void 10402bce_dump_bc_state(struct bce_softc *sc) 10403{ 10404 u32 val; 10405 10406 BCE_PRINTF( 10407 "----------------------------" 10408 " Bootcode State " 10409 "----------------------------\n"); 10410 10411 BCE_PRINTF("%s - bootcode version\n", sc->bce_bc_ver); 10412 10413 val = bce_shmem_rd(sc, BCE_BC_RESET_TYPE); 10414 BCE_PRINTF("0x%08X - (0x%06X) reset_type\n", 10415 val, BCE_BC_RESET_TYPE); 10416 10417 val = bce_shmem_rd(sc, BCE_BC_STATE); 10418 BCE_PRINTF("0x%08X - (0x%06X) state\n", 10419 val, BCE_BC_STATE); 10420 10421 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); 10422 BCE_PRINTF("0x%08X - (0x%06X) condition\n", 10423 val, BCE_BC_STATE_CONDITION); 10424 10425 val = bce_shmem_rd(sc, BCE_BC_STATE_DEBUG_CMD); 10426 BCE_PRINTF("0x%08X - (0x%06X) debug_cmd\n", 10427 val, BCE_BC_STATE_DEBUG_CMD); 10428 10429 BCE_PRINTF( 10430 "----------------------------" 10431 "----------------" 10432 "----------------------------\n"); 10433} 10434 10435 10436/****************************************************************************/ 10437/* Prints out the TXP processor state. */ 10438/* */ 10439/* Returns: */ 10440/* Nothing. */ 10441/****************************************************************************/ 10442static __attribute__ ((noinline)) void 10443bce_dump_txp_state(struct bce_softc *sc, int regs) 10444{ 10445 u32 val; 10446 u32 fw_version[3]; 10447 10448 BCE_PRINTF( 10449 "----------------------------" 10450 " TXP State " 10451 "----------------------------\n"); 10452 10453 for (int i = 0; i < 3; i++) 10454 fw_version[i] = htonl(REG_RD_IND(sc, 10455 (BCE_TXP_SCRATCH + 0x10 + i * 4))); 10456 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 10457 10458 val = REG_RD_IND(sc, BCE_TXP_CPU_MODE); 10459 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_mode\n", 10460 val, BCE_TXP_CPU_MODE); 10461 10462 val = REG_RD_IND(sc, BCE_TXP_CPU_STATE); 10463 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n", 10464 val, BCE_TXP_CPU_STATE); 10465 10466 val = REG_RD_IND(sc, BCE_TXP_CPU_EVENT_MASK); 10467 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_event_mask\n", 10468 val, BCE_TXP_CPU_EVENT_MASK); 10469 10470 if (regs) { 10471 BCE_PRINTF( 10472 "----------------------------" 10473 " Register Dump " 10474 "----------------------------\n"); 10475 10476 for (int i = BCE_TXP_CPU_MODE; i < 0x68000; i += 0x10) { 10477 /* Skip the big blank spaces */ 10478 if (i < 0x454000 && i > 0x5ffff) 10479 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 10480 "0x%08X 0x%08X\n", i, 10481 REG_RD_IND(sc, i), 10482 REG_RD_IND(sc, i + 0x4), 10483 REG_RD_IND(sc, i + 0x8), 10484 REG_RD_IND(sc, i + 0xC)); 10485 } 10486 } 10487 10488 BCE_PRINTF( 10489 "----------------------------" 10490 "----------------" 10491 "----------------------------\n"); 10492} 10493 10494 10495/****************************************************************************/ 10496/* Prints out the RXP processor state. */ 10497/* */ 10498/* Returns: */ 10499/* Nothing. */ 10500/****************************************************************************/ 10501static __attribute__ ((noinline)) void 10502bce_dump_rxp_state(struct bce_softc *sc, int regs) 10503{ 10504 u32 val; 10505 u32 fw_version[3]; 10506 10507 BCE_PRINTF( 10508 "----------------------------" 10509 " RXP State " 10510 "----------------------------\n"); 10511 10512 for (int i = 0; i < 3; i++) 10513 fw_version[i] = htonl(REG_RD_IND(sc, 10514 (BCE_RXP_SCRATCH + 0x10 + i * 4))); 10515 10516 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 10517 10518 val = REG_RD_IND(sc, BCE_RXP_CPU_MODE); 10519 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_mode\n", 10520 val, BCE_RXP_CPU_MODE); 10521 10522 val = REG_RD_IND(sc, BCE_RXP_CPU_STATE); 10523 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n", 10524 val, BCE_RXP_CPU_STATE); 10525 10526 val = REG_RD_IND(sc, BCE_RXP_CPU_EVENT_MASK); 10527 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_event_mask\n", 10528 val, BCE_RXP_CPU_EVENT_MASK); 10529 10530 if (regs) { 10531 BCE_PRINTF( 10532 "----------------------------" 10533 " Register Dump " 10534 "----------------------------\n"); 10535 10536 for (int i = BCE_RXP_CPU_MODE; i < 0xe8fff; i += 0x10) { 10537 /* Skip the big blank sapces */ 10538 if (i < 0xc5400 && i > 0xdffff) 10539 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 10540 "0x%08X 0x%08X\n", i, 10541 REG_RD_IND(sc, i), 10542 REG_RD_IND(sc, i + 0x4), 10543 REG_RD_IND(sc, i + 0x8), 10544 REG_RD_IND(sc, i + 0xC)); 10545 } 10546 } 10547 10548 BCE_PRINTF( 10549 "----------------------------" 10550 "----------------" 10551 "----------------------------\n"); 10552} 10553 10554 10555/****************************************************************************/ 10556/* Prints out the TPAT processor state. */ 10557/* */ 10558/* Returns: */ 10559/* Nothing. */ 10560/****************************************************************************/ 10561static __attribute__ ((noinline)) void 10562bce_dump_tpat_state(struct bce_softc *sc, int regs) 10563{ 10564 u32 val; 10565 u32 fw_version[3]; 10566 10567 BCE_PRINTF( 10568 "----------------------------" 10569 " TPAT State " 10570 "----------------------------\n"); 10571 10572 for (int i = 0; i < 3; i++) 10573 fw_version[i] = htonl(REG_RD_IND(sc, 10574 (BCE_TPAT_SCRATCH + 0x410 + i * 4))); 10575 10576 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 10577 10578 val = REG_RD_IND(sc, BCE_TPAT_CPU_MODE); 10579 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_mode\n", 10580 val, BCE_TPAT_CPU_MODE); 10581 10582 val = REG_RD_IND(sc, BCE_TPAT_CPU_STATE); 10583 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n", 10584 val, BCE_TPAT_CPU_STATE); 10585 10586 val = REG_RD_IND(sc, BCE_TPAT_CPU_EVENT_MASK); 10587 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_event_mask\n", 10588 val, BCE_TPAT_CPU_EVENT_MASK); 10589 10590 if (regs) { 10591 BCE_PRINTF( 10592 "----------------------------" 10593 " Register Dump " 10594 "----------------------------\n"); 10595 10596 for (int i = BCE_TPAT_CPU_MODE; i < 0xa3fff; i += 0x10) { 10597 /* Skip the big blank spaces */ 10598 if (i < 0x854000 && i > 0x9ffff) 10599 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 10600 "0x%08X 0x%08X\n", i, 10601 REG_RD_IND(sc, i), 10602 REG_RD_IND(sc, i + 0x4), 10603 REG_RD_IND(sc, i + 0x8), 10604 REG_RD_IND(sc, i + 0xC)); 10605 } 10606 } 10607 10608 BCE_PRINTF( 10609 "----------------------------" 10610 "----------------" 10611 "----------------------------\n"); 10612} 10613 10614 10615/****************************************************************************/ 10616/* Prints out the Command Procesor (CP) state. */ 10617/* */ 10618/* Returns: */ 10619/* Nothing. */ 10620/****************************************************************************/ 10621static __attribute__ ((noinline)) void 10622bce_dump_cp_state(struct bce_softc *sc, int regs) 10623{ 10624 u32 val; 10625 u32 fw_version[3]; 10626 10627 BCE_PRINTF( 10628 "----------------------------" 10629 " CP State " 10630 "----------------------------\n"); 10631 10632 for (int i = 0; i < 3; i++) 10633 fw_version[i] = htonl(REG_RD_IND(sc, 10634 (BCE_CP_SCRATCH + 0x10 + i * 4))); 10635 10636 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 10637 10638 val = REG_RD_IND(sc, BCE_CP_CPU_MODE); 10639 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_mode\n", 10640 val, BCE_CP_CPU_MODE); 10641 10642 val = REG_RD_IND(sc, BCE_CP_CPU_STATE); 10643 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n", 10644 val, BCE_CP_CPU_STATE); 10645 10646 val = REG_RD_IND(sc, BCE_CP_CPU_EVENT_MASK); 10647 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_event_mask\n", val, 10648 BCE_CP_CPU_EVENT_MASK); 10649 10650 if (regs) { 10651 BCE_PRINTF( 10652 "----------------------------" 10653 " Register Dump " 10654 "----------------------------\n"); 10655 10656 for (int i = BCE_CP_CPU_MODE; i < 0x1aa000; i += 0x10) { 10657 /* Skip the big blank spaces */ 10658 if (i < 0x185400 && i > 0x19ffff) 10659 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 10660 "0x%08X 0x%08X\n", i, 10661 REG_RD_IND(sc, i), 10662 REG_RD_IND(sc, i + 0x4), 10663 REG_RD_IND(sc, i + 0x8), 10664 REG_RD_IND(sc, i + 0xC)); 10665 } 10666 } 10667 10668 BCE_PRINTF( 10669 "----------------------------" 10670 "----------------" 10671 "----------------------------\n"); 10672} 10673 10674 10675/****************************************************************************/ 10676/* Prints out the Completion Procesor (COM) state. */ 10677/* */ 10678/* Returns: */ 10679/* Nothing. */ 10680/****************************************************************************/ 10681static __attribute__ ((noinline)) void 10682bce_dump_com_state(struct bce_softc *sc, int regs) 10683{ 10684 u32 val; 10685 u32 fw_version[4]; 10686 10687 BCE_PRINTF( 10688 "----------------------------" 10689 " COM State " 10690 "----------------------------\n"); 10691 10692 for (int i = 0; i < 3; i++) 10693 fw_version[i] = htonl(REG_RD_IND(sc, 10694 (BCE_COM_SCRATCH + 0x10 + i * 4))); 10695 10696 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 10697 10698 val = REG_RD_IND(sc, BCE_COM_CPU_MODE); 10699 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_mode\n", 10700 val, BCE_COM_CPU_MODE); 10701 10702 val = REG_RD_IND(sc, BCE_COM_CPU_STATE); 10703 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n", 10704 val, BCE_COM_CPU_STATE); 10705 10706 val = REG_RD_IND(sc, BCE_COM_CPU_EVENT_MASK); 10707 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_event_mask\n", val, 10708 BCE_COM_CPU_EVENT_MASK); 10709 10710 if (regs) { 10711 BCE_PRINTF( 10712 "----------------------------" 10713 " Register Dump " 10714 "----------------------------\n"); 10715 10716 for (int i = BCE_COM_CPU_MODE; i < 0x1053e8; i += 0x10) { 10717 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 10718 "0x%08X 0x%08X\n", i, 10719 REG_RD_IND(sc, i), 10720 REG_RD_IND(sc, i + 0x4), 10721 REG_RD_IND(sc, i + 0x8), 10722 REG_RD_IND(sc, i + 0xC)); 10723 } 10724 } 10725 10726 BCE_PRINTF( 10727 "----------------------------" 10728 "----------------" 10729 "----------------------------\n"); 10730} 10731 10732 10733/****************************************************************************/ 10734/* Prints out the Receive Virtual 2 Physical (RV2P) state. */ 10735/* */ 10736/* Returns: */ 10737/* Nothing. */ 10738/****************************************************************************/ 10739static __attribute__ ((noinline)) void 10740bce_dump_rv2p_state(struct bce_softc *sc) 10741{ 10742 u32 val, pc1, pc2, fw_ver_high, fw_ver_low; 10743 10744 BCE_PRINTF( 10745 "----------------------------" 10746 " RV2P State " 10747 "----------------------------\n"); 10748 10749 /* Stall the RV2P processors. */ 10750 val = REG_RD_IND(sc, BCE_RV2P_CONFIG); 10751 val |= BCE_RV2P_CONFIG_STALL_PROC1 | BCE_RV2P_CONFIG_STALL_PROC2; 10752 REG_WR_IND(sc, BCE_RV2P_CONFIG, val); 10753 10754 /* Read the firmware version. */ 10755 val = 0x00000001; 10756 REG_WR_IND(sc, BCE_RV2P_PROC1_ADDR_CMD, val); 10757 fw_ver_low = REG_RD_IND(sc, BCE_RV2P_INSTR_LOW); 10758 fw_ver_high = REG_RD_IND(sc, BCE_RV2P_INSTR_HIGH) & 10759 BCE_RV2P_INSTR_HIGH_HIGH; 10760 BCE_PRINTF("RV2P1 Firmware version - 0x%08X:0x%08X\n", 10761 fw_ver_high, fw_ver_low); 10762 10763 val = 0x00000001; 10764 REG_WR_IND(sc, BCE_RV2P_PROC2_ADDR_CMD, val); 10765 fw_ver_low = REG_RD_IND(sc, BCE_RV2P_INSTR_LOW); 10766 fw_ver_high = REG_RD_IND(sc, BCE_RV2P_INSTR_HIGH) & 10767 BCE_RV2P_INSTR_HIGH_HIGH; 10768 BCE_PRINTF("RV2P2 Firmware version - 0x%08X:0x%08X\n", 10769 fw_ver_high, fw_ver_low); 10770 10771 /* Resume the RV2P processors. */ 10772 val = REG_RD_IND(sc, BCE_RV2P_CONFIG); 10773 val &= ~(BCE_RV2P_CONFIG_STALL_PROC1 | BCE_RV2P_CONFIG_STALL_PROC2); 10774 REG_WR_IND(sc, BCE_RV2P_CONFIG, val); 10775 10776 /* Fetch the program counter value. */ 10777 val = 0x68007800; 10778 REG_WR_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK, val); 10779 val = REG_RD_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK); 10780 pc1 = (val & BCE_RV2P_DEBUG_VECT_PEEK_1_VALUE); 10781 pc2 = (val & BCE_RV2P_DEBUG_VECT_PEEK_2_VALUE) >> 16; 10782 BCE_PRINTF("0x%08X - RV2P1 program counter (1st read)\n", pc1); 10783 BCE_PRINTF("0x%08X - RV2P2 program counter (1st read)\n", pc2); 10784 10785 /* Fetch the program counter value again to see if it is advancing. */ 10786 val = 0x68007800; 10787 REG_WR_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK, val); 10788 val = REG_RD_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK); 10789 pc1 = (val & BCE_RV2P_DEBUG_VECT_PEEK_1_VALUE); 10790 pc2 = (val & BCE_RV2P_DEBUG_VECT_PEEK_2_VALUE) >> 16; 10791 BCE_PRINTF("0x%08X - RV2P1 program counter (2nd read)\n", pc1); 10792 BCE_PRINTF("0x%08X - RV2P2 program counter (2nd read)\n", pc2); 10793 10794 BCE_PRINTF( 10795 "----------------------------" 10796 "----------------" 10797 "----------------------------\n"); 10798} 10799 10800 10801/****************************************************************************/ 10802/* Prints out the driver state and then enters the debugger. */ 10803/* */ 10804/* Returns: */ 10805/* Nothing. */ 10806/****************************************************************************/ 10807static __attribute__ ((noinline)) void 10808bce_breakpoint(struct bce_softc *sc) 10809{ 10810 10811 /* 10812 * Unreachable code to silence compiler warnings 10813 * about unused functions. 10814 */ 10815 if (0) { 10816 bce_freeze_controller(sc); 10817 bce_unfreeze_controller(sc); 10818 bce_dump_enet(sc, NULL); 10819 bce_dump_txbd(sc, 0, NULL); 10820 bce_dump_rxbd(sc, 0, NULL); 10821 bce_dump_tx_mbuf_chain(sc, 0, USABLE_TX_BD); 10822 bce_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD); 10823 bce_dump_l2fhdr(sc, 0, NULL); 10824 bce_dump_ctx(sc, RX_CID); 10825 bce_dump_ftqs(sc); 10826 bce_dump_tx_chain(sc, 0, USABLE_TX_BD); 10827 bce_dump_rx_bd_chain(sc, 0, USABLE_RX_BD); 10828 bce_dump_status_block(sc); 10829 bce_dump_stats_block(sc); 10830 bce_dump_driver_state(sc); 10831 bce_dump_hw_state(sc); 10832 bce_dump_bc_state(sc); 10833 bce_dump_txp_state(sc, 0); 10834 bce_dump_rxp_state(sc, 0); 10835 bce_dump_tpat_state(sc, 0); 10836 bce_dump_cp_state(sc, 0); 10837 bce_dump_com_state(sc, 0); 10838 bce_dump_rv2p_state(sc); 10839 10840#ifdef BCE_JUMBO_HDRSPLIT 10841 bce_dump_pgbd(sc, 0, NULL); 10842 bce_dump_pg_mbuf_chain(sc, 0, USABLE_PG_BD); 10843 bce_dump_pg_chain(sc, 0, USABLE_PG_BD); 10844#endif 10845 } 10846 10847 bce_dump_status_block(sc); 10848 bce_dump_driver_state(sc); 10849 10850 /* Call the debugger. */ 10851 breakpoint(); 10852 10853 return; 10854} 10855#endif 10856 10857