if_bce.c revision 170392
1/*- 2 * Copyright (c) 2006-2007 Broadcom Corporation 3 * David Christensen <davidch@broadcom.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. Neither the name of Broadcom Corporation nor the name of its contributors 15 * may be used to endorse or promote products derived from this software 16 * without specific prior written consent. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 28 * THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#include <sys/cdefs.h> 32__FBSDID("$FreeBSD: head/sys/dev/bce/if_bce.c 170392 2007-06-07 02:23:56Z davidch $"); 33 34/* 35 * The following controllers are supported by this driver: 36 * BCM5706C A2, A3 37 * BCM5708C B1, B2 38 * 39 * The following controllers are not supported by this driver: 40 * BCM5706C A0, A1 41 * BCM5706S A0, A1, A2, A3 42 * BCM5708C A0, B0 43 * BCM5708S A0, B0, B1, B2 44 */ 45 46#include "opt_bce.h" 47 48#include <dev/bce/if_bcereg.h> 49#include <dev/bce/if_bcefw.h> 50 51/****************************************************************************/ 52/* BCE Debug Options */ 53/****************************************************************************/ 54#ifdef BCE_DEBUG 55 u32 bce_debug = BCE_WARN; 56 57 /* 0 = Never */ 58 /* 1 = 1 in 2,147,483,648 */ 59 /* 256 = 1 in 8,388,608 */ 60 /* 2048 = 1 in 1,048,576 */ 61 /* 65536 = 1 in 32,768 */ 62 /* 1048576 = 1 in 2,048 */ 63 /* 268435456 = 1 in 8 */ 64 /* 536870912 = 1 in 4 */ 65 /* 1073741824 = 1 in 2 */ 66 67 /* Controls how often the l2_fhdr frame error check will fail. */ 68 int bce_debug_l2fhdr_status_check = 0; 69 70 /* Controls how often the unexpected attention check will fail. */ 71 int bce_debug_unexpected_attention = 0; 72 73 /* Controls how often to simulate an mbuf allocation failure. */ 74 int bce_debug_mbuf_allocation_failure = 0; 75 76 /* Controls how often to simulate a DMA mapping failure. */ 77 int bce_debug_dma_map_addr_failure = 0; 78 79 /* Controls how often to simulate a bootcode failure. */ 80 int bce_debug_bootcode_running_failure = 0; 81#endif 82 83 84/****************************************************************************/ 85/* PCI Device ID Table */ 86/* */ 87/* Used by bce_probe() to identify the devices supported by this driver. */ 88/****************************************************************************/ 89#define BCE_DEVDESC_MAX 64 90 91static struct bce_type bce_devs[] = { 92 /* BCM5706C Controllers and OEM boards. */ 93 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3101, 94 "HP NC370T Multifunction Gigabit Server Adapter" }, 95 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3106, 96 "HP NC370i Multifunction Gigabit Server Adapter" }, 97 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, PCI_ANY_ID, PCI_ANY_ID, 98 "Broadcom NetXtreme II BCM5706 1000Base-T" }, 99 100 /* BCM5706S controllers and OEM boards. */ 101 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, HP_VENDORID, 0x3102, 102 "HP NC370F Multifunction Gigabit Server Adapter" }, 103 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, PCI_ANY_ID, PCI_ANY_ID, 104 "Broadcom NetXtreme II BCM5706 1000Base-SX" }, 105 106 /* BCM5708C controllers and OEM boards. */ 107 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, PCI_ANY_ID, PCI_ANY_ID, 108 "Broadcom NetXtreme II BCM5708 1000Base-T" }, 109 110 /* BCM5708S controllers and OEM boards. */ 111 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, PCI_ANY_ID, PCI_ANY_ID, 112 "Broadcom NetXtreme II BCM5708 1000Base-SX" }, 113 { 0, 0, 0, 0, NULL } 114}; 115 116 117/****************************************************************************/ 118/* Supported Flash NVRAM device data. */ 119/****************************************************************************/ 120static struct flash_spec flash_table[] = 121{ 122 /* Slow EEPROM */ 123 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400, 124 1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 125 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 126 "EEPROM - slow"}, 127 /* Expansion entry 0001 */ 128 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406, 129 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 130 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 131 "Entry 0001"}, 132 /* Saifun SA25F010 (non-buffered flash) */ 133 /* strap, cfg1, & write1 need updates */ 134 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406, 135 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 136 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2, 137 "Non-buffered flash (128kB)"}, 138 /* Saifun SA25F020 (non-buffered flash) */ 139 /* strap, cfg1, & write1 need updates */ 140 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406, 141 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 142 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4, 143 "Non-buffered flash (256kB)"}, 144 /* Expansion entry 0100 */ 145 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406, 146 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 147 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 148 "Entry 0100"}, 149 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */ 150 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406, 151 0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 152 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2, 153 "Entry 0101: ST M45PE10 (128kB non-bufferred)"}, 154 /* Entry 0110: ST M45PE20 (non-buffered flash)*/ 155 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406, 156 0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 157 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4, 158 "Entry 0110: ST M45PE20 (256kB non-bufferred)"}, 159 /* Saifun SA25F005 (non-buffered flash) */ 160 /* strap, cfg1, & write1 need updates */ 161 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406, 162 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 163 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE, 164 "Non-buffered flash (64kB)"}, 165 /* Fast EEPROM */ 166 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400, 167 1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 168 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 169 "EEPROM - fast"}, 170 /* Expansion entry 1001 */ 171 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406, 172 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 173 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 174 "Entry 1001"}, 175 /* Expansion entry 1010 */ 176 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406, 177 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 178 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 179 "Entry 1010"}, 180 /* ATMEL AT45DB011B (buffered flash) */ 181 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400, 182 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 183 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE, 184 "Buffered flash (128kB)"}, 185 /* Expansion entry 1100 */ 186 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406, 187 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 188 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 189 "Entry 1100"}, 190 /* Expansion entry 1101 */ 191 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406, 192 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 193 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 194 "Entry 1101"}, 195 /* Ateml Expansion entry 1110 */ 196 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400, 197 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 198 BUFFERED_FLASH_BYTE_ADDR_MASK, 0, 199 "Entry 1110 (Atmel)"}, 200 /* ATMEL AT45DB021B (buffered flash) */ 201 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400, 202 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 203 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2, 204 "Buffered flash (256kB)"}, 205}; 206 207 208/****************************************************************************/ 209/* FreeBSD device entry points. */ 210/****************************************************************************/ 211static int bce_probe (device_t); 212static int bce_attach (device_t); 213static int bce_detach (device_t); 214static void bce_shutdown (device_t); 215 216 217/****************************************************************************/ 218/* BCE Debug Data Structure Dump Routines */ 219/****************************************************************************/ 220#ifdef BCE_DEBUG 221static void bce_dump_mbuf (struct bce_softc *, struct mbuf *); 222static void bce_dump_tx_mbuf_chain (struct bce_softc *, int, int); 223static void bce_dump_rx_mbuf_chain (struct bce_softc *, int, int); 224static void bce_dump_txbd (struct bce_softc *, int, struct tx_bd *); 225static void bce_dump_rxbd (struct bce_softc *, int, struct rx_bd *); 226static void bce_dump_l2fhdr (struct bce_softc *, int, struct l2_fhdr *); 227static void bce_dump_tx_chain (struct bce_softc *, int, int); 228static void bce_dump_rx_chain (struct bce_softc *, int, int); 229static void bce_dump_status_block (struct bce_softc *); 230static void bce_dump_stats_block (struct bce_softc *); 231static void bce_dump_driver_state (struct bce_softc *); 232static void bce_dump_hw_state (struct bce_softc *); 233static void bce_breakpoint (struct bce_softc *); 234#endif 235 236 237/****************************************************************************/ 238/* BCE Register/Memory Access Routines */ 239/****************************************************************************/ 240static u32 bce_reg_rd_ind (struct bce_softc *, u32); 241static void bce_reg_wr_ind (struct bce_softc *, u32, u32); 242static void bce_ctx_wr (struct bce_softc *, u32, u32, u32); 243static int bce_miibus_read_reg (device_t, int, int); 244static int bce_miibus_write_reg (device_t, int, int, int); 245static void bce_miibus_statchg (device_t); 246 247 248/****************************************************************************/ 249/* BCE NVRAM Access Routines */ 250/****************************************************************************/ 251static int bce_acquire_nvram_lock (struct bce_softc *); 252static int bce_release_nvram_lock (struct bce_softc *); 253static void bce_enable_nvram_access (struct bce_softc *); 254static void bce_disable_nvram_access(struct bce_softc *); 255static int bce_nvram_read_dword (struct bce_softc *, u32, u8 *, u32); 256static int bce_init_nvram (struct bce_softc *); 257static int bce_nvram_read (struct bce_softc *, u32, u8 *, int); 258static int bce_nvram_test (struct bce_softc *); 259#ifdef BCE_NVRAM_WRITE_SUPPORT 260static int bce_enable_nvram_write (struct bce_softc *); 261static void bce_disable_nvram_write (struct bce_softc *); 262static int bce_nvram_erase_page (struct bce_softc *, u32); 263static int bce_nvram_write_dword (struct bce_softc *, u32, u8 *, u32); 264static int bce_nvram_write (struct bce_softc *, u32, u8 *, int); 265#endif 266 267/****************************************************************************/ 268/* */ 269/****************************************************************************/ 270static void bce_dma_map_addr (void *, bus_dma_segment_t *, int, int); 271static int bce_dma_alloc (device_t); 272static void bce_dma_free (struct bce_softc *); 273static void bce_release_resources (struct bce_softc *); 274 275/****************************************************************************/ 276/* BCE Firmware Synchronization and Load */ 277/****************************************************************************/ 278static int bce_fw_sync (struct bce_softc *, u32); 279static void bce_load_rv2p_fw (struct bce_softc *, u32 *, u32, u32); 280static void bce_load_cpu_fw (struct bce_softc *, struct cpu_reg *, struct fw_info *); 281static void bce_init_cpus (struct bce_softc *); 282 283static void bce_stop (struct bce_softc *); 284static int bce_reset (struct bce_softc *, u32); 285static int bce_chipinit (struct bce_softc *); 286static int bce_blockinit (struct bce_softc *); 287static int bce_get_buf (struct bce_softc *, struct mbuf *, u16 *, u16 *, u32 *); 288 289static int bce_init_tx_chain (struct bce_softc *); 290static int bce_init_rx_chain (struct bce_softc *); 291static void bce_free_rx_chain (struct bce_softc *); 292static void bce_free_tx_chain (struct bce_softc *); 293 294static int bce_tx_encap (struct bce_softc *, struct mbuf **); 295static void bce_start_locked (struct ifnet *); 296static void bce_start (struct ifnet *); 297static int bce_ioctl (struct ifnet *, u_long, caddr_t); 298static void bce_watchdog (struct bce_softc *); 299static int bce_ifmedia_upd (struct ifnet *); 300static void bce_ifmedia_upd_locked (struct ifnet *); 301static void bce_ifmedia_sts (struct ifnet *, struct ifmediareq *); 302static void bce_init_locked (struct bce_softc *); 303static void bce_init (void *); 304static void bce_mgmt_init_locked(struct bce_softc *sc); 305 306static void bce_init_context (struct bce_softc *); 307static void bce_get_mac_addr (struct bce_softc *); 308static void bce_set_mac_addr (struct bce_softc *); 309static void bce_phy_intr (struct bce_softc *); 310static void bce_rx_intr (struct bce_softc *); 311static void bce_tx_intr (struct bce_softc *); 312static void bce_disable_intr (struct bce_softc *); 313static void bce_enable_intr (struct bce_softc *); 314 315#ifdef DEVICE_POLLING 316static void bce_poll_locked (struct ifnet *, enum poll_cmd, int); 317static void bce_poll (struct ifnet *, enum poll_cmd, int); 318#endif 319static void bce_intr (void *); 320static void bce_set_rx_mode (struct bce_softc *); 321static void bce_stats_update (struct bce_softc *); 322static void bce_tick (void *); 323static void bce_add_sysctls (struct bce_softc *); 324 325 326/****************************************************************************/ 327/* FreeBSD device dispatch table. */ 328/****************************************************************************/ 329static device_method_t bce_methods[] = { 330 /* Device interface */ 331 DEVMETHOD(device_probe, bce_probe), 332 DEVMETHOD(device_attach, bce_attach), 333 DEVMETHOD(device_detach, bce_detach), 334 DEVMETHOD(device_shutdown, bce_shutdown), 335 336 /* bus interface */ 337 DEVMETHOD(bus_print_child, bus_generic_print_child), 338 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 339 340 /* MII interface */ 341 DEVMETHOD(miibus_readreg, bce_miibus_read_reg), 342 DEVMETHOD(miibus_writereg, bce_miibus_write_reg), 343 DEVMETHOD(miibus_statchg, bce_miibus_statchg), 344 345 { 0, 0 } 346}; 347 348static driver_t bce_driver = { 349 "bce", 350 bce_methods, 351 sizeof(struct bce_softc) 352}; 353 354static devclass_t bce_devclass; 355 356MODULE_DEPEND(bce, pci, 1, 1, 1); 357MODULE_DEPEND(bce, ether, 1, 1, 1); 358MODULE_DEPEND(bce, miibus, 1, 1, 1); 359 360DRIVER_MODULE(bce, pci, bce_driver, bce_devclass, 0, 0); 361DRIVER_MODULE(miibus, bce, miibus_driver, miibus_devclass, 0, 0); 362 363 364/****************************************************************************/ 365/* Tunable device values */ 366/****************************************************************************/ 367static int bce_tso_enable = TRUE; 368static int bce_msi_enable = 1; 369 370/* Allowable values are TRUE or FALSE */ 371TUNABLE_INT("hw.bce.tso_enable", &bce_tso_enable); 372/* Allowable values are 0 (IRQ only) and 1 (IRQ or MSI) */ 373TUNABLE_INT("hw.bce.msi_enable", &bce_msi_enable); 374 375SYSCTL_NODE(_hw, OID_AUTO, bce, CTLFLAG_RD, 0, "bce driver parameters"); 376SYSCTL_UINT(_hw_bce, OID_AUTO, tso_enable, CTLFLAG_RDTUN, &bce_tso_enable, 0, 377"TSO Enable/Disable"); 378SYSCTL_UINT(_hw_bce, OID_AUTO, msi_enable, CTLFLAG_RDTUN, &bce_msi_enable, 0, 379"MSI | INTx selector"); 380 381/****************************************************************************/ 382/* Device probe function. */ 383/* */ 384/* Compares the device to the driver's list of supported devices and */ 385/* reports back to the OS whether this is the right driver for the device. */ 386/* */ 387/* Returns: */ 388/* BUS_PROBE_DEFAULT on success, positive value on failure. */ 389/****************************************************************************/ 390static int 391bce_probe(device_t dev) 392{ 393 struct bce_type *t; 394 struct bce_softc *sc; 395 char *descbuf; 396 u16 vid = 0, did = 0, svid = 0, sdid = 0; 397 398 t = bce_devs; 399 400 sc = device_get_softc(dev); 401 bzero(sc, sizeof(struct bce_softc)); 402 sc->bce_unit = device_get_unit(dev); 403 sc->bce_dev = dev; 404 405 /* Get the data for the device to be probed. */ 406 vid = pci_get_vendor(dev); 407 did = pci_get_device(dev); 408 svid = pci_get_subvendor(dev); 409 sdid = pci_get_subdevice(dev); 410 411 DBPRINT(sc, BCE_VERBOSE_LOAD, 412 "%s(); VID = 0x%04X, DID = 0x%04X, SVID = 0x%04X, " 413 "SDID = 0x%04X\n", __FUNCTION__, vid, did, svid, sdid); 414 415 /* Look through the list of known devices for a match. */ 416 while(t->bce_name != NULL) { 417 418 if ((vid == t->bce_vid) && (did == t->bce_did) && 419 ((svid == t->bce_svid) || (t->bce_svid == PCI_ANY_ID)) && 420 ((sdid == t->bce_sdid) || (t->bce_sdid == PCI_ANY_ID))) { 421 422 descbuf = malloc(BCE_DEVDESC_MAX, M_TEMP, M_NOWAIT); 423 424 if (descbuf == NULL) 425 return(ENOMEM); 426 427 /* Print out the device identity. */ 428 snprintf(descbuf, BCE_DEVDESC_MAX, "%s (%c%d)", 429 t->bce_name, 430 (((pci_read_config(dev, PCIR_REVID, 4) & 0xf0) >> 4) + 'A'), 431 (pci_read_config(dev, PCIR_REVID, 4) & 0xf)); 432 433 device_set_desc_copy(dev, descbuf); 434 free(descbuf, M_TEMP); 435 return(BUS_PROBE_DEFAULT); 436 } 437 t++; 438 } 439 440 DBPRINT(sc, BCE_VERBOSE_LOAD, "%s(%d): No IOCTL match found!\n", 441 __FILE__, __LINE__); 442 443 return(ENXIO); 444} 445 446 447/****************************************************************************/ 448/* Device attach function. */ 449/* */ 450/* Allocates device resources, performs secondary chip identification, */ 451/* resets and initializes the hardware, and initializes driver instance */ 452/* variables. */ 453/* */ 454/* Returns: */ 455/* 0 on success, positive value on failure. */ 456/****************************************************************************/ 457static int 458bce_attach(device_t dev) 459{ 460 struct bce_softc *sc; 461 struct ifnet *ifp; 462 u32 val; 463 int count, mbuf, rid, rc = 0; 464 465 sc = device_get_softc(dev); 466 sc->bce_dev = dev; 467 468 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 469 470 mbuf = device_get_unit(dev); 471 472 /* Set initial device and PHY flags */ 473 sc->bce_flags = 0; 474 sc->bce_phy_flags = 0; 475 476 sc->bce_unit = mbuf; 477 478 pci_enable_busmaster(dev); 479 480 /* Allocate PCI memory resources. */ 481 rid = PCIR_BAR(0); 482 sc->bce_res_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 483 &rid, RF_ACTIVE | PCI_RF_DENSE); 484 485 if (sc->bce_res_mem == NULL) { 486 BCE_PRINTF("%s(%d): PCI memory allocation failed\n", 487 __FILE__, __LINE__); 488 rc = ENXIO; 489 goto bce_attach_fail; 490 } 491 492 /* Get various resource handles. */ 493 sc->bce_btag = rman_get_bustag(sc->bce_res_mem); 494 sc->bce_bhandle = rman_get_bushandle(sc->bce_res_mem); 495 sc->bce_vhandle = (vm_offset_t) rman_get_virtual(sc->bce_res_mem); 496 497 /* If MSI is enabled in the driver, get the vector count. */ 498 count = bce_msi_enable ? pci_msi_count(dev) : 0; 499 500 /* Allocate PCI IRQ resources. */ 501 if (count == 1 && pci_alloc_msi(dev, &count) == 0 && count == 1) { 502 rid = 1; 503 sc->bce_flags |= BCE_USING_MSI_FLAG; 504 DBPRINT(sc, BCE_INFO, "Allocating %d MSI interrupt(s).\n", count); 505 } else { 506 rid = 0; 507 DBPRINT(sc, BCE_INFO, "Allocating IRQ interrupt.\n"); 508 } 509 510 sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 511 RF_SHAREABLE | RF_ACTIVE); 512 513 if (sc->bce_res_irq == NULL) { 514 BCE_PRINTF("%s(%d): PCI map interrupt failed!\n", 515 __FILE__, __LINE__); 516 rc = ENXIO; 517 goto bce_attach_fail; 518 } 519 520 /* Initialize mutex for the current device instance. */ 521 BCE_LOCK_INIT(sc, device_get_nameunit(dev)); 522 523 /* 524 * Configure byte swap and enable indirect register access. 525 * Rely on CPU to do target byte swapping on big endian systems. 526 * Access to registers outside of PCI configurtion space are not 527 * valid until this is done. 528 */ 529 pci_write_config(dev, BCE_PCICFG_MISC_CONFIG, 530 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 531 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP, 4); 532 533 /* Save ASIC revsion info. */ 534 sc->bce_chipid = REG_RD(sc, BCE_MISC_ID); 535 536 /* Weed out any non-production controller revisions. */ 537 switch(BCE_CHIP_ID(sc)) { 538 case BCE_CHIP_ID_5706_A0: 539 case BCE_CHIP_ID_5706_A1: 540 case BCE_CHIP_ID_5708_A0: 541 case BCE_CHIP_ID_5708_B0: 542 BCE_PRINTF("%s(%d): Unsupported controller revision (%c%d)!\n", 543 __FILE__, __LINE__, 544 (((pci_read_config(dev, PCIR_REVID, 4) & 0xf0) >> 4) + 'A'), 545 (pci_read_config(dev, PCIR_REVID, 4) & 0xf)); 546 rc = ENODEV; 547 goto bce_attach_fail; 548 } 549 550 /* 551 * The embedded PCIe to PCI-X bridge (EPB) 552 * in the 5708 cannot address memory above 553 * 40 bits (E7_5708CB1_23043 & E6_5708SB1_23043). 554 */ 555 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708) 556 sc->max_bus_addr = BCE_BUS_SPACE_MAXADDR; 557 else 558 sc->max_bus_addr = BUS_SPACE_MAXADDR; 559 560 /* 561 * Find the base address for shared memory access. 562 * Newer versions of bootcode use a signature and offset 563 * while older versions use a fixed address. 564 */ 565 val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE); 566 if ((val & BCE_SHM_HDR_SIGNATURE_SIG_MASK) == BCE_SHM_HDR_SIGNATURE_SIG) 567 sc->bce_shmem_base = REG_RD_IND(sc, BCE_SHM_HDR_ADDR_0); 568 else 569 sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE; 570 571 DBPRINT(sc, BCE_INFO, "bce_shmem_base = 0x%08X\n", sc->bce_shmem_base); 572 573 /* Get PCI bus information (speed and type). */ 574 val = REG_RD(sc, BCE_PCICFG_MISC_STATUS); 575 if (val & BCE_PCICFG_MISC_STATUS_PCIX_DET) { 576 u32 clkreg; 577 578 sc->bce_flags |= BCE_PCIX_FLAG; 579 580 clkreg = REG_RD(sc, BCE_PCICFG_PCI_CLOCK_CONTROL_BITS); 581 582 clkreg &= BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET; 583 switch (clkreg) { 584 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ: 585 sc->bus_speed_mhz = 133; 586 break; 587 588 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ: 589 sc->bus_speed_mhz = 100; 590 break; 591 592 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ: 593 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ: 594 sc->bus_speed_mhz = 66; 595 break; 596 597 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ: 598 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ: 599 sc->bus_speed_mhz = 50; 600 break; 601 602 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW: 603 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ: 604 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ: 605 sc->bus_speed_mhz = 33; 606 break; 607 } 608 } else { 609 if (val & BCE_PCICFG_MISC_STATUS_M66EN) 610 sc->bus_speed_mhz = 66; 611 else 612 sc->bus_speed_mhz = 33; 613 } 614 615 if (val & BCE_PCICFG_MISC_STATUS_32BIT_DET) 616 sc->bce_flags |= BCE_PCI_32BIT_FLAG; 617 618 BCE_PRINTF("ASIC ID 0x%08X; Revision (%c%d); PCI%s %s %dMHz\n", 619 sc->bce_chipid, 620 ((BCE_CHIP_ID(sc) & 0xf000) >> 12) + 'A', 621 ((BCE_CHIP_ID(sc) & 0x0ff0) >> 4), 622 ((sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : ""), 623 ((sc->bce_flags & BCE_PCI_32BIT_FLAG) ? "32-bit" : "64-bit"), 624 sc->bus_speed_mhz); 625 626 /* Reset the controller. */ 627 if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) { 628 rc = ENXIO; 629 goto bce_attach_fail; 630 } 631 632 /* Initialize the controller. */ 633 if (bce_chipinit(sc)) { 634 BCE_PRINTF("%s(%d): Controller initialization failed!\n", 635 __FILE__, __LINE__); 636 rc = ENXIO; 637 goto bce_attach_fail; 638 } 639 640 /* Perform NVRAM test. */ 641 if (bce_nvram_test(sc)) { 642 BCE_PRINTF("%s(%d): NVRAM test failed!\n", 643 __FILE__, __LINE__); 644 rc = ENXIO; 645 goto bce_attach_fail; 646 } 647 648 /* Fetch the permanent Ethernet MAC address. */ 649 bce_get_mac_addr(sc); 650 651 /* 652 * Trip points control how many BDs 653 * should be ready before generating an 654 * interrupt while ticks control how long 655 * a BD can sit in the chain before 656 * generating an interrupt. Set the default 657 * values for the RX and TX rings. 658 */ 659 660#ifdef BCE_DRBUG 661 /* Force more frequent interrupts. */ 662 sc->bce_tx_quick_cons_trip_int = 1; 663 sc->bce_tx_quick_cons_trip = 1; 664 sc->bce_tx_ticks_int = 0; 665 sc->bce_tx_ticks = 0; 666 667 sc->bce_rx_quick_cons_trip_int = 1; 668 sc->bce_rx_quick_cons_trip = 1; 669 sc->bce_rx_ticks_int = 0; 670 sc->bce_rx_ticks = 0; 671#else 672 sc->bce_tx_quick_cons_trip_int = 20; 673 sc->bce_tx_quick_cons_trip = 20; 674 sc->bce_tx_ticks_int = 80; 675 sc->bce_tx_ticks = 80; 676 677 sc->bce_rx_quick_cons_trip_int = 6; 678 sc->bce_rx_quick_cons_trip = 6; 679 sc->bce_rx_ticks_int = 18; 680 sc->bce_rx_ticks = 18; 681#endif 682 683 /* Update statistics once every second. */ 684 sc->bce_stats_ticks = 1000000 & 0xffff00; 685 686 /* 687 * The SerDes based NetXtreme II controllers 688 * that support 2.5Gb operation (currently 689 * 5708S) use a PHY at address 2, otherwise 690 * the PHY is present at address 1. 691 */ 692 sc->bce_phy_addr = 1; 693 694 if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT) { 695 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 696 sc->bce_flags |= BCE_NO_WOL_FLAG; 697 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) { 698 sc->bce_phy_addr = 2; 699 val = REG_RD_IND(sc, sc->bce_shmem_base + 700 BCE_SHARED_HW_CFG_CONFIG); 701 if (val & BCE_SHARED_HW_CFG_PHY_2_5G) { 702 sc->bce_phy_flags |= BCE_PHY_2_5G_CAPABLE_FLAG; 703 DBPRINT(sc, BCE_WARN, "Found 2.5Gb capable adapter\n"); 704 } 705 } 706 } 707 708 /* Store config data needed by the PHY driver for backplane applications */ 709 sc->bce_shared_hw_cfg = REG_RD_IND(sc, sc->bce_shmem_base + 710 BCE_SHARED_HW_CFG_CONFIG); 711 sc->bce_port_hw_cfg = REG_RD_IND(sc, sc->bce_shmem_base + 712 BCE_SHARED_HW_CFG_CONFIG); 713 714 /* Allocate DMA memory resources. */ 715 if (bce_dma_alloc(dev)) { 716 BCE_PRINTF("%s(%d): DMA resource allocation failed!\n", 717 __FILE__, __LINE__); 718 rc = ENXIO; 719 goto bce_attach_fail; 720 } 721 722 /* Allocate an ifnet structure. */ 723 ifp = sc->bce_ifp = if_alloc(IFT_ETHER); 724 if (ifp == NULL) { 725 BCE_PRINTF("%s(%d): Interface allocation failed!\n", 726 __FILE__, __LINE__); 727 rc = ENXIO; 728 goto bce_attach_fail; 729 } 730 731 /* Initialize the ifnet interface. */ 732 ifp->if_softc = sc; 733 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 734 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 735 ifp->if_ioctl = bce_ioctl; 736 ifp->if_start = bce_start; 737 ifp->if_init = bce_init; 738 ifp->if_mtu = ETHERMTU; 739 740 if (bce_tso_enable) { 741 ifp->if_hwassist = BCE_IF_HWASSIST | CSUM_TSO; 742 ifp->if_capabilities = BCE_IF_CAPABILITIES | IFCAP_TSO4; 743 } else { 744 ifp->if_hwassist = BCE_IF_HWASSIST; 745 ifp->if_capabilities = BCE_IF_CAPABILITIES; 746 } 747 748 ifp->if_capenable = ifp->if_capabilities; 749 750 /* Assume a standard 1500 byte MTU size for mbuf allocations. */ 751 sc->mbuf_alloc_size = MCLBYTES; 752#ifdef DEVICE_POLLING 753 ifp->if_capabilities |= IFCAP_POLLING; 754#endif 755 756 ifp->if_snd.ifq_drv_maxlen = USABLE_TX_BD; 757 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) 758 ifp->if_baudrate = IF_Mbps(2500ULL); 759 else 760 ifp->if_baudrate = IF_Mbps(1000); 761 762 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 763 IFQ_SET_READY(&ifp->if_snd); 764 765 /* Look for our PHY. */ 766 if (mii_phy_probe(dev, &sc->bce_miibus, bce_ifmedia_upd, 767 bce_ifmedia_sts)) { 768 BCE_PRINTF("%s(%d): PHY probe failed!\n", 769 __FILE__, __LINE__); 770 rc = ENXIO; 771 goto bce_attach_fail; 772 } 773 774 /* Attach to the Ethernet interface list. */ 775 ether_ifattach(ifp, sc->eaddr); 776 777#if __FreeBSD_version < 500000 778 callout_init(&sc->bce_stat_ch); 779#else 780 callout_init_mtx(&sc->bce_stat_ch, &sc->bce_mtx, 0); 781#endif 782 783 /* Hookup IRQ last. */ 784 rc = bus_setup_intr(dev, sc->bce_res_irq, INTR_TYPE_NET | INTR_MPSAFE, NULL, 785 bce_intr, sc, &sc->bce_intrhand); 786 787 if (rc) { 788 BCE_PRINTF("%s(%d): Failed to setup IRQ!\n", 789 __FILE__, __LINE__); 790 bce_detach(dev); 791 goto bce_attach_exit; 792 } 793 794 /* Print some important debugging info. */ 795 DBRUN(BCE_INFO, bce_dump_driver_state(sc)); 796 797 /* Add the supported sysctls to the kernel. */ 798 bce_add_sysctls(sc); 799 800 /* Get the firmware running so IPMI still works */ 801 BCE_LOCK(sc); 802 bce_mgmt_init_locked(sc); 803 BCE_UNLOCK(sc); 804 805 goto bce_attach_exit; 806 807bce_attach_fail: 808 bce_release_resources(sc); 809 810bce_attach_exit: 811 812 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 813 814 return(rc); 815} 816 817 818/****************************************************************************/ 819/* Device detach function. */ 820/* */ 821/* Stops the controller, resets the controller, and releases resources. */ 822/* */ 823/* Returns: */ 824/* 0 on success, positive value on failure. */ 825/****************************************************************************/ 826static int 827bce_detach(device_t dev) 828{ 829 struct bce_softc *sc; 830 struct ifnet *ifp; 831 832 sc = device_get_softc(dev); 833 834 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 835 836 ifp = sc->bce_ifp; 837 838#ifdef DEVICE_POLLING 839 if (ifp->if_capenable & IFCAP_POLLING) 840 ether_poll_deregister(ifp); 841#endif 842 843 /* Stop and reset the controller. */ 844 BCE_LOCK(sc); 845 bce_stop(sc); 846 bce_reset(sc, BCE_DRV_MSG_CODE_RESET); 847 BCE_UNLOCK(sc); 848 849 ether_ifdetach(ifp); 850 851 /* If we have a child device on the MII bus remove it too. */ 852 bus_generic_detach(dev); 853 device_delete_child(dev, sc->bce_miibus); 854 855 /* Release all remaining resources. */ 856 bce_release_resources(sc); 857 858 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 859 860 return(0); 861} 862 863 864/****************************************************************************/ 865/* Device shutdown function. */ 866/* */ 867/* Stops and resets the controller. */ 868/* */ 869/* Returns: */ 870/* Nothing */ 871/****************************************************************************/ 872static void 873bce_shutdown(device_t dev) 874{ 875 struct bce_softc *sc = device_get_softc(dev); 876 877 BCE_LOCK(sc); 878 bce_stop(sc); 879 bce_reset(sc, BCE_DRV_MSG_CODE_RESET); 880 BCE_UNLOCK(sc); 881} 882 883 884/****************************************************************************/ 885/* Indirect register read. */ 886/* */ 887/* Reads NetXtreme II registers using an index/data register pair in PCI */ 888/* configuration space. Using this mechanism avoids issues with posted */ 889/* reads but is much slower than memory-mapped I/O. */ 890/* */ 891/* Returns: */ 892/* The value of the register. */ 893/****************************************************************************/ 894static u32 895bce_reg_rd_ind(struct bce_softc *sc, u32 offset) 896{ 897 device_t dev; 898 dev = sc->bce_dev; 899 900 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4); 901#ifdef BCE_DEBUG 902 { 903 u32 val; 904 val = pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4); 905 DBPRINT(sc, BCE_EXCESSIVE, "%s(); offset = 0x%08X, val = 0x%08X\n", 906 __FUNCTION__, offset, val); 907 return val; 908 } 909#else 910 return pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4); 911#endif 912} 913 914 915/****************************************************************************/ 916/* Indirect register write. */ 917/* */ 918/* Writes NetXtreme II registers using an index/data register pair in PCI */ 919/* configuration space. Using this mechanism avoids issues with posted */ 920/* writes but is muchh slower than memory-mapped I/O. */ 921/* */ 922/* Returns: */ 923/* Nothing. */ 924/****************************************************************************/ 925static void 926bce_reg_wr_ind(struct bce_softc *sc, u32 offset, u32 val) 927{ 928 device_t dev; 929 dev = sc->bce_dev; 930 931 DBPRINT(sc, BCE_EXCESSIVE, "%s(); offset = 0x%08X, val = 0x%08X\n", 932 __FUNCTION__, offset, val); 933 934 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4); 935 pci_write_config(dev, BCE_PCICFG_REG_WINDOW, val, 4); 936} 937 938 939/****************************************************************************/ 940/* Context memory write. */ 941/* */ 942/* The NetXtreme II controller uses context memory to track connection */ 943/* information for L2 and higher network protocols. */ 944/* */ 945/* Returns: */ 946/* Nothing. */ 947/****************************************************************************/ 948static void 949bce_ctx_wr(struct bce_softc *sc, u32 cid_addr, u32 offset, u32 val) 950{ 951 952 DBPRINT(sc, BCE_EXCESSIVE, "%s(); cid_addr = 0x%08X, offset = 0x%08X, " 953 "val = 0x%08X\n", __FUNCTION__, cid_addr, offset, val); 954 955 offset += cid_addr; 956 REG_WR(sc, BCE_CTX_DATA_ADR, offset); 957 REG_WR(sc, BCE_CTX_DATA, val); 958} 959 960 961/****************************************************************************/ 962/* PHY register read. */ 963/* */ 964/* Implements register reads on the MII bus. */ 965/* */ 966/* Returns: */ 967/* The value of the register. */ 968/****************************************************************************/ 969static int 970bce_miibus_read_reg(device_t dev, int phy, int reg) 971{ 972 struct bce_softc *sc; 973 u32 val; 974 int i; 975 976 sc = device_get_softc(dev); 977 978 /* Make sure we are accessing the correct PHY address. */ 979 if (phy != sc->bce_phy_addr) { 980 DBPRINT(sc, BCE_VERBOSE, "Invalid PHY address %d for PHY read!\n", phy); 981 return(0); 982 } 983 984 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 985 val = REG_RD(sc, BCE_EMAC_MDIO_MODE); 986 val &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL; 987 988 REG_WR(sc, BCE_EMAC_MDIO_MODE, val); 989 REG_RD(sc, BCE_EMAC_MDIO_MODE); 990 991 DELAY(40); 992 } 993 994 val = BCE_MIPHY(phy) | BCE_MIREG(reg) | 995 BCE_EMAC_MDIO_COMM_COMMAND_READ | BCE_EMAC_MDIO_COMM_DISEXT | 996 BCE_EMAC_MDIO_COMM_START_BUSY; 997 REG_WR(sc, BCE_EMAC_MDIO_COMM, val); 998 999 for (i = 0; i < BCE_PHY_TIMEOUT; i++) { 1000 DELAY(10); 1001 1002 val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1003 if (!(val & BCE_EMAC_MDIO_COMM_START_BUSY)) { 1004 DELAY(5); 1005 1006 val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1007 val &= BCE_EMAC_MDIO_COMM_DATA; 1008 1009 break; 1010 } 1011 } 1012 1013 if (val & BCE_EMAC_MDIO_COMM_START_BUSY) { 1014 BCE_PRINTF("%s(%d): Error: PHY read timeout! phy = %d, reg = 0x%04X\n", 1015 __FILE__, __LINE__, phy, reg); 1016 val = 0x0; 1017 } else { 1018 val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1019 } 1020 1021 DBPRINT(sc, BCE_EXCESSIVE, "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n", 1022 __FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff); 1023 1024 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1025 val = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1026 val |= BCE_EMAC_MDIO_MODE_AUTO_POLL; 1027 1028 REG_WR(sc, BCE_EMAC_MDIO_MODE, val); 1029 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1030 1031 DELAY(40); 1032 } 1033 1034 return (val & 0xffff); 1035 1036} 1037 1038 1039/****************************************************************************/ 1040/* PHY register write. */ 1041/* */ 1042/* Implements register writes on the MII bus. */ 1043/* */ 1044/* Returns: */ 1045/* The value of the register. */ 1046/****************************************************************************/ 1047static int 1048bce_miibus_write_reg(device_t dev, int phy, int reg, int val) 1049{ 1050 struct bce_softc *sc; 1051 u32 val1; 1052 int i; 1053 1054 sc = device_get_softc(dev); 1055 1056 /* Make sure we are accessing the correct PHY address. */ 1057 if (phy != sc->bce_phy_addr) { 1058 DBPRINT(sc, BCE_VERBOSE, "Invalid PHY address %d for PHY write!\n", phy); 1059 return(0); 1060 } 1061 1062 DBPRINT(sc, BCE_EXCESSIVE, "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n", 1063 __FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff); 1064 1065 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1066 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1067 val1 &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL; 1068 1069 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1); 1070 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1071 1072 DELAY(40); 1073 } 1074 1075 val1 = BCE_MIPHY(phy) | BCE_MIREG(reg) | val | 1076 BCE_EMAC_MDIO_COMM_COMMAND_WRITE | 1077 BCE_EMAC_MDIO_COMM_START_BUSY | BCE_EMAC_MDIO_COMM_DISEXT; 1078 REG_WR(sc, BCE_EMAC_MDIO_COMM, val1); 1079 1080 for (i = 0; i < BCE_PHY_TIMEOUT; i++) { 1081 DELAY(10); 1082 1083 val1 = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1084 if (!(val1 & BCE_EMAC_MDIO_COMM_START_BUSY)) { 1085 DELAY(5); 1086 break; 1087 } 1088 } 1089 1090 if (val1 & BCE_EMAC_MDIO_COMM_START_BUSY) 1091 BCE_PRINTF("%s(%d): PHY write timeout!\n", 1092 __FILE__, __LINE__); 1093 1094 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1095 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1096 val1 |= BCE_EMAC_MDIO_MODE_AUTO_POLL; 1097 1098 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1); 1099 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1100 1101 DELAY(40); 1102 } 1103 1104 return 0; 1105} 1106 1107 1108/****************************************************************************/ 1109/* MII bus status change. */ 1110/* */ 1111/* Called by the MII bus driver when the PHY establishes link to set the */ 1112/* MAC interface registers. */ 1113/* */ 1114/* Returns: */ 1115/* Nothing. */ 1116/****************************************************************************/ 1117static void 1118bce_miibus_statchg(device_t dev) 1119{ 1120 struct bce_softc *sc; 1121 struct mii_data *mii; 1122 int val; 1123 1124 sc = device_get_softc(dev); 1125 1126 mii = device_get_softc(sc->bce_miibus); 1127 1128 val = REG_RD(sc, BCE_EMAC_MODE); 1129 val &= ~(BCE_EMAC_MODE_PORT | BCE_EMAC_MODE_HALF_DUPLEX | 1130 BCE_EMAC_MODE_MAC_LOOP | BCE_EMAC_MODE_FORCE_LINK | 1131 BCE_EMAC_MODE_25G); 1132 1133 /* Set MII or GMII interface based on the speed negotiated by the PHY. */ 1134 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1135 case IFM_10_T: 1136 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) { 1137 DBPRINT(sc, BCE_INFO, "Enabling 10Mb interface.\n"); 1138 val |= BCE_EMAC_MODE_PORT_MII_10; 1139 break; 1140 } 1141 /* fall-through */ 1142 case IFM_100_TX: 1143 DBPRINT(sc, BCE_INFO, "Enabling MII interface.\n"); 1144 val |= BCE_EMAC_MODE_PORT_MII; 1145 break; 1146 case IFM_2500_SX: 1147 DBPRINT(sc, BCE_INFO, "Enabling 2.5G MAC mode.\n"); 1148 val |= BCE_EMAC_MODE_25G; 1149 /* fall-through */ 1150 case IFM_1000_T: 1151 case IFM_1000_SX: 1152 DBPRINT(sc, BCE_INFO, "Enablinb GMII interface.\n"); 1153 val |= BCE_EMAC_MODE_PORT_GMII; 1154 break; 1155 default: 1156 val |= BCE_EMAC_MODE_PORT_GMII; 1157 } 1158 1159 /* Set half or full duplex based on the duplicity negotiated by the PHY. */ 1160 if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) { 1161 DBPRINT(sc, BCE_INFO, "Setting Half-Duplex interface.\n"); 1162 val |= BCE_EMAC_MODE_HALF_DUPLEX; 1163 } else 1164 DBPRINT(sc, BCE_INFO, "Setting Full-Duplex interface.\n"); 1165 1166 REG_WR(sc, BCE_EMAC_MODE, val); 1167 1168#if 0 1169 /* Todo: Enable this support in brgphy and bge. */ 1170 /* FLAG0 is set if RX is enabled and FLAG1 if TX is enabled */ 1171 if (mii->mii_media_active & IFM_FLAG0) 1172 BCE_SETBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_RX_MODE_FLOW_EN); 1173 if (mii->mii_media_active & IFM_FLAG1) 1174 BCE_SETBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_TX_MODE_FLOW_EN); 1175#endif 1176 1177} 1178 1179 1180/****************************************************************************/ 1181/* Acquire NVRAM lock. */ 1182/* */ 1183/* Before the NVRAM can be accessed the caller must acquire an NVRAM lock. */ 1184/* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 1185/* for use by the driver. */ 1186/* */ 1187/* Returns: */ 1188/* 0 on success, positive value on failure. */ 1189/****************************************************************************/ 1190static int 1191bce_acquire_nvram_lock(struct bce_softc *sc) 1192{ 1193 u32 val; 1194 int j; 1195 1196 DBPRINT(sc, BCE_VERBOSE, "Acquiring NVRAM lock.\n"); 1197 1198 /* Request access to the flash interface. */ 1199 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2); 1200 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1201 val = REG_RD(sc, BCE_NVM_SW_ARB); 1202 if (val & BCE_NVM_SW_ARB_ARB_ARB2) 1203 break; 1204 1205 DELAY(5); 1206 } 1207 1208 if (j >= NVRAM_TIMEOUT_COUNT) { 1209 DBPRINT(sc, BCE_WARN, "Timeout acquiring NVRAM lock!\n"); 1210 return EBUSY; 1211 } 1212 1213 return 0; 1214} 1215 1216 1217/****************************************************************************/ 1218/* Release NVRAM lock. */ 1219/* */ 1220/* When the caller is finished accessing NVRAM the lock must be released. */ 1221/* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 1222/* for use by the driver. */ 1223/* */ 1224/* Returns: */ 1225/* 0 on success, positive value on failure. */ 1226/****************************************************************************/ 1227static int 1228bce_release_nvram_lock(struct bce_softc *sc) 1229{ 1230 int j; 1231 u32 val; 1232 1233 DBPRINT(sc, BCE_VERBOSE, "Releasing NVRAM lock.\n"); 1234 1235 /* 1236 * Relinquish nvram interface. 1237 */ 1238 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2); 1239 1240 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1241 val = REG_RD(sc, BCE_NVM_SW_ARB); 1242 if (!(val & BCE_NVM_SW_ARB_ARB_ARB2)) 1243 break; 1244 1245 DELAY(5); 1246 } 1247 1248 if (j >= NVRAM_TIMEOUT_COUNT) { 1249 DBPRINT(sc, BCE_WARN, "Timeout reeasing NVRAM lock!\n"); 1250 return EBUSY; 1251 } 1252 1253 return 0; 1254} 1255 1256 1257#ifdef BCE_NVRAM_WRITE_SUPPORT 1258/****************************************************************************/ 1259/* Enable NVRAM write access. */ 1260/* */ 1261/* Before writing to NVRAM the caller must enable NVRAM writes. */ 1262/* */ 1263/* Returns: */ 1264/* 0 on success, positive value on failure. */ 1265/****************************************************************************/ 1266static int 1267bce_enable_nvram_write(struct bce_softc *sc) 1268{ 1269 u32 val; 1270 1271 DBPRINT(sc, BCE_VERBOSE, "Enabling NVRAM write.\n"); 1272 1273 val = REG_RD(sc, BCE_MISC_CFG); 1274 REG_WR(sc, BCE_MISC_CFG, val | BCE_MISC_CFG_NVM_WR_EN_PCI); 1275 1276 if (!sc->bce_flash_info->buffered) { 1277 int j; 1278 1279 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 1280 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_WREN | BCE_NVM_COMMAND_DOIT); 1281 1282 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1283 DELAY(5); 1284 1285 val = REG_RD(sc, BCE_NVM_COMMAND); 1286 if (val & BCE_NVM_COMMAND_DONE) 1287 break; 1288 } 1289 1290 if (j >= NVRAM_TIMEOUT_COUNT) { 1291 DBPRINT(sc, BCE_WARN, "Timeout writing NVRAM!\n"); 1292 return EBUSY; 1293 } 1294 } 1295 return 0; 1296} 1297 1298 1299/****************************************************************************/ 1300/* Disable NVRAM write access. */ 1301/* */ 1302/* When the caller is finished writing to NVRAM write access must be */ 1303/* disabled. */ 1304/* */ 1305/* Returns: */ 1306/* Nothing. */ 1307/****************************************************************************/ 1308static void 1309bce_disable_nvram_write(struct bce_softc *sc) 1310{ 1311 u32 val; 1312 1313 DBPRINT(sc, BCE_VERBOSE, "Disabling NVRAM write.\n"); 1314 1315 val = REG_RD(sc, BCE_MISC_CFG); 1316 REG_WR(sc, BCE_MISC_CFG, val & ~BCE_MISC_CFG_NVM_WR_EN); 1317} 1318#endif 1319 1320 1321/****************************************************************************/ 1322/* Enable NVRAM access. */ 1323/* */ 1324/* Before accessing NVRAM for read or write operations the caller must */ 1325/* enabled NVRAM access. */ 1326/* */ 1327/* Returns: */ 1328/* Nothing. */ 1329/****************************************************************************/ 1330static void 1331bce_enable_nvram_access(struct bce_softc *sc) 1332{ 1333 u32 val; 1334 1335 DBPRINT(sc, BCE_VERBOSE, "Enabling NVRAM access.\n"); 1336 1337 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE); 1338 /* Enable both bits, even on read. */ 1339 REG_WR(sc, BCE_NVM_ACCESS_ENABLE, 1340 val | BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN); 1341} 1342 1343 1344/****************************************************************************/ 1345/* Disable NVRAM access. */ 1346/* */ 1347/* When the caller is finished accessing NVRAM access must be disabled. */ 1348/* */ 1349/* Returns: */ 1350/* Nothing. */ 1351/****************************************************************************/ 1352static void 1353bce_disable_nvram_access(struct bce_softc *sc) 1354{ 1355 u32 val; 1356 1357 DBPRINT(sc, BCE_VERBOSE, "Disabling NVRAM access.\n"); 1358 1359 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE); 1360 1361 /* Disable both bits, even after read. */ 1362 REG_WR(sc, BCE_NVM_ACCESS_ENABLE, 1363 val & ~(BCE_NVM_ACCESS_ENABLE_EN | 1364 BCE_NVM_ACCESS_ENABLE_WR_EN)); 1365} 1366 1367 1368#ifdef BCE_NVRAM_WRITE_SUPPORT 1369/****************************************************************************/ 1370/* Erase NVRAM page before writing. */ 1371/* */ 1372/* Non-buffered flash parts require that a page be erased before it is */ 1373/* written. */ 1374/* */ 1375/* Returns: */ 1376/* 0 on success, positive value on failure. */ 1377/****************************************************************************/ 1378static int 1379bce_nvram_erase_page(struct bce_softc *sc, u32 offset) 1380{ 1381 u32 cmd; 1382 int j; 1383 1384 /* Buffered flash doesn't require an erase. */ 1385 if (sc->bce_flash_info->buffered) 1386 return 0; 1387 1388 DBPRINT(sc, BCE_VERBOSE, "Erasing NVRAM page.\n"); 1389 1390 /* Build an erase command. */ 1391 cmd = BCE_NVM_COMMAND_ERASE | BCE_NVM_COMMAND_WR | 1392 BCE_NVM_COMMAND_DOIT; 1393 1394 /* 1395 * Clear the DONE bit separately, set the NVRAM adress to erase, 1396 * and issue the erase command. 1397 */ 1398 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 1399 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 1400 REG_WR(sc, BCE_NVM_COMMAND, cmd); 1401 1402 /* Wait for completion. */ 1403 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1404 u32 val; 1405 1406 DELAY(5); 1407 1408 val = REG_RD(sc, BCE_NVM_COMMAND); 1409 if (val & BCE_NVM_COMMAND_DONE) 1410 break; 1411 } 1412 1413 if (j >= NVRAM_TIMEOUT_COUNT) { 1414 DBPRINT(sc, BCE_WARN, "Timeout erasing NVRAM.\n"); 1415 return EBUSY; 1416 } 1417 1418 return 0; 1419} 1420#endif /* BCE_NVRAM_WRITE_SUPPORT */ 1421 1422 1423/****************************************************************************/ 1424/* Read a dword (32 bits) from NVRAM. */ 1425/* */ 1426/* Read a 32 bit word from NVRAM. The caller is assumed to have already */ 1427/* obtained the NVRAM lock and enabled the controller for NVRAM access. */ 1428/* */ 1429/* Returns: */ 1430/* 0 on success and the 32 bit value read, positive value on failure. */ 1431/****************************************************************************/ 1432static int 1433bce_nvram_read_dword(struct bce_softc *sc, u32 offset, u8 *ret_val, 1434 u32 cmd_flags) 1435{ 1436 u32 cmd; 1437 int i, rc = 0; 1438 1439 /* Build the command word. */ 1440 cmd = BCE_NVM_COMMAND_DOIT | cmd_flags; 1441 1442 /* Calculate the offset for buffered flash. */ 1443 if (sc->bce_flash_info->buffered) { 1444 offset = ((offset / sc->bce_flash_info->page_size) << 1445 sc->bce_flash_info->page_bits) + 1446 (offset % sc->bce_flash_info->page_size); 1447 } 1448 1449 /* 1450 * Clear the DONE bit separately, set the address to read, 1451 * and issue the read. 1452 */ 1453 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 1454 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 1455 REG_WR(sc, BCE_NVM_COMMAND, cmd); 1456 1457 /* Wait for completion. */ 1458 for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) { 1459 u32 val; 1460 1461 DELAY(5); 1462 1463 val = REG_RD(sc, BCE_NVM_COMMAND); 1464 if (val & BCE_NVM_COMMAND_DONE) { 1465 val = REG_RD(sc, BCE_NVM_READ); 1466 1467 val = bce_be32toh(val); 1468 memcpy(ret_val, &val, 4); 1469 break; 1470 } 1471 } 1472 1473 /* Check for errors. */ 1474 if (i >= NVRAM_TIMEOUT_COUNT) { 1475 BCE_PRINTF("%s(%d): Timeout error reading NVRAM at offset 0x%08X!\n", 1476 __FILE__, __LINE__, offset); 1477 rc = EBUSY; 1478 } 1479 1480 return(rc); 1481} 1482 1483 1484#ifdef BCE_NVRAM_WRITE_SUPPORT 1485/****************************************************************************/ 1486/* Write a dword (32 bits) to NVRAM. */ 1487/* */ 1488/* Write a 32 bit word to NVRAM. The caller is assumed to have already */ 1489/* obtained the NVRAM lock, enabled the controller for NVRAM access, and */ 1490/* enabled NVRAM write access. */ 1491/* */ 1492/* Returns: */ 1493/* 0 on success, positive value on failure. */ 1494/****************************************************************************/ 1495static int 1496bce_nvram_write_dword(struct bce_softc *sc, u32 offset, u8 *val, 1497 u32 cmd_flags) 1498{ 1499 u32 cmd, val32; 1500 int j; 1501 1502 /* Build the command word. */ 1503 cmd = BCE_NVM_COMMAND_DOIT | BCE_NVM_COMMAND_WR | cmd_flags; 1504 1505 /* Calculate the offset for buffered flash. */ 1506 if (sc->bce_flash_info->buffered) { 1507 offset = ((offset / sc->bce_flash_info->page_size) << 1508 sc->bce_flash_info->page_bits) + 1509 (offset % sc->bce_flash_info->page_size); 1510 } 1511 1512 /* 1513 * Clear the DONE bit separately, convert NVRAM data to big-endian, 1514 * set the NVRAM address to write, and issue the write command 1515 */ 1516 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 1517 memcpy(&val32, val, 4); 1518 val32 = htobe32(val32); 1519 REG_WR(sc, BCE_NVM_WRITE, val32); 1520 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 1521 REG_WR(sc, BCE_NVM_COMMAND, cmd); 1522 1523 /* Wait for completion. */ 1524 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1525 DELAY(5); 1526 1527 if (REG_RD(sc, BCE_NVM_COMMAND) & BCE_NVM_COMMAND_DONE) 1528 break; 1529 } 1530 if (j >= NVRAM_TIMEOUT_COUNT) { 1531 BCE_PRINTF("%s(%d): Timeout error writing NVRAM at offset 0x%08X\n", 1532 __FILE__, __LINE__, offset); 1533 return EBUSY; 1534 } 1535 1536 return 0; 1537} 1538#endif /* BCE_NVRAM_WRITE_SUPPORT */ 1539 1540 1541/****************************************************************************/ 1542/* Initialize NVRAM access. */ 1543/* */ 1544/* Identify the NVRAM device in use and prepare the NVRAM interface to */ 1545/* access that device. */ 1546/* */ 1547/* Returns: */ 1548/* 0 on success, positive value on failure. */ 1549/****************************************************************************/ 1550static int 1551bce_init_nvram(struct bce_softc *sc) 1552{ 1553 u32 val; 1554 int j, entry_count, rc; 1555 struct flash_spec *flash; 1556 1557 DBPRINT(sc,BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 1558 1559 /* Determine the selected interface. */ 1560 val = REG_RD(sc, BCE_NVM_CFG1); 1561 1562 entry_count = sizeof(flash_table) / sizeof(struct flash_spec); 1563 1564 rc = 0; 1565 1566 /* 1567 * Flash reconfiguration is required to support additional 1568 * NVRAM devices not directly supported in hardware. 1569 * Check if the flash interface was reconfigured 1570 * by the bootcode. 1571 */ 1572 1573 if (val & 0x40000000) { 1574 /* Flash interface reconfigured by bootcode. */ 1575 1576 DBPRINT(sc,BCE_INFO_LOAD, 1577 "bce_init_nvram(): Flash WAS reconfigured.\n"); 1578 1579 for (j = 0, flash = &flash_table[0]; j < entry_count; 1580 j++, flash++) { 1581 if ((val & FLASH_BACKUP_STRAP_MASK) == 1582 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) { 1583 sc->bce_flash_info = flash; 1584 break; 1585 } 1586 } 1587 } else { 1588 /* Flash interface not yet reconfigured. */ 1589 u32 mask; 1590 1591 DBPRINT(sc,BCE_INFO_LOAD, 1592 "bce_init_nvram(): Flash was NOT reconfigured.\n"); 1593 1594 if (val & (1 << 23)) 1595 mask = FLASH_BACKUP_STRAP_MASK; 1596 else 1597 mask = FLASH_STRAP_MASK; 1598 1599 /* Look for the matching NVRAM device configuration data. */ 1600 for (j = 0, flash = &flash_table[0]; j < entry_count; j++, flash++) { 1601 1602 /* Check if the device matches any of the known devices. */ 1603 if ((val & mask) == (flash->strapping & mask)) { 1604 /* Found a device match. */ 1605 sc->bce_flash_info = flash; 1606 1607 /* Request access to the flash interface. */ 1608 if ((rc = bce_acquire_nvram_lock(sc)) != 0) 1609 return rc; 1610 1611 /* Reconfigure the flash interface. */ 1612 bce_enable_nvram_access(sc); 1613 REG_WR(sc, BCE_NVM_CFG1, flash->config1); 1614 REG_WR(sc, BCE_NVM_CFG2, flash->config2); 1615 REG_WR(sc, BCE_NVM_CFG3, flash->config3); 1616 REG_WR(sc, BCE_NVM_WRITE1, flash->write1); 1617 bce_disable_nvram_access(sc); 1618 bce_release_nvram_lock(sc); 1619 1620 break; 1621 } 1622 } 1623 } 1624 1625 /* Check if a matching device was found. */ 1626 if (j == entry_count) { 1627 sc->bce_flash_info = NULL; 1628 BCE_PRINTF("%s(%d): Unknown Flash NVRAM found!\n", 1629 __FILE__, __LINE__); 1630 rc = ENODEV; 1631 } 1632 1633 /* Write the flash config data to the shared memory interface. */ 1634 val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_SHARED_HW_CFG_CONFIG2); 1635 val &= BCE_SHARED_HW_CFG2_NVM_SIZE_MASK; 1636 if (val) 1637 sc->bce_flash_size = val; 1638 else 1639 sc->bce_flash_size = sc->bce_flash_info->total_size; 1640 1641 DBPRINT(sc, BCE_INFO_LOAD, "bce_init_nvram() flash->total_size = 0x%08X\n", 1642 sc->bce_flash_info->total_size); 1643 1644 DBPRINT(sc,BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 1645 1646 return rc; 1647} 1648 1649 1650/****************************************************************************/ 1651/* Read an arbitrary range of data from NVRAM. */ 1652/* */ 1653/* Prepares the NVRAM interface for access and reads the requested data */ 1654/* into the supplied buffer. */ 1655/* */ 1656/* Returns: */ 1657/* 0 on success and the data read, positive value on failure. */ 1658/****************************************************************************/ 1659static int 1660bce_nvram_read(struct bce_softc *sc, u32 offset, u8 *ret_buf, 1661 int buf_size) 1662{ 1663 int rc = 0; 1664 u32 cmd_flags, offset32, len32, extra; 1665 1666 if (buf_size == 0) 1667 return 0; 1668 1669 /* Request access to the flash interface. */ 1670 if ((rc = bce_acquire_nvram_lock(sc)) != 0) 1671 return rc; 1672 1673 /* Enable access to flash interface */ 1674 bce_enable_nvram_access(sc); 1675 1676 len32 = buf_size; 1677 offset32 = offset; 1678 extra = 0; 1679 1680 cmd_flags = 0; 1681 1682 if (offset32 & 3) { 1683 u8 buf[4]; 1684 u32 pre_len; 1685 1686 offset32 &= ~3; 1687 pre_len = 4 - (offset & 3); 1688 1689 if (pre_len >= len32) { 1690 pre_len = len32; 1691 cmd_flags = BCE_NVM_COMMAND_FIRST | BCE_NVM_COMMAND_LAST; 1692 } 1693 else { 1694 cmd_flags = BCE_NVM_COMMAND_FIRST; 1695 } 1696 1697 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 1698 1699 if (rc) 1700 return rc; 1701 1702 memcpy(ret_buf, buf + (offset & 3), pre_len); 1703 1704 offset32 += 4; 1705 ret_buf += pre_len; 1706 len32 -= pre_len; 1707 } 1708 1709 if (len32 & 3) { 1710 extra = 4 - (len32 & 3); 1711 len32 = (len32 + 4) & ~3; 1712 } 1713 1714 if (len32 == 4) { 1715 u8 buf[4]; 1716 1717 if (cmd_flags) 1718 cmd_flags = BCE_NVM_COMMAND_LAST; 1719 else 1720 cmd_flags = BCE_NVM_COMMAND_FIRST | 1721 BCE_NVM_COMMAND_LAST; 1722 1723 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 1724 1725 memcpy(ret_buf, buf, 4 - extra); 1726 } 1727 else if (len32 > 0) { 1728 u8 buf[4]; 1729 1730 /* Read the first word. */ 1731 if (cmd_flags) 1732 cmd_flags = 0; 1733 else 1734 cmd_flags = BCE_NVM_COMMAND_FIRST; 1735 1736 rc = bce_nvram_read_dword(sc, offset32, ret_buf, cmd_flags); 1737 1738 /* Advance to the next dword. */ 1739 offset32 += 4; 1740 ret_buf += 4; 1741 len32 -= 4; 1742 1743 while (len32 > 4 && rc == 0) { 1744 rc = bce_nvram_read_dword(sc, offset32, ret_buf, 0); 1745 1746 /* Advance to the next dword. */ 1747 offset32 += 4; 1748 ret_buf += 4; 1749 len32 -= 4; 1750 } 1751 1752 if (rc) 1753 return rc; 1754 1755 cmd_flags = BCE_NVM_COMMAND_LAST; 1756 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 1757 1758 memcpy(ret_buf, buf, 4 - extra); 1759 } 1760 1761 /* Disable access to flash interface and release the lock. */ 1762 bce_disable_nvram_access(sc); 1763 bce_release_nvram_lock(sc); 1764 1765 return rc; 1766} 1767 1768 1769#ifdef BCE_NVRAM_WRITE_SUPPORT 1770/****************************************************************************/ 1771/* Write an arbitrary range of data from NVRAM. */ 1772/* */ 1773/* Prepares the NVRAM interface for write access and writes the requested */ 1774/* data from the supplied buffer. The caller is responsible for */ 1775/* calculating any appropriate CRCs. */ 1776/* */ 1777/* Returns: */ 1778/* 0 on success, positive value on failure. */ 1779/****************************************************************************/ 1780static int 1781bce_nvram_write(struct bce_softc *sc, u32 offset, u8 *data_buf, 1782 int buf_size) 1783{ 1784 u32 written, offset32, len32; 1785 u8 *buf, start[4], end[4]; 1786 int rc = 0; 1787 int align_start, align_end; 1788 1789 buf = data_buf; 1790 offset32 = offset; 1791 len32 = buf_size; 1792 align_start = align_end = 0; 1793 1794 if ((align_start = (offset32 & 3))) { 1795 offset32 &= ~3; 1796 len32 += align_start; 1797 if ((rc = bce_nvram_read(sc, offset32, start, 4))) 1798 return rc; 1799 } 1800 1801 if (len32 & 3) { 1802 if ((len32 > 4) || !align_start) { 1803 align_end = 4 - (len32 & 3); 1804 len32 += align_end; 1805 if ((rc = bce_nvram_read(sc, offset32 + len32 - 4, 1806 end, 4))) { 1807 return rc; 1808 } 1809 } 1810 } 1811 1812 if (align_start || align_end) { 1813 buf = malloc(len32, M_DEVBUF, M_NOWAIT); 1814 if (buf == 0) 1815 return ENOMEM; 1816 if (align_start) { 1817 memcpy(buf, start, 4); 1818 } 1819 if (align_end) { 1820 memcpy(buf + len32 - 4, end, 4); 1821 } 1822 memcpy(buf + align_start, data_buf, buf_size); 1823 } 1824 1825 written = 0; 1826 while ((written < len32) && (rc == 0)) { 1827 u32 page_start, page_end, data_start, data_end; 1828 u32 addr, cmd_flags; 1829 int i; 1830 u8 flash_buffer[264]; 1831 1832 /* Find the page_start addr */ 1833 page_start = offset32 + written; 1834 page_start -= (page_start % sc->bce_flash_info->page_size); 1835 /* Find the page_end addr */ 1836 page_end = page_start + sc->bce_flash_info->page_size; 1837 /* Find the data_start addr */ 1838 data_start = (written == 0) ? offset32 : page_start; 1839 /* Find the data_end addr */ 1840 data_end = (page_end > offset32 + len32) ? 1841 (offset32 + len32) : page_end; 1842 1843 /* Request access to the flash interface. */ 1844 if ((rc = bce_acquire_nvram_lock(sc)) != 0) 1845 goto nvram_write_end; 1846 1847 /* Enable access to flash interface */ 1848 bce_enable_nvram_access(sc); 1849 1850 cmd_flags = BCE_NVM_COMMAND_FIRST; 1851 if (sc->bce_flash_info->buffered == 0) { 1852 int j; 1853 1854 /* Read the whole page into the buffer 1855 * (non-buffer flash only) */ 1856 for (j = 0; j < sc->bce_flash_info->page_size; j += 4) { 1857 if (j == (sc->bce_flash_info->page_size - 4)) { 1858 cmd_flags |= BCE_NVM_COMMAND_LAST; 1859 } 1860 rc = bce_nvram_read_dword(sc, 1861 page_start + j, 1862 &flash_buffer[j], 1863 cmd_flags); 1864 1865 if (rc) 1866 goto nvram_write_end; 1867 1868 cmd_flags = 0; 1869 } 1870 } 1871 1872 /* Enable writes to flash interface (unlock write-protect) */ 1873 if ((rc = bce_enable_nvram_write(sc)) != 0) 1874 goto nvram_write_end; 1875 1876 /* Erase the page */ 1877 if ((rc = bce_nvram_erase_page(sc, page_start)) != 0) 1878 goto nvram_write_end; 1879 1880 /* Re-enable the write again for the actual write */ 1881 bce_enable_nvram_write(sc); 1882 1883 /* Loop to write back the buffer data from page_start to 1884 * data_start */ 1885 i = 0; 1886 if (sc->bce_flash_info->buffered == 0) { 1887 for (addr = page_start; addr < data_start; 1888 addr += 4, i += 4) { 1889 1890 rc = bce_nvram_write_dword(sc, addr, 1891 &flash_buffer[i], cmd_flags); 1892 1893 if (rc != 0) 1894 goto nvram_write_end; 1895 1896 cmd_flags = 0; 1897 } 1898 } 1899 1900 /* Loop to write the new data from data_start to data_end */ 1901 for (addr = data_start; addr < data_end; addr += 4, i++) { 1902 if ((addr == page_end - 4) || 1903 ((sc->bce_flash_info->buffered) && 1904 (addr == data_end - 4))) { 1905 1906 cmd_flags |= BCE_NVM_COMMAND_LAST; 1907 } 1908 rc = bce_nvram_write_dword(sc, addr, buf, 1909 cmd_flags); 1910 1911 if (rc != 0) 1912 goto nvram_write_end; 1913 1914 cmd_flags = 0; 1915 buf += 4; 1916 } 1917 1918 /* Loop to write back the buffer data from data_end 1919 * to page_end */ 1920 if (sc->bce_flash_info->buffered == 0) { 1921 for (addr = data_end; addr < page_end; 1922 addr += 4, i += 4) { 1923 1924 if (addr == page_end-4) { 1925 cmd_flags = BCE_NVM_COMMAND_LAST; 1926 } 1927 rc = bce_nvram_write_dword(sc, addr, 1928 &flash_buffer[i], cmd_flags); 1929 1930 if (rc != 0) 1931 goto nvram_write_end; 1932 1933 cmd_flags = 0; 1934 } 1935 } 1936 1937 /* Disable writes to flash interface (lock write-protect) */ 1938 bce_disable_nvram_write(sc); 1939 1940 /* Disable access to flash interface */ 1941 bce_disable_nvram_access(sc); 1942 bce_release_nvram_lock(sc); 1943 1944 /* Increment written */ 1945 written += data_end - data_start; 1946 } 1947 1948nvram_write_end: 1949 if (align_start || align_end) 1950 free(buf, M_DEVBUF); 1951 1952 return rc; 1953} 1954#endif /* BCE_NVRAM_WRITE_SUPPORT */ 1955 1956 1957/****************************************************************************/ 1958/* Verifies that NVRAM is accessible and contains valid data. */ 1959/* */ 1960/* Reads the configuration data from NVRAM and verifies that the CRC is */ 1961/* correct. */ 1962/* */ 1963/* Returns: */ 1964/* 0 on success, positive value on failure. */ 1965/****************************************************************************/ 1966static int 1967bce_nvram_test(struct bce_softc *sc) 1968{ 1969 u32 buf[BCE_NVRAM_SIZE / 4]; 1970 u8 *data = (u8 *) buf; 1971 int rc = 0; 1972 u32 magic, csum; 1973 1974 1975 /* 1976 * Check that the device NVRAM is valid by reading 1977 * the magic value at offset 0. 1978 */ 1979 if ((rc = bce_nvram_read(sc, 0, data, 4)) != 0) 1980 goto bce_nvram_test_done; 1981 1982 1983 magic = bce_be32toh(buf[0]); 1984 if (magic != BCE_NVRAM_MAGIC) { 1985 rc = ENODEV; 1986 BCE_PRINTF("%s(%d): Invalid NVRAM magic value! Expected: 0x%08X, " 1987 "Found: 0x%08X\n", 1988 __FILE__, __LINE__, BCE_NVRAM_MAGIC, magic); 1989 goto bce_nvram_test_done; 1990 } 1991 1992 /* 1993 * Verify that the device NVRAM includes valid 1994 * configuration data. 1995 */ 1996 if ((rc = bce_nvram_read(sc, 0x100, data, BCE_NVRAM_SIZE)) != 0) 1997 goto bce_nvram_test_done; 1998 1999 csum = ether_crc32_le(data, 0x100); 2000 if (csum != BCE_CRC32_RESIDUAL) { 2001 rc = ENODEV; 2002 BCE_PRINTF("%s(%d): Invalid Manufacturing Information NVRAM CRC! " 2003 "Expected: 0x%08X, Found: 0x%08X\n", 2004 __FILE__, __LINE__, BCE_CRC32_RESIDUAL, csum); 2005 goto bce_nvram_test_done; 2006 } 2007 2008 csum = ether_crc32_le(data + 0x100, 0x100); 2009 if (csum != BCE_CRC32_RESIDUAL) { 2010 BCE_PRINTF("%s(%d): Invalid Feature Configuration Information " 2011 "NVRAM CRC! Expected: 0x%08X, Found: 08%08X\n", 2012 __FILE__, __LINE__, BCE_CRC32_RESIDUAL, csum); 2013 rc = ENODEV; 2014 } 2015 2016bce_nvram_test_done: 2017 return rc; 2018} 2019 2020 2021/****************************************************************************/ 2022/* Free any DMA memory owned by the driver. */ 2023/* */ 2024/* Scans through each data structre that requires DMA memory and frees */ 2025/* the memory if allocated. */ 2026/* */ 2027/* Returns: */ 2028/* Nothing. */ 2029/****************************************************************************/ 2030static void 2031bce_dma_free(struct bce_softc *sc) 2032{ 2033 int i; 2034 2035 DBPRINT(sc,BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 2036 2037 /* Destroy the status block. */ 2038 if (sc->status_block != NULL) 2039 bus_dmamem_free( 2040 sc->status_tag, 2041 sc->status_block, 2042 sc->status_map); 2043 2044 if (sc->status_map != NULL) { 2045 bus_dmamap_unload( 2046 sc->status_tag, 2047 sc->status_map); 2048 bus_dmamap_destroy(sc->status_tag, 2049 sc->status_map); 2050 } 2051 2052 if (sc->status_tag != NULL) 2053 bus_dma_tag_destroy(sc->status_tag); 2054 2055 2056 /* Destroy the statistics block. */ 2057 if (sc->stats_block != NULL) 2058 bus_dmamem_free( 2059 sc->stats_tag, 2060 sc->stats_block, 2061 sc->stats_map); 2062 2063 if (sc->stats_map != NULL) { 2064 bus_dmamap_unload( 2065 sc->stats_tag, 2066 sc->stats_map); 2067 bus_dmamap_destroy(sc->stats_tag, 2068 sc->stats_map); 2069 } 2070 2071 if (sc->stats_tag != NULL) 2072 bus_dma_tag_destroy(sc->stats_tag); 2073 2074 2075 /* Free, unmap and destroy all TX buffer descriptor chain pages. */ 2076 for (i = 0; i < TX_PAGES; i++ ) { 2077 if (sc->tx_bd_chain[i] != NULL) 2078 bus_dmamem_free( 2079 sc->tx_bd_chain_tag, 2080 sc->tx_bd_chain[i], 2081 sc->tx_bd_chain_map[i]); 2082 2083 if (sc->tx_bd_chain_map[i] != NULL) { 2084 bus_dmamap_unload( 2085 sc->tx_bd_chain_tag, 2086 sc->tx_bd_chain_map[i]); 2087 bus_dmamap_destroy( 2088 sc->tx_bd_chain_tag, 2089 sc->tx_bd_chain_map[i]); 2090 } 2091 2092 } 2093 2094 /* Destroy the TX buffer descriptor tag. */ 2095 if (sc->tx_bd_chain_tag != NULL) 2096 bus_dma_tag_destroy(sc->tx_bd_chain_tag); 2097 2098 2099 /* Free, unmap and destroy all RX buffer descriptor chain pages. */ 2100 for (i = 0; i < RX_PAGES; i++ ) { 2101 if (sc->rx_bd_chain[i] != NULL) 2102 bus_dmamem_free( 2103 sc->rx_bd_chain_tag, 2104 sc->rx_bd_chain[i], 2105 sc->rx_bd_chain_map[i]); 2106 2107 if (sc->rx_bd_chain_map[i] != NULL) { 2108 bus_dmamap_unload( 2109 sc->rx_bd_chain_tag, 2110 sc->rx_bd_chain_map[i]); 2111 bus_dmamap_destroy( 2112 sc->rx_bd_chain_tag, 2113 sc->rx_bd_chain_map[i]); 2114 } 2115 } 2116 2117 /* Destroy the RX buffer descriptor tag. */ 2118 if (sc->rx_bd_chain_tag != NULL) 2119 bus_dma_tag_destroy(sc->rx_bd_chain_tag); 2120 2121 2122 /* Unload and destroy the TX mbuf maps. */ 2123 for (i = 0; i < TOTAL_TX_BD; i++) { 2124 if (sc->tx_mbuf_map[i] != NULL) { 2125 bus_dmamap_unload(sc->tx_mbuf_tag, 2126 sc->tx_mbuf_map[i]); 2127 bus_dmamap_destroy(sc->tx_mbuf_tag, 2128 sc->tx_mbuf_map[i]); 2129 } 2130 } 2131 2132 /* Destroy the TX mbuf tag. */ 2133 if (sc->tx_mbuf_tag != NULL) 2134 bus_dma_tag_destroy(sc->tx_mbuf_tag); 2135 2136 2137 /* Unload and destroy the RX mbuf maps. */ 2138 for (i = 0; i < TOTAL_RX_BD; i++) { 2139 if (sc->rx_mbuf_map[i] != NULL) { 2140 bus_dmamap_unload(sc->rx_mbuf_tag, 2141 sc->rx_mbuf_map[i]); 2142 bus_dmamap_destroy(sc->rx_mbuf_tag, 2143 sc->rx_mbuf_map[i]); 2144 } 2145 } 2146 2147 /* Destroy the RX mbuf tag. */ 2148 if (sc->rx_mbuf_tag != NULL) 2149 bus_dma_tag_destroy(sc->rx_mbuf_tag); 2150 2151 2152 /* Destroy the parent tag */ 2153 if (sc->parent_tag != NULL) 2154 bus_dma_tag_destroy(sc->parent_tag); 2155 2156 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 2157 2158} 2159 2160 2161/****************************************************************************/ 2162/* Get DMA memory from the OS. */ 2163/* */ 2164/* Validates that the OS has provided DMA buffers in response to a */ 2165/* bus_dmamap_load() call and saves the physical address of those buffers. */ 2166/* When the callback is used the OS will return 0 for the mapping function */ 2167/* (bus_dmamap_load()) so we use the value of map_arg->maxsegs to pass any */ 2168/* failures back to the caller. */ 2169/* */ 2170/* Returns: */ 2171/* Nothing. */ 2172/****************************************************************************/ 2173static void 2174bce_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2175{ 2176 bus_addr_t *busaddr = arg; 2177 2178 /* Simulate a mapping failure. */ 2179 DBRUNIF(DB_RANDOMTRUE(bce_debug_dma_map_addr_failure), 2180 printf("bce: %s(%d): Simulating DMA mapping error.\n", 2181 __FILE__, __LINE__); 2182 error = ENOMEM); 2183 2184 /* Check for an error and signal the caller that an error occurred. */ 2185 if (error) { 2186 printf("bce %s(%d): DMA mapping error! error = %d, " 2187 "nseg = %d\n", __FILE__, __LINE__, error, nseg); 2188 *busaddr = 0; 2189 return; 2190 } 2191 2192 *busaddr = segs->ds_addr; 2193 return; 2194} 2195 2196 2197/****************************************************************************/ 2198/* Allocate any DMA memory needed by the driver. */ 2199/* */ 2200/* Allocates DMA memory needed for the various global structures needed by */ 2201/* hardware. */ 2202/* */ 2203/* Returns: */ 2204/* 0 for success, positive value for failure. */ 2205/****************************************************************************/ 2206static int 2207bce_dma_alloc(device_t dev) 2208{ 2209 struct bce_softc *sc; 2210 int i, error, rc = 0; 2211 bus_addr_t busaddr; 2212 bus_size_t max_size, max_seg_size; 2213 int max_segments; 2214 2215 sc = device_get_softc(dev); 2216 2217 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 2218 2219 /* 2220 * Allocate the parent bus DMA tag appropriate for PCI. 2221 */ 2222 if (bus_dma_tag_create(NULL, 2223 1, 2224 BCE_DMA_BOUNDARY, 2225 sc->max_bus_addr, 2226 BUS_SPACE_MAXADDR, 2227 NULL, NULL, 2228 MAXBSIZE, 2229 BUS_SPACE_UNRESTRICTED, 2230 BUS_SPACE_MAXSIZE_32BIT, 2231 0, 2232 NULL, NULL, 2233 &sc->parent_tag)) { 2234 BCE_PRINTF("%s(%d): Could not allocate parent DMA tag!\n", 2235 __FILE__, __LINE__); 2236 rc = ENOMEM; 2237 goto bce_dma_alloc_exit; 2238 } 2239 2240 /* 2241 * Create a DMA tag for the status block, allocate and clear the 2242 * memory, map the memory into DMA space, and fetch the physical 2243 * address of the block. 2244 */ 2245 if (bus_dma_tag_create(sc->parent_tag, 2246 BCE_DMA_ALIGN, 2247 BCE_DMA_BOUNDARY, 2248 sc->max_bus_addr, 2249 BUS_SPACE_MAXADDR, 2250 NULL, NULL, 2251 BCE_STATUS_BLK_SZ, 2252 1, 2253 BCE_STATUS_BLK_SZ, 2254 0, 2255 NULL, NULL, 2256 &sc->status_tag)) { 2257 BCE_PRINTF("%s(%d): Could not allocate status block DMA tag!\n", 2258 __FILE__, __LINE__); 2259 rc = ENOMEM; 2260 goto bce_dma_alloc_exit; 2261 } 2262 2263 if(bus_dmamem_alloc(sc->status_tag, 2264 (void **)&sc->status_block, 2265 BUS_DMA_NOWAIT, 2266 &sc->status_map)) { 2267 BCE_PRINTF("%s(%d): Could not allocate status block DMA memory!\n", 2268 __FILE__, __LINE__); 2269 rc = ENOMEM; 2270 goto bce_dma_alloc_exit; 2271 } 2272 2273 bzero((char *)sc->status_block, BCE_STATUS_BLK_SZ); 2274 2275 error = bus_dmamap_load(sc->status_tag, 2276 sc->status_map, 2277 sc->status_block, 2278 BCE_STATUS_BLK_SZ, 2279 bce_dma_map_addr, 2280 &busaddr, 2281 BUS_DMA_NOWAIT); 2282 2283 if (error) { 2284 BCE_PRINTF("%s(%d): Could not map status block DMA memory!\n", 2285 __FILE__, __LINE__); 2286 rc = ENOMEM; 2287 goto bce_dma_alloc_exit; 2288 } 2289 2290 sc->status_block_paddr = busaddr; 2291 /* DRC - Fix for 64 bit addresses. */ 2292 DBPRINT(sc, BCE_INFO, "status_block_paddr = 0x%08X\n", 2293 (u32) sc->status_block_paddr); 2294 2295 /* 2296 * Create a DMA tag for the statistics block, allocate and clear the 2297 * memory, map the memory into DMA space, and fetch the physical 2298 * address of the block. 2299 */ 2300 if (bus_dma_tag_create(sc->parent_tag, 2301 BCE_DMA_ALIGN, 2302 BCE_DMA_BOUNDARY, 2303 sc->max_bus_addr, 2304 BUS_SPACE_MAXADDR, 2305 NULL, NULL, 2306 BCE_STATS_BLK_SZ, 2307 1, 2308 BCE_STATS_BLK_SZ, 2309 0, 2310 NULL, NULL, 2311 &sc->stats_tag)) { 2312 BCE_PRINTF("%s(%d): Could not allocate statistics block DMA tag!\n", 2313 __FILE__, __LINE__); 2314 rc = ENOMEM; 2315 goto bce_dma_alloc_exit; 2316 } 2317 2318 if (bus_dmamem_alloc(sc->stats_tag, 2319 (void **)&sc->stats_block, 2320 BUS_DMA_NOWAIT, 2321 &sc->stats_map)) { 2322 BCE_PRINTF("%s(%d): Could not allocate statistics block DMA memory!\n", 2323 __FILE__, __LINE__); 2324 rc = ENOMEM; 2325 goto bce_dma_alloc_exit; 2326 } 2327 2328 bzero((char *)sc->stats_block, BCE_STATS_BLK_SZ); 2329 2330 error = bus_dmamap_load(sc->stats_tag, 2331 sc->stats_map, 2332 sc->stats_block, 2333 BCE_STATS_BLK_SZ, 2334 bce_dma_map_addr, 2335 &busaddr, 2336 BUS_DMA_NOWAIT); 2337 2338 if(error) { 2339 BCE_PRINTF("%s(%d): Could not map statistics block DMA memory!\n", 2340 __FILE__, __LINE__); 2341 rc = ENOMEM; 2342 goto bce_dma_alloc_exit; 2343 } 2344 2345 sc->stats_block_paddr = busaddr; 2346 /* DRC - Fix for 64 bit address. */ 2347 DBPRINT(sc,BCE_INFO, "stats_block_paddr = 0x%08X\n", 2348 (u32) sc->stats_block_paddr); 2349 2350 /* 2351 * Create a DMA tag for the TX buffer descriptor chain, 2352 * allocate and clear the memory, and fetch the 2353 * physical address of the block. 2354 */ 2355 if(bus_dma_tag_create(sc->parent_tag, 2356 BCM_PAGE_SIZE, 2357 BCE_DMA_BOUNDARY, 2358 sc->max_bus_addr, 2359 BUS_SPACE_MAXADDR, 2360 NULL, NULL, 2361 BCE_TX_CHAIN_PAGE_SZ, 2362 1, 2363 BCE_TX_CHAIN_PAGE_SZ, 2364 0, 2365 NULL, NULL, 2366 &sc->tx_bd_chain_tag)) { 2367 BCE_PRINTF("%s(%d): Could not allocate TX descriptor chain DMA tag!\n", 2368 __FILE__, __LINE__); 2369 rc = ENOMEM; 2370 goto bce_dma_alloc_exit; 2371 } 2372 2373 for (i = 0; i < TX_PAGES; i++) { 2374 2375 if(bus_dmamem_alloc(sc->tx_bd_chain_tag, 2376 (void **)&sc->tx_bd_chain[i], 2377 BUS_DMA_NOWAIT, 2378 &sc->tx_bd_chain_map[i])) { 2379 BCE_PRINTF("%s(%d): Could not allocate TX descriptor " 2380 "chain DMA memory!\n", __FILE__, __LINE__); 2381 rc = ENOMEM; 2382 goto bce_dma_alloc_exit; 2383 } 2384 2385 error = bus_dmamap_load(sc->tx_bd_chain_tag, 2386 sc->tx_bd_chain_map[i], 2387 sc->tx_bd_chain[i], 2388 BCE_TX_CHAIN_PAGE_SZ, 2389 bce_dma_map_addr, 2390 &busaddr, 2391 BUS_DMA_NOWAIT); 2392 2393 if (error) { 2394 BCE_PRINTF("%s(%d): Could not map TX descriptor chain DMA memory!\n", 2395 __FILE__, __LINE__); 2396 rc = ENOMEM; 2397 goto bce_dma_alloc_exit; 2398 } 2399 2400 sc->tx_bd_chain_paddr[i] = busaddr; 2401 /* DRC - Fix for 64 bit systems. */ 2402 DBPRINT(sc, BCE_INFO, "tx_bd_chain_paddr[%d] = 0x%08X\n", 2403 i, (u32) sc->tx_bd_chain_paddr[i]); 2404 } 2405 2406 /* Check the required size before mapping to conserve resources. */ 2407 if (bce_tso_enable) { 2408 max_size = BCE_TSO_MAX_SIZE; 2409 max_segments = BCE_MAX_SEGMENTS; 2410 max_seg_size = BCE_TSO_MAX_SEG_SIZE; 2411 } else { 2412 max_size = MCLBYTES * BCE_MAX_SEGMENTS; 2413 max_segments = BCE_MAX_SEGMENTS; 2414 max_seg_size = MCLBYTES; 2415 } 2416 2417 /* Create a DMA tag for TX mbufs. */ 2418 if (bus_dma_tag_create(sc->parent_tag, 2419 1, 2420 BCE_DMA_BOUNDARY, 2421 sc->max_bus_addr, 2422 BUS_SPACE_MAXADDR, 2423 NULL, NULL, 2424 max_size, 2425 max_segments, 2426 max_seg_size, 2427 0, 2428 NULL, NULL, 2429 &sc->tx_mbuf_tag)) { 2430 BCE_PRINTF("%s(%d): Could not allocate TX mbuf DMA tag!\n", 2431 __FILE__, __LINE__); 2432 rc = ENOMEM; 2433 goto bce_dma_alloc_exit; 2434 } 2435 2436 /* Create DMA maps for the TX mbufs clusters. */ 2437 for (i = 0; i < TOTAL_TX_BD; i++) { 2438 if (bus_dmamap_create(sc->tx_mbuf_tag, BUS_DMA_NOWAIT, 2439 &sc->tx_mbuf_map[i])) { 2440 BCE_PRINTF("%s(%d): Unable to create TX mbuf DMA map!\n", 2441 __FILE__, __LINE__); 2442 rc = ENOMEM; 2443 goto bce_dma_alloc_exit; 2444 } 2445 } 2446 2447 /* 2448 * Create a DMA tag for the RX buffer descriptor chain, 2449 * allocate and clear the memory, and fetch the physical 2450 * address of the blocks. 2451 */ 2452 if (bus_dma_tag_create(sc->parent_tag, 2453 BCM_PAGE_SIZE, 2454 BCE_DMA_BOUNDARY, 2455 BUS_SPACE_MAXADDR, 2456 sc->max_bus_addr, 2457 NULL, NULL, 2458 BCE_RX_CHAIN_PAGE_SZ, 2459 1, 2460 BCE_RX_CHAIN_PAGE_SZ, 2461 0, 2462 NULL, NULL, 2463 &sc->rx_bd_chain_tag)) { 2464 BCE_PRINTF("%s(%d): Could not allocate RX descriptor chain DMA tag!\n", 2465 __FILE__, __LINE__); 2466 rc = ENOMEM; 2467 goto bce_dma_alloc_exit; 2468 } 2469 2470 for (i = 0; i < RX_PAGES; i++) { 2471 2472 if (bus_dmamem_alloc(sc->rx_bd_chain_tag, 2473 (void **)&sc->rx_bd_chain[i], 2474 BUS_DMA_NOWAIT, 2475 &sc->rx_bd_chain_map[i])) { 2476 BCE_PRINTF("%s(%d): Could not allocate RX descriptor chain " 2477 "DMA memory!\n", __FILE__, __LINE__); 2478 rc = ENOMEM; 2479 goto bce_dma_alloc_exit; 2480 } 2481 2482 bzero((char *)sc->rx_bd_chain[i], BCE_RX_CHAIN_PAGE_SZ); 2483 2484 error = bus_dmamap_load(sc->rx_bd_chain_tag, 2485 sc->rx_bd_chain_map[i], 2486 sc->rx_bd_chain[i], 2487 BCE_RX_CHAIN_PAGE_SZ, 2488 bce_dma_map_addr, 2489 &busaddr, 2490 BUS_DMA_NOWAIT); 2491 2492 if (error) { 2493 BCE_PRINTF("%s(%d): Could not map RX descriptor chain DMA memory!\n", 2494 __FILE__, __LINE__); 2495 rc = ENOMEM; 2496 goto bce_dma_alloc_exit; 2497 } 2498 2499 sc->rx_bd_chain_paddr[i] = busaddr; 2500 /* DRC - Fix for 64 bit systems. */ 2501 DBPRINT(sc, BCE_INFO, "rx_bd_chain_paddr[%d] = 0x%08X\n", 2502 i, (u32) sc->rx_bd_chain_paddr[i]); 2503 } 2504 2505 /* 2506 * Create a DMA tag for RX mbufs. 2507 */ 2508 if (bus_dma_tag_create(sc->parent_tag, 2509 1, 2510 BCE_DMA_BOUNDARY, 2511 sc->max_bus_addr, 2512 BUS_SPACE_MAXADDR, 2513 NULL, NULL, 2514 MJUM9BYTES, 2515 BCE_MAX_SEGMENTS, 2516 MJUM9BYTES, 2517 0, 2518 NULL, NULL, 2519 &sc->rx_mbuf_tag)) { 2520 BCE_PRINTF("%s(%d): Could not allocate RX mbuf DMA tag!\n", 2521 __FILE__, __LINE__); 2522 rc = ENOMEM; 2523 goto bce_dma_alloc_exit; 2524 } 2525 2526 /* Create DMA maps for the RX mbuf clusters. */ 2527 for (i = 0; i < TOTAL_RX_BD; i++) { 2528 if (bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_NOWAIT, 2529 &sc->rx_mbuf_map[i])) { 2530 BCE_PRINTF("%s(%d): Unable to create RX mbuf DMA map!\n", 2531 __FILE__, __LINE__); 2532 rc = ENOMEM; 2533 goto bce_dma_alloc_exit; 2534 } 2535 } 2536 2537bce_dma_alloc_exit: 2538 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 2539 2540 return(rc); 2541} 2542 2543 2544/****************************************************************************/ 2545/* Release all resources used by the driver. */ 2546/* */ 2547/* Releases all resources acquired by the driver including interrupts, */ 2548/* interrupt handler, interfaces, mutexes, and DMA memory. */ 2549/* */ 2550/* Returns: */ 2551/* Nothing. */ 2552/****************************************************************************/ 2553static void 2554bce_release_resources(struct bce_softc *sc) 2555{ 2556 device_t dev; 2557 2558 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 2559 2560 dev = sc->bce_dev; 2561 2562 bce_dma_free(sc); 2563 2564 if (sc->bce_intrhand != NULL) { 2565 DBPRINT(sc, BCE_INFO_RESET, "Removing interrupt handler.\n"); 2566 bus_teardown_intr(dev, sc->bce_res_irq, sc->bce_intrhand); 2567 } 2568 2569 if (sc->bce_res_irq != NULL) { 2570 DBPRINT(sc, BCE_INFO_RESET, "Releasing IRQ.\n"); 2571 bus_release_resource(dev, SYS_RES_IRQ, sc->bce_flags & BCE_USING_MSI_FLAG ? 1 : 0, 2572 sc->bce_res_irq); 2573 } 2574 2575 if (sc->bce_flags & BCE_USING_MSI_FLAG) { 2576 DBPRINT(sc, BCE_INFO_RESET, "Releasing MSI vector.\n"); 2577 pci_release_msi(dev); 2578 } 2579 2580 if (sc->bce_res_mem != NULL) { 2581 DBPRINT(sc, BCE_INFO_RESET, "Releasing PCI memory.\n"); 2582 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0), sc->bce_res_mem); 2583 } 2584 2585 if (sc->bce_ifp != NULL) { 2586 DBPRINT(sc, BCE_INFO_RESET, "Releasing IF.\n"); 2587 if_free(sc->bce_ifp); 2588 } 2589 2590 if (mtx_initialized(&sc->bce_mtx)) 2591 BCE_LOCK_DESTROY(sc); 2592 2593 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 2594 2595} 2596 2597 2598/****************************************************************************/ 2599/* Firmware synchronization. */ 2600/* */ 2601/* Before performing certain events such as a chip reset, synchronize with */ 2602/* the firmware first. */ 2603/* */ 2604/* Returns: */ 2605/* 0 for success, positive value for failure. */ 2606/****************************************************************************/ 2607static int 2608bce_fw_sync(struct bce_softc *sc, u32 msg_data) 2609{ 2610 int i, rc = 0; 2611 u32 val; 2612 2613 /* Don't waste any time if we've timed out before. */ 2614 if (sc->bce_fw_timed_out) { 2615 rc = EBUSY; 2616 goto bce_fw_sync_exit; 2617 } 2618 2619 /* Increment the message sequence number. */ 2620 sc->bce_fw_wr_seq++; 2621 msg_data |= sc->bce_fw_wr_seq; 2622 2623 DBPRINT(sc, BCE_VERBOSE, "bce_fw_sync(): msg_data = 0x%08X\n", msg_data); 2624 2625 /* Send the message to the bootcode driver mailbox. */ 2626 REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_MB, msg_data); 2627 2628 /* Wait for the bootcode to acknowledge the message. */ 2629 for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) { 2630 /* Check for a response in the bootcode firmware mailbox. */ 2631 val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_FW_MB); 2632 if ((val & BCE_FW_MSG_ACK) == (msg_data & BCE_DRV_MSG_SEQ)) 2633 break; 2634 DELAY(1000); 2635 } 2636 2637 /* If we've timed out, tell the bootcode that we've stopped waiting. */ 2638 if (((val & BCE_FW_MSG_ACK) != (msg_data & BCE_DRV_MSG_SEQ)) && 2639 ((msg_data & BCE_DRV_MSG_DATA) != BCE_DRV_MSG_DATA_WAIT0)) { 2640 2641 BCE_PRINTF("%s(%d): Firmware synchronization timeout! " 2642 "msg_data = 0x%08X\n", 2643 __FILE__, __LINE__, msg_data); 2644 2645 msg_data &= ~BCE_DRV_MSG_CODE; 2646 msg_data |= BCE_DRV_MSG_CODE_FW_TIMEOUT; 2647 2648 REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_MB, msg_data); 2649 2650 sc->bce_fw_timed_out = 1; 2651 rc = EBUSY; 2652 } 2653 2654bce_fw_sync_exit: 2655 return (rc); 2656} 2657 2658 2659/****************************************************************************/ 2660/* Load Receive Virtual 2 Physical (RV2P) processor firmware. */ 2661/* */ 2662/* Returns: */ 2663/* Nothing. */ 2664/****************************************************************************/ 2665static void 2666bce_load_rv2p_fw(struct bce_softc *sc, u32 *rv2p_code, 2667 u32 rv2p_code_len, u32 rv2p_proc) 2668{ 2669 int i; 2670 u32 val; 2671 2672 for (i = 0; i < rv2p_code_len; i += 8) { 2673 REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code); 2674 rv2p_code++; 2675 REG_WR(sc, BCE_RV2P_INSTR_LOW, *rv2p_code); 2676 rv2p_code++; 2677 2678 if (rv2p_proc == RV2P_PROC1) { 2679 val = (i / 8) | BCE_RV2P_PROC1_ADDR_CMD_RDWR; 2680 REG_WR(sc, BCE_RV2P_PROC1_ADDR_CMD, val); 2681 } 2682 else { 2683 val = (i / 8) | BCE_RV2P_PROC2_ADDR_CMD_RDWR; 2684 REG_WR(sc, BCE_RV2P_PROC2_ADDR_CMD, val); 2685 } 2686 } 2687 2688 /* Reset the processor, un-stall is done later. */ 2689 if (rv2p_proc == RV2P_PROC1) { 2690 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET); 2691 } 2692 else { 2693 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET); 2694 } 2695} 2696 2697 2698/****************************************************************************/ 2699/* Load RISC processor firmware. */ 2700/* */ 2701/* Loads firmware from the file if_bcefw.h into the scratchpad memory */ 2702/* associated with a particular processor. */ 2703/* */ 2704/* Returns: */ 2705/* Nothing. */ 2706/****************************************************************************/ 2707static void 2708bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg, 2709 struct fw_info *fw) 2710{ 2711 u32 offset; 2712 u32 val; 2713 2714 /* Halt the CPU. */ 2715 val = REG_RD_IND(sc, cpu_reg->mode); 2716 val |= cpu_reg->mode_value_halt; 2717 REG_WR_IND(sc, cpu_reg->mode, val); 2718 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 2719 2720 /* Load the Text area. */ 2721 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base); 2722 if (fw->text) { 2723 int j; 2724 2725 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) { 2726 REG_WR_IND(sc, offset, fw->text[j]); 2727 } 2728 } 2729 2730 /* Load the Data area. */ 2731 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base); 2732 if (fw->data) { 2733 int j; 2734 2735 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) { 2736 REG_WR_IND(sc, offset, fw->data[j]); 2737 } 2738 } 2739 2740 /* Load the SBSS area. */ 2741 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base); 2742 if (fw->sbss) { 2743 int j; 2744 2745 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) { 2746 REG_WR_IND(sc, offset, fw->sbss[j]); 2747 } 2748 } 2749 2750 /* Load the BSS area. */ 2751 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base); 2752 if (fw->bss) { 2753 int j; 2754 2755 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) { 2756 REG_WR_IND(sc, offset, fw->bss[j]); 2757 } 2758 } 2759 2760 /* Load the Read-Only area. */ 2761 offset = cpu_reg->spad_base + 2762 (fw->rodata_addr - cpu_reg->mips_view_base); 2763 if (fw->rodata) { 2764 int j; 2765 2766 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) { 2767 REG_WR_IND(sc, offset, fw->rodata[j]); 2768 } 2769 } 2770 2771 /* Clear the pre-fetch instruction. */ 2772 REG_WR_IND(sc, cpu_reg->inst, 0); 2773 REG_WR_IND(sc, cpu_reg->pc, fw->start_addr); 2774 2775 /* Start the CPU. */ 2776 val = REG_RD_IND(sc, cpu_reg->mode); 2777 val &= ~cpu_reg->mode_value_halt; 2778 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 2779 REG_WR_IND(sc, cpu_reg->mode, val); 2780} 2781 2782 2783/****************************************************************************/ 2784/* Initialize the RV2P, RX, TX, TPAT, and COM CPUs. */ 2785/* */ 2786/* Loads the firmware for each CPU and starts the CPU. */ 2787/* */ 2788/* Returns: */ 2789/* Nothing. */ 2790/****************************************************************************/ 2791static void 2792bce_init_cpus(struct bce_softc *sc) 2793{ 2794 struct cpu_reg cpu_reg; 2795 struct fw_info fw; 2796 2797 /* Initialize the RV2P processor. */ 2798 bce_load_rv2p_fw(sc, bce_rv2p_proc1, sizeof(bce_rv2p_proc1), RV2P_PROC1); 2799 bce_load_rv2p_fw(sc, bce_rv2p_proc2, sizeof(bce_rv2p_proc2), RV2P_PROC2); 2800 2801 /* Initialize the RX Processor. */ 2802 cpu_reg.mode = BCE_RXP_CPU_MODE; 2803 cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT; 2804 cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA; 2805 cpu_reg.state = BCE_RXP_CPU_STATE; 2806 cpu_reg.state_value_clear = 0xffffff; 2807 cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE; 2808 cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK; 2809 cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER; 2810 cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION; 2811 cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT; 2812 cpu_reg.spad_base = BCE_RXP_SCRATCH; 2813 cpu_reg.mips_view_base = 0x8000000; 2814 2815 fw.ver_major = bce_RXP_b06FwReleaseMajor; 2816 fw.ver_minor = bce_RXP_b06FwReleaseMinor; 2817 fw.ver_fix = bce_RXP_b06FwReleaseFix; 2818 fw.start_addr = bce_RXP_b06FwStartAddr; 2819 2820 fw.text_addr = bce_RXP_b06FwTextAddr; 2821 fw.text_len = bce_RXP_b06FwTextLen; 2822 fw.text_index = 0; 2823 fw.text = bce_RXP_b06FwText; 2824 2825 fw.data_addr = bce_RXP_b06FwDataAddr; 2826 fw.data_len = bce_RXP_b06FwDataLen; 2827 fw.data_index = 0; 2828 fw.data = bce_RXP_b06FwData; 2829 2830 fw.sbss_addr = bce_RXP_b06FwSbssAddr; 2831 fw.sbss_len = bce_RXP_b06FwSbssLen; 2832 fw.sbss_index = 0; 2833 fw.sbss = bce_RXP_b06FwSbss; 2834 2835 fw.bss_addr = bce_RXP_b06FwBssAddr; 2836 fw.bss_len = bce_RXP_b06FwBssLen; 2837 fw.bss_index = 0; 2838 fw.bss = bce_RXP_b06FwBss; 2839 2840 fw.rodata_addr = bce_RXP_b06FwRodataAddr; 2841 fw.rodata_len = bce_RXP_b06FwRodataLen; 2842 fw.rodata_index = 0; 2843 fw.rodata = bce_RXP_b06FwRodata; 2844 2845 DBPRINT(sc, BCE_INFO_RESET, "Loading RX firmware.\n"); 2846 bce_load_cpu_fw(sc, &cpu_reg, &fw); 2847 2848 /* Initialize the TX Processor. */ 2849 cpu_reg.mode = BCE_TXP_CPU_MODE; 2850 cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT; 2851 cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA; 2852 cpu_reg.state = BCE_TXP_CPU_STATE; 2853 cpu_reg.state_value_clear = 0xffffff; 2854 cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE; 2855 cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK; 2856 cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER; 2857 cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION; 2858 cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT; 2859 cpu_reg.spad_base = BCE_TXP_SCRATCH; 2860 cpu_reg.mips_view_base = 0x8000000; 2861 2862 fw.ver_major = bce_TXP_b06FwReleaseMajor; 2863 fw.ver_minor = bce_TXP_b06FwReleaseMinor; 2864 fw.ver_fix = bce_TXP_b06FwReleaseFix; 2865 fw.start_addr = bce_TXP_b06FwStartAddr; 2866 2867 fw.text_addr = bce_TXP_b06FwTextAddr; 2868 fw.text_len = bce_TXP_b06FwTextLen; 2869 fw.text_index = 0; 2870 fw.text = bce_TXP_b06FwText; 2871 2872 fw.data_addr = bce_TXP_b06FwDataAddr; 2873 fw.data_len = bce_TXP_b06FwDataLen; 2874 fw.data_index = 0; 2875 fw.data = bce_TXP_b06FwData; 2876 2877 fw.sbss_addr = bce_TXP_b06FwSbssAddr; 2878 fw.sbss_len = bce_TXP_b06FwSbssLen; 2879 fw.sbss_index = 0; 2880 fw.sbss = bce_TXP_b06FwSbss; 2881 2882 fw.bss_addr = bce_TXP_b06FwBssAddr; 2883 fw.bss_len = bce_TXP_b06FwBssLen; 2884 fw.bss_index = 0; 2885 fw.bss = bce_TXP_b06FwBss; 2886 2887 fw.rodata_addr = bce_TXP_b06FwRodataAddr; 2888 fw.rodata_len = bce_TXP_b06FwRodataLen; 2889 fw.rodata_index = 0; 2890 fw.rodata = bce_TXP_b06FwRodata; 2891 2892 DBPRINT(sc, BCE_INFO_RESET, "Loading TX firmware.\n"); 2893 bce_load_cpu_fw(sc, &cpu_reg, &fw); 2894 2895 /* Initialize the TX Patch-up Processor. */ 2896 cpu_reg.mode = BCE_TPAT_CPU_MODE; 2897 cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT; 2898 cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA; 2899 cpu_reg.state = BCE_TPAT_CPU_STATE; 2900 cpu_reg.state_value_clear = 0xffffff; 2901 cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE; 2902 cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK; 2903 cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER; 2904 cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION; 2905 cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT; 2906 cpu_reg.spad_base = BCE_TPAT_SCRATCH; 2907 cpu_reg.mips_view_base = 0x8000000; 2908 2909 fw.ver_major = bce_TPAT_b06FwReleaseMajor; 2910 fw.ver_minor = bce_TPAT_b06FwReleaseMinor; 2911 fw.ver_fix = bce_TPAT_b06FwReleaseFix; 2912 fw.start_addr = bce_TPAT_b06FwStartAddr; 2913 2914 fw.text_addr = bce_TPAT_b06FwTextAddr; 2915 fw.text_len = bce_TPAT_b06FwTextLen; 2916 fw.text_index = 0; 2917 fw.text = bce_TPAT_b06FwText; 2918 2919 fw.data_addr = bce_TPAT_b06FwDataAddr; 2920 fw.data_len = bce_TPAT_b06FwDataLen; 2921 fw.data_index = 0; 2922 fw.data = bce_TPAT_b06FwData; 2923 2924 fw.sbss_addr = bce_TPAT_b06FwSbssAddr; 2925 fw.sbss_len = bce_TPAT_b06FwSbssLen; 2926 fw.sbss_index = 0; 2927 fw.sbss = bce_TPAT_b06FwSbss; 2928 2929 fw.bss_addr = bce_TPAT_b06FwBssAddr; 2930 fw.bss_len = bce_TPAT_b06FwBssLen; 2931 fw.bss_index = 0; 2932 fw.bss = bce_TPAT_b06FwBss; 2933 2934 fw.rodata_addr = bce_TPAT_b06FwRodataAddr; 2935 fw.rodata_len = bce_TPAT_b06FwRodataLen; 2936 fw.rodata_index = 0; 2937 fw.rodata = bce_TPAT_b06FwRodata; 2938 2939 DBPRINT(sc, BCE_INFO_RESET, "Loading TPAT firmware.\n"); 2940 bce_load_cpu_fw(sc, &cpu_reg, &fw); 2941 2942 /* Initialize the Completion Processor. */ 2943 cpu_reg.mode = BCE_COM_CPU_MODE; 2944 cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT; 2945 cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA; 2946 cpu_reg.state = BCE_COM_CPU_STATE; 2947 cpu_reg.state_value_clear = 0xffffff; 2948 cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE; 2949 cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK; 2950 cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER; 2951 cpu_reg.inst = BCE_COM_CPU_INSTRUCTION; 2952 cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT; 2953 cpu_reg.spad_base = BCE_COM_SCRATCH; 2954 cpu_reg.mips_view_base = 0x8000000; 2955 2956 fw.ver_major = bce_COM_b06FwReleaseMajor; 2957 fw.ver_minor = bce_COM_b06FwReleaseMinor; 2958 fw.ver_fix = bce_COM_b06FwReleaseFix; 2959 fw.start_addr = bce_COM_b06FwStartAddr; 2960 2961 fw.text_addr = bce_COM_b06FwTextAddr; 2962 fw.text_len = bce_COM_b06FwTextLen; 2963 fw.text_index = 0; 2964 fw.text = bce_COM_b06FwText; 2965 2966 fw.data_addr = bce_COM_b06FwDataAddr; 2967 fw.data_len = bce_COM_b06FwDataLen; 2968 fw.data_index = 0; 2969 fw.data = bce_COM_b06FwData; 2970 2971 fw.sbss_addr = bce_COM_b06FwSbssAddr; 2972 fw.sbss_len = bce_COM_b06FwSbssLen; 2973 fw.sbss_index = 0; 2974 fw.sbss = bce_COM_b06FwSbss; 2975 2976 fw.bss_addr = bce_COM_b06FwBssAddr; 2977 fw.bss_len = bce_COM_b06FwBssLen; 2978 fw.bss_index = 0; 2979 fw.bss = bce_COM_b06FwBss; 2980 2981 fw.rodata_addr = bce_COM_b06FwRodataAddr; 2982 fw.rodata_len = bce_COM_b06FwRodataLen; 2983 fw.rodata_index = 0; 2984 fw.rodata = bce_COM_b06FwRodata; 2985 2986 DBPRINT(sc, BCE_INFO_RESET, "Loading COM firmware.\n"); 2987 bce_load_cpu_fw(sc, &cpu_reg, &fw); 2988} 2989 2990 2991/****************************************************************************/ 2992/* Initialize context memory. */ 2993/* */ 2994/* Clears the memory associated with each Context ID (CID). */ 2995/* */ 2996/* Returns: */ 2997/* Nothing. */ 2998/****************************************************************************/ 2999static void 3000bce_init_context(struct bce_softc *sc) 3001{ 3002 u32 vcid; 3003 3004 vcid = 96; 3005 while (vcid) { 3006 u32 vcid_addr, pcid_addr, offset; 3007 3008 vcid--; 3009 3010 vcid_addr = GET_CID_ADDR(vcid); 3011 pcid_addr = vcid_addr; 3012 3013 REG_WR(sc, BCE_CTX_VIRT_ADDR, 0x00); 3014 REG_WR(sc, BCE_CTX_PAGE_TBL, pcid_addr); 3015 3016 /* Zero out the context. */ 3017 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4) { 3018 CTX_WR(sc, 0x00, offset, 0); 3019 } 3020 3021 REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr); 3022 REG_WR(sc, BCE_CTX_PAGE_TBL, pcid_addr); 3023 } 3024} 3025 3026 3027/****************************************************************************/ 3028/* Fetch the permanent MAC address of the controller. */ 3029/* */ 3030/* Returns: */ 3031/* Nothing. */ 3032/****************************************************************************/ 3033static void 3034bce_get_mac_addr(struct bce_softc *sc) 3035{ 3036 u32 mac_lo = 0, mac_hi = 0; 3037 3038 /* 3039 * The NetXtreme II bootcode populates various NIC 3040 * power-on and runtime configuration items in a 3041 * shared memory area. The factory configured MAC 3042 * address is available from both NVRAM and the 3043 * shared memory area so we'll read the value from 3044 * shared memory for speed. 3045 */ 3046 3047 mac_hi = REG_RD_IND(sc, sc->bce_shmem_base + 3048 BCE_PORT_HW_CFG_MAC_UPPER); 3049 mac_lo = REG_RD_IND(sc, sc->bce_shmem_base + 3050 BCE_PORT_HW_CFG_MAC_LOWER); 3051 3052 if ((mac_lo == 0) && (mac_hi == 0)) { 3053 BCE_PRINTF("%s(%d): Invalid Ethernet address!\n", 3054 __FILE__, __LINE__); 3055 } else { 3056 sc->eaddr[0] = (u_char)(mac_hi >> 8); 3057 sc->eaddr[1] = (u_char)(mac_hi >> 0); 3058 sc->eaddr[2] = (u_char)(mac_lo >> 24); 3059 sc->eaddr[3] = (u_char)(mac_lo >> 16); 3060 sc->eaddr[4] = (u_char)(mac_lo >> 8); 3061 sc->eaddr[5] = (u_char)(mac_lo >> 0); 3062 } 3063 3064 DBPRINT(sc, BCE_INFO, "Permanent Ethernet address = %6D\n", sc->eaddr, ":"); 3065} 3066 3067 3068/****************************************************************************/ 3069/* Program the MAC address. */ 3070/* */ 3071/* Returns: */ 3072/* Nothing. */ 3073/****************************************************************************/ 3074static void 3075bce_set_mac_addr(struct bce_softc *sc) 3076{ 3077 u32 val; 3078 u8 *mac_addr = sc->eaddr; 3079 3080 DBPRINT(sc, BCE_INFO, "Setting Ethernet address = %6D\n", sc->eaddr, ":"); 3081 3082 val = (mac_addr[0] << 8) | mac_addr[1]; 3083 3084 REG_WR(sc, BCE_EMAC_MAC_MATCH0, val); 3085 3086 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 3087 (mac_addr[4] << 8) | mac_addr[5]; 3088 3089 REG_WR(sc, BCE_EMAC_MAC_MATCH1, val); 3090} 3091 3092 3093/****************************************************************************/ 3094/* Stop the controller. */ 3095/* */ 3096/* Returns: */ 3097/* Nothing. */ 3098/****************************************************************************/ 3099static void 3100bce_stop(struct bce_softc *sc) 3101{ 3102 struct ifnet *ifp; 3103 struct ifmedia_entry *ifm; 3104 struct mii_data *mii = NULL; 3105 int mtmp, itmp; 3106 3107 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 3108 3109 BCE_LOCK_ASSERT(sc); 3110 3111 ifp = sc->bce_ifp; 3112 3113 mii = device_get_softc(sc->bce_miibus); 3114 3115 callout_stop(&sc->bce_stat_ch); 3116 3117 /* Disable the transmit/receive blocks. */ 3118 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, 0x5ffffff); 3119 REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS); 3120 DELAY(20); 3121 3122 bce_disable_intr(sc); 3123 3124 /* Tell firmware that the driver is going away. */ 3125 bce_reset(sc, BCE_DRV_MSG_CODE_SUSPEND_NO_WOL); 3126 3127 /* Free the RX lists. */ 3128 bce_free_rx_chain(sc); 3129 3130 /* Free TX buffers. */ 3131 bce_free_tx_chain(sc); 3132 3133 /* 3134 * Isolate/power down the PHY, but leave the media selection 3135 * unchanged so that things will be put back to normal when 3136 * we bring the interface back up. 3137 */ 3138 3139 itmp = ifp->if_flags; 3140 ifp->if_flags |= IFF_UP; 3141 /* 3142 * If we are called from bce_detach(), mii is already NULL. 3143 */ 3144 if (mii != NULL) { 3145 ifm = mii->mii_media.ifm_cur; 3146 mtmp = ifm->ifm_media; 3147 ifm->ifm_media = IFM_ETHER | IFM_NONE; 3148 mii_mediachg(mii); 3149 ifm->ifm_media = mtmp; 3150 } 3151 3152 ifp->if_flags = itmp; 3153 sc->watchdog_timer = 0; 3154 3155 sc->bce_link = 0; 3156 3157 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3158 3159 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 3160 3161 bce_mgmt_init_locked(sc); 3162} 3163 3164 3165static int 3166bce_reset(struct bce_softc *sc, u32 reset_code) 3167{ 3168 u32 val; 3169 int i, rc = 0; 3170 3171 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 3172 3173 /* Wait for pending PCI transactions to complete. */ 3174 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, 3175 BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE | 3176 BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE | 3177 BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE | 3178 BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE); 3179 val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS); 3180 DELAY(5); 3181 3182 /* Assume bootcode is running. */ 3183 sc->bce_fw_timed_out = 0; 3184 3185 /* Give the firmware a chance to prepare for the reset. */ 3186 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT0 | reset_code); 3187 if (rc) 3188 goto bce_reset_exit; 3189 3190 /* Set a firmware reminder that this is a soft reset. */ 3191 REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_RESET_SIGNATURE, 3192 BCE_DRV_RESET_SIGNATURE_MAGIC); 3193 3194 /* Dummy read to force the chip to complete all current transactions. */ 3195 val = REG_RD(sc, BCE_MISC_ID); 3196 3197 /* Chip reset. */ 3198 val = BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 3199 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 3200 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 3201 REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val); 3202 3203 /* Allow up to 30us for reset to complete. */ 3204 for (i = 0; i < 10; i++) { 3205 val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG); 3206 if ((val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 3207 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) { 3208 break; 3209 } 3210 DELAY(10); 3211 } 3212 3213 /* Check that reset completed successfully. */ 3214 if (val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 3215 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) { 3216 BCE_PRINTF("%s(%d): Reset failed!\n", 3217 __FILE__, __LINE__); 3218 rc = EBUSY; 3219 goto bce_reset_exit; 3220 } 3221 3222 /* Make sure byte swapping is properly configured. */ 3223 val = REG_RD(sc, BCE_PCI_SWAP_DIAG0); 3224 if (val != 0x01020304) { 3225 BCE_PRINTF("%s(%d): Byte swap is incorrect!\n", 3226 __FILE__, __LINE__); 3227 rc = ENODEV; 3228 goto bce_reset_exit; 3229 } 3230 3231 /* Just completed a reset, assume that firmware is running again. */ 3232 sc->bce_fw_timed_out = 0; 3233 3234 /* Wait for the firmware to finish its initialization. */ 3235 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT1 | reset_code); 3236 if (rc) 3237 BCE_PRINTF("%s(%d): Firmware did not complete initialization!\n", 3238 __FILE__, __LINE__); 3239 3240bce_reset_exit: 3241 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 3242 3243 return (rc); 3244} 3245 3246 3247static int 3248bce_chipinit(struct bce_softc *sc) 3249{ 3250 u32 val; 3251 int rc = 0; 3252 3253 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 3254 3255 /* Make sure the interrupt is not active. */ 3256 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT); 3257 3258 /* 3259 * Initialize DMA byte/word swapping, configure the number of DMA 3260 * channels and PCI clock compensation delay. 3261 */ 3262 val = BCE_DMA_CONFIG_DATA_BYTE_SWAP | 3263 BCE_DMA_CONFIG_DATA_WORD_SWAP | 3264#if BYTE_ORDER == BIG_ENDIAN 3265 BCE_DMA_CONFIG_CNTL_BYTE_SWAP | 3266#endif 3267 BCE_DMA_CONFIG_CNTL_WORD_SWAP | 3268 DMA_READ_CHANS << 12 | 3269 DMA_WRITE_CHANS << 16; 3270 3271 val |= (0x2 << 20) | BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY; 3272 3273 if ((sc->bce_flags & BCE_PCIX_FLAG) && (sc->bus_speed_mhz == 133)) 3274 val |= BCE_DMA_CONFIG_PCI_FAST_CLK_CMP; 3275 3276 /* 3277 * This setting resolves a problem observed on certain Intel PCI 3278 * chipsets that cannot handle multiple outstanding DMA operations. 3279 * See errata E9_5706A1_65. 3280 */ 3281 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) && 3282 (BCE_CHIP_ID(sc) != BCE_CHIP_ID_5706_A0) && 3283 !(sc->bce_flags & BCE_PCIX_FLAG)) 3284 val |= BCE_DMA_CONFIG_CNTL_PING_PONG_DMA; 3285 3286 REG_WR(sc, BCE_DMA_CONFIG, val); 3287 3288 /* Clear the PCI-X relaxed ordering bit. See errata E3_5708CA0_570. */ 3289 if (sc->bce_flags & BCE_PCIX_FLAG) { 3290 u16 val; 3291 3292 val = pci_read_config(sc->bce_dev, BCE_PCI_PCIX_CMD, 2); 3293 pci_write_config(sc->bce_dev, BCE_PCI_PCIX_CMD, val & ~0x2, 2); 3294 } 3295 3296 /* Enable the RX_V2P and Context state machines before access. */ 3297 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 3298 BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE | 3299 BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE | 3300 BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE); 3301 3302 /* Initialize context mapping and zero out the quick contexts. */ 3303 bce_init_context(sc); 3304 3305 /* Initialize the on-boards CPUs */ 3306 bce_init_cpus(sc); 3307 3308 /* Prepare NVRAM for access. */ 3309 if (bce_init_nvram(sc)) { 3310 rc = ENODEV; 3311 goto bce_chipinit_exit; 3312 } 3313 3314 /* Set the kernel bypass block size */ 3315 val = REG_RD(sc, BCE_MQ_CONFIG); 3316 val &= ~BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE; 3317 val |= BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256; 3318 REG_WR(sc, BCE_MQ_CONFIG, val); 3319 3320 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE); 3321 REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val); 3322 REG_WR(sc, BCE_MQ_KNL_WIND_END, val); 3323 3324 /* Set the page size and clear the RV2P processor stall bits. */ 3325 val = (BCM_PAGE_BITS - 8) << 24; 3326 REG_WR(sc, BCE_RV2P_CONFIG, val); 3327 3328 /* Configure page size. */ 3329 val = REG_RD(sc, BCE_TBDR_CONFIG); 3330 val &= ~BCE_TBDR_CONFIG_PAGE_SIZE; 3331 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40; 3332 REG_WR(sc, BCE_TBDR_CONFIG, val); 3333 3334bce_chipinit_exit: 3335 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 3336 3337 return(rc); 3338} 3339 3340 3341/****************************************************************************/ 3342/* Initialize the controller in preparation to send/receive traffic. */ 3343/* */ 3344/* Returns: */ 3345/* 0 for success, positive value for failure. */ 3346/****************************************************************************/ 3347static int 3348bce_blockinit(struct bce_softc *sc) 3349{ 3350 u32 reg, val; 3351 int rc = 0; 3352 3353 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 3354 3355 /* Load the hardware default MAC address. */ 3356 bce_set_mac_addr(sc); 3357 3358 /* Set the Ethernet backoff seed value */ 3359 val = sc->eaddr[0] + (sc->eaddr[1] << 8) + 3360 (sc->eaddr[2] << 16) + (sc->eaddr[3] ) + 3361 (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16); 3362 REG_WR(sc, BCE_EMAC_BACKOFF_SEED, val); 3363 3364 sc->last_status_idx = 0; 3365 sc->rx_mode = BCE_EMAC_RX_MODE_SORT_MODE; 3366 3367 /* Set up link change interrupt generation. */ 3368 REG_WR(sc, BCE_EMAC_ATTENTION_ENA, BCE_EMAC_ATTENTION_ENA_LINK); 3369 3370 /* Program the physical address of the status block. */ 3371 REG_WR(sc, BCE_HC_STATUS_ADDR_L, 3372 BCE_ADDR_LO(sc->status_block_paddr)); 3373 REG_WR(sc, BCE_HC_STATUS_ADDR_H, 3374 BCE_ADDR_HI(sc->status_block_paddr)); 3375 3376 /* Program the physical address of the statistics block. */ 3377 REG_WR(sc, BCE_HC_STATISTICS_ADDR_L, 3378 BCE_ADDR_LO(sc->stats_block_paddr)); 3379 REG_WR(sc, BCE_HC_STATISTICS_ADDR_H, 3380 BCE_ADDR_HI(sc->stats_block_paddr)); 3381 3382 /* Program various host coalescing parameters. */ 3383 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP, 3384 (sc->bce_tx_quick_cons_trip_int << 16) | sc->bce_tx_quick_cons_trip); 3385 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP, 3386 (sc->bce_rx_quick_cons_trip_int << 16) | sc->bce_rx_quick_cons_trip); 3387 REG_WR(sc, BCE_HC_COMP_PROD_TRIP, 3388 (sc->bce_comp_prod_trip_int << 16) | sc->bce_comp_prod_trip); 3389 REG_WR(sc, BCE_HC_TX_TICKS, 3390 (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks); 3391 REG_WR(sc, BCE_HC_RX_TICKS, 3392 (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks); 3393 REG_WR(sc, BCE_HC_COM_TICKS, 3394 (sc->bce_com_ticks_int << 16) | sc->bce_com_ticks); 3395 REG_WR(sc, BCE_HC_CMD_TICKS, 3396 (sc->bce_cmd_ticks_int << 16) | sc->bce_cmd_ticks); 3397 REG_WR(sc, BCE_HC_STATS_TICKS, 3398 (sc->bce_stats_ticks & 0xffff00)); 3399 REG_WR(sc, BCE_HC_STAT_COLLECT_TICKS, 3400 0xbb8); /* 3ms */ 3401 REG_WR(sc, BCE_HC_CONFIG, 3402 (BCE_HC_CONFIG_RX_TMR_MODE | BCE_HC_CONFIG_TX_TMR_MODE | 3403 BCE_HC_CONFIG_COLLECT_STATS)); 3404 3405 /* Clear the internal statistics counters. */ 3406 REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW); 3407 3408 /* Verify that bootcode is running. */ 3409 reg = REG_RD_IND(sc, sc->bce_shmem_base + BCE_DEV_INFO_SIGNATURE); 3410 3411 DBRUNIF(DB_RANDOMTRUE(bce_debug_bootcode_running_failure), 3412 BCE_PRINTF("%s(%d): Simulating bootcode failure.\n", 3413 __FILE__, __LINE__); 3414 reg = 0); 3415 3416 if ((reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK) != 3417 BCE_DEV_INFO_SIGNATURE_MAGIC) { 3418 BCE_PRINTF("%s(%d): Bootcode not running! Found: 0x%08X, " 3419 "Expected: 08%08X\n", __FILE__, __LINE__, 3420 (reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK), 3421 BCE_DEV_INFO_SIGNATURE_MAGIC); 3422 rc = ENODEV; 3423 goto bce_blockinit_exit; 3424 } 3425 3426 /* Check if any management firmware is running. */ 3427 reg = REG_RD_IND(sc, sc->bce_shmem_base + BCE_PORT_FEATURE); 3428 if (reg & (BCE_PORT_FEATURE_ASF_ENABLED | BCE_PORT_FEATURE_IMD_ENABLED)) { 3429 DBPRINT(sc, BCE_INFO, "Management F/W Enabled.\n"); 3430 sc->bce_flags |= BCE_MFW_ENABLE_FLAG; 3431 } 3432 3433 sc->bce_fw_ver = REG_RD_IND(sc, sc->bce_shmem_base + BCE_DEV_INFO_BC_REV); 3434 DBPRINT(sc, BCE_INFO, "bootcode rev = 0x%08X\n", sc->bce_fw_ver); 3435 3436 /* Allow bootcode to apply any additional fixes before enabling MAC. */ 3437 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT2 | BCE_DRV_MSG_CODE_RESET); 3438 3439 /* Enable link state change interrupt generation. */ 3440 REG_WR(sc, BCE_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE); 3441 3442 /* Enable all remaining blocks in the MAC. */ 3443 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 0x5ffffff); 3444 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS); 3445 DELAY(20); 3446 3447bce_blockinit_exit: 3448 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 3449 3450 return (rc); 3451} 3452 3453 3454/****************************************************************************/ 3455/* Encapsulate an mbuf cluster into the rx_bd chain. */ 3456/* */ 3457/* The NetXtreme II can support Jumbo frames by using multiple rx_bd's. */ 3458/* This routine will map an mbuf cluster into 1 or more rx_bd's as */ 3459/* necessary. */ 3460/* */ 3461/* Returns: */ 3462/* 0 for success, positive value for failure. */ 3463/****************************************************************************/ 3464static int 3465bce_get_buf(struct bce_softc *sc, struct mbuf *m, u16 *prod, u16 *chain_prod, 3466 u32 *prod_bseq) 3467{ 3468 bus_dmamap_t map; 3469 bus_dma_segment_t segs[4]; 3470 struct mbuf *m_new = NULL; 3471 struct rx_bd *rxbd; 3472 int i, nsegs, error, rc = 0; 3473#ifdef BCE_DEBUG 3474 u16 debug_chain_prod = *chain_prod; 3475#endif 3476 3477 DBPRINT(sc, (BCE_VERBOSE_RESET | BCE_VERBOSE_RECV), "Entering %s()\n", 3478 __FUNCTION__); 3479 3480 /* Make sure the inputs are valid. */ 3481 DBRUNIF((*chain_prod > MAX_RX_BD), 3482 BCE_PRINTF("%s(%d): RX producer out of range: 0x%04X > 0x%04X\n", 3483 __FILE__, __LINE__, *chain_prod, (u16) MAX_RX_BD)); 3484 3485 DBPRINT(sc, BCE_VERBOSE_RECV, "%s(enter): prod = 0x%04X, chain_prod = 0x%04X, " 3486 "prod_bseq = 0x%08X\n", __FUNCTION__, *prod, *chain_prod, *prod_bseq); 3487 3488 if (m == NULL) { 3489 3490 DBRUNIF(DB_RANDOMTRUE(bce_debug_mbuf_allocation_failure), 3491 BCE_PRINTF("%s(%d): Simulating mbuf allocation failure.\n", 3492 __FILE__, __LINE__); 3493 sc->mbuf_alloc_failed++; 3494 rc = ENOBUFS; 3495 goto bce_get_buf_exit); 3496 3497 /* This is a new mbuf allocation. */ 3498 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 3499 if (m_new == NULL) { 3500 3501 DBPRINT(sc, BCE_WARN, "%s(%d): RX mbuf header allocation failed!\n", 3502 __FILE__, __LINE__); 3503 3504 DBRUNIF(1, sc->mbuf_alloc_failed++); 3505 3506 rc = ENOBUFS; 3507 goto bce_get_buf_exit; 3508 } 3509 3510 DBRUNIF(1, sc->rx_mbuf_alloc++); 3511 m_cljget(m_new, M_DONTWAIT, sc->mbuf_alloc_size); 3512 if (!(m_new->m_flags & M_EXT)) { 3513 3514 DBPRINT(sc, BCE_WARN, "%s(%d): RX mbuf chain allocation failed!\n", 3515 __FILE__, __LINE__); 3516 3517 m_freem(m_new); 3518 3519 DBRUNIF(1, sc->rx_mbuf_alloc--); 3520 DBRUNIF(1, sc->mbuf_alloc_failed++); 3521 3522 rc = ENOBUFS; 3523 goto bce_get_buf_exit; 3524 } 3525 3526 m_new->m_len = m_new->m_pkthdr.len = sc->mbuf_alloc_size; 3527 } else { 3528 m_new = m; 3529 m_new->m_len = m_new->m_pkthdr.len = sc->mbuf_alloc_size; 3530 m_new->m_data = m_new->m_ext.ext_buf; 3531 } 3532 3533 /* Map the mbuf cluster into device memory. */ 3534 map = sc->rx_mbuf_map[*chain_prod]; 3535 error = bus_dmamap_load_mbuf_sg(sc->rx_mbuf_tag, map, m_new, 3536 segs, &nsegs, BUS_DMA_NOWAIT); 3537 3538 if (error) { 3539 BCE_PRINTF("%s(%d): Error mapping mbuf into RX chain!\n", 3540 __FILE__, __LINE__); 3541 3542 m_freem(m_new); 3543 3544 DBRUNIF(1, sc->rx_mbuf_alloc--); 3545 3546 rc = ENOBUFS; 3547 goto bce_get_buf_exit; 3548 } 3549 3550 /* Watch for overflow. */ 3551 DBRUNIF((sc->free_rx_bd > USABLE_RX_BD), 3552 BCE_PRINTF("%s(%d): Too many free rx_bd (0x%04X > 0x%04X)!\n", 3553 __FILE__, __LINE__, sc->free_rx_bd, (u16) USABLE_RX_BD)); 3554 3555 /* Update some debug statistic counters */ 3556 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 3557 sc->rx_low_watermark = sc->free_rx_bd); 3558 DBRUNIF((sc->free_rx_bd == 0), sc->rx_empty_count++); 3559 3560 /* Setup the rx_bd for the first segment. */ 3561 rxbd = &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)]; 3562 3563 rxbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[0].ds_addr)); 3564 rxbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[0].ds_addr)); 3565 rxbd->rx_bd_len = htole32(segs[0].ds_len); 3566 rxbd->rx_bd_flags = htole32(RX_BD_FLAGS_START); 3567 *prod_bseq += segs[0].ds_len; 3568 3569 for (i = 1; i < nsegs; i++) { 3570 3571 *prod = NEXT_RX_BD(*prod); 3572 *chain_prod = RX_CHAIN_IDX(*prod); 3573 3574 rxbd = &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)]; 3575 3576 rxbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[i].ds_addr)); 3577 rxbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[i].ds_addr)); 3578 rxbd->rx_bd_len = htole32(segs[i].ds_len); 3579 rxbd->rx_bd_flags = 0; 3580 *prod_bseq += segs[i].ds_len; 3581 } 3582 3583 rxbd->rx_bd_flags |= htole32(RX_BD_FLAGS_END); 3584 3585 /* Save the mbuf and update our counter. */ 3586 sc->rx_mbuf_ptr[*chain_prod] = m_new; 3587 sc->free_rx_bd -= nsegs; 3588 3589 DBRUN(BCE_VERBOSE_RECV, bce_dump_rx_mbuf_chain(sc, debug_chain_prod, 3590 nsegs)); 3591 3592 DBPRINT(sc, BCE_VERBOSE_RECV, "%s(exit): prod = 0x%04X, chain_prod = 0x%04X, " 3593 "prod_bseq = 0x%08X\n", __FUNCTION__, *prod, *chain_prod, *prod_bseq); 3594 3595bce_get_buf_exit: 3596 DBPRINT(sc, (BCE_VERBOSE_RESET | BCE_VERBOSE_RECV), "Exiting %s()\n", 3597 __FUNCTION__); 3598 3599 return(rc); 3600} 3601 3602 3603/****************************************************************************/ 3604/* Allocate memory and initialize the TX data structures. */ 3605/* */ 3606/* Returns: */ 3607/* 0 for success, positive value for failure. */ 3608/****************************************************************************/ 3609static int 3610bce_init_tx_chain(struct bce_softc *sc) 3611{ 3612 struct tx_bd *txbd; 3613 u32 val; 3614 int i, rc = 0; 3615 3616 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 3617 3618 /* Set the initial TX producer/consumer indices. */ 3619 sc->tx_prod = 0; 3620 sc->tx_cons = 0; 3621 sc->tx_prod_bseq = 0; 3622 sc->used_tx_bd = 0; 3623 sc->max_tx_bd = USABLE_TX_BD; 3624 DBRUNIF(1, sc->tx_hi_watermark = USABLE_TX_BD); 3625 DBRUNIF(1, sc->tx_full_count = 0); 3626 3627 /* 3628 * The NetXtreme II supports a linked-list structre called 3629 * a Buffer Descriptor Chain (or BD chain). A BD chain 3630 * consists of a series of 1 or more chain pages, each of which 3631 * consists of a fixed number of BD entries. 3632 * The last BD entry on each page is a pointer to the next page 3633 * in the chain, and the last pointer in the BD chain 3634 * points back to the beginning of the chain. 3635 */ 3636 3637 /* Set the TX next pointer chain entries. */ 3638 for (i = 0; i < TX_PAGES; i++) { 3639 int j; 3640 3641 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE]; 3642 3643 /* Check if we've reached the last page. */ 3644 if (i == (TX_PAGES - 1)) 3645 j = 0; 3646 else 3647 j = i + 1; 3648 3649 txbd->tx_bd_haddr_hi = htole32(BCE_ADDR_HI(sc->tx_bd_chain_paddr[j])); 3650 txbd->tx_bd_haddr_lo = htole32(BCE_ADDR_LO(sc->tx_bd_chain_paddr[j])); 3651 } 3652 3653 /* Initialize the context ID for an L2 TX chain. */ 3654 val = BCE_L2CTX_TYPE_TYPE_L2; 3655 val |= BCE_L2CTX_TYPE_SIZE_L2; 3656 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TYPE, val); 3657 3658 val = BCE_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16); 3659 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_CMD_TYPE, val); 3660 3661 /* Point the hardware to the first page in the chain. */ 3662 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]); 3663 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TBDR_BHADDR_HI, val); 3664 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]); 3665 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TBDR_BHADDR_LO, val); 3666 3667 DBRUN(BCE_VERBOSE_SEND, bce_dump_tx_chain(sc, 0, TOTAL_TX_BD)); 3668 3669 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 3670 3671 return(rc); 3672} 3673 3674 3675/****************************************************************************/ 3676/* Free memory and clear the TX data structures. */ 3677/* */ 3678/* Returns: */ 3679/* Nothing. */ 3680/****************************************************************************/ 3681static void 3682bce_free_tx_chain(struct bce_softc *sc) 3683{ 3684 int i; 3685 3686 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 3687 3688 /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */ 3689 for (i = 0; i < TOTAL_TX_BD; i++) { 3690 if (sc->tx_mbuf_ptr[i] != NULL) { 3691 if (sc->tx_mbuf_map != NULL) 3692 bus_dmamap_sync(sc->tx_mbuf_tag, sc->tx_mbuf_map[i], 3693 BUS_DMASYNC_POSTWRITE); 3694 m_freem(sc->tx_mbuf_ptr[i]); 3695 sc->tx_mbuf_ptr[i] = NULL; 3696 DBRUNIF(1, sc->tx_mbuf_alloc--); 3697 } 3698 } 3699 3700 /* Clear each TX chain page. */ 3701 for (i = 0; i < TX_PAGES; i++) 3702 bzero((char *)sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ); 3703 3704 /* Check if we lost any mbufs in the process. */ 3705 DBRUNIF((sc->tx_mbuf_alloc), 3706 BCE_PRINTF("%s(%d): Memory leak! Lost %d mbufs " 3707 "from tx chain!\n", 3708 __FILE__, __LINE__, sc->tx_mbuf_alloc)); 3709 3710 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 3711} 3712 3713 3714/****************************************************************************/ 3715/* Allocate memory and initialize the RX data structures. */ 3716/* */ 3717/* Returns: */ 3718/* 0 for success, positive value for failure. */ 3719/****************************************************************************/ 3720static int 3721bce_init_rx_chain(struct bce_softc *sc) 3722{ 3723 struct rx_bd *rxbd; 3724 int i, rc = 0; 3725 u16 prod, chain_prod; 3726 u32 prod_bseq, val; 3727 3728 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 3729 3730 /* Initialize the RX producer and consumer indices. */ 3731 sc->rx_prod = 0; 3732 sc->rx_cons = 0; 3733 sc->rx_prod_bseq = 0; 3734 sc->free_rx_bd = USABLE_RX_BD; 3735 sc->max_rx_bd = USABLE_RX_BD; 3736 DBRUNIF(1, sc->rx_low_watermark = USABLE_RX_BD); 3737 DBRUNIF(1, sc->rx_empty_count = 0); 3738 3739 /* Initialize the RX next pointer chain entries. */ 3740 for (i = 0; i < RX_PAGES; i++) { 3741 int j; 3742 3743 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE]; 3744 3745 /* Check if we've reached the last page. */ 3746 if (i == (RX_PAGES - 1)) 3747 j = 0; 3748 else 3749 j = i + 1; 3750 3751 /* Setup the chain page pointers. */ 3752 rxbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(sc->rx_bd_chain_paddr[j])); 3753 rxbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(sc->rx_bd_chain_paddr[j])); 3754 } 3755 3756 /* Initialize the context ID for an L2 RX chain. */ 3757 val = BCE_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE; 3758 val |= BCE_L2CTX_CTX_TYPE_SIZE_L2; 3759 val |= 0x02 << 8; 3760 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_CTX_TYPE, val); 3761 3762 /* Point the hardware to the first page in the chain. */ 3763 val = BCE_ADDR_HI(sc->rx_bd_chain_paddr[0]); 3764 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_NX_BDHADDR_HI, val); 3765 val = BCE_ADDR_LO(sc->rx_bd_chain_paddr[0]); 3766 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_NX_BDHADDR_LO, val); 3767 3768 /* Allocate mbuf clusters for the rx_bd chain. */ 3769 prod = prod_bseq = 0; 3770 while (prod < TOTAL_RX_BD) { 3771 chain_prod = RX_CHAIN_IDX(prod); 3772 if (bce_get_buf(sc, NULL, &prod, &chain_prod, &prod_bseq)) { 3773 BCE_PRINTF("%s(%d): Error filling RX chain: rx_bd[0x%04X]!\n", 3774 __FILE__, __LINE__, chain_prod); 3775 rc = ENOBUFS; 3776 break; 3777 } 3778 prod = NEXT_RX_BD(prod); 3779 } 3780 3781 /* Save the RX chain producer index. */ 3782 sc->rx_prod = prod; 3783 sc->rx_prod_bseq = prod_bseq; 3784 3785 for (i = 0; i < RX_PAGES; i++) { 3786 bus_dmamap_sync( 3787 sc->rx_bd_chain_tag, 3788 sc->rx_bd_chain_map[i], 3789 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3790 } 3791 3792 /* Tell the chip about the waiting rx_bd's. */ 3793 REG_WR16(sc, MB_RX_CID_ADDR + BCE_L2CTX_HOST_BDIDX, sc->rx_prod); 3794 REG_WR(sc, MB_RX_CID_ADDR + BCE_L2CTX_HOST_BSEQ, sc->rx_prod_bseq); 3795 3796 DBRUN(BCE_VERBOSE_RECV, bce_dump_rx_chain(sc, 0, TOTAL_RX_BD)); 3797 3798 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 3799 3800 return(rc); 3801} 3802 3803 3804/****************************************************************************/ 3805/* Free memory and clear the RX data structures. */ 3806/* */ 3807/* Returns: */ 3808/* Nothing. */ 3809/****************************************************************************/ 3810static void 3811bce_free_rx_chain(struct bce_softc *sc) 3812{ 3813 int i; 3814 3815 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 3816 3817 /* Free any mbufs still in the RX mbuf chain. */ 3818 for (i = 0; i < TOTAL_RX_BD; i++) { 3819 if (sc->rx_mbuf_ptr[i] != NULL) { 3820 if (sc->rx_mbuf_map[i] != NULL) 3821 bus_dmamap_sync(sc->rx_mbuf_tag, sc->rx_mbuf_map[i], 3822 BUS_DMASYNC_POSTREAD); 3823 m_freem(sc->rx_mbuf_ptr[i]); 3824 sc->rx_mbuf_ptr[i] = NULL; 3825 DBRUNIF(1, sc->rx_mbuf_alloc--); 3826 } 3827 } 3828 3829 /* Clear each RX chain page. */ 3830 for (i = 0; i < RX_PAGES; i++) 3831 bzero((char *)sc->rx_bd_chain[i], BCE_RX_CHAIN_PAGE_SZ); 3832 3833 /* Check if we lost any mbufs in the process. */ 3834 DBRUNIF((sc->rx_mbuf_alloc), 3835 BCE_PRINTF("%s(%d): Memory leak! Lost %d mbufs from rx chain!\n", 3836 __FILE__, __LINE__, sc->rx_mbuf_alloc)); 3837 3838 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 3839} 3840 3841 3842/****************************************************************************/ 3843/* Set media options. */ 3844/* */ 3845/* Returns: */ 3846/* 0 for success, positive value for failure. */ 3847/****************************************************************************/ 3848static int 3849bce_ifmedia_upd(struct ifnet *ifp) 3850{ 3851 struct bce_softc *sc; 3852 3853 sc = ifp->if_softc; 3854 BCE_LOCK(sc); 3855 bce_ifmedia_upd_locked(ifp); 3856 BCE_UNLOCK(sc); 3857 return (0); 3858} 3859 3860 3861/****************************************************************************/ 3862/* Set media options. */ 3863/* */ 3864/* Returns: */ 3865/* Nothing. */ 3866/****************************************************************************/ 3867static void 3868bce_ifmedia_upd_locked(struct ifnet *ifp) 3869{ 3870 struct bce_softc *sc; 3871 struct mii_data *mii; 3872 struct ifmedia *ifm; 3873 3874 sc = ifp->if_softc; 3875 ifm = &sc->bce_ifmedia; 3876 BCE_LOCK_ASSERT(sc); 3877 3878 mii = device_get_softc(sc->bce_miibus); 3879 3880 /* Make sure the MII bus has been enumerated. */ 3881 if (mii) { 3882 sc->bce_link = 0; 3883 if (mii->mii_instance) { 3884 struct mii_softc *miisc; 3885 3886 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 3887 mii_phy_reset(miisc); 3888 } 3889 mii_mediachg(mii); 3890 } 3891} 3892 3893 3894/****************************************************************************/ 3895/* Reports current media status. */ 3896/* */ 3897/* Returns: */ 3898/* Nothing. */ 3899/****************************************************************************/ 3900static void 3901bce_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3902{ 3903 struct bce_softc *sc; 3904 struct mii_data *mii; 3905 3906 sc = ifp->if_softc; 3907 3908 BCE_LOCK(sc); 3909 3910 mii = device_get_softc(sc->bce_miibus); 3911 3912 mii_pollstat(mii); 3913 ifmr->ifm_active = mii->mii_media_active; 3914 ifmr->ifm_status = mii->mii_media_status; 3915 3916 BCE_UNLOCK(sc); 3917} 3918 3919 3920/****************************************************************************/ 3921/* Handles PHY generated interrupt events. */ 3922/* */ 3923/* Returns: */ 3924/* Nothing. */ 3925/****************************************************************************/ 3926static void 3927bce_phy_intr(struct bce_softc *sc) 3928{ 3929 u32 new_link_state, old_link_state; 3930 3931 new_link_state = sc->status_block->status_attn_bits & 3932 STATUS_ATTN_BITS_LINK_STATE; 3933 old_link_state = sc->status_block->status_attn_bits_ack & 3934 STATUS_ATTN_BITS_LINK_STATE; 3935 3936 /* Handle any changes if the link state has changed. */ 3937 if (new_link_state != old_link_state) { 3938 3939 DBRUN(BCE_VERBOSE_INTR, bce_dump_status_block(sc)); 3940 3941 sc->bce_link = 0; 3942 callout_stop(&sc->bce_stat_ch); 3943 bce_tick(sc); 3944 3945 /* Update the status_attn_bits_ack field in the status block. */ 3946 if (new_link_state) { 3947 REG_WR(sc, BCE_PCICFG_STATUS_BIT_SET_CMD, 3948 STATUS_ATTN_BITS_LINK_STATE); 3949 DBPRINT(sc, BCE_INFO, "Link is now UP.\n"); 3950 } 3951 else { 3952 REG_WR(sc, BCE_PCICFG_STATUS_BIT_CLEAR_CMD, 3953 STATUS_ATTN_BITS_LINK_STATE); 3954 DBPRINT(sc, BCE_INFO, "Link is now DOWN.\n"); 3955 } 3956 3957 } 3958 3959 /* Acknowledge the link change interrupt. */ 3960 REG_WR(sc, BCE_EMAC_STATUS, BCE_EMAC_STATUS_LINK_CHANGE); 3961} 3962 3963 3964/****************************************************************************/ 3965/* Handles received frame interrupt events. */ 3966/* */ 3967/* Returns: */ 3968/* Nothing. */ 3969/****************************************************************************/ 3970static void 3971bce_rx_intr(struct bce_softc *sc) 3972{ 3973 struct status_block *sblk = sc->status_block; 3974 struct ifnet *ifp = sc->bce_ifp; 3975 u16 hw_cons, sw_cons, sw_chain_cons, sw_prod, sw_chain_prod; 3976 u32 sw_prod_bseq; 3977 struct l2_fhdr *l2fhdr; 3978 3979 DBRUNIF(1, sc->rx_interrupts++); 3980 3981 /* Prepare the RX chain pages to be accessed by the host CPU. */ 3982 for (int i = 0; i < RX_PAGES; i++) 3983 bus_dmamap_sync(sc->rx_bd_chain_tag, 3984 sc->rx_bd_chain_map[i], BUS_DMASYNC_POSTWRITE); 3985 3986 /* Get the hardware's view of the RX consumer index. */ 3987 hw_cons = sc->hw_rx_cons = sblk->status_rx_quick_consumer_index0; 3988 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 3989 hw_cons++; 3990 3991 /* Get working copies of the driver's view of the RX indices. */ 3992 sw_cons = sc->rx_cons; 3993 sw_prod = sc->rx_prod; 3994 sw_prod_bseq = sc->rx_prod_bseq; 3995 3996 DBPRINT(sc, BCE_INFO_RECV, "%s(enter): sw_prod = 0x%04X, " 3997 "sw_cons = 0x%04X, sw_prod_bseq = 0x%08X\n", 3998 __FUNCTION__, sw_prod, sw_cons, 3999 sw_prod_bseq); 4000 4001 /* Prevent speculative reads from getting ahead of the status block. */ 4002 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 4003 BUS_SPACE_BARRIER_READ); 4004 4005 /* Update some debug statistics counters */ 4006 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 4007 sc->rx_low_watermark = sc->free_rx_bd); 4008 DBRUNIF((sc->free_rx_bd == 0), sc->rx_empty_count++); 4009 4010 /* Scan through the receive chain as long as there is work to do */ 4011 while (sw_cons != hw_cons) { 4012 struct mbuf *m; 4013 struct rx_bd *rxbd; 4014 unsigned int len; 4015 u32 status; 4016 4017 /* Clear the mbuf pointer. */ 4018 m = NULL; 4019 4020 /* Convert the producer/consumer indices to an actual rx_bd index. */ 4021 sw_chain_cons = RX_CHAIN_IDX(sw_cons); 4022 sw_chain_prod = RX_CHAIN_IDX(sw_prod); 4023 4024 /* Get the used rx_bd. */ 4025 rxbd = &sc->rx_bd_chain[RX_PAGE(sw_chain_cons)][RX_IDX(sw_chain_cons)]; 4026 sc->free_rx_bd++; 4027 4028 DBRUN(BCE_VERBOSE_RECV, 4029 BCE_PRINTF("%s(): ", __FUNCTION__); 4030 bce_dump_rxbd(sc, sw_chain_cons, rxbd)); 4031 4032#ifdef DEVICE_POLLING 4033 if (ifp->if_capenable & IFCAP_POLLING) { 4034 if (sc->bce_rxcycles <= 0) 4035 break; 4036 sc->bce_rxcycles--; 4037 } 4038#endif 4039 4040 /* The mbuf is stored with the last rx_bd entry of a packet. */ 4041 if (sc->rx_mbuf_ptr[sw_chain_cons] != NULL) { 4042 4043 /* Validate that this is the last rx_bd. */ 4044 DBRUNIF((!(rxbd->rx_bd_flags & RX_BD_FLAGS_END)), 4045 BCE_PRINTF("%s(%d): Unexpected mbuf found in rx_bd[0x%04X]!\n", 4046 __FILE__, __LINE__, sw_chain_cons); 4047 bce_breakpoint(sc)); 4048 4049 /* 4050 * ToDo: If the received packet is small enough 4051 * to fit into a single, non-M_EXT mbuf, 4052 * allocate a new mbuf here, copy the data to 4053 * that mbuf, and recycle the mapped jumbo frame. 4054 */ 4055 4056 /* Unmap the mbuf from DMA space. */ 4057 bus_dmamap_sync(sc->rx_mbuf_tag, 4058 sc->rx_mbuf_map[sw_chain_cons], 4059 BUS_DMASYNC_POSTREAD); 4060 bus_dmamap_unload(sc->rx_mbuf_tag, 4061 sc->rx_mbuf_map[sw_chain_cons]); 4062 4063 /* Remove the mbuf from the driver's chain. */ 4064 m = sc->rx_mbuf_ptr[sw_chain_cons]; 4065 sc->rx_mbuf_ptr[sw_chain_cons] = NULL; 4066 4067 /* 4068 * Frames received on the NetXteme II are prepended 4069 * with an l2_fhdr structure which provides status 4070 * information about the received frame (including 4071 * VLAN tags and checksum info). The frames are also 4072 * automatically adjusted to align the IP header 4073 * (i.e. two null bytes are inserted before the 4074 * Ethernet header). 4075 */ 4076 l2fhdr = mtod(m, struct l2_fhdr *); 4077 4078 len = l2fhdr->l2_fhdr_pkt_len; 4079 status = l2fhdr->l2_fhdr_status; 4080 4081 DBRUNIF(DB_RANDOMTRUE(bce_debug_l2fhdr_status_check), 4082 BCE_PRINTF("Simulating l2_fhdr status error.\n"); 4083 status = status | L2_FHDR_ERRORS_PHY_DECODE); 4084 4085 /* Watch for unusual sized frames. */ 4086 DBRUNIF(((len < BCE_MIN_MTU) || (len > BCE_MAX_JUMBO_ETHER_MTU_VLAN)), 4087 BCE_PRINTF("%s(%d): Unusual frame size found. " 4088 "Min(%d), Actual(%d), Max(%d)\n", 4089 __FILE__, __LINE__, (int) BCE_MIN_MTU, 4090 len, (int) BCE_MAX_JUMBO_ETHER_MTU_VLAN); 4091 bce_dump_mbuf(sc, m); 4092 bce_breakpoint(sc)); 4093 4094 len -= ETHER_CRC_LEN; 4095 4096 /* Check the received frame for errors. */ 4097 if (status & (L2_FHDR_ERRORS_BAD_CRC | 4098 L2_FHDR_ERRORS_PHY_DECODE | L2_FHDR_ERRORS_ALIGNMENT | 4099 L2_FHDR_ERRORS_TOO_SHORT | L2_FHDR_ERRORS_GIANT_FRAME)) { 4100 4101 ifp->if_ierrors++; 4102 DBRUNIF(1, sc->l2fhdr_status_errors++); 4103 4104 /* Reuse the mbuf for a new frame. */ 4105 if (bce_get_buf(sc, m, &sw_prod, &sw_chain_prod, &sw_prod_bseq)) { 4106 4107 DBRUNIF(1, bce_breakpoint(sc)); 4108 panic("bce%d: Can't reuse RX mbuf!\n", sc->bce_unit); 4109 4110 } 4111 goto bce_rx_int_next_rx; 4112 } 4113 4114 /* 4115 * Get a new mbuf for the rx_bd. If no new 4116 * mbufs are available then reuse the current mbuf, 4117 * log an ierror on the interface, and generate 4118 * an error in the system log. 4119 */ 4120 if (bce_get_buf(sc, NULL, &sw_prod, &sw_chain_prod, &sw_prod_bseq)) { 4121 4122 DBRUN(BCE_WARN, 4123 BCE_PRINTF("%s(%d): Failed to allocate " 4124 "new mbuf, incoming frame dropped!\n", 4125 __FILE__, __LINE__)); 4126 4127 ifp->if_ierrors++; 4128 4129 /* Try and reuse the exisitng mbuf. */ 4130 if (bce_get_buf(sc, m, &sw_prod, &sw_chain_prod, &sw_prod_bseq)) { 4131 4132 DBRUNIF(1, bce_breakpoint(sc)); 4133 panic("bce%d: Double mbuf allocation failure!", sc->bce_unit); 4134 4135 } 4136 goto bce_rx_int_next_rx; 4137 } 4138 4139 /* Skip over the l2_fhdr when passing the data up the stack. */ 4140 m_adj(m, sizeof(struct l2_fhdr) + ETHER_ALIGN); 4141 4142 /* Adjust the packet length to match the received data. */ 4143 m->m_pkthdr.len = m->m_len = len; 4144 4145 /* Send the packet to the appropriate interface. */ 4146 m->m_pkthdr.rcvif = ifp; 4147 4148 DBRUN(BCE_VERBOSE_RECV, 4149 struct ether_header *eh; 4150 eh = mtod(m, struct ether_header *); 4151 BCE_PRINTF("%s(): to: %6D, from: %6D, type: 0x%04X\n", 4152 __FUNCTION__, eh->ether_dhost, ":", 4153 eh->ether_shost, ":", htons(eh->ether_type))); 4154 4155 /* Validate the checksum if offload enabled. */ 4156 if (ifp->if_capenable & IFCAP_RXCSUM) { 4157 4158 /* Check for an IP datagram. */ 4159 if (status & L2_FHDR_STATUS_IP_DATAGRAM) { 4160 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 4161 4162 /* Check if the IP checksum is valid. */ 4163 if ((l2fhdr->l2_fhdr_ip_xsum ^ 0xffff) == 0) 4164 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 4165 else 4166 DBPRINT(sc, BCE_WARN_RECV, 4167 "%s(): Invalid IP checksum = 0x%04X!\n", 4168 __FUNCTION__, l2fhdr->l2_fhdr_ip_xsum); 4169 } 4170 4171 /* Check for a valid TCP/UDP frame. */ 4172 if (status & (L2_FHDR_STATUS_TCP_SEGMENT | 4173 L2_FHDR_STATUS_UDP_DATAGRAM)) { 4174 4175 /* Check for a good TCP/UDP checksum. */ 4176 if ((status & (L2_FHDR_ERRORS_TCP_XSUM | 4177 L2_FHDR_ERRORS_UDP_XSUM)) == 0) { 4178 m->m_pkthdr.csum_data = 4179 l2fhdr->l2_fhdr_tcp_udp_xsum; 4180 m->m_pkthdr.csum_flags |= (CSUM_DATA_VALID 4181 | CSUM_PSEUDO_HDR); 4182 } else 4183 DBPRINT(sc, BCE_WARN_RECV, 4184 "%s(): Invalid TCP/UDP checksum = 0x%04X!\n", 4185 __FUNCTION__, l2fhdr->l2_fhdr_tcp_udp_xsum); 4186 } 4187 } 4188 4189 4190 /* 4191 * If we received a packet with a vlan tag, 4192 * attach that information to the packet. 4193 */ 4194 if (status & L2_FHDR_STATUS_L2_VLAN_TAG) { 4195 DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): VLAN tag = 0x%04X\n", 4196 __FUNCTION__, l2fhdr->l2_fhdr_vlan_tag); 4197#if __FreeBSD_version < 700000 4198 VLAN_INPUT_TAG(ifp, m, l2fhdr->l2_fhdr_vlan_tag, continue); 4199#else 4200 m->m_pkthdr.ether_vtag = l2fhdr->l2_fhdr_vlan_tag; 4201 m->m_flags |= M_VLANTAG; 4202#endif 4203 } 4204 4205 /* Pass the mbuf off to the upper layers. */ 4206 ifp->if_ipackets++; 4207 4208bce_rx_int_next_rx: 4209 sw_prod = NEXT_RX_BD(sw_prod); 4210 } 4211 4212 sw_cons = NEXT_RX_BD(sw_cons); 4213 4214 /* If we have a packet, pass it up the stack */ 4215 if (m) { 4216 /* Make sure we don't lose our place when we release the lock. */ 4217 sc->rx_cons = sw_cons; 4218 sc->rx_prod = sw_prod; 4219 sc->rx_prod_bseq = sw_prod_bseq; 4220 4221 DBPRINT(sc, BCE_VERBOSE_RECV, "%s(): Passing received frame up.\n", 4222 __FUNCTION__); 4223 BCE_UNLOCK(sc); 4224 (*ifp->if_input)(ifp, m); 4225 DBRUNIF(1, sc->rx_mbuf_alloc--); 4226 BCE_LOCK(sc); 4227 4228 /* Recover our place. */ 4229 sw_cons = sc->rx_cons; 4230 sw_prod = sc->rx_prod; 4231 sw_prod_bseq = sc->rx_prod_bseq; 4232 hw_cons = sc->hw_rx_cons = sblk->status_rx_quick_consumer_index0; 4233 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 4234 hw_cons++; 4235 } 4236 4237 /* Refresh hw_cons to see if there's new work */ 4238 if (sw_cons == hw_cons) { 4239 hw_cons = sc->hw_rx_cons = sblk->status_rx_quick_consumer_index0; 4240 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 4241 hw_cons++; 4242 } 4243 4244 /* Prevent speculative reads from getting ahead of the status block. */ 4245 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 4246 BUS_SPACE_BARRIER_READ); 4247 } 4248 4249 for (int i = 0; i < RX_PAGES; i++) 4250 bus_dmamap_sync(sc->rx_bd_chain_tag, 4251 sc->rx_bd_chain_map[i], BUS_DMASYNC_PREWRITE); 4252 4253 sc->rx_cons = sw_cons; 4254 sc->rx_prod = sw_prod; 4255 sc->rx_prod_bseq = sw_prod_bseq; 4256 4257 REG_WR16(sc, MB_RX_CID_ADDR + BCE_L2CTX_HOST_BDIDX, sc->rx_prod); 4258 REG_WR(sc, MB_RX_CID_ADDR + BCE_L2CTX_HOST_BSEQ, sc->rx_prod_bseq); 4259 4260 DBPRINT(sc, BCE_INFO_RECV, "%s(exit): rx_prod = 0x%04X, " 4261 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n", 4262 __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq); 4263} 4264 4265 4266/****************************************************************************/ 4267/* Handles transmit completion interrupt events. */ 4268/* */ 4269/* Returns: */ 4270/* Nothing. */ 4271/****************************************************************************/ 4272static void 4273bce_tx_intr(struct bce_softc *sc) 4274{ 4275 struct status_block *sblk = sc->status_block; 4276 struct ifnet *ifp = sc->bce_ifp; 4277 u16 hw_tx_cons, sw_tx_cons, sw_tx_chain_cons; 4278 4279 BCE_LOCK_ASSERT(sc); 4280 4281 DBRUNIF(1, sc->tx_interrupts++); 4282 4283 /* Get the hardware's view of the TX consumer index. */ 4284 hw_tx_cons = sc->hw_tx_cons = sblk->status_tx_quick_consumer_index0; 4285 4286 /* Skip to the next entry if this is a chain page pointer. */ 4287 if ((hw_tx_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 4288 hw_tx_cons++; 4289 4290 sw_tx_cons = sc->tx_cons; 4291 4292 /* Prevent speculative reads from getting ahead of the status block. */ 4293 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 4294 BUS_SPACE_BARRIER_READ); 4295 4296 /* Cycle through any completed TX chain page entries. */ 4297 while (sw_tx_cons != hw_tx_cons) { 4298#ifdef BCE_DEBUG 4299 struct tx_bd *txbd = NULL; 4300#endif 4301 sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons); 4302 4303 DBPRINT(sc, BCE_INFO_SEND, 4304 "%s(): hw_tx_cons = 0x%04X, sw_tx_cons = 0x%04X, " 4305 "sw_tx_chain_cons = 0x%04X\n", 4306 __FUNCTION__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons); 4307 4308 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD), 4309 BCE_PRINTF("%s(%d): TX chain consumer out of range! " 4310 " 0x%04X > 0x%04X\n", __FILE__, __LINE__, sw_tx_chain_cons, 4311 (int) MAX_TX_BD); 4312 bce_breakpoint(sc)); 4313 4314 DBRUNIF(1, txbd = &sc->tx_bd_chain[TX_PAGE(sw_tx_chain_cons)] 4315 [TX_IDX(sw_tx_chain_cons)]); 4316 4317 DBRUNIF((txbd == NULL), 4318 BCE_PRINTF("%s(%d): Unexpected NULL tx_bd[0x%04X]!\n", 4319 __FILE__, __LINE__, sw_tx_chain_cons); 4320 bce_breakpoint(sc)); 4321 4322 DBRUN(BCE_INFO_SEND, BCE_PRINTF("%s(): ", __FUNCTION__); 4323 bce_dump_txbd(sc, sw_tx_chain_cons, txbd)); 4324 4325 /* 4326 * Free the associated mbuf. Remember 4327 * that only the last tx_bd of a packet 4328 * has an mbuf pointer and DMA map. 4329 */ 4330 if (sc->tx_mbuf_ptr[sw_tx_chain_cons] != NULL) { 4331 4332 /* Validate that this is the last tx_bd. */ 4333 DBRUNIF((!(txbd->tx_bd_flags & TX_BD_FLAGS_END)), 4334 BCE_PRINTF("%s(%d): tx_bd END flag not set but " 4335 "txmbuf == NULL!\n", __FILE__, __LINE__); 4336 bce_breakpoint(sc)); 4337 4338 DBRUN(BCE_INFO_SEND, 4339 BCE_PRINTF("%s(): Unloading map/freeing mbuf " 4340 "from tx_bd[0x%04X]\n", __FUNCTION__, sw_tx_chain_cons)); 4341 4342 /* Unmap the mbuf. */ 4343 bus_dmamap_unload(sc->tx_mbuf_tag, 4344 sc->tx_mbuf_map[sw_tx_chain_cons]); 4345 4346 /* Free the mbuf. */ 4347 m_freem(sc->tx_mbuf_ptr[sw_tx_chain_cons]); 4348 sc->tx_mbuf_ptr[sw_tx_chain_cons] = NULL; 4349 DBRUNIF(1, sc->tx_mbuf_alloc--); 4350 4351 ifp->if_opackets++; 4352 } 4353 4354 sc->used_tx_bd--; 4355 sw_tx_cons = NEXT_TX_BD(sw_tx_cons); 4356 4357 /* Refresh hw_cons to see if there's new work. */ 4358 hw_tx_cons = sc->hw_tx_cons = sblk->status_tx_quick_consumer_index0; 4359 if ((hw_tx_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 4360 hw_tx_cons++; 4361 4362 /* Prevent speculative reads from getting ahead of the status block. */ 4363 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 4364 BUS_SPACE_BARRIER_READ); 4365 } 4366 4367 /* Clear the TX timeout timer. */ 4368 sc->watchdog_timer = 0; 4369 4370 /* Clear the tx hardware queue full flag. */ 4371 if (sc->used_tx_bd < sc->max_tx_bd) { 4372 DBRUNIF((ifp->if_drv_flags & IFF_DRV_OACTIVE), 4373 DBPRINT(sc, BCE_WARN_SEND, 4374 "%s(): Open TX chain! %d/%d (used/total)\n", 4375 __FUNCTION__, sc->used_tx_bd, sc->max_tx_bd)); 4376 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 4377 } 4378 4379 sc->tx_cons = sw_tx_cons; 4380} 4381 4382 4383/****************************************************************************/ 4384/* Disables interrupt generation. */ 4385/* */ 4386/* Returns: */ 4387/* Nothing. */ 4388/****************************************************************************/ 4389static void 4390bce_disable_intr(struct bce_softc *sc) 4391{ 4392 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 4393 BCE_PCICFG_INT_ACK_CMD_MASK_INT); 4394 REG_RD(sc, BCE_PCICFG_INT_ACK_CMD); 4395} 4396 4397 4398/****************************************************************************/ 4399/* Enables interrupt generation. */ 4400/* */ 4401/* Returns: */ 4402/* Nothing. */ 4403/****************************************************************************/ 4404static void 4405bce_enable_intr(struct bce_softc *sc) 4406{ 4407 u32 val; 4408 4409 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 4410 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | 4411 BCE_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx); 4412 4413 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 4414 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx); 4415 4416 val = REG_RD(sc, BCE_HC_COMMAND); 4417 REG_WR(sc, BCE_HC_COMMAND, val | BCE_HC_COMMAND_COAL_NOW); 4418} 4419 4420 4421/****************************************************************************/ 4422/* Handles controller initialization. */ 4423/* */ 4424/* Returns: */ 4425/* Nothing. */ 4426/****************************************************************************/ 4427static void 4428bce_init_locked(struct bce_softc *sc) 4429{ 4430 struct ifnet *ifp; 4431 u32 ether_mtu; 4432 4433 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 4434 4435 BCE_LOCK_ASSERT(sc); 4436 4437 ifp = sc->bce_ifp; 4438 4439 /* Check if the driver is still running and bail out if it is. */ 4440 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 4441 goto bce_init_locked_exit; 4442 4443 bce_stop(sc); 4444 4445 if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) { 4446 BCE_PRINTF("%s(%d): Controller reset failed!\n", 4447 __FILE__, __LINE__); 4448 goto bce_init_locked_exit; 4449 } 4450 4451 if (bce_chipinit(sc)) { 4452 BCE_PRINTF("%s(%d): Controller initialization failed!\n", 4453 __FILE__, __LINE__); 4454 goto bce_init_locked_exit; 4455 } 4456 4457 if (bce_blockinit(sc)) { 4458 BCE_PRINTF("%s(%d): Block initialization failed!\n", 4459 __FILE__, __LINE__); 4460 goto bce_init_locked_exit; 4461 } 4462 4463 /* Load our MAC address. */ 4464 bcopy(IF_LLADDR(sc->bce_ifp), sc->eaddr, ETHER_ADDR_LEN); 4465 bce_set_mac_addr(sc); 4466 4467 /* Calculate and program the Ethernet MTU size. */ 4468 ether_mtu = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ifp->if_mtu + 4469 ETHER_CRC_LEN; 4470 4471 DBPRINT(sc, BCE_INFO, "%s(): setting mtu = %d\n",__FUNCTION__, ether_mtu); 4472 4473 /* 4474 * Program the mtu, enabling jumbo frame 4475 * support if necessary. Also set the mbuf 4476 * allocation count for RX frames. 4477 */ 4478 if (ether_mtu > ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) { 4479 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, min(ether_mtu, BCE_MAX_JUMBO_ETHER_MTU) | 4480 BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA); 4481 sc->mbuf_alloc_size = MJUM9BYTES; 4482 } else { 4483 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, ether_mtu); 4484 sc->mbuf_alloc_size = MCLBYTES; 4485 } 4486 4487 /* Calculate the RX Ethernet frame size for rx_bd's. */ 4488 sc->max_frame_size = sizeof(struct l2_fhdr) + 2 + ether_mtu + 8; 4489 4490 DBPRINT(sc, BCE_INFO, 4491 "%s(): mclbytes = %d, mbuf_alloc_size = %d, " 4492 "max_frame_size = %d\n", 4493 __FUNCTION__, (int) MCLBYTES, sc->mbuf_alloc_size, sc->max_frame_size); 4494 4495 /* Program appropriate promiscuous/multicast filtering. */ 4496 bce_set_rx_mode(sc); 4497 4498 /* Init RX buffer descriptor chain. */ 4499 bce_init_rx_chain(sc); 4500 4501 /* Init TX buffer descriptor chain. */ 4502 bce_init_tx_chain(sc); 4503 4504#ifdef DEVICE_POLLING 4505 /* Disable interrupts if we are polling. */ 4506 if (ifp->if_capenable & IFCAP_POLLING) { 4507 bce_disable_intr(sc); 4508 4509 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP, 4510 (1 << 16) | sc->bce_rx_quick_cons_trip); 4511 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP, 4512 (1 << 16) | sc->bce_tx_quick_cons_trip); 4513 } else 4514#endif 4515 /* Enable host interrupts. */ 4516 bce_enable_intr(sc); 4517 4518 bce_ifmedia_upd_locked(ifp); 4519 4520 ifp->if_drv_flags |= IFF_DRV_RUNNING; 4521 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 4522 4523 callout_reset(&sc->bce_stat_ch, hz, bce_tick, sc); 4524 4525bce_init_locked_exit: 4526 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 4527 4528 return; 4529} 4530 4531 4532/****************************************************************************/ 4533/* Initialize the controller just enough so that any management firmware */ 4534/* running on the device will continue to operate corectly. */ 4535/* */ 4536/* Returns: */ 4537/* Nothing. */ 4538/****************************************************************************/ 4539static void 4540bce_mgmt_init_locked(struct bce_softc *sc) 4541{ 4542 u32 val; 4543 struct ifnet *ifp; 4544 4545 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 4546 4547 BCE_LOCK_ASSERT(sc); 4548 4549 ifp = sc->bce_ifp; 4550 4551 /* Check if the driver is still running and bail out if it is. */ 4552 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 4553 goto bce_mgmt_init_locked_exit; 4554 4555 /* Initialize the on-boards CPUs */ 4556 bce_init_cpus(sc); 4557 4558 /* Set the page size and clear the RV2P processor stall bits. */ 4559 val = (BCM_PAGE_BITS - 8) << 24; 4560 REG_WR(sc, BCE_RV2P_CONFIG, val); 4561 4562 /* Enable all critical blocks in the MAC. */ 4563 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 4564 BCE_MISC_ENABLE_SET_BITS_RX_V2P_ENABLE | 4565 BCE_MISC_ENABLE_SET_BITS_RX_DMA_ENABLE | 4566 BCE_MISC_ENABLE_SET_BITS_COMPLETION_ENABLE); 4567 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS); 4568 DELAY(20); 4569 4570 bce_ifmedia_upd_locked(ifp); 4571bce_mgmt_init_locked_exit: 4572 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 4573 4574 return; 4575} 4576 4577 4578/****************************************************************************/ 4579/* Handles controller initialization when called from an unlocked routine. */ 4580/* */ 4581/* Returns: */ 4582/* Nothing. */ 4583/****************************************************************************/ 4584static void 4585bce_init(void *xsc) 4586{ 4587 struct bce_softc *sc = xsc; 4588 4589 BCE_LOCK(sc); 4590 bce_init_locked(sc); 4591 BCE_UNLOCK(sc); 4592} 4593 4594 4595/****************************************************************************/ 4596/* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */ 4597/* memory visible to the controller. */ 4598/* */ 4599/* Returns: */ 4600/* 0 for success, positive value for failure. */ 4601/****************************************************************************/ 4602static int 4603bce_tx_encap(struct bce_softc *sc, struct mbuf **m_head) 4604{ 4605 bus_dma_segment_t segs[BCE_MAX_SEGMENTS]; 4606 bus_dmamap_t map; 4607 struct tx_bd *txbd = NULL; 4608 struct mbuf *m0; 4609 struct ether_vlan_header *eh; 4610 struct ip *ip; 4611 struct tcphdr *th; 4612 u16 prod, chain_prod, etype, mss = 0, vlan_tag = 0, flags = 0; 4613 u32 prod_bseq; 4614 int hdr_len = 0, e_hlen = 0, ip_hlen = 0, tcp_hlen = 0, ip_len = 0; 4615 4616 4617#ifdef BCE_DEBUG 4618 u16 debug_prod; 4619#endif 4620 int i, error, nsegs, rc = 0; 4621 4622 /* Transfer any checksum offload flags to the bd. */ 4623 m0 = *m_head; 4624 if (m0->m_pkthdr.csum_flags) { 4625 if (m0->m_pkthdr.csum_flags & CSUM_IP) 4626 flags |= TX_BD_FLAGS_IP_CKSUM; 4627 if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 4628 flags |= TX_BD_FLAGS_TCP_UDP_CKSUM; 4629 if (m0->m_pkthdr.csum_flags & CSUM_TSO) { 4630 /* For TSO the controller needs two pieces of info, */ 4631 /* the MSS and the IP+TCP options length. */ 4632 mss = htole16(m0->m_pkthdr.tso_segsz); 4633 4634 /* Map the header and find the Ethernet type & header length */ 4635 eh = mtod(m0, struct ether_vlan_header *); 4636 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 4637 etype = ntohs(eh->evl_proto); 4638 e_hlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 4639 } else { 4640 etype = ntohs(eh->evl_encap_proto); 4641 e_hlen = ETHER_HDR_LEN; 4642 } 4643 4644 /* Check for supported TSO Ethernet types (only IPv4 for now) */ 4645 switch (etype) { 4646 case ETHERTYPE_IP: 4647 ip = (struct ip *)(m0->m_data + e_hlen); 4648 4649 /* TSO only supported for TCP protocol */ 4650 if (ip->ip_p != IPPROTO_TCP) { 4651 BCE_PRINTF("%s(%d): TSO enabled for non-TCP frame!.\n", 4652 __FILE__, __LINE__); 4653 goto bce_tx_encap_skip_tso; 4654 } 4655 4656 /* Get IP header length in bytes (min 20) */ 4657 ip_hlen = ip->ip_hl << 2; 4658 4659 /* Get the TCP header length in bytes (min 20) */ 4660 th = (struct tcphdr *)((caddr_t)ip + ip_hlen); 4661 tcp_hlen = (th->th_off << 2); 4662 4663 /* IP header length and checksum will be calc'd by hardware */ 4664 ip_len = ip->ip_len; 4665 ip->ip_len = 0; 4666 ip->ip_sum = 0; 4667 break; 4668 case ETHERTYPE_IPV6: 4669 BCE_PRINTF("%s(%d): TSO over IPv6 not supported!.\n", 4670 __FILE__, __LINE__); 4671 goto bce_tx_encap_skip_tso; 4672 default: 4673 BCE_PRINTF("%s(%d): TSO enabled for unsupported protocol!.\n", 4674 __FILE__, __LINE__); 4675 goto bce_tx_encap_skip_tso; 4676 } 4677 4678 hdr_len = e_hlen + ip_hlen + tcp_hlen; 4679 4680 DBPRINT(sc, BCE_EXCESSIVE_SEND, 4681 "%s(): hdr_len = %d, e_hlen = %d, ip_hlen = %d, tcp_hlen = %d, ip_len = %d\n", 4682 __FUNCTION__, hdr_len, e_hlen, ip_hlen, tcp_hlen, ip_len); 4683 4684 /* Set the LSO flag in the TX BD */ 4685 flags |= TX_BD_FLAGS_SW_LSO; 4686 /* Set the length of IP + TCP options (in 32 bit words) */ 4687 flags |= (((ip_hlen + tcp_hlen - 40) >> 2) << 8); 4688 4689bce_tx_encap_skip_tso: 4690 DBRUNIF(1, sc->requested_tso_frames++); 4691 } 4692 } 4693 4694 /* Transfer any VLAN tags to the bd. */ 4695 if (m0->m_flags & M_VLANTAG) { 4696 flags |= TX_BD_FLAGS_VLAN_TAG; 4697 vlan_tag = m0->m_pkthdr.ether_vtag; 4698 } 4699 4700 /* Map the mbuf into DMAable memory. */ 4701 prod = sc->tx_prod; 4702 chain_prod = TX_CHAIN_IDX(prod); 4703 map = sc->tx_mbuf_map[chain_prod]; 4704 4705 /* Map the mbuf into our DMA address space. */ 4706 error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag, map, m0, 4707 segs, &nsegs, BUS_DMA_NOWAIT); 4708 4709 /* Check if the DMA mapping was successful */ 4710 if (error == EFBIG) { 4711 4712 DBPRINT(sc, BCE_WARN, "%s(): fragmented mbuf (%d pieces)\n", 4713 __FUNCTION__, nsegs); 4714 DBRUNIF(1, bce_dump_mbuf(sc, m0);); 4715 4716 /* Try to defrag the mbuf if there are too many segments. */ 4717 m0 = m_defrag(*m_head, M_DONTWAIT); 4718 if (m0 == NULL) { 4719 /* Defrag was unsuccessful */ 4720 m_freem(*m_head); 4721 *m_head = NULL; 4722 return (ENOBUFS); 4723 } 4724 4725 /* Defrag was successful, try mapping again */ 4726 *m_head = m0; 4727 error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag, map, m0, 4728 segs, &nsegs, BUS_DMA_NOWAIT); 4729 4730 /* Still getting an error after a defrag. */ 4731 if (error == ENOMEM) { 4732 return (error); 4733 } else if (error != 0) { 4734 BCE_PRINTF( 4735 "%s(%d): Unknown error mapping mbuf into TX chain!\n", 4736 __FILE__, __LINE__); 4737 m_freem(m0); 4738 *m_head = NULL; 4739 return (ENOBUFS); 4740 } 4741 } else if (error == ENOMEM) { 4742 return (error); 4743 } else if (error != 0) { 4744 m_freem(m0); 4745 *m_head = NULL; 4746 return (error); 4747 } 4748 4749 /* Make sure there's room in the chain */ 4750 if (nsegs > (sc->max_tx_bd - sc->used_tx_bd)) { 4751 bus_dmamap_unload(sc->tx_mbuf_tag, map); 4752 return (ENOBUFS); 4753 } 4754 4755 /* prod points to an empty tx_bd at this point. */ 4756 prod_bseq = sc->tx_prod_bseq; 4757 4758#ifdef BCE_DEBUG 4759 debug_prod = chain_prod; 4760#endif 4761 4762 DBPRINT(sc, BCE_INFO_SEND, 4763 "%s(): Start: prod = 0x%04X, chain_prod = %04X, " 4764 "prod_bseq = 0x%08X\n", 4765 __FUNCTION__, prod, chain_prod, prod_bseq); 4766 4767 /* 4768 * Cycle through each mbuf segment that makes up 4769 * the outgoing frame, gathering the mapping info 4770 * for that segment and creating a tx_bd to for 4771 * the mbuf. 4772 */ 4773 for (i = 0; i < nsegs ; i++) { 4774 4775 chain_prod = TX_CHAIN_IDX(prod); 4776 txbd= &sc->tx_bd_chain[TX_PAGE(chain_prod)][TX_IDX(chain_prod)]; 4777 4778 txbd->tx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[i].ds_addr)); 4779 txbd->tx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[i].ds_addr)); 4780 txbd->tx_bd_mss_nbytes = htole32(mss << 16) | htole16(segs[i].ds_len); 4781 txbd->tx_bd_vlan_tag = htole16(vlan_tag); 4782 txbd->tx_bd_flags = htole16(flags); 4783 prod_bseq += segs[i].ds_len; 4784 if (i == 0) 4785 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_START); 4786 prod = NEXT_TX_BD(prod); 4787 } 4788 4789 /* Set the END flag on the last TX buffer descriptor. */ 4790 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_END); 4791 4792 DBRUN(BCE_EXCESSIVE_SEND, bce_dump_tx_chain(sc, debug_prod, nsegs)); 4793 4794 DBPRINT(sc, BCE_INFO_SEND, 4795 "%s(): End: prod = 0x%04X, chain_prod = %04X, " 4796 "prod_bseq = 0x%08X\n", 4797 __FUNCTION__, prod, chain_prod, prod_bseq); 4798 4799 /* 4800 * Ensure that the mbuf pointer for this transmission 4801 * is placed at the array index of the last 4802 * descriptor in this chain. This is done 4803 * because a single map is used for all 4804 * segments of the mbuf and we don't want to 4805 * unload the map before all of the segments 4806 * have been freed. 4807 */ 4808 sc->tx_mbuf_ptr[chain_prod] = m0; 4809 sc->used_tx_bd += nsegs; 4810 4811 /* Update some debug statistic counters */ 4812 DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark), 4813 sc->tx_hi_watermark = sc->used_tx_bd); 4814 DBRUNIF((sc->used_tx_bd == sc->max_tx_bd), sc->tx_full_count++); 4815 DBRUNIF(1, sc->tx_mbuf_alloc++); 4816 4817 DBRUN(BCE_VERBOSE_SEND, bce_dump_tx_mbuf_chain(sc, chain_prod, nsegs)); 4818 4819 /* prod points to the next free tx_bd at this point. */ 4820 sc->tx_prod = prod; 4821 sc->tx_prod_bseq = prod_bseq; 4822 4823 return(rc); 4824} 4825 4826 4827/****************************************************************************/ 4828/* Main transmit routine when called from another routine with a lock. */ 4829/* */ 4830/* Returns: */ 4831/* Nothing. */ 4832/****************************************************************************/ 4833static void 4834bce_start_locked(struct ifnet *ifp) 4835{ 4836 struct bce_softc *sc = ifp->if_softc; 4837 struct mbuf *m_head = NULL; 4838 int count = 0; 4839 u16 tx_prod, tx_chain_prod; 4840 4841 /* If there's no link or the transmit queue is empty then just exit. */ 4842 if (!sc->bce_link || IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 4843 DBPRINT(sc, BCE_INFO_SEND, "%s(): No link or transmit queue empty.\n", 4844 __FUNCTION__); 4845 goto bce_start_locked_exit; 4846 } 4847 4848 /* prod points to the next free tx_bd. */ 4849 tx_prod = sc->tx_prod; 4850 tx_chain_prod = TX_CHAIN_IDX(tx_prod); 4851 4852 DBPRINT(sc, BCE_INFO_SEND, 4853 "%s(): Start: tx_prod = 0x%04X, tx_chain_prod = %04X, " 4854 "tx_prod_bseq = 0x%08X\n", 4855 __FUNCTION__, tx_prod, tx_chain_prod, sc->tx_prod_bseq); 4856 4857 /* 4858 * Keep adding entries while there is space in the ring. 4859 */ 4860 while (sc->used_tx_bd < sc->max_tx_bd) { 4861 4862 /* Check for any frames to send. */ 4863 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 4864 if (m_head == NULL) 4865 break; 4866 4867 /* 4868 * Pack the data into the transmit ring. If we 4869 * don't have room, place the mbuf back at the 4870 * head of the queue and set the OACTIVE flag 4871 * to wait for the NIC to drain the chain. 4872 */ 4873 if (bce_tx_encap(sc, &m_head)) { 4874 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 4875 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 4876 DBPRINT(sc, BCE_INFO_SEND, 4877 "TX chain is closed for business! Total tx_bd used = %d\n", 4878 sc->used_tx_bd); 4879 break; 4880 } 4881 4882 count++; 4883 4884 /* Send a copy of the frame to any BPF listeners. */ 4885 ETHER_BPF_MTAP(ifp, m_head); 4886 } 4887 4888 if (count == 0) { 4889 /* no packets were dequeued */ 4890 DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): No packets were dequeued\n", 4891 __FUNCTION__); 4892 goto bce_start_locked_exit; 4893 } 4894 4895 /* Update the driver's counters. */ 4896 tx_chain_prod = TX_CHAIN_IDX(sc->tx_prod); 4897 4898 DBPRINT(sc, BCE_INFO_SEND, 4899 "%s(): End: tx_prod = 0x%04X, tx_chain_prod = 0x%04X, " 4900 "tx_prod_bseq = 0x%08X\n", 4901 __FUNCTION__, tx_prod, tx_chain_prod, sc->tx_prod_bseq); 4902 4903 /* Start the transmit. */ 4904 REG_WR16(sc, MB_TX_CID_ADDR + BCE_L2CTX_TX_HOST_BIDX, sc->tx_prod); 4905 REG_WR(sc, MB_TX_CID_ADDR + BCE_L2CTX_TX_HOST_BSEQ, sc->tx_prod_bseq); 4906 4907 /* Set the tx timeout. */ 4908 sc->watchdog_timer = BCE_TX_TIMEOUT; 4909 4910bce_start_locked_exit: 4911 return; 4912} 4913 4914 4915/****************************************************************************/ 4916/* Main transmit routine when called from another routine without a lock. */ 4917/* */ 4918/* Returns: */ 4919/* Nothing. */ 4920/****************************************************************************/ 4921static void 4922bce_start(struct ifnet *ifp) 4923{ 4924 struct bce_softc *sc = ifp->if_softc; 4925 4926 BCE_LOCK(sc); 4927 bce_start_locked(ifp); 4928 BCE_UNLOCK(sc); 4929} 4930 4931 4932/****************************************************************************/ 4933/* Handles any IOCTL calls from the operating system. */ 4934/* */ 4935/* Returns: */ 4936/* 0 for success, positive value for failure. */ 4937/****************************************************************************/ 4938static int 4939bce_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 4940{ 4941 struct bce_softc *sc = ifp->if_softc; 4942 struct ifreq *ifr = (struct ifreq *) data; 4943 struct mii_data *mii; 4944 int mask, error = 0; 4945 4946 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 4947 4948 switch(command) { 4949 4950 /* Set the MTU. */ 4951 case SIOCSIFMTU: 4952 /* Check that the MTU setting is supported. */ 4953 if ((ifr->ifr_mtu < BCE_MIN_MTU) || 4954 (ifr->ifr_mtu > BCE_MAX_JUMBO_MTU)) { 4955 error = EINVAL; 4956 break; 4957 } 4958 4959 DBPRINT(sc, BCE_INFO, "Setting new MTU of %d\n", ifr->ifr_mtu); 4960 4961 BCE_LOCK(sc); 4962 ifp->if_mtu = ifr->ifr_mtu; 4963 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 4964 bce_init_locked(sc); 4965 BCE_UNLOCK(sc); 4966 break; 4967 4968 /* Set interface. */ 4969 case SIOCSIFFLAGS: 4970 DBPRINT(sc, BCE_VERBOSE, "Received SIOCSIFFLAGS\n"); 4971 4972 BCE_LOCK(sc); 4973 4974 /* Check if the interface is up. */ 4975 if (ifp->if_flags & IFF_UP) { 4976 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 4977 /* Change the promiscuous/multicast flags as necessary. */ 4978 bce_set_rx_mode(sc); 4979 } else { 4980 /* Start the HW */ 4981 bce_init_locked(sc); 4982 } 4983 } else { 4984 /* The interface is down. Check if the driver is running. */ 4985 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 4986 bce_stop(sc); 4987 } 4988 } 4989 4990 BCE_UNLOCK(sc); 4991 error = 0; 4992 4993 break; 4994 4995 /* Add/Delete multicast address */ 4996 case SIOCADDMULTI: 4997 case SIOCDELMULTI: 4998 DBPRINT(sc, BCE_VERBOSE, "Received SIOCADDMULTI/SIOCDELMULTI\n"); 4999 5000 BCE_LOCK(sc); 5001 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 5002 bce_set_rx_mode(sc); 5003 error = 0; 5004 } 5005 BCE_UNLOCK(sc); 5006 5007 break; 5008 5009 /* Set/Get Interface media */ 5010 case SIOCSIFMEDIA: 5011 case SIOCGIFMEDIA: 5012 DBPRINT(sc, BCE_VERBOSE, "Received SIOCSIFMEDIA/SIOCGIFMEDIA\n"); 5013 5014 DBPRINT(sc, BCE_VERBOSE, "bce_phy_flags = 0x%08X\n", 5015 sc->bce_phy_flags); 5016 5017 DBPRINT(sc, BCE_VERBOSE, "Copper media set/get\n"); 5018 mii = device_get_softc(sc->bce_miibus); 5019 error = ifmedia_ioctl(ifp, ifr, 5020 &mii->mii_media, command); 5021 break; 5022 5023 /* Set interface capability */ 5024 case SIOCSIFCAP: 5025 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 5026 DBPRINT(sc, BCE_INFO, "Received SIOCSIFCAP = 0x%08X\n", (u32) mask); 5027 5028#ifdef DEVICE_POLLING 5029 if (mask & IFCAP_POLLING) { 5030 if (ifr->ifr_reqcap & IFCAP_POLLING) { 5031 5032 /* Setup the poll routine to call. */ 5033 error = ether_poll_register(bce_poll, ifp); 5034 if (error) { 5035 BCE_PRINTF("%s(%d): Error registering poll function!\n", 5036 __FILE__, __LINE__); 5037 goto bce_ioctl_exit; 5038 } 5039 5040 /* Clear the interrupt. */ 5041 BCE_LOCK(sc); 5042 bce_disable_intr(sc); 5043 5044 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP, 5045 (1 << 16) | sc->bce_rx_quick_cons_trip); 5046 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP, 5047 (1 << 16) | sc->bce_tx_quick_cons_trip); 5048 5049 ifp->if_capenable |= IFCAP_POLLING; 5050 BCE_UNLOCK(sc); 5051 } else { 5052 /* Clear the poll routine. */ 5053 error = ether_poll_deregister(ifp); 5054 5055 /* Enable interrupt even in error case */ 5056 BCE_LOCK(sc); 5057 bce_enable_intr(sc); 5058 5059 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP, 5060 (sc->bce_tx_quick_cons_trip_int << 16) | 5061 sc->bce_tx_quick_cons_trip); 5062 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP, 5063 (sc->bce_rx_quick_cons_trip_int << 16) | 5064 sc->bce_rx_quick_cons_trip); 5065 5066 ifp->if_capenable &= ~IFCAP_POLLING; 5067 BCE_UNLOCK(sc); 5068 } 5069 } 5070#endif /*DEVICE_POLLING */ 5071 5072 /* Toggle the TX checksum capabilites enable flag. */ 5073 if (mask & IFCAP_TXCSUM) { 5074 ifp->if_capenable ^= IFCAP_TXCSUM; 5075 if (IFCAP_TXCSUM & ifp->if_capenable) 5076 ifp->if_hwassist = BCE_IF_HWASSIST; 5077 else 5078 ifp->if_hwassist = 0; 5079 } 5080 5081 /* Toggle the RX checksum capabilities enable flag. */ 5082 if (mask & IFCAP_RXCSUM) { 5083 ifp->if_capenable ^= IFCAP_RXCSUM; 5084 if (IFCAP_RXCSUM & ifp->if_capenable) 5085 ifp->if_hwassist = BCE_IF_HWASSIST; 5086 else 5087 ifp->if_hwassist = 0; 5088 } 5089 5090 /* Toggle the TSO capabilities enable flag. */ 5091 if (bce_tso_enable && (mask & IFCAP_TSO4)) { 5092 ifp->if_capenable ^= IFCAP_TSO4; 5093 if (IFCAP_RXCSUM & ifp->if_capenable) 5094 ifp->if_hwassist = BCE_IF_HWASSIST; 5095 else 5096 ifp->if_hwassist = 0; 5097 } 5098 5099 /* Toggle VLAN_MTU capabilities enable flag. */ 5100 if (mask & IFCAP_VLAN_MTU) { 5101 BCE_PRINTF("%s(%d): Changing VLAN_MTU not supported.\n", 5102 __FILE__, __LINE__); 5103 } 5104 5105 /* Toggle VLANHWTAG capabilities enabled flag. */ 5106 if (mask & IFCAP_VLAN_HWTAGGING) { 5107 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) 5108 BCE_PRINTF("%s(%d): Cannot change VLAN_HWTAGGING while " 5109 "management firmware (ASF/IPMI/UMP) is running!\n", 5110 __FILE__, __LINE__); 5111 else 5112 BCE_PRINTF("%s(%d): Changing VLAN_HWTAGGING not supported!\n", 5113 __FILE__, __LINE__); 5114 } 5115 5116 break; 5117 default: 5118 DBPRINT(sc, BCE_INFO, "Received unsupported IOCTL: 0x%08X\n", 5119 (u32) command); 5120 5121 /* We don't know how to handle the IOCTL, pass it on. */ 5122 error = ether_ioctl(ifp, command, data); 5123 break; 5124 } 5125 5126#ifdef DEVICE_POLLING 5127bce_ioctl_exit: 5128#endif 5129 5130 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 5131 5132 return(error); 5133} 5134 5135 5136/****************************************************************************/ 5137/* Transmit timeout handler. */ 5138/* */ 5139/* Returns: */ 5140/* Nothing. */ 5141/****************************************************************************/ 5142static void 5143bce_watchdog(struct bce_softc *sc) 5144{ 5145 5146 DBRUN(BCE_VERBOSE_SEND, 5147 bce_dump_driver_state(sc); 5148 bce_dump_status_block(sc)); 5149 5150 BCE_LOCK_ASSERT(sc); 5151 5152 if (sc->watchdog_timer == 0 || --sc->watchdog_timer) 5153 return; 5154 5155 /* 5156 * If we are in this routine because of pause frames, then 5157 * don't reset the hardware. 5158 */ 5159 if (REG_RD(sc, BCE_EMAC_TX_STATUS) & BCE_EMAC_TX_STATUS_XOFFED) 5160 return; 5161 5162 BCE_PRINTF("%s(%d): Watchdog timeout occurred, resetting!\n", 5163 __FILE__, __LINE__); 5164 5165 /* DBRUN(BCE_FATAL, bce_breakpoint(sc)); */ 5166 5167 sc->bce_ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 5168 5169 bce_init_locked(sc); 5170 sc->bce_ifp->if_oerrors++; 5171 5172} 5173 5174 5175#ifdef DEVICE_POLLING 5176static void 5177bce_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 5178{ 5179 struct bce_softc *sc = ifp->if_softc; 5180 5181 BCE_LOCK_ASSERT(sc); 5182 5183 sc->bce_rxcycles = count; 5184 5185 bus_dmamap_sync(sc->status_tag, sc->status_map, 5186 BUS_DMASYNC_POSTWRITE); 5187 5188 /* Check for any completed RX frames. */ 5189 if (sc->status_block->status_rx_quick_consumer_index0 != 5190 sc->hw_rx_cons) 5191 bce_rx_intr(sc); 5192 5193 /* Check for any completed TX frames. */ 5194 if (sc->status_block->status_tx_quick_consumer_index0 != 5195 sc->hw_tx_cons) 5196 bce_tx_intr(sc); 5197 5198 /* Check for new frames to transmit. */ 5199 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 5200 bce_start_locked(ifp); 5201 5202} 5203 5204 5205static void 5206bce_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 5207{ 5208 struct bce_softc *sc = ifp->if_softc; 5209 5210 BCE_LOCK(sc); 5211 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 5212 bce_poll_locked(ifp, cmd, count); 5213 BCE_UNLOCK(sc); 5214} 5215#endif /* DEVICE_POLLING */ 5216 5217 5218#if 0 5219static inline int 5220bce_has_work(struct bce_softc *sc) 5221{ 5222 struct status_block *stat = sc->status_block; 5223 5224 if ((stat->status_rx_quick_consumer_index0 != sc->hw_rx_cons) || 5225 (stat->status_tx_quick_consumer_index0 != sc->hw_tx_cons)) 5226 return 1; 5227 5228 if (((stat->status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != 0) != 5229 bp->link_up) 5230 return 1; 5231 5232 return 0; 5233} 5234#endif 5235 5236 5237/* 5238 * Interrupt handler. 5239 */ 5240/****************************************************************************/ 5241/* Main interrupt entry point. Verifies that the controller generated the */ 5242/* interrupt and then calls a separate routine for handle the various */ 5243/* interrupt causes (PHY, TX, RX). */ 5244/* */ 5245/* Returns: */ 5246/* 0 for success, positive value for failure. */ 5247/****************************************************************************/ 5248static void 5249bce_intr(void *xsc) 5250{ 5251 struct bce_softc *sc; 5252 struct ifnet *ifp; 5253 u32 status_attn_bits; 5254 5255 sc = xsc; 5256 ifp = sc->bce_ifp; 5257 5258 DBPRINT(sc, BCE_EXCESSIVE, "Entering %s()\n", __FUNCTION__); 5259 BCE_LOCK(sc); 5260 5261 DBRUNIF(1, sc->interrupts_generated++); 5262 5263#ifdef DEVICE_POLLING 5264 if (ifp->if_capenable & IFCAP_POLLING) { 5265 DBPRINT(sc, BCE_INFO, "Polling enabled!\n"); 5266 goto bce_intr_exit; 5267 } 5268#endif 5269 5270 bus_dmamap_sync(sc->status_tag, sc->status_map, 5271 BUS_DMASYNC_POSTWRITE); 5272 5273 /* 5274 * If the hardware status block index 5275 * matches the last value read by the 5276 * driver and we haven't asserted our 5277 * interrupt then there's nothing to do. 5278 */ 5279 if ((sc->status_block->status_idx == sc->last_status_idx) && 5280 (REG_RD(sc, BCE_PCICFG_MISC_STATUS) & BCE_PCICFG_MISC_STATUS_INTA_VALUE)) 5281 goto bce_intr_exit; 5282 5283 /* Ack the interrupt and stop others from occuring. */ 5284 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 5285 BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM | 5286 BCE_PCICFG_INT_ACK_CMD_MASK_INT); 5287 5288 /* Keep processing data as long as there is work to do. */ 5289 for (;;) { 5290 5291 status_attn_bits = sc->status_block->status_attn_bits; 5292 5293 DBRUNIF(DB_RANDOMTRUE(bce_debug_unexpected_attention), 5294 BCE_PRINTF("Simulating unexpected status attention bit set."); 5295 status_attn_bits = status_attn_bits | STATUS_ATTN_BITS_PARITY_ERROR); 5296 5297 /* Was it a link change interrupt? */ 5298 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != 5299 (sc->status_block->status_attn_bits_ack & STATUS_ATTN_BITS_LINK_STATE)) 5300 bce_phy_intr(sc); 5301 5302 /* If any other attention is asserted then the chip is toast. */ 5303 if (((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) != 5304 (sc->status_block->status_attn_bits_ack & 5305 ~STATUS_ATTN_BITS_LINK_STATE))) { 5306 5307 DBRUN(1, sc->unexpected_attentions++); 5308 5309 BCE_PRINTF("%s(%d): Fatal attention detected: 0x%08X\n", 5310 __FILE__, __LINE__, sc->status_block->status_attn_bits); 5311 5312 DBRUN(BCE_FATAL, 5313 if (bce_debug_unexpected_attention == 0) 5314 bce_breakpoint(sc)); 5315 5316 bce_init_locked(sc); 5317 goto bce_intr_exit; 5318 } 5319 5320 /* Check for any completed RX frames. */ 5321 if (sc->status_block->status_rx_quick_consumer_index0 != sc->hw_rx_cons) 5322 bce_rx_intr(sc); 5323 5324 /* Check for any completed TX frames. */ 5325 if (sc->status_block->status_tx_quick_consumer_index0 != sc->hw_tx_cons) 5326 bce_tx_intr(sc); 5327 5328 /* Save the status block index value for use during the next interrupt. */ 5329 sc->last_status_idx = sc->status_block->status_idx; 5330 5331 /* Prevent speculative reads from getting ahead of the status block. */ 5332 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 5333 BUS_SPACE_BARRIER_READ); 5334 5335 /* If there's no work left then exit the interrupt service routine. */ 5336 if ((sc->status_block->status_rx_quick_consumer_index0 == sc->hw_rx_cons) && 5337 (sc->status_block->status_tx_quick_consumer_index0 == sc->hw_tx_cons)) 5338 break; 5339 5340 } 5341 5342 bus_dmamap_sync(sc->status_tag, sc->status_map, 5343 BUS_DMASYNC_PREWRITE); 5344 5345 /* Re-enable interrupts. */ 5346 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 5347 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx | 5348 BCE_PCICFG_INT_ACK_CMD_MASK_INT); 5349 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 5350 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx); 5351 5352 /* Handle any frames that arrived while handling the interrupt. */ 5353 if (ifp->if_drv_flags & IFF_DRV_RUNNING && !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 5354 bce_start_locked(ifp); 5355 5356bce_intr_exit: 5357 BCE_UNLOCK(sc); 5358} 5359 5360 5361/****************************************************************************/ 5362/* Programs the various packet receive modes (broadcast and multicast). */ 5363/* */ 5364/* Returns: */ 5365/* Nothing. */ 5366/****************************************************************************/ 5367static void 5368bce_set_rx_mode(struct bce_softc *sc) 5369{ 5370 struct ifnet *ifp; 5371 struct ifmultiaddr *ifma; 5372 u32 hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 5373 u32 rx_mode, sort_mode; 5374 int h, i; 5375 5376 BCE_LOCK_ASSERT(sc); 5377 5378 ifp = sc->bce_ifp; 5379 5380 /* Initialize receive mode default settings. */ 5381 rx_mode = sc->rx_mode & ~(BCE_EMAC_RX_MODE_PROMISCUOUS | 5382 BCE_EMAC_RX_MODE_KEEP_VLAN_TAG); 5383 sort_mode = 1 | BCE_RPM_SORT_USER0_BC_EN; 5384 5385 /* 5386 * ASF/IPMI/UMP firmware requires that VLAN tag stripping 5387 * be enbled. 5388 */ 5389 if (!(BCE_IF_CAPABILITIES & IFCAP_VLAN_HWTAGGING) && 5390 (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG))) 5391 rx_mode |= BCE_EMAC_RX_MODE_KEEP_VLAN_TAG; 5392 5393 /* 5394 * Check for promiscuous, all multicast, or selected 5395 * multicast address filtering. 5396 */ 5397 if (ifp->if_flags & IFF_PROMISC) { 5398 DBPRINT(sc, BCE_INFO, "Enabling promiscuous mode.\n"); 5399 5400 /* Enable promiscuous mode. */ 5401 rx_mode |= BCE_EMAC_RX_MODE_PROMISCUOUS; 5402 sort_mode |= BCE_RPM_SORT_USER0_PROM_EN; 5403 } else if (ifp->if_flags & IFF_ALLMULTI) { 5404 DBPRINT(sc, BCE_INFO, "Enabling all multicast mode.\n"); 5405 5406 /* Enable all multicast addresses. */ 5407 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) { 5408 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), 0xffffffff); 5409 } 5410 sort_mode |= BCE_RPM_SORT_USER0_MC_EN; 5411 } else { 5412 /* Accept one or more multicast(s). */ 5413 DBPRINT(sc, BCE_INFO, "Enabling selective multicast mode.\n"); 5414 5415 IF_ADDR_LOCK(ifp); 5416 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 5417 if (ifma->ifma_addr->sa_family != AF_LINK) 5418 continue; 5419 h = ether_crc32_le(LLADDR((struct sockaddr_dl *) 5420 ifma->ifma_addr), ETHER_ADDR_LEN) & 0xFF; 5421 hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F); 5422 } 5423 IF_ADDR_UNLOCK(ifp); 5424 5425 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) 5426 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), hashes[i]); 5427 5428 sort_mode |= BCE_RPM_SORT_USER0_MC_HSH_EN; 5429 } 5430 5431 /* Only make changes if the recive mode has actually changed. */ 5432 if (rx_mode != sc->rx_mode) { 5433 DBPRINT(sc, BCE_VERBOSE, "Enabling new receive mode: 0x%08X\n", 5434 rx_mode); 5435 5436 sc->rx_mode = rx_mode; 5437 REG_WR(sc, BCE_EMAC_RX_MODE, rx_mode); 5438 } 5439 5440 /* Disable and clear the exisitng sort before enabling a new sort. */ 5441 REG_WR(sc, BCE_RPM_SORT_USER0, 0x0); 5442 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode); 5443 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode | BCE_RPM_SORT_USER0_ENA); 5444} 5445 5446 5447/****************************************************************************/ 5448/* Called periodically to updates statistics from the controllers */ 5449/* statistics block. */ 5450/* */ 5451/* Returns: */ 5452/* Nothing. */ 5453/****************************************************************************/ 5454static void 5455bce_stats_update(struct bce_softc *sc) 5456{ 5457 struct ifnet *ifp; 5458 struct statistics_block *stats; 5459 5460 DBPRINT(sc, BCE_EXCESSIVE, "Entering %s()\n", __FUNCTION__); 5461 5462 ifp = sc->bce_ifp; 5463 5464 stats = (struct statistics_block *) sc->stats_block; 5465 5466 /* 5467 * Update the interface statistics from the 5468 * hardware statistics. 5469 */ 5470 ifp->if_collisions = (u_long) stats->stat_EtherStatsCollisions; 5471 5472 ifp->if_ierrors = (u_long) stats->stat_EtherStatsUndersizePkts + 5473 (u_long) stats->stat_EtherStatsOverrsizePkts + 5474 (u_long) stats->stat_IfInMBUFDiscards + 5475 (u_long) stats->stat_Dot3StatsAlignmentErrors + 5476 (u_long) stats->stat_Dot3StatsFCSErrors; 5477 5478 ifp->if_oerrors = (u_long) stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors + 5479 (u_long) stats->stat_Dot3StatsExcessiveCollisions + 5480 (u_long) stats->stat_Dot3StatsLateCollisions; 5481 5482 /* 5483 * Certain controllers don't report 5484 * carrier sense errors correctly. 5485 * See errata E11_5708CA0_1165. 5486 */ 5487 if (!(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) && 5488 !(BCE_CHIP_ID(sc) == BCE_CHIP_ID_5708_A0)) 5489 ifp->if_oerrors += (u_long) stats->stat_Dot3StatsCarrierSenseErrors; 5490 5491 /* 5492 * Update the sysctl statistics from the 5493 * hardware statistics. 5494 */ 5495 sc->stat_IfHCInOctets = 5496 ((u64) stats->stat_IfHCInOctets_hi << 32) + 5497 (u64) stats->stat_IfHCInOctets_lo; 5498 5499 sc->stat_IfHCInBadOctets = 5500 ((u64) stats->stat_IfHCInBadOctets_hi << 32) + 5501 (u64) stats->stat_IfHCInBadOctets_lo; 5502 5503 sc->stat_IfHCOutOctets = 5504 ((u64) stats->stat_IfHCOutOctets_hi << 32) + 5505 (u64) stats->stat_IfHCOutOctets_lo; 5506 5507 sc->stat_IfHCOutBadOctets = 5508 ((u64) stats->stat_IfHCOutBadOctets_hi << 32) + 5509 (u64) stats->stat_IfHCOutBadOctets_lo; 5510 5511 sc->stat_IfHCInUcastPkts = 5512 ((u64) stats->stat_IfHCInUcastPkts_hi << 32) + 5513 (u64) stats->stat_IfHCInUcastPkts_lo; 5514 5515 sc->stat_IfHCInMulticastPkts = 5516 ((u64) stats->stat_IfHCInMulticastPkts_hi << 32) + 5517 (u64) stats->stat_IfHCInMulticastPkts_lo; 5518 5519 sc->stat_IfHCInBroadcastPkts = 5520 ((u64) stats->stat_IfHCInBroadcastPkts_hi << 32) + 5521 (u64) stats->stat_IfHCInBroadcastPkts_lo; 5522 5523 sc->stat_IfHCOutUcastPkts = 5524 ((u64) stats->stat_IfHCOutUcastPkts_hi << 32) + 5525 (u64) stats->stat_IfHCOutUcastPkts_lo; 5526 5527 sc->stat_IfHCOutMulticastPkts = 5528 ((u64) stats->stat_IfHCOutMulticastPkts_hi << 32) + 5529 (u64) stats->stat_IfHCOutMulticastPkts_lo; 5530 5531 sc->stat_IfHCOutBroadcastPkts = 5532 ((u64) stats->stat_IfHCOutBroadcastPkts_hi << 32) + 5533 (u64) stats->stat_IfHCOutBroadcastPkts_lo; 5534 5535 sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors = 5536 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors; 5537 5538 sc->stat_Dot3StatsCarrierSenseErrors = 5539 stats->stat_Dot3StatsCarrierSenseErrors; 5540 5541 sc->stat_Dot3StatsFCSErrors = 5542 stats->stat_Dot3StatsFCSErrors; 5543 5544 sc->stat_Dot3StatsAlignmentErrors = 5545 stats->stat_Dot3StatsAlignmentErrors; 5546 5547 sc->stat_Dot3StatsSingleCollisionFrames = 5548 stats->stat_Dot3StatsSingleCollisionFrames; 5549 5550 sc->stat_Dot3StatsMultipleCollisionFrames = 5551 stats->stat_Dot3StatsMultipleCollisionFrames; 5552 5553 sc->stat_Dot3StatsDeferredTransmissions = 5554 stats->stat_Dot3StatsDeferredTransmissions; 5555 5556 sc->stat_Dot3StatsExcessiveCollisions = 5557 stats->stat_Dot3StatsExcessiveCollisions; 5558 5559 sc->stat_Dot3StatsLateCollisions = 5560 stats->stat_Dot3StatsLateCollisions; 5561 5562 sc->stat_EtherStatsCollisions = 5563 stats->stat_EtherStatsCollisions; 5564 5565 sc->stat_EtherStatsFragments = 5566 stats->stat_EtherStatsFragments; 5567 5568 sc->stat_EtherStatsJabbers = 5569 stats->stat_EtherStatsJabbers; 5570 5571 sc->stat_EtherStatsUndersizePkts = 5572 stats->stat_EtherStatsUndersizePkts; 5573 5574 sc->stat_EtherStatsOverrsizePkts = 5575 stats->stat_EtherStatsOverrsizePkts; 5576 5577 sc->stat_EtherStatsPktsRx64Octets = 5578 stats->stat_EtherStatsPktsRx64Octets; 5579 5580 sc->stat_EtherStatsPktsRx65Octetsto127Octets = 5581 stats->stat_EtherStatsPktsRx65Octetsto127Octets; 5582 5583 sc->stat_EtherStatsPktsRx128Octetsto255Octets = 5584 stats->stat_EtherStatsPktsRx128Octetsto255Octets; 5585 5586 sc->stat_EtherStatsPktsRx256Octetsto511Octets = 5587 stats->stat_EtherStatsPktsRx256Octetsto511Octets; 5588 5589 sc->stat_EtherStatsPktsRx512Octetsto1023Octets = 5590 stats->stat_EtherStatsPktsRx512Octetsto1023Octets; 5591 5592 sc->stat_EtherStatsPktsRx1024Octetsto1522Octets = 5593 stats->stat_EtherStatsPktsRx1024Octetsto1522Octets; 5594 5595 sc->stat_EtherStatsPktsRx1523Octetsto9022Octets = 5596 stats->stat_EtherStatsPktsRx1523Octetsto9022Octets; 5597 5598 sc->stat_EtherStatsPktsTx64Octets = 5599 stats->stat_EtherStatsPktsTx64Octets; 5600 5601 sc->stat_EtherStatsPktsTx65Octetsto127Octets = 5602 stats->stat_EtherStatsPktsTx65Octetsto127Octets; 5603 5604 sc->stat_EtherStatsPktsTx128Octetsto255Octets = 5605 stats->stat_EtherStatsPktsTx128Octetsto255Octets; 5606 5607 sc->stat_EtherStatsPktsTx256Octetsto511Octets = 5608 stats->stat_EtherStatsPktsTx256Octetsto511Octets; 5609 5610 sc->stat_EtherStatsPktsTx512Octetsto1023Octets = 5611 stats->stat_EtherStatsPktsTx512Octetsto1023Octets; 5612 5613 sc->stat_EtherStatsPktsTx1024Octetsto1522Octets = 5614 stats->stat_EtherStatsPktsTx1024Octetsto1522Octets; 5615 5616 sc->stat_EtherStatsPktsTx1523Octetsto9022Octets = 5617 stats->stat_EtherStatsPktsTx1523Octetsto9022Octets; 5618 5619 sc->stat_XonPauseFramesReceived = 5620 stats->stat_XonPauseFramesReceived; 5621 5622 sc->stat_XoffPauseFramesReceived = 5623 stats->stat_XoffPauseFramesReceived; 5624 5625 sc->stat_OutXonSent = 5626 stats->stat_OutXonSent; 5627 5628 sc->stat_OutXoffSent = 5629 stats->stat_OutXoffSent; 5630 5631 sc->stat_FlowControlDone = 5632 stats->stat_FlowControlDone; 5633 5634 sc->stat_MacControlFramesReceived = 5635 stats->stat_MacControlFramesReceived; 5636 5637 sc->stat_XoffStateEntered = 5638 stats->stat_XoffStateEntered; 5639 5640 sc->stat_IfInFramesL2FilterDiscards = 5641 stats->stat_IfInFramesL2FilterDiscards; 5642 5643 sc->stat_IfInRuleCheckerDiscards = 5644 stats->stat_IfInRuleCheckerDiscards; 5645 5646 sc->stat_IfInFTQDiscards = 5647 stats->stat_IfInFTQDiscards; 5648 5649 sc->stat_IfInMBUFDiscards = 5650 stats->stat_IfInMBUFDiscards; 5651 5652 sc->stat_IfInRuleCheckerP4Hit = 5653 stats->stat_IfInRuleCheckerP4Hit; 5654 5655 sc->stat_CatchupInRuleCheckerDiscards = 5656 stats->stat_CatchupInRuleCheckerDiscards; 5657 5658 sc->stat_CatchupInFTQDiscards = 5659 stats->stat_CatchupInFTQDiscards; 5660 5661 sc->stat_CatchupInMBUFDiscards = 5662 stats->stat_CatchupInMBUFDiscards; 5663 5664 sc->stat_CatchupInRuleCheckerP4Hit = 5665 stats->stat_CatchupInRuleCheckerP4Hit; 5666 5667 sc->com_no_buffers = REG_RD_IND(sc, 0x120084); 5668 5669 DBPRINT(sc, BCE_EXCESSIVE, "Exiting %s()\n", __FUNCTION__); 5670} 5671 5672 5673/****************************************************************************/ 5674/* Periodic function to perform maintenance tasks. */ 5675/* */ 5676/* Returns: */ 5677/* Nothing. */ 5678/****************************************************************************/ 5679static void 5680bce_tick(void *xsc) 5681{ 5682 struct bce_softc *sc = xsc; 5683 struct mii_data *mii; 5684 struct ifnet *ifp; 5685 u32 msg; 5686 5687 ifp = sc->bce_ifp; 5688 5689 BCE_LOCK_ASSERT(sc); 5690 5691 /* Tell the firmware that the driver is still running. */ 5692#ifdef BCE_DEBUG 5693 msg = (u32) BCE_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE; 5694#else 5695 msg = (u32) ++sc->bce_fw_drv_pulse_wr_seq; 5696#endif 5697 REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_PULSE_MB, msg); 5698 5699 /* Update the statistics from the hardware statistics block. */ 5700 bce_stats_update(sc); 5701 5702 /* Check that chip hasn't hung. */ 5703 bce_watchdog(sc); 5704 5705 /* Schedule the next tick. */ 5706 callout_reset( 5707 &sc->bce_stat_ch, /* callout */ 5708 hz, /* ticks */ 5709 bce_tick, /* function */ 5710 sc); /* function argument */ 5711 5712 /* If link is up already up then we're done. */ 5713 if (sc->bce_link) 5714 goto bce_tick_locked_exit; 5715 5716 mii = device_get_softc(sc->bce_miibus); 5717 mii_tick(mii); 5718 5719 /* Check if the link has come up. */ 5720 if (!sc->bce_link && mii->mii_media_status & IFM_ACTIVE && 5721 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 5722 sc->bce_link++; 5723 if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 5724 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) && 5725 bootverbose) 5726 BCE_PRINTF("Gigabit link up\n"); 5727 /* Now that link is up, handle any outstanding TX traffic. */ 5728 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 5729 bce_start_locked(ifp); 5730 } 5731 5732bce_tick_locked_exit: 5733 return; 5734} 5735 5736 5737#ifdef BCE_DEBUG 5738/****************************************************************************/ 5739/* Allows the driver state to be dumped through the sysctl interface. */ 5740/* */ 5741/* Returns: */ 5742/* 0 for success, positive value for failure. */ 5743/****************************************************************************/ 5744static int 5745bce_sysctl_driver_state(SYSCTL_HANDLER_ARGS) 5746{ 5747 int error; 5748 int result; 5749 struct bce_softc *sc; 5750 5751 result = -1; 5752 error = sysctl_handle_int(oidp, &result, 0, req); 5753 5754 if (error || !req->newptr) 5755 return (error); 5756 5757 if (result == 1) { 5758 sc = (struct bce_softc *)arg1; 5759 bce_dump_driver_state(sc); 5760 } 5761 5762 return error; 5763} 5764 5765 5766/****************************************************************************/ 5767/* Allows the hardware state to be dumped through the sysctl interface. */ 5768/* */ 5769/* Returns: */ 5770/* 0 for success, positive value for failure. */ 5771/****************************************************************************/ 5772static int 5773bce_sysctl_hw_state(SYSCTL_HANDLER_ARGS) 5774{ 5775 int error; 5776 int result; 5777 struct bce_softc *sc; 5778 5779 result = -1; 5780 error = sysctl_handle_int(oidp, &result, 0, req); 5781 5782 if (error || !req->newptr) 5783 return (error); 5784 5785 if (result == 1) { 5786 sc = (struct bce_softc *)arg1; 5787 bce_dump_hw_state(sc); 5788 } 5789 5790 return error; 5791} 5792 5793 5794/****************************************************************************/ 5795/* Provides a sysctl interface to allows dumping the RX chain. */ 5796/* */ 5797/* Returns: */ 5798/* 0 for success, positive value for failure. */ 5799/****************************************************************************/ 5800static int 5801bce_sysctl_dump_rx_chain(SYSCTL_HANDLER_ARGS) 5802{ 5803 int error; 5804 int result; 5805 struct bce_softc *sc; 5806 5807 result = -1; 5808 error = sysctl_handle_int(oidp, &result, 0, req); 5809 5810 if (error || !req->newptr) 5811 return (error); 5812 5813 if (result == 1) { 5814 sc = (struct bce_softc *)arg1; 5815 bce_dump_rx_chain(sc, 0, USABLE_RX_BD); 5816 } 5817 5818 return error; 5819} 5820 5821 5822/****************************************************************************/ 5823/* Provides a sysctl interface to allows dumping the TX chain. */ 5824/* */ 5825/* Returns: */ 5826/* 0 for success, positive value for failure. */ 5827/****************************************************************************/ 5828static int 5829bce_sysctl_dump_tx_chain(SYSCTL_HANDLER_ARGS) 5830{ 5831 int error; 5832 int result; 5833 struct bce_softc *sc; 5834 5835 result = -1; 5836 error = sysctl_handle_int(oidp, &result, 0, req); 5837 5838 if (error || !req->newptr) 5839 return (error); 5840 5841 if (result == 1) { 5842 sc = (struct bce_softc *)arg1; 5843 bce_dump_tx_chain(sc, 0, USABLE_TX_BD); 5844 } 5845 5846 return error; 5847} 5848 5849 5850/****************************************************************************/ 5851/* Provides a sysctl interface to allow reading arbitrary registers in the */ 5852/* device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 5853/* */ 5854/* Returns: */ 5855/* 0 for success, positive value for failure. */ 5856/****************************************************************************/ 5857static int 5858bce_sysctl_reg_read(SYSCTL_HANDLER_ARGS) 5859{ 5860 struct bce_softc *sc; 5861 int error; 5862 uint32_t val, result; 5863 5864 result = -1; 5865 error = sysctl_handle_int(oidp, &result, 0, req); 5866 if (error || (req->newptr == NULL)) 5867 return (error); 5868 5869 /* Make sure the register is accessible. */ 5870 if (result < 0x8000) { 5871 sc = (struct bce_softc *)arg1; 5872 val = REG_RD(sc, result); 5873 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val); 5874 } else if (result < 0x0280000) { 5875 sc = (struct bce_softc *)arg1; 5876 val = REG_RD_IND(sc, result); 5877 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val); 5878 } 5879 5880 return (error); 5881} 5882 5883 5884/****************************************************************************/ 5885/* Provides a sysctl interface to allow reading arbitrary PHY registers in */ 5886/* the device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 5887/* */ 5888/* Returns: */ 5889/* 0 for success, positive value for failure. */ 5890/****************************************************************************/ 5891static int 5892bce_sysctl_phy_read(SYSCTL_HANDLER_ARGS) 5893{ 5894 struct bce_softc *sc; 5895 device_t dev; 5896 int error, result; 5897 u16 val; 5898 5899 result = -1; 5900 error = sysctl_handle_int(oidp, &result, 0, req); 5901 if (error || (req->newptr == NULL)) 5902 return (error); 5903 5904 /* Make sure the register is accessible. */ 5905 if (result < 0x20) { 5906 sc = (struct bce_softc *)arg1; 5907 dev = sc->bce_dev; 5908 val = bce_miibus_read_reg(dev, sc->bce_phy_addr, result); 5909 BCE_PRINTF("phy 0x%02X = 0x%04X\n", result, val); 5910 } 5911 return (error); 5912} 5913 5914 5915/****************************************************************************/ 5916/* Provides a sysctl interface to forcing the driver to dump state and */ 5917/* enter the debugger. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 5918/* */ 5919/* Returns: */ 5920/* 0 for success, positive value for failure. */ 5921/****************************************************************************/ 5922static int 5923bce_sysctl_breakpoint(SYSCTL_HANDLER_ARGS) 5924{ 5925 int error; 5926 int result; 5927 struct bce_softc *sc; 5928 5929 result = -1; 5930 error = sysctl_handle_int(oidp, &result, 0, req); 5931 5932 if (error || !req->newptr) 5933 return (error); 5934 5935 if (result == 1) { 5936 sc = (struct bce_softc *)arg1; 5937 bce_breakpoint(sc); 5938 } 5939 5940 return error; 5941} 5942#endif 5943 5944 5945/****************************************************************************/ 5946/* Adds any sysctl parameters for tuning or debugging purposes. */ 5947/* */ 5948/* Returns: */ 5949/* 0 for success, positive value for failure. */ 5950/****************************************************************************/ 5951static void 5952bce_add_sysctls(struct bce_softc *sc) 5953{ 5954 struct sysctl_ctx_list *ctx; 5955 struct sysctl_oid_list *children; 5956 5957 ctx = device_get_sysctl_ctx(sc->bce_dev); 5958 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bce_dev)); 5959 5960#ifdef BCE_DEBUG 5961 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 5962 "rx_low_watermark", 5963 CTLFLAG_RD, &sc->rx_low_watermark, 5964 0, "Lowest level of free rx_bd's"); 5965 5966 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 5967 "rx_empty_count", 5968 CTLFLAG_RD, &sc->rx_empty_count, 5969 0, "Number of times the RX chain was empty"); 5970 5971 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 5972 "tx_hi_watermark", 5973 CTLFLAG_RD, &sc->tx_hi_watermark, 5974 0, "Highest level of used tx_bd's"); 5975 5976 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 5977 "tx_full_count", 5978 CTLFLAG_RD, &sc->tx_full_count, 5979 0, "Number of times the TX chain was full"); 5980 5981 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 5982 "l2fhdr_status_errors", 5983 CTLFLAG_RD, &sc->l2fhdr_status_errors, 5984 0, "l2_fhdr status errors"); 5985 5986 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 5987 "unexpected_attentions", 5988 CTLFLAG_RD, &sc->unexpected_attentions, 5989 0, "unexpected attentions"); 5990 5991 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 5992 "lost_status_block_updates", 5993 CTLFLAG_RD, &sc->lost_status_block_updates, 5994 0, "lost status block updates"); 5995 5996 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 5997 "mbuf_alloc_failed", 5998 CTLFLAG_RD, &sc->mbuf_alloc_failed, 5999 0, "mbuf cluster allocation failures"); 6000 6001 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 6002 "requested_tso_frames", 6003 CTLFLAG_RD, &sc->requested_tso_frames, 6004 0, "The number of TSO frames received"); 6005#endif 6006 6007 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 6008 "stat_IfHcInOctets", 6009 CTLFLAG_RD, &sc->stat_IfHCInOctets, 6010 "Bytes received"); 6011 6012 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 6013 "stat_IfHCInBadOctets", 6014 CTLFLAG_RD, &sc->stat_IfHCInBadOctets, 6015 "Bad bytes received"); 6016 6017 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 6018 "stat_IfHCOutOctets", 6019 CTLFLAG_RD, &sc->stat_IfHCOutOctets, 6020 "Bytes sent"); 6021 6022 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 6023 "stat_IfHCOutBadOctets", 6024 CTLFLAG_RD, &sc->stat_IfHCOutBadOctets, 6025 "Bad bytes sent"); 6026 6027 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 6028 "stat_IfHCInUcastPkts", 6029 CTLFLAG_RD, &sc->stat_IfHCInUcastPkts, 6030 "Unicast packets received"); 6031 6032 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 6033 "stat_IfHCInMulticastPkts", 6034 CTLFLAG_RD, &sc->stat_IfHCInMulticastPkts, 6035 "Multicast packets received"); 6036 6037 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 6038 "stat_IfHCInBroadcastPkts", 6039 CTLFLAG_RD, &sc->stat_IfHCInBroadcastPkts, 6040 "Broadcast packets received"); 6041 6042 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 6043 "stat_IfHCOutUcastPkts", 6044 CTLFLAG_RD, &sc->stat_IfHCOutUcastPkts, 6045 "Unicast packets sent"); 6046 6047 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 6048 "stat_IfHCOutMulticastPkts", 6049 CTLFLAG_RD, &sc->stat_IfHCOutMulticastPkts, 6050 "Multicast packets sent"); 6051 6052 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 6053 "stat_IfHCOutBroadcastPkts", 6054 CTLFLAG_RD, &sc->stat_IfHCOutBroadcastPkts, 6055 "Broadcast packets sent"); 6056 6057 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6058 "stat_emac_tx_stat_dot3statsinternalmactransmiterrors", 6059 CTLFLAG_RD, &sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors, 6060 0, "Internal MAC transmit errors"); 6061 6062 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6063 "stat_Dot3StatsCarrierSenseErrors", 6064 CTLFLAG_RD, &sc->stat_Dot3StatsCarrierSenseErrors, 6065 0, "Carrier sense errors"); 6066 6067 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6068 "stat_Dot3StatsFCSErrors", 6069 CTLFLAG_RD, &sc->stat_Dot3StatsFCSErrors, 6070 0, "Frame check sequence errors"); 6071 6072 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6073 "stat_Dot3StatsAlignmentErrors", 6074 CTLFLAG_RD, &sc->stat_Dot3StatsAlignmentErrors, 6075 0, "Alignment errors"); 6076 6077 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6078 "stat_Dot3StatsSingleCollisionFrames", 6079 CTLFLAG_RD, &sc->stat_Dot3StatsSingleCollisionFrames, 6080 0, "Single Collision Frames"); 6081 6082 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6083 "stat_Dot3StatsMultipleCollisionFrames", 6084 CTLFLAG_RD, &sc->stat_Dot3StatsMultipleCollisionFrames, 6085 0, "Multiple Collision Frames"); 6086 6087 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6088 "stat_Dot3StatsDeferredTransmissions", 6089 CTLFLAG_RD, &sc->stat_Dot3StatsDeferredTransmissions, 6090 0, "Deferred Transmissions"); 6091 6092 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6093 "stat_Dot3StatsExcessiveCollisions", 6094 CTLFLAG_RD, &sc->stat_Dot3StatsExcessiveCollisions, 6095 0, "Excessive Collisions"); 6096 6097 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6098 "stat_Dot3StatsLateCollisions", 6099 CTLFLAG_RD, &sc->stat_Dot3StatsLateCollisions, 6100 0, "Late Collisions"); 6101 6102 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6103 "stat_EtherStatsCollisions", 6104 CTLFLAG_RD, &sc->stat_EtherStatsCollisions, 6105 0, "Collisions"); 6106 6107 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6108 "stat_EtherStatsFragments", 6109 CTLFLAG_RD, &sc->stat_EtherStatsFragments, 6110 0, "Fragments"); 6111 6112 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6113 "stat_EtherStatsJabbers", 6114 CTLFLAG_RD, &sc->stat_EtherStatsJabbers, 6115 0, "Jabbers"); 6116 6117 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6118 "stat_EtherStatsUndersizePkts", 6119 CTLFLAG_RD, &sc->stat_EtherStatsUndersizePkts, 6120 0, "Undersize packets"); 6121 6122 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6123 "stat_EtherStatsOverrsizePkts", 6124 CTLFLAG_RD, &sc->stat_EtherStatsOverrsizePkts, 6125 0, "stat_EtherStatsOverrsizePkts"); 6126 6127 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6128 "stat_EtherStatsPktsRx64Octets", 6129 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx64Octets, 6130 0, "Bytes received in 64 byte packets"); 6131 6132 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6133 "stat_EtherStatsPktsRx65Octetsto127Octets", 6134 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx65Octetsto127Octets, 6135 0, "Bytes received in 65 to 127 byte packets"); 6136 6137 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6138 "stat_EtherStatsPktsRx128Octetsto255Octets", 6139 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx128Octetsto255Octets, 6140 0, "Bytes received in 128 to 255 byte packets"); 6141 6142 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6143 "stat_EtherStatsPktsRx256Octetsto511Octets", 6144 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx256Octetsto511Octets, 6145 0, "Bytes received in 256 to 511 byte packets"); 6146 6147 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6148 "stat_EtherStatsPktsRx512Octetsto1023Octets", 6149 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx512Octetsto1023Octets, 6150 0, "Bytes received in 512 to 1023 byte packets"); 6151 6152 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6153 "stat_EtherStatsPktsRx1024Octetsto1522Octets", 6154 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1024Octetsto1522Octets, 6155 0, "Bytes received in 1024 t0 1522 byte packets"); 6156 6157 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6158 "stat_EtherStatsPktsRx1523Octetsto9022Octets", 6159 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1523Octetsto9022Octets, 6160 0, "Bytes received in 1523 to 9022 byte packets"); 6161 6162 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6163 "stat_EtherStatsPktsTx64Octets", 6164 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx64Octets, 6165 0, "Bytes sent in 64 byte packets"); 6166 6167 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6168 "stat_EtherStatsPktsTx65Octetsto127Octets", 6169 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx65Octetsto127Octets, 6170 0, "Bytes sent in 65 to 127 byte packets"); 6171 6172 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6173 "stat_EtherStatsPktsTx128Octetsto255Octets", 6174 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx128Octetsto255Octets, 6175 0, "Bytes sent in 128 to 255 byte packets"); 6176 6177 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6178 "stat_EtherStatsPktsTx256Octetsto511Octets", 6179 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx256Octetsto511Octets, 6180 0, "Bytes sent in 256 to 511 byte packets"); 6181 6182 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6183 "stat_EtherStatsPktsTx512Octetsto1023Octets", 6184 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx512Octetsto1023Octets, 6185 0, "Bytes sent in 512 to 1023 byte packets"); 6186 6187 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6188 "stat_EtherStatsPktsTx1024Octetsto1522Octets", 6189 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1024Octetsto1522Octets, 6190 0, "Bytes sent in 1024 to 1522 byte packets"); 6191 6192 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6193 "stat_EtherStatsPktsTx1523Octetsto9022Octets", 6194 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1523Octetsto9022Octets, 6195 0, "Bytes sent in 1523 to 9022 byte packets"); 6196 6197 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6198 "stat_XonPauseFramesReceived", 6199 CTLFLAG_RD, &sc->stat_XonPauseFramesReceived, 6200 0, "XON pause frames receved"); 6201 6202 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6203 "stat_XoffPauseFramesReceived", 6204 CTLFLAG_RD, &sc->stat_XoffPauseFramesReceived, 6205 0, "XOFF pause frames received"); 6206 6207 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6208 "stat_OutXonSent", 6209 CTLFLAG_RD, &sc->stat_OutXonSent, 6210 0, "XON pause frames sent"); 6211 6212 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6213 "stat_OutXoffSent", 6214 CTLFLAG_RD, &sc->stat_OutXoffSent, 6215 0, "XOFF pause frames sent"); 6216 6217 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6218 "stat_FlowControlDone", 6219 CTLFLAG_RD, &sc->stat_FlowControlDone, 6220 0, "Flow control done"); 6221 6222 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6223 "stat_MacControlFramesReceived", 6224 CTLFLAG_RD, &sc->stat_MacControlFramesReceived, 6225 0, "MAC control frames received"); 6226 6227 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6228 "stat_XoffStateEntered", 6229 CTLFLAG_RD, &sc->stat_XoffStateEntered, 6230 0, "XOFF state entered"); 6231 6232 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6233 "stat_IfInFramesL2FilterDiscards", 6234 CTLFLAG_RD, &sc->stat_IfInFramesL2FilterDiscards, 6235 0, "Received L2 packets discarded"); 6236 6237 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6238 "stat_IfInRuleCheckerDiscards", 6239 CTLFLAG_RD, &sc->stat_IfInRuleCheckerDiscards, 6240 0, "Received packets discarded by rule"); 6241 6242 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6243 "stat_IfInFTQDiscards", 6244 CTLFLAG_RD, &sc->stat_IfInFTQDiscards, 6245 0, "Received packet FTQ discards"); 6246 6247 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6248 "stat_IfInMBUFDiscards", 6249 CTLFLAG_RD, &sc->stat_IfInMBUFDiscards, 6250 0, "Received packets discarded due to lack of controller buffer memory"); 6251 6252 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6253 "stat_IfInRuleCheckerP4Hit", 6254 CTLFLAG_RD, &sc->stat_IfInRuleCheckerP4Hit, 6255 0, "Received packets rule checker hits"); 6256 6257 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6258 "stat_CatchupInRuleCheckerDiscards", 6259 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerDiscards, 6260 0, "Received packets discarded in Catchup path"); 6261 6262 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6263 "stat_CatchupInFTQDiscards", 6264 CTLFLAG_RD, &sc->stat_CatchupInFTQDiscards, 6265 0, "Received packets discarded in FTQ in Catchup path"); 6266 6267 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6268 "stat_CatchupInMBUFDiscards", 6269 CTLFLAG_RD, &sc->stat_CatchupInMBUFDiscards, 6270 0, "Received packets discarded in controller buffer memory in Catchup path"); 6271 6272 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6273 "stat_CatchupInRuleCheckerP4Hit", 6274 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerP4Hit, 6275 0, "Received packets rule checker hits in Catchup path"); 6276 6277 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6278 "com_no_buffers", 6279 CTLFLAG_RD, &sc->com_no_buffers, 6280 0, "Valid packets received but no RX buffers available"); 6281 6282#ifdef BCE_DEBUG 6283 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 6284 "driver_state", CTLTYPE_INT | CTLFLAG_RW, 6285 (void *)sc, 0, 6286 bce_sysctl_driver_state, "I", "Drive state information"); 6287 6288 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 6289 "hw_state", CTLTYPE_INT | CTLFLAG_RW, 6290 (void *)sc, 0, 6291 bce_sysctl_hw_state, "I", "Hardware state information"); 6292 6293 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 6294 "dump_rx_chain", CTLTYPE_INT | CTLFLAG_RW, 6295 (void *)sc, 0, 6296 bce_sysctl_dump_rx_chain, "I", "Dump rx_bd chain"); 6297 6298 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 6299 "dump_tx_chain", CTLTYPE_INT | CTLFLAG_RW, 6300 (void *)sc, 0, 6301 bce_sysctl_dump_tx_chain, "I", "Dump tx_bd chain"); 6302 6303 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 6304 "breakpoint", CTLTYPE_INT | CTLFLAG_RW, 6305 (void *)sc, 0, 6306 bce_sysctl_breakpoint, "I", "Driver breakpoint"); 6307 6308 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 6309 "reg_read", CTLTYPE_INT | CTLFLAG_RW, 6310 (void *)sc, 0, 6311 bce_sysctl_reg_read, "I", "Register read"); 6312 6313 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 6314 "phy_read", CTLTYPE_INT | CTLFLAG_RW, 6315 (void *)sc, 0, 6316 bce_sysctl_phy_read, "I", "PHY register read"); 6317 6318#endif 6319 6320} 6321 6322 6323/****************************************************************************/ 6324/* BCE Debug Routines */ 6325/****************************************************************************/ 6326#ifdef BCE_DEBUG 6327 6328/****************************************************************************/ 6329/* Freezes the controller to allow for a cohesive state dump. */ 6330/* */ 6331/* Returns: */ 6332/* Nothing. */ 6333/****************************************************************************/ 6334static void 6335bce_freeze_controller(struct bce_softc *sc) 6336{ 6337 u32 val; 6338 val = REG_RD(sc, BCE_MISC_COMMAND); 6339 val |= BCE_MISC_COMMAND_DISABLE_ALL; 6340 REG_WR(sc, BCE_MISC_COMMAND, val); 6341 6342} 6343 6344 6345/****************************************************************************/ 6346/* Unfreezes the controller after a freeze operation. This may not always */ 6347/* work and the controller will require a reset! */ 6348/* */ 6349/* Returns: */ 6350/* Nothing. */ 6351/****************************************************************************/ 6352static void 6353bce_unfreeze_controller(struct bce_softc *sc) 6354{ 6355 u32 val; 6356 val = REG_RD(sc, BCE_MISC_COMMAND); 6357 val |= BCE_MISC_COMMAND_ENABLE_ALL; 6358 REG_WR(sc, BCE_MISC_COMMAND, val); 6359 6360} 6361 6362/****************************************************************************/ 6363/* Prints out information about an mbuf. */ 6364/* */ 6365/* Returns: */ 6366/* Nothing. */ 6367/****************************************************************************/ 6368static void 6369bce_dump_mbuf(struct bce_softc *sc, struct mbuf *m) 6370{ 6371 u32 val_hi, val_lo; 6372 struct mbuf *mp = m; 6373 6374 if (m == NULL) { 6375 BCE_PRINTF("mbuf: null pointer\n"); 6376 return; 6377 } 6378 6379 while (mp) { 6380 val_hi = BCE_ADDR_HI(mp); 6381 val_lo = BCE_ADDR_LO(mp); 6382 BCE_PRINTF("mbuf: vaddr = 0x%08X:%08X, m_len = %d, m_flags = ( ", 6383 val_hi, val_lo, mp->m_len); 6384 6385 if (mp->m_flags & M_EXT) 6386 printf("M_EXT "); 6387 if (mp->m_flags & M_PKTHDR) 6388 printf("M_PKTHDR "); 6389 if (mp->m_flags & M_EOR) 6390 printf("M_EOR "); 6391 if (mp->m_flags & M_RDONLY) 6392 printf("M_RDONLY "); 6393 6394 val_hi = BCE_ADDR_HI(mp->m_data); 6395 val_lo = BCE_ADDR_LO(mp->m_data); 6396 printf(") m_data = 0x%08X:%08X\n", 6397 val_hi, val_lo); 6398 6399 if (mp->m_flags & M_PKTHDR) { 6400 BCE_PRINTF("- m_pkthdr: flags = ( "); 6401 if (mp->m_flags & M_BCAST) 6402 printf("M_BCAST "); 6403 if (mp->m_flags & M_MCAST) 6404 printf("M_MCAST "); 6405 if (mp->m_flags & M_FRAG) 6406 printf("M_FRAG "); 6407 if (mp->m_flags & M_FIRSTFRAG) 6408 printf("M_FIRSTFRAG "); 6409 if (mp->m_flags & M_LASTFRAG) 6410 printf("M_LASTFRAG "); 6411 if (mp->m_flags & M_VLANTAG) 6412 printf("M_VLANTAG "); 6413 if (mp->m_flags & M_PROMISC) 6414 printf("M_PROMISC "); 6415 printf(") csum_flags = ( "); 6416 if (mp->m_pkthdr.csum_flags & CSUM_IP) 6417 printf("CSUM_IP "); 6418 if (mp->m_pkthdr.csum_flags & CSUM_TCP) 6419 printf("CSUM_TCP "); 6420 if (mp->m_pkthdr.csum_flags & CSUM_UDP) 6421 printf("CSUM_UDP "); 6422 if (mp->m_pkthdr.csum_flags & CSUM_IP_FRAGS) 6423 printf("CSUM_IP_FRAGS "); 6424 if (mp->m_pkthdr.csum_flags & CSUM_FRAGMENT) 6425 printf("CSUM_FRAGMENT "); 6426 if (mp->m_pkthdr.csum_flags & CSUM_TSO) 6427 printf("CSUM_TSO "); 6428 if (mp->m_pkthdr.csum_flags & CSUM_IP_CHECKED) 6429 printf("CSUM_IP_CHECKED "); 6430 if (mp->m_pkthdr.csum_flags & CSUM_IP_VALID) 6431 printf("CSUM_IP_VALID "); 6432 if (mp->m_pkthdr.csum_flags & CSUM_DATA_VALID) 6433 printf("CSUM_DATA_VALID "); 6434 printf(")\n"); 6435 } 6436 6437 if (mp->m_flags & M_EXT) { 6438 val_hi = BCE_ADDR_HI(mp->m_ext.ext_buf); 6439 val_lo = BCE_ADDR_LO(mp->m_ext.ext_buf); 6440 BCE_PRINTF("- m_ext: vaddr = 0x%08X:%08X, ext_size = %d, type = ", 6441 val_hi, val_lo, mp->m_ext.ext_size); 6442 switch (mp->m_ext.ext_type) { 6443 case EXT_CLUSTER: printf("EXT_CLUSTER\n"); break; 6444 case EXT_SFBUF: printf("EXT_SFBUF\n"); break; 6445 case EXT_JUMBO9: printf("EXT_JUMBO9\n"); break; 6446 case EXT_JUMBO16: printf("EXT_JUMBO16\n"); break; 6447 case EXT_PACKET: printf("EXT_PACKET\n"); break; 6448 case EXT_MBUF: printf("EXT_MBUF\n"); break; 6449 case EXT_NET_DRV: printf("EXT_NET_DRV\n"); break; 6450 case EXT_MOD_TYPE: printf("EXT_MDD_TYPE\n"); break; 6451 case EXT_DISPOSABLE: printf("EXT_DISPOSABLE\n"); break; 6452 case EXT_EXTREF: printf("EXT_EXTREF\n"); break; 6453 default: printf("UNKNOWN\n"); 6454 } 6455 } 6456 6457 mp = mp->m_next; 6458 } 6459} 6460 6461 6462/****************************************************************************/ 6463/* Prints out the mbufs in the TX mbuf chain. */ 6464/* */ 6465/* Returns: */ 6466/* Nothing. */ 6467/****************************************************************************/ 6468static void 6469bce_dump_tx_mbuf_chain(struct bce_softc *sc, int chain_prod, int count) 6470{ 6471 struct mbuf *m; 6472 6473 BCE_PRINTF( 6474 "----------------------------" 6475 " tx mbuf data " 6476 "----------------------------\n"); 6477 6478 for (int i = 0; i < count; i++) { 6479 m = sc->tx_mbuf_ptr[chain_prod]; 6480 BCE_PRINTF("txmbuf[%d]\n", chain_prod); 6481 bce_dump_mbuf(sc, m); 6482 chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod)); 6483 } 6484 6485 BCE_PRINTF( 6486 "----------------------------" 6487 "----------------" 6488 "----------------------------\n"); 6489} 6490 6491 6492/****************************************************************************/ 6493/* Prints out the mbufs in the RX mbuf chain. */ 6494/* */ 6495/* Returns: */ 6496/* Nothing. */ 6497/****************************************************************************/ 6498static void 6499bce_dump_rx_mbuf_chain(struct bce_softc *sc, int chain_prod, int count) 6500{ 6501 struct mbuf *m; 6502 6503 BCE_PRINTF( 6504 "----------------------------" 6505 " rx mbuf data " 6506 "----------------------------\n"); 6507 6508 for (int i = 0; i < count; i++) { 6509 m = sc->rx_mbuf_ptr[chain_prod]; 6510 BCE_PRINTF("rxmbuf[0x%04X]\n", chain_prod); 6511 bce_dump_mbuf(sc, m); 6512 chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod)); 6513 } 6514 6515 6516 BCE_PRINTF( 6517 "----------------------------" 6518 "----------------" 6519 "----------------------------\n"); 6520} 6521 6522 6523/****************************************************************************/ 6524/* Prints out a tx_bd structure. */ 6525/* */ 6526/* Returns: */ 6527/* Nothing. */ 6528/****************************************************************************/ 6529static void 6530bce_dump_txbd(struct bce_softc *sc, int idx, struct tx_bd *txbd) 6531{ 6532 if (idx > MAX_TX_BD) 6533 /* Index out of range. */ 6534 BCE_PRINTF("tx_bd[0x%04X]: Invalid tx_bd index!\n", idx); 6535 else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 6536 /* TX Chain page pointer. */ 6537 BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page pointer\n", 6538 idx, txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo); 6539 else { 6540 /* Normal tx_bd entry. */ 6541 BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = 0x%08X, " 6542 "vlan tag= 0x%04X, flags = 0x%04X (", idx, 6543 txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo, 6544 txbd->tx_bd_mss_nbytes, txbd->tx_bd_vlan_tag, 6545 txbd->tx_bd_flags); 6546 6547 if (txbd->tx_bd_flags & TX_BD_FLAGS_CONN_FAULT) 6548 printf(" CONN_FAULT"); 6549 6550 if (txbd->tx_bd_flags & TX_BD_FLAGS_TCP_UDP_CKSUM) 6551 printf(" TCP_UDP_CKSUM"); 6552 6553 if (txbd->tx_bd_flags & TX_BD_FLAGS_IP_CKSUM) 6554 printf(" IP_CKSUM"); 6555 6556 if (txbd->tx_bd_flags & TX_BD_FLAGS_VLAN_TAG) 6557 printf(" VLAN"); 6558 6559 if (txbd->tx_bd_flags & TX_BD_FLAGS_COAL_NOW) 6560 printf(" COAL_NOW"); 6561 6562 if (txbd->tx_bd_flags & TX_BD_FLAGS_DONT_GEN_CRC) 6563 printf(" DONT_GEN_CRC"); 6564 6565 if (txbd->tx_bd_flags & TX_BD_FLAGS_START) 6566 printf(" START"); 6567 6568 if (txbd->tx_bd_flags & TX_BD_FLAGS_END) 6569 printf(" END"); 6570 6571 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_LSO) 6572 printf(" LSO"); 6573 6574 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_OPTION_WORD) 6575 printf(" OPTION_WORD"); 6576 6577 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_FLAGS) 6578 printf(" FLAGS"); 6579 6580 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_SNAP) 6581 printf(" SNAP"); 6582 6583 printf(" )\n"); 6584 } 6585 6586} 6587 6588 6589/****************************************************************************/ 6590/* Prints out a rx_bd structure. */ 6591/* */ 6592/* Returns: */ 6593/* Nothing. */ 6594/****************************************************************************/ 6595static void 6596bce_dump_rxbd(struct bce_softc *sc, int idx, struct rx_bd *rxbd) 6597{ 6598 if (idx > MAX_RX_BD) 6599 /* Index out of range. */ 6600 BCE_PRINTF("rx_bd[0x%04X]: Invalid rx_bd index!\n", idx); 6601 else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 6602 /* TX Chain page pointer. */ 6603 BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page pointer\n", 6604 idx, rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo); 6605 else 6606 /* Normal tx_bd entry. */ 6607 BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = 0x%08X, " 6608 "flags = 0x%08X\n", idx, 6609 rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo, 6610 rxbd->rx_bd_len, rxbd->rx_bd_flags); 6611} 6612 6613 6614/****************************************************************************/ 6615/* Prints out a l2_fhdr structure. */ 6616/* */ 6617/* Returns: */ 6618/* Nothing. */ 6619/****************************************************************************/ 6620static void 6621bce_dump_l2fhdr(struct bce_softc *sc, int idx, struct l2_fhdr *l2fhdr) 6622{ 6623 6624 BCE_PRINTF("l2_fhdr[0x%04X]: status = 0x%08X, " 6625 "pkt_len = 0x%04X, vlan = 0x%04x, ip_xsum = 0x%04X, " 6626 "tcp_udp_xsum = 0x%04X\n", idx, 6627 l2fhdr->l2_fhdr_status, l2fhdr->l2_fhdr_pkt_len, 6628 l2fhdr->l2_fhdr_vlan_tag, l2fhdr->l2_fhdr_ip_xsum, 6629 l2fhdr->l2_fhdr_tcp_udp_xsum); 6630} 6631 6632 6633/****************************************************************************/ 6634/* Prints out the tx chain. */ 6635/* */ 6636/* Returns: */ 6637/* Nothing. */ 6638/****************************************************************************/ 6639static void 6640bce_dump_tx_chain(struct bce_softc *sc, int tx_prod, int count) 6641{ 6642 struct tx_bd *txbd; 6643 6644 /* First some info about the tx_bd chain structure. */ 6645 BCE_PRINTF( 6646 "----------------------------" 6647 " tx_bd chain " 6648 "----------------------------\n"); 6649 6650 BCE_PRINTF("page size = 0x%08X, tx chain pages = 0x%08X\n", 6651 (u32) BCM_PAGE_SIZE, (u32) TX_PAGES); 6652 6653 BCE_PRINTF("tx_bd per page = 0x%08X, usable tx_bd per page = 0x%08X\n", 6654 (u32) TOTAL_TX_BD_PER_PAGE, (u32) USABLE_TX_BD_PER_PAGE); 6655 6656 BCE_PRINTF("total tx_bd = 0x%08X\n", (u32) TOTAL_TX_BD); 6657 6658 BCE_PRINTF("" 6659 "----------------------------" 6660 " tx_bd data " 6661 "----------------------------\n"); 6662 6663 /* Now print out the tx_bd's themselves. */ 6664 for (int i = 0; i < count; i++) { 6665 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)]; 6666 bce_dump_txbd(sc, tx_prod, txbd); 6667 tx_prod = TX_CHAIN_IDX(NEXT_TX_BD(tx_prod)); 6668 } 6669 6670 BCE_PRINTF( 6671 "----------------------------" 6672 "----------------" 6673 "----------------------------\n"); 6674} 6675 6676 6677/****************************************************************************/ 6678/* Prints out the rx chain. */ 6679/* */ 6680/* Returns: */ 6681/* Nothing. */ 6682/****************************************************************************/ 6683static void 6684bce_dump_rx_chain(struct bce_softc *sc, int rx_prod, int count) 6685{ 6686 struct rx_bd *rxbd; 6687 6688 /* First some info about the tx_bd chain structure. */ 6689 BCE_PRINTF( 6690 "----------------------------" 6691 " rx_bd chain " 6692 "----------------------------\n"); 6693 6694 BCE_PRINTF("page size = 0x%08X, rx chain pages = 0x%08X\n", 6695 (u32) BCM_PAGE_SIZE, (u32) RX_PAGES); 6696 6697 BCE_PRINTF("rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n", 6698 (u32) TOTAL_RX_BD_PER_PAGE, (u32) USABLE_RX_BD_PER_PAGE); 6699 6700 BCE_PRINTF("total rx_bd = 0x%08X\n", (u32) TOTAL_RX_BD); 6701 6702 BCE_PRINTF( 6703 "----------------------------" 6704 " rx_bd data " 6705 "----------------------------\n"); 6706 6707 /* Now print out the rx_bd's themselves. */ 6708 for (int i = 0; i < count; i++) { 6709 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)]; 6710 bce_dump_rxbd(sc, rx_prod, rxbd); 6711 rx_prod = RX_CHAIN_IDX(NEXT_RX_BD(rx_prod)); 6712 } 6713 6714 BCE_PRINTF( 6715 "----------------------------" 6716 "----------------" 6717 "----------------------------\n"); 6718} 6719 6720 6721/****************************************************************************/ 6722/* Prints out the status block from host memory. */ 6723/* */ 6724/* Returns: */ 6725/* Nothing. */ 6726/****************************************************************************/ 6727static void 6728bce_dump_status_block(struct bce_softc *sc) 6729{ 6730 struct status_block *sblk; 6731 6732 sblk = sc->status_block; 6733 6734 BCE_PRINTF( 6735 "----------------------------" 6736 " Status Block " 6737 "----------------------------\n"); 6738 6739 BCE_PRINTF(" 0x%08X - attn_bits\n", 6740 sblk->status_attn_bits); 6741 6742 BCE_PRINTF(" 0x%08X - attn_bits_ack\n", 6743 sblk->status_attn_bits_ack); 6744 6745 BCE_PRINTF("0x%04X(0x%04X) - rx_cons0\n", 6746 sblk->status_rx_quick_consumer_index0, 6747 (u16) RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index0)); 6748 6749 BCE_PRINTF("0x%04X(0x%04X) - tx_cons0\n", 6750 sblk->status_tx_quick_consumer_index0, 6751 (u16) TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index0)); 6752 6753 BCE_PRINTF(" 0x%04X - status_idx\n", sblk->status_idx); 6754 6755 /* Theses indices are not used for normal L2 drivers. */ 6756 if (sblk->status_rx_quick_consumer_index1) 6757 BCE_PRINTF("0x%04X(0x%04X) - rx_cons1\n", 6758 sblk->status_rx_quick_consumer_index1, 6759 (u16) RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index1)); 6760 6761 if (sblk->status_tx_quick_consumer_index1) 6762 BCE_PRINTF("0x%04X(0x%04X) - tx_cons1\n", 6763 sblk->status_tx_quick_consumer_index1, 6764 (u16) TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index1)); 6765 6766 if (sblk->status_rx_quick_consumer_index2) 6767 BCE_PRINTF("0x%04X(0x%04X)- rx_cons2\n", 6768 sblk->status_rx_quick_consumer_index2, 6769 (u16) RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index2)); 6770 6771 if (sblk->status_tx_quick_consumer_index2) 6772 BCE_PRINTF("0x%04X(0x%04X) - tx_cons2\n", 6773 sblk->status_tx_quick_consumer_index2, 6774 (u16) TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index2)); 6775 6776 if (sblk->status_rx_quick_consumer_index3) 6777 BCE_PRINTF("0x%04X(0x%04X) - rx_cons3\n", 6778 sblk->status_rx_quick_consumer_index3, 6779 (u16) RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index3)); 6780 6781 if (sblk->status_tx_quick_consumer_index3) 6782 BCE_PRINTF("0x%04X(0x%04X) - tx_cons3\n", 6783 sblk->status_tx_quick_consumer_index3, 6784 (u16) TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index3)); 6785 6786 if (sblk->status_rx_quick_consumer_index4 || 6787 sblk->status_rx_quick_consumer_index5) 6788 BCE_PRINTF("rx_cons4 = 0x%08X, rx_cons5 = 0x%08X\n", 6789 sblk->status_rx_quick_consumer_index4, 6790 sblk->status_rx_quick_consumer_index5); 6791 6792 if (sblk->status_rx_quick_consumer_index6 || 6793 sblk->status_rx_quick_consumer_index7) 6794 BCE_PRINTF("rx_cons6 = 0x%08X, rx_cons7 = 0x%08X\n", 6795 sblk->status_rx_quick_consumer_index6, 6796 sblk->status_rx_quick_consumer_index7); 6797 6798 if (sblk->status_rx_quick_consumer_index8 || 6799 sblk->status_rx_quick_consumer_index9) 6800 BCE_PRINTF("rx_cons8 = 0x%08X, rx_cons9 = 0x%08X\n", 6801 sblk->status_rx_quick_consumer_index8, 6802 sblk->status_rx_quick_consumer_index9); 6803 6804 if (sblk->status_rx_quick_consumer_index10 || 6805 sblk->status_rx_quick_consumer_index11) 6806 BCE_PRINTF("rx_cons10 = 0x%08X, rx_cons11 = 0x%08X\n", 6807 sblk->status_rx_quick_consumer_index10, 6808 sblk->status_rx_quick_consumer_index11); 6809 6810 if (sblk->status_rx_quick_consumer_index12 || 6811 sblk->status_rx_quick_consumer_index13) 6812 BCE_PRINTF("rx_cons12 = 0x%08X, rx_cons13 = 0x%08X\n", 6813 sblk->status_rx_quick_consumer_index12, 6814 sblk->status_rx_quick_consumer_index13); 6815 6816 if (sblk->status_rx_quick_consumer_index14 || 6817 sblk->status_rx_quick_consumer_index15) 6818 BCE_PRINTF("rx_cons14 = 0x%08X, rx_cons15 = 0x%08X\n", 6819 sblk->status_rx_quick_consumer_index14, 6820 sblk->status_rx_quick_consumer_index15); 6821 6822 if (sblk->status_completion_producer_index || 6823 sblk->status_cmd_consumer_index) 6824 BCE_PRINTF("com_prod = 0x%08X, cmd_cons = 0x%08X\n", 6825 sblk->status_completion_producer_index, 6826 sblk->status_cmd_consumer_index); 6827 6828 BCE_PRINTF( 6829 "----------------------------" 6830 "----------------" 6831 "----------------------------\n"); 6832} 6833 6834 6835/****************************************************************************/ 6836/* Prints out the statistics block. */ 6837/* */ 6838/* Returns: */ 6839/* Nothing. */ 6840/****************************************************************************/ 6841static void 6842bce_dump_stats_block(struct bce_softc *sc) 6843{ 6844 struct statistics_block *sblk; 6845 6846 sblk = sc->stats_block; 6847 6848 BCE_PRINTF( 6849 "---------------" 6850 " Stats Block (All Stats Not Shown Are 0) " 6851 "---------------\n"); 6852 6853 if (sblk->stat_IfHCInOctets_hi 6854 || sblk->stat_IfHCInOctets_lo) 6855 BCE_PRINTF("0x%08X:%08X : " 6856 "IfHcInOctets\n", 6857 sblk->stat_IfHCInOctets_hi, 6858 sblk->stat_IfHCInOctets_lo); 6859 6860 if (sblk->stat_IfHCInBadOctets_hi 6861 || sblk->stat_IfHCInBadOctets_lo) 6862 BCE_PRINTF("0x%08X:%08X : " 6863 "IfHcInBadOctets\n", 6864 sblk->stat_IfHCInBadOctets_hi, 6865 sblk->stat_IfHCInBadOctets_lo); 6866 6867 if (sblk->stat_IfHCOutOctets_hi 6868 || sblk->stat_IfHCOutOctets_lo) 6869 BCE_PRINTF("0x%08X:%08X : " 6870 "IfHcOutOctets\n", 6871 sblk->stat_IfHCOutOctets_hi, 6872 sblk->stat_IfHCOutOctets_lo); 6873 6874 if (sblk->stat_IfHCOutBadOctets_hi 6875 || sblk->stat_IfHCOutBadOctets_lo) 6876 BCE_PRINTF("0x%08X:%08X : " 6877 "IfHcOutBadOctets\n", 6878 sblk->stat_IfHCOutBadOctets_hi, 6879 sblk->stat_IfHCOutBadOctets_lo); 6880 6881 if (sblk->stat_IfHCInUcastPkts_hi 6882 || sblk->stat_IfHCInUcastPkts_lo) 6883 BCE_PRINTF("0x%08X:%08X : " 6884 "IfHcInUcastPkts\n", 6885 sblk->stat_IfHCInUcastPkts_hi, 6886 sblk->stat_IfHCInUcastPkts_lo); 6887 6888 if (sblk->stat_IfHCInBroadcastPkts_hi 6889 || sblk->stat_IfHCInBroadcastPkts_lo) 6890 BCE_PRINTF("0x%08X:%08X : " 6891 "IfHcInBroadcastPkts\n", 6892 sblk->stat_IfHCInBroadcastPkts_hi, 6893 sblk->stat_IfHCInBroadcastPkts_lo); 6894 6895 if (sblk->stat_IfHCInMulticastPkts_hi 6896 || sblk->stat_IfHCInMulticastPkts_lo) 6897 BCE_PRINTF("0x%08X:%08X : " 6898 "IfHcInMulticastPkts\n", 6899 sblk->stat_IfHCInMulticastPkts_hi, 6900 sblk->stat_IfHCInMulticastPkts_lo); 6901 6902 if (sblk->stat_IfHCOutUcastPkts_hi 6903 || sblk->stat_IfHCOutUcastPkts_lo) 6904 BCE_PRINTF("0x%08X:%08X : " 6905 "IfHcOutUcastPkts\n", 6906 sblk->stat_IfHCOutUcastPkts_hi, 6907 sblk->stat_IfHCOutUcastPkts_lo); 6908 6909 if (sblk->stat_IfHCOutBroadcastPkts_hi 6910 || sblk->stat_IfHCOutBroadcastPkts_lo) 6911 BCE_PRINTF("0x%08X:%08X : " 6912 "IfHcOutBroadcastPkts\n", 6913 sblk->stat_IfHCOutBroadcastPkts_hi, 6914 sblk->stat_IfHCOutBroadcastPkts_lo); 6915 6916 if (sblk->stat_IfHCOutMulticastPkts_hi 6917 || sblk->stat_IfHCOutMulticastPkts_lo) 6918 BCE_PRINTF("0x%08X:%08X : " 6919 "IfHcOutMulticastPkts\n", 6920 sblk->stat_IfHCOutMulticastPkts_hi, 6921 sblk->stat_IfHCOutMulticastPkts_lo); 6922 6923 if (sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors) 6924 BCE_PRINTF(" 0x%08X : " 6925 "emac_tx_stat_dot3statsinternalmactransmiterrors\n", 6926 sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors); 6927 6928 if (sblk->stat_Dot3StatsCarrierSenseErrors) 6929 BCE_PRINTF(" 0x%08X : Dot3StatsCarrierSenseErrors\n", 6930 sblk->stat_Dot3StatsCarrierSenseErrors); 6931 6932 if (sblk->stat_Dot3StatsFCSErrors) 6933 BCE_PRINTF(" 0x%08X : Dot3StatsFCSErrors\n", 6934 sblk->stat_Dot3StatsFCSErrors); 6935 6936 if (sblk->stat_Dot3StatsAlignmentErrors) 6937 BCE_PRINTF(" 0x%08X : Dot3StatsAlignmentErrors\n", 6938 sblk->stat_Dot3StatsAlignmentErrors); 6939 6940 if (sblk->stat_Dot3StatsSingleCollisionFrames) 6941 BCE_PRINTF(" 0x%08X : Dot3StatsSingleCollisionFrames\n", 6942 sblk->stat_Dot3StatsSingleCollisionFrames); 6943 6944 if (sblk->stat_Dot3StatsMultipleCollisionFrames) 6945 BCE_PRINTF(" 0x%08X : Dot3StatsMultipleCollisionFrames\n", 6946 sblk->stat_Dot3StatsMultipleCollisionFrames); 6947 6948 if (sblk->stat_Dot3StatsDeferredTransmissions) 6949 BCE_PRINTF(" 0x%08X : Dot3StatsDeferredTransmissions\n", 6950 sblk->stat_Dot3StatsDeferredTransmissions); 6951 6952 if (sblk->stat_Dot3StatsExcessiveCollisions) 6953 BCE_PRINTF(" 0x%08X : Dot3StatsExcessiveCollisions\n", 6954 sblk->stat_Dot3StatsExcessiveCollisions); 6955 6956 if (sblk->stat_Dot3StatsLateCollisions) 6957 BCE_PRINTF(" 0x%08X : Dot3StatsLateCollisions\n", 6958 sblk->stat_Dot3StatsLateCollisions); 6959 6960 if (sblk->stat_EtherStatsCollisions) 6961 BCE_PRINTF(" 0x%08X : EtherStatsCollisions\n", 6962 sblk->stat_EtherStatsCollisions); 6963 6964 if (sblk->stat_EtherStatsFragments) 6965 BCE_PRINTF(" 0x%08X : EtherStatsFragments\n", 6966 sblk->stat_EtherStatsFragments); 6967 6968 if (sblk->stat_EtherStatsJabbers) 6969 BCE_PRINTF(" 0x%08X : EtherStatsJabbers\n", 6970 sblk->stat_EtherStatsJabbers); 6971 6972 if (sblk->stat_EtherStatsUndersizePkts) 6973 BCE_PRINTF(" 0x%08X : EtherStatsUndersizePkts\n", 6974 sblk->stat_EtherStatsUndersizePkts); 6975 6976 if (sblk->stat_EtherStatsOverrsizePkts) 6977 BCE_PRINTF(" 0x%08X : EtherStatsOverrsizePkts\n", 6978 sblk->stat_EtherStatsOverrsizePkts); 6979 6980 if (sblk->stat_EtherStatsPktsRx64Octets) 6981 BCE_PRINTF(" 0x%08X : EtherStatsPktsRx64Octets\n", 6982 sblk->stat_EtherStatsPktsRx64Octets); 6983 6984 if (sblk->stat_EtherStatsPktsRx65Octetsto127Octets) 6985 BCE_PRINTF(" 0x%08X : EtherStatsPktsRx65Octetsto127Octets\n", 6986 sblk->stat_EtherStatsPktsRx65Octetsto127Octets); 6987 6988 if (sblk->stat_EtherStatsPktsRx128Octetsto255Octets) 6989 BCE_PRINTF(" 0x%08X : EtherStatsPktsRx128Octetsto255Octets\n", 6990 sblk->stat_EtherStatsPktsRx128Octetsto255Octets); 6991 6992 if (sblk->stat_EtherStatsPktsRx256Octetsto511Octets) 6993 BCE_PRINTF(" 0x%08X : EtherStatsPktsRx256Octetsto511Octets\n", 6994 sblk->stat_EtherStatsPktsRx256Octetsto511Octets); 6995 6996 if (sblk->stat_EtherStatsPktsRx512Octetsto1023Octets) 6997 BCE_PRINTF(" 0x%08X : EtherStatsPktsRx512Octetsto1023Octets\n", 6998 sblk->stat_EtherStatsPktsRx512Octetsto1023Octets); 6999 7000 if (sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets) 7001 BCE_PRINTF(" 0x%08X : EtherStatsPktsRx1024Octetsto1522Octets\n", 7002 sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets); 7003 7004 if (sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets) 7005 BCE_PRINTF(" 0x%08X : EtherStatsPktsRx1523Octetsto9022Octets\n", 7006 sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets); 7007 7008 if (sblk->stat_EtherStatsPktsTx64Octets) 7009 BCE_PRINTF(" 0x%08X : EtherStatsPktsTx64Octets\n", 7010 sblk->stat_EtherStatsPktsTx64Octets); 7011 7012 if (sblk->stat_EtherStatsPktsTx65Octetsto127Octets) 7013 BCE_PRINTF(" 0x%08X : EtherStatsPktsTx65Octetsto127Octets\n", 7014 sblk->stat_EtherStatsPktsTx65Octetsto127Octets); 7015 7016 if (sblk->stat_EtherStatsPktsTx128Octetsto255Octets) 7017 BCE_PRINTF(" 0x%08X : EtherStatsPktsTx128Octetsto255Octets\n", 7018 sblk->stat_EtherStatsPktsTx128Octetsto255Octets); 7019 7020 if (sblk->stat_EtherStatsPktsTx256Octetsto511Octets) 7021 BCE_PRINTF(" 0x%08X : EtherStatsPktsTx256Octetsto511Octets\n", 7022 sblk->stat_EtherStatsPktsTx256Octetsto511Octets); 7023 7024 if (sblk->stat_EtherStatsPktsTx512Octetsto1023Octets) 7025 BCE_PRINTF(" 0x%08X : EtherStatsPktsTx512Octetsto1023Octets\n", 7026 sblk->stat_EtherStatsPktsTx512Octetsto1023Octets); 7027 7028 if (sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets) 7029 BCE_PRINTF(" 0x%08X : EtherStatsPktsTx1024Octetsto1522Octets\n", 7030 sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets); 7031 7032 if (sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets) 7033 BCE_PRINTF(" 0x%08X : EtherStatsPktsTx1523Octetsto9022Octets\n", 7034 sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets); 7035 7036 if (sblk->stat_XonPauseFramesReceived) 7037 BCE_PRINTF(" 0x%08X : XonPauseFramesReceived\n", 7038 sblk->stat_XonPauseFramesReceived); 7039 7040 if (sblk->stat_XoffPauseFramesReceived) 7041 BCE_PRINTF(" 0x%08X : XoffPauseFramesReceived\n", 7042 sblk->stat_XoffPauseFramesReceived); 7043 7044 if (sblk->stat_OutXonSent) 7045 BCE_PRINTF(" 0x%08X : OutXonSent\n", 7046 sblk->stat_OutXonSent); 7047 7048 if (sblk->stat_OutXoffSent) 7049 BCE_PRINTF(" 0x%08X : OutXoffSent\n", 7050 sblk->stat_OutXoffSent); 7051 7052 if (sblk->stat_FlowControlDone) 7053 BCE_PRINTF(" 0x%08X : FlowControlDone\n", 7054 sblk->stat_FlowControlDone); 7055 7056 if (sblk->stat_MacControlFramesReceived) 7057 BCE_PRINTF(" 0x%08X : MacControlFramesReceived\n", 7058 sblk->stat_MacControlFramesReceived); 7059 7060 if (sblk->stat_XoffStateEntered) 7061 BCE_PRINTF(" 0x%08X : XoffStateEntered\n", 7062 sblk->stat_XoffStateEntered); 7063 7064 if (sblk->stat_IfInFramesL2FilterDiscards) 7065 BCE_PRINTF(" 0x%08X : IfInFramesL2FilterDiscards\n", 7066 sblk->stat_IfInFramesL2FilterDiscards); 7067 7068 if (sblk->stat_IfInRuleCheckerDiscards) 7069 BCE_PRINTF(" 0x%08X : IfInRuleCheckerDiscards\n", 7070 sblk->stat_IfInRuleCheckerDiscards); 7071 7072 if (sblk->stat_IfInFTQDiscards) 7073 BCE_PRINTF(" 0x%08X : IfInFTQDiscards\n", 7074 sblk->stat_IfInFTQDiscards); 7075 7076 if (sblk->stat_IfInMBUFDiscards) 7077 BCE_PRINTF(" 0x%08X : IfInMBUFDiscards\n", 7078 sblk->stat_IfInMBUFDiscards); 7079 7080 if (sblk->stat_IfInRuleCheckerP4Hit) 7081 BCE_PRINTF(" 0x%08X : IfInRuleCheckerP4Hit\n", 7082 sblk->stat_IfInRuleCheckerP4Hit); 7083 7084 if (sblk->stat_CatchupInRuleCheckerDiscards) 7085 BCE_PRINTF(" 0x%08X : CatchupInRuleCheckerDiscards\n", 7086 sblk->stat_CatchupInRuleCheckerDiscards); 7087 7088 if (sblk->stat_CatchupInFTQDiscards) 7089 BCE_PRINTF(" 0x%08X : CatchupInFTQDiscards\n", 7090 sblk->stat_CatchupInFTQDiscards); 7091 7092 if (sblk->stat_CatchupInMBUFDiscards) 7093 BCE_PRINTF(" 0x%08X : CatchupInMBUFDiscards\n", 7094 sblk->stat_CatchupInMBUFDiscards); 7095 7096 if (sblk->stat_CatchupInRuleCheckerP4Hit) 7097 BCE_PRINTF(" 0x%08X : CatchupInRuleCheckerP4Hit\n", 7098 sblk->stat_CatchupInRuleCheckerP4Hit); 7099 7100 BCE_PRINTF( 7101 "----------------------------" 7102 "----------------" 7103 "----------------------------\n"); 7104} 7105 7106 7107/****************************************************************************/ 7108/* Prints out a summary of the driver state. */ 7109/* */ 7110/* Returns: */ 7111/* Nothing. */ 7112/****************************************************************************/ 7113static void 7114bce_dump_driver_state(struct bce_softc *sc) 7115{ 7116 u32 val_hi, val_lo; 7117 7118 BCE_PRINTF( 7119 "-----------------------------" 7120 " Driver State " 7121 "-----------------------------\n"); 7122 7123 val_hi = BCE_ADDR_HI(sc); 7124 val_lo = BCE_ADDR_LO(sc); 7125 BCE_PRINTF("0x%08X:%08X - (sc) driver softc structure virtual address\n", 7126 val_hi, val_lo); 7127 7128 val_hi = BCE_ADDR_HI(sc->bce_vhandle); 7129 val_lo = BCE_ADDR_LO(sc->bce_vhandle); 7130 BCE_PRINTF("0x%08X:%08X - (sc->bce_vhandle) PCI BAR virtual address\n", 7131 val_hi, val_lo); 7132 7133 val_hi = BCE_ADDR_HI(sc->status_block); 7134 val_lo = BCE_ADDR_LO(sc->status_block); 7135 BCE_PRINTF("0x%08X:%08X - (sc->status_block) status block virtual address\n", 7136 val_hi, val_lo); 7137 7138 val_hi = BCE_ADDR_HI(sc->stats_block); 7139 val_lo = BCE_ADDR_LO(sc->stats_block); 7140 BCE_PRINTF("0x%08X:%08X - (sc->stats_block) statistics block virtual address\n", 7141 val_hi, val_lo); 7142 7143 val_hi = BCE_ADDR_HI(sc->tx_bd_chain); 7144 val_lo = BCE_ADDR_LO(sc->tx_bd_chain); 7145 BCE_PRINTF( 7146 "0x%08X:%08X - (sc->tx_bd_chain) tx_bd chain virtual adddress\n", 7147 val_hi, val_lo); 7148 7149 val_hi = BCE_ADDR_HI(sc->rx_bd_chain); 7150 val_lo = BCE_ADDR_LO(sc->rx_bd_chain); 7151 BCE_PRINTF( 7152 "0x%08X:%08X - (sc->rx_bd_chain) rx_bd chain virtual address\n", 7153 val_hi, val_lo); 7154 7155 val_hi = BCE_ADDR_HI(sc->tx_mbuf_ptr); 7156 val_lo = BCE_ADDR_LO(sc->tx_mbuf_ptr); 7157 BCE_PRINTF( 7158 "0x%08X:%08X - (sc->tx_mbuf_ptr) tx mbuf chain virtual address\n", 7159 val_hi, val_lo); 7160 7161 val_hi = BCE_ADDR_HI(sc->rx_mbuf_ptr); 7162 val_lo = BCE_ADDR_LO(sc->rx_mbuf_ptr); 7163 BCE_PRINTF( 7164 "0x%08X:%08X - (sc->rx_mbuf_ptr) rx mbuf chain virtual address\n", 7165 val_hi, val_lo); 7166 7167 BCE_PRINTF(" 0x%08X - (sc->interrupts_generated) h/w intrs\n", 7168 sc->interrupts_generated); 7169 7170 BCE_PRINTF(" 0x%08X - (sc->rx_interrupts) rx interrupts handled\n", 7171 sc->rx_interrupts); 7172 7173 BCE_PRINTF(" 0x%08X - (sc->tx_interrupts) tx interrupts handled\n", 7174 sc->tx_interrupts); 7175 7176 BCE_PRINTF(" 0x%08X - (sc->last_status_idx) status block index\n", 7177 sc->last_status_idx); 7178 7179 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->tx_prod) tx producer index\n", 7180 sc->tx_prod, (u16) TX_CHAIN_IDX(sc->tx_prod)); 7181 7182 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->tx_cons) tx consumer index\n", 7183 sc->tx_cons, (u16) TX_CHAIN_IDX(sc->tx_cons)); 7184 7185 BCE_PRINTF(" 0x%08X - (sc->tx_prod_bseq) tx producer bseq index\n", 7186 sc->tx_prod_bseq); 7187 7188 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->rx_prod) rx producer index\n", 7189 sc->rx_prod, (u16) RX_CHAIN_IDX(sc->rx_prod)); 7190 7191 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->rx_cons) rx consumer index\n", 7192 sc->rx_cons, (u16) RX_CHAIN_IDX(sc->rx_cons)); 7193 7194 BCE_PRINTF(" 0x%08X - (sc->rx_prod_bseq) rx producer bseq index\n", 7195 sc->rx_prod_bseq); 7196 7197 BCE_PRINTF(" 0x%08X - (sc->rx_mbuf_alloc) rx mbufs allocated\n", 7198 sc->rx_mbuf_alloc); 7199 7200 BCE_PRINTF(" 0x%08X - (sc->free_rx_bd) free rx_bd's\n", 7201 sc->free_rx_bd); 7202 7203 BCE_PRINTF("0x%08X/%08X - (sc->rx_low_watermark) rx low watermark\n", 7204 sc->rx_low_watermark, sc->max_rx_bd); 7205 7206 BCE_PRINTF(" 0x%08X - (sc->txmbuf_alloc) tx mbufs allocated\n", 7207 sc->tx_mbuf_alloc); 7208 7209 BCE_PRINTF(" 0x%08X - (sc->rx_mbuf_alloc) rx mbufs allocated\n", 7210 sc->rx_mbuf_alloc); 7211 7212 BCE_PRINTF(" 0x%08X - (sc->used_tx_bd) used tx_bd's\n", 7213 sc->used_tx_bd); 7214 7215 BCE_PRINTF("0x%08X/%08X - (sc->tx_hi_watermark) tx hi watermark\n", 7216 sc->tx_hi_watermark, sc->max_tx_bd); 7217 7218 BCE_PRINTF(" 0x%08X - (sc->mbuf_alloc_failed) failed mbuf alloc\n", 7219 sc->mbuf_alloc_failed); 7220 7221 BCE_PRINTF( 7222 "----------------------------" 7223 "----------------" 7224 "----------------------------\n"); 7225} 7226 7227 7228/****************************************************************************/ 7229/* Prints out the hardware state through a summary of important registers, */ 7230/* followed by a complete register dump. */ 7231/* */ 7232/* Returns: */ 7233/* Nothing. */ 7234/****************************************************************************/ 7235static void 7236bce_dump_hw_state(struct bce_softc *sc) 7237{ 7238 u32 val1; 7239 7240 BCE_PRINTF( 7241 "----------------------------" 7242 " Hardware State " 7243 "----------------------------\n"); 7244 7245 BCE_PRINTF("0x%08X - bootcode version\n", sc->bce_fw_ver); 7246 7247 val1 = REG_RD(sc, BCE_MISC_ENABLE_STATUS_BITS); 7248 BCE_PRINTF("0x%08X - (0x%06X) misc_enable_status_bits\n", 7249 val1, BCE_MISC_ENABLE_STATUS_BITS); 7250 7251 val1 = REG_RD(sc, BCE_DMA_STATUS); 7252 BCE_PRINTF("0x%08X - (0x%06X) dma_status\n", val1, BCE_DMA_STATUS); 7253 7254 val1 = REG_RD(sc, BCE_CTX_STATUS); 7255 BCE_PRINTF("0x%08X - (0x%06X) ctx_status\n", val1, BCE_CTX_STATUS); 7256 7257 val1 = REG_RD(sc, BCE_EMAC_STATUS); 7258 BCE_PRINTF("0x%08X - (0x%06X) emac_status\n", val1, BCE_EMAC_STATUS); 7259 7260 val1 = REG_RD(sc, BCE_RPM_STATUS); 7261 BCE_PRINTF("0x%08X - (0x%06X) rpm_status\n", val1, BCE_RPM_STATUS); 7262 7263 val1 = REG_RD(sc, BCE_TBDR_STATUS); 7264 BCE_PRINTF("0x%08X - (0x%06X) tbdr_status\n", val1, BCE_TBDR_STATUS); 7265 7266 val1 = REG_RD(sc, BCE_TDMA_STATUS); 7267 BCE_PRINTF("0x%08X - (0x%06X) tdma_status\n", val1, BCE_TDMA_STATUS); 7268 7269 val1 = REG_RD(sc, BCE_HC_STATUS); 7270 BCE_PRINTF("0x%08X - (0x%06X) hc_status\n", val1, BCE_HC_STATUS); 7271 7272 val1 = REG_RD_IND(sc, BCE_TXP_CPU_STATE); 7273 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n", val1, BCE_TXP_CPU_STATE); 7274 7275 val1 = REG_RD_IND(sc, BCE_TPAT_CPU_STATE); 7276 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n", val1, BCE_TPAT_CPU_STATE); 7277 7278 val1 = REG_RD_IND(sc, BCE_RXP_CPU_STATE); 7279 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n", val1, BCE_RXP_CPU_STATE); 7280 7281 val1 = REG_RD_IND(sc, BCE_COM_CPU_STATE); 7282 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n", val1, BCE_COM_CPU_STATE); 7283 7284 val1 = REG_RD_IND(sc, BCE_MCP_CPU_STATE); 7285 BCE_PRINTF("0x%08X - (0x%06X) mcp_cpu_state\n", val1, BCE_MCP_CPU_STATE); 7286 7287 val1 = REG_RD_IND(sc, BCE_CP_CPU_STATE); 7288 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n", val1, BCE_CP_CPU_STATE); 7289 7290 BCE_PRINTF( 7291 "----------------------------" 7292 "----------------" 7293 "----------------------------\n"); 7294 7295 BCE_PRINTF( 7296 "----------------------------" 7297 " Register Dump " 7298 "----------------------------\n"); 7299 7300 for (int i = 0x400; i < 0x8000; i += 0x10) 7301 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 7302 i, REG_RD(sc, i), REG_RD(sc, i + 0x4), 7303 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC)); 7304 7305 BCE_PRINTF( 7306 "----------------------------" 7307 "----------------" 7308 "----------------------------\n"); 7309} 7310 7311 7312/****************************************************************************/ 7313/* Prints out the TXP state. */ 7314/* */ 7315/* Returns: */ 7316/* Nothing. */ 7317/****************************************************************************/ 7318static void 7319bce_dump_txp_state(struct bce_softc *sc) 7320{ 7321 u32 val1; 7322 7323 BCE_PRINTF( 7324 "----------------------------" 7325 " TXP State " 7326 "----------------------------\n"); 7327 7328 val1 = REG_RD_IND(sc, BCE_TXP_CPU_MODE); 7329 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_mode\n", val1, BCE_TXP_CPU_MODE); 7330 7331 val1 = REG_RD_IND(sc, BCE_TXP_CPU_STATE); 7332 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n", val1, BCE_TXP_CPU_STATE); 7333 7334 val1 = REG_RD_IND(sc, BCE_TXP_CPU_EVENT_MASK); 7335 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_event_mask\n", val1, BCE_TXP_CPU_EVENT_MASK); 7336 7337 BCE_PRINTF( 7338 "----------------------------" 7339 " Register Dump " 7340 "----------------------------\n"); 7341 7342 for (int i = BCE_TXP_CPU_MODE; i < 0x68000; i += 0x10) { 7343 /* Skip the big blank spaces */ 7344 if (i < 0x454000 && i > 0x5ffff) 7345 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 7346 i, REG_RD_IND(sc, i), REG_RD_IND(sc, i + 0x4), 7347 REG_RD_IND(sc, i + 0x8), REG_RD_IND(sc, i + 0xC)); 7348 } 7349 7350 BCE_PRINTF( 7351 "----------------------------" 7352 "----------------" 7353 "----------------------------\n"); 7354} 7355 7356 7357/****************************************************************************/ 7358/* Prints out the RXP state. */ 7359/* */ 7360/* Returns: */ 7361/* Nothing. */ 7362/****************************************************************************/ 7363static void 7364bce_dump_rxp_state(struct bce_softc *sc) 7365{ 7366 u32 val1; 7367 7368 BCE_PRINTF( 7369 "----------------------------" 7370 " RXP State " 7371 "----------------------------\n"); 7372 7373 val1 = REG_RD_IND(sc, BCE_RXP_CPU_MODE); 7374 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_mode\n", val1, BCE_RXP_CPU_MODE); 7375 7376 val1 = REG_RD_IND(sc, BCE_RXP_CPU_STATE); 7377 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n", val1, BCE_RXP_CPU_STATE); 7378 7379 val1 = REG_RD_IND(sc, BCE_RXP_CPU_EVENT_MASK); 7380 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_event_mask\n", val1, BCE_RXP_CPU_EVENT_MASK); 7381 7382 BCE_PRINTF( 7383 "----------------------------" 7384 " Register Dump " 7385 "----------------------------\n"); 7386 7387 for (int i = BCE_RXP_CPU_MODE; i < 0xe8fff; i += 0x10) { 7388 /* Skip the big blank sapces */ 7389 if (i < 0xc5400 && i > 0xdffff) 7390 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 7391 i, REG_RD_IND(sc, i), REG_RD_IND(sc, i + 0x4), 7392 REG_RD_IND(sc, i + 0x8), REG_RD_IND(sc, i + 0xC)); 7393 } 7394 7395 BCE_PRINTF( 7396 "----------------------------" 7397 "----------------" 7398 "----------------------------\n"); 7399} 7400 7401 7402/****************************************************************************/ 7403/* Prints out the TPAT state. */ 7404/* */ 7405/* Returns: */ 7406/* Nothing. */ 7407/****************************************************************************/ 7408static void 7409bce_dump_tpat_state(struct bce_softc *sc) 7410{ 7411 u32 val1; 7412 7413 BCE_PRINTF( 7414 "----------------------------" 7415 " TPAT State " 7416 "----------------------------\n"); 7417 7418 val1 = REG_RD_IND(sc, BCE_TPAT_CPU_MODE); 7419 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_mode\n", val1, BCE_TPAT_CPU_MODE); 7420 7421 val1 = REG_RD_IND(sc, BCE_TPAT_CPU_STATE); 7422 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n", val1, BCE_TPAT_CPU_STATE); 7423 7424 val1 = REG_RD_IND(sc, BCE_TPAT_CPU_EVENT_MASK); 7425 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_event_mask\n", val1, BCE_TPAT_CPU_EVENT_MASK); 7426 7427 BCE_PRINTF( 7428 "----------------------------" 7429 " Register Dump " 7430 "----------------------------\n"); 7431 7432 for (int i = BCE_TPAT_CPU_MODE; i < 0xa3fff; i += 0x10) { 7433 /* Skip the big blank spaces */ 7434 if (i < 0x854000 && i > 0x9ffff) 7435 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 7436 i, REG_RD_IND(sc, i), REG_RD_IND(sc, i + 0x4), 7437 REG_RD_IND(sc, i + 0x8), REG_RD_IND(sc, i + 0xC)); 7438 } 7439 7440 BCE_PRINTF( 7441 "----------------------------" 7442 "----------------" 7443 "----------------------------\n"); 7444} 7445 7446 7447/****************************************************************************/ 7448/* Prints out the driver state and then enters the debugger. */ 7449/* */ 7450/* Returns: */ 7451/* Nothing. */ 7452/****************************************************************************/ 7453static void 7454bce_breakpoint(struct bce_softc *sc) 7455{ 7456 7457 /* Unreachable code to shut the compiler up about unused functions. */ 7458 if (0) { 7459 bce_freeze_controller(sc); 7460 bce_unfreeze_controller(sc); 7461 bce_dump_txbd(sc, 0, NULL); 7462 bce_dump_rxbd(sc, 0, NULL); 7463 bce_dump_tx_mbuf_chain(sc, 0, USABLE_TX_BD); 7464 bce_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD); 7465 bce_dump_l2fhdr(sc, 0, NULL); 7466 bce_dump_tx_chain(sc, 0, USABLE_TX_BD); 7467 bce_dump_rx_chain(sc, 0, USABLE_RX_BD); 7468 bce_dump_status_block(sc); 7469 bce_dump_stats_block(sc); 7470 bce_dump_driver_state(sc); 7471 bce_dump_hw_state(sc); 7472 bce_dump_txp_state(sc); 7473 bce_dump_rxp_state(sc); 7474 bce_dump_tpat_state(sc); 7475 } 7476 7477/* bce_freeze_controller(sc); */ 7478 bce_dump_driver_state(sc); 7479 bce_dump_status_block(sc); 7480 bce_dump_tx_chain(sc, 0, TOTAL_TX_BD); 7481 bce_dump_hw_state(sc); 7482 bce_dump_txp_state(sc); 7483/* bce_unfreeze_controller(sc); */ 7484 7485 /* Call the debugger. */ 7486 breakpoint(); 7487 7488 return; 7489} 7490#endif 7491