if_bce.c revision 166153
1/*- 2 * Copyright (c) 2006 Broadcom Corporation 3 * David Christensen <davidch@broadcom.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. Neither the name of Broadcom Corporation nor the name of its contributors 15 * may be used to endorse or promote products derived from this software 16 * without specific prior written consent. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 28 * THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#include <sys/cdefs.h> 32__FBSDID("$FreeBSD: head/sys/dev/bce/if_bce.c 166153 2007-01-20 17:05:12Z scottl $"); 33 34/* 35 * The following controllers are supported by this driver: 36 * BCM5706C A2, A3 37 * BCM5708C B1 38 * 39 * The following controllers are not supported by this driver: 40 * (These are not "Production" versions of the controller.) 41 * 42 * BCM5706C A0, A1 43 * BCM5706S A0, A1, A2, A3 44 * BCM5708C A0, B0 45 * BCM5708S A0, B0, B1 46 */ 47 48#include "opt_bce.h" 49 50#include <dev/bce/if_bcereg.h> 51#include <dev/bce/if_bcefw.h> 52 53/****************************************************************************/ 54/* BCE Driver Version */ 55/****************************************************************************/ 56char bce_driver_version[] = "v0.9.6"; 57 58 59/****************************************************************************/ 60/* BCE Debug Options */ 61/****************************************************************************/ 62#ifdef BCE_DEBUG 63 u32 bce_debug = BCE_WARN; 64 65 /* 0 = Never */ 66 /* 1 = 1 in 2,147,483,648 */ 67 /* 256 = 1 in 8,388,608 */ 68 /* 2048 = 1 in 1,048,576 */ 69 /* 65536 = 1 in 32,768 */ 70 /* 1048576 = 1 in 2,048 */ 71 /* 268435456 = 1 in 8 */ 72 /* 536870912 = 1 in 4 */ 73 /* 1073741824 = 1 in 2 */ 74 75 /* Controls how often the l2_fhdr frame error check will fail. */ 76 int bce_debug_l2fhdr_status_check = 0; 77 78 /* Controls how often the unexpected attention check will fail. */ 79 int bce_debug_unexpected_attention = 0; 80 81 /* Controls how often to simulate an mbuf allocation failure. */ 82 int bce_debug_mbuf_allocation_failure = 0; 83 84 /* Controls how often to simulate a DMA mapping failure. */ 85 int bce_debug_dma_map_addr_failure = 0; 86 87 /* Controls how often to simulate a bootcode failure. */ 88 int bce_debug_bootcode_running_failure = 0; 89#endif 90 91 92/****************************************************************************/ 93/* PCI Device ID Table */ 94/* */ 95/* Used by bce_probe() to identify the devices supported by this driver. */ 96/****************************************************************************/ 97#define BCE_DEVDESC_MAX 64 98 99static struct bce_type bce_devs[] = { 100 /* BCM5706C Controllers and OEM boards. */ 101 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3101, 102 "HP NC370T Multifunction Gigabit Server Adapter" }, 103 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3106, 104 "HP NC370i Multifunction Gigabit Server Adapter" }, 105 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, PCI_ANY_ID, PCI_ANY_ID, 106 "Broadcom NetXtreme II BCM5706 1000Base-T" }, 107 108 /* BCM5706S controllers and OEM boards. */ 109 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, HP_VENDORID, 0x3102, 110 "HP NC370F Multifunction Gigabit Server Adapter" }, 111 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, PCI_ANY_ID, PCI_ANY_ID, 112 "Broadcom NetXtreme II BCM5706 1000Base-SX" }, 113 114 /* BCM5708C controllers and OEM boards. */ 115 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, PCI_ANY_ID, PCI_ANY_ID, 116 "Broadcom NetXtreme II BCM5708 1000Base-T" }, 117 118 /* BCM5708S controllers and OEM boards. */ 119 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, PCI_ANY_ID, PCI_ANY_ID, 120 "Broadcom NetXtreme II BCM5708S 1000Base-T" }, 121 { 0, 0, 0, 0, NULL } 122}; 123 124 125/****************************************************************************/ 126/* Supported Flash NVRAM device data. */ 127/****************************************************************************/ 128static struct flash_spec flash_table[] = 129{ 130 /* Slow EEPROM */ 131 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400, 132 1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 133 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 134 "EEPROM - slow"}, 135 /* Expansion entry 0001 */ 136 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406, 137 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 138 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 139 "Entry 0001"}, 140 /* Saifun SA25F010 (non-buffered flash) */ 141 /* strap, cfg1, & write1 need updates */ 142 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406, 143 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 144 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2, 145 "Non-buffered flash (128kB)"}, 146 /* Saifun SA25F020 (non-buffered flash) */ 147 /* strap, cfg1, & write1 need updates */ 148 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406, 149 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 150 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4, 151 "Non-buffered flash (256kB)"}, 152 /* Expansion entry 0100 */ 153 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406, 154 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 155 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 156 "Entry 0100"}, 157 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */ 158 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406, 159 0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 160 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2, 161 "Entry 0101: ST M45PE10 (128kB non-bufferred)"}, 162 /* Entry 0110: ST M45PE20 (non-buffered flash)*/ 163 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406, 164 0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 165 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4, 166 "Entry 0110: ST M45PE20 (256kB non-bufferred)"}, 167 /* Saifun SA25F005 (non-buffered flash) */ 168 /* strap, cfg1, & write1 need updates */ 169 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406, 170 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 171 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE, 172 "Non-buffered flash (64kB)"}, 173 /* Fast EEPROM */ 174 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400, 175 1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 176 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 177 "EEPROM - fast"}, 178 /* Expansion entry 1001 */ 179 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406, 180 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 181 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 182 "Entry 1001"}, 183 /* Expansion entry 1010 */ 184 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406, 185 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 186 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 187 "Entry 1010"}, 188 /* ATMEL AT45DB011B (buffered flash) */ 189 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400, 190 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 191 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE, 192 "Buffered flash (128kB)"}, 193 /* Expansion entry 1100 */ 194 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406, 195 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 196 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 197 "Entry 1100"}, 198 /* Expansion entry 1101 */ 199 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406, 200 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 201 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 202 "Entry 1101"}, 203 /* Ateml Expansion entry 1110 */ 204 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400, 205 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 206 BUFFERED_FLASH_BYTE_ADDR_MASK, 0, 207 "Entry 1110 (Atmel)"}, 208 /* ATMEL AT45DB021B (buffered flash) */ 209 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400, 210 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 211 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2, 212 "Buffered flash (256kB)"}, 213}; 214 215 216/****************************************************************************/ 217/* FreeBSD device entry points. */ 218/****************************************************************************/ 219static int bce_probe (device_t); 220static int bce_attach (device_t); 221static int bce_detach (device_t); 222static void bce_shutdown (device_t); 223 224 225/****************************************************************************/ 226/* BCE Debug Data Structure Dump Routines */ 227/****************************************************************************/ 228#ifdef BCE_DEBUG 229static void bce_dump_mbuf (struct bce_softc *, struct mbuf *); 230static void bce_dump_tx_mbuf_chain (struct bce_softc *, int, int); 231static void bce_dump_rx_mbuf_chain (struct bce_softc *, int, int); 232static void bce_dump_txbd (struct bce_softc *, int, struct tx_bd *); 233static void bce_dump_rxbd (struct bce_softc *, int, struct rx_bd *); 234static void bce_dump_l2fhdr (struct bce_softc *, int, struct l2_fhdr *); 235static void bce_dump_tx_chain (struct bce_softc *, int, int); 236static void bce_dump_rx_chain (struct bce_softc *, int, int); 237static void bce_dump_status_block (struct bce_softc *); 238static void bce_dump_stats_block (struct bce_softc *); 239static void bce_dump_driver_state (struct bce_softc *); 240static void bce_dump_hw_state (struct bce_softc *); 241static void bce_breakpoint (struct bce_softc *); 242#endif 243 244 245/****************************************************************************/ 246/* BCE Register/Memory Access Routines */ 247/****************************************************************************/ 248static u32 bce_reg_rd_ind (struct bce_softc *, u32); 249static void bce_reg_wr_ind (struct bce_softc *, u32, u32); 250static void bce_ctx_wr (struct bce_softc *, u32, u32, u32); 251static int bce_miibus_read_reg (device_t, int, int); 252static int bce_miibus_write_reg (device_t, int, int, int); 253static void bce_miibus_statchg (device_t); 254 255 256/****************************************************************************/ 257/* BCE NVRAM Access Routines */ 258/****************************************************************************/ 259static int bce_acquire_nvram_lock (struct bce_softc *); 260static int bce_release_nvram_lock (struct bce_softc *); 261static void bce_enable_nvram_access (struct bce_softc *); 262static void bce_disable_nvram_access(struct bce_softc *); 263static int bce_nvram_read_dword (struct bce_softc *, u32, u8 *, u32); 264static int bce_init_nvram (struct bce_softc *); 265static int bce_nvram_read (struct bce_softc *, u32, u8 *, int); 266static int bce_nvram_test (struct bce_softc *); 267#ifdef BCE_NVRAM_WRITE_SUPPORT 268static int bce_enable_nvram_write (struct bce_softc *); 269static void bce_disable_nvram_write (struct bce_softc *); 270static int bce_nvram_erase_page (struct bce_softc *, u32); 271static int bce_nvram_write_dword (struct bce_softc *, u32, u8 *, u32); 272static int bce_nvram_write (struct bce_softc *, u32, u8 *, int); 273#endif 274 275/****************************************************************************/ 276/* */ 277/****************************************************************************/ 278static void bce_dma_map_addr (void *, bus_dma_segment_t *, int, int); 279static int bce_dma_alloc (device_t); 280static void bce_dma_free (struct bce_softc *); 281static void bce_release_resources (struct bce_softc *); 282 283/****************************************************************************/ 284/* BCE Firmware Synchronization and Load */ 285/****************************************************************************/ 286static int bce_fw_sync (struct bce_softc *, u32); 287static void bce_load_rv2p_fw (struct bce_softc *, u32 *, u32, u32); 288static void bce_load_cpu_fw (struct bce_softc *, struct cpu_reg *, struct fw_info *); 289static void bce_init_cpus (struct bce_softc *); 290 291static void bce_stop (struct bce_softc *); 292static int bce_reset (struct bce_softc *, u32); 293static int bce_chipinit (struct bce_softc *); 294static int bce_blockinit (struct bce_softc *); 295static int bce_get_buf (struct bce_softc *, struct mbuf *, u16 *, u16 *, u32 *); 296 297static int bce_init_tx_chain (struct bce_softc *); 298static int bce_init_rx_chain (struct bce_softc *); 299static void bce_free_rx_chain (struct bce_softc *); 300static void bce_free_tx_chain (struct bce_softc *); 301 302static int bce_tx_encap (struct bce_softc *, struct mbuf **); 303static void bce_start_locked (struct ifnet *); 304static void bce_start (struct ifnet *); 305static int bce_ioctl (struct ifnet *, u_long, caddr_t); 306static void bce_watchdog (struct bce_softc *); 307static int bce_ifmedia_upd (struct ifnet *); 308static void bce_ifmedia_upd_locked (struct ifnet *); 309static void bce_ifmedia_sts (struct ifnet *, struct ifmediareq *); 310static void bce_init_locked (struct bce_softc *); 311static void bce_init (void *); 312static void bce_mgmt_init_locked(struct bce_softc *sc); 313 314static void bce_init_context (struct bce_softc *); 315static void bce_get_mac_addr (struct bce_softc *); 316static void bce_set_mac_addr (struct bce_softc *); 317static void bce_phy_intr (struct bce_softc *); 318static void bce_rx_intr (struct bce_softc *); 319static void bce_tx_intr (struct bce_softc *); 320static void bce_disable_intr (struct bce_softc *); 321static void bce_enable_intr (struct bce_softc *); 322 323#ifdef DEVICE_POLLING 324static void bce_poll_locked (struct ifnet *, enum poll_cmd, int); 325static void bce_poll (struct ifnet *, enum poll_cmd, int); 326#endif 327static void bce_intr (void *); 328static void bce_set_rx_mode (struct bce_softc *); 329static void bce_stats_update (struct bce_softc *); 330static void bce_tick (void *); 331static void bce_add_sysctls (struct bce_softc *); 332 333 334/****************************************************************************/ 335/* FreeBSD device dispatch table. */ 336/****************************************************************************/ 337static device_method_t bce_methods[] = { 338 /* Device interface */ 339 DEVMETHOD(device_probe, bce_probe), 340 DEVMETHOD(device_attach, bce_attach), 341 DEVMETHOD(device_detach, bce_detach), 342 DEVMETHOD(device_shutdown, bce_shutdown), 343 344 /* bus interface */ 345 DEVMETHOD(bus_print_child, bus_generic_print_child), 346 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 347 348 /* MII interface */ 349 DEVMETHOD(miibus_readreg, bce_miibus_read_reg), 350 DEVMETHOD(miibus_writereg, bce_miibus_write_reg), 351 DEVMETHOD(miibus_statchg, bce_miibus_statchg), 352 353 { 0, 0 } 354}; 355 356static driver_t bce_driver = { 357 "bce", 358 bce_methods, 359 sizeof(struct bce_softc) 360}; 361 362static devclass_t bce_devclass; 363 364MODULE_DEPEND(bce, pci, 1, 1, 1); 365MODULE_DEPEND(bce, ether, 1, 1, 1); 366MODULE_DEPEND(bce, miibus, 1, 1, 1); 367 368DRIVER_MODULE(bce, pci, bce_driver, bce_devclass, 0, 0); 369DRIVER_MODULE(miibus, bce, miibus_driver, miibus_devclass, 0, 0); 370 371 372/****************************************************************************/ 373/* Device probe function. */ 374/* */ 375/* Compares the device to the driver's list of supported devices and */ 376/* reports back to the OS whether this is the right driver for the device. */ 377/* */ 378/* Returns: */ 379/* BUS_PROBE_DEFAULT on success, positive value on failure. */ 380/****************************************************************************/ 381static int 382bce_probe(device_t dev) 383{ 384 struct bce_type *t; 385 struct bce_softc *sc; 386 char *descbuf; 387 u16 vid = 0, did = 0, svid = 0, sdid = 0; 388 389 t = bce_devs; 390 391 sc = device_get_softc(dev); 392 bzero(sc, sizeof(struct bce_softc)); 393 sc->bce_unit = device_get_unit(dev); 394 sc->bce_dev = dev; 395 396 /* Get the data for the device to be probed. */ 397 vid = pci_get_vendor(dev); 398 did = pci_get_device(dev); 399 svid = pci_get_subvendor(dev); 400 sdid = pci_get_subdevice(dev); 401 402 DBPRINT(sc, BCE_VERBOSE_LOAD, 403 "%s(); VID = 0x%04X, DID = 0x%04X, SVID = 0x%04X, " 404 "SDID = 0x%04X\n", __FUNCTION__, vid, did, svid, sdid); 405 406 /* Look through the list of known devices for a match. */ 407 while(t->bce_name != NULL) { 408 409 if ((vid == t->bce_vid) && (did == t->bce_did) && 410 ((svid == t->bce_svid) || (t->bce_svid == PCI_ANY_ID)) && 411 ((sdid == t->bce_sdid) || (t->bce_sdid == PCI_ANY_ID))) { 412 413 descbuf = malloc(BCE_DEVDESC_MAX, M_TEMP, M_NOWAIT); 414 415 if (descbuf == NULL) 416 return(ENOMEM); 417 418 /* Print out the device identity. */ 419 snprintf(descbuf, BCE_DEVDESC_MAX, "%s (%c%d), %s", 420 t->bce_name, 421 (((pci_read_config(dev, PCIR_REVID, 4) & 0xf0) >> 4) + 'A'), 422 (pci_read_config(dev, PCIR_REVID, 4) & 0xf), 423 bce_driver_version); 424 425 device_set_desc_copy(dev, descbuf); 426 free(descbuf, M_TEMP); 427 return(BUS_PROBE_DEFAULT); 428 } 429 t++; 430 } 431 432 DBPRINT(sc, BCE_VERBOSE_LOAD, "%s(%d): No IOCTL match found!\n", 433 __FILE__, __LINE__); 434 435 return(ENXIO); 436} 437 438 439/****************************************************************************/ 440/* Device attach function. */ 441/* */ 442/* Allocates device resources, performs secondary chip identification, */ 443/* resets and initializes the hardware, and initializes driver instance */ 444/* variables. */ 445/* */ 446/* Returns: */ 447/* 0 on success, positive value on failure. */ 448/****************************************************************************/ 449static int 450bce_attach(device_t dev) 451{ 452 struct bce_softc *sc; 453 struct ifnet *ifp; 454 u32 val; 455 int count, mbuf, rid, rc = 0; 456 457 sc = device_get_softc(dev); 458 sc->bce_dev = dev; 459 460 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 461 462 mbuf = device_get_unit(dev); 463 sc->bce_unit = mbuf; 464 465 pci_enable_busmaster(dev); 466 467 /* Allocate PCI memory resources. */ 468 rid = PCIR_BAR(0); 469 sc->bce_res = bus_alloc_resource_any( 470 dev, /* dev */ 471 SYS_RES_MEMORY, /* type */ 472 &rid, /* rid */ 473 RF_ACTIVE | PCI_RF_DENSE); /* flags */ 474 475 if (sc->bce_res == NULL) { 476 BCE_PRINTF(sc, "%s(%d): PCI memory allocation failed\n", 477 __FILE__, __LINE__); 478 rc = ENXIO; 479 goto bce_attach_fail; 480 } 481 482 /* Get various resource handles. */ 483 sc->bce_btag = rman_get_bustag(sc->bce_res); 484 sc->bce_bhandle = rman_get_bushandle(sc->bce_res); 485 sc->bce_vhandle = (vm_offset_t) rman_get_virtual(sc->bce_res); 486 487 /* Allocate PCI IRQ resources. */ 488 count = pci_msi_count(dev); 489 if (count == 1 && pci_alloc_msi(dev, &count) == 0) { 490 rid = 1; 491 sc->bce_flags |= BCE_USING_MSI_FLAG; 492 } else 493 rid = 0; 494 sc->bce_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 495 RF_SHAREABLE | RF_ACTIVE); 496 497 if (sc->bce_irq == NULL) { 498 BCE_PRINTF(sc, "%s(%d): PCI map interrupt failed\n", 499 __FILE__, __LINE__); 500 rc = ENXIO; 501 goto bce_attach_fail; 502 } 503 504 /* Initialize mutex for the current device instance. */ 505 BCE_LOCK_INIT(sc, device_get_nameunit(dev)); 506 507 /* 508 * Configure byte swap and enable indirect register access. 509 * Rely on CPU to do target byte swapping on big endian systems. 510 * Access to registers outside of PCI configurtion space are not 511 * valid until this is done. 512 */ 513 pci_write_config(dev, BCE_PCICFG_MISC_CONFIG, 514 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 515 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP, 4); 516 517 /* Save ASIC revsion info. */ 518 sc->bce_chipid = REG_RD(sc, BCE_MISC_ID); 519 520 /* Weed out any non-production controller revisions. */ 521 switch(BCE_CHIP_ID(sc)) { 522 case BCE_CHIP_ID_5706_A0: 523 case BCE_CHIP_ID_5706_A1: 524 case BCE_CHIP_ID_5708_A0: 525 case BCE_CHIP_ID_5708_B0: 526 BCE_PRINTF(sc, "%s(%d): Unsupported controller revision (%c%d)!\n", 527 __FILE__, __LINE__, 528 (((pci_read_config(dev, PCIR_REVID, 4) & 0xf0) >> 4) + 'A'), 529 (pci_read_config(dev, PCIR_REVID, 4) & 0xf)); 530 rc = ENODEV; 531 goto bce_attach_fail; 532 } 533 534 if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT) { 535 BCE_PRINTF(sc, "%s(%d): SerDes controllers are not supported!\n", 536 __FILE__, __LINE__); 537 rc = ENODEV; 538 goto bce_attach_fail; 539 } 540 541 /* 542 * The embedded PCIe to PCI-X bridge (EPB) 543 * in the 5708 cannot address memory above 544 * 40 bits (E7_5708CB1_23043 & E6_5708SB1_23043). 545 */ 546 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708) 547 sc->max_bus_addr = BCE_BUS_SPACE_MAXADDR; 548 else 549 sc->max_bus_addr = BUS_SPACE_MAXADDR; 550 551 /* 552 * Find the base address for shared memory access. 553 * Newer versions of bootcode use a signature and offset 554 * while older versions use a fixed address. 555 */ 556 val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE); 557 if ((val & BCE_SHM_HDR_SIGNATURE_SIG_MASK) == BCE_SHM_HDR_SIGNATURE_SIG) 558 sc->bce_shmem_base = REG_RD_IND(sc, BCE_SHM_HDR_ADDR_0); 559 else 560 sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE; 561 562 DBPRINT(sc, BCE_INFO, "bce_shmem_base = 0x%08X\n", sc->bce_shmem_base); 563 564 /* Set initial device and PHY flags */ 565 sc->bce_flags = 0; 566 sc->bce_phy_flags = 0; 567 568 /* Get PCI bus information (speed and type). */ 569 val = REG_RD(sc, BCE_PCICFG_MISC_STATUS); 570 if (val & BCE_PCICFG_MISC_STATUS_PCIX_DET) { 571 u32 clkreg; 572 573 sc->bce_flags |= BCE_PCIX_FLAG; 574 575 clkreg = REG_RD(sc, BCE_PCICFG_PCI_CLOCK_CONTROL_BITS); 576 577 clkreg &= BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET; 578 switch (clkreg) { 579 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ: 580 sc->bus_speed_mhz = 133; 581 break; 582 583 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ: 584 sc->bus_speed_mhz = 100; 585 break; 586 587 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ: 588 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ: 589 sc->bus_speed_mhz = 66; 590 break; 591 592 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ: 593 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ: 594 sc->bus_speed_mhz = 50; 595 break; 596 597 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW: 598 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ: 599 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ: 600 sc->bus_speed_mhz = 33; 601 break; 602 } 603 } else { 604 if (val & BCE_PCICFG_MISC_STATUS_M66EN) 605 sc->bus_speed_mhz = 66; 606 else 607 sc->bus_speed_mhz = 33; 608 } 609 610 if (val & BCE_PCICFG_MISC_STATUS_32BIT_DET) 611 sc->bce_flags |= BCE_PCI_32BIT_FLAG; 612 613 BCE_PRINTF(sc, "ASIC ID 0x%08X; Revision (%c%d); PCI%s %s %dMHz\n", 614 sc->bce_chipid, 615 ((BCE_CHIP_ID(sc) & 0xf000) >> 12) + 'A', 616 ((BCE_CHIP_ID(sc) & 0x0ff0) >> 4), 617 ((sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : ""), 618 ((sc->bce_flags & BCE_PCI_32BIT_FLAG) ? "32-bit" : "64-bit"), 619 sc->bus_speed_mhz); 620 621 /* Reset the controller. */ 622 if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) { 623 rc = ENXIO; 624 goto bce_attach_fail; 625 } 626 627 /* Initialize the controller. */ 628 if (bce_chipinit(sc)) { 629 BCE_PRINTF(sc, "%s(%d): Controller initialization failed!\n", 630 __FILE__, __LINE__); 631 rc = ENXIO; 632 goto bce_attach_fail; 633 } 634 635 /* Perform NVRAM test. */ 636 if (bce_nvram_test(sc)) { 637 BCE_PRINTF(sc, "%s(%d): NVRAM test failed!\n", 638 __FILE__, __LINE__); 639 rc = ENXIO; 640 goto bce_attach_fail; 641 } 642 643 /* Fetch the permanent Ethernet MAC address. */ 644 bce_get_mac_addr(sc); 645 646 /* 647 * Trip points control how many BDs 648 * should be ready before generating an 649 * interrupt while ticks control how long 650 * a BD can sit in the chain before 651 * generating an interrupt. Set the default 652 * values for the RX and TX rings. 653 */ 654 655#ifdef BCE_DRBUG 656 /* Force more frequent interrupts. */ 657 sc->bce_tx_quick_cons_trip_int = 1; 658 sc->bce_tx_quick_cons_trip = 1; 659 sc->bce_tx_ticks_int = 0; 660 sc->bce_tx_ticks = 0; 661 662 sc->bce_rx_quick_cons_trip_int = 1; 663 sc->bce_rx_quick_cons_trip = 1; 664 sc->bce_rx_ticks_int = 0; 665 sc->bce_rx_ticks = 0; 666#else 667 sc->bce_tx_quick_cons_trip_int = 20; 668 sc->bce_tx_quick_cons_trip = 20; 669 sc->bce_tx_ticks_int = 80; 670 sc->bce_tx_ticks = 80; 671 672 sc->bce_rx_quick_cons_trip_int = 6; 673 sc->bce_rx_quick_cons_trip = 6; 674 sc->bce_rx_ticks_int = 18; 675 sc->bce_rx_ticks = 18; 676#endif 677 678 /* Update statistics once every second. */ 679 sc->bce_stats_ticks = 1000000 & 0xffff00; 680 681 /* 682 * The copper based NetXtreme II controllers 683 * use an integrated PHY at address 1 while 684 * the SerDes controllers use a PHY at 685 * address 2. 686 */ 687 sc->bce_phy_addr = 1; 688 689 if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT) { 690 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 691 sc->bce_flags |= BCE_NO_WOL_FLAG; 692 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708) { 693 sc->bce_phy_addr = 2; 694 val = REG_RD_IND(sc, sc->bce_shmem_base + 695 BCE_SHARED_HW_CFG_CONFIG); 696 if (val & BCE_SHARED_HW_CFG_PHY_2_5G) 697 sc->bce_phy_flags |= BCE_PHY_2_5G_CAPABLE_FLAG; 698 } 699 } 700 701 /* Allocate DMA memory resources. */ 702 if (bce_dma_alloc(dev)) { 703 BCE_PRINTF(sc, "%s(%d): DMA resource allocation failed!\n", 704 __FILE__, __LINE__); 705 rc = ENXIO; 706 goto bce_attach_fail; 707 } 708 709 /* Allocate an ifnet structure. */ 710 ifp = sc->bce_ifp = if_alloc(IFT_ETHER); 711 if (ifp == NULL) { 712 BCE_PRINTF(sc, "%s(%d): Interface allocation failed!\n", 713 __FILE__, __LINE__); 714 rc = ENXIO; 715 goto bce_attach_fail; 716 } 717 718 /* Initialize the ifnet interface. */ 719 ifp->if_softc = sc; 720 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 721 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 722 ifp->if_ioctl = bce_ioctl; 723 ifp->if_start = bce_start; 724 ifp->if_init = bce_init; 725 ifp->if_mtu = ETHERMTU; 726 ifp->if_hwassist = BCE_IF_HWASSIST; 727 ifp->if_capabilities = BCE_IF_CAPABILITIES; 728 ifp->if_capenable = ifp->if_capabilities; 729 730 /* Assume a standard 1500 byte MTU size for mbuf allocations. */ 731 sc->mbuf_alloc_size = MCLBYTES; 732#ifdef DEVICE_POLLING 733 ifp->if_capabilities |= IFCAP_POLLING; 734#endif 735 736 ifp->if_snd.ifq_drv_maxlen = USABLE_TX_BD; 737 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) 738 ifp->if_baudrate = IF_Gbps(2.5); 739 else 740 ifp->if_baudrate = IF_Gbps(1); 741 742 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 743 IFQ_SET_READY(&ifp->if_snd); 744 745 if (sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) { 746 BCE_PRINTF(sc, "%s(%d): SerDes is not supported by this driver!\n", 747 __FILE__, __LINE__); 748 rc = ENODEV; 749 goto bce_attach_fail; 750 } else { 751 /* Look for our PHY. */ 752 if (mii_phy_probe(dev, &sc->bce_miibus, bce_ifmedia_upd, 753 bce_ifmedia_sts)) { 754 BCE_PRINTF(sc, "%s(%d): PHY probe failed!\n", 755 __FILE__, __LINE__); 756 rc = ENXIO; 757 goto bce_attach_fail; 758 } 759 } 760 761 /* Attach to the Ethernet interface list. */ 762 ether_ifattach(ifp, sc->eaddr); 763 764#if __FreeBSD_version < 500000 765 callout_init(&sc->bce_stat_ch); 766#else 767 callout_init_mtx(&sc->bce_stat_ch, &sc->bce_mtx, 0); 768#endif 769 770 /* Hookup IRQ last. */ 771 rc = bus_setup_intr(dev, sc->bce_irq, INTR_TYPE_NET | INTR_MPSAFE, 772 bce_intr, sc, &sc->bce_intrhand); 773 774 if (rc) { 775 BCE_PRINTF(sc, "%s(%d): Failed to setup IRQ!\n", 776 __FILE__, __LINE__); 777 bce_detach(dev); 778 goto bce_attach_exit; 779 } 780 781 /* Print some important debugging info. */ 782 DBRUN(BCE_INFO, bce_dump_driver_state(sc)); 783 784 /* Add the supported sysctls to the kernel. */ 785 bce_add_sysctls(sc); 786 787 /* Get the firmware running so IPMI still works */ 788 BCE_LOCK(sc); 789 bce_mgmt_init_locked(sc); 790 BCE_UNLOCK(sc); 791 792 goto bce_attach_exit; 793 794bce_attach_fail: 795 bce_release_resources(sc); 796 797bce_attach_exit: 798 799 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 800 801 return(rc); 802} 803 804 805/****************************************************************************/ 806/* Device detach function. */ 807/* */ 808/* Stops the controller, resets the controller, and releases resources. */ 809/* */ 810/* Returns: */ 811/* 0 on success, positive value on failure. */ 812/****************************************************************************/ 813static int 814bce_detach(device_t dev) 815{ 816 struct bce_softc *sc; 817 struct ifnet *ifp; 818 819 sc = device_get_softc(dev); 820 821 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 822 823 ifp = sc->bce_ifp; 824 825#ifdef DEVICE_POLLING 826 if (ifp->if_capenable & IFCAP_POLLING) 827 ether_poll_deregister(ifp); 828#endif 829 830 /* Stop and reset the controller. */ 831 BCE_LOCK(sc); 832 bce_stop(sc); 833 bce_reset(sc, BCE_DRV_MSG_CODE_RESET); 834 BCE_UNLOCK(sc); 835 836 ether_ifdetach(ifp); 837 838 /* If we have a child device on the MII bus remove it too. */ 839 if (sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) { 840 ifmedia_removeall(&sc->bce_ifmedia); 841 } else { 842 bus_generic_detach(dev); 843 device_delete_child(dev, sc->bce_miibus); 844 } 845 846 /* Release all remaining resources. */ 847 bce_release_resources(sc); 848 849 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 850 851 return(0); 852} 853 854 855/****************************************************************************/ 856/* Device shutdown function. */ 857/* */ 858/* Stops and resets the controller. */ 859/* */ 860/* Returns: */ 861/* Nothing */ 862/****************************************************************************/ 863static void 864bce_shutdown(device_t dev) 865{ 866 struct bce_softc *sc = device_get_softc(dev); 867 868 BCE_LOCK(sc); 869 bce_stop(sc); 870 bce_reset(sc, BCE_DRV_MSG_CODE_RESET); 871 BCE_UNLOCK(sc); 872} 873 874 875/****************************************************************************/ 876/* Indirect register read. */ 877/* */ 878/* Reads NetXtreme II registers using an index/data register pair in PCI */ 879/* configuration space. Using this mechanism avoids issues with posted */ 880/* reads but is much slower than memory-mapped I/O. */ 881/* */ 882/* Returns: */ 883/* The value of the register. */ 884/****************************************************************************/ 885static u32 886bce_reg_rd_ind(struct bce_softc *sc, u32 offset) 887{ 888 device_t dev; 889 dev = sc->bce_dev; 890 891 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4); 892#ifdef BCE_DEBUG 893 { 894 u32 val; 895 val = pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4); 896 DBPRINT(sc, BCE_EXCESSIVE, "%s(); offset = 0x%08X, val = 0x%08X\n", 897 __FUNCTION__, offset, val); 898 return val; 899 } 900#else 901 return pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4); 902#endif 903} 904 905 906/****************************************************************************/ 907/* Indirect register write. */ 908/* */ 909/* Writes NetXtreme II registers using an index/data register pair in PCI */ 910/* configuration space. Using this mechanism avoids issues with posted */ 911/* writes but is muchh slower than memory-mapped I/O. */ 912/* */ 913/* Returns: */ 914/* Nothing. */ 915/****************************************************************************/ 916static void 917bce_reg_wr_ind(struct bce_softc *sc, u32 offset, u32 val) 918{ 919 device_t dev; 920 dev = sc->bce_dev; 921 922 DBPRINT(sc, BCE_EXCESSIVE, "%s(); offset = 0x%08X, val = 0x%08X\n", 923 __FUNCTION__, offset, val); 924 925 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4); 926 pci_write_config(dev, BCE_PCICFG_REG_WINDOW, val, 4); 927} 928 929 930/****************************************************************************/ 931/* Context memory write. */ 932/* */ 933/* The NetXtreme II controller uses context memory to track connection */ 934/* information for L2 and higher network protocols. */ 935/* */ 936/* Returns: */ 937/* Nothing. */ 938/****************************************************************************/ 939static void 940bce_ctx_wr(struct bce_softc *sc, u32 cid_addr, u32 offset, u32 val) 941{ 942 943 DBPRINT(sc, BCE_EXCESSIVE, "%s(); cid_addr = 0x%08X, offset = 0x%08X, " 944 "val = 0x%08X\n", __FUNCTION__, cid_addr, offset, val); 945 946 offset += cid_addr; 947 REG_WR(sc, BCE_CTX_DATA_ADR, offset); 948 REG_WR(sc, BCE_CTX_DATA, val); 949} 950 951 952/****************************************************************************/ 953/* PHY register read. */ 954/* */ 955/* Implements register reads on the MII bus. */ 956/* */ 957/* Returns: */ 958/* The value of the register. */ 959/****************************************************************************/ 960static int 961bce_miibus_read_reg(device_t dev, int phy, int reg) 962{ 963 struct bce_softc *sc; 964 u32 val; 965 int i; 966 967 sc = device_get_softc(dev); 968 969 /* Make sure we are accessing the correct PHY address. */ 970 if (phy != sc->bce_phy_addr) { 971 DBPRINT(sc, BCE_VERBOSE, "Invalid PHY address %d for PHY read!\n", phy); 972 return(0); 973 } 974 975 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 976 val = REG_RD(sc, BCE_EMAC_MDIO_MODE); 977 val &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL; 978 979 REG_WR(sc, BCE_EMAC_MDIO_MODE, val); 980 REG_RD(sc, BCE_EMAC_MDIO_MODE); 981 982 DELAY(40); 983 } 984 985 val = BCE_MIPHY(phy) | BCE_MIREG(reg) | 986 BCE_EMAC_MDIO_COMM_COMMAND_READ | BCE_EMAC_MDIO_COMM_DISEXT | 987 BCE_EMAC_MDIO_COMM_START_BUSY; 988 REG_WR(sc, BCE_EMAC_MDIO_COMM, val); 989 990 for (i = 0; i < BCE_PHY_TIMEOUT; i++) { 991 DELAY(10); 992 993 val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 994 if (!(val & BCE_EMAC_MDIO_COMM_START_BUSY)) { 995 DELAY(5); 996 997 val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 998 val &= BCE_EMAC_MDIO_COMM_DATA; 999 1000 break; 1001 } 1002 } 1003 1004 if (val & BCE_EMAC_MDIO_COMM_START_BUSY) { 1005 BCE_PRINTF(sc, "%s(%d): Error: PHY read timeout! phy = %d, reg = 0x%04X\n", 1006 __FILE__, __LINE__, phy, reg); 1007 val = 0x0; 1008 } else { 1009 val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1010 } 1011 1012 DBPRINT(sc, BCE_EXCESSIVE, "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n", 1013 __FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff); 1014 1015 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1016 val = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1017 val |= BCE_EMAC_MDIO_MODE_AUTO_POLL; 1018 1019 REG_WR(sc, BCE_EMAC_MDIO_MODE, val); 1020 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1021 1022 DELAY(40); 1023 } 1024 1025 return (val & 0xffff); 1026 1027} 1028 1029 1030/****************************************************************************/ 1031/* PHY register write. */ 1032/* */ 1033/* Implements register writes on the MII bus. */ 1034/* */ 1035/* Returns: */ 1036/* The value of the register. */ 1037/****************************************************************************/ 1038static int 1039bce_miibus_write_reg(device_t dev, int phy, int reg, int val) 1040{ 1041 struct bce_softc *sc; 1042 u32 val1; 1043 int i; 1044 1045 sc = device_get_softc(dev); 1046 1047 /* Make sure we are accessing the correct PHY address. */ 1048 if (phy != sc->bce_phy_addr) { 1049 DBPRINT(sc, BCE_WARN, "Invalid PHY address %d for PHY write!\n", phy); 1050 return(0); 1051 } 1052 1053 DBPRINT(sc, BCE_EXCESSIVE, "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n", 1054 __FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff); 1055 1056 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1057 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1058 val1 &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL; 1059 1060 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1); 1061 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1062 1063 DELAY(40); 1064 } 1065 1066 val1 = BCE_MIPHY(phy) | BCE_MIREG(reg) | val | 1067 BCE_EMAC_MDIO_COMM_COMMAND_WRITE | 1068 BCE_EMAC_MDIO_COMM_START_BUSY | BCE_EMAC_MDIO_COMM_DISEXT; 1069 REG_WR(sc, BCE_EMAC_MDIO_COMM, val1); 1070 1071 for (i = 0; i < BCE_PHY_TIMEOUT; i++) { 1072 DELAY(10); 1073 1074 val1 = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1075 if (!(val1 & BCE_EMAC_MDIO_COMM_START_BUSY)) { 1076 DELAY(5); 1077 break; 1078 } 1079 } 1080 1081 if (val1 & BCE_EMAC_MDIO_COMM_START_BUSY) 1082 BCE_PRINTF(sc, "%s(%d): PHY write timeout!\n", 1083 __FILE__, __LINE__); 1084 1085 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1086 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1087 val1 |= BCE_EMAC_MDIO_MODE_AUTO_POLL; 1088 1089 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1); 1090 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1091 1092 DELAY(40); 1093 } 1094 1095 return 0; 1096} 1097 1098 1099/****************************************************************************/ 1100/* MII bus status change. */ 1101/* */ 1102/* Called by the MII bus driver when the PHY establishes link to set the */ 1103/* MAC interface registers. */ 1104/* */ 1105/* Returns: */ 1106/* Nothing. */ 1107/****************************************************************************/ 1108static void 1109bce_miibus_statchg(device_t dev) 1110{ 1111 struct bce_softc *sc; 1112 struct mii_data *mii; 1113 1114 sc = device_get_softc(dev); 1115 1116 mii = device_get_softc(sc->bce_miibus); 1117 1118 BCE_CLRBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT); 1119 1120 /* Set MII or GMII inerface based on the speed negotiated by the PHY. */ 1121 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 1122 DBPRINT(sc, BCE_INFO, "Setting GMII interface.\n"); 1123 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT_GMII); 1124 } else { 1125 DBPRINT(sc, BCE_INFO, "Setting MII interface.\n"); 1126 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT_MII); 1127 } 1128 1129 /* Set half or full duplex based on the duplicity negotiated by the PHY. */ 1130 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 1131 DBPRINT(sc, BCE_INFO, "Setting Full-Duplex interface.\n"); 1132 BCE_CLRBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_HALF_DUPLEX); 1133 } else { 1134 DBPRINT(sc, BCE_INFO, "Setting Half-Duplex interface.\n"); 1135 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_HALF_DUPLEX); 1136 } 1137} 1138 1139 1140/****************************************************************************/ 1141/* Acquire NVRAM lock. */ 1142/* */ 1143/* Before the NVRAM can be accessed the caller must acquire an NVRAM lock. */ 1144/* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 1145/* for use by the driver. */ 1146/* */ 1147/* Returns: */ 1148/* 0 on success, positive value on failure. */ 1149/****************************************************************************/ 1150static int 1151bce_acquire_nvram_lock(struct bce_softc *sc) 1152{ 1153 u32 val; 1154 int j; 1155 1156 DBPRINT(sc, BCE_VERBOSE, "Acquiring NVRAM lock.\n"); 1157 1158 /* Request access to the flash interface. */ 1159 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2); 1160 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1161 val = REG_RD(sc, BCE_NVM_SW_ARB); 1162 if (val & BCE_NVM_SW_ARB_ARB_ARB2) 1163 break; 1164 1165 DELAY(5); 1166 } 1167 1168 if (j >= NVRAM_TIMEOUT_COUNT) { 1169 DBPRINT(sc, BCE_WARN, "Timeout acquiring NVRAM lock!\n"); 1170 return EBUSY; 1171 } 1172 1173 return 0; 1174} 1175 1176 1177/****************************************************************************/ 1178/* Release NVRAM lock. */ 1179/* */ 1180/* When the caller is finished accessing NVRAM the lock must be released. */ 1181/* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 1182/* for use by the driver. */ 1183/* */ 1184/* Returns: */ 1185/* 0 on success, positive value on failure. */ 1186/****************************************************************************/ 1187static int 1188bce_release_nvram_lock(struct bce_softc *sc) 1189{ 1190 int j; 1191 u32 val; 1192 1193 DBPRINT(sc, BCE_VERBOSE, "Releasing NVRAM lock.\n"); 1194 1195 /* 1196 * Relinquish nvram interface. 1197 */ 1198 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2); 1199 1200 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1201 val = REG_RD(sc, BCE_NVM_SW_ARB); 1202 if (!(val & BCE_NVM_SW_ARB_ARB_ARB2)) 1203 break; 1204 1205 DELAY(5); 1206 } 1207 1208 if (j >= NVRAM_TIMEOUT_COUNT) { 1209 DBPRINT(sc, BCE_WARN, "Timeout reeasing NVRAM lock!\n"); 1210 return EBUSY; 1211 } 1212 1213 return 0; 1214} 1215 1216 1217#ifdef BCE_NVRAM_WRITE_SUPPORT 1218/****************************************************************************/ 1219/* Enable NVRAM write access. */ 1220/* */ 1221/* Before writing to NVRAM the caller must enable NVRAM writes. */ 1222/* */ 1223/* Returns: */ 1224/* 0 on success, positive value on failure. */ 1225/****************************************************************************/ 1226static int 1227bce_enable_nvram_write(struct bce_softc *sc) 1228{ 1229 u32 val; 1230 1231 DBPRINT(sc, BCE_VERBOSE, "Enabling NVRAM write.\n"); 1232 1233 val = REG_RD(sc, BCE_MISC_CFG); 1234 REG_WR(sc, BCE_MISC_CFG, val | BCE_MISC_CFG_NVM_WR_EN_PCI); 1235 1236 if (!sc->bce_flash_info->buffered) { 1237 int j; 1238 1239 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 1240 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_WREN | BCE_NVM_COMMAND_DOIT); 1241 1242 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1243 DELAY(5); 1244 1245 val = REG_RD(sc, BCE_NVM_COMMAND); 1246 if (val & BCE_NVM_COMMAND_DONE) 1247 break; 1248 } 1249 1250 if (j >= NVRAM_TIMEOUT_COUNT) { 1251 DBPRINT(sc, BCE_WARN, "Timeout writing NVRAM!\n"); 1252 return EBUSY; 1253 } 1254 } 1255 return 0; 1256} 1257 1258 1259/****************************************************************************/ 1260/* Disable NVRAM write access. */ 1261/* */ 1262/* When the caller is finished writing to NVRAM write access must be */ 1263/* disabled. */ 1264/* */ 1265/* Returns: */ 1266/* Nothing. */ 1267/****************************************************************************/ 1268static void 1269bce_disable_nvram_write(struct bce_softc *sc) 1270{ 1271 u32 val; 1272 1273 DBPRINT(sc, BCE_VERBOSE, "Disabling NVRAM write.\n"); 1274 1275 val = REG_RD(sc, BCE_MISC_CFG); 1276 REG_WR(sc, BCE_MISC_CFG, val & ~BCE_MISC_CFG_NVM_WR_EN); 1277} 1278#endif 1279 1280 1281/****************************************************************************/ 1282/* Enable NVRAM access. */ 1283/* */ 1284/* Before accessing NVRAM for read or write operations the caller must */ 1285/* enabled NVRAM access. */ 1286/* */ 1287/* Returns: */ 1288/* Nothing. */ 1289/****************************************************************************/ 1290static void 1291bce_enable_nvram_access(struct bce_softc *sc) 1292{ 1293 u32 val; 1294 1295 DBPRINT(sc, BCE_VERBOSE, "Enabling NVRAM access.\n"); 1296 1297 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE); 1298 /* Enable both bits, even on read. */ 1299 REG_WR(sc, BCE_NVM_ACCESS_ENABLE, 1300 val | BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN); 1301} 1302 1303 1304/****************************************************************************/ 1305/* Disable NVRAM access. */ 1306/* */ 1307/* When the caller is finished accessing NVRAM access must be disabled. */ 1308/* */ 1309/* Returns: */ 1310/* Nothing. */ 1311/****************************************************************************/ 1312static void 1313bce_disable_nvram_access(struct bce_softc *sc) 1314{ 1315 u32 val; 1316 1317 DBPRINT(sc, BCE_VERBOSE, "Disabling NVRAM access.\n"); 1318 1319 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE); 1320 1321 /* Disable both bits, even after read. */ 1322 REG_WR(sc, BCE_NVM_ACCESS_ENABLE, 1323 val & ~(BCE_NVM_ACCESS_ENABLE_EN | 1324 BCE_NVM_ACCESS_ENABLE_WR_EN)); 1325} 1326 1327 1328#ifdef BCE_NVRAM_WRITE_SUPPORT 1329/****************************************************************************/ 1330/* Erase NVRAM page before writing. */ 1331/* */ 1332/* Non-buffered flash parts require that a page be erased before it is */ 1333/* written. */ 1334/* */ 1335/* Returns: */ 1336/* 0 on success, positive value on failure. */ 1337/****************************************************************************/ 1338static int 1339bce_nvram_erase_page(struct bce_softc *sc, u32 offset) 1340{ 1341 u32 cmd; 1342 int j; 1343 1344 /* Buffered flash doesn't require an erase. */ 1345 if (sc->bce_flash_info->buffered) 1346 return 0; 1347 1348 DBPRINT(sc, BCE_VERBOSE, "Erasing NVRAM page.\n"); 1349 1350 /* Build an erase command. */ 1351 cmd = BCE_NVM_COMMAND_ERASE | BCE_NVM_COMMAND_WR | 1352 BCE_NVM_COMMAND_DOIT; 1353 1354 /* 1355 * Clear the DONE bit separately, set the NVRAM adress to erase, 1356 * and issue the erase command. 1357 */ 1358 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 1359 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 1360 REG_WR(sc, BCE_NVM_COMMAND, cmd); 1361 1362 /* Wait for completion. */ 1363 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1364 u32 val; 1365 1366 DELAY(5); 1367 1368 val = REG_RD(sc, BCE_NVM_COMMAND); 1369 if (val & BCE_NVM_COMMAND_DONE) 1370 break; 1371 } 1372 1373 if (j >= NVRAM_TIMEOUT_COUNT) { 1374 DBPRINT(sc, BCE_WARN, "Timeout erasing NVRAM.\n"); 1375 return EBUSY; 1376 } 1377 1378 return 0; 1379} 1380#endif /* BCE_NVRAM_WRITE_SUPPORT */ 1381 1382 1383/****************************************************************************/ 1384/* Read a dword (32 bits) from NVRAM. */ 1385/* */ 1386/* Read a 32 bit word from NVRAM. The caller is assumed to have already */ 1387/* obtained the NVRAM lock and enabled the controller for NVRAM access. */ 1388/* */ 1389/* Returns: */ 1390/* 0 on success and the 32 bit value read, positive value on failure. */ 1391/****************************************************************************/ 1392static int 1393bce_nvram_read_dword(struct bce_softc *sc, u32 offset, u8 *ret_val, 1394 u32 cmd_flags) 1395{ 1396 u32 cmd; 1397 int i, rc = 0; 1398 1399 /* Build the command word. */ 1400 cmd = BCE_NVM_COMMAND_DOIT | cmd_flags; 1401 1402 /* Calculate the offset for buffered flash. */ 1403 if (sc->bce_flash_info->buffered) { 1404 offset = ((offset / sc->bce_flash_info->page_size) << 1405 sc->bce_flash_info->page_bits) + 1406 (offset % sc->bce_flash_info->page_size); 1407 } 1408 1409 /* 1410 * Clear the DONE bit separately, set the address to read, 1411 * and issue the read. 1412 */ 1413 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 1414 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 1415 REG_WR(sc, BCE_NVM_COMMAND, cmd); 1416 1417 /* Wait for completion. */ 1418 for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) { 1419 u32 val; 1420 1421 DELAY(5); 1422 1423 val = REG_RD(sc, BCE_NVM_COMMAND); 1424 if (val & BCE_NVM_COMMAND_DONE) { 1425 val = REG_RD(sc, BCE_NVM_READ); 1426 1427 val = bce_be32toh(val); 1428 memcpy(ret_val, &val, 4); 1429 break; 1430 } 1431 } 1432 1433 /* Check for errors. */ 1434 if (i >= NVRAM_TIMEOUT_COUNT) { 1435 BCE_PRINTF(sc, "%s(%d): Timeout error reading NVRAM at offset 0x%08X!\n", 1436 __FILE__, __LINE__, offset); 1437 rc = EBUSY; 1438 } 1439 1440 return(rc); 1441} 1442 1443 1444#ifdef BCE_NVRAM_WRITE_SUPPORT 1445/****************************************************************************/ 1446/* Write a dword (32 bits) to NVRAM. */ 1447/* */ 1448/* Write a 32 bit word to NVRAM. The caller is assumed to have already */ 1449/* obtained the NVRAM lock, enabled the controller for NVRAM access, and */ 1450/* enabled NVRAM write access. */ 1451/* */ 1452/* Returns: */ 1453/* 0 on success, positive value on failure. */ 1454/****************************************************************************/ 1455static int 1456bce_nvram_write_dword(struct bce_softc *sc, u32 offset, u8 *val, 1457 u32 cmd_flags) 1458{ 1459 u32 cmd, val32; 1460 int j; 1461 1462 /* Build the command word. */ 1463 cmd = BCE_NVM_COMMAND_DOIT | BCE_NVM_COMMAND_WR | cmd_flags; 1464 1465 /* Calculate the offset for buffered flash. */ 1466 if (sc->bce_flash_info->buffered) { 1467 offset = ((offset / sc->bce_flash_info->page_size) << 1468 sc->bce_flash_info->page_bits) + 1469 (offset % sc->bce_flash_info->page_size); 1470 } 1471 1472 /* 1473 * Clear the DONE bit separately, convert NVRAM data to big-endian, 1474 * set the NVRAM address to write, and issue the write command 1475 */ 1476 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 1477 memcpy(&val32, val, 4); 1478 val32 = htobe32(val32); 1479 REG_WR(sc, BCE_NVM_WRITE, val32); 1480 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 1481 REG_WR(sc, BCE_NVM_COMMAND, cmd); 1482 1483 /* Wait for completion. */ 1484 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1485 DELAY(5); 1486 1487 if (REG_RD(sc, BCE_NVM_COMMAND) & BCE_NVM_COMMAND_DONE) 1488 break; 1489 } 1490 if (j >= NVRAM_TIMEOUT_COUNT) { 1491 BCE_PRINTF(sc, "%s(%d): Timeout error writing NVRAM at offset 0x%08X\n", 1492 __FILE__, __LINE__, offset); 1493 return EBUSY; 1494 } 1495 1496 return 0; 1497} 1498#endif /* BCE_NVRAM_WRITE_SUPPORT */ 1499 1500 1501/****************************************************************************/ 1502/* Initialize NVRAM access. */ 1503/* */ 1504/* Identify the NVRAM device in use and prepare the NVRAM interface to */ 1505/* access that device. */ 1506/* */ 1507/* Returns: */ 1508/* 0 on success, positive value on failure. */ 1509/****************************************************************************/ 1510static int 1511bce_init_nvram(struct bce_softc *sc) 1512{ 1513 u32 val; 1514 int j, entry_count, rc; 1515 struct flash_spec *flash; 1516 1517 DBPRINT(sc,BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 1518 1519 /* Determine the selected interface. */ 1520 val = REG_RD(sc, BCE_NVM_CFG1); 1521 1522 entry_count = sizeof(flash_table) / sizeof(struct flash_spec); 1523 1524 rc = 0; 1525 1526 /* 1527 * Flash reconfiguration is required to support additional 1528 * NVRAM devices not directly supported in hardware. 1529 * Check if the flash interface was reconfigured 1530 * by the bootcode. 1531 */ 1532 1533 if (val & 0x40000000) { 1534 /* Flash interface reconfigured by bootcode. */ 1535 1536 DBPRINT(sc,BCE_INFO_LOAD, 1537 "bce_init_nvram(): Flash WAS reconfigured.\n"); 1538 1539 for (j = 0, flash = &flash_table[0]; j < entry_count; 1540 j++, flash++) { 1541 if ((val & FLASH_BACKUP_STRAP_MASK) == 1542 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) { 1543 sc->bce_flash_info = flash; 1544 break; 1545 } 1546 } 1547 } else { 1548 /* Flash interface not yet reconfigured. */ 1549 u32 mask; 1550 1551 DBPRINT(sc,BCE_INFO_LOAD, 1552 "bce_init_nvram(): Flash was NOT reconfigured.\n"); 1553 1554 if (val & (1 << 23)) 1555 mask = FLASH_BACKUP_STRAP_MASK; 1556 else 1557 mask = FLASH_STRAP_MASK; 1558 1559 /* Look for the matching NVRAM device configuration data. */ 1560 for (j = 0, flash = &flash_table[0]; j < entry_count; j++, flash++) { 1561 1562 /* Check if the device matches any of the known devices. */ 1563 if ((val & mask) == (flash->strapping & mask)) { 1564 /* Found a device match. */ 1565 sc->bce_flash_info = flash; 1566 1567 /* Request access to the flash interface. */ 1568 if ((rc = bce_acquire_nvram_lock(sc)) != 0) 1569 return rc; 1570 1571 /* Reconfigure the flash interface. */ 1572 bce_enable_nvram_access(sc); 1573 REG_WR(sc, BCE_NVM_CFG1, flash->config1); 1574 REG_WR(sc, BCE_NVM_CFG2, flash->config2); 1575 REG_WR(sc, BCE_NVM_CFG3, flash->config3); 1576 REG_WR(sc, BCE_NVM_WRITE1, flash->write1); 1577 bce_disable_nvram_access(sc); 1578 bce_release_nvram_lock(sc); 1579 1580 break; 1581 } 1582 } 1583 } 1584 1585 /* Check if a matching device was found. */ 1586 if (j == entry_count) { 1587 sc->bce_flash_info = NULL; 1588 BCE_PRINTF(sc, "%s(%d): Unknown Flash NVRAM found!\n", 1589 __FILE__, __LINE__); 1590 rc = ENODEV; 1591 } 1592 1593 /* Write the flash config data to the shared memory interface. */ 1594 val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_SHARED_HW_CFG_CONFIG2); 1595 val &= BCE_SHARED_HW_CFG2_NVM_SIZE_MASK; 1596 if (val) 1597 sc->bce_flash_size = val; 1598 else 1599 sc->bce_flash_size = sc->bce_flash_info->total_size; 1600 1601 DBPRINT(sc, BCE_INFO_LOAD, "bce_init_nvram() flash->total_size = 0x%08X\n", 1602 sc->bce_flash_info->total_size); 1603 1604 DBPRINT(sc,BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 1605 1606 return rc; 1607} 1608 1609 1610/****************************************************************************/ 1611/* Read an arbitrary range of data from NVRAM. */ 1612/* */ 1613/* Prepares the NVRAM interface for access and reads the requested data */ 1614/* into the supplied buffer. */ 1615/* */ 1616/* Returns: */ 1617/* 0 on success and the data read, positive value on failure. */ 1618/****************************************************************************/ 1619static int 1620bce_nvram_read(struct bce_softc *sc, u32 offset, u8 *ret_buf, 1621 int buf_size) 1622{ 1623 int rc = 0; 1624 u32 cmd_flags, offset32, len32, extra; 1625 1626 if (buf_size == 0) 1627 return 0; 1628 1629 /* Request access to the flash interface. */ 1630 if ((rc = bce_acquire_nvram_lock(sc)) != 0) 1631 return rc; 1632 1633 /* Enable access to flash interface */ 1634 bce_enable_nvram_access(sc); 1635 1636 len32 = buf_size; 1637 offset32 = offset; 1638 extra = 0; 1639 1640 cmd_flags = 0; 1641 1642 if (offset32 & 3) { 1643 u8 buf[4]; 1644 u32 pre_len; 1645 1646 offset32 &= ~3; 1647 pre_len = 4 - (offset & 3); 1648 1649 if (pre_len >= len32) { 1650 pre_len = len32; 1651 cmd_flags = BCE_NVM_COMMAND_FIRST | BCE_NVM_COMMAND_LAST; 1652 } 1653 else { 1654 cmd_flags = BCE_NVM_COMMAND_FIRST; 1655 } 1656 1657 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 1658 1659 if (rc) 1660 return rc; 1661 1662 memcpy(ret_buf, buf + (offset & 3), pre_len); 1663 1664 offset32 += 4; 1665 ret_buf += pre_len; 1666 len32 -= pre_len; 1667 } 1668 1669 if (len32 & 3) { 1670 extra = 4 - (len32 & 3); 1671 len32 = (len32 + 4) & ~3; 1672 } 1673 1674 if (len32 == 4) { 1675 u8 buf[4]; 1676 1677 if (cmd_flags) 1678 cmd_flags = BCE_NVM_COMMAND_LAST; 1679 else 1680 cmd_flags = BCE_NVM_COMMAND_FIRST | 1681 BCE_NVM_COMMAND_LAST; 1682 1683 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 1684 1685 memcpy(ret_buf, buf, 4 - extra); 1686 } 1687 else if (len32 > 0) { 1688 u8 buf[4]; 1689 1690 /* Read the first word. */ 1691 if (cmd_flags) 1692 cmd_flags = 0; 1693 else 1694 cmd_flags = BCE_NVM_COMMAND_FIRST; 1695 1696 rc = bce_nvram_read_dword(sc, offset32, ret_buf, cmd_flags); 1697 1698 /* Advance to the next dword. */ 1699 offset32 += 4; 1700 ret_buf += 4; 1701 len32 -= 4; 1702 1703 while (len32 > 4 && rc == 0) { 1704 rc = bce_nvram_read_dword(sc, offset32, ret_buf, 0); 1705 1706 /* Advance to the next dword. */ 1707 offset32 += 4; 1708 ret_buf += 4; 1709 len32 -= 4; 1710 } 1711 1712 if (rc) 1713 return rc; 1714 1715 cmd_flags = BCE_NVM_COMMAND_LAST; 1716 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 1717 1718 memcpy(ret_buf, buf, 4 - extra); 1719 } 1720 1721 /* Disable access to flash interface and release the lock. */ 1722 bce_disable_nvram_access(sc); 1723 bce_release_nvram_lock(sc); 1724 1725 return rc; 1726} 1727 1728 1729#ifdef BCE_NVRAM_WRITE_SUPPORT 1730/****************************************************************************/ 1731/* Write an arbitrary range of data from NVRAM. */ 1732/* */ 1733/* Prepares the NVRAM interface for write access and writes the requested */ 1734/* data from the supplied buffer. The caller is responsible for */ 1735/* calculating any appropriate CRCs. */ 1736/* */ 1737/* Returns: */ 1738/* 0 on success, positive value on failure. */ 1739/****************************************************************************/ 1740static int 1741bce_nvram_write(struct bce_softc *sc, u32 offset, u8 *data_buf, 1742 int buf_size) 1743{ 1744 u32 written, offset32, len32; 1745 u8 *buf, start[4], end[4]; 1746 int rc = 0; 1747 int align_start, align_end; 1748 1749 buf = data_buf; 1750 offset32 = offset; 1751 len32 = buf_size; 1752 align_start = align_end = 0; 1753 1754 if ((align_start = (offset32 & 3))) { 1755 offset32 &= ~3; 1756 len32 += align_start; 1757 if ((rc = bce_nvram_read(sc, offset32, start, 4))) 1758 return rc; 1759 } 1760 1761 if (len32 & 3) { 1762 if ((len32 > 4) || !align_start) { 1763 align_end = 4 - (len32 & 3); 1764 len32 += align_end; 1765 if ((rc = bce_nvram_read(sc, offset32 + len32 - 4, 1766 end, 4))) { 1767 return rc; 1768 } 1769 } 1770 } 1771 1772 if (align_start || align_end) { 1773 buf = malloc(len32, M_DEVBUF, M_NOWAIT); 1774 if (buf == 0) 1775 return ENOMEM; 1776 if (align_start) { 1777 memcpy(buf, start, 4); 1778 } 1779 if (align_end) { 1780 memcpy(buf + len32 - 4, end, 4); 1781 } 1782 memcpy(buf + align_start, data_buf, buf_size); 1783 } 1784 1785 written = 0; 1786 while ((written < len32) && (rc == 0)) { 1787 u32 page_start, page_end, data_start, data_end; 1788 u32 addr, cmd_flags; 1789 int i; 1790 u8 flash_buffer[264]; 1791 1792 /* Find the page_start addr */ 1793 page_start = offset32 + written; 1794 page_start -= (page_start % sc->bce_flash_info->page_size); 1795 /* Find the page_end addr */ 1796 page_end = page_start + sc->bce_flash_info->page_size; 1797 /* Find the data_start addr */ 1798 data_start = (written == 0) ? offset32 : page_start; 1799 /* Find the data_end addr */ 1800 data_end = (page_end > offset32 + len32) ? 1801 (offset32 + len32) : page_end; 1802 1803 /* Request access to the flash interface. */ 1804 if ((rc = bce_acquire_nvram_lock(sc)) != 0) 1805 goto nvram_write_end; 1806 1807 /* Enable access to flash interface */ 1808 bce_enable_nvram_access(sc); 1809 1810 cmd_flags = BCE_NVM_COMMAND_FIRST; 1811 if (sc->bce_flash_info->buffered == 0) { 1812 int j; 1813 1814 /* Read the whole page into the buffer 1815 * (non-buffer flash only) */ 1816 for (j = 0; j < sc->bce_flash_info->page_size; j += 4) { 1817 if (j == (sc->bce_flash_info->page_size - 4)) { 1818 cmd_flags |= BCE_NVM_COMMAND_LAST; 1819 } 1820 rc = bce_nvram_read_dword(sc, 1821 page_start + j, 1822 &flash_buffer[j], 1823 cmd_flags); 1824 1825 if (rc) 1826 goto nvram_write_end; 1827 1828 cmd_flags = 0; 1829 } 1830 } 1831 1832 /* Enable writes to flash interface (unlock write-protect) */ 1833 if ((rc = bce_enable_nvram_write(sc)) != 0) 1834 goto nvram_write_end; 1835 1836 /* Erase the page */ 1837 if ((rc = bce_nvram_erase_page(sc, page_start)) != 0) 1838 goto nvram_write_end; 1839 1840 /* Re-enable the write again for the actual write */ 1841 bce_enable_nvram_write(sc); 1842 1843 /* Loop to write back the buffer data from page_start to 1844 * data_start */ 1845 i = 0; 1846 if (sc->bce_flash_info->buffered == 0) { 1847 for (addr = page_start; addr < data_start; 1848 addr += 4, i += 4) { 1849 1850 rc = bce_nvram_write_dword(sc, addr, 1851 &flash_buffer[i], cmd_flags); 1852 1853 if (rc != 0) 1854 goto nvram_write_end; 1855 1856 cmd_flags = 0; 1857 } 1858 } 1859 1860 /* Loop to write the new data from data_start to data_end */ 1861 for (addr = data_start; addr < data_end; addr += 4, i++) { 1862 if ((addr == page_end - 4) || 1863 ((sc->bce_flash_info->buffered) && 1864 (addr == data_end - 4))) { 1865 1866 cmd_flags |= BCE_NVM_COMMAND_LAST; 1867 } 1868 rc = bce_nvram_write_dword(sc, addr, buf, 1869 cmd_flags); 1870 1871 if (rc != 0) 1872 goto nvram_write_end; 1873 1874 cmd_flags = 0; 1875 buf += 4; 1876 } 1877 1878 /* Loop to write back the buffer data from data_end 1879 * to page_end */ 1880 if (sc->bce_flash_info->buffered == 0) { 1881 for (addr = data_end; addr < page_end; 1882 addr += 4, i += 4) { 1883 1884 if (addr == page_end-4) { 1885 cmd_flags = BCE_NVM_COMMAND_LAST; 1886 } 1887 rc = bce_nvram_write_dword(sc, addr, 1888 &flash_buffer[i], cmd_flags); 1889 1890 if (rc != 0) 1891 goto nvram_write_end; 1892 1893 cmd_flags = 0; 1894 } 1895 } 1896 1897 /* Disable writes to flash interface (lock write-protect) */ 1898 bce_disable_nvram_write(sc); 1899 1900 /* Disable access to flash interface */ 1901 bce_disable_nvram_access(sc); 1902 bce_release_nvram_lock(sc); 1903 1904 /* Increment written */ 1905 written += data_end - data_start; 1906 } 1907 1908nvram_write_end: 1909 if (align_start || align_end) 1910 free(buf, M_DEVBUF); 1911 1912 return rc; 1913} 1914#endif /* BCE_NVRAM_WRITE_SUPPORT */ 1915 1916 1917/****************************************************************************/ 1918/* Verifies that NVRAM is accessible and contains valid data. */ 1919/* */ 1920/* Reads the configuration data from NVRAM and verifies that the CRC is */ 1921/* correct. */ 1922/* */ 1923/* Returns: */ 1924/* 0 on success, positive value on failure. */ 1925/****************************************************************************/ 1926static int 1927bce_nvram_test(struct bce_softc *sc) 1928{ 1929 u32 buf[BCE_NVRAM_SIZE / 4]; 1930 u8 *data = (u8 *) buf; 1931 int rc = 0; 1932 u32 magic, csum; 1933 1934 1935 /* 1936 * Check that the device NVRAM is valid by reading 1937 * the magic value at offset 0. 1938 */ 1939 if ((rc = bce_nvram_read(sc, 0, data, 4)) != 0) 1940 goto bce_nvram_test_done; 1941 1942 1943 magic = bce_be32toh(buf[0]); 1944 if (magic != BCE_NVRAM_MAGIC) { 1945 rc = ENODEV; 1946 BCE_PRINTF(sc, "%s(%d): Invalid NVRAM magic value! Expected: 0x%08X, " 1947 "Found: 0x%08X\n", 1948 __FILE__, __LINE__, BCE_NVRAM_MAGIC, magic); 1949 goto bce_nvram_test_done; 1950 } 1951 1952 /* 1953 * Verify that the device NVRAM includes valid 1954 * configuration data. 1955 */ 1956 if ((rc = bce_nvram_read(sc, 0x100, data, BCE_NVRAM_SIZE)) != 0) 1957 goto bce_nvram_test_done; 1958 1959 csum = ether_crc32_le(data, 0x100); 1960 if (csum != BCE_CRC32_RESIDUAL) { 1961 rc = ENODEV; 1962 BCE_PRINTF(sc, "%s(%d): Invalid Manufacturing Information NVRAM CRC! " 1963 "Expected: 0x%08X, Found: 0x%08X\n", 1964 __FILE__, __LINE__, BCE_CRC32_RESIDUAL, csum); 1965 goto bce_nvram_test_done; 1966 } 1967 1968 csum = ether_crc32_le(data + 0x100, 0x100); 1969 if (csum != BCE_CRC32_RESIDUAL) { 1970 BCE_PRINTF(sc, "%s(%d): Invalid Feature Configuration Information " 1971 "NVRAM CRC! Expected: 0x%08X, Found: 08%08X\n", 1972 __FILE__, __LINE__, BCE_CRC32_RESIDUAL, csum); 1973 rc = ENODEV; 1974 } 1975 1976bce_nvram_test_done: 1977 return rc; 1978} 1979 1980 1981/****************************************************************************/ 1982/* Free any DMA memory owned by the driver. */ 1983/* */ 1984/* Scans through each data structre that requires DMA memory and frees */ 1985/* the memory if allocated. */ 1986/* */ 1987/* Returns: */ 1988/* Nothing. */ 1989/****************************************************************************/ 1990static void 1991bce_dma_free(struct bce_softc *sc) 1992{ 1993 int i; 1994 1995 DBPRINT(sc,BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 1996 1997 /* Destroy the status block. */ 1998 if (sc->status_block != NULL) 1999 bus_dmamem_free( 2000 sc->status_tag, 2001 sc->status_block, 2002 sc->status_map); 2003 2004 if (sc->status_map != NULL) { 2005 bus_dmamap_unload( 2006 sc->status_tag, 2007 sc->status_map); 2008 bus_dmamap_destroy(sc->status_tag, 2009 sc->status_map); 2010 } 2011 2012 if (sc->status_tag != NULL) 2013 bus_dma_tag_destroy(sc->status_tag); 2014 2015 2016 /* Destroy the statistics block. */ 2017 if (sc->stats_block != NULL) 2018 bus_dmamem_free( 2019 sc->stats_tag, 2020 sc->stats_block, 2021 sc->stats_map); 2022 2023 if (sc->stats_map != NULL) { 2024 bus_dmamap_unload( 2025 sc->stats_tag, 2026 sc->stats_map); 2027 bus_dmamap_destroy(sc->stats_tag, 2028 sc->stats_map); 2029 } 2030 2031 if (sc->stats_tag != NULL) 2032 bus_dma_tag_destroy(sc->stats_tag); 2033 2034 2035 /* Free, unmap and destroy all TX buffer descriptor chain pages. */ 2036 for (i = 0; i < TX_PAGES; i++ ) { 2037 if (sc->tx_bd_chain[i] != NULL) 2038 bus_dmamem_free( 2039 sc->tx_bd_chain_tag, 2040 sc->tx_bd_chain[i], 2041 sc->tx_bd_chain_map[i]); 2042 2043 if (sc->tx_bd_chain_map[i] != NULL) { 2044 bus_dmamap_unload( 2045 sc->tx_bd_chain_tag, 2046 sc->tx_bd_chain_map[i]); 2047 bus_dmamap_destroy( 2048 sc->tx_bd_chain_tag, 2049 sc->tx_bd_chain_map[i]); 2050 } 2051 2052 } 2053 2054 /* Destroy the TX buffer descriptor tag. */ 2055 if (sc->tx_bd_chain_tag != NULL) 2056 bus_dma_tag_destroy(sc->tx_bd_chain_tag); 2057 2058 2059 /* Free, unmap and destroy all RX buffer descriptor chain pages. */ 2060 for (i = 0; i < RX_PAGES; i++ ) { 2061 if (sc->rx_bd_chain[i] != NULL) 2062 bus_dmamem_free( 2063 sc->rx_bd_chain_tag, 2064 sc->rx_bd_chain[i], 2065 sc->rx_bd_chain_map[i]); 2066 2067 if (sc->rx_bd_chain_map[i] != NULL) { 2068 bus_dmamap_unload( 2069 sc->rx_bd_chain_tag, 2070 sc->rx_bd_chain_map[i]); 2071 bus_dmamap_destroy( 2072 sc->rx_bd_chain_tag, 2073 sc->rx_bd_chain_map[i]); 2074 } 2075 } 2076 2077 /* Destroy the RX buffer descriptor tag. */ 2078 if (sc->rx_bd_chain_tag != NULL) 2079 bus_dma_tag_destroy(sc->rx_bd_chain_tag); 2080 2081 2082 /* Unload and destroy the TX mbuf maps. */ 2083 for (i = 0; i < TOTAL_TX_BD; i++) { 2084 if (sc->tx_mbuf_map[i] != NULL) { 2085 bus_dmamap_unload(sc->tx_mbuf_tag, 2086 sc->tx_mbuf_map[i]); 2087 bus_dmamap_destroy(sc->tx_mbuf_tag, 2088 sc->tx_mbuf_map[i]); 2089 } 2090 } 2091 2092 /* Destroy the TX mbuf tag. */ 2093 if (sc->tx_mbuf_tag != NULL) 2094 bus_dma_tag_destroy(sc->tx_mbuf_tag); 2095 2096 2097 /* Unload and destroy the RX mbuf maps. */ 2098 for (i = 0; i < TOTAL_RX_BD; i++) { 2099 if (sc->rx_mbuf_map[i] != NULL) { 2100 bus_dmamap_unload(sc->rx_mbuf_tag, 2101 sc->rx_mbuf_map[i]); 2102 bus_dmamap_destroy(sc->rx_mbuf_tag, 2103 sc->rx_mbuf_map[i]); 2104 } 2105 } 2106 2107 /* Destroy the RX mbuf tag. */ 2108 if (sc->rx_mbuf_tag != NULL) 2109 bus_dma_tag_destroy(sc->rx_mbuf_tag); 2110 2111 2112 /* Destroy the parent tag */ 2113 if (sc->parent_tag != NULL) 2114 bus_dma_tag_destroy(sc->parent_tag); 2115 2116 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 2117 2118} 2119 2120 2121/****************************************************************************/ 2122/* Get DMA memory from the OS. */ 2123/* */ 2124/* Validates that the OS has provided DMA buffers in response to a */ 2125/* bus_dmamap_load() call and saves the physical address of those buffers. */ 2126/* When the callback is used the OS will return 0 for the mapping function */ 2127/* (bus_dmamap_load()) so we use the value of map_arg->maxsegs to pass any */ 2128/* failures back to the caller. */ 2129/* */ 2130/* Returns: */ 2131/* Nothing. */ 2132/****************************************************************************/ 2133static void 2134bce_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2135{ 2136 bus_addr_t *busaddr = arg; 2137 2138 /* Simulate a mapping failure. */ 2139 DBRUNIF(DB_RANDOMTRUE(bce_debug_dma_map_addr_failure), 2140 printf("bce: %s(%d): Simulating DMA mapping error.\n", 2141 __FILE__, __LINE__); 2142 error = ENOMEM); 2143 2144 /* Check for an error and signal the caller that an error occurred. */ 2145 if (error) { 2146 printf("bce %s(%d): DMA mapping error! error = %d, " 2147 "nseg = %d\n", __FILE__, __LINE__, error, nseg); 2148 *busaddr = 0; 2149 return; 2150 } 2151 2152 *busaddr = segs->ds_addr; 2153 return; 2154} 2155 2156 2157/****************************************************************************/ 2158/* Allocate any DMA memory needed by the driver. */ 2159/* */ 2160/* Allocates DMA memory needed for the various global structures needed by */ 2161/* hardware. */ 2162/* */ 2163/* Returns: */ 2164/* 0 for success, positive value for failure. */ 2165/****************************************************************************/ 2166static int 2167bce_dma_alloc(device_t dev) 2168{ 2169 struct bce_softc *sc; 2170 int i, error, rc = 0; 2171 bus_addr_t busaddr; 2172 2173 sc = device_get_softc(dev); 2174 2175 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 2176 2177 /* 2178 * Allocate the parent bus DMA tag appropriate for PCI. 2179 */ 2180 if (bus_dma_tag_create(NULL, /* parent */ 2181 1, /* alignment */ 2182 BCE_DMA_BOUNDARY, /* boundary */ 2183 sc->max_bus_addr, /* lowaddr */ 2184 BUS_SPACE_MAXADDR, /* highaddr */ 2185 NULL, /* filterfunc */ 2186 NULL, /* filterarg */ 2187 MAXBSIZE, /* maxsize */ 2188 BUS_SPACE_UNRESTRICTED, /* nsegments */ 2189 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 2190 0, /* flags */ 2191 NULL, /* locfunc */ 2192 NULL, /* lockarg */ 2193 &sc->parent_tag)) { 2194 BCE_PRINTF(sc, "%s(%d): Could not allocate parent DMA tag!\n", 2195 __FILE__, __LINE__); 2196 rc = ENOMEM; 2197 goto bce_dma_alloc_exit; 2198 } 2199 2200 /* 2201 * Create a DMA tag for the status block, allocate and clear the 2202 * memory, map the memory into DMA space, and fetch the physical 2203 * address of the block. 2204 */ 2205 if (bus_dma_tag_create( 2206 sc->parent_tag, /* parent */ 2207 BCE_DMA_ALIGN, /* alignment */ 2208 BCE_DMA_BOUNDARY, /* boundary */ 2209 sc->max_bus_addr, /* lowaddr */ 2210 BUS_SPACE_MAXADDR, /* highaddr */ 2211 NULL, /* filterfunc */ 2212 NULL, /* filterarg */ 2213 BCE_STATUS_BLK_SZ, /* maxsize */ 2214 1, /* nsegments */ 2215 BCE_STATUS_BLK_SZ, /* maxsegsize */ 2216 0, /* flags */ 2217 NULL, /* lockfunc */ 2218 NULL, /* lockarg */ 2219 &sc->status_tag)) { 2220 BCE_PRINTF(sc, "%s(%d): Could not allocate status block DMA tag!\n", 2221 __FILE__, __LINE__); 2222 rc = ENOMEM; 2223 goto bce_dma_alloc_exit; 2224 } 2225 2226 if(bus_dmamem_alloc( 2227 sc->status_tag, /* dmat */ 2228 (void **)&sc->status_block, /* vaddr */ 2229 BUS_DMA_NOWAIT, /* flags */ 2230 &sc->status_map)) { 2231 BCE_PRINTF(sc, "%s(%d): Could not allocate status block DMA memory!\n", 2232 __FILE__, __LINE__); 2233 rc = ENOMEM; 2234 goto bce_dma_alloc_exit; 2235 } 2236 2237 bzero((char *)sc->status_block, BCE_STATUS_BLK_SZ); 2238 2239 error = bus_dmamap_load( 2240 sc->status_tag, /* dmat */ 2241 sc->status_map, /* map */ 2242 sc->status_block, /* buf */ 2243 BCE_STATUS_BLK_SZ, /* buflen */ 2244 bce_dma_map_addr, /* callback */ 2245 &busaddr, /* callbackarg */ 2246 BUS_DMA_NOWAIT); /* flags */ 2247 2248 if (error) { 2249 BCE_PRINTF(sc, "%s(%d): Could not map status block DMA memory!\n", 2250 __FILE__, __LINE__); 2251 rc = ENOMEM; 2252 goto bce_dma_alloc_exit; 2253 } 2254 2255 sc->status_block_paddr = busaddr; 2256 /* DRC - Fix for 64 bit addresses. */ 2257 DBPRINT(sc, BCE_INFO, "status_block_paddr = 0x%08X\n", 2258 (u32) sc->status_block_paddr); 2259 2260 /* 2261 * Create a DMA tag for the statistics block, allocate and clear the 2262 * memory, map the memory into DMA space, and fetch the physical 2263 * address of the block. 2264 */ 2265 if (bus_dma_tag_create( 2266 sc->parent_tag, /* parent */ 2267 BCE_DMA_ALIGN, /* alignment */ 2268 BCE_DMA_BOUNDARY, /* boundary */ 2269 sc->max_bus_addr, /* lowaddr */ 2270 BUS_SPACE_MAXADDR, /* highaddr */ 2271 NULL, /* filterfunc */ 2272 NULL, /* filterarg */ 2273 BCE_STATS_BLK_SZ, /* maxsize */ 2274 1, /* nsegments */ 2275 BCE_STATS_BLK_SZ, /* maxsegsize */ 2276 0, /* flags */ 2277 NULL, /* lockfunc */ 2278 NULL, /* lockarg */ 2279 &sc->stats_tag)) { 2280 BCE_PRINTF(sc, "%s(%d): Could not allocate statistics block DMA tag!\n", 2281 __FILE__, __LINE__); 2282 rc = ENOMEM; 2283 goto bce_dma_alloc_exit; 2284 } 2285 2286 if (bus_dmamem_alloc( 2287 sc->stats_tag, /* dmat */ 2288 (void **)&sc->stats_block, /* vaddr */ 2289 BUS_DMA_NOWAIT, /* flags */ 2290 &sc->stats_map)) { 2291 BCE_PRINTF(sc, "%s(%d): Could not allocate statistics block DMA memory!\n", 2292 __FILE__, __LINE__); 2293 rc = ENOMEM; 2294 goto bce_dma_alloc_exit; 2295 } 2296 2297 bzero((char *)sc->stats_block, BCE_STATS_BLK_SZ); 2298 2299 error = bus_dmamap_load( 2300 sc->stats_tag, /* dmat */ 2301 sc->stats_map, /* map */ 2302 sc->stats_block, /* buf */ 2303 BCE_STATS_BLK_SZ, /* buflen */ 2304 bce_dma_map_addr, /* callback */ 2305 &busaddr, /* callbackarg */ 2306 BUS_DMA_NOWAIT); /* flags */ 2307 2308 if(error) { 2309 BCE_PRINTF(sc, "%s(%d): Could not map statistics block DMA memory!\n", 2310 __FILE__, __LINE__); 2311 rc = ENOMEM; 2312 goto bce_dma_alloc_exit; 2313 } 2314 2315 sc->stats_block_paddr = busaddr; 2316 /* DRC - Fix for 64 bit address. */ 2317 DBPRINT(sc,BCE_INFO, "stats_block_paddr = 0x%08X\n", 2318 (u32) sc->stats_block_paddr); 2319 2320 /* 2321 * Create a DMA tag for the TX buffer descriptor chain, 2322 * allocate and clear the memory, and fetch the 2323 * physical address of the block. 2324 */ 2325 if(bus_dma_tag_create( 2326 sc->parent_tag, /* parent */ 2327 BCM_PAGE_SIZE, /* alignment */ 2328 BCE_DMA_BOUNDARY, /* boundary */ 2329 sc->max_bus_addr, /* lowaddr */ 2330 BUS_SPACE_MAXADDR, /* highaddr */ 2331 NULL, /* filterfunc */ 2332 NULL, /* filterarg */ 2333 BCE_TX_CHAIN_PAGE_SZ, /* maxsize */ 2334 1, /* nsegments */ 2335 BCE_TX_CHAIN_PAGE_SZ, /* maxsegsize */ 2336 0, /* flags */ 2337 NULL, /* lockfunc */ 2338 NULL, /* lockarg */ 2339 &sc->tx_bd_chain_tag)) { 2340 BCE_PRINTF(sc, "%s(%d): Could not allocate TX descriptor chain DMA tag!\n", 2341 __FILE__, __LINE__); 2342 rc = ENOMEM; 2343 goto bce_dma_alloc_exit; 2344 } 2345 2346 for (i = 0; i < TX_PAGES; i++) { 2347 2348 if(bus_dmamem_alloc( 2349 sc->tx_bd_chain_tag, /* tag */ 2350 (void **)&sc->tx_bd_chain[i], /* vaddr */ 2351 BUS_DMA_NOWAIT, /* flags */ 2352 &sc->tx_bd_chain_map[i])) { 2353 BCE_PRINTF(sc, "%s(%d): Could not allocate TX descriptor " 2354 "chain DMA memory!\n", __FILE__, __LINE__); 2355 rc = ENOMEM; 2356 goto bce_dma_alloc_exit; 2357 } 2358 2359 error = bus_dmamap_load( 2360 sc->tx_bd_chain_tag, /* dmat */ 2361 sc->tx_bd_chain_map[i], /* map */ 2362 sc->tx_bd_chain[i], /* buf */ 2363 BCE_TX_CHAIN_PAGE_SZ, /* buflen */ 2364 bce_dma_map_addr, /* callback */ 2365 &busaddr, /* callbackarg */ 2366 BUS_DMA_NOWAIT); /* flags */ 2367 2368 if (error) { 2369 BCE_PRINTF(sc, "%s(%d): Could not map TX descriptor chain DMA memory!\n", 2370 __FILE__, __LINE__); 2371 rc = ENOMEM; 2372 goto bce_dma_alloc_exit; 2373 } 2374 2375 sc->tx_bd_chain_paddr[i] = busaddr; 2376 /* DRC - Fix for 64 bit systems. */ 2377 DBPRINT(sc, BCE_INFO, "tx_bd_chain_paddr[%d] = 0x%08X\n", 2378 i, (u32) sc->tx_bd_chain_paddr[i]); 2379 } 2380 2381 /* Create a DMA tag for TX mbufs. */ 2382 if (bus_dma_tag_create( 2383 sc->parent_tag, /* parent */ 2384 1, /* alignment */ 2385 BCE_DMA_BOUNDARY, /* boundary */ 2386 sc->max_bus_addr, /* lowaddr */ 2387 BUS_SPACE_MAXADDR, /* highaddr */ 2388 NULL, /* filterfunc */ 2389 NULL, /* filterarg */ 2390 MCLBYTES * BCE_MAX_SEGMENTS, /* maxsize */ 2391 BCE_MAX_SEGMENTS, /* nsegments */ 2392 MCLBYTES, /* maxsegsize */ 2393 0, /* flags */ 2394 NULL, /* lockfunc */ 2395 NULL, /* lockarg */ 2396 &sc->tx_mbuf_tag)) { 2397 BCE_PRINTF(sc, "%s(%d): Could not allocate TX mbuf DMA tag!\n", 2398 __FILE__, __LINE__); 2399 rc = ENOMEM; 2400 goto bce_dma_alloc_exit; 2401 } 2402 2403 /* Create DMA maps for the TX mbufs clusters. */ 2404 for (i = 0; i < TOTAL_TX_BD; i++) { 2405 if (bus_dmamap_create(sc->tx_mbuf_tag, BUS_DMA_NOWAIT, 2406 &sc->tx_mbuf_map[i])) { 2407 BCE_PRINTF(sc, "%s(%d): Unable to create TX mbuf DMA map!\n", 2408 __FILE__, __LINE__); 2409 rc = ENOMEM; 2410 goto bce_dma_alloc_exit; 2411 } 2412 } 2413 2414 /* 2415 * Create a DMA tag for the RX buffer descriptor chain, 2416 * allocate and clear the memory, and fetch the physical 2417 * address of the blocks. 2418 */ 2419 if (bus_dma_tag_create( 2420 sc->parent_tag, /* parent */ 2421 BCM_PAGE_SIZE, /* alignment */ 2422 BCE_DMA_BOUNDARY, /* boundary */ 2423 BUS_SPACE_MAXADDR, /* lowaddr */ 2424 sc->max_bus_addr, /* lowaddr */ 2425 NULL, /* filter */ 2426 NULL, /* filterarg */ 2427 BCE_RX_CHAIN_PAGE_SZ, /* maxsize */ 2428 1, /* nsegments */ 2429 BCE_RX_CHAIN_PAGE_SZ, /* maxsegsize */ 2430 0, /* flags */ 2431 NULL, /* lockfunc */ 2432 NULL, /* lockarg */ 2433 &sc->rx_bd_chain_tag)) { 2434 BCE_PRINTF(sc, "%s(%d): Could not allocate RX descriptor chain DMA tag!\n", 2435 __FILE__, __LINE__); 2436 rc = ENOMEM; 2437 goto bce_dma_alloc_exit; 2438 } 2439 2440 for (i = 0; i < RX_PAGES; i++) { 2441 2442 if (bus_dmamem_alloc( 2443 sc->rx_bd_chain_tag, /* tag */ 2444 (void **)&sc->rx_bd_chain[i], /* vaddr */ 2445 BUS_DMA_NOWAIT, /* flags */ 2446 &sc->rx_bd_chain_map[i])) { 2447 BCE_PRINTF(sc, "%s(%d): Could not allocate RX descriptor chain " 2448 "DMA memory!\n", __FILE__, __LINE__); 2449 rc = ENOMEM; 2450 goto bce_dma_alloc_exit; 2451 } 2452 2453 bzero((char *)sc->rx_bd_chain[i], BCE_RX_CHAIN_PAGE_SZ); 2454 2455 error = bus_dmamap_load( 2456 sc->rx_bd_chain_tag, /* dmat */ 2457 sc->rx_bd_chain_map[i], /* map */ 2458 sc->rx_bd_chain[i], /* buf */ 2459 BCE_RX_CHAIN_PAGE_SZ, /* buflen */ 2460 bce_dma_map_addr, /* callback */ 2461 &busaddr, /* callbackarg */ 2462 BUS_DMA_NOWAIT); /* flags */ 2463 2464 if (error) { 2465 BCE_PRINTF(sc, "%s(%d): Could not map RX descriptor chain DMA memory!\n", 2466 __FILE__, __LINE__); 2467 rc = ENOMEM; 2468 goto bce_dma_alloc_exit; 2469 } 2470 2471 sc->rx_bd_chain_paddr[i] = busaddr; 2472 /* DRC - Fix for 64 bit systems. */ 2473 DBPRINT(sc, BCE_INFO, "rx_bd_chain_paddr[%d] = 0x%08X\n", 2474 i, (u32) sc->rx_bd_chain_paddr[i]); 2475 } 2476 2477 /* 2478 * Create a DMA tag for RX mbufs. 2479 */ 2480 if (bus_dma_tag_create( 2481 sc->parent_tag, /* parent */ 2482 1, /* alignment */ 2483 BCE_DMA_BOUNDARY, /* boundary */ 2484 sc->max_bus_addr, /* lowaddr */ 2485 BUS_SPACE_MAXADDR, /* highaddr */ 2486 NULL, /* filterfunc */ 2487 NULL, /* filterarg */ 2488 MJUM9BYTES, /* maxsize */ 2489 BCE_MAX_SEGMENTS, /* nsegments */ 2490 MJUM9BYTES, /* maxsegsize */ 2491 0, /* flags */ 2492 NULL, /* lockfunc */ 2493 NULL, /* lockarg */ 2494 &sc->rx_mbuf_tag)) { 2495 BCE_PRINTF(sc, "%s(%d): Could not allocate RX mbuf DMA tag!\n", 2496 __FILE__, __LINE__); 2497 rc = ENOMEM; 2498 goto bce_dma_alloc_exit; 2499 } 2500 2501 /* Create DMA maps for the RX mbuf clusters. */ 2502 for (i = 0; i < TOTAL_RX_BD; i++) { 2503 if (bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_NOWAIT, 2504 &sc->rx_mbuf_map[i])) { 2505 BCE_PRINTF(sc, "%s(%d): Unable to create RX mbuf DMA map!\n", 2506 __FILE__, __LINE__); 2507 rc = ENOMEM; 2508 goto bce_dma_alloc_exit; 2509 } 2510 } 2511 2512bce_dma_alloc_exit: 2513 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 2514 2515 return(rc); 2516} 2517 2518 2519/****************************************************************************/ 2520/* Release all resources used by the driver. */ 2521/* */ 2522/* Releases all resources acquired by the driver including interrupts, */ 2523/* interrupt handler, interfaces, mutexes, and DMA memory. */ 2524/* */ 2525/* Returns: */ 2526/* Nothing. */ 2527/****************************************************************************/ 2528static void 2529bce_release_resources(struct bce_softc *sc) 2530{ 2531 device_t dev; 2532 2533 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 2534 2535 dev = sc->bce_dev; 2536 2537 bce_dma_free(sc); 2538 2539 if (sc->bce_intrhand != NULL) 2540 bus_teardown_intr(dev, sc->bce_irq, sc->bce_intrhand); 2541 2542 if (sc->bce_irq != NULL) 2543 bus_release_resource(dev, 2544 SYS_RES_IRQ, 2545 sc->bce_flags & BCE_USING_MSI_FLAG ? 1 : 0, 2546 sc->bce_irq); 2547 2548 if (sc->bce_flags & BCE_USING_MSI_FLAG) 2549 pci_release_msi(dev); 2550 2551 if (sc->bce_res != NULL) 2552 bus_release_resource(dev, 2553 SYS_RES_MEMORY, 2554 PCIR_BAR(0), 2555 sc->bce_res); 2556 2557 if (sc->bce_ifp != NULL) 2558 if_free(sc->bce_ifp); 2559 2560 2561 if (mtx_initialized(&sc->bce_mtx)) 2562 BCE_LOCK_DESTROY(sc); 2563 2564 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 2565 2566} 2567 2568 2569/****************************************************************************/ 2570/* Firmware synchronization. */ 2571/* */ 2572/* Before performing certain events such as a chip reset, synchronize with */ 2573/* the firmware first. */ 2574/* */ 2575/* Returns: */ 2576/* 0 for success, positive value for failure. */ 2577/****************************************************************************/ 2578static int 2579bce_fw_sync(struct bce_softc *sc, u32 msg_data) 2580{ 2581 int i, rc = 0; 2582 u32 val; 2583 2584 /* Don't waste any time if we've timed out before. */ 2585 if (sc->bce_fw_timed_out) { 2586 rc = EBUSY; 2587 goto bce_fw_sync_exit; 2588 } 2589 2590 /* Increment the message sequence number. */ 2591 sc->bce_fw_wr_seq++; 2592 msg_data |= sc->bce_fw_wr_seq; 2593 2594 DBPRINT(sc, BCE_VERBOSE, "bce_fw_sync(): msg_data = 0x%08X\n", msg_data); 2595 2596 /* Send the message to the bootcode driver mailbox. */ 2597 REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_MB, msg_data); 2598 2599 /* Wait for the bootcode to acknowledge the message. */ 2600 for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) { 2601 /* Check for a response in the bootcode firmware mailbox. */ 2602 val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_FW_MB); 2603 if ((val & BCE_FW_MSG_ACK) == (msg_data & BCE_DRV_MSG_SEQ)) 2604 break; 2605 DELAY(1000); 2606 } 2607 2608 /* If we've timed out, tell the bootcode that we've stopped waiting. */ 2609 if (((val & BCE_FW_MSG_ACK) != (msg_data & BCE_DRV_MSG_SEQ)) && 2610 ((msg_data & BCE_DRV_MSG_DATA) != BCE_DRV_MSG_DATA_WAIT0)) { 2611 2612 BCE_PRINTF(sc, "%s(%d): Firmware synchronization timeout! " 2613 "msg_data = 0x%08X\n", 2614 __FILE__, __LINE__, msg_data); 2615 2616 msg_data &= ~BCE_DRV_MSG_CODE; 2617 msg_data |= BCE_DRV_MSG_CODE_FW_TIMEOUT; 2618 2619 REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_MB, msg_data); 2620 2621 sc->bce_fw_timed_out = 1; 2622 rc = EBUSY; 2623 } 2624 2625bce_fw_sync_exit: 2626 return (rc); 2627} 2628 2629 2630/****************************************************************************/ 2631/* Load Receive Virtual 2 Physical (RV2P) processor firmware. */ 2632/* */ 2633/* Returns: */ 2634/* Nothing. */ 2635/****************************************************************************/ 2636static void 2637bce_load_rv2p_fw(struct bce_softc *sc, u32 *rv2p_code, 2638 u32 rv2p_code_len, u32 rv2p_proc) 2639{ 2640 int i; 2641 u32 val; 2642 2643 for (i = 0; i < rv2p_code_len; i += 8) { 2644 REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code); 2645 rv2p_code++; 2646 REG_WR(sc, BCE_RV2P_INSTR_LOW, *rv2p_code); 2647 rv2p_code++; 2648 2649 if (rv2p_proc == RV2P_PROC1) { 2650 val = (i / 8) | BCE_RV2P_PROC1_ADDR_CMD_RDWR; 2651 REG_WR(sc, BCE_RV2P_PROC1_ADDR_CMD, val); 2652 } 2653 else { 2654 val = (i / 8) | BCE_RV2P_PROC2_ADDR_CMD_RDWR; 2655 REG_WR(sc, BCE_RV2P_PROC2_ADDR_CMD, val); 2656 } 2657 } 2658 2659 /* Reset the processor, un-stall is done later. */ 2660 if (rv2p_proc == RV2P_PROC1) { 2661 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET); 2662 } 2663 else { 2664 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET); 2665 } 2666} 2667 2668 2669/****************************************************************************/ 2670/* Load RISC processor firmware. */ 2671/* */ 2672/* Loads firmware from the file if_bcefw.h into the scratchpad memory */ 2673/* associated with a particular processor. */ 2674/* */ 2675/* Returns: */ 2676/* Nothing. */ 2677/****************************************************************************/ 2678static void 2679bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg, 2680 struct fw_info *fw) 2681{ 2682 u32 offset; 2683 u32 val; 2684 2685 /* Halt the CPU. */ 2686 val = REG_RD_IND(sc, cpu_reg->mode); 2687 val |= cpu_reg->mode_value_halt; 2688 REG_WR_IND(sc, cpu_reg->mode, val); 2689 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 2690 2691 /* Load the Text area. */ 2692 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base); 2693 if (fw->text) { 2694 int j; 2695 2696 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) { 2697 REG_WR_IND(sc, offset, fw->text[j]); 2698 } 2699 } 2700 2701 /* Load the Data area. */ 2702 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base); 2703 if (fw->data) { 2704 int j; 2705 2706 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) { 2707 REG_WR_IND(sc, offset, fw->data[j]); 2708 } 2709 } 2710 2711 /* Load the SBSS area. */ 2712 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base); 2713 if (fw->sbss) { 2714 int j; 2715 2716 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) { 2717 REG_WR_IND(sc, offset, fw->sbss[j]); 2718 } 2719 } 2720 2721 /* Load the BSS area. */ 2722 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base); 2723 if (fw->bss) { 2724 int j; 2725 2726 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) { 2727 REG_WR_IND(sc, offset, fw->bss[j]); 2728 } 2729 } 2730 2731 /* Load the Read-Only area. */ 2732 offset = cpu_reg->spad_base + 2733 (fw->rodata_addr - cpu_reg->mips_view_base); 2734 if (fw->rodata) { 2735 int j; 2736 2737 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) { 2738 REG_WR_IND(sc, offset, fw->rodata[j]); 2739 } 2740 } 2741 2742 /* Clear the pre-fetch instruction. */ 2743 REG_WR_IND(sc, cpu_reg->inst, 0); 2744 REG_WR_IND(sc, cpu_reg->pc, fw->start_addr); 2745 2746 /* Start the CPU. */ 2747 val = REG_RD_IND(sc, cpu_reg->mode); 2748 val &= ~cpu_reg->mode_value_halt; 2749 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 2750 REG_WR_IND(sc, cpu_reg->mode, val); 2751} 2752 2753 2754/****************************************************************************/ 2755/* Initialize the RV2P, RX, TX, TPAT, and COM CPUs. */ 2756/* */ 2757/* Loads the firmware for each CPU and starts the CPU. */ 2758/* */ 2759/* Returns: */ 2760/* Nothing. */ 2761/****************************************************************************/ 2762static void 2763bce_init_cpus(struct bce_softc *sc) 2764{ 2765 struct cpu_reg cpu_reg; 2766 struct fw_info fw; 2767 2768 /* Initialize the RV2P processor. */ 2769 bce_load_rv2p_fw(sc, bce_rv2p_proc1, sizeof(bce_rv2p_proc1), RV2P_PROC1); 2770 bce_load_rv2p_fw(sc, bce_rv2p_proc2, sizeof(bce_rv2p_proc2), RV2P_PROC2); 2771 2772 /* Initialize the RX Processor. */ 2773 cpu_reg.mode = BCE_RXP_CPU_MODE; 2774 cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT; 2775 cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA; 2776 cpu_reg.state = BCE_RXP_CPU_STATE; 2777 cpu_reg.state_value_clear = 0xffffff; 2778 cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE; 2779 cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK; 2780 cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER; 2781 cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION; 2782 cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT; 2783 cpu_reg.spad_base = BCE_RXP_SCRATCH; 2784 cpu_reg.mips_view_base = 0x8000000; 2785 2786 fw.ver_major = bce_RXP_b06FwReleaseMajor; 2787 fw.ver_minor = bce_RXP_b06FwReleaseMinor; 2788 fw.ver_fix = bce_RXP_b06FwReleaseFix; 2789 fw.start_addr = bce_RXP_b06FwStartAddr; 2790 2791 fw.text_addr = bce_RXP_b06FwTextAddr; 2792 fw.text_len = bce_RXP_b06FwTextLen; 2793 fw.text_index = 0; 2794 fw.text = bce_RXP_b06FwText; 2795 2796 fw.data_addr = bce_RXP_b06FwDataAddr; 2797 fw.data_len = bce_RXP_b06FwDataLen; 2798 fw.data_index = 0; 2799 fw.data = bce_RXP_b06FwData; 2800 2801 fw.sbss_addr = bce_RXP_b06FwSbssAddr; 2802 fw.sbss_len = bce_RXP_b06FwSbssLen; 2803 fw.sbss_index = 0; 2804 fw.sbss = bce_RXP_b06FwSbss; 2805 2806 fw.bss_addr = bce_RXP_b06FwBssAddr; 2807 fw.bss_len = bce_RXP_b06FwBssLen; 2808 fw.bss_index = 0; 2809 fw.bss = bce_RXP_b06FwBss; 2810 2811 fw.rodata_addr = bce_RXP_b06FwRodataAddr; 2812 fw.rodata_len = bce_RXP_b06FwRodataLen; 2813 fw.rodata_index = 0; 2814 fw.rodata = bce_RXP_b06FwRodata; 2815 2816 DBPRINT(sc, BCE_INFO_RESET, "Loading RX firmware.\n"); 2817 bce_load_cpu_fw(sc, &cpu_reg, &fw); 2818 2819 /* Initialize the TX Processor. */ 2820 cpu_reg.mode = BCE_TXP_CPU_MODE; 2821 cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT; 2822 cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA; 2823 cpu_reg.state = BCE_TXP_CPU_STATE; 2824 cpu_reg.state_value_clear = 0xffffff; 2825 cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE; 2826 cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK; 2827 cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER; 2828 cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION; 2829 cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT; 2830 cpu_reg.spad_base = BCE_TXP_SCRATCH; 2831 cpu_reg.mips_view_base = 0x8000000; 2832 2833 fw.ver_major = bce_TXP_b06FwReleaseMajor; 2834 fw.ver_minor = bce_TXP_b06FwReleaseMinor; 2835 fw.ver_fix = bce_TXP_b06FwReleaseFix; 2836 fw.start_addr = bce_TXP_b06FwStartAddr; 2837 2838 fw.text_addr = bce_TXP_b06FwTextAddr; 2839 fw.text_len = bce_TXP_b06FwTextLen; 2840 fw.text_index = 0; 2841 fw.text = bce_TXP_b06FwText; 2842 2843 fw.data_addr = bce_TXP_b06FwDataAddr; 2844 fw.data_len = bce_TXP_b06FwDataLen; 2845 fw.data_index = 0; 2846 fw.data = bce_TXP_b06FwData; 2847 2848 fw.sbss_addr = bce_TXP_b06FwSbssAddr; 2849 fw.sbss_len = bce_TXP_b06FwSbssLen; 2850 fw.sbss_index = 0; 2851 fw.sbss = bce_TXP_b06FwSbss; 2852 2853 fw.bss_addr = bce_TXP_b06FwBssAddr; 2854 fw.bss_len = bce_TXP_b06FwBssLen; 2855 fw.bss_index = 0; 2856 fw.bss = bce_TXP_b06FwBss; 2857 2858 fw.rodata_addr = bce_TXP_b06FwRodataAddr; 2859 fw.rodata_len = bce_TXP_b06FwRodataLen; 2860 fw.rodata_index = 0; 2861 fw.rodata = bce_TXP_b06FwRodata; 2862 2863 DBPRINT(sc, BCE_INFO_RESET, "Loading TX firmware.\n"); 2864 bce_load_cpu_fw(sc, &cpu_reg, &fw); 2865 2866 /* Initialize the TX Patch-up Processor. */ 2867 cpu_reg.mode = BCE_TPAT_CPU_MODE; 2868 cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT; 2869 cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA; 2870 cpu_reg.state = BCE_TPAT_CPU_STATE; 2871 cpu_reg.state_value_clear = 0xffffff; 2872 cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE; 2873 cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK; 2874 cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER; 2875 cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION; 2876 cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT; 2877 cpu_reg.spad_base = BCE_TPAT_SCRATCH; 2878 cpu_reg.mips_view_base = 0x8000000; 2879 2880 fw.ver_major = bce_TPAT_b06FwReleaseMajor; 2881 fw.ver_minor = bce_TPAT_b06FwReleaseMinor; 2882 fw.ver_fix = bce_TPAT_b06FwReleaseFix; 2883 fw.start_addr = bce_TPAT_b06FwStartAddr; 2884 2885 fw.text_addr = bce_TPAT_b06FwTextAddr; 2886 fw.text_len = bce_TPAT_b06FwTextLen; 2887 fw.text_index = 0; 2888 fw.text = bce_TPAT_b06FwText; 2889 2890 fw.data_addr = bce_TPAT_b06FwDataAddr; 2891 fw.data_len = bce_TPAT_b06FwDataLen; 2892 fw.data_index = 0; 2893 fw.data = bce_TPAT_b06FwData; 2894 2895 fw.sbss_addr = bce_TPAT_b06FwSbssAddr; 2896 fw.sbss_len = bce_TPAT_b06FwSbssLen; 2897 fw.sbss_index = 0; 2898 fw.sbss = bce_TPAT_b06FwSbss; 2899 2900 fw.bss_addr = bce_TPAT_b06FwBssAddr; 2901 fw.bss_len = bce_TPAT_b06FwBssLen; 2902 fw.bss_index = 0; 2903 fw.bss = bce_TPAT_b06FwBss; 2904 2905 fw.rodata_addr = bce_TPAT_b06FwRodataAddr; 2906 fw.rodata_len = bce_TPAT_b06FwRodataLen; 2907 fw.rodata_index = 0; 2908 fw.rodata = bce_TPAT_b06FwRodata; 2909 2910 DBPRINT(sc, BCE_INFO_RESET, "Loading TPAT firmware.\n"); 2911 bce_load_cpu_fw(sc, &cpu_reg, &fw); 2912 2913 /* Initialize the Completion Processor. */ 2914 cpu_reg.mode = BCE_COM_CPU_MODE; 2915 cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT; 2916 cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA; 2917 cpu_reg.state = BCE_COM_CPU_STATE; 2918 cpu_reg.state_value_clear = 0xffffff; 2919 cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE; 2920 cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK; 2921 cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER; 2922 cpu_reg.inst = BCE_COM_CPU_INSTRUCTION; 2923 cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT; 2924 cpu_reg.spad_base = BCE_COM_SCRATCH; 2925 cpu_reg.mips_view_base = 0x8000000; 2926 2927 fw.ver_major = bce_COM_b06FwReleaseMajor; 2928 fw.ver_minor = bce_COM_b06FwReleaseMinor; 2929 fw.ver_fix = bce_COM_b06FwReleaseFix; 2930 fw.start_addr = bce_COM_b06FwStartAddr; 2931 2932 fw.text_addr = bce_COM_b06FwTextAddr; 2933 fw.text_len = bce_COM_b06FwTextLen; 2934 fw.text_index = 0; 2935 fw.text = bce_COM_b06FwText; 2936 2937 fw.data_addr = bce_COM_b06FwDataAddr; 2938 fw.data_len = bce_COM_b06FwDataLen; 2939 fw.data_index = 0; 2940 fw.data = bce_COM_b06FwData; 2941 2942 fw.sbss_addr = bce_COM_b06FwSbssAddr; 2943 fw.sbss_len = bce_COM_b06FwSbssLen; 2944 fw.sbss_index = 0; 2945 fw.sbss = bce_COM_b06FwSbss; 2946 2947 fw.bss_addr = bce_COM_b06FwBssAddr; 2948 fw.bss_len = bce_COM_b06FwBssLen; 2949 fw.bss_index = 0; 2950 fw.bss = bce_COM_b06FwBss; 2951 2952 fw.rodata_addr = bce_COM_b06FwRodataAddr; 2953 fw.rodata_len = bce_COM_b06FwRodataLen; 2954 fw.rodata_index = 0; 2955 fw.rodata = bce_COM_b06FwRodata; 2956 2957 DBPRINT(sc, BCE_INFO_RESET, "Loading COM firmware.\n"); 2958 bce_load_cpu_fw(sc, &cpu_reg, &fw); 2959} 2960 2961 2962/****************************************************************************/ 2963/* Initialize context memory. */ 2964/* */ 2965/* Clears the memory associated with each Context ID (CID). */ 2966/* */ 2967/* Returns: */ 2968/* Nothing. */ 2969/****************************************************************************/ 2970static void 2971bce_init_context(struct bce_softc *sc) 2972{ 2973 u32 vcid; 2974 2975 vcid = 96; 2976 while (vcid) { 2977 u32 vcid_addr, pcid_addr, offset; 2978 2979 vcid--; 2980 2981 vcid_addr = GET_CID_ADDR(vcid); 2982 pcid_addr = vcid_addr; 2983 2984 REG_WR(sc, BCE_CTX_VIRT_ADDR, 0x00); 2985 REG_WR(sc, BCE_CTX_PAGE_TBL, pcid_addr); 2986 2987 /* Zero out the context. */ 2988 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4) { 2989 CTX_WR(sc, 0x00, offset, 0); 2990 } 2991 2992 REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr); 2993 REG_WR(sc, BCE_CTX_PAGE_TBL, pcid_addr); 2994 } 2995} 2996 2997 2998/****************************************************************************/ 2999/* Fetch the permanent MAC address of the controller. */ 3000/* */ 3001/* Returns: */ 3002/* Nothing. */ 3003/****************************************************************************/ 3004static void 3005bce_get_mac_addr(struct bce_softc *sc) 3006{ 3007 u32 mac_lo = 0, mac_hi = 0; 3008 3009 /* 3010 * The NetXtreme II bootcode populates various NIC 3011 * power-on and runtime configuration items in a 3012 * shared memory area. The factory configured MAC 3013 * address is available from both NVRAM and the 3014 * shared memory area so we'll read the value from 3015 * shared memory for speed. 3016 */ 3017 3018 mac_hi = REG_RD_IND(sc, sc->bce_shmem_base + 3019 BCE_PORT_HW_CFG_MAC_UPPER); 3020 mac_lo = REG_RD_IND(sc, sc->bce_shmem_base + 3021 BCE_PORT_HW_CFG_MAC_LOWER); 3022 3023 if ((mac_lo == 0) && (mac_hi == 0)) { 3024 BCE_PRINTF(sc, "%s(%d): Invalid Ethernet address!\n", 3025 __FILE__, __LINE__); 3026 } else { 3027 sc->eaddr[0] = (u_char)(mac_hi >> 8); 3028 sc->eaddr[1] = (u_char)(mac_hi >> 0); 3029 sc->eaddr[2] = (u_char)(mac_lo >> 24); 3030 sc->eaddr[3] = (u_char)(mac_lo >> 16); 3031 sc->eaddr[4] = (u_char)(mac_lo >> 8); 3032 sc->eaddr[5] = (u_char)(mac_lo >> 0); 3033 } 3034 3035 DBPRINT(sc, BCE_INFO, "Permanent Ethernet address = %6D\n", sc->eaddr, ":"); 3036} 3037 3038 3039/****************************************************************************/ 3040/* Program the MAC address. */ 3041/* */ 3042/* Returns: */ 3043/* Nothing. */ 3044/****************************************************************************/ 3045static void 3046bce_set_mac_addr(struct bce_softc *sc) 3047{ 3048 u32 val; 3049 u8 *mac_addr = sc->eaddr; 3050 3051 DBPRINT(sc, BCE_INFO, "Setting Ethernet address = %6D\n", sc->eaddr, ":"); 3052 3053 val = (mac_addr[0] << 8) | mac_addr[1]; 3054 3055 REG_WR(sc, BCE_EMAC_MAC_MATCH0, val); 3056 3057 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 3058 (mac_addr[4] << 8) | mac_addr[5]; 3059 3060 REG_WR(sc, BCE_EMAC_MAC_MATCH1, val); 3061} 3062 3063 3064/****************************************************************************/ 3065/* Stop the controller. */ 3066/* */ 3067/* Returns: */ 3068/* Nothing. */ 3069/****************************************************************************/ 3070static void 3071bce_stop(struct bce_softc *sc) 3072{ 3073 struct ifnet *ifp; 3074 struct ifmedia_entry *ifm; 3075 struct mii_data *mii = NULL; 3076 int mtmp, itmp; 3077 3078 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 3079 3080 BCE_LOCK_ASSERT(sc); 3081 3082 ifp = sc->bce_ifp; 3083 3084 mii = device_get_softc(sc->bce_miibus); 3085 3086 callout_stop(&sc->bce_stat_ch); 3087 3088 /* Disable the transmit/receive blocks. */ 3089 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, 0x5ffffff); 3090 REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS); 3091 DELAY(20); 3092 3093 bce_disable_intr(sc); 3094 3095 /* Tell firmware that the driver is going away. */ 3096 bce_reset(sc, BCE_DRV_MSG_CODE_SUSPEND_NO_WOL); 3097 3098 /* Free the RX lists. */ 3099 bce_free_rx_chain(sc); 3100 3101 /* Free TX buffers. */ 3102 bce_free_tx_chain(sc); 3103 3104 /* 3105 * Isolate/power down the PHY, but leave the media selection 3106 * unchanged so that things will be put back to normal when 3107 * we bring the interface back up. 3108 */ 3109 3110 itmp = ifp->if_flags; 3111 ifp->if_flags |= IFF_UP; 3112 /* 3113 * If we are called from bce_detach(), mii is already NULL. 3114 */ 3115 if (mii != NULL) { 3116 ifm = mii->mii_media.ifm_cur; 3117 mtmp = ifm->ifm_media; 3118 ifm->ifm_media = IFM_ETHER | IFM_NONE; 3119 mii_mediachg(mii); 3120 ifm->ifm_media = mtmp; 3121 } 3122 3123 ifp->if_flags = itmp; 3124 sc->watchdog_timer = 0; 3125 3126 sc->bce_link = 0; 3127 3128 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3129 3130 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 3131 3132 bce_mgmt_init_locked(sc); 3133} 3134 3135 3136static int 3137bce_reset(struct bce_softc *sc, u32 reset_code) 3138{ 3139 u32 val; 3140 int i, rc = 0; 3141 3142 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 3143 3144 /* Wait for pending PCI transactions to complete. */ 3145 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, 3146 BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE | 3147 BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE | 3148 BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE | 3149 BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE); 3150 val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS); 3151 DELAY(5); 3152 3153 /* Assume bootcode is running. */ 3154 sc->bce_fw_timed_out = 0; 3155 3156 /* Give the firmware a chance to prepare for the reset. */ 3157 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT0 | reset_code); 3158 if (rc) 3159 goto bce_reset_exit; 3160 3161 /* Set a firmware reminder that this is a soft reset. */ 3162 REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_RESET_SIGNATURE, 3163 BCE_DRV_RESET_SIGNATURE_MAGIC); 3164 3165 /* Dummy read to force the chip to complete all current transactions. */ 3166 val = REG_RD(sc, BCE_MISC_ID); 3167 3168 /* Chip reset. */ 3169 val = BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 3170 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 3171 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 3172 REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val); 3173 3174 /* Allow up to 30us for reset to complete. */ 3175 for (i = 0; i < 10; i++) { 3176 val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG); 3177 if ((val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 3178 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) { 3179 break; 3180 } 3181 DELAY(10); 3182 } 3183 3184 /* Check that reset completed successfully. */ 3185 if (val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 3186 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) { 3187 BCE_PRINTF(sc, "%s(%d): Reset failed!\n", 3188 __FILE__, __LINE__); 3189 rc = EBUSY; 3190 goto bce_reset_exit; 3191 } 3192 3193 /* Make sure byte swapping is properly configured. */ 3194 val = REG_RD(sc, BCE_PCI_SWAP_DIAG0); 3195 if (val != 0x01020304) { 3196 BCE_PRINTF(sc, "%s(%d): Byte swap is incorrect!\n", 3197 __FILE__, __LINE__); 3198 rc = ENODEV; 3199 goto bce_reset_exit; 3200 } 3201 3202 /* Just completed a reset, assume that firmware is running again. */ 3203 sc->bce_fw_timed_out = 0; 3204 3205 /* Wait for the firmware to finish its initialization. */ 3206 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT1 | reset_code); 3207 if (rc) 3208 BCE_PRINTF(sc, "%s(%d): Firmware did not complete initialization!\n", 3209 __FILE__, __LINE__); 3210 3211bce_reset_exit: 3212 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 3213 3214 return (rc); 3215} 3216 3217 3218static int 3219bce_chipinit(struct bce_softc *sc) 3220{ 3221 u32 val; 3222 int rc = 0; 3223 3224 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 3225 3226 /* Make sure the interrupt is not active. */ 3227 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT); 3228 3229 /* Initialize DMA byte/word swapping, configure the number of DMA */ 3230 /* channels and PCI clock compensation delay. */ 3231 val = BCE_DMA_CONFIG_DATA_BYTE_SWAP | 3232 BCE_DMA_CONFIG_DATA_WORD_SWAP | 3233#if BYTE_ORDER == BIG_ENDIAN 3234 BCE_DMA_CONFIG_CNTL_BYTE_SWAP | 3235#endif 3236 BCE_DMA_CONFIG_CNTL_WORD_SWAP | 3237 DMA_READ_CHANS << 12 | 3238 DMA_WRITE_CHANS << 16; 3239 3240 val |= (0x2 << 20) | BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY; 3241 3242 if ((sc->bce_flags & BCE_PCIX_FLAG) && (sc->bus_speed_mhz == 133)) 3243 val |= BCE_DMA_CONFIG_PCI_FAST_CLK_CMP; 3244 3245 /* 3246 * This setting resolves a problem observed on certain Intel PCI 3247 * chipsets that cannot handle multiple outstanding DMA operations. 3248 * See errata E9_5706A1_65. 3249 */ 3250 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) && 3251 (BCE_CHIP_ID(sc) != BCE_CHIP_ID_5706_A0) && 3252 !(sc->bce_flags & BCE_PCIX_FLAG)) 3253 val |= BCE_DMA_CONFIG_CNTL_PING_PONG_DMA; 3254 3255 REG_WR(sc, BCE_DMA_CONFIG, val); 3256 3257 /* Clear the PCI-X relaxed ordering bit. See errata E3_5708CA0_570. */ 3258 if (sc->bce_flags & BCE_PCIX_FLAG) { 3259 u16 val; 3260 3261 val = pci_read_config(sc->bce_dev, BCE_PCI_PCIX_CMD, 2); 3262 pci_write_config(sc->bce_dev, BCE_PCI_PCIX_CMD, val & ~0x2, 2); 3263 } 3264 3265 /* Enable the RX_V2P and Context state machines before access. */ 3266 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 3267 BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE | 3268 BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE | 3269 BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE); 3270 3271 /* Initialize context mapping and zero out the quick contexts. */ 3272 bce_init_context(sc); 3273 3274 /* Initialize the on-boards CPUs */ 3275 bce_init_cpus(sc); 3276 3277 /* Prepare NVRAM for access. */ 3278 if (bce_init_nvram(sc)) { 3279 rc = ENODEV; 3280 goto bce_chipinit_exit; 3281 } 3282 3283 /* Set the kernel bypass block size */ 3284 val = REG_RD(sc, BCE_MQ_CONFIG); 3285 val &= ~BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE; 3286 val |= BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256; 3287 REG_WR(sc, BCE_MQ_CONFIG, val); 3288 3289 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE); 3290 REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val); 3291 REG_WR(sc, BCE_MQ_KNL_WIND_END, val); 3292 3293 val = (BCM_PAGE_BITS - 8) << 24; 3294 REG_WR(sc, BCE_RV2P_CONFIG, val); 3295 3296 /* Configure page size. */ 3297 val = REG_RD(sc, BCE_TBDR_CONFIG); 3298 val &= ~BCE_TBDR_CONFIG_PAGE_SIZE; 3299 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40; 3300 REG_WR(sc, BCE_TBDR_CONFIG, val); 3301 3302bce_chipinit_exit: 3303 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 3304 3305 return(rc); 3306} 3307 3308 3309/****************************************************************************/ 3310/* Initialize the controller in preparation to send/receive traffic. */ 3311/* */ 3312/* Returns: */ 3313/* 0 for success, positive value for failure. */ 3314/****************************************************************************/ 3315static int 3316bce_blockinit(struct bce_softc *sc) 3317{ 3318 u32 reg, val; 3319 int rc = 0; 3320 3321 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 3322 3323 /* Load the hardware default MAC address. */ 3324 bce_set_mac_addr(sc); 3325 3326 /* Set the Ethernet backoff seed value */ 3327 val = sc->eaddr[0] + (sc->eaddr[1] << 8) + 3328 (sc->eaddr[2] << 16) + (sc->eaddr[3] ) + 3329 (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16); 3330 REG_WR(sc, BCE_EMAC_BACKOFF_SEED, val); 3331 3332 sc->last_status_idx = 0; 3333 sc->rx_mode = BCE_EMAC_RX_MODE_SORT_MODE; 3334 3335 /* Set up link change interrupt generation. */ 3336 REG_WR(sc, BCE_EMAC_ATTENTION_ENA, BCE_EMAC_ATTENTION_ENA_LINK); 3337 3338 /* Program the physical address of the status block. */ 3339 REG_WR(sc, BCE_HC_STATUS_ADDR_L, 3340 BCE_ADDR_LO(sc->status_block_paddr)); 3341 REG_WR(sc, BCE_HC_STATUS_ADDR_H, 3342 BCE_ADDR_HI(sc->status_block_paddr)); 3343 3344 /* Program the physical address of the statistics block. */ 3345 REG_WR(sc, BCE_HC_STATISTICS_ADDR_L, 3346 BCE_ADDR_LO(sc->stats_block_paddr)); 3347 REG_WR(sc, BCE_HC_STATISTICS_ADDR_H, 3348 BCE_ADDR_HI(sc->stats_block_paddr)); 3349 3350 /* Program various host coalescing parameters. */ 3351 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP, 3352 (sc->bce_tx_quick_cons_trip_int << 16) | sc->bce_tx_quick_cons_trip); 3353 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP, 3354 (sc->bce_rx_quick_cons_trip_int << 16) | sc->bce_rx_quick_cons_trip); 3355 REG_WR(sc, BCE_HC_COMP_PROD_TRIP, 3356 (sc->bce_comp_prod_trip_int << 16) | sc->bce_comp_prod_trip); 3357 REG_WR(sc, BCE_HC_TX_TICKS, 3358 (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks); 3359 REG_WR(sc, BCE_HC_RX_TICKS, 3360 (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks); 3361 REG_WR(sc, BCE_HC_COM_TICKS, 3362 (sc->bce_com_ticks_int << 16) | sc->bce_com_ticks); 3363 REG_WR(sc, BCE_HC_CMD_TICKS, 3364 (sc->bce_cmd_ticks_int << 16) | sc->bce_cmd_ticks); 3365 REG_WR(sc, BCE_HC_STATS_TICKS, 3366 (sc->bce_stats_ticks & 0xffff00)); 3367 REG_WR(sc, BCE_HC_STAT_COLLECT_TICKS, 3368 0xbb8); /* 3ms */ 3369 REG_WR(sc, BCE_HC_CONFIG, 3370 (BCE_HC_CONFIG_RX_TMR_MODE | BCE_HC_CONFIG_TX_TMR_MODE | 3371 BCE_HC_CONFIG_COLLECT_STATS)); 3372 3373 /* Clear the internal statistics counters. */ 3374 REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW); 3375 3376 /* Verify that bootcode is running. */ 3377 reg = REG_RD_IND(sc, sc->bce_shmem_base + BCE_DEV_INFO_SIGNATURE); 3378 3379 DBRUNIF(DB_RANDOMTRUE(bce_debug_bootcode_running_failure), 3380 BCE_PRINTF(sc, "%s(%d): Simulating bootcode failure.\n", 3381 __FILE__, __LINE__); 3382 reg = 0); 3383 3384 if ((reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK) != 3385 BCE_DEV_INFO_SIGNATURE_MAGIC) { 3386 BCE_PRINTF(sc, "%s(%d): Bootcode not running! Found: 0x%08X, " 3387 "Expected: 08%08X\n", __FILE__, __LINE__, 3388 (reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK), 3389 BCE_DEV_INFO_SIGNATURE_MAGIC); 3390 rc = ENODEV; 3391 goto bce_blockinit_exit; 3392 } 3393 3394 /* Check if any management firmware is running. */ 3395 reg = REG_RD_IND(sc, sc->bce_shmem_base + BCE_PORT_FEATURE); 3396 if (reg & (BCE_PORT_FEATURE_ASF_ENABLED | BCE_PORT_FEATURE_IMD_ENABLED)) { 3397 DBPRINT(sc, BCE_INFO, "Management F/W Enabled.\n"); 3398 sc->bce_flags |= BCE_MFW_ENABLE_FLAG; 3399 } 3400 3401 sc->bce_fw_ver = REG_RD_IND(sc, sc->bce_shmem_base + BCE_DEV_INFO_BC_REV); 3402 DBPRINT(sc, BCE_INFO, "bootcode rev = 0x%08X\n", sc->bce_fw_ver); 3403 3404 /* Allow bootcode to apply any additional fixes before enabling MAC. */ 3405 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT2 | BCE_DRV_MSG_CODE_RESET); 3406 3407 /* Enable link state change interrupt generation. */ 3408 REG_WR(sc, BCE_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE); 3409 3410 /* Enable all remaining blocks in the MAC. */ 3411 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 0x5ffffff); 3412 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS); 3413 DELAY(20); 3414 3415bce_blockinit_exit: 3416 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 3417 3418 return (rc); 3419} 3420 3421 3422/****************************************************************************/ 3423/* Encapsulate an mbuf cluster into the rx_bd chain. */ 3424/* */ 3425/* The NetXtreme II can support Jumbo frames by using multiple rx_bd's. */ 3426/* This routine will map an mbuf cluster into 1 or more rx_bd's as */ 3427/* necessary. */ 3428/* */ 3429/* Returns: */ 3430/* 0 for success, positive value for failure. */ 3431/****************************************************************************/ 3432static int 3433bce_get_buf(struct bce_softc *sc, struct mbuf *m, u16 *prod, u16 *chain_prod, 3434 u32 *prod_bseq) 3435{ 3436 bus_dmamap_t map; 3437 bus_dma_segment_t segs[4]; 3438 struct mbuf *m_new = NULL; 3439 struct rx_bd *rxbd; 3440 int i, nsegs, error, rc = 0; 3441#ifdef BCE_DEBUG 3442 u16 debug_chain_prod = *chain_prod; 3443#endif 3444 3445 DBPRINT(sc, (BCE_VERBOSE_RESET | BCE_VERBOSE_RECV), "Entering %s()\n", 3446 __FUNCTION__); 3447 3448 /* Make sure the inputs are valid. */ 3449 DBRUNIF((*chain_prod > MAX_RX_BD), 3450 BCE_PRINTF(sc, "%s(%d): RX producer out of range: 0x%04X > 0x%04X\n", 3451 __FILE__, __LINE__, *chain_prod, (u16) MAX_RX_BD)); 3452 3453 DBPRINT(sc, BCE_VERBOSE_RECV, "%s(enter): prod = 0x%04X, chain_prod = 0x%04X, " 3454 "prod_bseq = 0x%08X\n", __FUNCTION__, *prod, *chain_prod, *prod_bseq); 3455 3456 if (m == NULL) { 3457 3458 DBRUNIF(DB_RANDOMTRUE(bce_debug_mbuf_allocation_failure), 3459 BCE_PRINTF(sc, "%s(%d): Simulating mbuf allocation failure.\n", 3460 __FILE__, __LINE__); 3461 sc->mbuf_alloc_failed++; 3462 rc = ENOBUFS; 3463 goto bce_get_buf_exit); 3464 3465 /* This is a new mbuf allocation. */ 3466 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 3467 if (m_new == NULL) { 3468 3469 DBPRINT(sc, BCE_WARN, "%s(%d): RX mbuf header allocation failed!\n", 3470 __FILE__, __LINE__); 3471 3472 DBRUNIF(1, sc->mbuf_alloc_failed++); 3473 3474 rc = ENOBUFS; 3475 goto bce_get_buf_exit; 3476 } 3477 3478 DBRUNIF(1, sc->rx_mbuf_alloc++); 3479 m_cljget(m_new, M_DONTWAIT, sc->mbuf_alloc_size); 3480 if (!(m_new->m_flags & M_EXT)) { 3481 3482 DBPRINT(sc, BCE_WARN, "%s(%d): RX mbuf chain allocation failed!\n", 3483 __FILE__, __LINE__); 3484 3485 m_freem(m_new); 3486 3487 DBRUNIF(1, sc->rx_mbuf_alloc--); 3488 DBRUNIF(1, sc->mbuf_alloc_failed++); 3489 3490 rc = ENOBUFS; 3491 goto bce_get_buf_exit; 3492 } 3493 3494 m_new->m_len = m_new->m_pkthdr.len = sc->mbuf_alloc_size; 3495 } else { 3496 m_new = m; 3497 m_new->m_len = m_new->m_pkthdr.len = sc->mbuf_alloc_size; 3498 m_new->m_data = m_new->m_ext.ext_buf; 3499 } 3500 3501 /* Map the mbuf cluster into device memory. */ 3502 map = sc->rx_mbuf_map[*chain_prod]; 3503 error = bus_dmamap_load_mbuf_sg(sc->rx_mbuf_tag, map, m_new, 3504 segs, &nsegs, BUS_DMA_NOWAIT); 3505 3506 if (error) { 3507 BCE_PRINTF(sc, "%s(%d): Error mapping mbuf into RX chain!\n", 3508 __FILE__, __LINE__); 3509 3510 m_freem(m_new); 3511 3512 DBRUNIF(1, sc->rx_mbuf_alloc--); 3513 3514 rc = ENOBUFS; 3515 goto bce_get_buf_exit; 3516 } 3517 3518 /* Watch for overflow. */ 3519 DBRUNIF((sc->free_rx_bd > USABLE_RX_BD), 3520 BCE_PRINTF(sc, "%s(%d): Too many free rx_bd (0x%04X > 0x%04X)!\n", 3521 __FILE__, __LINE__, sc->free_rx_bd, (u16) USABLE_RX_BD)); 3522 3523 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 3524 sc->rx_low_watermark = sc->free_rx_bd); 3525 3526 /* Setup the rx_bd for the first segment. */ 3527 rxbd = &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)]; 3528 3529 rxbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[0].ds_addr)); 3530 rxbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[0].ds_addr)); 3531 rxbd->rx_bd_len = htole32(segs[0].ds_len); 3532 rxbd->rx_bd_flags = htole32(RX_BD_FLAGS_START); 3533 *prod_bseq += segs[0].ds_len; 3534 3535 for (i = 1; i < nsegs; i++) { 3536 3537 *prod = NEXT_RX_BD(*prod); 3538 *chain_prod = RX_CHAIN_IDX(*prod); 3539 3540 rxbd = &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)]; 3541 3542 rxbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[i].ds_addr)); 3543 rxbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[i].ds_addr)); 3544 rxbd->rx_bd_len = htole32(segs[i].ds_len); 3545 rxbd->rx_bd_flags = 0; 3546 *prod_bseq += segs[i].ds_len; 3547 } 3548 3549 rxbd->rx_bd_flags |= htole32(RX_BD_FLAGS_END); 3550 3551 /* Save the mbuf and update our counter. */ 3552 sc->rx_mbuf_ptr[*chain_prod] = m_new; 3553 sc->free_rx_bd -= nsegs; 3554 3555 DBRUN(BCE_VERBOSE_RECV, bce_dump_rx_mbuf_chain(sc, debug_chain_prod, 3556 nsegs)); 3557 3558 DBPRINT(sc, BCE_VERBOSE_RECV, "%s(exit): prod = 0x%04X, chain_prod = 0x%04X, " 3559 "prod_bseq = 0x%08X\n", __FUNCTION__, *prod, *chain_prod, *prod_bseq); 3560 3561bce_get_buf_exit: 3562 DBPRINT(sc, (BCE_VERBOSE_RESET | BCE_VERBOSE_RECV), "Exiting %s()\n", 3563 __FUNCTION__); 3564 3565 return(rc); 3566} 3567 3568 3569/****************************************************************************/ 3570/* Allocate memory and initialize the TX data structures. */ 3571/* */ 3572/* Returns: */ 3573/* 0 for success, positive value for failure. */ 3574/****************************************************************************/ 3575static int 3576bce_init_tx_chain(struct bce_softc *sc) 3577{ 3578 struct tx_bd *txbd; 3579 u32 val; 3580 int i, rc = 0; 3581 3582 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 3583 3584 /* Set the initial TX producer/consumer indices. */ 3585 sc->tx_prod = 0; 3586 sc->tx_cons = 0; 3587 sc->tx_prod_bseq = 0; 3588 sc->used_tx_bd = 0; 3589 DBRUNIF(1, sc->tx_hi_watermark = USABLE_TX_BD); 3590 3591 /* 3592 * The NetXtreme II supports a linked-list structre called 3593 * a Buffer Descriptor Chain (or BD chain). A BD chain 3594 * consists of a series of 1 or more chain pages, each of which 3595 * consists of a fixed number of BD entries. 3596 * The last BD entry on each page is a pointer to the next page 3597 * in the chain, and the last pointer in the BD chain 3598 * points back to the beginning of the chain. 3599 */ 3600 3601 /* Set the TX next pointer chain entries. */ 3602 for (i = 0; i < TX_PAGES; i++) { 3603 int j; 3604 3605 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE]; 3606 3607 /* Check if we've reached the last page. */ 3608 if (i == (TX_PAGES - 1)) 3609 j = 0; 3610 else 3611 j = i + 1; 3612 3613 txbd->tx_bd_haddr_hi = htole32(BCE_ADDR_HI(sc->tx_bd_chain_paddr[j])); 3614 txbd->tx_bd_haddr_lo = htole32(BCE_ADDR_LO(sc->tx_bd_chain_paddr[j])); 3615 } 3616 3617 /* 3618 * Initialize the context ID for an L2 TX chain. 3619 */ 3620 val = BCE_L2CTX_TYPE_TYPE_L2; 3621 val |= BCE_L2CTX_TYPE_SIZE_L2; 3622 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TYPE, val); 3623 3624 val = BCE_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16); 3625 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_CMD_TYPE, val); 3626 3627 /* Point the hardware to the first page in the chain. */ 3628 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]); 3629 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TBDR_BHADDR_HI, val); 3630 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]); 3631 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TBDR_BHADDR_LO, val); 3632 3633 DBRUN(BCE_VERBOSE_SEND, bce_dump_tx_chain(sc, 0, TOTAL_TX_BD)); 3634 3635 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 3636 3637 return(rc); 3638} 3639 3640 3641/****************************************************************************/ 3642/* Free memory and clear the TX data structures. */ 3643/* */ 3644/* Returns: */ 3645/* Nothing. */ 3646/****************************************************************************/ 3647static void 3648bce_free_tx_chain(struct bce_softc *sc) 3649{ 3650 int i; 3651 3652 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 3653 3654 /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */ 3655 for (i = 0; i < TOTAL_TX_BD; i++) { 3656 if (sc->tx_mbuf_ptr[i] != NULL) { 3657 if (sc->tx_mbuf_map != NULL) 3658 bus_dmamap_sync(sc->tx_mbuf_tag, sc->tx_mbuf_map[i], 3659 BUS_DMASYNC_POSTWRITE); 3660 m_freem(sc->tx_mbuf_ptr[i]); 3661 sc->tx_mbuf_ptr[i] = NULL; 3662 DBRUNIF(1, sc->tx_mbuf_alloc--); 3663 } 3664 } 3665 3666 /* Clear each TX chain page. */ 3667 for (i = 0; i < TX_PAGES; i++) 3668 bzero((char *)sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ); 3669 3670 /* Check if we lost any mbufs in the process. */ 3671 DBRUNIF((sc->tx_mbuf_alloc), 3672 BCE_PRINTF(sc, "%s(%d): Memory leak! Lost %d mbufs " 3673 "from tx chain!\n", 3674 __FILE__, __LINE__, sc->tx_mbuf_alloc)); 3675 3676 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 3677} 3678 3679 3680/****************************************************************************/ 3681/* Allocate memory and initialize the RX data structures. */ 3682/* */ 3683/* Returns: */ 3684/* 0 for success, positive value for failure. */ 3685/****************************************************************************/ 3686static int 3687bce_init_rx_chain(struct bce_softc *sc) 3688{ 3689 struct rx_bd *rxbd; 3690 int i, rc = 0; 3691 u16 prod, chain_prod; 3692 u32 prod_bseq, val; 3693 3694 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 3695 3696 /* Initialize the RX producer and consumer indices. */ 3697 sc->rx_prod = 0; 3698 sc->rx_cons = 0; 3699 sc->rx_prod_bseq = 0; 3700 sc->free_rx_bd = BCE_RX_SLACK_SPACE; 3701 DBRUNIF(1, sc->rx_low_watermark = USABLE_RX_BD); 3702 3703 /* Initialize the RX next pointer chain entries. */ 3704 for (i = 0; i < RX_PAGES; i++) { 3705 int j; 3706 3707 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE]; 3708 3709 /* Check if we've reached the last page. */ 3710 if (i == (RX_PAGES - 1)) 3711 j = 0; 3712 else 3713 j = i + 1; 3714 3715 /* Setup the chain page pointers. */ 3716 rxbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(sc->rx_bd_chain_paddr[j])); 3717 rxbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(sc->rx_bd_chain_paddr[j])); 3718 } 3719 3720 /* Initialize the context ID for an L2 RX chain. */ 3721 val = BCE_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE; 3722 val |= BCE_L2CTX_CTX_TYPE_SIZE_L2; 3723 val |= 0x02 << 8; 3724 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_CTX_TYPE, val); 3725 3726 /* Point the hardware to the first page in the chain. */ 3727 val = BCE_ADDR_HI(sc->rx_bd_chain_paddr[0]); 3728 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_NX_BDHADDR_HI, val); 3729 val = BCE_ADDR_LO(sc->rx_bd_chain_paddr[0]); 3730 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_NX_BDHADDR_LO, val); 3731 3732 /* Allocate mbuf clusters for the rx_bd chain. */ 3733 prod = prod_bseq = 0; 3734 while (prod < BCE_RX_SLACK_SPACE) { 3735 chain_prod = RX_CHAIN_IDX(prod); 3736 if (bce_get_buf(sc, NULL, &prod, &chain_prod, &prod_bseq)) { 3737 BCE_PRINTF(sc, "%s(%d): Error filling RX chain: rx_bd[0x%04X]!\n", 3738 __FILE__, __LINE__, chain_prod); 3739 rc = ENOBUFS; 3740 break; 3741 } 3742 prod = NEXT_RX_BD(prod); 3743 } 3744 3745 /* Save the RX chain producer index. */ 3746 sc->rx_prod = prod; 3747 sc->rx_prod_bseq = prod_bseq; 3748 3749 for (i = 0; i < RX_PAGES; i++) { 3750 bus_dmamap_sync( 3751 sc->rx_bd_chain_tag, 3752 sc->rx_bd_chain_map[i], 3753 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3754 } 3755 3756 /* Tell the chip about the waiting rx_bd's. */ 3757 REG_WR16(sc, MB_RX_CID_ADDR + BCE_L2CTX_HOST_BDIDX, sc->rx_prod); 3758 REG_WR(sc, MB_RX_CID_ADDR + BCE_L2CTX_HOST_BSEQ, sc->rx_prod_bseq); 3759 3760 DBRUN(BCE_VERBOSE_RECV, bce_dump_rx_chain(sc, 0, TOTAL_RX_BD)); 3761 3762 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 3763 3764 return(rc); 3765} 3766 3767 3768/****************************************************************************/ 3769/* Free memory and clear the RX data structures. */ 3770/* */ 3771/* Returns: */ 3772/* Nothing. */ 3773/****************************************************************************/ 3774static void 3775bce_free_rx_chain(struct bce_softc *sc) 3776{ 3777 int i; 3778 3779 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 3780 3781 /* Free any mbufs still in the RX mbuf chain. */ 3782 for (i = 0; i < TOTAL_RX_BD; i++) { 3783 if (sc->rx_mbuf_ptr[i] != NULL) { 3784 if (sc->rx_mbuf_map[i] != NULL) 3785 bus_dmamap_sync(sc->rx_mbuf_tag, sc->rx_mbuf_map[i], 3786 BUS_DMASYNC_POSTREAD); 3787 m_freem(sc->rx_mbuf_ptr[i]); 3788 sc->rx_mbuf_ptr[i] = NULL; 3789 DBRUNIF(1, sc->rx_mbuf_alloc--); 3790 } 3791 } 3792 3793 /* Clear each RX chain page. */ 3794 for (i = 0; i < RX_PAGES; i++) 3795 bzero((char *)sc->rx_bd_chain[i], BCE_RX_CHAIN_PAGE_SZ); 3796 3797 /* Check if we lost any mbufs in the process. */ 3798 DBRUNIF((sc->rx_mbuf_alloc), 3799 BCE_PRINTF(sc, "%s(%d): Memory leak! Lost %d mbufs from rx chain!\n", 3800 __FILE__, __LINE__, sc->rx_mbuf_alloc)); 3801 3802 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 3803} 3804 3805 3806/****************************************************************************/ 3807/* Set media options. */ 3808/* */ 3809/* Returns: */ 3810/* 0 for success, positive value for failure. */ 3811/****************************************************************************/ 3812static int 3813bce_ifmedia_upd(struct ifnet *ifp) 3814{ 3815 struct bce_softc *sc; 3816 3817 sc = ifp->if_softc; 3818 BCE_LOCK(sc); 3819 bce_ifmedia_upd_locked(ifp); 3820 BCE_UNLOCK(sc); 3821 return (0); 3822} 3823 3824static void 3825bce_ifmedia_upd_locked(struct ifnet *ifp) 3826{ 3827 struct bce_softc *sc; 3828 struct mii_data *mii; 3829 struct ifmedia *ifm; 3830 3831 sc = ifp->if_softc; 3832 ifm = &sc->bce_ifmedia; 3833 BCE_LOCK_ASSERT(sc); 3834 3835 /* DRC - ToDo: Add SerDes support. */ 3836 3837 mii = device_get_softc(sc->bce_miibus); 3838 sc->bce_link = 0; 3839 if (mii->mii_instance) { 3840 struct mii_softc *miisc; 3841 3842 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 3843 mii_phy_reset(miisc); 3844 } 3845 mii_mediachg(mii); 3846} 3847 3848 3849/****************************************************************************/ 3850/* Reports current media status. */ 3851/* */ 3852/* Returns: */ 3853/* Nothing. */ 3854/****************************************************************************/ 3855static void 3856bce_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3857{ 3858 struct bce_softc *sc; 3859 struct mii_data *mii; 3860 3861 sc = ifp->if_softc; 3862 3863 BCE_LOCK(sc); 3864 3865 mii = device_get_softc(sc->bce_miibus); 3866 3867 /* DRC - ToDo: Add SerDes support. */ 3868 3869 mii_pollstat(mii); 3870 ifmr->ifm_active = mii->mii_media_active; 3871 ifmr->ifm_status = mii->mii_media_status; 3872 3873 BCE_UNLOCK(sc); 3874} 3875 3876 3877/****************************************************************************/ 3878/* Handles PHY generated interrupt events. */ 3879/* */ 3880/* Returns: */ 3881/* Nothing. */ 3882/****************************************************************************/ 3883static void 3884bce_phy_intr(struct bce_softc *sc) 3885{ 3886 u32 new_link_state, old_link_state; 3887 3888 new_link_state = sc->status_block->status_attn_bits & 3889 STATUS_ATTN_BITS_LINK_STATE; 3890 old_link_state = sc->status_block->status_attn_bits_ack & 3891 STATUS_ATTN_BITS_LINK_STATE; 3892 3893 /* Handle any changes if the link state has changed. */ 3894 if (new_link_state != old_link_state) { 3895 3896 DBRUN(BCE_VERBOSE_INTR, bce_dump_status_block(sc)); 3897 3898 sc->bce_link = 0; 3899 callout_stop(&sc->bce_stat_ch); 3900 bce_tick(sc); 3901 3902 /* Update the status_attn_bits_ack field in the status block. */ 3903 if (new_link_state) { 3904 REG_WR(sc, BCE_PCICFG_STATUS_BIT_SET_CMD, 3905 STATUS_ATTN_BITS_LINK_STATE); 3906 DBPRINT(sc, BCE_INFO, "Link is now UP.\n"); 3907 } 3908 else { 3909 REG_WR(sc, BCE_PCICFG_STATUS_BIT_CLEAR_CMD, 3910 STATUS_ATTN_BITS_LINK_STATE); 3911 DBPRINT(sc, BCE_INFO, "Link is now DOWN.\n"); 3912 } 3913 3914 } 3915 3916 /* Acknowledge the link change interrupt. */ 3917 REG_WR(sc, BCE_EMAC_STATUS, BCE_EMAC_STATUS_LINK_CHANGE); 3918} 3919 3920 3921/****************************************************************************/ 3922/* Handles received frame interrupt events. */ 3923/* */ 3924/* Returns: */ 3925/* Nothing. */ 3926/****************************************************************************/ 3927static void 3928bce_rx_intr(struct bce_softc *sc) 3929{ 3930 struct status_block *sblk = sc->status_block; 3931 struct ifnet *ifp = sc->bce_ifp; 3932 u16 hw_cons, sw_cons, sw_chain_cons, sw_prod, sw_chain_prod; 3933 u32 sw_prod_bseq; 3934 struct l2_fhdr *l2fhdr; 3935 3936 DBRUNIF(1, sc->rx_interrupts++); 3937 3938 /* Prepare the RX chain pages to be accessed by the host CPU. */ 3939 for (int i = 0; i < RX_PAGES; i++) 3940 bus_dmamap_sync(sc->rx_bd_chain_tag, 3941 sc->rx_bd_chain_map[i], BUS_DMASYNC_POSTWRITE); 3942 3943 /* Get the hardware's view of the RX consumer index. */ 3944 hw_cons = sc->hw_rx_cons = sblk->status_rx_quick_consumer_index0; 3945 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 3946 hw_cons++; 3947 3948 /* Get working copies of the driver's view of the RX indices. */ 3949 sw_cons = sc->rx_cons; 3950 sw_prod = sc->rx_prod; 3951 sw_prod_bseq = sc->rx_prod_bseq; 3952 3953 DBPRINT(sc, BCE_INFO_RECV, "%s(enter): sw_prod = 0x%04X, " 3954 "sw_cons = 0x%04X, sw_prod_bseq = 0x%08X\n", 3955 __FUNCTION__, sw_prod, sw_cons, 3956 sw_prod_bseq); 3957 3958 /* Prevent speculative reads from getting ahead of the status block. */ 3959 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 3960 BUS_SPACE_BARRIER_READ); 3961 3962 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 3963 sc->rx_low_watermark = sc->free_rx_bd); 3964 3965 /* 3966 * Scan through the receive chain as long 3967 * as there is work to do. 3968 */ 3969 while (sw_cons != hw_cons) { 3970 struct mbuf *m; 3971 struct rx_bd *rxbd; 3972 unsigned int len; 3973 u32 status; 3974 3975 /* Convert the producer/consumer indices to an actual rx_bd index. */ 3976 sw_chain_cons = RX_CHAIN_IDX(sw_cons); 3977 sw_chain_prod = RX_CHAIN_IDX(sw_prod); 3978 3979 /* Get the used rx_bd. */ 3980 rxbd = &sc->rx_bd_chain[RX_PAGE(sw_chain_cons)][RX_IDX(sw_chain_cons)]; 3981 sc->free_rx_bd++; 3982 3983 DBRUN(BCE_VERBOSE_RECV, 3984 BCE_PRINTF(sc, "%s(): ", __FUNCTION__); 3985 bce_dump_rxbd(sc, sw_chain_cons, rxbd)); 3986 3987#ifdef DEVICE_POLLING 3988 if (ifp->if_capenable & IFCAP_POLLING) { 3989 if (sc->bce_rxcycles <= 0) 3990 break; 3991 sc->bce_rxcycles--; 3992 } 3993#endif 3994 3995 /* The mbuf is stored with the last rx_bd entry of a packet. */ 3996 if (sc->rx_mbuf_ptr[sw_chain_cons] != NULL) { 3997 3998 /* Validate that this is the last rx_bd. */ 3999 DBRUNIF((!(rxbd->rx_bd_flags & RX_BD_FLAGS_END)), 4000 BCE_PRINTF(sc, "%s(%d): Unexpected mbuf found in rx_bd[0x%04X]!\n", 4001 __FILE__, __LINE__, sw_chain_cons); 4002 bce_breakpoint(sc)); 4003 4004 /* DRC - ToDo: If the received packet is small, say less */ 4005 /* than 128 bytes, allocate a new mbuf here, */ 4006 /* copy the data to that mbuf, and recycle */ 4007 /* the mapped jumbo frame. */ 4008 4009 /* Unmap the mbuf from DMA space. */ 4010 bus_dmamap_sync(sc->rx_mbuf_tag, 4011 sc->rx_mbuf_map[sw_chain_cons], 4012 BUS_DMASYNC_POSTREAD); 4013 bus_dmamap_unload(sc->rx_mbuf_tag, 4014 sc->rx_mbuf_map[sw_chain_cons]); 4015 4016 /* Remove the mbuf from the driver's chain. */ 4017 m = sc->rx_mbuf_ptr[sw_chain_cons]; 4018 sc->rx_mbuf_ptr[sw_chain_cons] = NULL; 4019 4020 /* 4021 * Frames received on the NetXteme II are prepended 4022 * with the l2_fhdr structure which provides status 4023 * information about the received frame (including 4024 * VLAN tags and checksum info) and are also 4025 * automatically adjusted to align the IP header 4026 * (i.e. two null bytes are inserted before the 4027 * Ethernet header). 4028 */ 4029 l2fhdr = mtod(m, struct l2_fhdr *); 4030 4031 len = l2fhdr->l2_fhdr_pkt_len; 4032 status = l2fhdr->l2_fhdr_status; 4033 4034 DBRUNIF(DB_RANDOMTRUE(bce_debug_l2fhdr_status_check), 4035 BCE_PRINTF(sc, "Simulating l2_fhdr status error.\n"); 4036 status = status | L2_FHDR_ERRORS_PHY_DECODE); 4037 4038 /* Watch for unusual sized frames. */ 4039 DBRUNIF(((len < BCE_MIN_MTU) || (len > BCE_MAX_JUMBO_ETHER_MTU_VLAN)), 4040 BCE_PRINTF(sc, "%s(%d): Unusual frame size found. " 4041 "Min(%d), Actual(%d), Max(%d)\n", 4042 __FILE__, __LINE__, (int) BCE_MIN_MTU, 4043 len, (int) BCE_MAX_JUMBO_ETHER_MTU_VLAN); 4044 bce_dump_mbuf(sc, m); 4045 bce_breakpoint(sc)); 4046 4047 len -= ETHER_CRC_LEN; 4048 4049 /* Check the received frame for errors. */ 4050 if (status & (L2_FHDR_ERRORS_BAD_CRC | 4051 L2_FHDR_ERRORS_PHY_DECODE | L2_FHDR_ERRORS_ALIGNMENT | 4052 L2_FHDR_ERRORS_TOO_SHORT | L2_FHDR_ERRORS_GIANT_FRAME)) { 4053 4054 ifp->if_ierrors++; 4055 DBRUNIF(1, sc->l2fhdr_status_errors++); 4056 4057 /* Reuse the mbuf for a new frame. */ 4058 if (bce_get_buf(sc, m, &sw_prod, &sw_chain_prod, &sw_prod_bseq)) { 4059 4060 DBRUNIF(1, bce_breakpoint(sc)); 4061 panic("bce%d: Can't reuse RX mbuf!\n", sc->bce_unit); 4062 4063 } 4064 goto bce_rx_int_next_rx; 4065 } 4066 4067 /* 4068 * Get a new mbuf for the rx_bd. If no new 4069 * mbufs are available then reuse the current mbuf, 4070 * log an ierror on the interface, and generate 4071 * an error in the system log. 4072 */ 4073 if (bce_get_buf(sc, NULL, &sw_prod, &sw_chain_prod, &sw_prod_bseq)) { 4074 4075 DBRUN(BCE_WARN, 4076 BCE_PRINTF(sc, "%s(%d): Failed to allocate " 4077 "new mbuf, incoming frame dropped!\n", 4078 __FILE__, __LINE__)); 4079 4080 ifp->if_ierrors++; 4081 4082 /* Try and reuse the exisitng mbuf. */ 4083 if (bce_get_buf(sc, m, &sw_prod, &sw_chain_prod, &sw_prod_bseq)) { 4084 4085 DBRUNIF(1, bce_breakpoint(sc)); 4086 panic("bce%d: Double mbuf allocation failure!", sc->bce_unit); 4087 4088 } 4089 goto bce_rx_int_next_rx; 4090 } 4091 4092 /* Skip over the l2_fhdr when passing the data up the stack. */ 4093 m_adj(m, sizeof(struct l2_fhdr) + ETHER_ALIGN); 4094 4095 /* Adjust the packet length to match the received data. */ 4096 m->m_pkthdr.len = m->m_len = len; 4097 4098 /* Send the packet to the appropriate interface. */ 4099 m->m_pkthdr.rcvif = ifp; 4100 4101 DBRUN(BCE_VERBOSE_RECV, 4102 struct ether_header *eh; 4103 eh = mtod(m, struct ether_header *); 4104 BCE_PRINTF(sc, "%s(): to: %6D, from: %6D, type: 0x%04X\n", 4105 __FUNCTION__, eh->ether_dhost, ":", 4106 eh->ether_shost, ":", htons(eh->ether_type))); 4107 4108 /* Validate the checksum if offload enabled. */ 4109 if (ifp->if_capenable & IFCAP_RXCSUM) { 4110 4111 /* Check for an IP datagram. */ 4112 if (status & L2_FHDR_STATUS_IP_DATAGRAM) { 4113 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 4114 4115 /* Check if the IP checksum is valid. */ 4116 if ((l2fhdr->l2_fhdr_ip_xsum ^ 0xffff) == 0) 4117 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 4118 else 4119 DBPRINT(sc, BCE_WARN_SEND, 4120 "%s(): Invalid IP checksum = 0x%04X!\n", 4121 __FUNCTION__, l2fhdr->l2_fhdr_ip_xsum); 4122 } 4123 4124 /* Check for a valid TCP/UDP frame. */ 4125 if (status & (L2_FHDR_STATUS_TCP_SEGMENT | 4126 L2_FHDR_STATUS_UDP_DATAGRAM)) { 4127 4128 /* Check for a good TCP/UDP checksum. */ 4129 if ((status & (L2_FHDR_ERRORS_TCP_XSUM | 4130 L2_FHDR_ERRORS_UDP_XSUM)) == 0) { 4131 m->m_pkthdr.csum_data = 4132 l2fhdr->l2_fhdr_tcp_udp_xsum; 4133 m->m_pkthdr.csum_flags |= (CSUM_DATA_VALID 4134 | CSUM_PSEUDO_HDR); 4135 } else 4136 DBPRINT(sc, BCE_WARN_SEND, 4137 "%s(): Invalid TCP/UDP checksum = 0x%04X!\n", 4138 __FUNCTION__, l2fhdr->l2_fhdr_tcp_udp_xsum); 4139 } 4140 } 4141 4142 4143 /* 4144 * If we received a packet with a vlan tag, 4145 * attach that information to the packet. 4146 */ 4147 if (status & L2_FHDR_STATUS_L2_VLAN_TAG) { 4148 DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): VLAN tag = 0x%04X\n", 4149 __FUNCTION__, l2fhdr->l2_fhdr_vlan_tag); 4150#if __FreeBSD_version < 700000 4151 VLAN_INPUT_TAG(ifp, m, l2fhdr->l2_fhdr_vlan_tag, continue); 4152#else 4153 m->m_pkthdr.ether_vtag = l2fhdr->l2_fhdr_vlan_tag; 4154 m->m_flags |= M_VLANTAG; 4155#endif 4156 } 4157 4158 /* Pass the mbuf off to the upper layers. */ 4159 ifp->if_ipackets++; 4160 DBPRINT(sc, BCE_VERBOSE_RECV, "%s(): Passing received frame up.\n", 4161 __FUNCTION__); 4162 BCE_UNLOCK(sc); 4163 (*ifp->if_input)(ifp, m); 4164 DBRUNIF(1, sc->rx_mbuf_alloc--); 4165 BCE_LOCK(sc); 4166 4167bce_rx_int_next_rx: 4168 sw_prod = NEXT_RX_BD(sw_prod); 4169 } 4170 4171 sw_cons = NEXT_RX_BD(sw_cons); 4172 4173 /* Refresh hw_cons to see if there's new work */ 4174 if (sw_cons == hw_cons) { 4175 hw_cons = sc->hw_rx_cons = sblk->status_rx_quick_consumer_index0; 4176 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 4177 hw_cons++; 4178 } 4179 4180 /* Prevent speculative reads from getting ahead of the status block. */ 4181 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 4182 BUS_SPACE_BARRIER_READ); 4183 } 4184 4185 for (int i = 0; i < RX_PAGES; i++) 4186 bus_dmamap_sync(sc->rx_bd_chain_tag, 4187 sc->rx_bd_chain_map[i], BUS_DMASYNC_PREWRITE); 4188 4189 sc->rx_cons = sw_cons; 4190 sc->rx_prod = sw_prod; 4191 sc->rx_prod_bseq = sw_prod_bseq; 4192 4193 REG_WR16(sc, MB_RX_CID_ADDR + BCE_L2CTX_HOST_BDIDX, sc->rx_prod); 4194 REG_WR(sc, MB_RX_CID_ADDR + BCE_L2CTX_HOST_BSEQ, sc->rx_prod_bseq); 4195 4196 DBPRINT(sc, BCE_INFO_RECV, "%s(exit): rx_prod = 0x%04X, " 4197 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n", 4198 __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq); 4199} 4200 4201 4202/****************************************************************************/ 4203/* Handles transmit completion interrupt events. */ 4204/* */ 4205/* Returns: */ 4206/* Nothing. */ 4207/****************************************************************************/ 4208static void 4209bce_tx_intr(struct bce_softc *sc) 4210{ 4211 struct status_block *sblk = sc->status_block; 4212 struct ifnet *ifp = sc->bce_ifp; 4213 u16 hw_tx_cons, sw_tx_cons, sw_tx_chain_cons; 4214 4215 BCE_LOCK_ASSERT(sc); 4216 4217 DBRUNIF(1, sc->tx_interrupts++); 4218 4219 /* Get the hardware's view of the TX consumer index. */ 4220 hw_tx_cons = sc->hw_tx_cons = sblk->status_tx_quick_consumer_index0; 4221 4222 /* Skip to the next entry if this is a chain page pointer. */ 4223 if ((hw_tx_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 4224 hw_tx_cons++; 4225 4226 sw_tx_cons = sc->tx_cons; 4227 4228 /* Prevent speculative reads from getting ahead of the status block. */ 4229 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 4230 BUS_SPACE_BARRIER_READ); 4231 4232 /* Cycle through any completed TX chain page entries. */ 4233 while (sw_tx_cons != hw_tx_cons) { 4234#ifdef BCE_DEBUG 4235 struct tx_bd *txbd = NULL; 4236#endif 4237 sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons); 4238 4239 DBPRINT(sc, BCE_INFO_SEND, 4240 "%s(): hw_tx_cons = 0x%04X, sw_tx_cons = 0x%04X, " 4241 "sw_tx_chain_cons = 0x%04X\n", 4242 __FUNCTION__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons); 4243 4244 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD), 4245 BCE_PRINTF(sc, "%s(%d): TX chain consumer out of range! " 4246 " 0x%04X > 0x%04X\n", 4247 __FILE__, __LINE__, sw_tx_chain_cons, 4248 (int) MAX_TX_BD); 4249 bce_breakpoint(sc)); 4250 4251 DBRUNIF(1, 4252 txbd = &sc->tx_bd_chain[TX_PAGE(sw_tx_chain_cons)] 4253 [TX_IDX(sw_tx_chain_cons)]); 4254 4255 DBRUNIF((txbd == NULL), 4256 BCE_PRINTF(sc, "%s(%d): Unexpected NULL tx_bd[0x%04X]!\n", 4257 __FILE__, __LINE__, sw_tx_chain_cons); 4258 bce_breakpoint(sc)); 4259 4260 DBRUN(BCE_INFO_SEND, 4261 BCE_PRINTF(sc, "%s(): ", __FUNCTION__); 4262 bce_dump_txbd(sc, sw_tx_chain_cons, txbd)); 4263 4264 /* 4265 * Free the associated mbuf. Remember 4266 * that only the last tx_bd of a packet 4267 * has an mbuf pointer and DMA map. 4268 */ 4269 if (sc->tx_mbuf_ptr[sw_tx_chain_cons] != NULL) { 4270 4271 /* Validate that this is the last tx_bd. */ 4272 DBRUNIF((!(txbd->tx_bd_flags & TX_BD_FLAGS_END)), 4273 BCE_PRINTF(sc, "%s(%d): tx_bd END flag not set but " 4274 "txmbuf == NULL!\n", __FILE__, __LINE__); 4275 bce_breakpoint(sc)); 4276 4277 DBRUN(BCE_INFO_SEND, 4278 BCE_PRINTF(sc, "%s(): Unloading map/freeing mbuf " 4279 "from tx_bd[0x%04X]\n", __FUNCTION__, sw_tx_chain_cons)); 4280 4281 /* Unmap the mbuf. */ 4282 bus_dmamap_unload(sc->tx_mbuf_tag, 4283 sc->tx_mbuf_map[sw_tx_chain_cons]); 4284 4285 /* Free the mbuf. */ 4286 m_freem(sc->tx_mbuf_ptr[sw_tx_chain_cons]); 4287 sc->tx_mbuf_ptr[sw_tx_chain_cons] = NULL; 4288 DBRUNIF(1, sc->tx_mbuf_alloc--); 4289 4290 ifp->if_opackets++; 4291 } 4292 4293 sc->used_tx_bd--; 4294 sw_tx_cons = NEXT_TX_BD(sw_tx_cons); 4295 4296 /* Refresh hw_cons to see if there's new work. */ 4297 hw_tx_cons = sc->hw_tx_cons = sblk->status_tx_quick_consumer_index0; 4298 if ((hw_tx_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 4299 hw_tx_cons++; 4300 4301 /* Prevent speculative reads from getting ahead of the status block. */ 4302 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 4303 BUS_SPACE_BARRIER_READ); 4304 } 4305 4306 /* Clear the TX timeout timer. */ 4307 sc->watchdog_timer = 0; 4308 4309 /* Clear the tx hardware queue full flag. */ 4310 if ((sc->used_tx_bd + BCE_TX_SLACK_SPACE) < USABLE_TX_BD) { 4311 DBRUNIF((ifp->if_drv_flags & IFF_DRV_OACTIVE), 4312 BCE_PRINTF(sc, "%s(): TX chain is open for business! Used tx_bd = %d\n", 4313 __FUNCTION__, sc->used_tx_bd)); 4314 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 4315 } 4316 4317 sc->tx_cons = sw_tx_cons; 4318} 4319 4320 4321/****************************************************************************/ 4322/* Disables interrupt generation. */ 4323/* */ 4324/* Returns: */ 4325/* Nothing. */ 4326/****************************************************************************/ 4327static void 4328bce_disable_intr(struct bce_softc *sc) 4329{ 4330 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 4331 BCE_PCICFG_INT_ACK_CMD_MASK_INT); 4332 REG_RD(sc, BCE_PCICFG_INT_ACK_CMD); 4333} 4334 4335 4336/****************************************************************************/ 4337/* Enables interrupt generation. */ 4338/* */ 4339/* Returns: */ 4340/* Nothing. */ 4341/****************************************************************************/ 4342static void 4343bce_enable_intr(struct bce_softc *sc) 4344{ 4345 u32 val; 4346 4347 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 4348 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | 4349 BCE_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx); 4350 4351 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 4352 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx); 4353 4354 val = REG_RD(sc, BCE_HC_COMMAND); 4355 REG_WR(sc, BCE_HC_COMMAND, val | BCE_HC_COMMAND_COAL_NOW); 4356} 4357 4358 4359/****************************************************************************/ 4360/* Handles controller initialization. */ 4361/* */ 4362/* Must be called from a locked routine. */ 4363/* */ 4364/* Returns: */ 4365/* Nothing. */ 4366/****************************************************************************/ 4367static void 4368bce_init_locked(struct bce_softc *sc) 4369{ 4370 struct ifnet *ifp; 4371 u32 ether_mtu; 4372 4373 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 4374 4375 BCE_LOCK_ASSERT(sc); 4376 4377 ifp = sc->bce_ifp; 4378 4379 /* Check if the driver is still running and bail out if it is. */ 4380 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 4381 goto bce_init_locked_exit; 4382 4383 bce_stop(sc); 4384 4385 if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) { 4386 BCE_PRINTF(sc, "%s(%d): Controller reset failed!\n", 4387 __FILE__, __LINE__); 4388 goto bce_init_locked_exit; 4389 } 4390 4391 if (bce_chipinit(sc)) { 4392 BCE_PRINTF(sc, "%s(%d): Controller initialization failed!\n", 4393 __FILE__, __LINE__); 4394 goto bce_init_locked_exit; 4395 } 4396 4397 if (bce_blockinit(sc)) { 4398 BCE_PRINTF(sc, "%s(%d): Block initialization failed!\n", 4399 __FILE__, __LINE__); 4400 goto bce_init_locked_exit; 4401 } 4402 4403 /* Load our MAC address. */ 4404 bcopy(IF_LLADDR(sc->bce_ifp), sc->eaddr, ETHER_ADDR_LEN); 4405 bce_set_mac_addr(sc); 4406 4407 /* Calculate and program the Ethernet MTU size. */ 4408 ether_mtu = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ifp->if_mtu + 4409 ETHER_CRC_LEN; 4410 4411 DBPRINT(sc, BCE_INFO, "%s(): setting mtu = %d\n",__FUNCTION__, ether_mtu); 4412 4413 /* 4414 * Program the mtu, enabling jumbo frame 4415 * support if necessary. Also set the mbuf 4416 * allocation count for RX frames. 4417 */ 4418 if (ether_mtu > ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) { 4419 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, ether_mtu | 4420 BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA); 4421 sc->mbuf_alloc_size = MJUM9BYTES; 4422 } else { 4423 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, ether_mtu); 4424 sc->mbuf_alloc_size = MCLBYTES; 4425 } 4426 4427 /* Calculate the RX Ethernet frame size for rx_bd's. */ 4428 sc->max_frame_size = sizeof(struct l2_fhdr) + 2 + ether_mtu + 8; 4429 4430 DBPRINT(sc, BCE_INFO, 4431 "%s(): mclbytes = %d, mbuf_alloc_size = %d, " 4432 "max_frame_size = %d\n", 4433 __FUNCTION__, (int) MCLBYTES, sc->mbuf_alloc_size, sc->max_frame_size); 4434 4435 /* Program appropriate promiscuous/multicast filtering. */ 4436 bce_set_rx_mode(sc); 4437 4438 /* Init RX buffer descriptor chain. */ 4439 bce_init_rx_chain(sc); 4440 4441 /* Init TX buffer descriptor chain. */ 4442 bce_init_tx_chain(sc); 4443 4444#ifdef DEVICE_POLLING 4445 /* Disable interrupts if we are polling. */ 4446 if (ifp->if_capenable & IFCAP_POLLING) { 4447 bce_disable_intr(sc); 4448 4449 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP, 4450 (1 << 16) | sc->bce_rx_quick_cons_trip); 4451 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP, 4452 (1 << 16) | sc->bce_tx_quick_cons_trip); 4453 } else 4454#endif 4455 /* Enable host interrupts. */ 4456 bce_enable_intr(sc); 4457 4458 bce_ifmedia_upd_locked(ifp); 4459 4460 ifp->if_drv_flags |= IFF_DRV_RUNNING; 4461 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 4462 4463 callout_reset(&sc->bce_stat_ch, hz, bce_tick, sc); 4464 4465bce_init_locked_exit: 4466 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 4467 4468 return; 4469} 4470 4471static void 4472bce_mgmt_init_locked(struct bce_softc *sc) 4473{ 4474 u32 val; 4475 struct ifnet *ifp; 4476 4477 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 4478 4479 BCE_LOCK_ASSERT(sc); 4480 4481 ifp = sc->bce_ifp; 4482 4483 /* Check if the driver is still running and bail out if it is. */ 4484 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 4485 goto bce_mgmt_init_locked_exit; 4486 4487 /* Initialize the on-boards CPUs */ 4488 bce_init_cpus(sc); 4489 4490 val = (BCM_PAGE_BITS - 8) << 24; 4491 REG_WR(sc, BCE_RV2P_CONFIG, val); 4492 4493 /* Enable all critical blocks in the MAC. */ 4494 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 4495 BCE_MISC_ENABLE_SET_BITS_RX_V2P_ENABLE | 4496 BCE_MISC_ENABLE_SET_BITS_RX_DMA_ENABLE | 4497 BCE_MISC_ENABLE_SET_BITS_COMPLETION_ENABLE); 4498 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS); 4499 DELAY(20); 4500 4501 bce_ifmedia_upd_locked(ifp); 4502bce_mgmt_init_locked_exit: 4503 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 4504 4505 return; 4506} 4507 4508 4509/****************************************************************************/ 4510/* Handles controller initialization when called from an unlocked routine. */ 4511/* */ 4512/* Returns: */ 4513/* Nothing. */ 4514/****************************************************************************/ 4515static void 4516bce_init(void *xsc) 4517{ 4518 struct bce_softc *sc = xsc; 4519 4520 BCE_LOCK(sc); 4521 bce_init_locked(sc); 4522 BCE_UNLOCK(sc); 4523} 4524 4525 4526/****************************************************************************/ 4527/* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */ 4528/* memory visible to the controller. */ 4529/* */ 4530/* Returns: */ 4531/* 0 for success, positive value for failure. */ 4532/****************************************************************************/ 4533static int 4534bce_tx_encap(struct bce_softc *sc, struct mbuf **m_head) 4535{ 4536 bus_dma_segment_t segs[BCE_MAX_SEGMENTS]; 4537 bus_dmamap_t map; 4538 struct tx_bd *txbd = NULL; 4539 struct mbuf *m0; 4540 u16 vlan_tag = 0, flags = 0; 4541 u16 chain_prod, prod; 4542 u32 prod_bseq; 4543 4544#ifdef BCE_DEBUG 4545 u16 debug_prod; 4546#endif 4547 int i, error, nsegs, rc = 0; 4548 4549 /* Transfer any checksum offload flags to the bd. */ 4550 m0 = *m_head; 4551 if (m0->m_pkthdr.csum_flags) { 4552 if (m0->m_pkthdr.csum_flags & CSUM_IP) 4553 flags |= TX_BD_FLAGS_IP_CKSUM; 4554 if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 4555 flags |= TX_BD_FLAGS_TCP_UDP_CKSUM; 4556 } 4557 4558 /* Transfer any VLAN tags to the bd. */ 4559 if (m0->m_flags & M_VLANTAG) { 4560 flags |= TX_BD_FLAGS_VLAN_TAG; 4561 vlan_tag = m0->m_pkthdr.ether_vtag; 4562 } 4563 4564 /* Map the mbuf into DMAable memory. */ 4565 prod = sc->tx_prod; 4566 chain_prod = TX_CHAIN_IDX(prod); 4567 map = sc->tx_mbuf_map[chain_prod]; 4568 4569 /* Map the mbuf into our DMA address space. */ 4570 error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag, map, m0, 4571 segs, &nsegs, BUS_DMA_NOWAIT); 4572 4573 if (error == EFBIG) { 4574 4575 /* Try to defrag the mbuf if there are too many segments. */ 4576 DBPRINT(sc, BCE_WARN, "%s(): fragmented mbuf (%d pieces)\n", 4577 __FUNCTION__, nsegs); 4578 4579 m0 = m_defrag(*m_head, M_DONTWAIT); 4580 if (m0 == NULL) { 4581 m_freem(*m_head); 4582 *m_head = NULL; 4583 return (ENOBUFS); 4584 } 4585 4586 *m_head = m0; 4587 error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag, map, m0, 4588 segs, &nsegs, BUS_DMA_NOWAIT); 4589 4590 /* Still getting an error after a defrag. */ 4591 if (error == ENOMEM) { 4592 return (error); 4593 } else if (error != 0) { 4594 BCE_PRINTF(sc, 4595 "%s(%d): Error mapping mbuf into TX chain!\n", 4596 __FILE__, __LINE__); 4597 m_freem(m0); 4598 *m_head = NULL; 4599 return (ENOBUFS); 4600 } 4601 } else if (error == ENOMEM) { 4602 return (error); 4603 } else if (error != 0) { 4604 m_freem(m0); 4605 *m_head = NULL; 4606 return (error); 4607 } 4608 4609 /* 4610 * The chip seems to require that at least 16 descriptors be kept 4611 * empty at all times. Make sure we honor that. 4612 * XXX Would it be faster to assume worst case scenario for nsegs 4613 * and do this calculation higher up? 4614 */ 4615 if (nsegs > (USABLE_TX_BD - sc->used_tx_bd - BCE_TX_SLACK_SPACE)) { 4616 bus_dmamap_unload(sc->tx_mbuf_tag, map); 4617 return (ENOBUFS); 4618 } 4619 4620 /* prod points to an empty tx_bd at this point. */ 4621 prod_bseq = sc->tx_prod_bseq; 4622 4623#ifdef BCE_DEBUG 4624 debug_prod = chain_prod; 4625#endif 4626 4627 DBPRINT(sc, BCE_INFO_SEND, 4628 "%s(): Start: prod = 0x%04X, chain_prod = %04X, " 4629 "prod_bseq = 0x%08X\n", 4630 __FUNCTION__, prod, chain_prod, prod_bseq); 4631 4632 /* 4633 * Cycle through each mbuf segment that makes up 4634 * the outgoing frame, gathering the mapping info 4635 * for that segment and creating a tx_bd to for 4636 * the mbuf. 4637 */ 4638 for (i = 0; i < nsegs ; i++) { 4639 4640 chain_prod = TX_CHAIN_IDX(prod); 4641 txbd= &sc->tx_bd_chain[TX_PAGE(chain_prod)][TX_IDX(chain_prod)]; 4642 4643 txbd->tx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[i].ds_addr)); 4644 txbd->tx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[i].ds_addr)); 4645 txbd->tx_bd_mss_nbytes = htole16(segs[i].ds_len); 4646 txbd->tx_bd_vlan_tag = htole16(vlan_tag); 4647 txbd->tx_bd_flags = htole16(flags); 4648 prod_bseq += segs[i].ds_len; 4649 if (i == 0) 4650 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_START); 4651 prod = NEXT_TX_BD(prod); 4652 } 4653 4654 /* Set the END flag on the last TX buffer descriptor. */ 4655 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_END); 4656 4657 DBRUN(BCE_INFO_SEND, bce_dump_tx_chain(sc, debug_prod, nsegs)); 4658 4659 DBPRINT(sc, BCE_INFO_SEND, 4660 "%s(): End: prod = 0x%04X, chain_prod = %04X, " 4661 "prod_bseq = 0x%08X\n", 4662 __FUNCTION__, prod, chain_prod, prod_bseq); 4663 4664 /* 4665 * Ensure that the mbuf pointer for this transmission 4666 * is placed at the array index of the last 4667 * descriptor in this chain. This is done 4668 * because a single map is used for all 4669 * segments of the mbuf and we don't want to 4670 * unload the map before all of the segments 4671 * have been freed. 4672 */ 4673 sc->tx_mbuf_ptr[chain_prod] = m0; 4674 sc->used_tx_bd += nsegs; 4675 4676 DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark), 4677 sc->tx_hi_watermark = sc->used_tx_bd); 4678 4679 DBRUNIF(1, sc->tx_mbuf_alloc++); 4680 4681 DBRUN(BCE_VERBOSE_SEND, bce_dump_tx_mbuf_chain(sc, chain_prod, nsegs)); 4682 4683 /* prod points to the next free tx_bd at this point. */ 4684 sc->tx_prod = prod; 4685 sc->tx_prod_bseq = prod_bseq; 4686 4687 return(rc); 4688} 4689 4690 4691/****************************************************************************/ 4692/* Main transmit routine when called from another routine with a lock. */ 4693/* */ 4694/* Returns: */ 4695/* Nothing. */ 4696/****************************************************************************/ 4697static void 4698bce_start_locked(struct ifnet *ifp) 4699{ 4700 struct bce_softc *sc = ifp->if_softc; 4701 struct mbuf *m_head = NULL; 4702 int count = 0; 4703 u16 tx_prod, tx_chain_prod; 4704 4705 /* If there's no link or the transmit queue is empty then just exit. */ 4706 if (!sc->bce_link || IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 4707 DBPRINT(sc, BCE_INFO_SEND, "%s(): No link or transmit queue empty.\n", 4708 __FUNCTION__); 4709 goto bce_start_locked_exit; 4710 } 4711 4712 /* prod points to the next free tx_bd. */ 4713 tx_prod = sc->tx_prod; 4714 tx_chain_prod = TX_CHAIN_IDX(tx_prod); 4715 4716 DBPRINT(sc, BCE_INFO_SEND, 4717 "%s(): Start: tx_prod = 0x%04X, tx_chain_prod = %04X, " 4718 "tx_prod_bseq = 0x%08X\n", 4719 __FUNCTION__, tx_prod, tx_chain_prod, sc->tx_prod_bseq); 4720 4721 /* 4722 * Keep adding entries while there is space in the ring. We keep 4723 * BCE_TX_SLACK_SPACE entries unused at all times. 4724 */ 4725 while (sc->used_tx_bd < USABLE_TX_BD - BCE_TX_SLACK_SPACE) { 4726 4727 /* Check for any frames to send. */ 4728 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 4729 if (m_head == NULL) 4730 break; 4731 4732 /* 4733 * Pack the data into the transmit ring. If we 4734 * don't have room, place the mbuf back at the 4735 * head of the queue and set the OACTIVE flag 4736 * to wait for the NIC to drain the chain. 4737 */ 4738 if (bce_tx_encap(sc, &m_head)) { 4739 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 4740 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 4741 DBPRINT(sc, BCE_INFO_SEND, 4742 "TX chain is closed for business! Total tx_bd used = %d\n", 4743 sc->used_tx_bd); 4744 break; 4745 } 4746 4747 count++; 4748 4749 /* Send a copy of the frame to any BPF listeners. */ 4750 BPF_MTAP(ifp, m_head); 4751 } 4752 4753 if (count == 0) { 4754 /* no packets were dequeued */ 4755 DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): No packets were dequeued\n", 4756 __FUNCTION__); 4757 goto bce_start_locked_exit; 4758 } 4759 4760 /* Update the driver's counters. */ 4761 tx_chain_prod = TX_CHAIN_IDX(sc->tx_prod); 4762 4763 DBPRINT(sc, BCE_INFO_SEND, 4764 "%s(): End: tx_prod = 0x%04X, tx_chain_prod = 0x%04X, " 4765 "tx_prod_bseq = 0x%08X\n", 4766 __FUNCTION__, tx_prod, tx_chain_prod, sc->tx_prod_bseq); 4767 4768 /* Start the transmit. */ 4769 REG_WR16(sc, MB_TX_CID_ADDR + BCE_L2CTX_TX_HOST_BIDX, sc->tx_prod); 4770 REG_WR(sc, MB_TX_CID_ADDR + BCE_L2CTX_TX_HOST_BSEQ, sc->tx_prod_bseq); 4771 4772 /* Set the tx timeout. */ 4773 sc->watchdog_timer = BCE_TX_TIMEOUT; 4774 4775bce_start_locked_exit: 4776 return; 4777} 4778 4779 4780/****************************************************************************/ 4781/* Main transmit routine when called from another routine without a lock. */ 4782/* */ 4783/* Returns: */ 4784/* Nothing. */ 4785/****************************************************************************/ 4786static void 4787bce_start(struct ifnet *ifp) 4788{ 4789 struct bce_softc *sc = ifp->if_softc; 4790 4791 BCE_LOCK(sc); 4792 bce_start_locked(ifp); 4793 BCE_UNLOCK(sc); 4794} 4795 4796 4797/****************************************************************************/ 4798/* Handles any IOCTL calls from the operating system. */ 4799/* */ 4800/* Returns: */ 4801/* 0 for success, positive value for failure. */ 4802/****************************************************************************/ 4803static int 4804bce_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 4805{ 4806 struct bce_softc *sc = ifp->if_softc; 4807 struct ifreq *ifr = (struct ifreq *) data; 4808 struct mii_data *mii; 4809 int mask, error = 0; 4810 4811 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 4812 4813 switch(command) { 4814 4815 /* Set the MTU. */ 4816 case SIOCSIFMTU: 4817 /* Check that the MTU setting is supported. */ 4818 if ((ifr->ifr_mtu < BCE_MIN_MTU) || 4819 (ifr->ifr_mtu > BCE_MAX_JUMBO_MTU)) { 4820 error = EINVAL; 4821 break; 4822 } 4823 4824 DBPRINT(sc, BCE_INFO, "Setting new MTU of %d\n", ifr->ifr_mtu); 4825 4826 BCE_LOCK(sc); 4827 ifp->if_mtu = ifr->ifr_mtu; 4828 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 4829 bce_init_locked(sc); 4830 BCE_UNLOCK(sc); 4831 break; 4832 4833 /* Set interface. */ 4834 case SIOCSIFFLAGS: 4835 DBPRINT(sc, BCE_VERBOSE, "Received SIOCSIFFLAGS\n"); 4836 4837 BCE_LOCK(sc); 4838 4839 /* Check if the interface is up. */ 4840 if (ifp->if_flags & IFF_UP) { 4841 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 4842 /* Change the promiscuous/multicast flags as necessary. */ 4843 bce_set_rx_mode(sc); 4844 } else { 4845 /* Start the HW */ 4846 bce_init_locked(sc); 4847 } 4848 } else { 4849 /* The interface is down. Check if the driver is running. */ 4850 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 4851 bce_stop(sc); 4852 } 4853 } 4854 4855 BCE_UNLOCK(sc); 4856 error = 0; 4857 4858 break; 4859 4860 /* Add/Delete multicast address */ 4861 case SIOCADDMULTI: 4862 case SIOCDELMULTI: 4863 DBPRINT(sc, BCE_VERBOSE, "Received SIOCADDMULTI/SIOCDELMULTI\n"); 4864 4865 BCE_LOCK(sc); 4866 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 4867 bce_set_rx_mode(sc); 4868 error = 0; 4869 } 4870 BCE_UNLOCK(sc); 4871 4872 break; 4873 4874 /* Set/Get Interface media */ 4875 case SIOCSIFMEDIA: 4876 case SIOCGIFMEDIA: 4877 DBPRINT(sc, BCE_VERBOSE, "Received SIOCSIFMEDIA/SIOCGIFMEDIA\n"); 4878 4879 DBPRINT(sc, BCE_VERBOSE, "bce_phy_flags = 0x%08X\n", 4880 sc->bce_phy_flags); 4881 4882 if (sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) { 4883 DBPRINT(sc, BCE_VERBOSE, "SerDes media set/get\n"); 4884 4885 error = ifmedia_ioctl(ifp, ifr, 4886 &sc->bce_ifmedia, command); 4887 } else { 4888 DBPRINT(sc, BCE_VERBOSE, "Copper media set/get\n"); 4889 mii = device_get_softc(sc->bce_miibus); 4890 error = ifmedia_ioctl(ifp, ifr, 4891 &mii->mii_media, command); 4892 } 4893 break; 4894 4895 /* Set interface capability */ 4896 case SIOCSIFCAP: 4897 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 4898 DBPRINT(sc, BCE_INFO, "Received SIOCSIFCAP = 0x%08X\n", (u32) mask); 4899 4900#ifdef DEVICE_POLLING 4901 if (mask & IFCAP_POLLING) { 4902 if (ifr->ifr_reqcap & IFCAP_POLLING) { 4903 4904 /* Setup the poll routine to call. */ 4905 error = ether_poll_register(bce_poll, ifp); 4906 if (error) { 4907 BCE_PRINTF(sc, "%s(%d): Error registering poll function!\n", 4908 __FILE__, __LINE__); 4909 goto bce_ioctl_exit; 4910 } 4911 4912 /* Clear the interrupt. */ 4913 BCE_LOCK(sc); 4914 bce_disable_intr(sc); 4915 4916 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP, 4917 (1 << 16) | sc->bce_rx_quick_cons_trip); 4918 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP, 4919 (1 << 16) | sc->bce_tx_quick_cons_trip); 4920 4921 ifp->if_capenable |= IFCAP_POLLING; 4922 BCE_UNLOCK(sc); 4923 } else { 4924 /* Clear the poll routine. */ 4925 error = ether_poll_deregister(ifp); 4926 4927 /* Enable interrupt even in error case */ 4928 BCE_LOCK(sc); 4929 bce_enable_intr(sc); 4930 4931 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP, 4932 (sc->bce_tx_quick_cons_trip_int << 16) | 4933 sc->bce_tx_quick_cons_trip); 4934 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP, 4935 (sc->bce_rx_quick_cons_trip_int << 16) | 4936 sc->bce_rx_quick_cons_trip); 4937 4938 ifp->if_capenable &= ~IFCAP_POLLING; 4939 BCE_UNLOCK(sc); 4940 } 4941 } 4942#endif /*DEVICE_POLLING */ 4943 4944 /* Toggle the TX checksum capabilites enable flag. */ 4945 if (mask & IFCAP_TXCSUM) { 4946 ifp->if_capenable ^= IFCAP_TXCSUM; 4947 if (IFCAP_TXCSUM & ifp->if_capenable) 4948 ifp->if_hwassist = BCE_IF_HWASSIST; 4949 else 4950 ifp->if_hwassist = 0; 4951 } 4952 4953 /* Toggle the RX checksum capabilities enable flag. */ 4954 if (mask & IFCAP_RXCSUM) { 4955 ifp->if_capenable ^= IFCAP_RXCSUM; 4956 if (IFCAP_RXCSUM & ifp->if_capenable) 4957 ifp->if_hwassist = BCE_IF_HWASSIST; 4958 else 4959 ifp->if_hwassist = 0; 4960 } 4961 4962 /* Toggle VLAN_MTU capabilities enable flag. */ 4963 if (mask & IFCAP_VLAN_MTU) { 4964 BCE_PRINTF(sc, "%s(%d): Changing VLAN_MTU not supported.\n", 4965 __FILE__, __LINE__); 4966 } 4967 4968 /* Toggle VLANHWTAG capabilities enabled flag. */ 4969 if (mask & IFCAP_VLAN_HWTAGGING) { 4970 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) 4971 BCE_PRINTF(sc, "%s(%d): Cannot change VLAN_HWTAGGING while " 4972 "management firmware (ASF/IPMI/UMP) is running!\n", 4973 __FILE__, __LINE__); 4974 else 4975 BCE_PRINTF(sc, "%s(%d): Changing VLAN_HWTAGGING not supported!\n", 4976 __FILE__, __LINE__); 4977 } 4978 4979 break; 4980 default: 4981 DBPRINT(sc, BCE_INFO, "Received unsupported IOCTL: 0x%08X\n", 4982 (u32) command); 4983 4984 /* We don't know how to handle the IOCTL, pass it on. */ 4985 error = ether_ioctl(ifp, command, data); 4986 break; 4987 } 4988 4989#ifdef DEVICE_POLLING 4990bce_ioctl_exit: 4991#endif 4992 4993 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 4994 4995 return(error); 4996} 4997 4998 4999/****************************************************************************/ 5000/* Transmit timeout handler. */ 5001/* */ 5002/* Returns: */ 5003/* Nothing. */ 5004/****************************************************************************/ 5005static void 5006bce_watchdog(struct bce_softc *sc) 5007{ 5008 5009 DBRUN(BCE_WARN_SEND, 5010 bce_dump_driver_state(sc); 5011 bce_dump_status_block(sc)); 5012 5013 BCE_LOCK_ASSERT(sc); 5014 5015 if (sc->watchdog_timer == 0 || --sc->watchdog_timer) 5016 return; 5017 5018 /* 5019 * If we are in this routine because of pause frames, then 5020 * don't reset the hardware. 5021 */ 5022 if (REG_RD(sc, BCE_EMAC_TX_STATUS) & BCE_EMAC_TX_STATUS_XOFFED) 5023 return; 5024 5025 BCE_PRINTF(sc, "%s(%d): Watchdog timeout occurred, resetting!\n", 5026 __FILE__, __LINE__); 5027 5028 /* DBRUN(BCE_FATAL, bce_breakpoint(sc)); */ 5029 5030 sc->bce_ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 5031 5032 bce_init_locked(sc); 5033 sc->bce_ifp->if_oerrors++; 5034 5035} 5036 5037 5038#ifdef DEVICE_POLLING 5039static void 5040bce_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 5041{ 5042 struct bce_softc *sc = ifp->if_softc; 5043 5044 BCE_LOCK_ASSERT(sc); 5045 5046 sc->bce_rxcycles = count; 5047 5048 bus_dmamap_sync(sc->status_tag, sc->status_map, 5049 BUS_DMASYNC_POSTWRITE); 5050 5051 /* Check for any completed RX frames. */ 5052 if (sc->status_block->status_rx_quick_consumer_index0 != 5053 sc->hw_rx_cons) 5054 bce_rx_intr(sc); 5055 5056 /* Check for any completed TX frames. */ 5057 if (sc->status_block->status_tx_quick_consumer_index0 != 5058 sc->hw_tx_cons) 5059 bce_tx_intr(sc); 5060 5061 /* Check for new frames to transmit. */ 5062 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 5063 bce_start_locked(ifp); 5064 5065} 5066 5067 5068static void 5069bce_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 5070{ 5071 struct bce_softc *sc = ifp->if_softc; 5072 5073 BCE_LOCK(sc); 5074 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 5075 bce_poll_locked(ifp, cmd, count); 5076 BCE_UNLOCK(sc); 5077} 5078#endif /* DEVICE_POLLING */ 5079 5080 5081#if 0 5082static inline int 5083bce_has_work(struct bce_softc *sc) 5084{ 5085 struct status_block *stat = sc->status_block; 5086 5087 if ((stat->status_rx_quick_consumer_index0 != sc->hw_rx_cons) || 5088 (stat->status_tx_quick_consumer_index0 != sc->hw_tx_cons)) 5089 return 1; 5090 5091 if (((stat->status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != 0) != 5092 bp->link_up) 5093 return 1; 5094 5095 return 0; 5096} 5097#endif 5098 5099 5100/* 5101 * Interrupt handler. 5102 */ 5103/****************************************************************************/ 5104/* Main interrupt entry point. Verifies that the controller generated the */ 5105/* interrupt and then calls a separate routine for handle the various */ 5106/* interrupt causes (PHY, TX, RX). */ 5107/* */ 5108/* Returns: */ 5109/* 0 for success, positive value for failure. */ 5110/****************************************************************************/ 5111static void 5112bce_intr(void *xsc) 5113{ 5114 struct bce_softc *sc; 5115 struct ifnet *ifp; 5116 u32 status_attn_bits; 5117 5118 sc = xsc; 5119 ifp = sc->bce_ifp; 5120 5121 BCE_LOCK(sc); 5122 5123 DBRUNIF(1, sc->interrupts_generated++); 5124 5125#ifdef DEVICE_POLLING 5126 if (ifp->if_capenable & IFCAP_POLLING) { 5127 DBPRINT(sc, BCE_INFO, "Polling enabled!\n"); 5128 goto bce_intr_exit; 5129 } 5130#endif 5131 5132 bus_dmamap_sync(sc->status_tag, sc->status_map, 5133 BUS_DMASYNC_POSTWRITE); 5134 5135 /* 5136 * If the hardware status block index 5137 * matches the last value read by the 5138 * driver and we haven't asserted our 5139 * interrupt then there's nothing to do. 5140 */ 5141 if ((sc->status_block->status_idx == sc->last_status_idx) && 5142 (REG_RD(sc, BCE_PCICFG_MISC_STATUS) & BCE_PCICFG_MISC_STATUS_INTA_VALUE)) 5143 goto bce_intr_exit; 5144 5145 /* Ack the interrupt and stop others from occuring. */ 5146 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 5147 BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM | 5148 BCE_PCICFG_INT_ACK_CMD_MASK_INT); 5149 5150 /* Keep processing data as long as there is work to do. */ 5151 for (;;) { 5152 5153 status_attn_bits = sc->status_block->status_attn_bits; 5154 5155 DBRUNIF(DB_RANDOMTRUE(bce_debug_unexpected_attention), 5156 BCE_PRINTF(sc, "Simulating unexpected status attention bit set."); 5157 status_attn_bits = status_attn_bits | STATUS_ATTN_BITS_PARITY_ERROR); 5158 5159 /* Was it a link change interrupt? */ 5160 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != 5161 (sc->status_block->status_attn_bits_ack & STATUS_ATTN_BITS_LINK_STATE)) 5162 bce_phy_intr(sc); 5163 5164 /* If any other attention is asserted then the chip is toast. */ 5165 if (((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) != 5166 (sc->status_block->status_attn_bits_ack & 5167 ~STATUS_ATTN_BITS_LINK_STATE))) { 5168 5169 DBRUN(1, sc->unexpected_attentions++); 5170 5171 BCE_PRINTF(sc, "%s(%d): Fatal attention detected: 0x%08X\n", 5172 __FILE__, __LINE__, sc->status_block->status_attn_bits); 5173 5174 DBRUN(BCE_FATAL, 5175 if (bce_debug_unexpected_attention == 0) 5176 bce_breakpoint(sc)); 5177 5178 bce_init_locked(sc); 5179 goto bce_intr_exit; 5180 } 5181 5182 /* Check for any completed RX frames. */ 5183 if (sc->status_block->status_rx_quick_consumer_index0 != sc->hw_rx_cons) 5184 bce_rx_intr(sc); 5185 5186 /* Check for any completed TX frames. */ 5187 if (sc->status_block->status_tx_quick_consumer_index0 != sc->hw_tx_cons) 5188 bce_tx_intr(sc); 5189 5190 /* Save the status block index value for use during the next interrupt. */ 5191 sc->last_status_idx = sc->status_block->status_idx; 5192 5193 /* Prevent speculative reads from getting ahead of the status block. */ 5194 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 5195 BUS_SPACE_BARRIER_READ); 5196 5197 /* If there's no work left then exit the interrupt service routine. */ 5198 if ((sc->status_block->status_rx_quick_consumer_index0 == sc->hw_rx_cons) && 5199 (sc->status_block->status_tx_quick_consumer_index0 == sc->hw_tx_cons)) 5200 break; 5201 5202 } 5203 5204 bus_dmamap_sync(sc->status_tag, sc->status_map, 5205 BUS_DMASYNC_PREWRITE); 5206 5207 /* Re-enable interrupts. */ 5208 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 5209 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx | 5210 BCE_PCICFG_INT_ACK_CMD_MASK_INT); 5211 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 5212 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx); 5213 5214 /* Handle any frames that arrived while handling the interrupt. */ 5215 if (ifp->if_drv_flags & IFF_DRV_RUNNING && !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 5216 bce_start_locked(ifp); 5217 5218bce_intr_exit: 5219 BCE_UNLOCK(sc); 5220} 5221 5222 5223/****************************************************************************/ 5224/* Programs the various packet receive modes (broadcast and multicast). */ 5225/* */ 5226/* Returns: */ 5227/* Nothing. */ 5228/****************************************************************************/ 5229static void 5230bce_set_rx_mode(struct bce_softc *sc) 5231{ 5232 struct ifnet *ifp; 5233 struct ifmultiaddr *ifma; 5234 u32 hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 5235 u32 rx_mode, sort_mode; 5236 int h, i; 5237 5238 BCE_LOCK_ASSERT(sc); 5239 5240 ifp = sc->bce_ifp; 5241 5242 /* Initialize receive mode default settings. */ 5243 rx_mode = sc->rx_mode & ~(BCE_EMAC_RX_MODE_PROMISCUOUS | 5244 BCE_EMAC_RX_MODE_KEEP_VLAN_TAG); 5245 sort_mode = 1 | BCE_RPM_SORT_USER0_BC_EN; 5246 5247 /* 5248 * ASF/IPMI/UMP firmware requires that VLAN tag stripping 5249 * be enbled. 5250 */ 5251 if (!(BCE_IF_CAPABILITIES & IFCAP_VLAN_HWTAGGING) && 5252 (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG))) 5253 rx_mode |= BCE_EMAC_RX_MODE_KEEP_VLAN_TAG; 5254 5255 /* 5256 * Check for promiscuous, all multicast, or selected 5257 * multicast address filtering. 5258 */ 5259 if (ifp->if_flags & IFF_PROMISC) { 5260 DBPRINT(sc, BCE_INFO, "Enabling promiscuous mode.\n"); 5261 5262 /* Enable promiscuous mode. */ 5263 rx_mode |= BCE_EMAC_RX_MODE_PROMISCUOUS; 5264 sort_mode |= BCE_RPM_SORT_USER0_PROM_EN; 5265 } else if (ifp->if_flags & IFF_ALLMULTI) { 5266 DBPRINT(sc, BCE_INFO, "Enabling all multicast mode.\n"); 5267 5268 /* Enable all multicast addresses. */ 5269 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) { 5270 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), 0xffffffff); 5271 } 5272 sort_mode |= BCE_RPM_SORT_USER0_MC_EN; 5273 } else { 5274 /* Accept one or more multicast(s). */ 5275 DBPRINT(sc, BCE_INFO, "Enabling selective multicast mode.\n"); 5276 5277 IF_ADDR_LOCK(ifp); 5278 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 5279 if (ifma->ifma_addr->sa_family != AF_LINK) 5280 continue; 5281 h = ether_crc32_le(LLADDR((struct sockaddr_dl *) 5282 ifma->ifma_addr), ETHER_ADDR_LEN) & 0xFF; 5283 hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F); 5284 } 5285 IF_ADDR_UNLOCK(ifp); 5286 5287 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) 5288 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), hashes[i]); 5289 5290 sort_mode |= BCE_RPM_SORT_USER0_MC_HSH_EN; 5291 } 5292 5293 /* Only make changes if the recive mode has actually changed. */ 5294 if (rx_mode != sc->rx_mode) { 5295 DBPRINT(sc, BCE_VERBOSE, "Enabling new receive mode: 0x%08X\n", 5296 rx_mode); 5297 5298 sc->rx_mode = rx_mode; 5299 REG_WR(sc, BCE_EMAC_RX_MODE, rx_mode); 5300 } 5301 5302 /* Disable and clear the exisitng sort before enabling a new sort. */ 5303 REG_WR(sc, BCE_RPM_SORT_USER0, 0x0); 5304 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode); 5305 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode | BCE_RPM_SORT_USER0_ENA); 5306} 5307 5308 5309/****************************************************************************/ 5310/* Called periodically to updates statistics from the controllers */ 5311/* statistics block. */ 5312/* */ 5313/* Returns: */ 5314/* Nothing. */ 5315/****************************************************************************/ 5316static void 5317bce_stats_update(struct bce_softc *sc) 5318{ 5319 struct ifnet *ifp; 5320 struct statistics_block *stats; 5321 5322 DBPRINT(sc, BCE_EXCESSIVE, "Entering %s()\n", __FUNCTION__); 5323 5324 ifp = sc->bce_ifp; 5325 5326 stats = (struct statistics_block *) sc->stats_block; 5327 5328 /* 5329 * Update the interface statistics from the 5330 * hardware statistics. 5331 */ 5332 ifp->if_collisions = (u_long) stats->stat_EtherStatsCollisions; 5333 5334 ifp->if_ierrors = (u_long) stats->stat_EtherStatsUndersizePkts + 5335 (u_long) stats->stat_EtherStatsOverrsizePkts + 5336 (u_long) stats->stat_IfInMBUFDiscards + 5337 (u_long) stats->stat_Dot3StatsAlignmentErrors + 5338 (u_long) stats->stat_Dot3StatsFCSErrors; 5339 5340 ifp->if_oerrors = (u_long) stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors + 5341 (u_long) stats->stat_Dot3StatsExcessiveCollisions + 5342 (u_long) stats->stat_Dot3StatsLateCollisions; 5343 5344 /* 5345 * Certain controllers don't report 5346 * carrier sense errors correctly. 5347 * See errata E11_5708CA0_1165. 5348 */ 5349 if (!(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) && 5350 !(BCE_CHIP_ID(sc) == BCE_CHIP_ID_5708_A0)) 5351 ifp->if_oerrors += (u_long) stats->stat_Dot3StatsCarrierSenseErrors; 5352 5353 /* 5354 * Update the sysctl statistics from the 5355 * hardware statistics. 5356 */ 5357 sc->stat_IfHCInOctets = 5358 ((u64) stats->stat_IfHCInOctets_hi << 32) + 5359 (u64) stats->stat_IfHCInOctets_lo; 5360 5361 sc->stat_IfHCInBadOctets = 5362 ((u64) stats->stat_IfHCInBadOctets_hi << 32) + 5363 (u64) stats->stat_IfHCInBadOctets_lo; 5364 5365 sc->stat_IfHCOutOctets = 5366 ((u64) stats->stat_IfHCOutOctets_hi << 32) + 5367 (u64) stats->stat_IfHCOutOctets_lo; 5368 5369 sc->stat_IfHCOutBadOctets = 5370 ((u64) stats->stat_IfHCOutBadOctets_hi << 32) + 5371 (u64) stats->stat_IfHCOutBadOctets_lo; 5372 5373 sc->stat_IfHCInUcastPkts = 5374 ((u64) stats->stat_IfHCInUcastPkts_hi << 32) + 5375 (u64) stats->stat_IfHCInUcastPkts_lo; 5376 5377 sc->stat_IfHCInMulticastPkts = 5378 ((u64) stats->stat_IfHCInMulticastPkts_hi << 32) + 5379 (u64) stats->stat_IfHCInMulticastPkts_lo; 5380 5381 sc->stat_IfHCInBroadcastPkts = 5382 ((u64) stats->stat_IfHCInBroadcastPkts_hi << 32) + 5383 (u64) stats->stat_IfHCInBroadcastPkts_lo; 5384 5385 sc->stat_IfHCOutUcastPkts = 5386 ((u64) stats->stat_IfHCOutUcastPkts_hi << 32) + 5387 (u64) stats->stat_IfHCOutUcastPkts_lo; 5388 5389 sc->stat_IfHCOutMulticastPkts = 5390 ((u64) stats->stat_IfHCOutMulticastPkts_hi << 32) + 5391 (u64) stats->stat_IfHCOutMulticastPkts_lo; 5392 5393 sc->stat_IfHCOutBroadcastPkts = 5394 ((u64) stats->stat_IfHCOutBroadcastPkts_hi << 32) + 5395 (u64) stats->stat_IfHCOutBroadcastPkts_lo; 5396 5397 sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors = 5398 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors; 5399 5400 sc->stat_Dot3StatsCarrierSenseErrors = 5401 stats->stat_Dot3StatsCarrierSenseErrors; 5402 5403 sc->stat_Dot3StatsFCSErrors = 5404 stats->stat_Dot3StatsFCSErrors; 5405 5406 sc->stat_Dot3StatsAlignmentErrors = 5407 stats->stat_Dot3StatsAlignmentErrors; 5408 5409 sc->stat_Dot3StatsSingleCollisionFrames = 5410 stats->stat_Dot3StatsSingleCollisionFrames; 5411 5412 sc->stat_Dot3StatsMultipleCollisionFrames = 5413 stats->stat_Dot3StatsMultipleCollisionFrames; 5414 5415 sc->stat_Dot3StatsDeferredTransmissions = 5416 stats->stat_Dot3StatsDeferredTransmissions; 5417 5418 sc->stat_Dot3StatsExcessiveCollisions = 5419 stats->stat_Dot3StatsExcessiveCollisions; 5420 5421 sc->stat_Dot3StatsLateCollisions = 5422 stats->stat_Dot3StatsLateCollisions; 5423 5424 sc->stat_EtherStatsCollisions = 5425 stats->stat_EtherStatsCollisions; 5426 5427 sc->stat_EtherStatsFragments = 5428 stats->stat_EtherStatsFragments; 5429 5430 sc->stat_EtherStatsJabbers = 5431 stats->stat_EtherStatsJabbers; 5432 5433 sc->stat_EtherStatsUndersizePkts = 5434 stats->stat_EtherStatsUndersizePkts; 5435 5436 sc->stat_EtherStatsOverrsizePkts = 5437 stats->stat_EtherStatsOverrsizePkts; 5438 5439 sc->stat_EtherStatsPktsRx64Octets = 5440 stats->stat_EtherStatsPktsRx64Octets; 5441 5442 sc->stat_EtherStatsPktsRx65Octetsto127Octets = 5443 stats->stat_EtherStatsPktsRx65Octetsto127Octets; 5444 5445 sc->stat_EtherStatsPktsRx128Octetsto255Octets = 5446 stats->stat_EtherStatsPktsRx128Octetsto255Octets; 5447 5448 sc->stat_EtherStatsPktsRx256Octetsto511Octets = 5449 stats->stat_EtherStatsPktsRx256Octetsto511Octets; 5450 5451 sc->stat_EtherStatsPktsRx512Octetsto1023Octets = 5452 stats->stat_EtherStatsPktsRx512Octetsto1023Octets; 5453 5454 sc->stat_EtherStatsPktsRx1024Octetsto1522Octets = 5455 stats->stat_EtherStatsPktsRx1024Octetsto1522Octets; 5456 5457 sc->stat_EtherStatsPktsRx1523Octetsto9022Octets = 5458 stats->stat_EtherStatsPktsRx1523Octetsto9022Octets; 5459 5460 sc->stat_EtherStatsPktsTx64Octets = 5461 stats->stat_EtherStatsPktsTx64Octets; 5462 5463 sc->stat_EtherStatsPktsTx65Octetsto127Octets = 5464 stats->stat_EtherStatsPktsTx65Octetsto127Octets; 5465 5466 sc->stat_EtherStatsPktsTx128Octetsto255Octets = 5467 stats->stat_EtherStatsPktsTx128Octetsto255Octets; 5468 5469 sc->stat_EtherStatsPktsTx256Octetsto511Octets = 5470 stats->stat_EtherStatsPktsTx256Octetsto511Octets; 5471 5472 sc->stat_EtherStatsPktsTx512Octetsto1023Octets = 5473 stats->stat_EtherStatsPktsTx512Octetsto1023Octets; 5474 5475 sc->stat_EtherStatsPktsTx1024Octetsto1522Octets = 5476 stats->stat_EtherStatsPktsTx1024Octetsto1522Octets; 5477 5478 sc->stat_EtherStatsPktsTx1523Octetsto9022Octets = 5479 stats->stat_EtherStatsPktsTx1523Octetsto9022Octets; 5480 5481 sc->stat_XonPauseFramesReceived = 5482 stats->stat_XonPauseFramesReceived; 5483 5484 sc->stat_XoffPauseFramesReceived = 5485 stats->stat_XoffPauseFramesReceived; 5486 5487 sc->stat_OutXonSent = 5488 stats->stat_OutXonSent; 5489 5490 sc->stat_OutXoffSent = 5491 stats->stat_OutXoffSent; 5492 5493 sc->stat_FlowControlDone = 5494 stats->stat_FlowControlDone; 5495 5496 sc->stat_MacControlFramesReceived = 5497 stats->stat_MacControlFramesReceived; 5498 5499 sc->stat_XoffStateEntered = 5500 stats->stat_XoffStateEntered; 5501 5502 sc->stat_IfInFramesL2FilterDiscards = 5503 stats->stat_IfInFramesL2FilterDiscards; 5504 5505 sc->stat_IfInRuleCheckerDiscards = 5506 stats->stat_IfInRuleCheckerDiscards; 5507 5508 sc->stat_IfInFTQDiscards = 5509 stats->stat_IfInFTQDiscards; 5510 5511 sc->stat_IfInMBUFDiscards = 5512 stats->stat_IfInMBUFDiscards; 5513 5514 sc->stat_IfInRuleCheckerP4Hit = 5515 stats->stat_IfInRuleCheckerP4Hit; 5516 5517 sc->stat_CatchupInRuleCheckerDiscards = 5518 stats->stat_CatchupInRuleCheckerDiscards; 5519 5520 sc->stat_CatchupInFTQDiscards = 5521 stats->stat_CatchupInFTQDiscards; 5522 5523 sc->stat_CatchupInMBUFDiscards = 5524 stats->stat_CatchupInMBUFDiscards; 5525 5526 sc->stat_CatchupInRuleCheckerP4Hit = 5527 stats->stat_CatchupInRuleCheckerP4Hit; 5528 5529 DBPRINT(sc, BCE_EXCESSIVE, "Exiting %s()\n", __FUNCTION__); 5530} 5531 5532 5533static void 5534bce_tick(void *xsc) 5535{ 5536 struct bce_softc *sc = xsc; 5537 struct mii_data *mii = NULL; 5538 struct ifnet *ifp; 5539 u32 msg; 5540 5541 ifp = sc->bce_ifp; 5542 5543 BCE_LOCK_ASSERT(sc); 5544 5545 /* Tell the firmware that the driver is still running. */ 5546#ifdef BCE_DEBUG 5547 msg = (u32) BCE_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE; 5548#else 5549 msg = (u32) ++sc->bce_fw_drv_pulse_wr_seq; 5550#endif 5551 REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_PULSE_MB, msg); 5552 5553 /* Update the statistics from the hardware statistics block. */ 5554 bce_stats_update(sc); 5555 5556 /* Check that chip hasn't hang. */ 5557 bce_watchdog(sc); 5558 5559 /* Schedule the next tick. */ 5560 callout_reset( 5561 &sc->bce_stat_ch, /* callout */ 5562 hz, /* ticks */ 5563 bce_tick, /* function */ 5564 sc); /* function argument */ 5565 5566 /* If link is up already up then we're done. */ 5567 if (sc->bce_link) 5568 goto bce_tick_locked_exit; 5569 5570 /* DRC - ToDo: Add SerDes support and check SerDes link here. */ 5571 5572 mii = device_get_softc(sc->bce_miibus); 5573 mii_tick(mii); 5574 5575 /* Check if the link has come up. */ 5576 if (!sc->bce_link && mii->mii_media_status & IFM_ACTIVE && 5577 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 5578 sc->bce_link++; 5579 if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 5580 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) && 5581 bootverbose) 5582 BCE_PRINTF(sc, "Gigabit link up\n"); 5583 /* Now that link is up, handle any outstanding TX traffic. */ 5584 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 5585 bce_start_locked(ifp); 5586 } 5587 5588bce_tick_locked_exit: 5589 return; 5590} 5591 5592 5593#ifdef BCE_DEBUG 5594/****************************************************************************/ 5595/* Allows the driver state to be dumped through the sysctl interface. */ 5596/* */ 5597/* Returns: */ 5598/* 0 for success, positive value for failure. */ 5599/****************************************************************************/ 5600static int 5601bce_sysctl_driver_state(SYSCTL_HANDLER_ARGS) 5602{ 5603 int error; 5604 int result; 5605 struct bce_softc *sc; 5606 5607 result = -1; 5608 error = sysctl_handle_int(oidp, &result, 0, req); 5609 5610 if (error || !req->newptr) 5611 return (error); 5612 5613 if (result == 1) { 5614 sc = (struct bce_softc *)arg1; 5615 bce_dump_driver_state(sc); 5616 } 5617 5618 return error; 5619} 5620 5621 5622/****************************************************************************/ 5623/* Allows the hardware state to be dumped through the sysctl interface. */ 5624/* */ 5625/* Returns: */ 5626/* 0 for success, positive value for failure. */ 5627/****************************************************************************/ 5628static int 5629bce_sysctl_hw_state(SYSCTL_HANDLER_ARGS) 5630{ 5631 int error; 5632 int result; 5633 struct bce_softc *sc; 5634 5635 result = -1; 5636 error = sysctl_handle_int(oidp, &result, 0, req); 5637 5638 if (error || !req->newptr) 5639 return (error); 5640 5641 if (result == 1) { 5642 sc = (struct bce_softc *)arg1; 5643 bce_dump_hw_state(sc); 5644 } 5645 5646 return error; 5647} 5648 5649 5650/****************************************************************************/ 5651/* */ 5652/* */ 5653/* Returns: */ 5654/* 0 for success, positive value for failure. */ 5655/****************************************************************************/ 5656static int 5657bce_sysctl_dump_rx_chain(SYSCTL_HANDLER_ARGS) 5658{ 5659 int error; 5660 int result; 5661 struct bce_softc *sc; 5662 5663 result = -1; 5664 error = sysctl_handle_int(oidp, &result, 0, req); 5665 5666 if (error || !req->newptr) 5667 return (error); 5668 5669 if (result == 1) { 5670 sc = (struct bce_softc *)arg1; 5671 bce_dump_rx_chain(sc, 0, USABLE_RX_BD); 5672 } 5673 5674 return error; 5675} 5676 5677 5678/****************************************************************************/ 5679/* */ 5680/* */ 5681/* Returns: */ 5682/* 0 for success, positive value for failure. */ 5683/****************************************************************************/ 5684static int 5685bce_sysctl_breakpoint(SYSCTL_HANDLER_ARGS) 5686{ 5687 int error; 5688 int result; 5689 struct bce_softc *sc; 5690 5691 result = -1; 5692 error = sysctl_handle_int(oidp, &result, 0, req); 5693 5694 if (error || !req->newptr) 5695 return (error); 5696 5697 if (result == 1) { 5698 sc = (struct bce_softc *)arg1; 5699 bce_breakpoint(sc); 5700 } 5701 5702 return error; 5703} 5704#endif 5705 5706 5707/****************************************************************************/ 5708/* Adds any sysctl parameters for tuning or debugging purposes. */ 5709/* */ 5710/* Returns: */ 5711/* 0 for success, positive value for failure. */ 5712/****************************************************************************/ 5713static void 5714bce_add_sysctls(struct bce_softc *sc) 5715{ 5716 struct sysctl_ctx_list *ctx; 5717 struct sysctl_oid_list *children; 5718 5719 ctx = device_get_sysctl_ctx(sc->bce_dev); 5720 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bce_dev)); 5721 5722 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, 5723 "driver_version", 5724 CTLFLAG_RD, &bce_driver_version, 5725 0, "bce driver version"); 5726 5727#ifdef BCE_DEBUG 5728 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 5729 "rx_low_watermark", 5730 CTLFLAG_RD, &sc->rx_low_watermark, 5731 0, "Lowest level of free rx_bd's"); 5732 5733 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 5734 "tx_hi_watermark", 5735 CTLFLAG_RD, &sc->tx_hi_watermark, 5736 0, "Highest level of used tx_bd's"); 5737 5738 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 5739 "l2fhdr_status_errors", 5740 CTLFLAG_RD, &sc->l2fhdr_status_errors, 5741 0, "l2_fhdr status errors"); 5742 5743 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 5744 "unexpected_attentions", 5745 CTLFLAG_RD, &sc->unexpected_attentions, 5746 0, "unexpected attentions"); 5747 5748 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 5749 "lost_status_block_updates", 5750 CTLFLAG_RD, &sc->lost_status_block_updates, 5751 0, "lost status block updates"); 5752 5753 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 5754 "mbuf_alloc_failed", 5755 CTLFLAG_RD, &sc->mbuf_alloc_failed, 5756 0, "mbuf cluster allocation failures"); 5757#endif 5758 5759 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 5760 "stat_IfHcInOctets", 5761 CTLFLAG_RD, &sc->stat_IfHCInOctets, 5762 "Bytes received"); 5763 5764 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 5765 "stat_IfHCInBadOctets", 5766 CTLFLAG_RD, &sc->stat_IfHCInBadOctets, 5767 "Bad bytes received"); 5768 5769 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 5770 "stat_IfHCOutOctets", 5771 CTLFLAG_RD, &sc->stat_IfHCOutOctets, 5772 "Bytes sent"); 5773 5774 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 5775 "stat_IfHCOutBadOctets", 5776 CTLFLAG_RD, &sc->stat_IfHCOutBadOctets, 5777 "Bad bytes sent"); 5778 5779 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 5780 "stat_IfHCInUcastPkts", 5781 CTLFLAG_RD, &sc->stat_IfHCInUcastPkts, 5782 "Unicast packets received"); 5783 5784 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 5785 "stat_IfHCInMulticastPkts", 5786 CTLFLAG_RD, &sc->stat_IfHCInMulticastPkts, 5787 "Multicast packets received"); 5788 5789 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 5790 "stat_IfHCInBroadcastPkts", 5791 CTLFLAG_RD, &sc->stat_IfHCInBroadcastPkts, 5792 "Broadcast packets received"); 5793 5794 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 5795 "stat_IfHCOutUcastPkts", 5796 CTLFLAG_RD, &sc->stat_IfHCOutUcastPkts, 5797 "Unicast packets sent"); 5798 5799 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 5800 "stat_IfHCOutMulticastPkts", 5801 CTLFLAG_RD, &sc->stat_IfHCOutMulticastPkts, 5802 "Multicast packets sent"); 5803 5804 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 5805 "stat_IfHCOutBroadcastPkts", 5806 CTLFLAG_RD, &sc->stat_IfHCOutBroadcastPkts, 5807 "Broadcast packets sent"); 5808 5809 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5810 "stat_emac_tx_stat_dot3statsinternalmactransmiterrors", 5811 CTLFLAG_RD, &sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors, 5812 0, "Internal MAC transmit errors"); 5813 5814 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5815 "stat_Dot3StatsCarrierSenseErrors", 5816 CTLFLAG_RD, &sc->stat_Dot3StatsCarrierSenseErrors, 5817 0, "Carrier sense errors"); 5818 5819 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5820 "stat_Dot3StatsFCSErrors", 5821 CTLFLAG_RD, &sc->stat_Dot3StatsFCSErrors, 5822 0, "Frame check sequence errors"); 5823 5824 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5825 "stat_Dot3StatsAlignmentErrors", 5826 CTLFLAG_RD, &sc->stat_Dot3StatsAlignmentErrors, 5827 0, "Alignment errors"); 5828 5829 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5830 "stat_Dot3StatsSingleCollisionFrames", 5831 CTLFLAG_RD, &sc->stat_Dot3StatsSingleCollisionFrames, 5832 0, "Single Collision Frames"); 5833 5834 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5835 "stat_Dot3StatsMultipleCollisionFrames", 5836 CTLFLAG_RD, &sc->stat_Dot3StatsMultipleCollisionFrames, 5837 0, "Multiple Collision Frames"); 5838 5839 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5840 "stat_Dot3StatsDeferredTransmissions", 5841 CTLFLAG_RD, &sc->stat_Dot3StatsDeferredTransmissions, 5842 0, "Deferred Transmissions"); 5843 5844 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5845 "stat_Dot3StatsExcessiveCollisions", 5846 CTLFLAG_RD, &sc->stat_Dot3StatsExcessiveCollisions, 5847 0, "Excessive Collisions"); 5848 5849 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5850 "stat_Dot3StatsLateCollisions", 5851 CTLFLAG_RD, &sc->stat_Dot3StatsLateCollisions, 5852 0, "Late Collisions"); 5853 5854 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5855 "stat_EtherStatsCollisions", 5856 CTLFLAG_RD, &sc->stat_EtherStatsCollisions, 5857 0, "Collisions"); 5858 5859 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5860 "stat_EtherStatsFragments", 5861 CTLFLAG_RD, &sc->stat_EtherStatsFragments, 5862 0, "Fragments"); 5863 5864 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5865 "stat_EtherStatsJabbers", 5866 CTLFLAG_RD, &sc->stat_EtherStatsJabbers, 5867 0, "Jabbers"); 5868 5869 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5870 "stat_EtherStatsUndersizePkts", 5871 CTLFLAG_RD, &sc->stat_EtherStatsUndersizePkts, 5872 0, "Undersize packets"); 5873 5874 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5875 "stat_EtherStatsOverrsizePkts", 5876 CTLFLAG_RD, &sc->stat_EtherStatsOverrsizePkts, 5877 0, "stat_EtherStatsOverrsizePkts"); 5878 5879 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5880 "stat_EtherStatsPktsRx64Octets", 5881 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx64Octets, 5882 0, "Bytes received in 64 byte packets"); 5883 5884 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5885 "stat_EtherStatsPktsRx65Octetsto127Octets", 5886 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx65Octetsto127Octets, 5887 0, "Bytes received in 65 to 127 byte packets"); 5888 5889 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5890 "stat_EtherStatsPktsRx128Octetsto255Octets", 5891 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx128Octetsto255Octets, 5892 0, "Bytes received in 128 to 255 byte packets"); 5893 5894 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5895 "stat_EtherStatsPktsRx256Octetsto511Octets", 5896 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx256Octetsto511Octets, 5897 0, "Bytes received in 256 to 511 byte packets"); 5898 5899 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5900 "stat_EtherStatsPktsRx512Octetsto1023Octets", 5901 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx512Octetsto1023Octets, 5902 0, "Bytes received in 512 to 1023 byte packets"); 5903 5904 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5905 "stat_EtherStatsPktsRx1024Octetsto1522Octets", 5906 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1024Octetsto1522Octets, 5907 0, "Bytes received in 1024 t0 1522 byte packets"); 5908 5909 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5910 "stat_EtherStatsPktsRx1523Octetsto9022Octets", 5911 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1523Octetsto9022Octets, 5912 0, "Bytes received in 1523 to 9022 byte packets"); 5913 5914 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5915 "stat_EtherStatsPktsTx64Octets", 5916 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx64Octets, 5917 0, "Bytes sent in 64 byte packets"); 5918 5919 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5920 "stat_EtherStatsPktsTx65Octetsto127Octets", 5921 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx65Octetsto127Octets, 5922 0, "Bytes sent in 65 to 127 byte packets"); 5923 5924 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5925 "stat_EtherStatsPktsTx128Octetsto255Octets", 5926 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx128Octetsto255Octets, 5927 0, "Bytes sent in 128 to 255 byte packets"); 5928 5929 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5930 "stat_EtherStatsPktsTx256Octetsto511Octets", 5931 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx256Octetsto511Octets, 5932 0, "Bytes sent in 256 to 511 byte packets"); 5933 5934 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5935 "stat_EtherStatsPktsTx512Octetsto1023Octets", 5936 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx512Octetsto1023Octets, 5937 0, "Bytes sent in 512 to 1023 byte packets"); 5938 5939 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5940 "stat_EtherStatsPktsTx1024Octetsto1522Octets", 5941 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1024Octetsto1522Octets, 5942 0, "Bytes sent in 1024 to 1522 byte packets"); 5943 5944 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5945 "stat_EtherStatsPktsTx1523Octetsto9022Octets", 5946 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1523Octetsto9022Octets, 5947 0, "Bytes sent in 1523 to 9022 byte packets"); 5948 5949 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5950 "stat_XonPauseFramesReceived", 5951 CTLFLAG_RD, &sc->stat_XonPauseFramesReceived, 5952 0, "XON pause frames receved"); 5953 5954 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5955 "stat_XoffPauseFramesReceived", 5956 CTLFLAG_RD, &sc->stat_XoffPauseFramesReceived, 5957 0, "XOFF pause frames received"); 5958 5959 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5960 "stat_OutXonSent", 5961 CTLFLAG_RD, &sc->stat_OutXonSent, 5962 0, "XON pause frames sent"); 5963 5964 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5965 "stat_OutXoffSent", 5966 CTLFLAG_RD, &sc->stat_OutXoffSent, 5967 0, "XOFF pause frames sent"); 5968 5969 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5970 "stat_FlowControlDone", 5971 CTLFLAG_RD, &sc->stat_FlowControlDone, 5972 0, "Flow control done"); 5973 5974 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5975 "stat_MacControlFramesReceived", 5976 CTLFLAG_RD, &sc->stat_MacControlFramesReceived, 5977 0, "MAC control frames received"); 5978 5979 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5980 "stat_XoffStateEntered", 5981 CTLFLAG_RD, &sc->stat_XoffStateEntered, 5982 0, "XOFF state entered"); 5983 5984 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5985 "stat_IfInFramesL2FilterDiscards", 5986 CTLFLAG_RD, &sc->stat_IfInFramesL2FilterDiscards, 5987 0, "Received L2 packets discarded"); 5988 5989 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5990 "stat_IfInRuleCheckerDiscards", 5991 CTLFLAG_RD, &sc->stat_IfInRuleCheckerDiscards, 5992 0, "Received packets discarded by rule"); 5993 5994 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5995 "stat_IfInFTQDiscards", 5996 CTLFLAG_RD, &sc->stat_IfInFTQDiscards, 5997 0, "Received packet FTQ discards"); 5998 5999 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6000 "stat_IfInMBUFDiscards", 6001 CTLFLAG_RD, &sc->stat_IfInMBUFDiscards, 6002 0, "Received packets discarded due to lack of controller buffer memory"); 6003 6004 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6005 "stat_IfInRuleCheckerP4Hit", 6006 CTLFLAG_RD, &sc->stat_IfInRuleCheckerP4Hit, 6007 0, "Received packets rule checker hits"); 6008 6009 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6010 "stat_CatchupInRuleCheckerDiscards", 6011 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerDiscards, 6012 0, "Received packets discarded in Catchup path"); 6013 6014 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6015 "stat_CatchupInFTQDiscards", 6016 CTLFLAG_RD, &sc->stat_CatchupInFTQDiscards, 6017 0, "Received packets discarded in FTQ in Catchup path"); 6018 6019 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6020 "stat_CatchupInMBUFDiscards", 6021 CTLFLAG_RD, &sc->stat_CatchupInMBUFDiscards, 6022 0, "Received packets discarded in controller buffer memory in Catchup path"); 6023 6024 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6025 "stat_CatchupInRuleCheckerP4Hit", 6026 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerP4Hit, 6027 0, "Received packets rule checker hits in Catchup path"); 6028 6029#ifdef BCE_DEBUG 6030 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 6031 "driver_state", CTLTYPE_INT | CTLFLAG_RW, 6032 (void *)sc, 0, 6033 bce_sysctl_driver_state, "I", "Drive state information"); 6034 6035 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 6036 "hw_state", CTLTYPE_INT | CTLFLAG_RW, 6037 (void *)sc, 0, 6038 bce_sysctl_hw_state, "I", "Hardware state information"); 6039 6040 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 6041 "dump_rx_chain", CTLTYPE_INT | CTLFLAG_RW, 6042 (void *)sc, 0, 6043 bce_sysctl_dump_rx_chain, "I", "Dump rx_bd chain"); 6044 6045 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 6046 "breakpoint", CTLTYPE_INT | CTLFLAG_RW, 6047 (void *)sc, 0, 6048 bce_sysctl_breakpoint, "I", "Driver breakpoint"); 6049#endif 6050 6051} 6052 6053 6054/****************************************************************************/ 6055/* BCE Debug Routines */ 6056/****************************************************************************/ 6057#ifdef BCE_DEBUG 6058 6059/****************************************************************************/ 6060/* Prints out information about an mbuf. */ 6061/* */ 6062/* Returns: */ 6063/* Nothing. */ 6064/****************************************************************************/ 6065static void 6066bce_dump_mbuf(struct bce_softc *sc, struct mbuf *m) 6067{ 6068 u32 val_hi, val_lo; 6069 struct mbuf *mp = m; 6070 6071 if (m == NULL) { 6072 /* Index out of range. */ 6073 printf("mbuf ptr is null!\n"); 6074 return; 6075 } 6076 6077 while (mp) { 6078 val_hi = BCE_ADDR_HI(mp); 6079 val_lo = BCE_ADDR_LO(mp); 6080 BCE_PRINTF(sc, "mbuf: vaddr = 0x%08X:%08X, m_len = %d, m_flags = ", 6081 val_hi, val_lo, mp->m_len); 6082 6083 if (mp->m_flags & M_EXT) 6084 printf("M_EXT "); 6085 if (mp->m_flags & M_PKTHDR) 6086 printf("M_PKTHDR "); 6087 printf("\n"); 6088 6089 if (mp->m_flags & M_EXT) { 6090 val_hi = BCE_ADDR_HI(mp->m_ext.ext_buf); 6091 val_lo = BCE_ADDR_LO(mp->m_ext.ext_buf); 6092 BCE_PRINTF(sc, "- m_ext: vaddr = 0x%08X:%08X, ext_size = 0x%04X\n", 6093 val_hi, val_lo, mp->m_ext.ext_size); 6094 } 6095 6096 mp = mp->m_next; 6097 } 6098 6099 6100} 6101 6102 6103/****************************************************************************/ 6104/* Prints out the mbufs in the TX mbuf chain. */ 6105/* */ 6106/* Returns: */ 6107/* Nothing. */ 6108/****************************************************************************/ 6109static void 6110bce_dump_tx_mbuf_chain(struct bce_softc *sc, int chain_prod, int count) 6111{ 6112 struct mbuf *m; 6113 6114 BCE_PRINTF(sc, 6115 "----------------------------" 6116 " tx mbuf data " 6117 "----------------------------\n"); 6118 6119 for (int i = 0; i < count; i++) { 6120 m = sc->tx_mbuf_ptr[chain_prod]; 6121 BCE_PRINTF(sc, "txmbuf[%d]\n", chain_prod); 6122 bce_dump_mbuf(sc, m); 6123 chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod)); 6124 } 6125 6126 BCE_PRINTF(sc, 6127 "----------------------------" 6128 "----------------" 6129 "----------------------------\n"); 6130} 6131 6132 6133/* 6134 * This routine prints the RX mbuf chain. 6135 */ 6136static void 6137bce_dump_rx_mbuf_chain(struct bce_softc *sc, int chain_prod, int count) 6138{ 6139 struct mbuf *m; 6140 6141 BCE_PRINTF(sc, 6142 "----------------------------" 6143 " rx mbuf data " 6144 "----------------------------\n"); 6145 6146 for (int i = 0; i < count; i++) { 6147 m = sc->rx_mbuf_ptr[chain_prod]; 6148 BCE_PRINTF(sc, "rxmbuf[0x%04X]\n", chain_prod); 6149 bce_dump_mbuf(sc, m); 6150 chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod)); 6151 } 6152 6153 6154 BCE_PRINTF(sc, 6155 "----------------------------" 6156 "----------------" 6157 "----------------------------\n"); 6158} 6159 6160 6161static void 6162bce_dump_txbd(struct bce_softc *sc, int idx, struct tx_bd *txbd) 6163{ 6164 if (idx > MAX_TX_BD) 6165 /* Index out of range. */ 6166 BCE_PRINTF(sc, "tx_bd[0x%04X]: Invalid tx_bd index!\n", idx); 6167 else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 6168 /* TX Chain page pointer. */ 6169 BCE_PRINTF(sc, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page pointer\n", 6170 idx, txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo); 6171 else 6172 /* Normal tx_bd entry. */ 6173 BCE_PRINTF(sc, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = 0x%08X, " 6174 "vlan tag= 0x%4X, flags = 0x%04X\n", idx, 6175 txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo, 6176 txbd->tx_bd_mss_nbytes, txbd->tx_bd_vlan_tag, 6177 txbd->tx_bd_flags); 6178} 6179 6180 6181static void 6182bce_dump_rxbd(struct bce_softc *sc, int idx, struct rx_bd *rxbd) 6183{ 6184 if (idx > MAX_RX_BD) 6185 /* Index out of range. */ 6186 BCE_PRINTF(sc, "rx_bd[0x%04X]: Invalid rx_bd index!\n", idx); 6187 else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 6188 /* TX Chain page pointer. */ 6189 BCE_PRINTF(sc, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page pointer\n", 6190 idx, rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo); 6191 else 6192 /* Normal tx_bd entry. */ 6193 BCE_PRINTF(sc, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = 0x%08X, " 6194 "flags = 0x%08X\n", idx, 6195 rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo, 6196 rxbd->rx_bd_len, rxbd->rx_bd_flags); 6197} 6198 6199 6200static void 6201bce_dump_l2fhdr(struct bce_softc *sc, int idx, struct l2_fhdr *l2fhdr) 6202{ 6203 BCE_PRINTF(sc, "l2_fhdr[0x%04X]: status = 0x%08X, " 6204 "pkt_len = 0x%04X, vlan = 0x%04x, ip_xsum = 0x%04X, " 6205 "tcp_udp_xsum = 0x%04X\n", idx, 6206 l2fhdr->l2_fhdr_status, l2fhdr->l2_fhdr_pkt_len, 6207 l2fhdr->l2_fhdr_vlan_tag, l2fhdr->l2_fhdr_ip_xsum, 6208 l2fhdr->l2_fhdr_tcp_udp_xsum); 6209} 6210 6211 6212/* 6213 * This routine prints the TX chain. 6214 */ 6215static void 6216bce_dump_tx_chain(struct bce_softc *sc, int tx_prod, int count) 6217{ 6218 struct tx_bd *txbd; 6219 6220 /* First some info about the tx_bd chain structure. */ 6221 BCE_PRINTF(sc, 6222 "----------------------------" 6223 " tx_bd chain " 6224 "----------------------------\n"); 6225 6226 BCE_PRINTF(sc, "page size = 0x%08X, tx chain pages = 0x%08X\n", 6227 (u32) BCM_PAGE_SIZE, (u32) TX_PAGES); 6228 6229 BCE_PRINTF(sc, "tx_bd per page = 0x%08X, usable tx_bd per page = 0x%08X\n", 6230 (u32) TOTAL_TX_BD_PER_PAGE, (u32) USABLE_TX_BD_PER_PAGE); 6231 6232 BCE_PRINTF(sc, "total tx_bd = 0x%08X\n", (u32) TOTAL_TX_BD); 6233 6234 BCE_PRINTF(sc, "" 6235 "-----------------------------" 6236 " tx_bd data " 6237 "-----------------------------\n"); 6238 6239 /* Now print out the tx_bd's themselves. */ 6240 for (int i = 0; i < count; i++) { 6241 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)]; 6242 bce_dump_txbd(sc, tx_prod, txbd); 6243 tx_prod = TX_CHAIN_IDX(NEXT_TX_BD(tx_prod)); 6244 } 6245 6246 BCE_PRINTF(sc, 6247 "-----------------------------" 6248 "--------------" 6249 "-----------------------------\n"); 6250} 6251 6252 6253/* 6254 * This routine prints the RX chain. 6255 */ 6256static void 6257bce_dump_rx_chain(struct bce_softc *sc, int rx_prod, int count) 6258{ 6259 struct rx_bd *rxbd; 6260 6261 /* First some info about the tx_bd chain structure. */ 6262 BCE_PRINTF(sc, 6263 "----------------------------" 6264 " rx_bd chain " 6265 "----------------------------\n"); 6266 6267 BCE_PRINTF(sc, "----- RX_BD Chain -----\n"); 6268 6269 BCE_PRINTF(sc, "page size = 0x%08X, rx chain pages = 0x%08X\n", 6270 (u32) BCM_PAGE_SIZE, (u32) RX_PAGES); 6271 6272 BCE_PRINTF(sc, "rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n", 6273 (u32) TOTAL_RX_BD_PER_PAGE, (u32) USABLE_RX_BD_PER_PAGE); 6274 6275 BCE_PRINTF(sc, "total rx_bd = 0x%08X\n", (u32) TOTAL_RX_BD); 6276 6277 BCE_PRINTF(sc, 6278 "----------------------------" 6279 " rx_bd data " 6280 "----------------------------\n"); 6281 6282 /* Now print out the rx_bd's themselves. */ 6283 for (int i = 0; i < count; i++) { 6284 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)]; 6285 bce_dump_rxbd(sc, rx_prod, rxbd); 6286 rx_prod = RX_CHAIN_IDX(NEXT_RX_BD(rx_prod)); 6287 } 6288 6289 BCE_PRINTF(sc, 6290 "----------------------------" 6291 "--------------" 6292 "----------------------------\n"); 6293} 6294 6295 6296/* 6297 * This routine prints the status block. 6298 */ 6299static void 6300bce_dump_status_block(struct bce_softc *sc) 6301{ 6302 struct status_block *sblk; 6303 6304 sblk = sc->status_block; 6305 6306 BCE_PRINTF(sc, "----------------------------- Status Block " 6307 "-----------------------------\n"); 6308 6309 BCE_PRINTF(sc, "attn_bits = 0x%08X, attn_bits_ack = 0x%08X, index = 0x%04X\n", 6310 sblk->status_attn_bits, sblk->status_attn_bits_ack, 6311 sblk->status_idx); 6312 6313 BCE_PRINTF(sc, "rx_cons0 = 0x%08X, tx_cons0 = 0x%08X\n", 6314 sblk->status_rx_quick_consumer_index0, 6315 sblk->status_tx_quick_consumer_index0); 6316 6317 BCE_PRINTF(sc, "status_idx = 0x%04X\n", sblk->status_idx); 6318 6319 /* Theses indices are not used for normal L2 drivers. */ 6320 if (sblk->status_rx_quick_consumer_index1 || 6321 sblk->status_tx_quick_consumer_index1) 6322 BCE_PRINTF(sc, "rx_cons1 = 0x%08X, tx_cons1 = 0x%08X\n", 6323 sblk->status_rx_quick_consumer_index1, 6324 sblk->status_tx_quick_consumer_index1); 6325 6326 if (sblk->status_rx_quick_consumer_index2 || 6327 sblk->status_tx_quick_consumer_index2) 6328 BCE_PRINTF(sc, "rx_cons2 = 0x%08X, tx_cons2 = 0x%08X\n", 6329 sblk->status_rx_quick_consumer_index2, 6330 sblk->status_tx_quick_consumer_index2); 6331 6332 if (sblk->status_rx_quick_consumer_index3 || 6333 sblk->status_tx_quick_consumer_index3) 6334 BCE_PRINTF(sc, "rx_cons3 = 0x%08X, tx_cons3 = 0x%08X\n", 6335 sblk->status_rx_quick_consumer_index3, 6336 sblk->status_tx_quick_consumer_index3); 6337 6338 if (sblk->status_rx_quick_consumer_index4 || 6339 sblk->status_rx_quick_consumer_index5) 6340 BCE_PRINTF(sc, "rx_cons4 = 0x%08X, rx_cons5 = 0x%08X\n", 6341 sblk->status_rx_quick_consumer_index4, 6342 sblk->status_rx_quick_consumer_index5); 6343 6344 if (sblk->status_rx_quick_consumer_index6 || 6345 sblk->status_rx_quick_consumer_index7) 6346 BCE_PRINTF(sc, "rx_cons6 = 0x%08X, rx_cons7 = 0x%08X\n", 6347 sblk->status_rx_quick_consumer_index6, 6348 sblk->status_rx_quick_consumer_index7); 6349 6350 if (sblk->status_rx_quick_consumer_index8 || 6351 sblk->status_rx_quick_consumer_index9) 6352 BCE_PRINTF(sc, "rx_cons8 = 0x%08X, rx_cons9 = 0x%08X\n", 6353 sblk->status_rx_quick_consumer_index8, 6354 sblk->status_rx_quick_consumer_index9); 6355 6356 if (sblk->status_rx_quick_consumer_index10 || 6357 sblk->status_rx_quick_consumer_index11) 6358 BCE_PRINTF(sc, "rx_cons10 = 0x%08X, rx_cons11 = 0x%08X\n", 6359 sblk->status_rx_quick_consumer_index10, 6360 sblk->status_rx_quick_consumer_index11); 6361 6362 if (sblk->status_rx_quick_consumer_index12 || 6363 sblk->status_rx_quick_consumer_index13) 6364 BCE_PRINTF(sc, "rx_cons12 = 0x%08X, rx_cons13 = 0x%08X\n", 6365 sblk->status_rx_quick_consumer_index12, 6366 sblk->status_rx_quick_consumer_index13); 6367 6368 if (sblk->status_rx_quick_consumer_index14 || 6369 sblk->status_rx_quick_consumer_index15) 6370 BCE_PRINTF(sc, "rx_cons14 = 0x%08X, rx_cons15 = 0x%08X\n", 6371 sblk->status_rx_quick_consumer_index14, 6372 sblk->status_rx_quick_consumer_index15); 6373 6374 if (sblk->status_completion_producer_index || 6375 sblk->status_cmd_consumer_index) 6376 BCE_PRINTF(sc, "com_prod = 0x%08X, cmd_cons = 0x%08X\n", 6377 sblk->status_completion_producer_index, 6378 sblk->status_cmd_consumer_index); 6379 6380 BCE_PRINTF(sc, "-------------------------------------------" 6381 "-----------------------------\n"); 6382} 6383 6384 6385/* 6386 * This routine prints the statistics block. 6387 */ 6388static void 6389bce_dump_stats_block(struct bce_softc *sc) 6390{ 6391 struct statistics_block *sblk; 6392 6393 sblk = sc->stats_block; 6394 6395 BCE_PRINTF(sc, "" 6396 "-----------------------------" 6397 " Stats Block " 6398 "-----------------------------\n"); 6399 6400 BCE_PRINTF(sc, "IfHcInOctets = 0x%08X:%08X, " 6401 "IfHcInBadOctets = 0x%08X:%08X\n", 6402 sblk->stat_IfHCInOctets_hi, sblk->stat_IfHCInOctets_lo, 6403 sblk->stat_IfHCInBadOctets_hi, sblk->stat_IfHCInBadOctets_lo); 6404 6405 BCE_PRINTF(sc, "IfHcOutOctets = 0x%08X:%08X, " 6406 "IfHcOutBadOctets = 0x%08X:%08X\n", 6407 sblk->stat_IfHCOutOctets_hi, sblk->stat_IfHCOutOctets_lo, 6408 sblk->stat_IfHCOutBadOctets_hi, sblk->stat_IfHCOutBadOctets_lo); 6409 6410 BCE_PRINTF(sc, "IfHcInUcastPkts = 0x%08X:%08X, " 6411 "IfHcInMulticastPkts = 0x%08X:%08X\n", 6412 sblk->stat_IfHCInUcastPkts_hi, sblk->stat_IfHCInUcastPkts_lo, 6413 sblk->stat_IfHCInMulticastPkts_hi, sblk->stat_IfHCInMulticastPkts_lo); 6414 6415 BCE_PRINTF(sc, "IfHcInBroadcastPkts = 0x%08X:%08X, " 6416 "IfHcOutUcastPkts = 0x%08X:%08X\n", 6417 sblk->stat_IfHCInBroadcastPkts_hi, sblk->stat_IfHCInBroadcastPkts_lo, 6418 sblk->stat_IfHCOutUcastPkts_hi, sblk->stat_IfHCOutUcastPkts_lo); 6419 6420 BCE_PRINTF(sc, "IfHcOutMulticastPkts = 0x%08X:%08X, IfHcOutBroadcastPkts = 0x%08X:%08X\n", 6421 sblk->stat_IfHCOutMulticastPkts_hi, sblk->stat_IfHCOutMulticastPkts_lo, 6422 sblk->stat_IfHCOutBroadcastPkts_hi, sblk->stat_IfHCOutBroadcastPkts_lo); 6423 6424 if (sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors) 6425 BCE_PRINTF(sc, "0x%08X : " 6426 "emac_tx_stat_dot3statsinternalmactransmiterrors\n", 6427 sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors); 6428 6429 if (sblk->stat_Dot3StatsCarrierSenseErrors) 6430 BCE_PRINTF(sc, "0x%08X : Dot3StatsCarrierSenseErrors\n", 6431 sblk->stat_Dot3StatsCarrierSenseErrors); 6432 6433 if (sblk->stat_Dot3StatsFCSErrors) 6434 BCE_PRINTF(sc, "0x%08X : Dot3StatsFCSErrors\n", 6435 sblk->stat_Dot3StatsFCSErrors); 6436 6437 if (sblk->stat_Dot3StatsAlignmentErrors) 6438 BCE_PRINTF(sc, "0x%08X : Dot3StatsAlignmentErrors\n", 6439 sblk->stat_Dot3StatsAlignmentErrors); 6440 6441 if (sblk->stat_Dot3StatsSingleCollisionFrames) 6442 BCE_PRINTF(sc, "0x%08X : Dot3StatsSingleCollisionFrames\n", 6443 sblk->stat_Dot3StatsSingleCollisionFrames); 6444 6445 if (sblk->stat_Dot3StatsMultipleCollisionFrames) 6446 BCE_PRINTF(sc, "0x%08X : Dot3StatsMultipleCollisionFrames\n", 6447 sblk->stat_Dot3StatsMultipleCollisionFrames); 6448 6449 if (sblk->stat_Dot3StatsDeferredTransmissions) 6450 BCE_PRINTF(sc, "0x%08X : Dot3StatsDeferredTransmissions\n", 6451 sblk->stat_Dot3StatsDeferredTransmissions); 6452 6453 if (sblk->stat_Dot3StatsExcessiveCollisions) 6454 BCE_PRINTF(sc, "0x%08X : Dot3StatsExcessiveCollisions\n", 6455 sblk->stat_Dot3StatsExcessiveCollisions); 6456 6457 if (sblk->stat_Dot3StatsLateCollisions) 6458 BCE_PRINTF(sc, "0x%08X : Dot3StatsLateCollisions\n", 6459 sblk->stat_Dot3StatsLateCollisions); 6460 6461 if (sblk->stat_EtherStatsCollisions) 6462 BCE_PRINTF(sc, "0x%08X : EtherStatsCollisions\n", 6463 sblk->stat_EtherStatsCollisions); 6464 6465 if (sblk->stat_EtherStatsFragments) 6466 BCE_PRINTF(sc, "0x%08X : EtherStatsFragments\n", 6467 sblk->stat_EtherStatsFragments); 6468 6469 if (sblk->stat_EtherStatsJabbers) 6470 BCE_PRINTF(sc, "0x%08X : EtherStatsJabbers\n", 6471 sblk->stat_EtherStatsJabbers); 6472 6473 if (sblk->stat_EtherStatsUndersizePkts) 6474 BCE_PRINTF(sc, "0x%08X : EtherStatsUndersizePkts\n", 6475 sblk->stat_EtherStatsUndersizePkts); 6476 6477 if (sblk->stat_EtherStatsOverrsizePkts) 6478 BCE_PRINTF(sc, "0x%08X : EtherStatsOverrsizePkts\n", 6479 sblk->stat_EtherStatsOverrsizePkts); 6480 6481 if (sblk->stat_EtherStatsPktsRx64Octets) 6482 BCE_PRINTF(sc, "0x%08X : EtherStatsPktsRx64Octets\n", 6483 sblk->stat_EtherStatsPktsRx64Octets); 6484 6485 if (sblk->stat_EtherStatsPktsRx65Octetsto127Octets) 6486 BCE_PRINTF(sc, "0x%08X : EtherStatsPktsRx65Octetsto127Octets\n", 6487 sblk->stat_EtherStatsPktsRx65Octetsto127Octets); 6488 6489 if (sblk->stat_EtherStatsPktsRx128Octetsto255Octets) 6490 BCE_PRINTF(sc, "0x%08X : EtherStatsPktsRx128Octetsto255Octets\n", 6491 sblk->stat_EtherStatsPktsRx128Octetsto255Octets); 6492 6493 if (sblk->stat_EtherStatsPktsRx256Octetsto511Octets) 6494 BCE_PRINTF(sc, "0x%08X : EtherStatsPktsRx256Octetsto511Octets\n", 6495 sblk->stat_EtherStatsPktsRx256Octetsto511Octets); 6496 6497 if (sblk->stat_EtherStatsPktsRx512Octetsto1023Octets) 6498 BCE_PRINTF(sc, "0x%08X : EtherStatsPktsRx512Octetsto1023Octets\n", 6499 sblk->stat_EtherStatsPktsRx512Octetsto1023Octets); 6500 6501 if (sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets) 6502 BCE_PRINTF(sc, "0x%08X : EtherStatsPktsRx1024Octetsto1522Octets\n", 6503 sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets); 6504 6505 if (sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets) 6506 BCE_PRINTF(sc, "0x%08X : EtherStatsPktsRx1523Octetsto9022Octets\n", 6507 sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets); 6508 6509 if (sblk->stat_EtherStatsPktsTx64Octets) 6510 BCE_PRINTF(sc, "0x%08X : EtherStatsPktsTx64Octets\n", 6511 sblk->stat_EtherStatsPktsTx64Octets); 6512 6513 if (sblk->stat_EtherStatsPktsTx65Octetsto127Octets) 6514 BCE_PRINTF(sc, "0x%08X : EtherStatsPktsTx65Octetsto127Octets\n", 6515 sblk->stat_EtherStatsPktsTx65Octetsto127Octets); 6516 6517 if (sblk->stat_EtherStatsPktsTx128Octetsto255Octets) 6518 BCE_PRINTF(sc, "0x%08X : EtherStatsPktsTx128Octetsto255Octets\n", 6519 sblk->stat_EtherStatsPktsTx128Octetsto255Octets); 6520 6521 if (sblk->stat_EtherStatsPktsTx256Octetsto511Octets) 6522 BCE_PRINTF(sc, "0x%08X : EtherStatsPktsTx256Octetsto511Octets\n", 6523 sblk->stat_EtherStatsPktsTx256Octetsto511Octets); 6524 6525 if (sblk->stat_EtherStatsPktsTx512Octetsto1023Octets) 6526 BCE_PRINTF(sc, "0x%08X : EtherStatsPktsTx512Octetsto1023Octets\n", 6527 sblk->stat_EtherStatsPktsTx512Octetsto1023Octets); 6528 6529 if (sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets) 6530 BCE_PRINTF(sc, "0x%08X : EtherStatsPktsTx1024Octetsto1522Octets\n", 6531 sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets); 6532 6533 if (sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets) 6534 BCE_PRINTF(sc, "0x%08X : EtherStatsPktsTx1523Octetsto9022Octets\n", 6535 sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets); 6536 6537 if (sblk->stat_XonPauseFramesReceived) 6538 BCE_PRINTF(sc, "0x%08X : XonPauseFramesReceived\n", 6539 sblk->stat_XonPauseFramesReceived); 6540 6541 if (sblk->stat_XoffPauseFramesReceived) 6542 BCE_PRINTF(sc, "0x%08X : XoffPauseFramesReceived\n", 6543 sblk->stat_XoffPauseFramesReceived); 6544 6545 if (sblk->stat_OutXonSent) 6546 BCE_PRINTF(sc, "0x%08X : OutXonSent\n", 6547 sblk->stat_OutXonSent); 6548 6549 if (sblk->stat_OutXoffSent) 6550 BCE_PRINTF(sc, "0x%08X : OutXoffSent\n", 6551 sblk->stat_OutXoffSent); 6552 6553 if (sblk->stat_FlowControlDone) 6554 BCE_PRINTF(sc, "0x%08X : FlowControlDone\n", 6555 sblk->stat_FlowControlDone); 6556 6557 if (sblk->stat_MacControlFramesReceived) 6558 BCE_PRINTF(sc, "0x%08X : MacControlFramesReceived\n", 6559 sblk->stat_MacControlFramesReceived); 6560 6561 if (sblk->stat_XoffStateEntered) 6562 BCE_PRINTF(sc, "0x%08X : XoffStateEntered\n", 6563 sblk->stat_XoffStateEntered); 6564 6565 if (sblk->stat_IfInFramesL2FilterDiscards) 6566 BCE_PRINTF(sc, "0x%08X : IfInFramesL2FilterDiscards\n", 6567 sblk->stat_IfInFramesL2FilterDiscards); 6568 6569 if (sblk->stat_IfInRuleCheckerDiscards) 6570 BCE_PRINTF(sc, "0x%08X : IfInRuleCheckerDiscards\n", 6571 sblk->stat_IfInRuleCheckerDiscards); 6572 6573 if (sblk->stat_IfInFTQDiscards) 6574 BCE_PRINTF(sc, "0x%08X : IfInFTQDiscards\n", 6575 sblk->stat_IfInFTQDiscards); 6576 6577 if (sblk->stat_IfInMBUFDiscards) 6578 BCE_PRINTF(sc, "0x%08X : IfInMBUFDiscards\n", 6579 sblk->stat_IfInMBUFDiscards); 6580 6581 if (sblk->stat_IfInRuleCheckerP4Hit) 6582 BCE_PRINTF(sc, "0x%08X : IfInRuleCheckerP4Hit\n", 6583 sblk->stat_IfInRuleCheckerP4Hit); 6584 6585 if (sblk->stat_CatchupInRuleCheckerDiscards) 6586 BCE_PRINTF(sc, "0x%08X : CatchupInRuleCheckerDiscards\n", 6587 sblk->stat_CatchupInRuleCheckerDiscards); 6588 6589 if (sblk->stat_CatchupInFTQDiscards) 6590 BCE_PRINTF(sc, "0x%08X : CatchupInFTQDiscards\n", 6591 sblk->stat_CatchupInFTQDiscards); 6592 6593 if (sblk->stat_CatchupInMBUFDiscards) 6594 BCE_PRINTF(sc, "0x%08X : CatchupInMBUFDiscards\n", 6595 sblk->stat_CatchupInMBUFDiscards); 6596 6597 if (sblk->stat_CatchupInRuleCheckerP4Hit) 6598 BCE_PRINTF(sc, "0x%08X : CatchupInRuleCheckerP4Hit\n", 6599 sblk->stat_CatchupInRuleCheckerP4Hit); 6600 6601 BCE_PRINTF(sc, 6602 "-----------------------------" 6603 "--------------" 6604 "-----------------------------\n"); 6605} 6606 6607 6608static void 6609bce_dump_driver_state(struct bce_softc *sc) 6610{ 6611 u32 val_hi, val_lo; 6612 6613 BCE_PRINTF(sc, 6614 "-----------------------------" 6615 " Driver State " 6616 "-----------------------------\n"); 6617 6618 val_hi = BCE_ADDR_HI(sc); 6619 val_lo = BCE_ADDR_LO(sc); 6620 BCE_PRINTF(sc, "0x%08X:%08X - (sc) driver softc structure virtual address\n", 6621 val_hi, val_lo); 6622 6623 val_hi = BCE_ADDR_HI(sc->bce_vhandle); 6624 val_lo = BCE_ADDR_LO(sc->bce_vhandle); 6625 BCE_PRINTF(sc, "0x%08X:%08X - (sc->bce_vhandle) PCI BAR virtual address\n", 6626 val_hi, val_lo); 6627 6628 val_hi = BCE_ADDR_HI(sc->status_block); 6629 val_lo = BCE_ADDR_LO(sc->status_block); 6630 BCE_PRINTF(sc, "0x%08X:%08X - (sc->status_block) status block virtual address\n", 6631 val_hi, val_lo); 6632 6633 val_hi = BCE_ADDR_HI(sc->stats_block); 6634 val_lo = BCE_ADDR_LO(sc->stats_block); 6635 BCE_PRINTF(sc, "0x%08X:%08X - (sc->stats_block) statistics block virtual address\n", 6636 val_hi, val_lo); 6637 6638 val_hi = BCE_ADDR_HI(sc->tx_bd_chain); 6639 val_lo = BCE_ADDR_LO(sc->tx_bd_chain); 6640 BCE_PRINTF(sc, 6641 "0x%08X:%08X - (sc->tx_bd_chain) tx_bd chain virtual adddress\n", 6642 val_hi, val_lo); 6643 6644 val_hi = BCE_ADDR_HI(sc->rx_bd_chain); 6645 val_lo = BCE_ADDR_LO(sc->rx_bd_chain); 6646 BCE_PRINTF(sc, 6647 "0x%08X:%08X - (sc->rx_bd_chain) rx_bd chain virtual address\n", 6648 val_hi, val_lo); 6649 6650 val_hi = BCE_ADDR_HI(sc->tx_mbuf_ptr); 6651 val_lo = BCE_ADDR_LO(sc->tx_mbuf_ptr); 6652 BCE_PRINTF(sc, 6653 "0x%08X:%08X - (sc->tx_mbuf_ptr) tx mbuf chain virtual address\n", 6654 val_hi, val_lo); 6655 6656 val_hi = BCE_ADDR_HI(sc->rx_mbuf_ptr); 6657 val_lo = BCE_ADDR_LO(sc->rx_mbuf_ptr); 6658 BCE_PRINTF(sc, 6659 "0x%08X:%08X - (sc->rx_mbuf_ptr) rx mbuf chain virtual address\n", 6660 val_hi, val_lo); 6661 6662 BCE_PRINTF(sc, " 0x%08X - (sc->interrupts_generated) h/w intrs\n", 6663 sc->interrupts_generated); 6664 6665 BCE_PRINTF(sc, " 0x%08X - (sc->rx_interrupts) rx interrupts handled\n", 6666 sc->rx_interrupts); 6667 6668 BCE_PRINTF(sc, " 0x%08X - (sc->tx_interrupts) tx interrupts handled\n", 6669 sc->tx_interrupts); 6670 6671 BCE_PRINTF(sc, " 0x%08X - (sc->last_status_idx) status block index\n", 6672 sc->last_status_idx); 6673 6674 BCE_PRINTF(sc, " 0x%08X - (sc->tx_prod) tx producer index\n", 6675 sc->tx_prod); 6676 6677 BCE_PRINTF(sc, " 0x%08X - (sc->tx_cons) tx consumer index\n", 6678 sc->tx_cons); 6679 6680 BCE_PRINTF(sc, " 0x%08X - (sc->tx_prod_bseq) tx producer bseq index\n", 6681 sc->tx_prod_bseq); 6682 6683 BCE_PRINTF(sc, " 0x%08X - (sc->rx_prod) rx producer index\n", 6684 sc->rx_prod); 6685 6686 BCE_PRINTF(sc, " 0x%08X - (sc->rx_cons) rx consumer index\n", 6687 sc->rx_cons); 6688 6689 BCE_PRINTF(sc, " 0x%08X - (sc->rx_prod_bseq) rx producer bseq index\n", 6690 sc->rx_prod_bseq); 6691 6692 BCE_PRINTF(sc, " 0x%08X - (sc->rx_mbuf_alloc) rx mbufs allocated\n", 6693 sc->rx_mbuf_alloc); 6694 6695 BCE_PRINTF(sc, " 0x%08X - (sc->free_rx_bd) free rx_bd's\n", 6696 sc->free_rx_bd); 6697 6698 BCE_PRINTF(sc, "0x%08X/%08X - (sc->rx_low_watermark) rx low watermark\n", 6699 sc->rx_low_watermark, (u32) USABLE_RX_BD); 6700 6701 BCE_PRINTF(sc, " 0x%08X - (sc->txmbuf_alloc) tx mbufs allocated\n", 6702 sc->tx_mbuf_alloc); 6703 6704 BCE_PRINTF(sc, " 0x%08X - (sc->rx_mbuf_alloc) rx mbufs allocated\n", 6705 sc->rx_mbuf_alloc); 6706 6707 BCE_PRINTF(sc, " 0x%08X - (sc->used_tx_bd) used tx_bd's\n", 6708 sc->used_tx_bd); 6709 6710 BCE_PRINTF(sc, "0x%08X/%08X - (sc->tx_hi_watermark) tx hi watermark\n", 6711 sc->tx_hi_watermark, (u32) USABLE_TX_BD); 6712 6713 BCE_PRINTF(sc, " 0x%08X - (sc->mbuf_alloc_failed) failed mbuf alloc\n", 6714 sc->mbuf_alloc_failed); 6715 6716 BCE_PRINTF(sc, 6717 "-----------------------------" 6718 "--------------" 6719 "-----------------------------\n"); 6720} 6721 6722 6723static void 6724bce_dump_hw_state(struct bce_softc *sc) 6725{ 6726 u32 val1; 6727 6728 BCE_PRINTF(sc, 6729 "----------------------------" 6730 " Hardware State " 6731 "----------------------------\n"); 6732 6733 BCE_PRINTF(sc, "0x%08X : bootcode version\n", sc->bce_fw_ver); 6734 6735 val1 = REG_RD(sc, BCE_MISC_ENABLE_STATUS_BITS); 6736 BCE_PRINTF(sc, "0x%08X : (0x%04X) misc_enable_status_bits\n", 6737 val1, BCE_MISC_ENABLE_STATUS_BITS); 6738 6739 val1 = REG_RD(sc, BCE_DMA_STATUS); 6740 BCE_PRINTF(sc, "0x%08X : (0x%04X) dma_status\n", val1, BCE_DMA_STATUS); 6741 6742 val1 = REG_RD(sc, BCE_CTX_STATUS); 6743 BCE_PRINTF(sc, "0x%08X : (0x%04X) ctx_status\n", val1, BCE_CTX_STATUS); 6744 6745 val1 = REG_RD(sc, BCE_EMAC_STATUS); 6746 BCE_PRINTF(sc, "0x%08X : (0x%04X) emac_status\n", val1, BCE_EMAC_STATUS); 6747 6748 val1 = REG_RD(sc, BCE_RPM_STATUS); 6749 BCE_PRINTF(sc, "0x%08X : (0x%04X) rpm_status\n", val1, BCE_RPM_STATUS); 6750 6751 val1 = REG_RD(sc, BCE_TBDR_STATUS); 6752 BCE_PRINTF(sc, "0x%08X : (0x%04X) tbdr_status\n", val1, BCE_TBDR_STATUS); 6753 6754 val1 = REG_RD(sc, BCE_TDMA_STATUS); 6755 BCE_PRINTF(sc, "0x%08X : (0x%04X) tdma_status\n", val1, BCE_TDMA_STATUS); 6756 6757 val1 = REG_RD(sc, BCE_HC_STATUS); 6758 BCE_PRINTF(sc, "0x%08X : (0x%04X) hc_status\n", val1, BCE_HC_STATUS); 6759 6760 BCE_PRINTF(sc, 6761 "----------------------------" 6762 "----------------" 6763 "----------------------------\n"); 6764 6765 BCE_PRINTF(sc, 6766 "----------------------------" 6767 " Register Dump " 6768 "----------------------------\n"); 6769 6770 for (int i = 0x400; i < 0x8000; i += 0x10) 6771 BCE_PRINTF(sc, "0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 6772 i, REG_RD(sc, i), REG_RD(sc, i + 0x4), 6773 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC)); 6774 6775 BCE_PRINTF(sc, 6776 "----------------------------" 6777 "----------------" 6778 "----------------------------\n"); 6779} 6780 6781 6782static void 6783bce_breakpoint(struct bce_softc *sc) 6784{ 6785 6786 /* Unreachable code to shut the compiler up about unused functions. */ 6787 if (0) { 6788 bce_dump_txbd(sc, 0, NULL); 6789 bce_dump_rxbd(sc, 0, NULL); 6790 bce_dump_tx_mbuf_chain(sc, 0, USABLE_TX_BD); 6791 bce_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD); 6792 bce_dump_l2fhdr(sc, 0, NULL); 6793 bce_dump_tx_chain(sc, 0, USABLE_TX_BD); 6794 bce_dump_rx_chain(sc, 0, USABLE_RX_BD); 6795 bce_dump_status_block(sc); 6796 bce_dump_stats_block(sc); 6797 bce_dump_driver_state(sc); 6798 bce_dump_hw_state(sc); 6799 } 6800 6801 bce_dump_driver_state(sc); 6802 /* Print the important status block fields. */ 6803 bce_dump_status_block(sc); 6804 6805 /* Call the debugger. */ 6806 breakpoint(); 6807 6808 return; 6809} 6810#endif 6811