if_bce.c revision 204374
1157642Sps/*- 2189117Sdavidch * Copyright (c) 2006-2009 Broadcom Corporation 3157642Sps * David Christensen <davidch@broadcom.com>. All rights reserved. 4157642Sps * 5157642Sps * Redistribution and use in source and binary forms, with or without 6157642Sps * modification, are permitted provided that the following conditions 7157642Sps * are met: 8157642Sps * 9157642Sps * 1. Redistributions of source code must retain the above copyright 10157642Sps * notice, this list of conditions and the following disclaimer. 11157642Sps * 2. Redistributions in binary form must reproduce the above copyright 12157642Sps * notice, this list of conditions and the following disclaimer in the 13157642Sps * documentation and/or other materials provided with the distribution. 14157642Sps * 3. Neither the name of Broadcom Corporation nor the name of its contributors 15157642Sps * may be used to endorse or promote products derived from this software 16157642Sps * without specific prior written consent. 17157642Sps * 18157642Sps * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 19157642Sps * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20157642Sps * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21157642Sps * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 22157642Sps * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23157642Sps * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24157642Sps * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25157642Sps * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26157642Sps * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27157642Sps * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 28157642Sps * THE POSSIBILITY OF SUCH DAMAGE. 29157642Sps */ 30157642Sps 31157642Sps#include <sys/cdefs.h> 32157642Sps__FBSDID("$FreeBSD: head/sys/dev/bce/if_bce.c 204374 2010-02-26 21:26:07Z yongari $"); 33157642Sps 34157642Sps/* 35157642Sps * The following controllers are supported by this driver: 36157642Sps * BCM5706C A2, A3 37176448Sdavidch * BCM5706S A2, A3 38169271Sdavidch * BCM5708C B1, B2 39176448Sdavidch * BCM5708S B1, B2 40182293Sdavidch * BCM5709C A1, C0 41189325Sdavidch * BCM5716C C0 42157642Sps * 43157642Sps * The following controllers are not supported by this driver: 44176448Sdavidch * BCM5706C A0, A1 (pre-production) 45176448Sdavidch * BCM5706S A0, A1 (pre-production) 46176448Sdavidch * BCM5708C A0, B0 (pre-production) 47176448Sdavidch * BCM5708S A0, B0 (pre-production) 48179771Sdavidch * BCM5709C A0 B0, B1, B2 (pre-production) 49179771Sdavidch * BCM5709S A0, A1, B0, B1, B2, C0 (pre-production) 50157642Sps */ 51157642Sps 52157643Sps#include "opt_bce.h" 53157643Sps 54157642Sps#include <dev/bce/if_bcereg.h> 55157642Sps#include <dev/bce/if_bcefw.h> 56157642Sps 57157642Sps/****************************************************************************/ 58157642Sps/* BCE Debug Options */ 59157642Sps/****************************************************************************/ 60157642Sps#ifdef BCE_DEBUG 61157642Sps u32 bce_debug = BCE_WARN; 62157642Sps 63157642Sps /* 0 = Never */ 64157642Sps /* 1 = 1 in 2,147,483,648 */ 65157642Sps /* 256 = 1 in 8,388,608 */ 66157642Sps /* 2048 = 1 in 1,048,576 */ 67157642Sps /* 65536 = 1 in 32,768 */ 68157642Sps /* 1048576 = 1 in 2,048 */ 69157642Sps /* 268435456 = 1 in 8 */ 70157642Sps /* 536870912 = 1 in 4 */ 71157642Sps /* 1073741824 = 1 in 2 */ 72157642Sps 73157642Sps /* Controls how often the l2_fhdr frame error check will fail. */ 74189325Sdavidch int l2fhdr_error_sim_control = 0; 75157642Sps 76157642Sps /* Controls how often the unexpected attention check will fail. */ 77189325Sdavidch int unexpected_attention_sim_control = 0; 78157642Sps 79157642Sps /* Controls how often to simulate an mbuf allocation failure. */ 80189325Sdavidch int mbuf_alloc_failed_sim_control = 0; 81157642Sps 82157642Sps /* Controls how often to simulate a DMA mapping failure. */ 83189325Sdavidch int dma_map_addr_failed_sim_control = 0; 84157642Sps 85157642Sps /* Controls how often to simulate a bootcode failure. */ 86189325Sdavidch int bootcode_running_failure_sim_control = 0; 87157642Sps#endif 88178132Sdavidch 89179695Sdavidch/****************************************************************************/ 90179695Sdavidch/* BCE Build Time Options */ 91179695Sdavidch/****************************************************************************/ 92179695Sdavidch/* #define BCE_NVRAM_WRITE_SUPPORT 1 */ 93178132Sdavidch 94182293Sdavidch 95157642Sps/****************************************************************************/ 96157642Sps/* PCI Device ID Table */ 97157642Sps/* */ 98157642Sps/* Used by bce_probe() to identify the devices supported by this driver. */ 99157642Sps/****************************************************************************/ 100157642Sps#define BCE_DEVDESC_MAX 64 101157642Sps 102157642Spsstatic struct bce_type bce_devs[] = { 103157642Sps /* BCM5706C Controllers and OEM boards. */ 104157642Sps { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3101, 105157642Sps "HP NC370T Multifunction Gigabit Server Adapter" }, 106157642Sps { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3106, 107157642Sps "HP NC370i Multifunction Gigabit Server Adapter" }, 108187133Sdelphij { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3070, 109187317Sdelphij "HP NC380T PCIe DP Multifunc Gig Server Adapter" }, 110187317Sdelphij { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x1709, 111187317Sdelphij "HP NC371i Multifunction Gigabit Server Adapter" }, 112157642Sps { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, PCI_ANY_ID, PCI_ANY_ID, 113157642Sps "Broadcom NetXtreme II BCM5706 1000Base-T" }, 114157642Sps 115157642Sps /* BCM5706S controllers and OEM boards. */ 116157642Sps { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, HP_VENDORID, 0x3102, 117157642Sps "HP NC370F Multifunction Gigabit Server Adapter" }, 118157642Sps { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, PCI_ANY_ID, PCI_ANY_ID, 119157642Sps "Broadcom NetXtreme II BCM5706 1000Base-SX" }, 120157642Sps 121157642Sps /* BCM5708C controllers and OEM boards. */ 122187133Sdelphij { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7037, 123187317Sdelphij "HP NC373T PCIe Multifunction Gig Server Adapter" }, 124187133Sdelphij { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7038, 125187317Sdelphij "HP NC373i Multifunction Gigabit Server Adapter" }, 126187317Sdelphij { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7045, 127187317Sdelphij "HP NC374m PCIe Multifunction Adapter" }, 128157642Sps { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, PCI_ANY_ID, PCI_ANY_ID, 129157642Sps "Broadcom NetXtreme II BCM5708 1000Base-T" }, 130157642Sps 131157642Sps /* BCM5708S controllers and OEM boards. */ 132187133Sdelphij { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x1706, 133187317Sdelphij "HP NC373m Multifunction Gigabit Server Adapter" }, 134187133Sdelphij { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x703b, 135187317Sdelphij "HP NC373i Multifunction Gigabit Server Adapter" }, 136187133Sdelphij { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x703d, 137187317Sdelphij "HP NC373F PCIe Multifunc Giga Server Adapter" }, 138163814Sscottl { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, PCI_ANY_ID, PCI_ANY_ID, 139170392Sdavidch "Broadcom NetXtreme II BCM5708 1000Base-SX" }, 140179771Sdavidch 141179771Sdavidch /* BCM5709C controllers and OEM boards. */ 142187133Sdelphij { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, HP_VENDORID, 0x7055, 143187317Sdelphij "HP NC382i DP Multifunction Gigabit Server Adapter" }, 144187133Sdelphij { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, HP_VENDORID, 0x7059, 145187317Sdelphij "HP NC382T PCIe DP Multifunction Gigabit Server Adapter" }, 146179771Sdavidch { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, PCI_ANY_ID, PCI_ANY_ID, 147179771Sdavidch "Broadcom NetXtreme II BCM5709 1000Base-T" }, 148179771Sdavidch 149179771Sdavidch /* BCM5709S controllers and OEM boards. */ 150187133Sdelphij { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, HP_VENDORID, 0x171d, 151187317Sdelphij "HP NC382m DP 1GbE Multifunction BL-c Adapter" }, 152187133Sdelphij { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, HP_VENDORID, 0x7056, 153187317Sdelphij "HP NC382i DP Multifunction Gigabit Server Adapter" }, 154179771Sdavidch { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, PCI_ANY_ID, PCI_ANY_ID, 155179771Sdavidch "Broadcom NetXtreme II BCM5709 1000Base-SX" }, 156179771Sdavidch 157179771Sdavidch /* BCM5716 controllers and OEM boards. */ 158179771Sdavidch { BRCM_VENDORID, BRCM_DEVICEID_BCM5716, PCI_ANY_ID, PCI_ANY_ID, 159179771Sdavidch "Broadcom NetXtreme II BCM5716 1000Base-T" }, 160179771Sdavidch 161157642Sps { 0, 0, 0, 0, NULL } 162157642Sps}; 163157642Sps 164157642Sps 165157642Sps/****************************************************************************/ 166157642Sps/* Supported Flash NVRAM device data. */ 167157642Sps/****************************************************************************/ 168157642Spsstatic struct flash_spec flash_table[] = 169157642Sps{ 170179771Sdavidch#define BUFFERED_FLAGS (BCE_NV_BUFFERED | BCE_NV_TRANSLATE) 171179771Sdavidch#define NONBUFFERED_FLAGS (BCE_NV_WREN) 172179771Sdavidch 173157642Sps /* Slow EEPROM */ 174157642Sps {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400, 175179771Sdavidch BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 176157642Sps SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 177157642Sps "EEPROM - slow"}, 178157642Sps /* Expansion entry 0001 */ 179157642Sps {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406, 180179771Sdavidch NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 181157642Sps SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 182157642Sps "Entry 0001"}, 183157642Sps /* Saifun SA25F010 (non-buffered flash) */ 184157642Sps /* strap, cfg1, & write1 need updates */ 185157642Sps {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406, 186179771Sdavidch NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 187157642Sps SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2, 188157642Sps "Non-buffered flash (128kB)"}, 189157642Sps /* Saifun SA25F020 (non-buffered flash) */ 190157642Sps /* strap, cfg1, & write1 need updates */ 191157642Sps {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406, 192179771Sdavidch NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 193157642Sps SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4, 194157642Sps "Non-buffered flash (256kB)"}, 195157642Sps /* Expansion entry 0100 */ 196157642Sps {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406, 197179771Sdavidch NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 198157642Sps SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 199157642Sps "Entry 0100"}, 200157642Sps /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */ 201157642Sps {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406, 202179771Sdavidch NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 203157642Sps ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2, 204157642Sps "Entry 0101: ST M45PE10 (128kB non-bufferred)"}, 205157642Sps /* Entry 0110: ST M45PE20 (non-buffered flash)*/ 206157642Sps {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406, 207179771Sdavidch NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 208157642Sps ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4, 209157642Sps "Entry 0110: ST M45PE20 (256kB non-bufferred)"}, 210157642Sps /* Saifun SA25F005 (non-buffered flash) */ 211157642Sps /* strap, cfg1, & write1 need updates */ 212157642Sps {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406, 213179771Sdavidch NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 214157642Sps SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE, 215157642Sps "Non-buffered flash (64kB)"}, 216157642Sps /* Fast EEPROM */ 217157642Sps {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400, 218179771Sdavidch BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 219157642Sps SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 220157642Sps "EEPROM - fast"}, 221157642Sps /* Expansion entry 1001 */ 222157642Sps {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406, 223179771Sdavidch NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 224157642Sps SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 225157642Sps "Entry 1001"}, 226157642Sps /* Expansion entry 1010 */ 227157642Sps {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406, 228179771Sdavidch NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 229157642Sps SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 230157642Sps "Entry 1010"}, 231157642Sps /* ATMEL AT45DB011B (buffered flash) */ 232157642Sps {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400, 233179771Sdavidch BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 234157642Sps BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE, 235157642Sps "Buffered flash (128kB)"}, 236157642Sps /* Expansion entry 1100 */ 237157642Sps {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406, 238179771Sdavidch NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 239157642Sps SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 240157642Sps "Entry 1100"}, 241157642Sps /* Expansion entry 1101 */ 242157642Sps {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406, 243179771Sdavidch NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 244157642Sps SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 245157642Sps "Entry 1101"}, 246157642Sps /* Ateml Expansion entry 1110 */ 247157642Sps {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400, 248179771Sdavidch BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 249157642Sps BUFFERED_FLASH_BYTE_ADDR_MASK, 0, 250157642Sps "Entry 1110 (Atmel)"}, 251157642Sps /* ATMEL AT45DB021B (buffered flash) */ 252157642Sps {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400, 253179771Sdavidch BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 254157642Sps BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2, 255157642Sps "Buffered flash (256kB)"}, 256157642Sps}; 257157642Sps 258179771Sdavidch/* 259179771Sdavidch * The BCM5709 controllers transparently handle the 260179771Sdavidch * differences between Atmel 264 byte pages and all 261179771Sdavidch * flash devices which use 256 byte pages, so no 262179771Sdavidch * logical-to-physical mapping is required in the 263179771Sdavidch * driver. 264179771Sdavidch */ 265179771Sdavidchstatic struct flash_spec flash_5709 = { 266179771Sdavidch .flags = BCE_NV_BUFFERED, 267179771Sdavidch .page_bits = BCM5709_FLASH_PAGE_BITS, 268179771Sdavidch .page_size = BCM5709_FLASH_PAGE_SIZE, 269179771Sdavidch .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK, 270179771Sdavidch .total_size = BUFFERED_FLASH_TOTAL_SIZE * 2, 271182293Sdavidch .name = "5709/5716 buffered flash (256kB)", 272179771Sdavidch}; 273157642Sps 274179771Sdavidch 275157642Sps/****************************************************************************/ 276157642Sps/* FreeBSD device entry points. */ 277157642Sps/****************************************************************************/ 278157642Spsstatic int bce_probe (device_t); 279157642Spsstatic int bce_attach (device_t); 280157642Spsstatic int bce_detach (device_t); 281173839Syongaristatic int bce_shutdown (device_t); 282157642Sps 283157642Sps 284157642Sps/****************************************************************************/ 285157642Sps/* BCE Debug Data Structure Dump Routines */ 286157642Sps/****************************************************************************/ 287157642Sps#ifdef BCE_DEBUG 288179771Sdavidchstatic u32 bce_reg_rd (struct bce_softc *, u32); 289179771Sdavidchstatic void bce_reg_wr (struct bce_softc *, u32, u32); 290179771Sdavidchstatic void bce_reg_wr16 (struct bce_softc *, u32, u16); 291176448Sdavidchstatic u32 bce_ctx_rd (struct bce_softc *, u32, u32); 292182293Sdavidchstatic void bce_dump_enet (struct bce_softc *, struct mbuf *); 293157642Spsstatic void bce_dump_mbuf (struct bce_softc *, struct mbuf *); 294176448Sdavidchstatic void bce_dump_tx_mbuf_chain (struct bce_softc *, u16, int); 295176448Sdavidchstatic void bce_dump_rx_mbuf_chain (struct bce_softc *, u16, int); 296198320Sstas#ifdef BCE_JUMBO_HDRSPLIT 297179771Sdavidchstatic void bce_dump_pg_mbuf_chain (struct bce_softc *, u16, int); 298179695Sdavidch#endif 299157642Spsstatic void bce_dump_txbd (struct bce_softc *, int, struct tx_bd *); 300157642Spsstatic void bce_dump_rxbd (struct bce_softc *, int, struct rx_bd *); 301198320Sstas#ifdef BCE_JUMBO_HDRSPLIT 302179771Sdavidchstatic void bce_dump_pgbd (struct bce_softc *, int, struct rx_bd *); 303179695Sdavidch#endif 304157642Spsstatic void bce_dump_l2fhdr (struct bce_softc *, int, struct l2_fhdr *); 305176448Sdavidchstatic void bce_dump_ctx (struct bce_softc *, u16); 306176448Sdavidchstatic void bce_dump_ftqs (struct bce_softc *); 307176448Sdavidchstatic void bce_dump_tx_chain (struct bce_softc *, u16, int); 308176448Sdavidchstatic void bce_dump_rx_chain (struct bce_softc *, u16, int); 309198320Sstas#ifdef BCE_JUMBO_HDRSPLIT 310179771Sdavidchstatic void bce_dump_pg_chain (struct bce_softc *, u16, int); 311179695Sdavidch#endif 312157642Spsstatic void bce_dump_status_block (struct bce_softc *); 313157642Spsstatic void bce_dump_stats_block (struct bce_softc *); 314157642Spsstatic void bce_dump_driver_state (struct bce_softc *); 315157642Spsstatic void bce_dump_hw_state (struct bce_softc *); 316179771Sdavidchstatic void bce_dump_mq_regs (struct bce_softc *); 317170810Sdavidchstatic void bce_dump_bc_state (struct bce_softc *); 318179771Sdavidchstatic void bce_dump_txp_state (struct bce_softc *, int); 319179771Sdavidchstatic void bce_dump_rxp_state (struct bce_softc *, int); 320179771Sdavidchstatic void bce_dump_tpat_state (struct bce_softc *, int); 321179771Sdavidchstatic void bce_dump_cp_state (struct bce_softc *, int); 322179771Sdavidchstatic void bce_dump_com_state (struct bce_softc *, int); 323157642Spsstatic void bce_breakpoint (struct bce_softc *); 324157642Sps#endif 325157642Sps 326157642Sps 327157642Sps/****************************************************************************/ 328157642Sps/* BCE Register/Memory Access Routines */ 329157642Sps/****************************************************************************/ 330157642Spsstatic u32 bce_reg_rd_ind (struct bce_softc *, u32); 331157642Spsstatic void bce_reg_wr_ind (struct bce_softc *, u32, u32); 332194781Sdavidchstatic void bce_shmem_wr (struct bce_softc *, u32, u32); 333194781Sdavidchstatic u32 bce_shmem_rd (struct bce_softc *, u32); 334157642Spsstatic void bce_ctx_wr (struct bce_softc *, u32, u32, u32); 335157642Spsstatic int bce_miibus_read_reg (device_t, int, int); 336157642Spsstatic int bce_miibus_write_reg (device_t, int, int, int); 337157642Spsstatic void bce_miibus_statchg (device_t); 338157642Sps 339157642Sps 340157642Sps/****************************************************************************/ 341157642Sps/* BCE NVRAM Access Routines */ 342157642Sps/****************************************************************************/ 343157642Spsstatic int bce_acquire_nvram_lock (struct bce_softc *); 344157642Spsstatic int bce_release_nvram_lock (struct bce_softc *); 345157642Spsstatic void bce_enable_nvram_access (struct bce_softc *); 346157642Spsstatic void bce_disable_nvram_access(struct bce_softc *); 347157642Spsstatic int bce_nvram_read_dword (struct bce_softc *, u32, u8 *, u32); 348157642Spsstatic int bce_init_nvram (struct bce_softc *); 349157642Spsstatic int bce_nvram_read (struct bce_softc *, u32, u8 *, int); 350157642Spsstatic int bce_nvram_test (struct bce_softc *); 351157642Sps#ifdef BCE_NVRAM_WRITE_SUPPORT 352157642Spsstatic int bce_enable_nvram_write (struct bce_softc *); 353157642Spsstatic void bce_disable_nvram_write (struct bce_softc *); 354157642Spsstatic int bce_nvram_erase_page (struct bce_softc *, u32); 355157642Spsstatic int bce_nvram_write_dword (struct bce_softc *, u32, u8 *, u32); 356157642Spsstatic int bce_nvram_write (struct bce_softc *, u32, u8 *, int); 357157642Sps#endif 358157642Sps 359157642Sps/****************************************************************************/ 360157642Sps/* */ 361157642Sps/****************************************************************************/ 362179771Sdavidchstatic void bce_get_media (struct bce_softc *); 363157642Spsstatic void bce_dma_map_addr (void *, bus_dma_segment_t *, int, int); 364157642Spsstatic int bce_dma_alloc (device_t); 365157642Spsstatic void bce_dma_free (struct bce_softc *); 366157642Spsstatic void bce_release_resources (struct bce_softc *); 367157642Sps 368157642Sps/****************************************************************************/ 369157642Sps/* BCE Firmware Synchronization and Load */ 370157642Sps/****************************************************************************/ 371157642Spsstatic int bce_fw_sync (struct bce_softc *, u32); 372157642Spsstatic void bce_load_rv2p_fw (struct bce_softc *, u32 *, u32, u32); 373157642Spsstatic void bce_load_cpu_fw (struct bce_softc *, struct cpu_reg *, struct fw_info *); 374202717Sdavidchstatic void bce_start_cpu (struct bce_softc *, struct cpu_reg *); 375202717Sdavidchstatic void bce_halt_cpu (struct bce_softc *, struct cpu_reg *); 376202717Sdavidchstatic void bce_start_rxp_cpu (struct bce_softc *); 377179771Sdavidchstatic void bce_init_rxp_cpu (struct bce_softc *); 378179771Sdavidchstatic void bce_init_txp_cpu (struct bce_softc *); 379179771Sdavidchstatic void bce_init_tpat_cpu (struct bce_softc *); 380179771Sdavidchstatic void bce_init_cp_cpu (struct bce_softc *); 381179771Sdavidchstatic void bce_init_com_cpu (struct bce_softc *); 382157642Spsstatic void bce_init_cpus (struct bce_softc *); 383157642Sps 384179771Sdavidchstatic void bce_print_adapter_info (struct bce_softc *); 385179771Sdavidchstatic void bce_probe_pci_caps (device_t, struct bce_softc *); 386157642Spsstatic void bce_stop (struct bce_softc *); 387157642Spsstatic int bce_reset (struct bce_softc *, u32); 388157642Spsstatic int bce_chipinit (struct bce_softc *); 389157642Spsstatic int bce_blockinit (struct bce_softc *); 390157642Sps 391157642Spsstatic int bce_init_tx_chain (struct bce_softc *); 392176448Sdavidchstatic void bce_free_tx_chain (struct bce_softc *); 393176448Sdavidch 394179771Sdavidchstatic int bce_get_rx_buf (struct bce_softc *, struct mbuf *, u16 *, u16 *, u32 *); 395176448Sdavidchstatic int bce_init_rx_chain (struct bce_softc *); 396171667Sdavidchstatic void bce_fill_rx_chain (struct bce_softc *); 397157642Spsstatic void bce_free_rx_chain (struct bce_softc *); 398179771Sdavidch 399198320Sstas#ifdef BCE_JUMBO_HDRSPLIT 400179771Sdavidchstatic int bce_get_pg_buf (struct bce_softc *, struct mbuf *, u16 *, u16 *); 401176448Sdavidchstatic int bce_init_pg_chain (struct bce_softc *); 402176448Sdavidchstatic void bce_fill_pg_chain (struct bce_softc *); 403179771Sdavidchstatic void bce_free_pg_chain (struct bce_softc *); 404179695Sdavidch#endif 405176448Sdavidch 406204373Syongaristatic struct mbuf *bce_tso_setup (struct bce_softc *, struct mbuf **, u16 *); 407171667Sdavidchstatic int bce_tx_encap (struct bce_softc *, struct mbuf **); 408157642Spsstatic void bce_start_locked (struct ifnet *); 409157642Spsstatic void bce_start (struct ifnet *); 410157642Spsstatic int bce_ioctl (struct ifnet *, u_long, caddr_t); 411165933Sdelphijstatic void bce_watchdog (struct bce_softc *); 412157642Spsstatic int bce_ifmedia_upd (struct ifnet *); 413171667Sdavidchstatic void bce_ifmedia_upd_locked (struct ifnet *); 414157642Spsstatic void bce_ifmedia_sts (struct ifnet *, struct ifmediareq *); 415157642Spsstatic void bce_init_locked (struct bce_softc *); 416157642Spsstatic void bce_init (void *); 417171667Sdavidchstatic void bce_mgmt_init_locked (struct bce_softc *sc); 418157642Sps 419176448Sdavidchstatic void bce_init_ctx (struct bce_softc *); 420157642Spsstatic void bce_get_mac_addr (struct bce_softc *); 421157642Spsstatic void bce_set_mac_addr (struct bce_softc *); 422157642Spsstatic void bce_phy_intr (struct bce_softc *); 423176448Sdavidchstatic inline u16 bce_get_hw_rx_cons(struct bce_softc *); 424157642Spsstatic void bce_rx_intr (struct bce_softc *); 425157642Spsstatic void bce_tx_intr (struct bce_softc *); 426157642Spsstatic void bce_disable_intr (struct bce_softc *); 427179771Sdavidchstatic void bce_enable_intr (struct bce_softc *, int); 428179771Sdavidch 429157642Spsstatic void bce_intr (void *); 430157642Spsstatic void bce_set_rx_mode (struct bce_softc *); 431157642Spsstatic void bce_stats_update (struct bce_softc *); 432157642Spsstatic void bce_tick (void *); 433170810Sdavidchstatic void bce_pulse (void *); 434157642Spsstatic void bce_add_sysctls (struct bce_softc *); 435157642Sps 436157642Sps 437157642Sps/****************************************************************************/ 438157642Sps/* FreeBSD device dispatch table. */ 439157642Sps/****************************************************************************/ 440157642Spsstatic device_method_t bce_methods[] = { 441176448Sdavidch /* Device interface (device_if.h) */ 442157642Sps DEVMETHOD(device_probe, bce_probe), 443157642Sps DEVMETHOD(device_attach, bce_attach), 444157642Sps DEVMETHOD(device_detach, bce_detach), 445157642Sps DEVMETHOD(device_shutdown, bce_shutdown), 446178132Sdavidch/* Supported by device interface but not used here. */ 447176448Sdavidch/* DEVMETHOD(device_identify, bce_identify), */ 448176448Sdavidch/* DEVMETHOD(device_suspend, bce_suspend), */ 449176448Sdavidch/* DEVMETHOD(device_resume, bce_resume), */ 450176448Sdavidch/* DEVMETHOD(device_quiesce, bce_quiesce), */ 451157642Sps 452176448Sdavidch /* Bus interface (bus_if.h) */ 453157642Sps DEVMETHOD(bus_print_child, bus_generic_print_child), 454157642Sps DEVMETHOD(bus_driver_added, bus_generic_driver_added), 455157642Sps 456176448Sdavidch /* MII interface (miibus_if.h) */ 457157642Sps DEVMETHOD(miibus_readreg, bce_miibus_read_reg), 458157642Sps DEVMETHOD(miibus_writereg, bce_miibus_write_reg), 459157642Sps DEVMETHOD(miibus_statchg, bce_miibus_statchg), 460178132Sdavidch/* Supported by MII interface but not used here. */ 461176448Sdavidch/* DEVMETHOD(miibus_linkchg, bce_miibus_linkchg), */ 462176448Sdavidch/* DEVMETHOD(miibus_mediainit, bce_miibus_mediainit), */ 463157642Sps 464157642Sps { 0, 0 } 465157642Sps}; 466157642Sps 467157642Spsstatic driver_t bce_driver = { 468157642Sps "bce", 469157642Sps bce_methods, 470157642Sps sizeof(struct bce_softc) 471157642Sps}; 472157642Sps 473157642Spsstatic devclass_t bce_devclass; 474157642Sps 475157642SpsMODULE_DEPEND(bce, pci, 1, 1, 1); 476157642SpsMODULE_DEPEND(bce, ether, 1, 1, 1); 477157642SpsMODULE_DEPEND(bce, miibus, 1, 1, 1); 478157642Sps 479157642SpsDRIVER_MODULE(bce, pci, bce_driver, bce_devclass, 0, 0); 480157642SpsDRIVER_MODULE(miibus, bce, miibus_driver, miibus_devclass, 0, 0); 481170392Sdavidch 482170392Sdavidch 483169632Sdavidch/****************************************************************************/ 484169632Sdavidch/* Tunable device values */ 485169632Sdavidch/****************************************************************************/ 486176448SdavidchSYSCTL_NODE(_hw, OID_AUTO, bce, CTLFLAG_RD, 0, "bce driver parameters"); 487176448Sdavidch 488170392Sdavidch/* Allowable values are TRUE or FALSE */ 489179771Sdavidchstatic int bce_tso_enable = TRUE; 490170392SdavidchTUNABLE_INT("hw.bce.tso_enable", &bce_tso_enable); 491176448SdavidchSYSCTL_UINT(_hw_bce, OID_AUTO, tso_enable, CTLFLAG_RDTUN, &bce_tso_enable, 0, 492176448Sdavidch"TSO Enable/Disable"); 493176448Sdavidch 494179771Sdavidch/* Allowable values are 0 (IRQ), 1 (MSI/IRQ), and 2 (MSI-X/MSI/IRQ) */ 495179771Sdavidch/* ToDo: Add MSI-X support. */ 496179771Sdavidchstatic int bce_msi_enable = 1; 497169632SdavidchTUNABLE_INT("hw.bce.msi_enable", &bce_msi_enable); 498170392SdavidchSYSCTL_UINT(_hw_bce, OID_AUTO, msi_enable, CTLFLAG_RDTUN, &bce_msi_enable, 0, 499179771Sdavidch"MSI-X|MSI|INTx selector"); 500178132Sdavidch 501178132Sdavidch/* ToDo: Add tunable to enable/disable strict MTU handling. */ 502178132Sdavidch/* Currently allows "loose" RX MTU checking (i.e. sets the */ 503182293Sdavidch/* H/W RX MTU to the size of the largest receive buffer, or */ 504189325Sdavidch/* 2048 bytes). This will cause a UNH failure but is more */ 505189325Sdavidch/* desireable from a functional perspective. */ 506170392Sdavidch 507182293Sdavidch 508157642Sps/****************************************************************************/ 509157642Sps/* Device probe function. */ 510157642Sps/* */ 511157642Sps/* Compares the device to the driver's list of supported devices and */ 512157642Sps/* reports back to the OS whether this is the right driver for the device. */ 513157642Sps/* */ 514157642Sps/* Returns: */ 515157642Sps/* BUS_PROBE_DEFAULT on success, positive value on failure. */ 516157642Sps/****************************************************************************/ 517157642Spsstatic int 518157642Spsbce_probe(device_t dev) 519157642Sps{ 520157642Sps struct bce_type *t; 521157642Sps struct bce_softc *sc; 522157642Sps char *descbuf; 523157642Sps u16 vid = 0, did = 0, svid = 0, sdid = 0; 524157642Sps 525157642Sps t = bce_devs; 526157642Sps 527157642Sps sc = device_get_softc(dev); 528157642Sps bzero(sc, sizeof(struct bce_softc)); 529157642Sps sc->bce_unit = device_get_unit(dev); 530157642Sps sc->bce_dev = dev; 531157642Sps 532157642Sps /* Get the data for the device to be probed. */ 533157642Sps vid = pci_get_vendor(dev); 534157642Sps did = pci_get_device(dev); 535157642Sps svid = pci_get_subvendor(dev); 536157642Sps sdid = pci_get_subdevice(dev); 537157642Sps 538179771Sdavidch DBPRINT(sc, BCE_EXTREME_LOAD, 539157642Sps "%s(); VID = 0x%04X, DID = 0x%04X, SVID = 0x%04X, " 540157642Sps "SDID = 0x%04X\n", __FUNCTION__, vid, did, svid, sdid); 541157642Sps 542157642Sps /* Look through the list of known devices for a match. */ 543157642Sps while(t->bce_name != NULL) { 544157642Sps 545179771Sdavidch if ((vid == t->bce_vid) && (did == t->bce_did) && 546157642Sps ((svid == t->bce_svid) || (t->bce_svid == PCI_ANY_ID)) && 547157642Sps ((sdid == t->bce_sdid) || (t->bce_sdid == PCI_ANY_ID))) { 548157642Sps 549157642Sps descbuf = malloc(BCE_DEVDESC_MAX, M_TEMP, M_NOWAIT); 550157642Sps 551157642Sps if (descbuf == NULL) 552157642Sps return(ENOMEM); 553157642Sps 554157642Sps /* Print out the device identity. */ 555179771Sdavidch snprintf(descbuf, BCE_DEVDESC_MAX, "%s (%c%d)", 556157642Sps t->bce_name, 557157642Sps (((pci_read_config(dev, PCIR_REVID, 4) & 0xf0) >> 4) + 'A'), 558169271Sdavidch (pci_read_config(dev, PCIR_REVID, 4) & 0xf)); 559157642Sps 560157642Sps device_set_desc_copy(dev, descbuf); 561157642Sps free(descbuf, M_TEMP); 562157642Sps return(BUS_PROBE_DEFAULT); 563157642Sps } 564157642Sps t++; 565157642Sps } 566157642Sps 567157642Sps return(ENXIO); 568157642Sps} 569157642Sps 570157642Sps 571157642Sps/****************************************************************************/ 572179771Sdavidch/* PCI Capabilities Probe Function. */ 573179771Sdavidch/* */ 574179771Sdavidch/* Walks the PCI capabiites list for the device to find what features are */ 575179771Sdavidch/* supported. */ 576179771Sdavidch/* */ 577179771Sdavidch/* Returns: */ 578179771Sdavidch/* None. */ 579179771Sdavidch/****************************************************************************/ 580179771Sdavidchstatic void 581179771Sdavidchbce_print_adapter_info(struct bce_softc *sc) 582179771Sdavidch{ 583194781Sdavidch int i = 0; 584194781Sdavidch 585179771Sdavidch DBENTER(BCE_VERBOSE_LOAD); 586179771Sdavidch 587179771Sdavidch BCE_PRINTF("ASIC (0x%08X); ", sc->bce_chipid); 588179771Sdavidch printf("Rev (%c%d); ", ((BCE_CHIP_ID(sc) & 0xf000) >> 12) + 'A', 589179771Sdavidch ((BCE_CHIP_ID(sc) & 0x0ff0) >> 4)); 590179771Sdavidch 591179771Sdavidch /* Bus info. */ 592179771Sdavidch if (sc->bce_flags & BCE_PCIE_FLAG) { 593179771Sdavidch printf("Bus (PCIe x%d, ", sc->link_width); 594179771Sdavidch switch (sc->link_speed) { 595179771Sdavidch case 1: printf("2.5Gbps); "); break; 596179771Sdavidch case 2: printf("5Gbps); "); break; 597179771Sdavidch default: printf("Unknown link speed); "); 598179771Sdavidch } 599179771Sdavidch } else { 600179771Sdavidch printf("Bus (PCI%s, %s, %dMHz); ", 601179771Sdavidch ((sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : ""), 602179771Sdavidch ((sc->bce_flags & BCE_PCI_32BIT_FLAG) ? "32-bit" : "64-bit"), 603179771Sdavidch sc->bus_speed_mhz); 604179771Sdavidch } 605179771Sdavidch 606179771Sdavidch /* Firmware version and device features. */ 607194781Sdavidch printf("B/C (%s); Flags (", sc->bce_bc_ver); 608194781Sdavidch 609198320Sstas#ifdef BCE_JUMBO_HDRSPLIT 610202717Sdavidch printf("SPLT"); 611194781Sdavidch i++; 612179771Sdavidch#endif 613202717Sdavidch 614194781Sdavidch if (sc->bce_flags & BCE_USING_MSI_FLAG) { 615194781Sdavidch if (i > 0) printf("|"); 616196970Sphk printf("MSI"); i++; 617194781Sdavidch } 618179771Sdavidch 619194781Sdavidch if (sc->bce_flags & BCE_USING_MSIX_FLAG) { 620194781Sdavidch if (i > 0) printf("|"); 621202717Sdavidch printf("MSI-X"); i++; 622194781Sdavidch } 623194781Sdavidch 624194781Sdavidch if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) { 625194781Sdavidch if (i > 0) printf("|"); 626196970Sphk printf("2.5G"); i++; 627194781Sdavidch } 628194781Sdavidch 629194781Sdavidch if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 630194781Sdavidch if (i > 0) printf("|"); 631194781Sdavidch printf("MFW); MFW (%s)\n", sc->bce_mfw_ver); 632194781Sdavidch } else { 633194781Sdavidch printf(")\n"); 634194781Sdavidch } 635194781Sdavidch 636196970Sphk DBEXIT(BCE_VERBOSE_LOAD); 637179771Sdavidch} 638179771Sdavidch 639179771Sdavidch 640179771Sdavidch/****************************************************************************/ 641179771Sdavidch/* PCI Capabilities Probe Function. */ 642179771Sdavidch/* */ 643179771Sdavidch/* Walks the PCI capabiites list for the device to find what features are */ 644179771Sdavidch/* supported. */ 645179771Sdavidch/* */ 646179771Sdavidch/* Returns: */ 647179771Sdavidch/* None. */ 648179771Sdavidch/****************************************************************************/ 649179771Sdavidchstatic void 650179771Sdavidchbce_probe_pci_caps(device_t dev, struct bce_softc *sc) 651179771Sdavidch{ 652179771Sdavidch u32 reg; 653179771Sdavidch 654179771Sdavidch DBENTER(BCE_VERBOSE_LOAD); 655179771Sdavidch 656179771Sdavidch /* Check if PCI-X capability is enabled. */ 657179771Sdavidch if (pci_find_extcap(dev, PCIY_PCIX, ®) == 0) { 658179771Sdavidch if (reg != 0) 659179771Sdavidch sc->bce_cap_flags |= BCE_PCIX_CAPABLE_FLAG; 660179771Sdavidch } 661179771Sdavidch 662179771Sdavidch /* Check if PCIe capability is enabled. */ 663179771Sdavidch if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { 664179771Sdavidch if (reg != 0) { 665179771Sdavidch u16 link_status = pci_read_config(dev, reg + 0x12, 2); 666179771Sdavidch DBPRINT(sc, BCE_INFO_LOAD, "PCIe link_status = 0x%08X\n", 667179771Sdavidch link_status); 668179771Sdavidch sc->link_speed = link_status & 0xf; 669179771Sdavidch sc->link_width = (link_status >> 4) & 0x3f; 670179771Sdavidch sc->bce_cap_flags |= BCE_PCIE_CAPABLE_FLAG; 671179771Sdavidch sc->bce_flags |= BCE_PCIE_FLAG; 672179771Sdavidch } 673179771Sdavidch } 674179771Sdavidch 675179771Sdavidch /* Check if MSI capability is enabled. */ 676179771Sdavidch if (pci_find_extcap(dev, PCIY_MSI, ®) == 0) { 677179771Sdavidch if (reg != 0) 678179771Sdavidch sc->bce_cap_flags |= BCE_MSI_CAPABLE_FLAG; 679179771Sdavidch } 680179771Sdavidch 681179771Sdavidch /* Check if MSI-X capability is enabled. */ 682179771Sdavidch if (pci_find_extcap(dev, PCIY_MSIX, ®) == 0) { 683179771Sdavidch if (reg != 0) 684179771Sdavidch sc->bce_cap_flags |= BCE_MSIX_CAPABLE_FLAG; 685179771Sdavidch } 686179771Sdavidch 687179771Sdavidch DBEXIT(BCE_VERBOSE_LOAD); 688179771Sdavidch} 689179771Sdavidch 690179771Sdavidch 691179771Sdavidch/****************************************************************************/ 692157642Sps/* Device attach function. */ 693157642Sps/* */ 694157642Sps/* Allocates device resources, performs secondary chip identification, */ 695157642Sps/* resets and initializes the hardware, and initializes driver instance */ 696157642Sps/* variables. */ 697157642Sps/* */ 698157642Sps/* Returns: */ 699157642Sps/* 0 on success, positive value on failure. */ 700157642Sps/****************************************************************************/ 701157642Spsstatic int 702157642Spsbce_attach(device_t dev) 703157642Sps{ 704157642Sps struct bce_softc *sc; 705157642Sps struct ifnet *ifp; 706157642Sps u32 val; 707179771Sdavidch int error, rid, rc = 0; 708157642Sps 709157642Sps sc = device_get_softc(dev); 710157642Sps sc->bce_dev = dev; 711157642Sps 712179771Sdavidch DBENTER(BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 713157642Sps 714176448Sdavidch sc->bce_unit = device_get_unit(dev); 715170392Sdavidch 716169632Sdavidch /* Set initial device and PHY flags */ 717169632Sdavidch sc->bce_flags = 0; 718169632Sdavidch sc->bce_phy_flags = 0; 719169632Sdavidch 720157642Sps pci_enable_busmaster(dev); 721157642Sps 722157642Sps /* Allocate PCI memory resources. */ 723157642Sps rid = PCIR_BAR(0); 724169632Sdavidch sc->bce_res_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 725178588Smarius &rid, RF_ACTIVE); 726157642Sps 727169632Sdavidch if (sc->bce_res_mem == NULL) { 728179771Sdavidch BCE_PRINTF("%s(%d): PCI memory allocation failed\n", 729157642Sps __FILE__, __LINE__); 730157642Sps rc = ENXIO; 731157642Sps goto bce_attach_fail; 732157642Sps } 733157642Sps 734157642Sps /* Get various resource handles. */ 735169632Sdavidch sc->bce_btag = rman_get_bustag(sc->bce_res_mem); 736169632Sdavidch sc->bce_bhandle = rman_get_bushandle(sc->bce_res_mem); 737169632Sdavidch sc->bce_vhandle = (vm_offset_t) rman_get_virtual(sc->bce_res_mem); 738157642Sps 739179771Sdavidch bce_probe_pci_caps(dev, sc); 740170392Sdavidch 741179771Sdavidch rid = 1; 742179771Sdavidch#if 0 743179771Sdavidch /* Try allocating MSI-X interrupts. */ 744179771Sdavidch if ((sc->bce_cap_flags & BCE_MSIX_CAPABLE_FLAG) && 745179771Sdavidch (bce_msi_enable >= 2) && 746179771Sdavidch ((sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 747179771Sdavidch &rid, RF_ACTIVE)) != NULL)) { 748179771Sdavidch 749179771Sdavidch msi_needed = sc->bce_msi_count = 1; 750179771Sdavidch 751179771Sdavidch if (((error = pci_alloc_msix(dev, &sc->bce_msi_count)) != 0) || 752179771Sdavidch (sc->bce_msi_count != msi_needed)) { 753179771Sdavidch BCE_PRINTF("%s(%d): MSI-X allocation failed! Requested = %d," 754179771Sdavidch "Received = %d, error = %d\n", __FILE__, __LINE__, 755179771Sdavidch msi_needed, sc->bce_msi_count, error); 756179771Sdavidch sc->bce_msi_count = 0; 757179771Sdavidch pci_release_msi(dev); 758179771Sdavidch bus_release_resource(dev, SYS_RES_MEMORY, rid, 759179771Sdavidch sc->bce_res_irq); 760179771Sdavidch sc->bce_res_irq = NULL; 761179771Sdavidch } else { 762179771Sdavidch DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using MSI-X interrupt.\n", 763179771Sdavidch __FUNCTION__); 764179771Sdavidch sc->bce_flags |= BCE_USING_MSIX_FLAG; 765179771Sdavidch sc->bce_intr = bce_intr; 766179771Sdavidch } 767179771Sdavidch } 768179771Sdavidch#endif 769179771Sdavidch 770179771Sdavidch /* Try allocating a MSI interrupt. */ 771179771Sdavidch if ((sc->bce_cap_flags & BCE_MSI_CAPABLE_FLAG) && 772179771Sdavidch (bce_msi_enable >= 1) && (sc->bce_msi_count == 0)) { 773179771Sdavidch sc->bce_msi_count = 1; 774179771Sdavidch if ((error = pci_alloc_msi(dev, &sc->bce_msi_count)) != 0) { 775179771Sdavidch BCE_PRINTF("%s(%d): MSI allocation failed! error = %d\n", 776179771Sdavidch __FILE__, __LINE__, error); 777179771Sdavidch sc->bce_msi_count = 0; 778179771Sdavidch pci_release_msi(dev); 779179771Sdavidch } else { 780179771Sdavidch DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using MSI interrupt.\n", 781179771Sdavidch __FUNCTION__); 782179771Sdavidch sc->bce_flags |= BCE_USING_MSI_FLAG; 783182293Sdavidch if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 784182293Sdavidch (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) 785179771Sdavidch sc->bce_flags |= BCE_ONE_SHOT_MSI_FLAG; 786179771Sdavidch sc->bce_irq_rid = 1; 787179771Sdavidch sc->bce_intr = bce_intr; 788179771Sdavidch } 789179771Sdavidch } 790179771Sdavidch 791179771Sdavidch /* Try allocating a legacy interrupt. */ 792179771Sdavidch if (sc->bce_msi_count == 0) { 793179771Sdavidch DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using INTx interrupt.\n", 794179771Sdavidch __FUNCTION__); 795170392Sdavidch rid = 0; 796179771Sdavidch sc->bce_intr = bce_intr; 797169632Sdavidch } 798170392Sdavidch 799179771Sdavidch sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 800179771Sdavidch &rid, RF_SHAREABLE | RF_ACTIVE); 801157642Sps 802179771Sdavidch sc->bce_irq_rid = rid; 803179771Sdavidch 804179771Sdavidch /* Report any IRQ allocation errors. */ 805169632Sdavidch if (sc->bce_res_irq == NULL) { 806179771Sdavidch BCE_PRINTF("%s(%d): PCI map interrupt failed!\n", 807157642Sps __FILE__, __LINE__); 808157642Sps rc = ENXIO; 809157642Sps goto bce_attach_fail; 810157642Sps } 811157642Sps 812157642Sps /* Initialize mutex for the current device instance. */ 813157642Sps BCE_LOCK_INIT(sc, device_get_nameunit(dev)); 814157642Sps 815157642Sps /* 816157642Sps * Configure byte swap and enable indirect register access. 817157642Sps * Rely on CPU to do target byte swapping on big endian systems. 818157642Sps * Access to registers outside of PCI configurtion space are not 819157642Sps * valid until this is done. 820157642Sps */ 821157642Sps pci_write_config(dev, BCE_PCICFG_MISC_CONFIG, 822157642Sps BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 823157642Sps BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP, 4); 824157642Sps 825157642Sps /* Save ASIC revsion info. */ 826157642Sps sc->bce_chipid = REG_RD(sc, BCE_MISC_ID); 827157642Sps 828157642Sps /* Weed out any non-production controller revisions. */ 829157642Sps switch(BCE_CHIP_ID(sc)) { 830157642Sps case BCE_CHIP_ID_5706_A0: 831157642Sps case BCE_CHIP_ID_5706_A1: 832157642Sps case BCE_CHIP_ID_5708_A0: 833157642Sps case BCE_CHIP_ID_5708_B0: 834179771Sdavidch case BCE_CHIP_ID_5709_A0: 835179771Sdavidch case BCE_CHIP_ID_5709_B0: 836179771Sdavidch case BCE_CHIP_ID_5709_B1: 837179771Sdavidch case BCE_CHIP_ID_5709_B2: 838169271Sdavidch BCE_PRINTF("%s(%d): Unsupported controller revision (%c%d)!\n", 839179771Sdavidch __FILE__, __LINE__, 840157642Sps (((pci_read_config(dev, PCIR_REVID, 4) & 0xf0) >> 4) + 'A'), 841157642Sps (pci_read_config(dev, PCIR_REVID, 4) & 0xf)); 842157642Sps rc = ENODEV; 843157642Sps goto bce_attach_fail; 844157642Sps } 845157642Sps 846179771Sdavidch /* 847179771Sdavidch * The embedded PCIe to PCI-X bridge (EPB) 848179771Sdavidch * in the 5708 cannot address memory above 849179771Sdavidch * 40 bits (E7_5708CB1_23043 & E6_5708SB1_23043). 850157642Sps */ 851157642Sps if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708) 852157642Sps sc->max_bus_addr = BCE_BUS_SPACE_MAXADDR; 853157642Sps else 854157642Sps sc->max_bus_addr = BUS_SPACE_MAXADDR; 855157642Sps 856157642Sps /* 857157642Sps * Find the base address for shared memory access. 858157642Sps * Newer versions of bootcode use a signature and offset 859157642Sps * while older versions use a fixed address. 860157642Sps */ 861157642Sps val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE); 862157642Sps if ((val & BCE_SHM_HDR_SIGNATURE_SIG_MASK) == BCE_SHM_HDR_SIGNATURE_SIG) 863179771Sdavidch /* Multi-port devices use different offsets in shared memory. */ 864179771Sdavidch sc->bce_shmem_base = REG_RD_IND(sc, BCE_SHM_HDR_ADDR_0 + 865179771Sdavidch (pci_get_function(sc->bce_dev) << 2)); 866157642Sps else 867157642Sps sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE; 868157642Sps 869179771Sdavidch DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): bce_shmem_base = 0x%08X\n", 870170810Sdavidch __FUNCTION__, sc->bce_shmem_base); 871157642Sps 872178132Sdavidch /* Fetch the bootcode revision. */ 873194781Sdavidch val = bce_shmem_rd(sc, BCE_DEV_INFO_BC_REV); 874194781Sdavidch for (int i = 0, j = 0; i < 3; i++) { 875194781Sdavidch u8 num; 876170810Sdavidch 877194781Sdavidch num = (u8) (val >> (24 - (i * 8))); 878194781Sdavidch for (int k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) { 879194781Sdavidch if (num >= k || !skip0 || k == 1) { 880194781Sdavidch sc->bce_bc_ver[j++] = (num / k) + '0'; 881194781Sdavidch skip0 = 0; 882194781Sdavidch } 883194781Sdavidch } 884194781Sdavidch if (i != 2) 885194781Sdavidch sc->bce_bc_ver[j++] = '.'; 886194781Sdavidch } 887170810Sdavidch 888194781Sdavidch /* Check if any management firwmare is running. */ 889194781Sdavidch val = bce_shmem_rd(sc, BCE_PORT_FEATURE); 890194781Sdavidch if (val & BCE_PORT_FEATURE_ASF_ENABLED) { 891194781Sdavidch sc->bce_flags |= BCE_MFW_ENABLE_FLAG; 892194781Sdavidch 893194781Sdavidch /* Allow time for firmware to enter the running state. */ 894194781Sdavidch for (int i = 0; i < 30; i++) { 895194781Sdavidch val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); 896194781Sdavidch if (val & BCE_CONDITION_MFW_RUN_MASK) 897194781Sdavidch break; 898194781Sdavidch DELAY(10000); 899194781Sdavidch } 900194781Sdavidch } 901194781Sdavidch 902194781Sdavidch /* Check the current bootcode state. */ 903194781Sdavidch val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); 904194781Sdavidch val &= BCE_CONDITION_MFW_RUN_MASK; 905194781Sdavidch if (val != BCE_CONDITION_MFW_RUN_UNKNOWN && 906194781Sdavidch val != BCE_CONDITION_MFW_RUN_NONE) { 907194781Sdavidch u32 addr = bce_shmem_rd(sc, BCE_MFW_VER_PTR); 908194781Sdavidch int i = 0; 909194781Sdavidch 910194781Sdavidch for (int j = 0; j < 3; j++) { 911194781Sdavidch val = bce_reg_rd_ind(sc, addr + j * 4); 912194781Sdavidch val = bswap32(val); 913194781Sdavidch memcpy(&sc->bce_mfw_ver[i], &val, 4); 914194781Sdavidch i += 4; 915194781Sdavidch } 916194781Sdavidch } 917194781Sdavidch 918157642Sps /* Get PCI bus information (speed and type). */ 919157642Sps val = REG_RD(sc, BCE_PCICFG_MISC_STATUS); 920157642Sps if (val & BCE_PCICFG_MISC_STATUS_PCIX_DET) { 921157642Sps u32 clkreg; 922157642Sps 923157642Sps sc->bce_flags |= BCE_PCIX_FLAG; 924157642Sps 925157642Sps clkreg = REG_RD(sc, BCE_PCICFG_PCI_CLOCK_CONTROL_BITS); 926157642Sps 927157642Sps clkreg &= BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET; 928157642Sps switch (clkreg) { 929157642Sps case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ: 930157642Sps sc->bus_speed_mhz = 133; 931157642Sps break; 932157642Sps 933157642Sps case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ: 934157642Sps sc->bus_speed_mhz = 100; 935157642Sps break; 936157642Sps 937157642Sps case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ: 938157642Sps case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ: 939157642Sps sc->bus_speed_mhz = 66; 940157642Sps break; 941157642Sps 942157642Sps case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ: 943157642Sps case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ: 944157642Sps sc->bus_speed_mhz = 50; 945157642Sps break; 946157642Sps 947157642Sps case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW: 948157642Sps case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ: 949157642Sps case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ: 950157642Sps sc->bus_speed_mhz = 33; 951157642Sps break; 952157642Sps } 953157642Sps } else { 954157642Sps if (val & BCE_PCICFG_MISC_STATUS_M66EN) 955157642Sps sc->bus_speed_mhz = 66; 956157642Sps else 957157642Sps sc->bus_speed_mhz = 33; 958157642Sps } 959157642Sps 960157642Sps if (val & BCE_PCICFG_MISC_STATUS_32BIT_DET) 961157642Sps sc->bce_flags |= BCE_PCI_32BIT_FLAG; 962157642Sps 963171667Sdavidch /* Reset the controller and announce to bootcode that driver is present. */ 964157642Sps if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) { 965179771Sdavidch BCE_PRINTF("%s(%d): Controller reset failed!\n", 966170810Sdavidch __FILE__, __LINE__); 967157642Sps rc = ENXIO; 968157642Sps goto bce_attach_fail; 969157642Sps } 970157642Sps 971157642Sps /* Initialize the controller. */ 972157642Sps if (bce_chipinit(sc)) { 973169271Sdavidch BCE_PRINTF("%s(%d): Controller initialization failed!\n", 974170392Sdavidch __FILE__, __LINE__); 975157642Sps rc = ENXIO; 976157642Sps goto bce_attach_fail; 977157642Sps } 978157642Sps 979157642Sps /* Perform NVRAM test. */ 980157642Sps if (bce_nvram_test(sc)) { 981169271Sdavidch BCE_PRINTF("%s(%d): NVRAM test failed!\n", 982157642Sps __FILE__, __LINE__); 983157642Sps rc = ENXIO; 984157642Sps goto bce_attach_fail; 985157642Sps } 986157642Sps 987157642Sps /* Fetch the permanent Ethernet MAC address. */ 988157642Sps bce_get_mac_addr(sc); 989157642Sps 990157642Sps /* 991157642Sps * Trip points control how many BDs 992157642Sps * should be ready before generating an 993157642Sps * interrupt while ticks control how long 994157642Sps * a BD can sit in the chain before 995179771Sdavidch * generating an interrupt. Set the default 996170810Sdavidch * values for the RX and TX chains. 997157642Sps */ 998157642Sps 999170810Sdavidch#ifdef BCE_DEBUG 1000157642Sps /* Force more frequent interrupts. */ 1001157642Sps sc->bce_tx_quick_cons_trip_int = 1; 1002157642Sps sc->bce_tx_quick_cons_trip = 1; 1003157642Sps sc->bce_tx_ticks_int = 0; 1004157642Sps sc->bce_tx_ticks = 0; 1005157642Sps 1006157642Sps sc->bce_rx_quick_cons_trip_int = 1; 1007157642Sps sc->bce_rx_quick_cons_trip = 1; 1008157642Sps sc->bce_rx_ticks_int = 0; 1009157642Sps sc->bce_rx_ticks = 0; 1010157642Sps#else 1011170810Sdavidch /* Improve throughput at the expense of increased latency. */ 1012157642Sps sc->bce_tx_quick_cons_trip_int = 20; 1013157642Sps sc->bce_tx_quick_cons_trip = 20; 1014157642Sps sc->bce_tx_ticks_int = 80; 1015157642Sps sc->bce_tx_ticks = 80; 1016157642Sps 1017157642Sps sc->bce_rx_quick_cons_trip_int = 6; 1018157642Sps sc->bce_rx_quick_cons_trip = 6; 1019157642Sps sc->bce_rx_ticks_int = 18; 1020157642Sps sc->bce_rx_ticks = 18; 1021157642Sps#endif 1022157642Sps 1023157642Sps /* Update statistics once every second. */ 1024157642Sps sc->bce_stats_ticks = 1000000 & 0xffff00; 1025157642Sps 1026179771Sdavidch /* Find the media type for the adapter. */ 1027179771Sdavidch bce_get_media(sc); 1028157642Sps 1029170810Sdavidch /* Store data needed by PHY driver for backplane applications */ 1030194781Sdavidch sc->bce_shared_hw_cfg = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG); 1031194781Sdavidch sc->bce_port_hw_cfg = bce_shmem_rd(sc, BCE_PORT_HW_CFG_CONFIG); 1032170392Sdavidch 1033157642Sps /* Allocate DMA memory resources. */ 1034157642Sps if (bce_dma_alloc(dev)) { 1035169271Sdavidch BCE_PRINTF("%s(%d): DMA resource allocation failed!\n", 1036157642Sps __FILE__, __LINE__); 1037157642Sps rc = ENXIO; 1038157642Sps goto bce_attach_fail; 1039157642Sps } 1040157642Sps 1041157642Sps /* Allocate an ifnet structure. */ 1042157642Sps ifp = sc->bce_ifp = if_alloc(IFT_ETHER); 1043157642Sps if (ifp == NULL) { 1044179771Sdavidch BCE_PRINTF("%s(%d): Interface allocation failed!\n", 1045157642Sps __FILE__, __LINE__); 1046157642Sps rc = ENXIO; 1047157642Sps goto bce_attach_fail; 1048157642Sps } 1049157642Sps 1050157642Sps /* Initialize the ifnet interface. */ 1051157642Sps ifp->if_softc = sc; 1052157642Sps if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1053157642Sps ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1054157642Sps ifp->if_ioctl = bce_ioctl; 1055157642Sps ifp->if_start = bce_start; 1056157642Sps ifp->if_init = bce_init; 1057157642Sps ifp->if_mtu = ETHERMTU; 1058170392Sdavidch 1059170392Sdavidch if (bce_tso_enable) { 1060170392Sdavidch ifp->if_hwassist = BCE_IF_HWASSIST | CSUM_TSO; 1061204374Syongari ifp->if_capabilities = BCE_IF_CAPABILITIES | IFCAP_TSO4 | 1062204374Syongari IFCAP_VLAN_HWTSO; 1063170392Sdavidch } else { 1064170392Sdavidch ifp->if_hwassist = BCE_IF_HWASSIST; 1065170392Sdavidch ifp->if_capabilities = BCE_IF_CAPABILITIES; 1066170392Sdavidch } 1067169632Sdavidch 1068157642Sps ifp->if_capenable = ifp->if_capabilities; 1069157642Sps 1070182293Sdavidch /* 1071182293Sdavidch * Assume standard mbuf sizes for buffer allocation. 1072182293Sdavidch * This may change later if the MTU size is set to 1073182293Sdavidch * something other than 1500. 1074179771Sdavidch */ 1075198320Sstas#ifdef BCE_JUMBO_HDRSPLIT 1076176448Sdavidch sc->rx_bd_mbuf_alloc_size = MHLEN; 1077179771Sdavidch /* Make sure offset is 16 byte aligned for hardware. */ 1078179771Sdavidch sc->rx_bd_mbuf_align_pad = roundup2((MSIZE - MHLEN), 16) - 1079179695Sdavidch (MSIZE - MHLEN); 1080179771Sdavidch sc->rx_bd_mbuf_data_len = sc->rx_bd_mbuf_alloc_size - 1081179695Sdavidch sc->rx_bd_mbuf_align_pad; 1082179771Sdavidch sc->pg_bd_mbuf_alloc_size = MCLBYTES; 1083178853Sscottl#else 1084179436Sjhb sc->rx_bd_mbuf_alloc_size = MCLBYTES; 1085179695Sdavidch sc->rx_bd_mbuf_align_pad = roundup2(MCLBYTES, 16) - MCLBYTES; 1086179771Sdavidch sc->rx_bd_mbuf_data_len = sc->rx_bd_mbuf_alloc_size - 1087179695Sdavidch sc->rx_bd_mbuf_align_pad; 1088179771Sdavidch#endif 1089176448Sdavidch 1090157642Sps ifp->if_snd.ifq_drv_maxlen = USABLE_TX_BD; 1091170810Sdavidch IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 1092170810Sdavidch IFQ_SET_READY(&ifp->if_snd); 1093170810Sdavidch 1094157642Sps if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) 1095170392Sdavidch ifp->if_baudrate = IF_Mbps(2500ULL); 1096157642Sps else 1097170392Sdavidch ifp->if_baudrate = IF_Mbps(1000); 1098157642Sps 1099170810Sdavidch /* Check for an MII child bus by probing the PHY. */ 1100166261Sdwhite if (mii_phy_probe(dev, &sc->bce_miibus, bce_ifmedia_upd, 1101166261Sdwhite bce_ifmedia_sts)) { 1102179771Sdavidch BCE_PRINTF("%s(%d): No PHY found on child MII bus!\n", 1103157642Sps __FILE__, __LINE__); 1104166261Sdwhite rc = ENXIO; 1105157642Sps goto bce_attach_fail; 1106157642Sps } 1107157642Sps 1108157642Sps /* Attach to the Ethernet interface list. */ 1109157642Sps ether_ifattach(ifp, sc->eaddr); 1110157642Sps 1111157642Sps#if __FreeBSD_version < 500000 1112170810Sdavidch callout_init(&sc->bce_tick_callout); 1113170810Sdavidch callout_init(&sc->bce_pulse_callout); 1114157642Sps#else 1115170810Sdavidch callout_init_mtx(&sc->bce_tick_callout, &sc->bce_mtx, 0); 1116170810Sdavidch callout_init_mtx(&sc->bce_pulse_callout, &sc->bce_mtx, 0); 1117157642Sps#endif 1118157642Sps 1119157642Sps /* Hookup IRQ last. */ 1120179771Sdavidch rc = bus_setup_intr(dev, sc->bce_res_irq, INTR_TYPE_NET | INTR_MPSAFE, 1121179771Sdavidch NULL, bce_intr, sc, &sc->bce_intrhand); 1122157642Sps 1123157642Sps if (rc) { 1124179771Sdavidch BCE_PRINTF("%s(%d): Failed to setup IRQ!\n", 1125157642Sps __FILE__, __LINE__); 1126157642Sps bce_detach(dev); 1127157642Sps goto bce_attach_exit; 1128157642Sps } 1129157642Sps 1130179771Sdavidch /* 1131179771Sdavidch * At this point we've acquired all the resources 1132170810Sdavidch * we need to run so there's no turning back, we're 1133170810Sdavidch * cleared for launch. 1134170810Sdavidch */ 1135170810Sdavidch 1136157642Sps /* Print some important debugging info. */ 1137176448Sdavidch DBRUNMSG(BCE_INFO, bce_dump_driver_state(sc)); 1138157642Sps 1139157642Sps /* Add the supported sysctls to the kernel. */ 1140157642Sps bce_add_sysctls(sc); 1141157642Sps 1142170810Sdavidch BCE_LOCK(sc); 1143182293Sdavidch 1144179771Sdavidch /* 1145170810Sdavidch * The chip reset earlier notified the bootcode that 1146170810Sdavidch * a driver is present. We now need to start our pulse 1147170810Sdavidch * routine so that the bootcode is reminded that we're 1148170810Sdavidch * still running. 1149170810Sdavidch */ 1150170810Sdavidch bce_pulse(sc); 1151170810Sdavidch 1152162474Sambrisko bce_mgmt_init_locked(sc); 1153170392Sdavidch BCE_UNLOCK(sc); 1154162474Sambrisko 1155170810Sdavidch /* Finally, print some useful adapter info */ 1156179771Sdavidch bce_print_adapter_info(sc); 1157176448Sdavidch DBPRINT(sc, BCE_FATAL, "%s(): sc = %p\n", 1158176448Sdavidch __FUNCTION__, sc); 1159170810Sdavidch 1160157642Sps goto bce_attach_exit; 1161157642Sps 1162157642Spsbce_attach_fail: 1163157642Sps bce_release_resources(sc); 1164157642Sps 1165157642Spsbce_attach_exit: 1166157642Sps 1167179771Sdavidch DBEXIT(BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 1168157642Sps 1169157642Sps return(rc); 1170157642Sps} 1171157642Sps 1172157642Sps 1173157642Sps/****************************************************************************/ 1174157642Sps/* Device detach function. */ 1175157642Sps/* */ 1176157642Sps/* Stops the controller, resets the controller, and releases resources. */ 1177157642Sps/* */ 1178157642Sps/* Returns: */ 1179157642Sps/* 0 on success, positive value on failure. */ 1180157642Sps/****************************************************************************/ 1181157642Spsstatic int 1182157642Spsbce_detach(device_t dev) 1183157642Sps{ 1184170810Sdavidch struct bce_softc *sc = device_get_softc(dev); 1185157642Sps struct ifnet *ifp; 1186170810Sdavidch u32 msg; 1187157642Sps 1188179771Sdavidch DBENTER(BCE_VERBOSE_UNLOAD | BCE_VERBOSE_RESET); 1189157642Sps 1190157642Sps ifp = sc->bce_ifp; 1191157642Sps 1192176448Sdavidch /* Stop and reset the controller. */ 1193176448Sdavidch BCE_LOCK(sc); 1194176448Sdavidch 1195170810Sdavidch /* Stop the pulse so the bootcode can go to driver absent state. */ 1196170810Sdavidch callout_stop(&sc->bce_pulse_callout); 1197170810Sdavidch 1198157642Sps bce_stop(sc); 1199170810Sdavidch if (sc->bce_flags & BCE_NO_WOL_FLAG) 1200170810Sdavidch msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN; 1201170810Sdavidch else 1202170810Sdavidch msg = BCE_DRV_MSG_CODE_UNLOAD; 1203170810Sdavidch bce_reset(sc, msg); 1204176448Sdavidch 1205157642Sps BCE_UNLOCK(sc); 1206157642Sps 1207157642Sps ether_ifdetach(ifp); 1208157642Sps 1209157642Sps /* If we have a child device on the MII bus remove it too. */ 1210166261Sdwhite bus_generic_detach(dev); 1211166261Sdwhite device_delete_child(dev, sc->bce_miibus); 1212157642Sps 1213157642Sps /* Release all remaining resources. */ 1214157642Sps bce_release_resources(sc); 1215157642Sps 1216179771Sdavidch DBEXIT(BCE_VERBOSE_UNLOAD | BCE_VERBOSE_RESET); 1217157642Sps 1218157642Sps return(0); 1219157642Sps} 1220157642Sps 1221157642Sps 1222157642Sps/****************************************************************************/ 1223157642Sps/* Device shutdown function. */ 1224157642Sps/* */ 1225157642Sps/* Stops and resets the controller. */ 1226157642Sps/* */ 1227157642Sps/* Returns: */ 1228173839Syongari/* 0 on success, positive value on failure. */ 1229157642Sps/****************************************************************************/ 1230173839Syongaristatic int 1231157642Spsbce_shutdown(device_t dev) 1232157642Sps{ 1233157642Sps struct bce_softc *sc = device_get_softc(dev); 1234170810Sdavidch u32 msg; 1235157642Sps 1236179771Sdavidch DBENTER(BCE_VERBOSE); 1237170810Sdavidch 1238157642Sps BCE_LOCK(sc); 1239157642Sps bce_stop(sc); 1240170810Sdavidch if (sc->bce_flags & BCE_NO_WOL_FLAG) 1241170810Sdavidch msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN; 1242170810Sdavidch else 1243170810Sdavidch msg = BCE_DRV_MSG_CODE_UNLOAD; 1244170810Sdavidch bce_reset(sc, msg); 1245157642Sps BCE_UNLOCK(sc); 1246173839Syongari 1247179771Sdavidch DBEXIT(BCE_VERBOSE); 1248179771Sdavidch 1249173839Syongari return (0); 1250157642Sps} 1251157642Sps 1252157642Sps 1253179771Sdavidch#ifdef BCE_DEBUG 1254157642Sps/****************************************************************************/ 1255179771Sdavidch/* Register read. */ 1256179771Sdavidch/* */ 1257179771Sdavidch/* Returns: */ 1258179771Sdavidch/* The value of the register. */ 1259179771Sdavidch/****************************************************************************/ 1260179771Sdavidchstatic u32 1261179771Sdavidchbce_reg_rd(struct bce_softc *sc, u32 offset) 1262179771Sdavidch{ 1263179771Sdavidch u32 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, offset); 1264179771Sdavidch DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1265179771Sdavidch __FUNCTION__, offset, val); 1266179771Sdavidch return val; 1267179771Sdavidch} 1268179771Sdavidch 1269179771Sdavidch 1270179771Sdavidch/****************************************************************************/ 1271179771Sdavidch/* Register write (16 bit). */ 1272179771Sdavidch/* */ 1273179771Sdavidch/* Returns: */ 1274179771Sdavidch/* Nothing. */ 1275179771Sdavidch/****************************************************************************/ 1276179771Sdavidchstatic void 1277179771Sdavidchbce_reg_wr16(struct bce_softc *sc, u32 offset, u16 val) 1278179771Sdavidch{ 1279179771Sdavidch DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%04X\n", 1280179771Sdavidch __FUNCTION__, offset, val); 1281179771Sdavidch bus_space_write_2(sc->bce_btag, sc->bce_bhandle, offset, val); 1282179771Sdavidch} 1283179771Sdavidch 1284179771Sdavidch 1285179771Sdavidch/****************************************************************************/ 1286179771Sdavidch/* Register write. */ 1287179771Sdavidch/* */ 1288179771Sdavidch/* Returns: */ 1289179771Sdavidch/* Nothing. */ 1290179771Sdavidch/****************************************************************************/ 1291179771Sdavidchstatic void 1292179771Sdavidchbce_reg_wr(struct bce_softc *sc, u32 offset, u32 val) 1293179771Sdavidch{ 1294179771Sdavidch DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1295179771Sdavidch __FUNCTION__, offset, val); 1296179771Sdavidch bus_space_write_4(sc->bce_btag, sc->bce_bhandle, offset, val); 1297179771Sdavidch} 1298179771Sdavidch#endif 1299179771Sdavidch 1300179771Sdavidch/****************************************************************************/ 1301157642Sps/* Indirect register read. */ 1302157642Sps/* */ 1303157642Sps/* Reads NetXtreme II registers using an index/data register pair in PCI */ 1304157642Sps/* configuration space. Using this mechanism avoids issues with posted */ 1305157642Sps/* reads but is much slower than memory-mapped I/O. */ 1306157642Sps/* */ 1307157642Sps/* Returns: */ 1308157642Sps/* The value of the register. */ 1309157642Sps/****************************************************************************/ 1310157642Spsstatic u32 1311157642Spsbce_reg_rd_ind(struct bce_softc *sc, u32 offset) 1312157642Sps{ 1313157642Sps device_t dev; 1314157642Sps dev = sc->bce_dev; 1315157642Sps 1316157642Sps pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4); 1317157642Sps#ifdef BCE_DEBUG 1318157642Sps { 1319157642Sps u32 val; 1320157642Sps val = pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4); 1321179771Sdavidch DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1322157642Sps __FUNCTION__, offset, val); 1323157642Sps return val; 1324157642Sps } 1325157642Sps#else 1326157642Sps return pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4); 1327157642Sps#endif 1328157642Sps} 1329157642Sps 1330157642Sps 1331157642Sps/****************************************************************************/ 1332157642Sps/* Indirect register write. */ 1333157642Sps/* */ 1334157642Sps/* Writes NetXtreme II registers using an index/data register pair in PCI */ 1335157642Sps/* configuration space. Using this mechanism avoids issues with posted */ 1336157642Sps/* writes but is muchh slower than memory-mapped I/O. */ 1337157642Sps/* */ 1338157642Sps/* Returns: */ 1339157642Sps/* Nothing. */ 1340157642Sps/****************************************************************************/ 1341157642Spsstatic void 1342157642Spsbce_reg_wr_ind(struct bce_softc *sc, u32 offset, u32 val) 1343157642Sps{ 1344157642Sps device_t dev; 1345157642Sps dev = sc->bce_dev; 1346157642Sps 1347179771Sdavidch DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1348157642Sps __FUNCTION__, offset, val); 1349157642Sps 1350157642Sps pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4); 1351157642Sps pci_write_config(dev, BCE_PCICFG_REG_WINDOW, val, 4); 1352157642Sps} 1353157642Sps 1354178132Sdavidch 1355194781Sdavidch/****************************************************************************/ 1356194781Sdavidch/* Shared memory write. */ 1357194781Sdavidch/* */ 1358194781Sdavidch/* Writes NetXtreme II shared memory region. */ 1359194781Sdavidch/* */ 1360194781Sdavidch/* Returns: */ 1361194781Sdavidch/* Nothing. */ 1362194781Sdavidch/****************************************************************************/ 1363194781Sdavidchstatic void 1364194781Sdavidchbce_shmem_wr(struct bce_softc *sc, u32 offset, u32 val) 1365194781Sdavidch{ 1366194781Sdavidch bce_reg_wr_ind(sc, sc->bce_shmem_base + offset, val); 1367194781Sdavidch} 1368194781Sdavidch 1369194781Sdavidch 1370194781Sdavidch/****************************************************************************/ 1371194781Sdavidch/* Shared memory read. */ 1372194781Sdavidch/* */ 1373194781Sdavidch/* Reads NetXtreme II shared memory region. */ 1374194781Sdavidch/* */ 1375194781Sdavidch/* Returns: */ 1376194781Sdavidch/* The 32 bit value read. */ 1377194781Sdavidch/****************************************************************************/ 1378194781Sdavidchstatic u32 1379194781Sdavidchbce_shmem_rd(struct bce_softc *sc, u32 offset) 1380194781Sdavidch{ 1381194781Sdavidch return (bce_reg_rd_ind(sc, sc->bce_shmem_base + offset)); 1382194781Sdavidch} 1383194781Sdavidch 1384194781Sdavidch 1385176448Sdavidch#ifdef BCE_DEBUG 1386176448Sdavidch/****************************************************************************/ 1387176448Sdavidch/* Context memory read. */ 1388176448Sdavidch/* */ 1389176448Sdavidch/* The NetXtreme II controller uses context memory to track connection */ 1390176448Sdavidch/* information for L2 and higher network protocols. */ 1391176448Sdavidch/* */ 1392176448Sdavidch/* Returns: */ 1393176448Sdavidch/* The requested 32 bit value of context memory. */ 1394176448Sdavidch/****************************************************************************/ 1395176448Sdavidchstatic u32 1396179771Sdavidchbce_ctx_rd(struct bce_softc *sc, u32 cid_addr, u32 ctx_offset) 1397176448Sdavidch{ 1398179771Sdavidch u32 idx, offset, retry_cnt = 5, val; 1399157642Sps 1400179771Sdavidch DBRUNIF((cid_addr > MAX_CID_ADDR || ctx_offset & 0x3 || cid_addr & CTX_MASK), 1401179771Sdavidch BCE_PRINTF("%s(): Invalid CID address: 0x%08X.\n", 1402179771Sdavidch __FUNCTION__, cid_addr)); 1403176448Sdavidch 1404179771Sdavidch offset = ctx_offset + cid_addr; 1405176448Sdavidch 1406182293Sdavidch if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 1407182293Sdavidch (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 1408179771Sdavidch 1409179771Sdavidch REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_READ_REQ)); 1410179771Sdavidch 1411179771Sdavidch for (idx = 0; idx < retry_cnt; idx++) { 1412179771Sdavidch val = REG_RD(sc, BCE_CTX_CTX_CTRL); 1413179771Sdavidch if ((val & BCE_CTX_CTX_CTRL_READ_REQ) == 0) 1414179771Sdavidch break; 1415179771Sdavidch DELAY(5); 1416179771Sdavidch } 1417179771Sdavidch 1418179771Sdavidch if (val & BCE_CTX_CTX_CTRL_READ_REQ) 1419179771Sdavidch BCE_PRINTF("%s(%d); Unable to read CTX memory: " 1420179771Sdavidch "cid_addr = 0x%08X, offset = 0x%08X!\n", 1421179771Sdavidch __FILE__, __LINE__, cid_addr, ctx_offset); 1422179771Sdavidch 1423179771Sdavidch val = REG_RD(sc, BCE_CTX_CTX_DATA); 1424179771Sdavidch } else { 1425179771Sdavidch REG_WR(sc, BCE_CTX_DATA_ADR, offset); 1426179771Sdavidch val = REG_RD(sc, BCE_CTX_DATA); 1427179771Sdavidch } 1428179771Sdavidch 1429179771Sdavidch DBPRINT(sc, BCE_EXTREME_CTX, "%s(); cid_addr = 0x%08X, offset = 0x%08X, " 1430179771Sdavidch "val = 0x%08X\n", __FUNCTION__, cid_addr, ctx_offset, val); 1431179771Sdavidch 1432176448Sdavidch return(val); 1433176448Sdavidch} 1434176448Sdavidch#endif 1435176448Sdavidch 1436178132Sdavidch 1437157642Sps/****************************************************************************/ 1438157642Sps/* Context memory write. */ 1439157642Sps/* */ 1440157642Sps/* The NetXtreme II controller uses context memory to track connection */ 1441157642Sps/* information for L2 and higher network protocols. */ 1442157642Sps/* */ 1443157642Sps/* Returns: */ 1444157642Sps/* Nothing. */ 1445157642Sps/****************************************************************************/ 1446157642Spsstatic void 1447179771Sdavidchbce_ctx_wr(struct bce_softc *sc, u32 cid_addr, u32 ctx_offset, u32 ctx_val) 1448157642Sps{ 1449179771Sdavidch u32 idx, offset = ctx_offset + cid_addr; 1450179771Sdavidch u32 val, retry_cnt = 5; 1451157642Sps 1452179771Sdavidch DBPRINT(sc, BCE_EXTREME_CTX, "%s(); cid_addr = 0x%08X, offset = 0x%08X, " 1453179771Sdavidch "val = 0x%08X\n", __FUNCTION__, cid_addr, ctx_offset, ctx_val); 1454157642Sps 1455179771Sdavidch DBRUNIF((cid_addr > MAX_CID_ADDR || ctx_offset & 0x3 || cid_addr & CTX_MASK), 1456179771Sdavidch BCE_PRINTF("%s(): Invalid CID address: 0x%08X.\n", 1457179771Sdavidch __FUNCTION__, cid_addr)); 1458179771Sdavidch 1459182293Sdavidch if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 1460182293Sdavidch (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 1461179771Sdavidch 1462179771Sdavidch REG_WR(sc, BCE_CTX_CTX_DATA, ctx_val); 1463179771Sdavidch REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_WRITE_REQ)); 1464179771Sdavidch 1465179771Sdavidch for (idx = 0; idx < retry_cnt; idx++) { 1466179771Sdavidch val = REG_RD(sc, BCE_CTX_CTX_CTRL); 1467179771Sdavidch if ((val & BCE_CTX_CTX_CTRL_WRITE_REQ) == 0) 1468179771Sdavidch break; 1469179771Sdavidch DELAY(5); 1470179771Sdavidch } 1471179771Sdavidch 1472179771Sdavidch if (val & BCE_CTX_CTX_CTRL_WRITE_REQ) 1473179771Sdavidch BCE_PRINTF("%s(%d); Unable to write CTX memory: " 1474179771Sdavidch "cid_addr = 0x%08X, offset = 0x%08X!\n", 1475179771Sdavidch __FILE__, __LINE__, cid_addr, ctx_offset); 1476179771Sdavidch 1477179771Sdavidch } else { 1478179771Sdavidch REG_WR(sc, BCE_CTX_DATA_ADR, offset); 1479179771Sdavidch REG_WR(sc, BCE_CTX_DATA, ctx_val); 1480179771Sdavidch } 1481157642Sps} 1482157642Sps 1483157642Sps 1484157642Sps/****************************************************************************/ 1485157642Sps/* PHY register read. */ 1486157642Sps/* */ 1487157642Sps/* Implements register reads on the MII bus. */ 1488157642Sps/* */ 1489157642Sps/* Returns: */ 1490157642Sps/* The value of the register. */ 1491157642Sps/****************************************************************************/ 1492157642Spsstatic int 1493157642Spsbce_miibus_read_reg(device_t dev, int phy, int reg) 1494157642Sps{ 1495157642Sps struct bce_softc *sc; 1496157642Sps u32 val; 1497157642Sps int i; 1498157642Sps 1499157642Sps sc = device_get_softc(dev); 1500157642Sps 1501157642Sps /* Make sure we are accessing the correct PHY address. */ 1502157642Sps if (phy != sc->bce_phy_addr) { 1503179771Sdavidch DBPRINT(sc, BCE_INSANE_PHY, "Invalid PHY address %d for PHY read!\n", phy); 1504157642Sps return(0); 1505157642Sps } 1506157642Sps 1507157642Sps if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1508157642Sps val = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1509157642Sps val &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL; 1510157642Sps 1511157642Sps REG_WR(sc, BCE_EMAC_MDIO_MODE, val); 1512157642Sps REG_RD(sc, BCE_EMAC_MDIO_MODE); 1513157642Sps 1514157642Sps DELAY(40); 1515157642Sps } 1516157642Sps 1517179771Sdavidch 1518157642Sps val = BCE_MIPHY(phy) | BCE_MIREG(reg) | 1519157642Sps BCE_EMAC_MDIO_COMM_COMMAND_READ | BCE_EMAC_MDIO_COMM_DISEXT | 1520157642Sps BCE_EMAC_MDIO_COMM_START_BUSY; 1521157642Sps REG_WR(sc, BCE_EMAC_MDIO_COMM, val); 1522157642Sps 1523157642Sps for (i = 0; i < BCE_PHY_TIMEOUT; i++) { 1524157642Sps DELAY(10); 1525157642Sps 1526157642Sps val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1527157642Sps if (!(val & BCE_EMAC_MDIO_COMM_START_BUSY)) { 1528157642Sps DELAY(5); 1529157642Sps 1530157642Sps val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1531157642Sps val &= BCE_EMAC_MDIO_COMM_DATA; 1532157642Sps 1533157642Sps break; 1534157642Sps } 1535157642Sps } 1536157642Sps 1537157642Sps if (val & BCE_EMAC_MDIO_COMM_START_BUSY) { 1538169271Sdavidch BCE_PRINTF("%s(%d): Error: PHY read timeout! phy = %d, reg = 0x%04X\n", 1539157642Sps __FILE__, __LINE__, phy, reg); 1540157642Sps val = 0x0; 1541157642Sps } else { 1542157642Sps val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1543157642Sps } 1544157642Sps 1545157642Sps 1546157642Sps if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1547157642Sps val = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1548157642Sps val |= BCE_EMAC_MDIO_MODE_AUTO_POLL; 1549157642Sps 1550157642Sps REG_WR(sc, BCE_EMAC_MDIO_MODE, val); 1551157642Sps REG_RD(sc, BCE_EMAC_MDIO_MODE); 1552157642Sps 1553157642Sps DELAY(40); 1554157642Sps } 1555157642Sps 1556179771Sdavidch DB_PRINT_PHY_REG(reg, val); 1557157642Sps return (val & 0xffff); 1558157642Sps 1559157642Sps} 1560157642Sps 1561157642Sps 1562157642Sps/****************************************************************************/ 1563157642Sps/* PHY register write. */ 1564157642Sps/* */ 1565157642Sps/* Implements register writes on the MII bus. */ 1566157642Sps/* */ 1567157642Sps/* Returns: */ 1568157642Sps/* The value of the register. */ 1569157642Sps/****************************************************************************/ 1570157642Spsstatic int 1571157642Spsbce_miibus_write_reg(device_t dev, int phy, int reg, int val) 1572157642Sps{ 1573157642Sps struct bce_softc *sc; 1574157642Sps u32 val1; 1575157642Sps int i; 1576157642Sps 1577157642Sps sc = device_get_softc(dev); 1578157642Sps 1579157642Sps /* Make sure we are accessing the correct PHY address. */ 1580157642Sps if (phy != sc->bce_phy_addr) { 1581179771Sdavidch DBPRINT(sc, BCE_INSANE_PHY, "Invalid PHY address %d for PHY write!\n", phy); 1582157642Sps return(0); 1583157642Sps } 1584157642Sps 1585179771Sdavidch DB_PRINT_PHY_REG(reg, val); 1586157642Sps 1587157642Sps if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1588157642Sps val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1589157642Sps val1 &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL; 1590157642Sps 1591157642Sps REG_WR(sc, BCE_EMAC_MDIO_MODE, val1); 1592157642Sps REG_RD(sc, BCE_EMAC_MDIO_MODE); 1593157642Sps 1594157642Sps DELAY(40); 1595157642Sps } 1596157642Sps 1597157642Sps val1 = BCE_MIPHY(phy) | BCE_MIREG(reg) | val | 1598157642Sps BCE_EMAC_MDIO_COMM_COMMAND_WRITE | 1599157642Sps BCE_EMAC_MDIO_COMM_START_BUSY | BCE_EMAC_MDIO_COMM_DISEXT; 1600157642Sps REG_WR(sc, BCE_EMAC_MDIO_COMM, val1); 1601157642Sps 1602157642Sps for (i = 0; i < BCE_PHY_TIMEOUT; i++) { 1603157642Sps DELAY(10); 1604157642Sps 1605157642Sps val1 = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1606157642Sps if (!(val1 & BCE_EMAC_MDIO_COMM_START_BUSY)) { 1607157642Sps DELAY(5); 1608157642Sps break; 1609157642Sps } 1610157642Sps } 1611157642Sps 1612157642Sps if (val1 & BCE_EMAC_MDIO_COMM_START_BUSY) 1613179771Sdavidch BCE_PRINTF("%s(%d): PHY write timeout!\n", 1614157642Sps __FILE__, __LINE__); 1615157642Sps 1616157642Sps if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1617157642Sps val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1618157642Sps val1 |= BCE_EMAC_MDIO_MODE_AUTO_POLL; 1619157642Sps 1620157642Sps REG_WR(sc, BCE_EMAC_MDIO_MODE, val1); 1621157642Sps REG_RD(sc, BCE_EMAC_MDIO_MODE); 1622157642Sps 1623157642Sps DELAY(40); 1624157642Sps } 1625157642Sps 1626157642Sps return 0; 1627157642Sps} 1628157642Sps 1629157642Sps 1630157642Sps/****************************************************************************/ 1631157642Sps/* MII bus status change. */ 1632157642Sps/* */ 1633157642Sps/* Called by the MII bus driver when the PHY establishes link to set the */ 1634157642Sps/* MAC interface registers. */ 1635157642Sps/* */ 1636157642Sps/* Returns: */ 1637157642Sps/* Nothing. */ 1638157642Sps/****************************************************************************/ 1639157642Spsstatic void 1640157642Spsbce_miibus_statchg(device_t dev) 1641157642Sps{ 1642157642Sps struct bce_softc *sc; 1643157642Sps struct mii_data *mii; 1644170392Sdavidch int val; 1645157642Sps 1646157642Sps sc = device_get_softc(dev); 1647157642Sps 1648179771Sdavidch DBENTER(BCE_VERBOSE_PHY); 1649179771Sdavidch 1650157642Sps mii = device_get_softc(sc->bce_miibus); 1651157642Sps 1652170392Sdavidch val = REG_RD(sc, BCE_EMAC_MODE); 1653179771Sdavidch val &= ~(BCE_EMAC_MODE_PORT | BCE_EMAC_MODE_HALF_DUPLEX | 1654179771Sdavidch BCE_EMAC_MODE_MAC_LOOP | BCE_EMAC_MODE_FORCE_LINK | 1655170392Sdavidch BCE_EMAC_MODE_25G); 1656157642Sps 1657169632Sdavidch /* Set MII or GMII interface based on the speed negotiated by the PHY. */ 1658170392Sdavidch switch (IFM_SUBTYPE(mii->mii_media_active)) { 1659170392Sdavidch case IFM_10_T: 1660170392Sdavidch if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) { 1661170392Sdavidch DBPRINT(sc, BCE_INFO, "Enabling 10Mb interface.\n"); 1662170392Sdavidch val |= BCE_EMAC_MODE_PORT_MII_10; 1663170392Sdavidch break; 1664170392Sdavidch } 1665170392Sdavidch /* fall-through */ 1666170392Sdavidch case IFM_100_TX: 1667170392Sdavidch DBPRINT(sc, BCE_INFO, "Enabling MII interface.\n"); 1668170392Sdavidch val |= BCE_EMAC_MODE_PORT_MII; 1669170392Sdavidch break; 1670170392Sdavidch case IFM_2500_SX: 1671170392Sdavidch DBPRINT(sc, BCE_INFO, "Enabling 2.5G MAC mode.\n"); 1672170392Sdavidch val |= BCE_EMAC_MODE_25G; 1673170392Sdavidch /* fall-through */ 1674170392Sdavidch case IFM_1000_T: 1675170392Sdavidch case IFM_1000_SX: 1676170810Sdavidch DBPRINT(sc, BCE_INFO, "Enabling GMII interface.\n"); 1677170392Sdavidch val |= BCE_EMAC_MODE_PORT_GMII; 1678170392Sdavidch break; 1679170392Sdavidch default: 1680178132Sdavidch DBPRINT(sc, BCE_INFO, "Unknown speed, enabling default GMII " 1681176448Sdavidch "interface.\n"); 1682170392Sdavidch val |= BCE_EMAC_MODE_PORT_GMII; 1683157642Sps } 1684157642Sps 1685157642Sps /* Set half or full duplex based on the duplicity negotiated by the PHY. */ 1686170392Sdavidch if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) { 1687170392Sdavidch DBPRINT(sc, BCE_INFO, "Setting Half-Duplex interface.\n"); 1688170392Sdavidch val |= BCE_EMAC_MODE_HALF_DUPLEX; 1689170392Sdavidch } else 1690157642Sps DBPRINT(sc, BCE_INFO, "Setting Full-Duplex interface.\n"); 1691170392Sdavidch 1692170392Sdavidch REG_WR(sc, BCE_EMAC_MODE, val); 1693170392Sdavidch 1694170392Sdavidch#if 0 1695176448Sdavidch /* ToDo: Enable flow control support in brgphy and bge. */ 1696170392Sdavidch /* FLAG0 is set if RX is enabled and FLAG1 if TX is enabled */ 1697170392Sdavidch if (mii->mii_media_active & IFM_FLAG0) 1698170392Sdavidch BCE_SETBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_RX_MODE_FLOW_EN); 1699170392Sdavidch if (mii->mii_media_active & IFM_FLAG1) 1700170392Sdavidch BCE_SETBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_TX_MODE_FLOW_EN); 1701170392Sdavidch#endif 1702170392Sdavidch 1703179771Sdavidch DBEXIT(BCE_VERBOSE_PHY); 1704157642Sps} 1705157642Sps 1706157642Sps 1707157642Sps/****************************************************************************/ 1708157642Sps/* Acquire NVRAM lock. */ 1709157642Sps/* */ 1710157642Sps/* Before the NVRAM can be accessed the caller must acquire an NVRAM lock. */ 1711157642Sps/* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 1712157642Sps/* for use by the driver. */ 1713157642Sps/* */ 1714157642Sps/* Returns: */ 1715157642Sps/* 0 on success, positive value on failure. */ 1716157642Sps/****************************************************************************/ 1717157642Spsstatic int 1718157642Spsbce_acquire_nvram_lock(struct bce_softc *sc) 1719157642Sps{ 1720157642Sps u32 val; 1721179771Sdavidch int j, rc = 0; 1722157642Sps 1723179771Sdavidch DBENTER(BCE_VERBOSE_NVRAM); 1724157642Sps 1725157642Sps /* Request access to the flash interface. */ 1726157642Sps REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2); 1727157642Sps for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1728157642Sps val = REG_RD(sc, BCE_NVM_SW_ARB); 1729157642Sps if (val & BCE_NVM_SW_ARB_ARB_ARB2) 1730157642Sps break; 1731157642Sps 1732157642Sps DELAY(5); 1733157642Sps } 1734157642Sps 1735157642Sps if (j >= NVRAM_TIMEOUT_COUNT) { 1736157642Sps DBPRINT(sc, BCE_WARN, "Timeout acquiring NVRAM lock!\n"); 1737179771Sdavidch rc = EBUSY; 1738157642Sps } 1739157642Sps 1740179771Sdavidch DBEXIT(BCE_VERBOSE_NVRAM); 1741179771Sdavidch return (rc); 1742157642Sps} 1743157642Sps 1744157642Sps 1745157642Sps/****************************************************************************/ 1746157642Sps/* Release NVRAM lock. */ 1747157642Sps/* */ 1748157642Sps/* When the caller is finished accessing NVRAM the lock must be released. */ 1749157642Sps/* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 1750157642Sps/* for use by the driver. */ 1751157642Sps/* */ 1752157642Sps/* Returns: */ 1753157642Sps/* 0 on success, positive value on failure. */ 1754157642Sps/****************************************************************************/ 1755157642Spsstatic int 1756157642Spsbce_release_nvram_lock(struct bce_softc *sc) 1757157642Sps{ 1758157642Sps u32 val; 1759179771Sdavidch int j, rc = 0; 1760157642Sps 1761179771Sdavidch DBENTER(BCE_VERBOSE_NVRAM); 1762157642Sps 1763157642Sps /* 1764157642Sps * Relinquish nvram interface. 1765157642Sps */ 1766157642Sps REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2); 1767157642Sps 1768157642Sps for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1769157642Sps val = REG_RD(sc, BCE_NVM_SW_ARB); 1770157642Sps if (!(val & BCE_NVM_SW_ARB_ARB_ARB2)) 1771157642Sps break; 1772157642Sps 1773157642Sps DELAY(5); 1774157642Sps } 1775157642Sps 1776157642Sps if (j >= NVRAM_TIMEOUT_COUNT) { 1777179771Sdavidch DBPRINT(sc, BCE_WARN, "Timeout releasing NVRAM lock!\n"); 1778179771Sdavidch rc = EBUSY; 1779157642Sps } 1780157642Sps 1781179771Sdavidch DBEXIT(BCE_VERBOSE_NVRAM); 1782179771Sdavidch return (rc); 1783157642Sps} 1784157642Sps 1785157642Sps 1786157642Sps#ifdef BCE_NVRAM_WRITE_SUPPORT 1787157642Sps/****************************************************************************/ 1788157642Sps/* Enable NVRAM write access. */ 1789157642Sps/* */ 1790157642Sps/* Before writing to NVRAM the caller must enable NVRAM writes. */ 1791157642Sps/* */ 1792157642Sps/* Returns: */ 1793157642Sps/* 0 on success, positive value on failure. */ 1794157642Sps/****************************************************************************/ 1795157642Spsstatic int 1796157642Spsbce_enable_nvram_write(struct bce_softc *sc) 1797157642Sps{ 1798157642Sps u32 val; 1799179771Sdavidch int rc = 0; 1800157642Sps 1801179771Sdavidch DBENTER(BCE_VERBOSE_NVRAM); 1802157642Sps 1803157642Sps val = REG_RD(sc, BCE_MISC_CFG); 1804157642Sps REG_WR(sc, BCE_MISC_CFG, val | BCE_MISC_CFG_NVM_WR_EN_PCI); 1805157642Sps 1806179771Sdavidch if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 1807157642Sps int j; 1808157642Sps 1809157642Sps REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 1810157642Sps REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_WREN | BCE_NVM_COMMAND_DOIT); 1811157642Sps 1812157642Sps for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1813157642Sps DELAY(5); 1814157642Sps 1815157642Sps val = REG_RD(sc, BCE_NVM_COMMAND); 1816157642Sps if (val & BCE_NVM_COMMAND_DONE) 1817157642Sps break; 1818157642Sps } 1819157642Sps 1820157642Sps if (j >= NVRAM_TIMEOUT_COUNT) { 1821157642Sps DBPRINT(sc, BCE_WARN, "Timeout writing NVRAM!\n"); 1822179771Sdavidch rc = EBUSY; 1823157642Sps } 1824157642Sps } 1825179771Sdavidch 1826179771Sdavidch DBENTER(BCE_VERBOSE_NVRAM); 1827179771Sdavidch return (rc); 1828157642Sps} 1829157642Sps 1830157642Sps 1831157642Sps/****************************************************************************/ 1832157642Sps/* Disable NVRAM write access. */ 1833157642Sps/* */ 1834157642Sps/* When the caller is finished writing to NVRAM write access must be */ 1835157642Sps/* disabled. */ 1836157642Sps/* */ 1837157642Sps/* Returns: */ 1838157642Sps/* Nothing. */ 1839157642Sps/****************************************************************************/ 1840157642Spsstatic void 1841157642Spsbce_disable_nvram_write(struct bce_softc *sc) 1842157642Sps{ 1843157642Sps u32 val; 1844157642Sps 1845179771Sdavidch DBENTER(BCE_VERBOSE_NVRAM); 1846157642Sps 1847157642Sps val = REG_RD(sc, BCE_MISC_CFG); 1848157642Sps REG_WR(sc, BCE_MISC_CFG, val & ~BCE_MISC_CFG_NVM_WR_EN); 1849179771Sdavidch 1850179771Sdavidch DBEXIT(BCE_VERBOSE_NVRAM); 1851179771Sdavidch 1852157642Sps} 1853157642Sps#endif 1854157642Sps 1855157642Sps 1856157642Sps/****************************************************************************/ 1857157642Sps/* Enable NVRAM access. */ 1858157642Sps/* */ 1859157642Sps/* Before accessing NVRAM for read or write operations the caller must */ 1860157642Sps/* enabled NVRAM access. */ 1861157642Sps/* */ 1862157642Sps/* Returns: */ 1863157642Sps/* Nothing. */ 1864157642Sps/****************************************************************************/ 1865157642Spsstatic void 1866157642Spsbce_enable_nvram_access(struct bce_softc *sc) 1867157642Sps{ 1868157642Sps u32 val; 1869157642Sps 1870179771Sdavidch DBENTER(BCE_VERBOSE_NVRAM); 1871157642Sps 1872157642Sps val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE); 1873157642Sps /* Enable both bits, even on read. */ 1874157642Sps REG_WR(sc, BCE_NVM_ACCESS_ENABLE, 1875157642Sps val | BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN); 1876179771Sdavidch 1877179771Sdavidch DBEXIT(BCE_VERBOSE_NVRAM); 1878157642Sps} 1879157642Sps 1880157642Sps 1881157642Sps/****************************************************************************/ 1882157642Sps/* Disable NVRAM access. */ 1883157642Sps/* */ 1884157642Sps/* When the caller is finished accessing NVRAM access must be disabled. */ 1885157642Sps/* */ 1886157642Sps/* Returns: */ 1887157642Sps/* Nothing. */ 1888157642Sps/****************************************************************************/ 1889157642Spsstatic void 1890157642Spsbce_disable_nvram_access(struct bce_softc *sc) 1891157642Sps{ 1892157642Sps u32 val; 1893157642Sps 1894179771Sdavidch DBENTER(BCE_VERBOSE_NVRAM); 1895157642Sps 1896157642Sps val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE); 1897157642Sps 1898157642Sps /* Disable both bits, even after read. */ 1899157642Sps REG_WR(sc, BCE_NVM_ACCESS_ENABLE, 1900157642Sps val & ~(BCE_NVM_ACCESS_ENABLE_EN | 1901157642Sps BCE_NVM_ACCESS_ENABLE_WR_EN)); 1902179771Sdavidch 1903179771Sdavidch DBEXIT(BCE_VERBOSE_NVRAM); 1904157642Sps} 1905157642Sps 1906157642Sps 1907157642Sps#ifdef BCE_NVRAM_WRITE_SUPPORT 1908157642Sps/****************************************************************************/ 1909157642Sps/* Erase NVRAM page before writing. */ 1910157642Sps/* */ 1911157642Sps/* Non-buffered flash parts require that a page be erased before it is */ 1912157642Sps/* written. */ 1913157642Sps/* */ 1914157642Sps/* Returns: */ 1915157642Sps/* 0 on success, positive value on failure. */ 1916157642Sps/****************************************************************************/ 1917157642Spsstatic int 1918157642Spsbce_nvram_erase_page(struct bce_softc *sc, u32 offset) 1919157642Sps{ 1920157642Sps u32 cmd; 1921179771Sdavidch int j, rc = 0; 1922157642Sps 1923179771Sdavidch DBENTER(BCE_VERBOSE_NVRAM); 1924179771Sdavidch 1925157642Sps /* Buffered flash doesn't require an erase. */ 1926179771Sdavidch if (sc->bce_flash_info->flags & BCE_NV_BUFFERED) 1927179771Sdavidch goto bce_nvram_erase_page_exit; 1928157642Sps 1929157642Sps /* Build an erase command. */ 1930157642Sps cmd = BCE_NVM_COMMAND_ERASE | BCE_NVM_COMMAND_WR | 1931157642Sps BCE_NVM_COMMAND_DOIT; 1932157642Sps 1933157642Sps /* 1934157642Sps * Clear the DONE bit separately, set the NVRAM adress to erase, 1935157642Sps * and issue the erase command. 1936157642Sps */ 1937157642Sps REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 1938157642Sps REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 1939157642Sps REG_WR(sc, BCE_NVM_COMMAND, cmd); 1940157642Sps 1941157642Sps /* Wait for completion. */ 1942157642Sps for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1943157642Sps u32 val; 1944157642Sps 1945157642Sps DELAY(5); 1946157642Sps 1947157642Sps val = REG_RD(sc, BCE_NVM_COMMAND); 1948157642Sps if (val & BCE_NVM_COMMAND_DONE) 1949157642Sps break; 1950157642Sps } 1951157642Sps 1952157642Sps if (j >= NVRAM_TIMEOUT_COUNT) { 1953157642Sps DBPRINT(sc, BCE_WARN, "Timeout erasing NVRAM.\n"); 1954179771Sdavidch rc = EBUSY; 1955157642Sps } 1956157642Sps 1957179771Sdavidchbce_nvram_erase_page_exit: 1958179771Sdavidch DBEXIT(BCE_VERBOSE_NVRAM); 1959179771Sdavidch return (rc); 1960157642Sps} 1961157642Sps#endif /* BCE_NVRAM_WRITE_SUPPORT */ 1962157642Sps 1963157642Sps 1964157642Sps/****************************************************************************/ 1965157642Sps/* Read a dword (32 bits) from NVRAM. */ 1966157642Sps/* */ 1967157642Sps/* Read a 32 bit word from NVRAM. The caller is assumed to have already */ 1968157642Sps/* obtained the NVRAM lock and enabled the controller for NVRAM access. */ 1969157642Sps/* */ 1970157642Sps/* Returns: */ 1971157642Sps/* 0 on success and the 32 bit value read, positive value on failure. */ 1972157642Sps/****************************************************************************/ 1973157642Spsstatic int 1974157642Spsbce_nvram_read_dword(struct bce_softc *sc, u32 offset, u8 *ret_val, 1975157642Sps u32 cmd_flags) 1976157642Sps{ 1977157642Sps u32 cmd; 1978157642Sps int i, rc = 0; 1979157642Sps 1980179771Sdavidch DBENTER(BCE_EXTREME_NVRAM); 1981179771Sdavidch 1982157642Sps /* Build the command word. */ 1983157642Sps cmd = BCE_NVM_COMMAND_DOIT | cmd_flags; 1984157642Sps 1985179771Sdavidch /* Calculate the offset for buffered flash if translation is used. */ 1986179771Sdavidch if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) { 1987157642Sps offset = ((offset / sc->bce_flash_info->page_size) << 1988157642Sps sc->bce_flash_info->page_bits) + 1989157642Sps (offset % sc->bce_flash_info->page_size); 1990157642Sps } 1991157642Sps 1992157642Sps /* 1993157642Sps * Clear the DONE bit separately, set the address to read, 1994157642Sps * and issue the read. 1995157642Sps */ 1996157642Sps REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 1997157642Sps REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 1998157642Sps REG_WR(sc, BCE_NVM_COMMAND, cmd); 1999157642Sps 2000157642Sps /* Wait for completion. */ 2001157642Sps for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) { 2002157642Sps u32 val; 2003157642Sps 2004157642Sps DELAY(5); 2005157642Sps 2006157642Sps val = REG_RD(sc, BCE_NVM_COMMAND); 2007157642Sps if (val & BCE_NVM_COMMAND_DONE) { 2008157642Sps val = REG_RD(sc, BCE_NVM_READ); 2009157642Sps 2010157642Sps val = bce_be32toh(val); 2011157642Sps memcpy(ret_val, &val, 4); 2012157642Sps break; 2013157642Sps } 2014157642Sps } 2015157642Sps 2016157642Sps /* Check for errors. */ 2017157642Sps if (i >= NVRAM_TIMEOUT_COUNT) { 2018169271Sdavidch BCE_PRINTF("%s(%d): Timeout error reading NVRAM at offset 0x%08X!\n", 2019157642Sps __FILE__, __LINE__, offset); 2020157642Sps rc = EBUSY; 2021157642Sps } 2022157642Sps 2023179771Sdavidch DBEXIT(BCE_EXTREME_NVRAM); 2024157642Sps return(rc); 2025157642Sps} 2026157642Sps 2027157642Sps 2028157642Sps#ifdef BCE_NVRAM_WRITE_SUPPORT 2029157642Sps/****************************************************************************/ 2030157642Sps/* Write a dword (32 bits) to NVRAM. */ 2031157642Sps/* */ 2032157642Sps/* Write a 32 bit word to NVRAM. The caller is assumed to have already */ 2033157642Sps/* obtained the NVRAM lock, enabled the controller for NVRAM access, and */ 2034157642Sps/* enabled NVRAM write access. */ 2035157642Sps/* */ 2036157642Sps/* Returns: */ 2037157642Sps/* 0 on success, positive value on failure. */ 2038157642Sps/****************************************************************************/ 2039157642Spsstatic int 2040157642Spsbce_nvram_write_dword(struct bce_softc *sc, u32 offset, u8 *val, 2041157642Sps u32 cmd_flags) 2042157642Sps{ 2043157642Sps u32 cmd, val32; 2044179771Sdavidch int j, rc = 0; 2045157642Sps 2046179771Sdavidch DBENTER(BCE_VERBOSE_NVRAM); 2047179771Sdavidch 2048157642Sps /* Build the command word. */ 2049157642Sps cmd = BCE_NVM_COMMAND_DOIT | BCE_NVM_COMMAND_WR | cmd_flags; 2050157642Sps 2051179771Sdavidch /* Calculate the offset for buffered flash if translation is used. */ 2052179771Sdavidch if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) { 2053157642Sps offset = ((offset / sc->bce_flash_info->page_size) << 2054157642Sps sc->bce_flash_info->page_bits) + 2055157642Sps (offset % sc->bce_flash_info->page_size); 2056157642Sps } 2057157642Sps 2058157642Sps /* 2059157642Sps * Clear the DONE bit separately, convert NVRAM data to big-endian, 2060157642Sps * set the NVRAM address to write, and issue the write command 2061157642Sps */ 2062157642Sps REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 2063157642Sps memcpy(&val32, val, 4); 2064157642Sps val32 = htobe32(val32); 2065157642Sps REG_WR(sc, BCE_NVM_WRITE, val32); 2066157642Sps REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 2067157642Sps REG_WR(sc, BCE_NVM_COMMAND, cmd); 2068157642Sps 2069157642Sps /* Wait for completion. */ 2070157642Sps for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2071157642Sps DELAY(5); 2072157642Sps 2073157642Sps if (REG_RD(sc, BCE_NVM_COMMAND) & BCE_NVM_COMMAND_DONE) 2074157642Sps break; 2075157642Sps } 2076157642Sps if (j >= NVRAM_TIMEOUT_COUNT) { 2077169271Sdavidch BCE_PRINTF("%s(%d): Timeout error writing NVRAM at offset 0x%08X\n", 2078157642Sps __FILE__, __LINE__, offset); 2079179771Sdavidch rc = EBUSY; 2080157642Sps } 2081157642Sps 2082179771Sdavidch DBEXIT(BCE_VERBOSE_NVRAM); 2083179771Sdavidch return (rc); 2084157642Sps} 2085157642Sps#endif /* BCE_NVRAM_WRITE_SUPPORT */ 2086157642Sps 2087157642Sps 2088157642Sps/****************************************************************************/ 2089157642Sps/* Initialize NVRAM access. */ 2090157642Sps/* */ 2091157642Sps/* Identify the NVRAM device in use and prepare the NVRAM interface to */ 2092157642Sps/* access that device. */ 2093157642Sps/* */ 2094157642Sps/* Returns: */ 2095157642Sps/* 0 on success, positive value on failure. */ 2096157642Sps/****************************************************************************/ 2097157642Spsstatic int 2098157642Spsbce_init_nvram(struct bce_softc *sc) 2099157642Sps{ 2100157642Sps u32 val; 2101179771Sdavidch int j, entry_count, rc = 0; 2102157642Sps struct flash_spec *flash; 2103157642Sps 2104179771Sdavidch DBENTER(BCE_VERBOSE_NVRAM); 2105157642Sps 2106182293Sdavidch if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 2107182293Sdavidch (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 2108179771Sdavidch sc->bce_flash_info = &flash_5709; 2109179771Sdavidch goto bce_init_nvram_get_flash_size; 2110179771Sdavidch } 2111179771Sdavidch 2112157642Sps /* Determine the selected interface. */ 2113157642Sps val = REG_RD(sc, BCE_NVM_CFG1); 2114157642Sps 2115157642Sps entry_count = sizeof(flash_table) / sizeof(struct flash_spec); 2116157642Sps 2117157642Sps /* 2118157642Sps * Flash reconfiguration is required to support additional 2119157642Sps * NVRAM devices not directly supported in hardware. 2120157642Sps * Check if the flash interface was reconfigured 2121157642Sps * by the bootcode. 2122157642Sps */ 2123157642Sps 2124157642Sps if (val & 0x40000000) { 2125157642Sps /* Flash interface reconfigured by bootcode. */ 2126157642Sps 2127179771Sdavidch DBPRINT(sc,BCE_INFO_LOAD, 2128157642Sps "bce_init_nvram(): Flash WAS reconfigured.\n"); 2129157642Sps 2130157642Sps for (j = 0, flash = &flash_table[0]; j < entry_count; 2131157642Sps j++, flash++) { 2132157642Sps if ((val & FLASH_BACKUP_STRAP_MASK) == 2133157642Sps (flash->config1 & FLASH_BACKUP_STRAP_MASK)) { 2134157642Sps sc->bce_flash_info = flash; 2135157642Sps break; 2136157642Sps } 2137157642Sps } 2138157642Sps } else { 2139157642Sps /* Flash interface not yet reconfigured. */ 2140157642Sps u32 mask; 2141157642Sps 2142179771Sdavidch DBPRINT(sc, BCE_INFO_LOAD, "%s(): Flash was NOT reconfigured.\n", 2143179771Sdavidch __FUNCTION__); 2144157642Sps 2145157642Sps if (val & (1 << 23)) 2146157642Sps mask = FLASH_BACKUP_STRAP_MASK; 2147157642Sps else 2148157642Sps mask = FLASH_STRAP_MASK; 2149157642Sps 2150157642Sps /* Look for the matching NVRAM device configuration data. */ 2151157642Sps for (j = 0, flash = &flash_table[0]; j < entry_count; j++, flash++) { 2152157642Sps 2153157642Sps /* Check if the device matches any of the known devices. */ 2154157642Sps if ((val & mask) == (flash->strapping & mask)) { 2155157642Sps /* Found a device match. */ 2156157642Sps sc->bce_flash_info = flash; 2157157642Sps 2158157642Sps /* Request access to the flash interface. */ 2159157642Sps if ((rc = bce_acquire_nvram_lock(sc)) != 0) 2160157642Sps return rc; 2161157642Sps 2162157642Sps /* Reconfigure the flash interface. */ 2163157642Sps bce_enable_nvram_access(sc); 2164157642Sps REG_WR(sc, BCE_NVM_CFG1, flash->config1); 2165157642Sps REG_WR(sc, BCE_NVM_CFG2, flash->config2); 2166157642Sps REG_WR(sc, BCE_NVM_CFG3, flash->config3); 2167157642Sps REG_WR(sc, BCE_NVM_WRITE1, flash->write1); 2168157642Sps bce_disable_nvram_access(sc); 2169157642Sps bce_release_nvram_lock(sc); 2170157642Sps 2171157642Sps break; 2172157642Sps } 2173157642Sps } 2174157642Sps } 2175157642Sps 2176157642Sps /* Check if a matching device was found. */ 2177157642Sps if (j == entry_count) { 2178157642Sps sc->bce_flash_info = NULL; 2179179771Sdavidch BCE_PRINTF("%s(%d): Unknown Flash NVRAM found!\n", 2180157642Sps __FILE__, __LINE__); 2181157642Sps rc = ENODEV; 2182157642Sps } 2183157642Sps 2184179771Sdavidchbce_init_nvram_get_flash_size: 2185157642Sps /* Write the flash config data to the shared memory interface. */ 2186194781Sdavidch val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG2); 2187157642Sps val &= BCE_SHARED_HW_CFG2_NVM_SIZE_MASK; 2188157642Sps if (val) 2189157642Sps sc->bce_flash_size = val; 2190157642Sps else 2191157642Sps sc->bce_flash_size = sc->bce_flash_info->total_size; 2192157642Sps 2193179771Sdavidch DBPRINT(sc, BCE_INFO_LOAD, "%s(): Found %s, size = 0x%08X\n", 2194179771Sdavidch __FUNCTION__, sc->bce_flash_info->name, 2195157642Sps sc->bce_flash_info->total_size); 2196157642Sps 2197179771Sdavidch DBEXIT(BCE_VERBOSE_NVRAM); 2198157642Sps return rc; 2199157642Sps} 2200157642Sps 2201157642Sps 2202157642Sps/****************************************************************************/ 2203157642Sps/* Read an arbitrary range of data from NVRAM. */ 2204157642Sps/* */ 2205157642Sps/* Prepares the NVRAM interface for access and reads the requested data */ 2206157642Sps/* into the supplied buffer. */ 2207157642Sps/* */ 2208157642Sps/* Returns: */ 2209157642Sps/* 0 on success and the data read, positive value on failure. */ 2210157642Sps/****************************************************************************/ 2211157642Spsstatic int 2212157642Spsbce_nvram_read(struct bce_softc *sc, u32 offset, u8 *ret_buf, 2213157642Sps int buf_size) 2214157642Sps{ 2215157642Sps int rc = 0; 2216157642Sps u32 cmd_flags, offset32, len32, extra; 2217157642Sps 2218179771Sdavidch DBENTER(BCE_VERBOSE_NVRAM); 2219179771Sdavidch 2220157642Sps if (buf_size == 0) 2221179771Sdavidch goto bce_nvram_read_exit; 2222157642Sps 2223157642Sps /* Request access to the flash interface. */ 2224157642Sps if ((rc = bce_acquire_nvram_lock(sc)) != 0) 2225179771Sdavidch goto bce_nvram_read_exit; 2226157642Sps 2227157642Sps /* Enable access to flash interface */ 2228157642Sps bce_enable_nvram_access(sc); 2229157642Sps 2230157642Sps len32 = buf_size; 2231157642Sps offset32 = offset; 2232157642Sps extra = 0; 2233157642Sps 2234157642Sps cmd_flags = 0; 2235157642Sps 2236157642Sps if (offset32 & 3) { 2237157642Sps u8 buf[4]; 2238157642Sps u32 pre_len; 2239157642Sps 2240157642Sps offset32 &= ~3; 2241157642Sps pre_len = 4 - (offset & 3); 2242157642Sps 2243157642Sps if (pre_len >= len32) { 2244157642Sps pre_len = len32; 2245157642Sps cmd_flags = BCE_NVM_COMMAND_FIRST | BCE_NVM_COMMAND_LAST; 2246157642Sps } 2247157642Sps else { 2248157642Sps cmd_flags = BCE_NVM_COMMAND_FIRST; 2249157642Sps } 2250157642Sps 2251157642Sps rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 2252157642Sps 2253157642Sps if (rc) 2254157642Sps return rc; 2255157642Sps 2256157642Sps memcpy(ret_buf, buf + (offset & 3), pre_len); 2257157642Sps 2258157642Sps offset32 += 4; 2259157642Sps ret_buf += pre_len; 2260157642Sps len32 -= pre_len; 2261157642Sps } 2262157642Sps 2263157642Sps if (len32 & 3) { 2264157642Sps extra = 4 - (len32 & 3); 2265157642Sps len32 = (len32 + 4) & ~3; 2266157642Sps } 2267157642Sps 2268157642Sps if (len32 == 4) { 2269157642Sps u8 buf[4]; 2270157642Sps 2271157642Sps if (cmd_flags) 2272157642Sps cmd_flags = BCE_NVM_COMMAND_LAST; 2273157642Sps else 2274157642Sps cmd_flags = BCE_NVM_COMMAND_FIRST | 2275157642Sps BCE_NVM_COMMAND_LAST; 2276157642Sps 2277157642Sps rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 2278157642Sps 2279157642Sps memcpy(ret_buf, buf, 4 - extra); 2280157642Sps } 2281157642Sps else if (len32 > 0) { 2282157642Sps u8 buf[4]; 2283157642Sps 2284157642Sps /* Read the first word. */ 2285157642Sps if (cmd_flags) 2286157642Sps cmd_flags = 0; 2287157642Sps else 2288157642Sps cmd_flags = BCE_NVM_COMMAND_FIRST; 2289157642Sps 2290157642Sps rc = bce_nvram_read_dword(sc, offset32, ret_buf, cmd_flags); 2291157642Sps 2292157642Sps /* Advance to the next dword. */ 2293157642Sps offset32 += 4; 2294157642Sps ret_buf += 4; 2295157642Sps len32 -= 4; 2296157642Sps 2297157642Sps while (len32 > 4 && rc == 0) { 2298157642Sps rc = bce_nvram_read_dword(sc, offset32, ret_buf, 0); 2299157642Sps 2300157642Sps /* Advance to the next dword. */ 2301157642Sps offset32 += 4; 2302157642Sps ret_buf += 4; 2303157642Sps len32 -= 4; 2304157642Sps } 2305157642Sps 2306157642Sps if (rc) 2307179771Sdavidch goto bce_nvram_read_locked_exit; 2308157642Sps 2309157642Sps cmd_flags = BCE_NVM_COMMAND_LAST; 2310157642Sps rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 2311157642Sps 2312157642Sps memcpy(ret_buf, buf, 4 - extra); 2313157642Sps } 2314157642Sps 2315179771Sdavidchbce_nvram_read_locked_exit: 2316157642Sps /* Disable access to flash interface and release the lock. */ 2317157642Sps bce_disable_nvram_access(sc); 2318157642Sps bce_release_nvram_lock(sc); 2319157642Sps 2320179771Sdavidchbce_nvram_read_exit: 2321179771Sdavidch DBEXIT(BCE_VERBOSE_NVRAM); 2322157642Sps return rc; 2323157642Sps} 2324157642Sps 2325157642Sps 2326157642Sps#ifdef BCE_NVRAM_WRITE_SUPPORT 2327157642Sps/****************************************************************************/ 2328157642Sps/* Write an arbitrary range of data from NVRAM. */ 2329157642Sps/* */ 2330157642Sps/* Prepares the NVRAM interface for write access and writes the requested */ 2331157642Sps/* data from the supplied buffer. The caller is responsible for */ 2332157642Sps/* calculating any appropriate CRCs. */ 2333157642Sps/* */ 2334157642Sps/* Returns: */ 2335157642Sps/* 0 on success, positive value on failure. */ 2336157642Sps/****************************************************************************/ 2337157642Spsstatic int 2338157642Spsbce_nvram_write(struct bce_softc *sc, u32 offset, u8 *data_buf, 2339157642Sps int buf_size) 2340157642Sps{ 2341157642Sps u32 written, offset32, len32; 2342157642Sps u8 *buf, start[4], end[4]; 2343157642Sps int rc = 0; 2344157642Sps int align_start, align_end; 2345157642Sps 2346179771Sdavidch DBENTER(BCE_VERBOSE_NVRAM); 2347179771Sdavidch 2348157642Sps buf = data_buf; 2349157642Sps offset32 = offset; 2350157642Sps len32 = buf_size; 2351157642Sps align_start = align_end = 0; 2352157642Sps 2353157642Sps if ((align_start = (offset32 & 3))) { 2354157642Sps offset32 &= ~3; 2355157642Sps len32 += align_start; 2356157642Sps if ((rc = bce_nvram_read(sc, offset32, start, 4))) 2357179771Sdavidch goto bce_nvram_write_exit; 2358157642Sps } 2359157642Sps 2360157642Sps if (len32 & 3) { 2361157642Sps if ((len32 > 4) || !align_start) { 2362157642Sps align_end = 4 - (len32 & 3); 2363157642Sps len32 += align_end; 2364157642Sps if ((rc = bce_nvram_read(sc, offset32 + len32 - 4, 2365157642Sps end, 4))) { 2366179771Sdavidch goto bce_nvram_write_exit; 2367157642Sps } 2368157642Sps } 2369157642Sps } 2370157642Sps 2371157642Sps if (align_start || align_end) { 2372157642Sps buf = malloc(len32, M_DEVBUF, M_NOWAIT); 2373179771Sdavidch if (buf == 0) { 2374179771Sdavidch rc = ENOMEM; 2375179771Sdavidch goto bce_nvram_write_exit; 2376179771Sdavidch } 2377179771Sdavidch 2378157642Sps if (align_start) { 2379157642Sps memcpy(buf, start, 4); 2380157642Sps } 2381179771Sdavidch 2382157642Sps if (align_end) { 2383157642Sps memcpy(buf + len32 - 4, end, 4); 2384157642Sps } 2385157642Sps memcpy(buf + align_start, data_buf, buf_size); 2386157642Sps } 2387157642Sps 2388157642Sps written = 0; 2389157642Sps while ((written < len32) && (rc == 0)) { 2390157642Sps u32 page_start, page_end, data_start, data_end; 2391157642Sps u32 addr, cmd_flags; 2392157642Sps int i; 2393157642Sps u8 flash_buffer[264]; 2394157642Sps 2395157642Sps /* Find the page_start addr */ 2396157642Sps page_start = offset32 + written; 2397157642Sps page_start -= (page_start % sc->bce_flash_info->page_size); 2398157642Sps /* Find the page_end addr */ 2399157642Sps page_end = page_start + sc->bce_flash_info->page_size; 2400157642Sps /* Find the data_start addr */ 2401157642Sps data_start = (written == 0) ? offset32 : page_start; 2402157642Sps /* Find the data_end addr */ 2403157642Sps data_end = (page_end > offset32 + len32) ? 2404157642Sps (offset32 + len32) : page_end; 2405157642Sps 2406157642Sps /* Request access to the flash interface. */ 2407157642Sps if ((rc = bce_acquire_nvram_lock(sc)) != 0) 2408179771Sdavidch goto bce_nvram_write_exit; 2409157642Sps 2410157642Sps /* Enable access to flash interface */ 2411157642Sps bce_enable_nvram_access(sc); 2412157642Sps 2413157642Sps cmd_flags = BCE_NVM_COMMAND_FIRST; 2414179771Sdavidch if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2415157642Sps int j; 2416157642Sps 2417157642Sps /* Read the whole page into the buffer 2418157642Sps * (non-buffer flash only) */ 2419157642Sps for (j = 0; j < sc->bce_flash_info->page_size; j += 4) { 2420157642Sps if (j == (sc->bce_flash_info->page_size - 4)) { 2421157642Sps cmd_flags |= BCE_NVM_COMMAND_LAST; 2422157642Sps } 2423157642Sps rc = bce_nvram_read_dword(sc, 2424157642Sps page_start + j, 2425157642Sps &flash_buffer[j], 2426157642Sps cmd_flags); 2427157642Sps 2428157642Sps if (rc) 2429179771Sdavidch goto bce_nvram_write_locked_exit; 2430157642Sps 2431157642Sps cmd_flags = 0; 2432157642Sps } 2433157642Sps } 2434157642Sps 2435157642Sps /* Enable writes to flash interface (unlock write-protect) */ 2436157642Sps if ((rc = bce_enable_nvram_write(sc)) != 0) 2437179771Sdavidch goto bce_nvram_write_locked_exit; 2438157642Sps 2439157642Sps /* Erase the page */ 2440157642Sps if ((rc = bce_nvram_erase_page(sc, page_start)) != 0) 2441179771Sdavidch goto bce_nvram_write_locked_exit; 2442157642Sps 2443157642Sps /* Re-enable the write again for the actual write */ 2444157642Sps bce_enable_nvram_write(sc); 2445157642Sps 2446157642Sps /* Loop to write back the buffer data from page_start to 2447157642Sps * data_start */ 2448157642Sps i = 0; 2449179771Sdavidch if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2450157642Sps for (addr = page_start; addr < data_start; 2451157642Sps addr += 4, i += 4) { 2452157642Sps 2453157642Sps rc = bce_nvram_write_dword(sc, addr, 2454157642Sps &flash_buffer[i], cmd_flags); 2455157642Sps 2456157642Sps if (rc != 0) 2457179771Sdavidch goto bce_nvram_write_locked_exit; 2458157642Sps 2459157642Sps cmd_flags = 0; 2460157642Sps } 2461157642Sps } 2462157642Sps 2463157642Sps /* Loop to write the new data from data_start to data_end */ 2464157642Sps for (addr = data_start; addr < data_end; addr += 4, i++) { 2465157642Sps if ((addr == page_end - 4) || 2466179771Sdavidch ((sc->bce_flash_info->flags & BCE_NV_BUFFERED) && 2467179771Sdavidch (addr == data_end - 4))) { 2468157642Sps 2469157642Sps cmd_flags |= BCE_NVM_COMMAND_LAST; 2470157642Sps } 2471157642Sps rc = bce_nvram_write_dword(sc, addr, buf, 2472157642Sps cmd_flags); 2473157642Sps 2474157642Sps if (rc != 0) 2475179771Sdavidch goto bce_nvram_write_locked_exit; 2476157642Sps 2477157642Sps cmd_flags = 0; 2478157642Sps buf += 4; 2479157642Sps } 2480157642Sps 2481157642Sps /* Loop to write back the buffer data from data_end 2482157642Sps * to page_end */ 2483179771Sdavidch if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2484157642Sps for (addr = data_end; addr < page_end; 2485157642Sps addr += 4, i += 4) { 2486157642Sps 2487157642Sps if (addr == page_end-4) { 2488157642Sps cmd_flags = BCE_NVM_COMMAND_LAST; 2489157642Sps } 2490157642Sps rc = bce_nvram_write_dword(sc, addr, 2491157642Sps &flash_buffer[i], cmd_flags); 2492157642Sps 2493157642Sps if (rc != 0) 2494179771Sdavidch goto bce_nvram_write_locked_exit; 2495157642Sps 2496157642Sps cmd_flags = 0; 2497157642Sps } 2498157642Sps } 2499157642Sps 2500157642Sps /* Disable writes to flash interface (lock write-protect) */ 2501157642Sps bce_disable_nvram_write(sc); 2502157642Sps 2503157642Sps /* Disable access to flash interface */ 2504157642Sps bce_disable_nvram_access(sc); 2505157642Sps bce_release_nvram_lock(sc); 2506157642Sps 2507157642Sps /* Increment written */ 2508157642Sps written += data_end - data_start; 2509157642Sps } 2510157642Sps 2511179771Sdavidch goto bce_nvram_write_exit; 2512179771Sdavidch 2513179771Sdavidchbce_nvram_write_locked_exit: 2514179771Sdavidch bce_disable_nvram_write(sc); 2515179771Sdavidch bce_disable_nvram_access(sc); 2516179771Sdavidch bce_release_nvram_lock(sc); 2517179771Sdavidch 2518179771Sdavidchbce_nvram_write_exit: 2519157642Sps if (align_start || align_end) 2520157642Sps free(buf, M_DEVBUF); 2521157642Sps 2522179771Sdavidch DBEXIT(BCE_VERBOSE_NVRAM); 2523179771Sdavidch return (rc); 2524157642Sps} 2525157642Sps#endif /* BCE_NVRAM_WRITE_SUPPORT */ 2526157642Sps 2527157642Sps 2528157642Sps/****************************************************************************/ 2529157642Sps/* Verifies that NVRAM is accessible and contains valid data. */ 2530157642Sps/* */ 2531157642Sps/* Reads the configuration data from NVRAM and verifies that the CRC is */ 2532157642Sps/* correct. */ 2533157642Sps/* */ 2534157642Sps/* Returns: */ 2535157642Sps/* 0 on success, positive value on failure. */ 2536157642Sps/****************************************************************************/ 2537157642Spsstatic int 2538157642Spsbce_nvram_test(struct bce_softc *sc) 2539157642Sps{ 2540157642Sps u32 buf[BCE_NVRAM_SIZE / 4]; 2541157642Sps u8 *data = (u8 *) buf; 2542157642Sps int rc = 0; 2543157642Sps u32 magic, csum; 2544157642Sps 2545179771Sdavidch DBENTER(BCE_VERBOSE_NVRAM | BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 2546157642Sps 2547157642Sps /* 2548157642Sps * Check that the device NVRAM is valid by reading 2549157642Sps * the magic value at offset 0. 2550157642Sps */ 2551179771Sdavidch if ((rc = bce_nvram_read(sc, 0, data, 4)) != 0) { 2552179771Sdavidch BCE_PRINTF("%s(%d): Unable to read NVRAM!\n", __FILE__, __LINE__); 2553179771Sdavidch goto bce_nvram_test_exit; 2554179771Sdavidch } 2555157642Sps 2556179771Sdavidch /* 2557179771Sdavidch * Verify that offset 0 of the NVRAM contains 2558179771Sdavidch * a valid magic number. 2559179771Sdavidch */ 2560157642Sps magic = bce_be32toh(buf[0]); 2561157642Sps if (magic != BCE_NVRAM_MAGIC) { 2562157642Sps rc = ENODEV; 2563169271Sdavidch BCE_PRINTF("%s(%d): Invalid NVRAM magic value! Expected: 0x%08X, " 2564157642Sps "Found: 0x%08X\n", 2565157642Sps __FILE__, __LINE__, BCE_NVRAM_MAGIC, magic); 2566179771Sdavidch goto bce_nvram_test_exit; 2567157642Sps } 2568157642Sps 2569157642Sps /* 2570157642Sps * Verify that the device NVRAM includes valid 2571157642Sps * configuration data. 2572157642Sps */ 2573179771Sdavidch if ((rc = bce_nvram_read(sc, 0x100, data, BCE_NVRAM_SIZE)) != 0) { 2574179771Sdavidch BCE_PRINTF("%s(%d): Unable to read Manufacturing Information from " 2575179771Sdavidch "NVRAM!\n", __FILE__, __LINE__); 2576179771Sdavidch goto bce_nvram_test_exit; 2577179771Sdavidch } 2578157642Sps 2579157642Sps csum = ether_crc32_le(data, 0x100); 2580157642Sps if (csum != BCE_CRC32_RESIDUAL) { 2581157642Sps rc = ENODEV; 2582169271Sdavidch BCE_PRINTF("%s(%d): Invalid Manufacturing Information NVRAM CRC! " 2583157642Sps "Expected: 0x%08X, Found: 0x%08X\n", 2584157642Sps __FILE__, __LINE__, BCE_CRC32_RESIDUAL, csum); 2585179771Sdavidch goto bce_nvram_test_exit; 2586157642Sps } 2587157642Sps 2588157642Sps csum = ether_crc32_le(data + 0x100, 0x100); 2589157642Sps if (csum != BCE_CRC32_RESIDUAL) { 2590179771Sdavidch rc = ENODEV; 2591169271Sdavidch BCE_PRINTF("%s(%d): Invalid Feature Configuration Information " 2592157642Sps "NVRAM CRC! Expected: 0x%08X, Found: 08%08X\n", 2593157642Sps __FILE__, __LINE__, BCE_CRC32_RESIDUAL, csum); 2594157642Sps } 2595157642Sps 2596179771Sdavidchbce_nvram_test_exit: 2597179771Sdavidch DBEXIT(BCE_VERBOSE_NVRAM | BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 2598157642Sps return rc; 2599157642Sps} 2600157642Sps 2601157642Sps 2602157642Sps/****************************************************************************/ 2603179771Sdavidch/* Identifies the current media type of the controller and sets the PHY */ 2604179771Sdavidch/* address. */ 2605179771Sdavidch/* */ 2606179771Sdavidch/* Returns: */ 2607179771Sdavidch/* Nothing. */ 2608179771Sdavidch/****************************************************************************/ 2609179771Sdavidchstatic void 2610179771Sdavidchbce_get_media(struct bce_softc *sc) 2611179771Sdavidch{ 2612179771Sdavidch u32 val; 2613179771Sdavidch 2614179771Sdavidch DBENTER(BCE_VERBOSE); 2615179771Sdavidch 2616182293Sdavidch /* Assume PHY address for copper controllers. */ 2617179771Sdavidch sc->bce_phy_addr = 1; 2618179771Sdavidch 2619179771Sdavidch if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 2620179771Sdavidch u32 val = REG_RD(sc, BCE_MISC_DUAL_MEDIA_CTRL); 2621179771Sdavidch u32 bond_id = val & BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID; 2622179771Sdavidch u32 strap; 2623179771Sdavidch 2624179771Sdavidch /* 2625179771Sdavidch * The BCM5709S is software configurable 2626179771Sdavidch * for Copper or SerDes operation. 2627179771Sdavidch */ 2628179771Sdavidch if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) { 2629179771Sdavidch DBPRINT(sc, BCE_INFO_LOAD, "5709 bonded for copper.\n"); 2630179771Sdavidch goto bce_get_media_exit; 2631179771Sdavidch } else if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) { 2632179771Sdavidch DBPRINT(sc, BCE_INFO_LOAD, "5709 bonded for dual media.\n"); 2633179771Sdavidch sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 2634179771Sdavidch goto bce_get_media_exit; 2635179771Sdavidch } 2636179771Sdavidch 2637179771Sdavidch if (val & BCE_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE) 2638179771Sdavidch strap = (val & BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21; 2639179771Sdavidch else 2640179771Sdavidch strap = (val & BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8; 2641179771Sdavidch 2642179771Sdavidch if (pci_get_function(sc->bce_dev) == 0) { 2643179771Sdavidch switch (strap) { 2644179771Sdavidch case 0x4: 2645179771Sdavidch case 0x5: 2646179771Sdavidch case 0x6: 2647182293Sdavidch DBPRINT(sc, BCE_INFO_LOAD, 2648179771Sdavidch "BCM5709 s/w configured for SerDes.\n"); 2649179771Sdavidch sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 2650179771Sdavidch default: 2651182293Sdavidch DBPRINT(sc, BCE_INFO_LOAD, 2652179771Sdavidch "BCM5709 s/w configured for Copper.\n"); 2653179771Sdavidch } 2654179771Sdavidch } else { 2655179771Sdavidch switch (strap) { 2656179771Sdavidch case 0x1: 2657179771Sdavidch case 0x2: 2658179771Sdavidch case 0x4: 2659182293Sdavidch DBPRINT(sc, BCE_INFO_LOAD, 2660179771Sdavidch "BCM5709 s/w configured for SerDes.\n"); 2661179771Sdavidch sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 2662179771Sdavidch default: 2663182293Sdavidch DBPRINT(sc, BCE_INFO_LOAD, 2664179771Sdavidch "BCM5709 s/w configured for Copper.\n"); 2665179771Sdavidch } 2666179771Sdavidch } 2667179771Sdavidch 2668179771Sdavidch } else if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT) 2669179771Sdavidch sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 2670179771Sdavidch 2671185082Sdelphij if (sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) { 2672179771Sdavidch sc->bce_flags |= BCE_NO_WOL_FLAG; 2673179771Sdavidch if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) { 2674179771Sdavidch sc->bce_phy_addr = 2; 2675194781Sdavidch val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG); 2676179771Sdavidch if (val & BCE_SHARED_HW_CFG_PHY_2_5G) { 2677179771Sdavidch sc->bce_phy_flags |= BCE_PHY_2_5G_CAPABLE_FLAG; 2678179771Sdavidch DBPRINT(sc, BCE_INFO_LOAD, "Found 2.5Gb capable adapter\n"); 2679179771Sdavidch } 2680179771Sdavidch } 2681179771Sdavidch } else if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) || 2682179771Sdavidch (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)) 2683179771Sdavidch sc->bce_phy_flags |= BCE_PHY_CRC_FIX_FLAG; 2684179771Sdavidch 2685179771Sdavidchbce_get_media_exit: 2686182293Sdavidch DBPRINT(sc, (BCE_INFO_LOAD | BCE_INFO_PHY), 2687179771Sdavidch "Using PHY address %d.\n", sc->bce_phy_addr); 2688182293Sdavidch 2689179771Sdavidch DBEXIT(BCE_VERBOSE); 2690179771Sdavidch} 2691179771Sdavidch 2692179771Sdavidch 2693179771Sdavidch/****************************************************************************/ 2694157642Sps/* Free any DMA memory owned by the driver. */ 2695157642Sps/* */ 2696157642Sps/* Scans through each data structre that requires DMA memory and frees */ 2697157642Sps/* the memory if allocated. */ 2698157642Sps/* */ 2699157642Sps/* Returns: */ 2700157642Sps/* Nothing. */ 2701157642Sps/****************************************************************************/ 2702157642Spsstatic void 2703157642Spsbce_dma_free(struct bce_softc *sc) 2704157642Sps{ 2705157642Sps int i; 2706157642Sps 2707179771Sdavidch DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_UNLOAD | BCE_VERBOSE_CTX); 2708157642Sps 2709179771Sdavidch /* Free, unmap, and destroy the status block. */ 2710176448Sdavidch if (sc->status_block != NULL) { 2711157642Sps bus_dmamem_free( 2712157642Sps sc->status_tag, 2713157642Sps sc->status_block, 2714157642Sps sc->status_map); 2715176448Sdavidch sc->status_block = NULL; 2716176448Sdavidch } 2717157642Sps 2718157642Sps if (sc->status_map != NULL) { 2719157642Sps bus_dmamap_unload( 2720157642Sps sc->status_tag, 2721157642Sps sc->status_map); 2722157642Sps bus_dmamap_destroy(sc->status_tag, 2723157642Sps sc->status_map); 2724176448Sdavidch sc->status_map = NULL; 2725157642Sps } 2726157642Sps 2727176448Sdavidch if (sc->status_tag != NULL) { 2728157642Sps bus_dma_tag_destroy(sc->status_tag); 2729176448Sdavidch sc->status_tag = NULL; 2730176448Sdavidch } 2731157642Sps 2732157642Sps 2733179771Sdavidch /* Free, unmap, and destroy the statistics block. */ 2734176448Sdavidch if (sc->stats_block != NULL) { 2735157642Sps bus_dmamem_free( 2736157642Sps sc->stats_tag, 2737157642Sps sc->stats_block, 2738157642Sps sc->stats_map); 2739176448Sdavidch sc->stats_block = NULL; 2740176448Sdavidch } 2741157642Sps 2742157642Sps if (sc->stats_map != NULL) { 2743157642Sps bus_dmamap_unload( 2744157642Sps sc->stats_tag, 2745157642Sps sc->stats_map); 2746157642Sps bus_dmamap_destroy(sc->stats_tag, 2747157642Sps sc->stats_map); 2748176448Sdavidch sc->stats_map = NULL; 2749157642Sps } 2750157642Sps 2751176448Sdavidch if (sc->stats_tag != NULL) { 2752157642Sps bus_dma_tag_destroy(sc->stats_tag); 2753176448Sdavidch sc->stats_tag = NULL; 2754176448Sdavidch } 2755157642Sps 2756157642Sps 2757179771Sdavidch /* Free, unmap and destroy all context memory pages. */ 2758182293Sdavidch if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 2759182293Sdavidch (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 2760179771Sdavidch for (i = 0; i < sc->ctx_pages; i++ ) { 2761179771Sdavidch if (sc->ctx_block[i] != NULL) { 2762179771Sdavidch bus_dmamem_free( 2763179771Sdavidch sc->ctx_tag, 2764179771Sdavidch sc->ctx_block[i], 2765179771Sdavidch sc->ctx_map[i]); 2766179771Sdavidch sc->ctx_block[i] = NULL; 2767179771Sdavidch } 2768179771Sdavidch 2769179771Sdavidch if (sc->ctx_map[i] != NULL) { 2770179771Sdavidch bus_dmamap_unload( 2771179771Sdavidch sc->ctx_tag, 2772179771Sdavidch sc->ctx_map[i]); 2773179771Sdavidch bus_dmamap_destroy( 2774179771Sdavidch sc->ctx_tag, 2775179771Sdavidch sc->ctx_map[i]); 2776179771Sdavidch sc->ctx_map[i] = NULL; 2777179771Sdavidch } 2778179771Sdavidch } 2779179771Sdavidch 2780179771Sdavidch /* Destroy the context memory tag. */ 2781179771Sdavidch if (sc->ctx_tag != NULL) { 2782179771Sdavidch bus_dma_tag_destroy(sc->ctx_tag); 2783179771Sdavidch sc->ctx_tag = NULL; 2784179771Sdavidch } 2785179771Sdavidch } 2786179771Sdavidch 2787179771Sdavidch 2788157642Sps /* Free, unmap and destroy all TX buffer descriptor chain pages. */ 2789157642Sps for (i = 0; i < TX_PAGES; i++ ) { 2790176448Sdavidch if (sc->tx_bd_chain[i] != NULL) { 2791157642Sps bus_dmamem_free( 2792157642Sps sc->tx_bd_chain_tag, 2793157642Sps sc->tx_bd_chain[i], 2794157642Sps sc->tx_bd_chain_map[i]); 2795176448Sdavidch sc->tx_bd_chain[i] = NULL; 2796176448Sdavidch } 2797157642Sps 2798157642Sps if (sc->tx_bd_chain_map[i] != NULL) { 2799157642Sps bus_dmamap_unload( 2800157642Sps sc->tx_bd_chain_tag, 2801157642Sps sc->tx_bd_chain_map[i]); 2802157642Sps bus_dmamap_destroy( 2803157642Sps sc->tx_bd_chain_tag, 2804157642Sps sc->tx_bd_chain_map[i]); 2805176448Sdavidch sc->tx_bd_chain_map[i] = NULL; 2806157642Sps } 2807157642Sps } 2808157642Sps 2809157642Sps /* Destroy the TX buffer descriptor tag. */ 2810176448Sdavidch if (sc->tx_bd_chain_tag != NULL) { 2811157642Sps bus_dma_tag_destroy(sc->tx_bd_chain_tag); 2812176448Sdavidch sc->tx_bd_chain_tag = NULL; 2813176448Sdavidch } 2814157642Sps 2815157642Sps 2816157642Sps /* Free, unmap and destroy all RX buffer descriptor chain pages. */ 2817157642Sps for (i = 0; i < RX_PAGES; i++ ) { 2818176448Sdavidch if (sc->rx_bd_chain[i] != NULL) { 2819157642Sps bus_dmamem_free( 2820157642Sps sc->rx_bd_chain_tag, 2821157642Sps sc->rx_bd_chain[i], 2822157642Sps sc->rx_bd_chain_map[i]); 2823176448Sdavidch sc->rx_bd_chain[i] = NULL; 2824176448Sdavidch } 2825157642Sps 2826157642Sps if (sc->rx_bd_chain_map[i] != NULL) { 2827157642Sps bus_dmamap_unload( 2828157642Sps sc->rx_bd_chain_tag, 2829157642Sps sc->rx_bd_chain_map[i]); 2830157642Sps bus_dmamap_destroy( 2831157642Sps sc->rx_bd_chain_tag, 2832157642Sps sc->rx_bd_chain_map[i]); 2833176448Sdavidch sc->rx_bd_chain_map[i] = NULL; 2834157642Sps } 2835157642Sps } 2836157642Sps 2837157642Sps /* Destroy the RX buffer descriptor tag. */ 2838176448Sdavidch if (sc->rx_bd_chain_tag != NULL) { 2839157642Sps bus_dma_tag_destroy(sc->rx_bd_chain_tag); 2840176448Sdavidch sc->rx_bd_chain_tag = NULL; 2841176448Sdavidch } 2842157642Sps 2843157642Sps 2844198320Sstas#ifdef BCE_JUMBO_HDRSPLIT 2845176448Sdavidch /* Free, unmap and destroy all page buffer descriptor chain pages. */ 2846176448Sdavidch for (i = 0; i < PG_PAGES; i++ ) { 2847176448Sdavidch if (sc->pg_bd_chain[i] != NULL) { 2848176448Sdavidch bus_dmamem_free( 2849176448Sdavidch sc->pg_bd_chain_tag, 2850176448Sdavidch sc->pg_bd_chain[i], 2851176448Sdavidch sc->pg_bd_chain_map[i]); 2852176448Sdavidch sc->pg_bd_chain[i] = NULL; 2853176448Sdavidch } 2854176448Sdavidch 2855176448Sdavidch if (sc->pg_bd_chain_map[i] != NULL) { 2856176448Sdavidch bus_dmamap_unload( 2857176448Sdavidch sc->pg_bd_chain_tag, 2858176448Sdavidch sc->pg_bd_chain_map[i]); 2859176448Sdavidch bus_dmamap_destroy( 2860176448Sdavidch sc->pg_bd_chain_tag, 2861176448Sdavidch sc->pg_bd_chain_map[i]); 2862176448Sdavidch sc->pg_bd_chain_map[i] = NULL; 2863176448Sdavidch } 2864176448Sdavidch } 2865176448Sdavidch 2866176448Sdavidch /* Destroy the page buffer descriptor tag. */ 2867176448Sdavidch if (sc->pg_bd_chain_tag != NULL) { 2868176448Sdavidch bus_dma_tag_destroy(sc->pg_bd_chain_tag); 2869176448Sdavidch sc->pg_bd_chain_tag = NULL; 2870176448Sdavidch } 2871179771Sdavidch#endif 2872176448Sdavidch 2873176448Sdavidch 2874157642Sps /* Unload and destroy the TX mbuf maps. */ 2875157642Sps for (i = 0; i < TOTAL_TX_BD; i++) { 2876157642Sps if (sc->tx_mbuf_map[i] != NULL) { 2877179771Sdavidch bus_dmamap_unload(sc->tx_mbuf_tag, 2878157642Sps sc->tx_mbuf_map[i]); 2879179771Sdavidch bus_dmamap_destroy(sc->tx_mbuf_tag, 2880157642Sps sc->tx_mbuf_map[i]); 2881176448Sdavidch sc->tx_mbuf_map[i] = NULL; 2882157642Sps } 2883157642Sps } 2884157642Sps 2885157642Sps /* Destroy the TX mbuf tag. */ 2886176448Sdavidch if (sc->tx_mbuf_tag != NULL) { 2887157642Sps bus_dma_tag_destroy(sc->tx_mbuf_tag); 2888176448Sdavidch sc->tx_mbuf_tag = NULL; 2889176448Sdavidch } 2890157642Sps 2891157642Sps /* Unload and destroy the RX mbuf maps. */ 2892157642Sps for (i = 0; i < TOTAL_RX_BD; i++) { 2893157642Sps if (sc->rx_mbuf_map[i] != NULL) { 2894179771Sdavidch bus_dmamap_unload(sc->rx_mbuf_tag, 2895157642Sps sc->rx_mbuf_map[i]); 2896179771Sdavidch bus_dmamap_destroy(sc->rx_mbuf_tag, 2897157642Sps sc->rx_mbuf_map[i]); 2898176448Sdavidch sc->rx_mbuf_map[i] = NULL; 2899157642Sps } 2900157642Sps } 2901157642Sps 2902157642Sps /* Destroy the RX mbuf tag. */ 2903176448Sdavidch if (sc->rx_mbuf_tag != NULL) { 2904157642Sps bus_dma_tag_destroy(sc->rx_mbuf_tag); 2905176448Sdavidch sc->rx_mbuf_tag = NULL; 2906176448Sdavidch } 2907157642Sps 2908198320Sstas#ifdef BCE_JUMBO_HDRSPLIT 2909176448Sdavidch /* Unload and destroy the page mbuf maps. */ 2910176448Sdavidch for (i = 0; i < TOTAL_PG_BD; i++) { 2911176448Sdavidch if (sc->pg_mbuf_map[i] != NULL) { 2912179771Sdavidch bus_dmamap_unload(sc->pg_mbuf_tag, 2913176448Sdavidch sc->pg_mbuf_map[i]); 2914179771Sdavidch bus_dmamap_destroy(sc->pg_mbuf_tag, 2915176448Sdavidch sc->pg_mbuf_map[i]); 2916176448Sdavidch sc->pg_mbuf_map[i] = NULL; 2917176448Sdavidch } 2918176448Sdavidch } 2919157642Sps 2920176448Sdavidch /* Destroy the page mbuf tag. */ 2921176448Sdavidch if (sc->pg_mbuf_tag != NULL) { 2922176448Sdavidch bus_dma_tag_destroy(sc->pg_mbuf_tag); 2923176448Sdavidch sc->pg_mbuf_tag = NULL; 2924176448Sdavidch } 2925179771Sdavidch#endif 2926176448Sdavidch 2927157642Sps /* Destroy the parent tag */ 2928176448Sdavidch if (sc->parent_tag != NULL) { 2929157642Sps bus_dma_tag_destroy(sc->parent_tag); 2930176448Sdavidch sc->parent_tag = NULL; 2931176448Sdavidch } 2932157642Sps 2933179771Sdavidch DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_UNLOAD | BCE_VERBOSE_CTX); 2934157642Sps} 2935157642Sps 2936157642Sps 2937157642Sps/****************************************************************************/ 2938157642Sps/* Get DMA memory from the OS. */ 2939157642Sps/* */ 2940157642Sps/* Validates that the OS has provided DMA buffers in response to a */ 2941157642Sps/* bus_dmamap_load() call and saves the physical address of those buffers. */ 2942157642Sps/* When the callback is used the OS will return 0 for the mapping function */ 2943157642Sps/* (bus_dmamap_load()) so we use the value of map_arg->maxsegs to pass any */ 2944157642Sps/* failures back to the caller. */ 2945157642Sps/* */ 2946157642Sps/* Returns: */ 2947157642Sps/* Nothing. */ 2948157642Sps/****************************************************************************/ 2949157642Spsstatic void 2950157642Spsbce_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2951157642Sps{ 2952163393Sscottl bus_addr_t *busaddr = arg; 2953157642Sps 2954157642Sps /* Simulate a mapping failure. */ 2955189325Sdavidch DBRUNIF(DB_RANDOMTRUE(dma_map_addr_failed_sim_control), 2956157642Sps error = ENOMEM); 2957179771Sdavidch 2958157642Sps /* Check for an error and signal the caller that an error occurred. */ 2959157642Sps if (error) { 2960163393Sscottl *busaddr = 0; 2961189325Sdavidch } else { 2962189325Sdavidch *busaddr = segs->ds_addr; 2963157642Sps } 2964157642Sps 2965163393Sscottl return; 2966157642Sps} 2967157642Sps 2968157642Sps 2969157642Sps/****************************************************************************/ 2970157642Sps/* Allocate any DMA memory needed by the driver. */ 2971157642Sps/* */ 2972157642Sps/* Allocates DMA memory needed for the various global structures needed by */ 2973182293Sdavidch/* hardware. */ 2974157642Sps/* */ 2975182293Sdavidch/* Memory alignment requirements: */ 2976182293Sdavidch/* +-----------------+----------+----------+----------+----------+ */ 2977182293Sdavidch/* | | 5706 | 5708 | 5709 | 5716 | */ 2978182293Sdavidch/* +-----------------+----------+----------+----------+----------+ */ 2979182293Sdavidch/* |Status Block | 8 bytes | 8 bytes | 16 bytes | 16 bytes | */ 2980182293Sdavidch/* |Statistics Block | 8 bytes | 8 bytes | 16 bytes | 16 bytes | */ 2981182293Sdavidch/* |RX Buffers | 16 bytes | 16 bytes | 16 bytes | 16 bytes | */ 2982182293Sdavidch/* |PG Buffers | none | none | none | none | */ 2983182293Sdavidch/* |TX Buffers | none | none | none | none | */ 2984182293Sdavidch/* |Chain Pages(1) | 4KiB | 4KiB | 4KiB | 4KiB | */ 2985202717Sdavidch/* |Context Memory | | | | | */ 2986182293Sdavidch/* +-----------------+----------+----------+----------+----------+ */ 2987182293Sdavidch/* */ 2988182293Sdavidch/* (1) Must align with CPU page size (BCM_PAGE_SZIE). */ 2989182293Sdavidch/* */ 2990157642Sps/* Returns: */ 2991157642Sps/* 0 for success, positive value for failure. */ 2992157642Sps/****************************************************************************/ 2993157642Spsstatic int 2994157642Spsbce_dma_alloc(device_t dev) 2995157642Sps{ 2996157642Sps struct bce_softc *sc; 2997157642Sps int i, error, rc = 0; 2998170392Sdavidch bus_size_t max_size, max_seg_size; 2999170392Sdavidch int max_segments; 3000157642Sps 3001157642Sps sc = device_get_softc(dev); 3002157642Sps 3003179771Sdavidch DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 3004179771Sdavidch 3005157642Sps /* 3006157642Sps * Allocate the parent bus DMA tag appropriate for PCI. 3007157642Sps */ 3008169632Sdavidch if (bus_dma_tag_create(NULL, 3009169632Sdavidch 1, 3010169632Sdavidch BCE_DMA_BOUNDARY, 3011169632Sdavidch sc->max_bus_addr, 3012169632Sdavidch BUS_SPACE_MAXADDR, 3013169632Sdavidch NULL, NULL, 3014169632Sdavidch MAXBSIZE, 3015169632Sdavidch BUS_SPACE_UNRESTRICTED, 3016169632Sdavidch BUS_SPACE_MAXSIZE_32BIT, 3017169632Sdavidch 0, 3018169632Sdavidch NULL, NULL, 3019157642Sps &sc->parent_tag)) { 3020169271Sdavidch BCE_PRINTF("%s(%d): Could not allocate parent DMA tag!\n", 3021157642Sps __FILE__, __LINE__); 3022157642Sps rc = ENOMEM; 3023157642Sps goto bce_dma_alloc_exit; 3024157642Sps } 3025157642Sps 3026157642Sps /* 3027157642Sps * Create a DMA tag for the status block, allocate and clear the 3028179771Sdavidch * memory, map the memory into DMA space, and fetch the physical 3029157642Sps * address of the block. 3030157642Sps */ 3031169632Sdavidch if (bus_dma_tag_create(sc->parent_tag, 3032169632Sdavidch BCE_DMA_ALIGN, 3033169632Sdavidch BCE_DMA_BOUNDARY, 3034169632Sdavidch sc->max_bus_addr, 3035169632Sdavidch BUS_SPACE_MAXADDR, 3036169632Sdavidch NULL, NULL, 3037169632Sdavidch BCE_STATUS_BLK_SZ, 3038169632Sdavidch 1, 3039169632Sdavidch BCE_STATUS_BLK_SZ, 3040169632Sdavidch 0, 3041169632Sdavidch NULL, NULL, 3042157642Sps &sc->status_tag)) { 3043169271Sdavidch BCE_PRINTF("%s(%d): Could not allocate status block DMA tag!\n", 3044157642Sps __FILE__, __LINE__); 3045157642Sps rc = ENOMEM; 3046157642Sps goto bce_dma_alloc_exit; 3047157642Sps } 3048157642Sps 3049169632Sdavidch if(bus_dmamem_alloc(sc->status_tag, 3050169632Sdavidch (void **)&sc->status_block, 3051169632Sdavidch BUS_DMA_NOWAIT, 3052157642Sps &sc->status_map)) { 3053169271Sdavidch BCE_PRINTF("%s(%d): Could not allocate status block DMA memory!\n", 3054157642Sps __FILE__, __LINE__); 3055157642Sps rc = ENOMEM; 3056157642Sps goto bce_dma_alloc_exit; 3057157642Sps } 3058157642Sps 3059157642Sps bzero((char *)sc->status_block, BCE_STATUS_BLK_SZ); 3060157642Sps 3061169632Sdavidch error = bus_dmamap_load(sc->status_tag, 3062169632Sdavidch sc->status_map, 3063169632Sdavidch sc->status_block, 3064169632Sdavidch BCE_STATUS_BLK_SZ, 3065169632Sdavidch bce_dma_map_addr, 3066187204Sdelphij &sc->status_block_paddr, 3067169632Sdavidch BUS_DMA_NOWAIT); 3068179771Sdavidch 3069163393Sscottl if (error) { 3070169271Sdavidch BCE_PRINTF("%s(%d): Could not map status block DMA memory!\n", 3071157642Sps __FILE__, __LINE__); 3072157642Sps rc = ENOMEM; 3073157642Sps goto bce_dma_alloc_exit; 3074157642Sps } 3075157642Sps 3076182293Sdavidch DBPRINT(sc, BCE_INFO, "%s(): status_block_paddr = 0x%jX\n", 3077182293Sdavidch __FUNCTION__, (uintmax_t) sc->status_block_paddr); 3078157642Sps 3079157642Sps /* 3080157642Sps * Create a DMA tag for the statistics block, allocate and clear the 3081179771Sdavidch * memory, map the memory into DMA space, and fetch the physical 3082157642Sps * address of the block. 3083157642Sps */ 3084169632Sdavidch if (bus_dma_tag_create(sc->parent_tag, 3085169632Sdavidch BCE_DMA_ALIGN, 3086169632Sdavidch BCE_DMA_BOUNDARY, 3087169632Sdavidch sc->max_bus_addr, 3088169632Sdavidch BUS_SPACE_MAXADDR, 3089169632Sdavidch NULL, NULL, 3090169632Sdavidch BCE_STATS_BLK_SZ, 3091169632Sdavidch 1, 3092169632Sdavidch BCE_STATS_BLK_SZ, 3093169632Sdavidch 0, 3094169632Sdavidch NULL, NULL, 3095157642Sps &sc->stats_tag)) { 3096169271Sdavidch BCE_PRINTF("%s(%d): Could not allocate statistics block DMA tag!\n", 3097157642Sps __FILE__, __LINE__); 3098157642Sps rc = ENOMEM; 3099157642Sps goto bce_dma_alloc_exit; 3100157642Sps } 3101157642Sps 3102169632Sdavidch if (bus_dmamem_alloc(sc->stats_tag, 3103169632Sdavidch (void **)&sc->stats_block, 3104169632Sdavidch BUS_DMA_NOWAIT, 3105157642Sps &sc->stats_map)) { 3106169271Sdavidch BCE_PRINTF("%s(%d): Could not allocate statistics block DMA memory!\n", 3107157642Sps __FILE__, __LINE__); 3108157642Sps rc = ENOMEM; 3109157642Sps goto bce_dma_alloc_exit; 3110157642Sps } 3111157642Sps 3112157642Sps bzero((char *)sc->stats_block, BCE_STATS_BLK_SZ); 3113157642Sps 3114169632Sdavidch error = bus_dmamap_load(sc->stats_tag, 3115169632Sdavidch sc->stats_map, 3116169632Sdavidch sc->stats_block, 3117169632Sdavidch BCE_STATS_BLK_SZ, 3118169632Sdavidch bce_dma_map_addr, 3119187204Sdelphij &sc->stats_block_paddr, 3120169632Sdavidch BUS_DMA_NOWAIT); 3121157642Sps 3122163393Sscottl if(error) { 3123169271Sdavidch BCE_PRINTF("%s(%d): Could not map statistics block DMA memory!\n", 3124157642Sps __FILE__, __LINE__); 3125157642Sps rc = ENOMEM; 3126157642Sps goto bce_dma_alloc_exit; 3127157642Sps } 3128157642Sps 3129182293Sdavidch DBPRINT(sc, BCE_INFO, "%s(): stats_block_paddr = 0x%jX\n", 3130182293Sdavidch __FUNCTION__, (uintmax_t) sc->stats_block_paddr); 3131157642Sps 3132179771Sdavidch /* BCM5709 uses host memory as cache for context memory. */ 3133182293Sdavidch if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 3134182293Sdavidch (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 3135179771Sdavidch sc->ctx_pages = 0x2000 / BCM_PAGE_SIZE; 3136179771Sdavidch if (sc->ctx_pages == 0) 3137179771Sdavidch sc->ctx_pages = 1; 3138179771Sdavidch 3139179771Sdavidch DBRUNIF((sc->ctx_pages > 512), 3140179771Sdavidch BCE_PRINTF("%s(%d): Too many CTX pages! %d > 512\n", 3141179771Sdavidch __FILE__, __LINE__, sc->ctx_pages)); 3142179771Sdavidch 3143179771Sdavidch /* 3144179771Sdavidch * Create a DMA tag for the context pages, 3145179771Sdavidch * allocate and clear the memory, map the 3146179771Sdavidch * memory into DMA space, and fetch the 3147179771Sdavidch * physical address of the block. 3148179771Sdavidch */ 3149179771Sdavidch if(bus_dma_tag_create(sc->parent_tag, 3150179771Sdavidch BCM_PAGE_SIZE, 3151179771Sdavidch BCE_DMA_BOUNDARY, 3152179771Sdavidch sc->max_bus_addr, 3153179771Sdavidch BUS_SPACE_MAXADDR, 3154179771Sdavidch NULL, NULL, 3155179771Sdavidch BCM_PAGE_SIZE, 3156179771Sdavidch 1, 3157179771Sdavidch BCM_PAGE_SIZE, 3158179771Sdavidch 0, 3159179771Sdavidch NULL, NULL, 3160179771Sdavidch &sc->ctx_tag)) { 3161179771Sdavidch BCE_PRINTF("%s(%d): Could not allocate CTX DMA tag!\n", 3162179771Sdavidch __FILE__, __LINE__); 3163179771Sdavidch rc = ENOMEM; 3164179771Sdavidch goto bce_dma_alloc_exit; 3165179771Sdavidch } 3166179771Sdavidch 3167179771Sdavidch for (i = 0; i < sc->ctx_pages; i++) { 3168179771Sdavidch 3169179771Sdavidch if(bus_dmamem_alloc(sc->ctx_tag, 3170179771Sdavidch (void **)&sc->ctx_block[i], 3171179771Sdavidch BUS_DMA_NOWAIT, 3172179771Sdavidch &sc->ctx_map[i])) { 3173179771Sdavidch BCE_PRINTF("%s(%d): Could not allocate CTX " 3174179771Sdavidch "DMA memory!\n", __FILE__, __LINE__); 3175179771Sdavidch rc = ENOMEM; 3176179771Sdavidch goto bce_dma_alloc_exit; 3177179771Sdavidch } 3178179771Sdavidch 3179179771Sdavidch bzero((char *)sc->ctx_block[i], BCM_PAGE_SIZE); 3180179771Sdavidch 3181179771Sdavidch error = bus_dmamap_load(sc->ctx_tag, 3182179771Sdavidch sc->ctx_map[i], 3183179771Sdavidch sc->ctx_block[i], 3184179771Sdavidch BCM_PAGE_SIZE, 3185179771Sdavidch bce_dma_map_addr, 3186187204Sdelphij &sc->ctx_paddr[i], 3187179771Sdavidch BUS_DMA_NOWAIT); 3188179771Sdavidch 3189179771Sdavidch if (error) { 3190179771Sdavidch BCE_PRINTF("%s(%d): Could not map CTX DMA memory!\n", 3191179771Sdavidch __FILE__, __LINE__); 3192179771Sdavidch rc = ENOMEM; 3193179771Sdavidch goto bce_dma_alloc_exit; 3194179771Sdavidch } 3195179771Sdavidch 3196182293Sdavidch DBPRINT(sc, BCE_INFO, "%s(): ctx_paddr[%d] = 0x%jX\n", 3197182293Sdavidch __FUNCTION__, i, (uintmax_t) sc->ctx_paddr[i]); 3198179771Sdavidch } 3199179771Sdavidch } 3200179771Sdavidch 3201157642Sps /* 3202157642Sps * Create a DMA tag for the TX buffer descriptor chain, 3203157642Sps * allocate and clear the memory, and fetch the 3204157642Sps * physical address of the block. 3205157642Sps */ 3206169632Sdavidch if(bus_dma_tag_create(sc->parent_tag, 3207169632Sdavidch BCM_PAGE_SIZE, 3208169632Sdavidch BCE_DMA_BOUNDARY, 3209169632Sdavidch sc->max_bus_addr, 3210179771Sdavidch BUS_SPACE_MAXADDR, 3211169632Sdavidch NULL, NULL, 3212169632Sdavidch BCE_TX_CHAIN_PAGE_SZ, 3213169632Sdavidch 1, 3214169632Sdavidch BCE_TX_CHAIN_PAGE_SZ, 3215169632Sdavidch 0, 3216169632Sdavidch NULL, NULL, 3217157642Sps &sc->tx_bd_chain_tag)) { 3218169271Sdavidch BCE_PRINTF("%s(%d): Could not allocate TX descriptor chain DMA tag!\n", 3219157642Sps __FILE__, __LINE__); 3220157642Sps rc = ENOMEM; 3221157642Sps goto bce_dma_alloc_exit; 3222157642Sps } 3223157642Sps 3224157642Sps for (i = 0; i < TX_PAGES; i++) { 3225157642Sps 3226169632Sdavidch if(bus_dmamem_alloc(sc->tx_bd_chain_tag, 3227169632Sdavidch (void **)&sc->tx_bd_chain[i], 3228169632Sdavidch BUS_DMA_NOWAIT, 3229157642Sps &sc->tx_bd_chain_map[i])) { 3230169271Sdavidch BCE_PRINTF("%s(%d): Could not allocate TX descriptor " 3231157642Sps "chain DMA memory!\n", __FILE__, __LINE__); 3232157642Sps rc = ENOMEM; 3233157642Sps goto bce_dma_alloc_exit; 3234157642Sps } 3235157642Sps 3236169632Sdavidch error = bus_dmamap_load(sc->tx_bd_chain_tag, 3237169632Sdavidch sc->tx_bd_chain_map[i], 3238169632Sdavidch sc->tx_bd_chain[i], 3239169632Sdavidch BCE_TX_CHAIN_PAGE_SZ, 3240169632Sdavidch bce_dma_map_addr, 3241187204Sdelphij &sc->tx_bd_chain_paddr[i], 3242169632Sdavidch BUS_DMA_NOWAIT); 3243157642Sps 3244163393Sscottl if (error) { 3245169271Sdavidch BCE_PRINTF("%s(%d): Could not map TX descriptor chain DMA memory!\n", 3246157642Sps __FILE__, __LINE__); 3247157642Sps rc = ENOMEM; 3248157642Sps goto bce_dma_alloc_exit; 3249157642Sps } 3250157642Sps 3251182293Sdavidch DBPRINT(sc, BCE_INFO, "%s(): tx_bd_chain_paddr[%d] = 0x%jX\n", 3252182293Sdavidch __FUNCTION__, i, (uintmax_t) sc->tx_bd_chain_paddr[i]); 3253157642Sps } 3254170392Sdavidch 3255170392Sdavidch /* Check the required size before mapping to conserve resources. */ 3256170392Sdavidch if (bce_tso_enable) { 3257170392Sdavidch max_size = BCE_TSO_MAX_SIZE; 3258170392Sdavidch max_segments = BCE_MAX_SEGMENTS; 3259170392Sdavidch max_seg_size = BCE_TSO_MAX_SEG_SIZE; 3260170392Sdavidch } else { 3261170392Sdavidch max_size = MCLBYTES * BCE_MAX_SEGMENTS; 3262170392Sdavidch max_segments = BCE_MAX_SEGMENTS; 3263170392Sdavidch max_seg_size = MCLBYTES; 3264170392Sdavidch } 3265179771Sdavidch 3266157642Sps /* Create a DMA tag for TX mbufs. */ 3267169632Sdavidch if (bus_dma_tag_create(sc->parent_tag, 3268169632Sdavidch 1, 3269169632Sdavidch BCE_DMA_BOUNDARY, 3270169632Sdavidch sc->max_bus_addr, 3271169632Sdavidch BUS_SPACE_MAXADDR, 3272169632Sdavidch NULL, NULL, 3273169632Sdavidch max_size, 3274169632Sdavidch max_segments, 3275170392Sdavidch max_seg_size, 3276169632Sdavidch 0, 3277169632Sdavidch NULL, NULL, 3278163287Sscottl &sc->tx_mbuf_tag)) { 3279169271Sdavidch BCE_PRINTF("%s(%d): Could not allocate TX mbuf DMA tag!\n", 3280157642Sps __FILE__, __LINE__); 3281157642Sps rc = ENOMEM; 3282157642Sps goto bce_dma_alloc_exit; 3283157642Sps } 3284157642Sps 3285157642Sps /* Create DMA maps for the TX mbufs clusters. */ 3286157642Sps for (i = 0; i < TOTAL_TX_BD; i++) { 3287179771Sdavidch if (bus_dmamap_create(sc->tx_mbuf_tag, BUS_DMA_NOWAIT, 3288157642Sps &sc->tx_mbuf_map[i])) { 3289169271Sdavidch BCE_PRINTF("%s(%d): Unable to create TX mbuf DMA map!\n", 3290157642Sps __FILE__, __LINE__); 3291157642Sps rc = ENOMEM; 3292157642Sps goto bce_dma_alloc_exit; 3293157642Sps } 3294157642Sps } 3295157642Sps 3296157642Sps /* 3297157642Sps * Create a DMA tag for the RX buffer descriptor chain, 3298176448Sdavidch * allocate and clear the memory, and fetch the physical 3299157642Sps * address of the blocks. 3300157642Sps */ 3301169632Sdavidch if (bus_dma_tag_create(sc->parent_tag, 3302169632Sdavidch BCM_PAGE_SIZE, 3303169632Sdavidch BCE_DMA_BOUNDARY, 3304169632Sdavidch BUS_SPACE_MAXADDR, 3305169632Sdavidch sc->max_bus_addr, 3306169632Sdavidch NULL, NULL, 3307169632Sdavidch BCE_RX_CHAIN_PAGE_SZ, 3308169632Sdavidch 1, 3309169632Sdavidch BCE_RX_CHAIN_PAGE_SZ, 3310169632Sdavidch 0, 3311169632Sdavidch NULL, NULL, 3312157642Sps &sc->rx_bd_chain_tag)) { 3313169271Sdavidch BCE_PRINTF("%s(%d): Could not allocate RX descriptor chain DMA tag!\n", 3314157642Sps __FILE__, __LINE__); 3315157642Sps rc = ENOMEM; 3316157642Sps goto bce_dma_alloc_exit; 3317157642Sps } 3318157642Sps 3319157642Sps for (i = 0; i < RX_PAGES; i++) { 3320157642Sps 3321169632Sdavidch if (bus_dmamem_alloc(sc->rx_bd_chain_tag, 3322169632Sdavidch (void **)&sc->rx_bd_chain[i], 3323169632Sdavidch BUS_DMA_NOWAIT, 3324157642Sps &sc->rx_bd_chain_map[i])) { 3325169271Sdavidch BCE_PRINTF("%s(%d): Could not allocate RX descriptor chain " 3326157642Sps "DMA memory!\n", __FILE__, __LINE__); 3327157642Sps rc = ENOMEM; 3328157642Sps goto bce_dma_alloc_exit; 3329157642Sps } 3330157642Sps 3331157642Sps bzero((char *)sc->rx_bd_chain[i], BCE_RX_CHAIN_PAGE_SZ); 3332157642Sps 3333169632Sdavidch error = bus_dmamap_load(sc->rx_bd_chain_tag, 3334169632Sdavidch sc->rx_bd_chain_map[i], 3335169632Sdavidch sc->rx_bd_chain[i], 3336169632Sdavidch BCE_RX_CHAIN_PAGE_SZ, 3337169632Sdavidch bce_dma_map_addr, 3338187204Sdelphij &sc->rx_bd_chain_paddr[i], 3339169632Sdavidch BUS_DMA_NOWAIT); 3340157642Sps 3341163393Sscottl if (error) { 3342169271Sdavidch BCE_PRINTF("%s(%d): Could not map RX descriptor chain DMA memory!\n", 3343157642Sps __FILE__, __LINE__); 3344157642Sps rc = ENOMEM; 3345157642Sps goto bce_dma_alloc_exit; 3346157642Sps } 3347157642Sps 3348182293Sdavidch DBPRINT(sc, BCE_INFO, "%s(): rx_bd_chain_paddr[%d] = 0x%jX\n", 3349182293Sdavidch __FUNCTION__, i, (uintmax_t) sc->rx_bd_chain_paddr[i]); 3350157642Sps } 3351157642Sps 3352157642Sps /* 3353157642Sps * Create a DMA tag for RX mbufs. 3354178132Sdavidch */ 3355198320Sstas#ifdef BCE_JUMBO_HDRSPLIT 3356182293Sdavidch max_size = max_seg_size = ((sc->rx_bd_mbuf_alloc_size < MCLBYTES) ? 3357179771Sdavidch MCLBYTES : sc->rx_bd_mbuf_alloc_size); 3358179771Sdavidch#else 3359179771Sdavidch max_size = max_seg_size = MJUM9BYTES; 3360179771Sdavidch#endif 3361189325Sdavidch max_segments = 1; 3362176448Sdavidch 3363189325Sdavidch DBPRINT(sc, BCE_INFO, "%s(): Creating rx_mbuf_tag (max size = 0x%jX " 3364189325Sdavidch "max segments = %d, max segment size = 0x%jX)\n", __FUNCTION__, 3365189325Sdavidch (uintmax_t) max_size, max_segments, (uintmax_t) max_seg_size); 3366189325Sdavidch 3367169632Sdavidch if (bus_dma_tag_create(sc->parent_tag, 3368169632Sdavidch 1, 3369169632Sdavidch BCE_DMA_BOUNDARY, 3370169632Sdavidch sc->max_bus_addr, 3371169632Sdavidch BUS_SPACE_MAXADDR, 3372169632Sdavidch NULL, NULL, 3373176448Sdavidch max_size, 3374189325Sdavidch max_segments, 3375176448Sdavidch max_seg_size, 3376169632Sdavidch 0, 3377169632Sdavidch NULL, NULL, 3378157642Sps &sc->rx_mbuf_tag)) { 3379169271Sdavidch BCE_PRINTF("%s(%d): Could not allocate RX mbuf DMA tag!\n", 3380157642Sps __FILE__, __LINE__); 3381157642Sps rc = ENOMEM; 3382157642Sps goto bce_dma_alloc_exit; 3383157642Sps } 3384157642Sps 3385157642Sps /* Create DMA maps for the RX mbuf clusters. */ 3386157642Sps for (i = 0; i < TOTAL_RX_BD; i++) { 3387157642Sps if (bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_NOWAIT, 3388157642Sps &sc->rx_mbuf_map[i])) { 3389169271Sdavidch BCE_PRINTF("%s(%d): Unable to create RX mbuf DMA map!\n", 3390157642Sps __FILE__, __LINE__); 3391157642Sps rc = ENOMEM; 3392157642Sps goto bce_dma_alloc_exit; 3393157642Sps } 3394157642Sps } 3395157642Sps 3396198320Sstas#ifdef BCE_JUMBO_HDRSPLIT 3397176448Sdavidch /* 3398176448Sdavidch * Create a DMA tag for the page buffer descriptor chain, 3399176448Sdavidch * allocate and clear the memory, and fetch the physical 3400176448Sdavidch * address of the blocks. 3401176448Sdavidch */ 3402176448Sdavidch if (bus_dma_tag_create(sc->parent_tag, 3403176448Sdavidch BCM_PAGE_SIZE, 3404176448Sdavidch BCE_DMA_BOUNDARY, 3405176448Sdavidch BUS_SPACE_MAXADDR, 3406176448Sdavidch sc->max_bus_addr, 3407176448Sdavidch NULL, NULL, 3408176448Sdavidch BCE_PG_CHAIN_PAGE_SZ, 3409176448Sdavidch 1, 3410176448Sdavidch BCE_PG_CHAIN_PAGE_SZ, 3411176448Sdavidch 0, 3412176448Sdavidch NULL, NULL, 3413176448Sdavidch &sc->pg_bd_chain_tag)) { 3414176448Sdavidch BCE_PRINTF("%s(%d): Could not allocate page descriptor chain DMA tag!\n", 3415176448Sdavidch __FILE__, __LINE__); 3416176448Sdavidch rc = ENOMEM; 3417176448Sdavidch goto bce_dma_alloc_exit; 3418176448Sdavidch } 3419176448Sdavidch 3420176448Sdavidch for (i = 0; i < PG_PAGES; i++) { 3421176448Sdavidch 3422176448Sdavidch if (bus_dmamem_alloc(sc->pg_bd_chain_tag, 3423176448Sdavidch (void **)&sc->pg_bd_chain[i], 3424176448Sdavidch BUS_DMA_NOWAIT, 3425176448Sdavidch &sc->pg_bd_chain_map[i])) { 3426176448Sdavidch BCE_PRINTF("%s(%d): Could not allocate page descriptor chain " 3427176448Sdavidch "DMA memory!\n", __FILE__, __LINE__); 3428176448Sdavidch rc = ENOMEM; 3429176448Sdavidch goto bce_dma_alloc_exit; 3430176448Sdavidch } 3431176448Sdavidch 3432176448Sdavidch bzero((char *)sc->pg_bd_chain[i], BCE_PG_CHAIN_PAGE_SZ); 3433176448Sdavidch 3434176448Sdavidch error = bus_dmamap_load(sc->pg_bd_chain_tag, 3435176448Sdavidch sc->pg_bd_chain_map[i], 3436176448Sdavidch sc->pg_bd_chain[i], 3437176448Sdavidch BCE_PG_CHAIN_PAGE_SZ, 3438176448Sdavidch bce_dma_map_addr, 3439187204Sdelphij &sc->pg_bd_chain_paddr[i], 3440176448Sdavidch BUS_DMA_NOWAIT); 3441176448Sdavidch 3442176448Sdavidch if (error) { 3443176448Sdavidch BCE_PRINTF("%s(%d): Could not map page descriptor chain DMA memory!\n", 3444176448Sdavidch __FILE__, __LINE__); 3445176448Sdavidch rc = ENOMEM; 3446176448Sdavidch goto bce_dma_alloc_exit; 3447176448Sdavidch } 3448176448Sdavidch 3449182293Sdavidch DBPRINT(sc, BCE_INFO, "%s(): pg_bd_chain_paddr[%d] = 0x%jX\n", 3450182293Sdavidch __FUNCTION__, i, (uintmax_t) sc->pg_bd_chain_paddr[i]); 3451176448Sdavidch } 3452176448Sdavidch 3453176448Sdavidch /* 3454176448Sdavidch * Create a DMA tag for page mbufs. 3455176448Sdavidch */ 3456179771Sdavidch max_size = max_seg_size = ((sc->pg_bd_mbuf_alloc_size < MCLBYTES) ? 3457179695Sdavidch MCLBYTES : sc->pg_bd_mbuf_alloc_size); 3458176448Sdavidch 3459176448Sdavidch if (bus_dma_tag_create(sc->parent_tag, 3460176448Sdavidch 1, 3461176448Sdavidch BCE_DMA_BOUNDARY, 3462176448Sdavidch sc->max_bus_addr, 3463176448Sdavidch BUS_SPACE_MAXADDR, 3464176448Sdavidch NULL, NULL, 3465176448Sdavidch max_size, 3466176448Sdavidch 1, 3467176448Sdavidch max_seg_size, 3468176448Sdavidch 0, 3469176448Sdavidch NULL, NULL, 3470176448Sdavidch &sc->pg_mbuf_tag)) { 3471176448Sdavidch BCE_PRINTF("%s(%d): Could not allocate page mbuf DMA tag!\n", 3472176448Sdavidch __FILE__, __LINE__); 3473176448Sdavidch rc = ENOMEM; 3474176448Sdavidch goto bce_dma_alloc_exit; 3475176448Sdavidch } 3476176448Sdavidch 3477176448Sdavidch /* Create DMA maps for the page mbuf clusters. */ 3478176448Sdavidch for (i = 0; i < TOTAL_PG_BD; i++) { 3479176448Sdavidch if (bus_dmamap_create(sc->pg_mbuf_tag, BUS_DMA_NOWAIT, 3480176448Sdavidch &sc->pg_mbuf_map[i])) { 3481176448Sdavidch BCE_PRINTF("%s(%d): Unable to create page mbuf DMA map!\n", 3482176448Sdavidch __FILE__, __LINE__); 3483176448Sdavidch rc = ENOMEM; 3484176448Sdavidch goto bce_dma_alloc_exit; 3485176448Sdavidch } 3486176448Sdavidch } 3487179771Sdavidch#endif 3488176448Sdavidch 3489157642Spsbce_dma_alloc_exit: 3490179771Sdavidch DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 3491157642Sps return(rc); 3492157642Sps} 3493157642Sps 3494157642Sps 3495157642Sps/****************************************************************************/ 3496157642Sps/* Release all resources used by the driver. */ 3497157642Sps/* */ 3498157642Sps/* Releases all resources acquired by the driver including interrupts, */ 3499157642Sps/* interrupt handler, interfaces, mutexes, and DMA memory. */ 3500157642Sps/* */ 3501157642Sps/* Returns: */ 3502157642Sps/* Nothing. */ 3503157642Sps/****************************************************************************/ 3504157642Spsstatic void 3505157642Spsbce_release_resources(struct bce_softc *sc) 3506157642Sps{ 3507157642Sps device_t dev; 3508157642Sps 3509179771Sdavidch DBENTER(BCE_VERBOSE_RESET); 3510157642Sps 3511157642Sps dev = sc->bce_dev; 3512157642Sps 3513157642Sps bce_dma_free(sc); 3514170392Sdavidch 3515170392Sdavidch if (sc->bce_intrhand != NULL) { 3516169632Sdavidch DBPRINT(sc, BCE_INFO_RESET, "Removing interrupt handler.\n"); 3517170392Sdavidch bus_teardown_intr(dev, sc->bce_res_irq, sc->bce_intrhand); 3518169632Sdavidch } 3519157642Sps 3520170392Sdavidch if (sc->bce_res_irq != NULL) { 3521169632Sdavidch DBPRINT(sc, BCE_INFO_RESET, "Releasing IRQ.\n"); 3522179771Sdavidch bus_release_resource(dev, SYS_RES_IRQ, sc->bce_irq_rid, 3523169632Sdavidch sc->bce_res_irq); 3524169632Sdavidch } 3525170392Sdavidch 3526179771Sdavidch if (sc->bce_flags & (BCE_USING_MSI_FLAG | BCE_USING_MSIX_FLAG)) { 3527179771Sdavidch DBPRINT(sc, BCE_INFO_RESET, "Releasing MSI/MSI-X vector.\n"); 3528170392Sdavidch pci_release_msi(dev); 3529170392Sdavidch } 3530157642Sps 3531170392Sdavidch if (sc->bce_res_mem != NULL) { 3532169632Sdavidch DBPRINT(sc, BCE_INFO_RESET, "Releasing PCI memory.\n"); 3533170392Sdavidch bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0), sc->bce_res_mem); 3534169632Sdavidch } 3535157642Sps 3536170392Sdavidch if (sc->bce_ifp != NULL) { 3537169632Sdavidch DBPRINT(sc, BCE_INFO_RESET, "Releasing IF.\n"); 3538170392Sdavidch if_free(sc->bce_ifp); 3539169632Sdavidch } 3540164305Sjhb 3541157642Sps if (mtx_initialized(&sc->bce_mtx)) 3542157642Sps BCE_LOCK_DESTROY(sc); 3543157642Sps 3544179771Sdavidch DBEXIT(BCE_VERBOSE_RESET); 3545157642Sps} 3546157642Sps 3547157642Sps 3548157642Sps/****************************************************************************/ 3549157642Sps/* Firmware synchronization. */ 3550157642Sps/* */ 3551157642Sps/* Before performing certain events such as a chip reset, synchronize with */ 3552157642Sps/* the firmware first. */ 3553157642Sps/* */ 3554157642Sps/* Returns: */ 3555157642Sps/* 0 for success, positive value for failure. */ 3556157642Sps/****************************************************************************/ 3557157642Spsstatic int 3558157642Spsbce_fw_sync(struct bce_softc *sc, u32 msg_data) 3559157642Sps{ 3560157642Sps int i, rc = 0; 3561157642Sps u32 val; 3562157642Sps 3563179771Sdavidch DBENTER(BCE_VERBOSE_RESET); 3564179771Sdavidch 3565157642Sps /* Don't waste any time if we've timed out before. */ 3566157642Sps if (sc->bce_fw_timed_out) { 3567157642Sps rc = EBUSY; 3568157642Sps goto bce_fw_sync_exit; 3569157642Sps } 3570157642Sps 3571157642Sps /* Increment the message sequence number. */ 3572157642Sps sc->bce_fw_wr_seq++; 3573157642Sps msg_data |= sc->bce_fw_wr_seq; 3574157642Sps 3575179771Sdavidch DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "bce_fw_sync(): msg_data = 0x%08X\n", 3576179771Sdavidch msg_data); 3577157642Sps 3578157642Sps /* Send the message to the bootcode driver mailbox. */ 3579194781Sdavidch bce_shmem_wr(sc, BCE_DRV_MB, msg_data); 3580157642Sps 3581157642Sps /* Wait for the bootcode to acknowledge the message. */ 3582157642Sps for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) { 3583157642Sps /* Check for a response in the bootcode firmware mailbox. */ 3584194781Sdavidch val = bce_shmem_rd(sc, BCE_FW_MB); 3585157642Sps if ((val & BCE_FW_MSG_ACK) == (msg_data & BCE_DRV_MSG_SEQ)) 3586157642Sps break; 3587157642Sps DELAY(1000); 3588157642Sps } 3589157642Sps 3590157642Sps /* If we've timed out, tell the bootcode that we've stopped waiting. */ 3591157642Sps if (((val & BCE_FW_MSG_ACK) != (msg_data & BCE_DRV_MSG_SEQ)) && 3592157642Sps ((msg_data & BCE_DRV_MSG_DATA) != BCE_DRV_MSG_DATA_WAIT0)) { 3593157642Sps 3594169271Sdavidch BCE_PRINTF("%s(%d): Firmware synchronization timeout! " 3595157642Sps "msg_data = 0x%08X\n", 3596157642Sps __FILE__, __LINE__, msg_data); 3597157642Sps 3598157642Sps msg_data &= ~BCE_DRV_MSG_CODE; 3599157642Sps msg_data |= BCE_DRV_MSG_CODE_FW_TIMEOUT; 3600157642Sps 3601194781Sdavidch bce_shmem_wr(sc, BCE_DRV_MB, msg_data); 3602157642Sps 3603157642Sps sc->bce_fw_timed_out = 1; 3604157642Sps rc = EBUSY; 3605157642Sps } 3606157642Sps 3607157642Spsbce_fw_sync_exit: 3608179771Sdavidch DBEXIT(BCE_VERBOSE_RESET); 3609157642Sps return (rc); 3610157642Sps} 3611157642Sps 3612157642Sps 3613157642Sps/****************************************************************************/ 3614157642Sps/* Load Receive Virtual 2 Physical (RV2P) processor firmware. */ 3615157642Sps/* */ 3616157642Sps/* Returns: */ 3617157642Sps/* Nothing. */ 3618157642Sps/****************************************************************************/ 3619157642Spsstatic void 3620179771Sdavidchbce_load_rv2p_fw(struct bce_softc *sc, u32 *rv2p_code, 3621157642Sps u32 rv2p_code_len, u32 rv2p_proc) 3622157642Sps{ 3623157642Sps int i; 3624157642Sps u32 val; 3625178132Sdavidch 3626179771Sdavidch DBENTER(BCE_VERBOSE_RESET); 3627179771Sdavidch 3628176448Sdavidch /* Set the page size used by RV2P. */ 3629176448Sdavidch if (rv2p_proc == RV2P_PROC2) { 3630178132Sdavidch BCE_RV2P_PROC2_CHG_MAX_BD_PAGE(USABLE_RX_BD_PER_PAGE); 3631176448Sdavidch } 3632178132Sdavidch 3633157642Sps for (i = 0; i < rv2p_code_len; i += 8) { 3634157642Sps REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code); 3635157642Sps rv2p_code++; 3636157642Sps REG_WR(sc, BCE_RV2P_INSTR_LOW, *rv2p_code); 3637157642Sps rv2p_code++; 3638157642Sps 3639157642Sps if (rv2p_proc == RV2P_PROC1) { 3640157642Sps val = (i / 8) | BCE_RV2P_PROC1_ADDR_CMD_RDWR; 3641157642Sps REG_WR(sc, BCE_RV2P_PROC1_ADDR_CMD, val); 3642157642Sps } 3643157642Sps else { 3644157642Sps val = (i / 8) | BCE_RV2P_PROC2_ADDR_CMD_RDWR; 3645157642Sps REG_WR(sc, BCE_RV2P_PROC2_ADDR_CMD, val); 3646157642Sps } 3647157642Sps } 3648157642Sps 3649157642Sps /* Reset the processor, un-stall is done later. */ 3650157642Sps if (rv2p_proc == RV2P_PROC1) { 3651157642Sps REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET); 3652157642Sps } 3653157642Sps else { 3654157642Sps REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET); 3655157642Sps } 3656179771Sdavidch 3657179771Sdavidch DBEXIT(BCE_VERBOSE_RESET); 3658157642Sps} 3659157642Sps 3660157642Sps 3661157642Sps/****************************************************************************/ 3662157642Sps/* Load RISC processor firmware. */ 3663157642Sps/* */ 3664157642Sps/* Loads firmware from the file if_bcefw.h into the scratchpad memory */ 3665157642Sps/* associated with a particular processor. */ 3666157642Sps/* */ 3667157642Sps/* Returns: */ 3668157642Sps/* Nothing. */ 3669157642Sps/****************************************************************************/ 3670157642Spsstatic void 3671157642Spsbce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg, 3672157642Sps struct fw_info *fw) 3673157642Sps{ 3674157642Sps u32 offset; 3675157642Sps 3676179771Sdavidch DBENTER(BCE_VERBOSE_RESET); 3677179771Sdavidch 3678202717Sdavidch bce_halt_cpu(sc, cpu_reg); 3679157642Sps 3680157642Sps /* Load the Text area. */ 3681157642Sps offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base); 3682157642Sps if (fw->text) { 3683157642Sps int j; 3684157642Sps 3685157642Sps for (j = 0; j < (fw->text_len / 4); j++, offset += 4) { 3686157642Sps REG_WR_IND(sc, offset, fw->text[j]); 3687157642Sps } 3688157642Sps } 3689157642Sps 3690157642Sps /* Load the Data area. */ 3691157642Sps offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base); 3692157642Sps if (fw->data) { 3693157642Sps int j; 3694157642Sps 3695157642Sps for (j = 0; j < (fw->data_len / 4); j++, offset += 4) { 3696157642Sps REG_WR_IND(sc, offset, fw->data[j]); 3697157642Sps } 3698157642Sps } 3699157642Sps 3700157642Sps /* Load the SBSS area. */ 3701157642Sps offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base); 3702157642Sps if (fw->sbss) { 3703157642Sps int j; 3704157642Sps 3705157642Sps for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) { 3706157642Sps REG_WR_IND(sc, offset, fw->sbss[j]); 3707157642Sps } 3708157642Sps } 3709157642Sps 3710157642Sps /* Load the BSS area. */ 3711157642Sps offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base); 3712157642Sps if (fw->bss) { 3713157642Sps int j; 3714157642Sps 3715157642Sps for (j = 0; j < (fw->bss_len/4); j++, offset += 4) { 3716157642Sps REG_WR_IND(sc, offset, fw->bss[j]); 3717157642Sps } 3718157642Sps } 3719157642Sps 3720157642Sps /* Load the Read-Only area. */ 3721157642Sps offset = cpu_reg->spad_base + 3722157642Sps (fw->rodata_addr - cpu_reg->mips_view_base); 3723157642Sps if (fw->rodata) { 3724157642Sps int j; 3725157642Sps 3726157642Sps for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) { 3727157642Sps REG_WR_IND(sc, offset, fw->rodata[j]); 3728157642Sps } 3729157642Sps } 3730157642Sps 3731202717Sdavidch /* Clear the pre-fetch instruction and set the FW start address. */ 3732202717Sdavidch REG_WR_IND(sc, cpu_reg->inst, 0); 3733202717Sdavidch REG_WR_IND(sc, cpu_reg->pc, fw->start_addr); 3734157642Sps 3735202717Sdavidch DBEXIT(BCE_VERBOSE_RESET); 3736202717Sdavidch} 3737202717Sdavidch 3738202717Sdavidch 3739202717Sdavidch/****************************************************************************/ 3740202717Sdavidch/* Starts the RISC processor. */ 3741202717Sdavidch/* */ 3742202717Sdavidch/* Assumes the CPU starting address has already been set. */ 3743202717Sdavidch/* */ 3744202717Sdavidch/* Returns: */ 3745202717Sdavidch/* Nothing. */ 3746202717Sdavidch/****************************************************************************/ 3747202717Sdavidchstatic void 3748202717Sdavidchbce_start_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg) 3749202717Sdavidch{ 3750202717Sdavidch u32 val; 3751202717Sdavidch 3752202717Sdavidch DBENTER(BCE_VERBOSE_RESET); 3753202717Sdavidch 3754157642Sps /* Start the CPU. */ 3755157642Sps val = REG_RD_IND(sc, cpu_reg->mode); 3756157642Sps val &= ~cpu_reg->mode_value_halt; 3757157642Sps REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 3758157642Sps REG_WR_IND(sc, cpu_reg->mode, val); 3759179771Sdavidch 3760179771Sdavidch DBEXIT(BCE_VERBOSE_RESET); 3761157642Sps} 3762157642Sps 3763157642Sps 3764157642Sps/****************************************************************************/ 3765202717Sdavidch/* Halts the RISC processor. */ 3766202717Sdavidch/* */ 3767202717Sdavidch/* Returns: */ 3768202717Sdavidch/* Nothing. */ 3769202717Sdavidch/****************************************************************************/ 3770202717Sdavidchstatic void 3771202717Sdavidchbce_halt_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg) 3772202717Sdavidch{ 3773202717Sdavidch u32 val; 3774202717Sdavidch 3775202717Sdavidch DBENTER(BCE_VERBOSE_RESET); 3776202717Sdavidch 3777202717Sdavidch /* Halt the CPU. */ 3778202717Sdavidch val = REG_RD_IND(sc, cpu_reg->mode); 3779202717Sdavidch val |= cpu_reg->mode_value_halt; 3780202717Sdavidch REG_WR_IND(sc, cpu_reg->mode, val); 3781202717Sdavidch REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 3782202717Sdavidch 3783202717Sdavidch DBEXIT(BCE_VERBOSE_RESET); 3784202717Sdavidch} 3785202717Sdavidch 3786202717Sdavidch 3787202717Sdavidch/****************************************************************************/ 3788179771Sdavidch/* Initialize the RX CPU. */ 3789157642Sps/* */ 3790157642Sps/* Returns: */ 3791157642Sps/* Nothing. */ 3792157642Sps/****************************************************************************/ 3793157642Spsstatic void 3794202717Sdavidchbce_start_rxp_cpu(struct bce_softc *sc) 3795202717Sdavidch{ 3796202717Sdavidch struct cpu_reg cpu_reg; 3797202717Sdavidch 3798202717Sdavidch DBENTER(BCE_VERBOSE_RESET); 3799202717Sdavidch 3800202717Sdavidch cpu_reg.mode = BCE_RXP_CPU_MODE; 3801202717Sdavidch cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT; 3802202717Sdavidch cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA; 3803202717Sdavidch cpu_reg.state = BCE_RXP_CPU_STATE; 3804202717Sdavidch cpu_reg.state_value_clear = 0xffffff; 3805202717Sdavidch cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE; 3806202717Sdavidch cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK; 3807202717Sdavidch cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER; 3808202717Sdavidch cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION; 3809202717Sdavidch cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT; 3810202717Sdavidch cpu_reg.spad_base = BCE_RXP_SCRATCH; 3811202717Sdavidch cpu_reg.mips_view_base = 0x8000000; 3812202717Sdavidch 3813202717Sdavidch DBPRINT(sc, BCE_INFO_RESET, "Starting RX firmware.\n"); 3814202717Sdavidch bce_start_cpu(sc, &cpu_reg); 3815202717Sdavidch 3816202717Sdavidch DBEXIT(BCE_VERBOSE_RESET); 3817202717Sdavidch} 3818202717Sdavidch 3819202717Sdavidch 3820202717Sdavidch/****************************************************************************/ 3821202717Sdavidch/* Initialize the RX CPU. */ 3822202717Sdavidch/* */ 3823202717Sdavidch/* Returns: */ 3824202717Sdavidch/* Nothing. */ 3825202717Sdavidch/****************************************************************************/ 3826202717Sdavidchstatic void 3827179771Sdavidchbce_init_rxp_cpu(struct bce_softc *sc) 3828157642Sps{ 3829157642Sps struct cpu_reg cpu_reg; 3830157642Sps struct fw_info fw; 3831157642Sps 3832179771Sdavidch DBENTER(BCE_VERBOSE_RESET); 3833157642Sps 3834157642Sps cpu_reg.mode = BCE_RXP_CPU_MODE; 3835157642Sps cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT; 3836157642Sps cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA; 3837157642Sps cpu_reg.state = BCE_RXP_CPU_STATE; 3838157642Sps cpu_reg.state_value_clear = 0xffffff; 3839157642Sps cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE; 3840157642Sps cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK; 3841157642Sps cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER; 3842157642Sps cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION; 3843157642Sps cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT; 3844157642Sps cpu_reg.spad_base = BCE_RXP_SCRATCH; 3845157642Sps cpu_reg.mips_view_base = 0x8000000; 3846157642Sps 3847182293Sdavidch if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 3848182293Sdavidch (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 3849179771Sdavidch fw.ver_major = bce_RXP_b09FwReleaseMajor; 3850179771Sdavidch fw.ver_minor = bce_RXP_b09FwReleaseMinor; 3851179771Sdavidch fw.ver_fix = bce_RXP_b09FwReleaseFix; 3852179771Sdavidch fw.start_addr = bce_RXP_b09FwStartAddr; 3853157642Sps 3854179771Sdavidch fw.text_addr = bce_RXP_b09FwTextAddr; 3855179771Sdavidch fw.text_len = bce_RXP_b09FwTextLen; 3856179771Sdavidch fw.text_index = 0; 3857179771Sdavidch fw.text = bce_RXP_b09FwText; 3858157642Sps 3859179771Sdavidch fw.data_addr = bce_RXP_b09FwDataAddr; 3860179771Sdavidch fw.data_len = bce_RXP_b09FwDataLen; 3861179771Sdavidch fw.data_index = 0; 3862179771Sdavidch fw.data = bce_RXP_b09FwData; 3863157642Sps 3864179771Sdavidch fw.sbss_addr = bce_RXP_b09FwSbssAddr; 3865179771Sdavidch fw.sbss_len = bce_RXP_b09FwSbssLen; 3866179771Sdavidch fw.sbss_index = 0; 3867179771Sdavidch fw.sbss = bce_RXP_b09FwSbss; 3868157642Sps 3869179771Sdavidch fw.bss_addr = bce_RXP_b09FwBssAddr; 3870179771Sdavidch fw.bss_len = bce_RXP_b09FwBssLen; 3871179771Sdavidch fw.bss_index = 0; 3872179771Sdavidch fw.bss = bce_RXP_b09FwBss; 3873157642Sps 3874179771Sdavidch fw.rodata_addr = bce_RXP_b09FwRodataAddr; 3875179771Sdavidch fw.rodata_len = bce_RXP_b09FwRodataLen; 3876179771Sdavidch fw.rodata_index = 0; 3877179771Sdavidch fw.rodata = bce_RXP_b09FwRodata; 3878179771Sdavidch } else { 3879179771Sdavidch fw.ver_major = bce_RXP_b06FwReleaseMajor; 3880179771Sdavidch fw.ver_minor = bce_RXP_b06FwReleaseMinor; 3881179771Sdavidch fw.ver_fix = bce_RXP_b06FwReleaseFix; 3882179771Sdavidch fw.start_addr = bce_RXP_b06FwStartAddr; 3883157642Sps 3884179771Sdavidch fw.text_addr = bce_RXP_b06FwTextAddr; 3885179771Sdavidch fw.text_len = bce_RXP_b06FwTextLen; 3886179771Sdavidch fw.text_index = 0; 3887179771Sdavidch fw.text = bce_RXP_b06FwText; 3888179771Sdavidch 3889179771Sdavidch fw.data_addr = bce_RXP_b06FwDataAddr; 3890179771Sdavidch fw.data_len = bce_RXP_b06FwDataLen; 3891179771Sdavidch fw.data_index = 0; 3892179771Sdavidch fw.data = bce_RXP_b06FwData; 3893179771Sdavidch 3894179771Sdavidch fw.sbss_addr = bce_RXP_b06FwSbssAddr; 3895179771Sdavidch fw.sbss_len = bce_RXP_b06FwSbssLen; 3896179771Sdavidch fw.sbss_index = 0; 3897179771Sdavidch fw.sbss = bce_RXP_b06FwSbss; 3898179771Sdavidch 3899179771Sdavidch fw.bss_addr = bce_RXP_b06FwBssAddr; 3900179771Sdavidch fw.bss_len = bce_RXP_b06FwBssLen; 3901179771Sdavidch fw.bss_index = 0; 3902179771Sdavidch fw.bss = bce_RXP_b06FwBss; 3903179771Sdavidch 3904179771Sdavidch fw.rodata_addr = bce_RXP_b06FwRodataAddr; 3905179771Sdavidch fw.rodata_len = bce_RXP_b06FwRodataLen; 3906179771Sdavidch fw.rodata_index = 0; 3907179771Sdavidch fw.rodata = bce_RXP_b06FwRodata; 3908179771Sdavidch } 3909179771Sdavidch 3910157642Sps DBPRINT(sc, BCE_INFO_RESET, "Loading RX firmware.\n"); 3911157642Sps bce_load_cpu_fw(sc, &cpu_reg, &fw); 3912157642Sps 3913202717Sdavidch /* Delay RXP start until initialization is complete. */ 3914202717Sdavidch 3915179771Sdavidch DBEXIT(BCE_VERBOSE_RESET); 3916179771Sdavidch} 3917179771Sdavidch 3918179771Sdavidch 3919179771Sdavidch/****************************************************************************/ 3920179771Sdavidch/* Initialize the TX CPU. */ 3921179771Sdavidch/* */ 3922179771Sdavidch/* Returns: */ 3923179771Sdavidch/* Nothing. */ 3924179771Sdavidch/****************************************************************************/ 3925179771Sdavidchstatic void 3926179771Sdavidchbce_init_txp_cpu(struct bce_softc *sc) 3927179771Sdavidch{ 3928179771Sdavidch struct cpu_reg cpu_reg; 3929179771Sdavidch struct fw_info fw; 3930179771Sdavidch 3931179771Sdavidch DBENTER(BCE_VERBOSE_RESET); 3932179771Sdavidch 3933157642Sps cpu_reg.mode = BCE_TXP_CPU_MODE; 3934157642Sps cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT; 3935157642Sps cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA; 3936157642Sps cpu_reg.state = BCE_TXP_CPU_STATE; 3937157642Sps cpu_reg.state_value_clear = 0xffffff; 3938157642Sps cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE; 3939157642Sps cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK; 3940157642Sps cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER; 3941157642Sps cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION; 3942157642Sps cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT; 3943157642Sps cpu_reg.spad_base = BCE_TXP_SCRATCH; 3944157642Sps cpu_reg.mips_view_base = 0x8000000; 3945157642Sps 3946182293Sdavidch if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 3947182293Sdavidch (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 3948179771Sdavidch fw.ver_major = bce_TXP_b09FwReleaseMajor; 3949179771Sdavidch fw.ver_minor = bce_TXP_b09FwReleaseMinor; 3950179771Sdavidch fw.ver_fix = bce_TXP_b09FwReleaseFix; 3951179771Sdavidch fw.start_addr = bce_TXP_b09FwStartAddr; 3952157642Sps 3953179771Sdavidch fw.text_addr = bce_TXP_b09FwTextAddr; 3954179771Sdavidch fw.text_len = bce_TXP_b09FwTextLen; 3955179771Sdavidch fw.text_index = 0; 3956179771Sdavidch fw.text = bce_TXP_b09FwText; 3957157642Sps 3958179771Sdavidch fw.data_addr = bce_TXP_b09FwDataAddr; 3959179771Sdavidch fw.data_len = bce_TXP_b09FwDataLen; 3960179771Sdavidch fw.data_index = 0; 3961179771Sdavidch fw.data = bce_TXP_b09FwData; 3962157642Sps 3963179771Sdavidch fw.sbss_addr = bce_TXP_b09FwSbssAddr; 3964179771Sdavidch fw.sbss_len = bce_TXP_b09FwSbssLen; 3965179771Sdavidch fw.sbss_index = 0; 3966179771Sdavidch fw.sbss = bce_TXP_b09FwSbss; 3967157642Sps 3968179771Sdavidch fw.bss_addr = bce_TXP_b09FwBssAddr; 3969179771Sdavidch fw.bss_len = bce_TXP_b09FwBssLen; 3970179771Sdavidch fw.bss_index = 0; 3971179771Sdavidch fw.bss = bce_TXP_b09FwBss; 3972157642Sps 3973179771Sdavidch fw.rodata_addr = bce_TXP_b09FwRodataAddr; 3974179771Sdavidch fw.rodata_len = bce_TXP_b09FwRodataLen; 3975179771Sdavidch fw.rodata_index = 0; 3976179771Sdavidch fw.rodata = bce_TXP_b09FwRodata; 3977179771Sdavidch } else { 3978179771Sdavidch fw.ver_major = bce_TXP_b06FwReleaseMajor; 3979179771Sdavidch fw.ver_minor = bce_TXP_b06FwReleaseMinor; 3980179771Sdavidch fw.ver_fix = bce_TXP_b06FwReleaseFix; 3981179771Sdavidch fw.start_addr = bce_TXP_b06FwStartAddr; 3982157642Sps 3983179771Sdavidch fw.text_addr = bce_TXP_b06FwTextAddr; 3984179771Sdavidch fw.text_len = bce_TXP_b06FwTextLen; 3985179771Sdavidch fw.text_index = 0; 3986179771Sdavidch fw.text = bce_TXP_b06FwText; 3987179771Sdavidch 3988179771Sdavidch fw.data_addr = bce_TXP_b06FwDataAddr; 3989179771Sdavidch fw.data_len = bce_TXP_b06FwDataLen; 3990179771Sdavidch fw.data_index = 0; 3991179771Sdavidch fw.data = bce_TXP_b06FwData; 3992179771Sdavidch 3993179771Sdavidch fw.sbss_addr = bce_TXP_b06FwSbssAddr; 3994179771Sdavidch fw.sbss_len = bce_TXP_b06FwSbssLen; 3995179771Sdavidch fw.sbss_index = 0; 3996179771Sdavidch fw.sbss = bce_TXP_b06FwSbss; 3997179771Sdavidch 3998179771Sdavidch fw.bss_addr = bce_TXP_b06FwBssAddr; 3999179771Sdavidch fw.bss_len = bce_TXP_b06FwBssLen; 4000179771Sdavidch fw.bss_index = 0; 4001179771Sdavidch fw.bss = bce_TXP_b06FwBss; 4002179771Sdavidch 4003179771Sdavidch fw.rodata_addr = bce_TXP_b06FwRodataAddr; 4004179771Sdavidch fw.rodata_len = bce_TXP_b06FwRodataLen; 4005179771Sdavidch fw.rodata_index = 0; 4006179771Sdavidch fw.rodata = bce_TXP_b06FwRodata; 4007179771Sdavidch } 4008179771Sdavidch 4009157642Sps DBPRINT(sc, BCE_INFO_RESET, "Loading TX firmware.\n"); 4010157642Sps bce_load_cpu_fw(sc, &cpu_reg, &fw); 4011202717Sdavidch bce_start_cpu(sc, &cpu_reg); 4012157642Sps 4013179771Sdavidch DBEXIT(BCE_VERBOSE_RESET); 4014179771Sdavidch} 4015179771Sdavidch 4016179771Sdavidch 4017179771Sdavidch/****************************************************************************/ 4018179771Sdavidch/* Initialize the TPAT CPU. */ 4019179771Sdavidch/* */ 4020179771Sdavidch/* Returns: */ 4021179771Sdavidch/* Nothing. */ 4022179771Sdavidch/****************************************************************************/ 4023179771Sdavidchstatic void 4024179771Sdavidchbce_init_tpat_cpu(struct bce_softc *sc) 4025179771Sdavidch{ 4026179771Sdavidch struct cpu_reg cpu_reg; 4027179771Sdavidch struct fw_info fw; 4028179771Sdavidch 4029179771Sdavidch DBENTER(BCE_VERBOSE_RESET); 4030179771Sdavidch 4031157642Sps cpu_reg.mode = BCE_TPAT_CPU_MODE; 4032157642Sps cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT; 4033157642Sps cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA; 4034157642Sps cpu_reg.state = BCE_TPAT_CPU_STATE; 4035157642Sps cpu_reg.state_value_clear = 0xffffff; 4036157642Sps cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE; 4037157642Sps cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK; 4038157642Sps cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER; 4039157642Sps cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION; 4040157642Sps cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT; 4041157642Sps cpu_reg.spad_base = BCE_TPAT_SCRATCH; 4042157642Sps cpu_reg.mips_view_base = 0x8000000; 4043157642Sps 4044182293Sdavidch if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 4045182293Sdavidch (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 4046179771Sdavidch fw.ver_major = bce_TPAT_b09FwReleaseMajor; 4047179771Sdavidch fw.ver_minor = bce_TPAT_b09FwReleaseMinor; 4048179771Sdavidch fw.ver_fix = bce_TPAT_b09FwReleaseFix; 4049179771Sdavidch fw.start_addr = bce_TPAT_b09FwStartAddr; 4050157642Sps 4051179771Sdavidch fw.text_addr = bce_TPAT_b09FwTextAddr; 4052179771Sdavidch fw.text_len = bce_TPAT_b09FwTextLen; 4053179771Sdavidch fw.text_index = 0; 4054179771Sdavidch fw.text = bce_TPAT_b09FwText; 4055157642Sps 4056179771Sdavidch fw.data_addr = bce_TPAT_b09FwDataAddr; 4057179771Sdavidch fw.data_len = bce_TPAT_b09FwDataLen; 4058179771Sdavidch fw.data_index = 0; 4059179771Sdavidch fw.data = bce_TPAT_b09FwData; 4060157642Sps 4061179771Sdavidch fw.sbss_addr = bce_TPAT_b09FwSbssAddr; 4062179771Sdavidch fw.sbss_len = bce_TPAT_b09FwSbssLen; 4063179771Sdavidch fw.sbss_index = 0; 4064179771Sdavidch fw.sbss = bce_TPAT_b09FwSbss; 4065157642Sps 4066179771Sdavidch fw.bss_addr = bce_TPAT_b09FwBssAddr; 4067179771Sdavidch fw.bss_len = bce_TPAT_b09FwBssLen; 4068179771Sdavidch fw.bss_index = 0; 4069179771Sdavidch fw.bss = bce_TPAT_b09FwBss; 4070157642Sps 4071179771Sdavidch fw.rodata_addr = bce_TPAT_b09FwRodataAddr; 4072179771Sdavidch fw.rodata_len = bce_TPAT_b09FwRodataLen; 4073179771Sdavidch fw.rodata_index = 0; 4074179771Sdavidch fw.rodata = bce_TPAT_b09FwRodata; 4075179771Sdavidch } else { 4076179771Sdavidch fw.ver_major = bce_TPAT_b06FwReleaseMajor; 4077179771Sdavidch fw.ver_minor = bce_TPAT_b06FwReleaseMinor; 4078179771Sdavidch fw.ver_fix = bce_TPAT_b06FwReleaseFix; 4079179771Sdavidch fw.start_addr = bce_TPAT_b06FwStartAddr; 4080157642Sps 4081179771Sdavidch fw.text_addr = bce_TPAT_b06FwTextAddr; 4082179771Sdavidch fw.text_len = bce_TPAT_b06FwTextLen; 4083179771Sdavidch fw.text_index = 0; 4084179771Sdavidch fw.text = bce_TPAT_b06FwText; 4085157642Sps 4086179771Sdavidch fw.data_addr = bce_TPAT_b06FwDataAddr; 4087179771Sdavidch fw.data_len = bce_TPAT_b06FwDataLen; 4088179771Sdavidch fw.data_index = 0; 4089179771Sdavidch fw.data = bce_TPAT_b06FwData; 4090157642Sps 4091179771Sdavidch fw.sbss_addr = bce_TPAT_b06FwSbssAddr; 4092179771Sdavidch fw.sbss_len = bce_TPAT_b06FwSbssLen; 4093179771Sdavidch fw.sbss_index = 0; 4094179771Sdavidch fw.sbss = bce_TPAT_b06FwSbss; 4095157642Sps 4096179771Sdavidch fw.bss_addr = bce_TPAT_b06FwBssAddr; 4097179771Sdavidch fw.bss_len = bce_TPAT_b06FwBssLen; 4098179771Sdavidch fw.bss_index = 0; 4099179771Sdavidch fw.bss = bce_TPAT_b06FwBss; 4100157642Sps 4101179771Sdavidch fw.rodata_addr = bce_TPAT_b06FwRodataAddr; 4102179771Sdavidch fw.rodata_len = bce_TPAT_b06FwRodataLen; 4103179771Sdavidch fw.rodata_index = 0; 4104179771Sdavidch fw.rodata = bce_TPAT_b06FwRodata; 4105179771Sdavidch } 4106157642Sps 4107179771Sdavidch DBPRINT(sc, BCE_INFO_RESET, "Loading TPAT firmware.\n"); 4108179771Sdavidch bce_load_cpu_fw(sc, &cpu_reg, &fw); 4109202717Sdavidch bce_start_cpu(sc, &cpu_reg); 4110157642Sps 4111179771Sdavidch DBEXIT(BCE_VERBOSE_RESET); 4112179771Sdavidch} 4113157642Sps 4114157642Sps 4115179771Sdavidch/****************************************************************************/ 4116179771Sdavidch/* Initialize the CP CPU. */ 4117179771Sdavidch/* */ 4118179771Sdavidch/* Returns: */ 4119179771Sdavidch/* Nothing. */ 4120179771Sdavidch/****************************************************************************/ 4121179771Sdavidchstatic void 4122179771Sdavidchbce_init_cp_cpu(struct bce_softc *sc) 4123179771Sdavidch{ 4124179771Sdavidch struct cpu_reg cpu_reg; 4125179771Sdavidch struct fw_info fw; 4126176448Sdavidch 4127179771Sdavidch DBENTER(BCE_VERBOSE_RESET); 4128179771Sdavidch 4129176448Sdavidch cpu_reg.mode = BCE_CP_CPU_MODE; 4130176448Sdavidch cpu_reg.mode_value_halt = BCE_CP_CPU_MODE_SOFT_HALT; 4131176448Sdavidch cpu_reg.mode_value_sstep = BCE_CP_CPU_MODE_STEP_ENA; 4132176448Sdavidch cpu_reg.state = BCE_CP_CPU_STATE; 4133176448Sdavidch cpu_reg.state_value_clear = 0xffffff; 4134176448Sdavidch cpu_reg.gpr0 = BCE_CP_CPU_REG_FILE; 4135176448Sdavidch cpu_reg.evmask = BCE_CP_CPU_EVENT_MASK; 4136176448Sdavidch cpu_reg.pc = BCE_CP_CPU_PROGRAM_COUNTER; 4137176448Sdavidch cpu_reg.inst = BCE_CP_CPU_INSTRUCTION; 4138176448Sdavidch cpu_reg.bp = BCE_CP_CPU_HW_BREAKPOINT; 4139176448Sdavidch cpu_reg.spad_base = BCE_CP_SCRATCH; 4140176448Sdavidch cpu_reg.mips_view_base = 0x8000000; 4141176448Sdavidch 4142182293Sdavidch if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 4143182293Sdavidch (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 4144179771Sdavidch fw.ver_major = bce_CP_b09FwReleaseMajor; 4145179771Sdavidch fw.ver_minor = bce_CP_b09FwReleaseMinor; 4146179771Sdavidch fw.ver_fix = bce_CP_b09FwReleaseFix; 4147179771Sdavidch fw.start_addr = bce_CP_b09FwStartAddr; 4148176448Sdavidch 4149179771Sdavidch fw.text_addr = bce_CP_b09FwTextAddr; 4150179771Sdavidch fw.text_len = bce_CP_b09FwTextLen; 4151179771Sdavidch fw.text_index = 0; 4152179771Sdavidch fw.text = bce_CP_b09FwText; 4153176448Sdavidch 4154179771Sdavidch fw.data_addr = bce_CP_b09FwDataAddr; 4155179771Sdavidch fw.data_len = bce_CP_b09FwDataLen; 4156179771Sdavidch fw.data_index = 0; 4157179771Sdavidch fw.data = bce_CP_b09FwData; 4158176448Sdavidch 4159179771Sdavidch fw.sbss_addr = bce_CP_b09FwSbssAddr; 4160179771Sdavidch fw.sbss_len = bce_CP_b09FwSbssLen; 4161179771Sdavidch fw.sbss_index = 0; 4162179771Sdavidch fw.sbss = bce_CP_b09FwSbss; 4163176448Sdavidch 4164179771Sdavidch fw.bss_addr = bce_CP_b09FwBssAddr; 4165179771Sdavidch fw.bss_len = bce_CP_b09FwBssLen; 4166179771Sdavidch fw.bss_index = 0; 4167179771Sdavidch fw.bss = bce_CP_b09FwBss; 4168176448Sdavidch 4169179771Sdavidch fw.rodata_addr = bce_CP_b09FwRodataAddr; 4170179771Sdavidch fw.rodata_len = bce_CP_b09FwRodataLen; 4171179771Sdavidch fw.rodata_index = 0; 4172179771Sdavidch fw.rodata = bce_CP_b09FwRodata; 4173179771Sdavidch } else { 4174179771Sdavidch fw.ver_major = bce_CP_b06FwReleaseMajor; 4175179771Sdavidch fw.ver_minor = bce_CP_b06FwReleaseMinor; 4176179771Sdavidch fw.ver_fix = bce_CP_b06FwReleaseFix; 4177179771Sdavidch fw.start_addr = bce_CP_b06FwStartAddr; 4178176448Sdavidch 4179179771Sdavidch fw.text_addr = bce_CP_b06FwTextAddr; 4180179771Sdavidch fw.text_len = bce_CP_b06FwTextLen; 4181179771Sdavidch fw.text_index = 0; 4182179771Sdavidch fw.text = bce_CP_b06FwText; 4183179771Sdavidch 4184179771Sdavidch fw.data_addr = bce_CP_b06FwDataAddr; 4185179771Sdavidch fw.data_len = bce_CP_b06FwDataLen; 4186179771Sdavidch fw.data_index = 0; 4187179771Sdavidch fw.data = bce_CP_b06FwData; 4188179771Sdavidch 4189179771Sdavidch fw.sbss_addr = bce_CP_b06FwSbssAddr; 4190179771Sdavidch fw.sbss_len = bce_CP_b06FwSbssLen; 4191179771Sdavidch fw.sbss_index = 0; 4192179771Sdavidch fw.sbss = bce_CP_b06FwSbss; 4193179771Sdavidch 4194179771Sdavidch fw.bss_addr = bce_CP_b06FwBssAddr; 4195179771Sdavidch fw.bss_len = bce_CP_b06FwBssLen; 4196179771Sdavidch fw.bss_index = 0; 4197179771Sdavidch fw.bss = bce_CP_b06FwBss; 4198179771Sdavidch 4199179771Sdavidch fw.rodata_addr = bce_CP_b06FwRodataAddr; 4200179771Sdavidch fw.rodata_len = bce_CP_b06FwRodataLen; 4201179771Sdavidch fw.rodata_index = 0; 4202179771Sdavidch fw.rodata = bce_CP_b06FwRodata; 4203179771Sdavidch } 4204179771Sdavidch 4205176448Sdavidch DBPRINT(sc, BCE_INFO_RESET, "Loading CP firmware.\n"); 4206176448Sdavidch bce_load_cpu_fw(sc, &cpu_reg, &fw); 4207202717Sdavidch bce_start_cpu(sc, &cpu_reg); 4208179771Sdavidch 4209179771Sdavidch DBEXIT(BCE_VERBOSE_RESET); 4210157642Sps} 4211157642Sps 4212157642Sps 4213157642Sps/****************************************************************************/ 4214179771Sdavidch/* Initialize the COM CPU. */ 4215179771Sdavidch/* */ 4216179771Sdavidch/* Returns: */ 4217179771Sdavidch/* Nothing. */ 4218179771Sdavidch/****************************************************************************/ 4219179771Sdavidchstatic void 4220179771Sdavidchbce_init_com_cpu(struct bce_softc *sc) 4221179771Sdavidch{ 4222179771Sdavidch struct cpu_reg cpu_reg; 4223179771Sdavidch struct fw_info fw; 4224179771Sdavidch 4225179771Sdavidch DBENTER(BCE_VERBOSE_RESET); 4226179771Sdavidch 4227179771Sdavidch cpu_reg.mode = BCE_COM_CPU_MODE; 4228179771Sdavidch cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT; 4229179771Sdavidch cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA; 4230179771Sdavidch cpu_reg.state = BCE_COM_CPU_STATE; 4231179771Sdavidch cpu_reg.state_value_clear = 0xffffff; 4232179771Sdavidch cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE; 4233179771Sdavidch cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK; 4234179771Sdavidch cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER; 4235179771Sdavidch cpu_reg.inst = BCE_COM_CPU_INSTRUCTION; 4236179771Sdavidch cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT; 4237179771Sdavidch cpu_reg.spad_base = BCE_COM_SCRATCH; 4238179771Sdavidch cpu_reg.mips_view_base = 0x8000000; 4239179771Sdavidch 4240182293Sdavidch if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 4241182293Sdavidch (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 4242179771Sdavidch fw.ver_major = bce_COM_b09FwReleaseMajor; 4243179771Sdavidch fw.ver_minor = bce_COM_b09FwReleaseMinor; 4244179771Sdavidch fw.ver_fix = bce_COM_b09FwReleaseFix; 4245179771Sdavidch fw.start_addr = bce_COM_b09FwStartAddr; 4246179771Sdavidch 4247179771Sdavidch fw.text_addr = bce_COM_b09FwTextAddr; 4248179771Sdavidch fw.text_len = bce_COM_b09FwTextLen; 4249179771Sdavidch fw.text_index = 0; 4250179771Sdavidch fw.text = bce_COM_b09FwText; 4251179771Sdavidch 4252179771Sdavidch fw.data_addr = bce_COM_b09FwDataAddr; 4253179771Sdavidch fw.data_len = bce_COM_b09FwDataLen; 4254179771Sdavidch fw.data_index = 0; 4255179771Sdavidch fw.data = bce_COM_b09FwData; 4256179771Sdavidch 4257179771Sdavidch fw.sbss_addr = bce_COM_b09FwSbssAddr; 4258179771Sdavidch fw.sbss_len = bce_COM_b09FwSbssLen; 4259179771Sdavidch fw.sbss_index = 0; 4260179771Sdavidch fw.sbss = bce_COM_b09FwSbss; 4261179771Sdavidch 4262179771Sdavidch fw.bss_addr = bce_COM_b09FwBssAddr; 4263179771Sdavidch fw.bss_len = bce_COM_b09FwBssLen; 4264179771Sdavidch fw.bss_index = 0; 4265179771Sdavidch fw.bss = bce_COM_b09FwBss; 4266179771Sdavidch 4267179771Sdavidch fw.rodata_addr = bce_COM_b09FwRodataAddr; 4268179771Sdavidch fw.rodata_len = bce_COM_b09FwRodataLen; 4269179771Sdavidch fw.rodata_index = 0; 4270179771Sdavidch fw.rodata = bce_COM_b09FwRodata; 4271179771Sdavidch } else { 4272179771Sdavidch fw.ver_major = bce_COM_b06FwReleaseMajor; 4273179771Sdavidch fw.ver_minor = bce_COM_b06FwReleaseMinor; 4274179771Sdavidch fw.ver_fix = bce_COM_b06FwReleaseFix; 4275179771Sdavidch fw.start_addr = bce_COM_b06FwStartAddr; 4276179771Sdavidch 4277179771Sdavidch fw.text_addr = bce_COM_b06FwTextAddr; 4278179771Sdavidch fw.text_len = bce_COM_b06FwTextLen; 4279179771Sdavidch fw.text_index = 0; 4280179771Sdavidch fw.text = bce_COM_b06FwText; 4281179771Sdavidch 4282179771Sdavidch fw.data_addr = bce_COM_b06FwDataAddr; 4283179771Sdavidch fw.data_len = bce_COM_b06FwDataLen; 4284179771Sdavidch fw.data_index = 0; 4285179771Sdavidch fw.data = bce_COM_b06FwData; 4286179771Sdavidch 4287179771Sdavidch fw.sbss_addr = bce_COM_b06FwSbssAddr; 4288179771Sdavidch fw.sbss_len = bce_COM_b06FwSbssLen; 4289179771Sdavidch fw.sbss_index = 0; 4290179771Sdavidch fw.sbss = bce_COM_b06FwSbss; 4291179771Sdavidch 4292179771Sdavidch fw.bss_addr = bce_COM_b06FwBssAddr; 4293179771Sdavidch fw.bss_len = bce_COM_b06FwBssLen; 4294179771Sdavidch fw.bss_index = 0; 4295179771Sdavidch fw.bss = bce_COM_b06FwBss; 4296179771Sdavidch 4297179771Sdavidch fw.rodata_addr = bce_COM_b06FwRodataAddr; 4298179771Sdavidch fw.rodata_len = bce_COM_b06FwRodataLen; 4299179771Sdavidch fw.rodata_index = 0; 4300179771Sdavidch fw.rodata = bce_COM_b06FwRodata; 4301179771Sdavidch } 4302179771Sdavidch 4303179771Sdavidch DBPRINT(sc, BCE_INFO_RESET, "Loading COM firmware.\n"); 4304179771Sdavidch bce_load_cpu_fw(sc, &cpu_reg, &fw); 4305202717Sdavidch bce_start_cpu(sc, &cpu_reg); 4306179771Sdavidch 4307179771Sdavidch DBEXIT(BCE_VERBOSE_RESET); 4308179771Sdavidch} 4309179771Sdavidch 4310179771Sdavidch 4311179771Sdavidch/****************************************************************************/ 4312179771Sdavidch/* Initialize the RV2P, RX, TX, TPAT, COM, and CP CPUs. */ 4313179771Sdavidch/* */ 4314179771Sdavidch/* Loads the firmware for each CPU and starts the CPU. */ 4315179771Sdavidch/* */ 4316179771Sdavidch/* Returns: */ 4317179771Sdavidch/* Nothing. */ 4318179771Sdavidch/****************************************************************************/ 4319179771Sdavidchstatic void 4320179771Sdavidchbce_init_cpus(struct bce_softc *sc) 4321179771Sdavidch{ 4322179771Sdavidch DBENTER(BCE_VERBOSE_RESET); 4323179771Sdavidch 4324182293Sdavidch if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 4325182293Sdavidch (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 4326189325Sdavidch 4327189325Sdavidch if ((BCE_CHIP_REV(sc) == BCE_CHIP_REV_Ax)) { 4328189325Sdavidch bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc1, 4329189325Sdavidch sizeof(bce_xi90_rv2p_proc1), RV2P_PROC1); 4330189325Sdavidch bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc2, 4331189325Sdavidch sizeof(bce_xi90_rv2p_proc2), RV2P_PROC2); 4332189325Sdavidch } else { 4333189325Sdavidch bce_load_rv2p_fw(sc, bce_xi_rv2p_proc1, 4334189325Sdavidch sizeof(bce_xi_rv2p_proc1), RV2P_PROC1); 4335189325Sdavidch bce_load_rv2p_fw(sc, bce_xi_rv2p_proc2, 4336189325Sdavidch sizeof(bce_xi_rv2p_proc2), RV2P_PROC2); 4337189325Sdavidch } 4338189325Sdavidch 4339179771Sdavidch } else { 4340189325Sdavidch bce_load_rv2p_fw(sc, bce_rv2p_proc1, 4341189325Sdavidch sizeof(bce_rv2p_proc1), RV2P_PROC1); 4342189325Sdavidch bce_load_rv2p_fw(sc, bce_rv2p_proc2, 4343189325Sdavidch sizeof(bce_rv2p_proc2), RV2P_PROC2); 4344179771Sdavidch } 4345179771Sdavidch 4346179771Sdavidch bce_init_rxp_cpu(sc); 4347179771Sdavidch bce_init_txp_cpu(sc); 4348179771Sdavidch bce_init_tpat_cpu(sc); 4349179771Sdavidch bce_init_com_cpu(sc); 4350179771Sdavidch bce_init_cp_cpu(sc); 4351179771Sdavidch 4352179771Sdavidch DBEXIT(BCE_VERBOSE_RESET); 4353179771Sdavidch} 4354179771Sdavidch 4355179771Sdavidch 4356179771Sdavidch/****************************************************************************/ 4357157642Sps/* Initialize context memory. */ 4358157642Sps/* */ 4359157642Sps/* Clears the memory associated with each Context ID (CID). */ 4360157642Sps/* */ 4361157642Sps/* Returns: */ 4362157642Sps/* Nothing. */ 4363157642Sps/****************************************************************************/ 4364157642Spsstatic void 4365176448Sdavidchbce_init_ctx(struct bce_softc *sc) 4366157642Sps{ 4367157642Sps 4368179771Sdavidch DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 4369157642Sps 4370182293Sdavidch if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 4371182293Sdavidch (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 4372191923Sdavidch int i, retry_cnt = CTX_INIT_RETRY_COUNT; 4373179771Sdavidch u32 val; 4374157642Sps 4375179771Sdavidch DBPRINT(sc, BCE_INFO_CTX, "Initializing 5709 context.\n"); 4376157642Sps 4377179771Sdavidch /* 4378179771Sdavidch * BCM5709 context memory may be cached 4379179771Sdavidch * in host memory so prepare the host memory 4380179771Sdavidch * for access. 4381179771Sdavidch */ 4382179771Sdavidch val = BCE_CTX_COMMAND_ENABLED | BCE_CTX_COMMAND_MEM_INIT | (1 << 12); 4383179771Sdavidch val |= (BCM_PAGE_BITS - 8) << 16; 4384179771Sdavidch REG_WR(sc, BCE_CTX_COMMAND, val); 4385157642Sps 4386179771Sdavidch /* Wait for mem init command to complete. */ 4387179771Sdavidch for (i = 0; i < retry_cnt; i++) { 4388179771Sdavidch val = REG_RD(sc, BCE_CTX_COMMAND); 4389179771Sdavidch if (!(val & BCE_CTX_COMMAND_MEM_INIT)) 4390179771Sdavidch break; 4391179771Sdavidch DELAY(2); 4392179771Sdavidch } 4393182293Sdavidch 4394179771Sdavidch /* ToDo: Consider returning an error here. */ 4395179771Sdavidch DBRUNIF((val & BCE_CTX_COMMAND_MEM_INIT), 4396179771Sdavidch BCE_PRINTF("%s(): Context memory initialization failed!\n", 4397179771Sdavidch __FUNCTION__)); 4398179771Sdavidch 4399179771Sdavidch for (i = 0; i < sc->ctx_pages; i++) { 4400179771Sdavidch int j; 4401179771Sdavidch 4402179771Sdavidch /* Set the physical address of the context memory cache. */ 4403179771Sdavidch REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA0, 4404182293Sdavidch BCE_ADDR_LO(sc->ctx_paddr[i] & 0xfffffff0) | 4405179771Sdavidch BCE_CTX_HOST_PAGE_TBL_DATA0_VALID); 4406179771Sdavidch REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA1, 4407179771Sdavidch BCE_ADDR_HI(sc->ctx_paddr[i])); 4408179771Sdavidch REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_CTRL, i | 4409179771Sdavidch BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ); 4410179771Sdavidch 4411179771Sdavidch /* Verify that the context memory write was successful. */ 4412179771Sdavidch for (j = 0; j < retry_cnt; j++) { 4413179771Sdavidch val = REG_RD(sc, BCE_CTX_HOST_PAGE_TBL_CTRL); 4414179771Sdavidch if ((val & BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0) 4415179771Sdavidch break; 4416179771Sdavidch DELAY(5); 4417179771Sdavidch } 4418179771Sdavidch 4419179771Sdavidch /* ToDo: Consider returning an error here. */ 4420179771Sdavidch DBRUNIF((val & BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ), 4421182293Sdavidch BCE_PRINTF("%s(): Failed to initialize context page %d!\n", 4422179771Sdavidch __FUNCTION__, i)); 4423179771Sdavidch } 4424179771Sdavidch } else { 4425179771Sdavidch u32 vcid_addr, offset; 4426179771Sdavidch 4427179771Sdavidch DBPRINT(sc, BCE_INFO, "Initializing 5706/5708 context.\n"); 4428179771Sdavidch 4429179771Sdavidch /* 4430179771Sdavidch * For the 5706/5708, context memory is local to 4431179771Sdavidch * the controller, so initialize the controller 4432179771Sdavidch * context memory. 4433179771Sdavidch */ 4434179771Sdavidch 4435179771Sdavidch vcid_addr = GET_CID_ADDR(96); 4436179771Sdavidch while (vcid_addr) { 4437179771Sdavidch 4438179771Sdavidch vcid_addr -= PHY_CTX_SIZE; 4439179771Sdavidch 4440179771Sdavidch REG_WR(sc, BCE_CTX_VIRT_ADDR, 0); 4441179771Sdavidch REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr); 4442179771Sdavidch 4443179771Sdavidch for(offset = 0; offset < PHY_CTX_SIZE; offset += 4) { 4444179771Sdavidch CTX_WR(sc, 0x00, offset, 0); 4445179771Sdavidch } 4446179771Sdavidch 4447176448Sdavidch REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr); 4448179771Sdavidch REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr); 4449179771Sdavidch } 4450176448Sdavidch 4451157642Sps } 4452179771Sdavidch DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 4453157642Sps} 4454157642Sps 4455182293Sdavidch 4456157642Sps/****************************************************************************/ 4457157642Sps/* Fetch the permanent MAC address of the controller. */ 4458157642Sps/* */ 4459157642Sps/* Returns: */ 4460157642Sps/* Nothing. */ 4461157642Sps/****************************************************************************/ 4462157642Spsstatic void 4463157642Spsbce_get_mac_addr(struct bce_softc *sc) 4464157642Sps{ 4465157642Sps u32 mac_lo = 0, mac_hi = 0; 4466157642Sps 4467179771Sdavidch DBENTER(BCE_VERBOSE_RESET); 4468157642Sps /* 4469157642Sps * The NetXtreme II bootcode populates various NIC 4470157642Sps * power-on and runtime configuration items in a 4471157642Sps * shared memory area. The factory configured MAC 4472157642Sps * address is available from both NVRAM and the 4473157642Sps * shared memory area so we'll read the value from 4474157642Sps * shared memory for speed. 4475157642Sps */ 4476157642Sps 4477194781Sdavidch mac_hi = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_UPPER); 4478194781Sdavidch mac_lo = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_LOWER); 4479157642Sps 4480157642Sps if ((mac_lo == 0) && (mac_hi == 0)) { 4481179771Sdavidch BCE_PRINTF("%s(%d): Invalid Ethernet address!\n", 4482157642Sps __FILE__, __LINE__); 4483157642Sps } else { 4484157642Sps sc->eaddr[0] = (u_char)(mac_hi >> 8); 4485157642Sps sc->eaddr[1] = (u_char)(mac_hi >> 0); 4486157642Sps sc->eaddr[2] = (u_char)(mac_lo >> 24); 4487157642Sps sc->eaddr[3] = (u_char)(mac_lo >> 16); 4488157642Sps sc->eaddr[4] = (u_char)(mac_lo >> 8); 4489157642Sps sc->eaddr[5] = (u_char)(mac_lo >> 0); 4490157642Sps } 4491157642Sps 4492170810Sdavidch DBPRINT(sc, BCE_INFO_MISC, "Permanent Ethernet address = %6D\n", sc->eaddr, ":"); 4493179771Sdavidch DBEXIT(BCE_VERBOSE_RESET); 4494157642Sps} 4495157642Sps 4496157642Sps 4497157642Sps/****************************************************************************/ 4498157642Sps/* Program the MAC address. */ 4499157642Sps/* */ 4500157642Sps/* Returns: */ 4501157642Sps/* Nothing. */ 4502157642Sps/****************************************************************************/ 4503157642Spsstatic void 4504157642Spsbce_set_mac_addr(struct bce_softc *sc) 4505157642Sps{ 4506157642Sps u32 val; 4507157642Sps u8 *mac_addr = sc->eaddr; 4508157642Sps 4509179771Sdavidch /* ToDo: Add support for setting multiple MAC addresses. */ 4510179771Sdavidch 4511179771Sdavidch DBENTER(BCE_VERBOSE_RESET); 4512170810Sdavidch DBPRINT(sc, BCE_INFO_MISC, "Setting Ethernet address = %6D\n", sc->eaddr, ":"); 4513157642Sps 4514157642Sps val = (mac_addr[0] << 8) | mac_addr[1]; 4515157642Sps 4516157642Sps REG_WR(sc, BCE_EMAC_MAC_MATCH0, val); 4517157642Sps 4518157642Sps val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 4519157642Sps (mac_addr[4] << 8) | mac_addr[5]; 4520157642Sps 4521157642Sps REG_WR(sc, BCE_EMAC_MAC_MATCH1, val); 4522179771Sdavidch 4523179771Sdavidch DBEXIT(BCE_VERBOSE_RESET); 4524157642Sps} 4525157642Sps 4526157642Sps 4527157642Sps/****************************************************************************/ 4528157642Sps/* Stop the controller. */ 4529157642Sps/* */ 4530157642Sps/* Returns: */ 4531157642Sps/* Nothing. */ 4532157642Sps/****************************************************************************/ 4533157642Spsstatic void 4534157642Spsbce_stop(struct bce_softc *sc) 4535157642Sps{ 4536157642Sps struct ifnet *ifp; 4537157642Sps struct ifmedia_entry *ifm; 4538157642Sps struct mii_data *mii = NULL; 4539157642Sps int mtmp, itmp; 4540157642Sps 4541179771Sdavidch DBENTER(BCE_VERBOSE_RESET); 4542157642Sps 4543157642Sps BCE_LOCK_ASSERT(sc); 4544157642Sps 4545157642Sps ifp = sc->bce_ifp; 4546157642Sps 4547157642Sps mii = device_get_softc(sc->bce_miibus); 4548157642Sps 4549170810Sdavidch callout_stop(&sc->bce_tick_callout); 4550157642Sps 4551157642Sps /* Disable the transmit/receive blocks. */ 4552179771Sdavidch REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, BCE_MISC_ENABLE_CLR_DEFAULT); 4553157642Sps REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS); 4554157642Sps DELAY(20); 4555157642Sps 4556157642Sps bce_disable_intr(sc); 4557157642Sps 4558171667Sdavidch /* Free RX buffers. */ 4559198320Sstas#ifdef BCE_JUMBO_HDRSPLIT 4560179771Sdavidch bce_free_pg_chain(sc); 4561179695Sdavidch#endif 4562157642Sps bce_free_rx_chain(sc); 4563157642Sps 4564157642Sps /* Free TX buffers. */ 4565157642Sps bce_free_tx_chain(sc); 4566157642Sps 4567157642Sps /* 4568157642Sps * Isolate/power down the PHY, but leave the media selection 4569157642Sps * unchanged so that things will be put back to normal when 4570157642Sps * we bring the interface back up. 4571157642Sps */ 4572157642Sps 4573157642Sps itmp = ifp->if_flags; 4574157642Sps ifp->if_flags |= IFF_UP; 4575170810Sdavidch 4576170810Sdavidch /* If we are called from bce_detach(), mii is already NULL. */ 4577157642Sps if (mii != NULL) { 4578157642Sps ifm = mii->mii_media.ifm_cur; 4579157642Sps mtmp = ifm->ifm_media; 4580157642Sps ifm->ifm_media = IFM_ETHER | IFM_NONE; 4581157642Sps mii_mediachg(mii); 4582157642Sps ifm->ifm_media = mtmp; 4583157642Sps } 4584157642Sps 4585157642Sps ifp->if_flags = itmp; 4586165933Sdelphij sc->watchdog_timer = 0; 4587157642Sps 4588157642Sps sc->bce_link = 0; 4589157642Sps 4590157642Sps ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 4591157642Sps 4592179771Sdavidch DBEXIT(BCE_VERBOSE_RESET); 4593157642Sps} 4594157642Sps 4595157642Sps 4596157642Spsstatic int 4597157642Spsbce_reset(struct bce_softc *sc, u32 reset_code) 4598157642Sps{ 4599157642Sps u32 val; 4600157642Sps int i, rc = 0; 4601157642Sps 4602179771Sdavidch DBENTER(BCE_VERBOSE_RESET); 4603179771Sdavidch 4604179771Sdavidch DBPRINT(sc, BCE_VERBOSE_RESET, "%s(): reset_code = 0x%08X\n", 4605170810Sdavidch __FUNCTION__, reset_code); 4606157642Sps 4607157642Sps /* Wait for pending PCI transactions to complete. */ 4608157642Sps REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, 4609157642Sps BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE | 4610157642Sps BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE | 4611157642Sps BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE | 4612157642Sps BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE); 4613157642Sps val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS); 4614157642Sps DELAY(5); 4615157642Sps 4616179771Sdavidch /* Disable DMA */ 4617182293Sdavidch if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 4618182293Sdavidch (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 4619179771Sdavidch val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL); 4620179771Sdavidch val &= ~BCE_MISC_NEW_CORE_CTL_DMA_ENABLE; 4621179771Sdavidch REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val); 4622179771Sdavidch } 4623179771Sdavidch 4624157642Sps /* Assume bootcode is running. */ 4625157642Sps sc->bce_fw_timed_out = 0; 4626157642Sps 4627157642Sps /* Give the firmware a chance to prepare for the reset. */ 4628157642Sps rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT0 | reset_code); 4629157642Sps if (rc) 4630157642Sps goto bce_reset_exit; 4631157642Sps 4632157642Sps /* Set a firmware reminder that this is a soft reset. */ 4633194781Sdavidch bce_shmem_wr(sc, BCE_DRV_RESET_SIGNATURE, BCE_DRV_RESET_SIGNATURE_MAGIC); 4634157642Sps 4635157642Sps /* Dummy read to force the chip to complete all current transactions. */ 4636157642Sps val = REG_RD(sc, BCE_MISC_ID); 4637157642Sps 4638157642Sps /* Chip reset. */ 4639182293Sdavidch if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 4640182293Sdavidch (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 4641179771Sdavidch REG_WR(sc, BCE_MISC_COMMAND, BCE_MISC_COMMAND_SW_RESET); 4642179771Sdavidch REG_RD(sc, BCE_MISC_COMMAND); 4643179771Sdavidch DELAY(5); 4644157642Sps 4645179771Sdavidch val = BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 4646179771Sdavidch BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 4647179771Sdavidch 4648179771Sdavidch pci_write_config(sc->bce_dev, BCE_PCICFG_MISC_CONFIG, val, 4); 4649179771Sdavidch } else { 4650179771Sdavidch val = BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 4651179771Sdavidch BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 4652179771Sdavidch BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 4653179771Sdavidch REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val); 4654179771Sdavidch 4655179771Sdavidch /* Allow up to 30us for reset to complete. */ 4656179771Sdavidch for (i = 0; i < 10; i++) { 4657179771Sdavidch val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG); 4658179771Sdavidch if ((val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 4659179771Sdavidch BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) { 4660179771Sdavidch break; 4661179771Sdavidch } 4662179771Sdavidch DELAY(10); 4663157642Sps } 4664157642Sps 4665179771Sdavidch /* Check that reset completed successfully. */ 4666179771Sdavidch if (val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 4667179771Sdavidch BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) { 4668179771Sdavidch BCE_PRINTF("%s(%d): Reset failed!\n", 4669179771Sdavidch __FILE__, __LINE__); 4670179771Sdavidch rc = EBUSY; 4671179771Sdavidch goto bce_reset_exit; 4672179771Sdavidch } 4673157642Sps } 4674157642Sps 4675157642Sps /* Make sure byte swapping is properly configured. */ 4676157642Sps val = REG_RD(sc, BCE_PCI_SWAP_DIAG0); 4677157642Sps if (val != 0x01020304) { 4678179771Sdavidch BCE_PRINTF("%s(%d): Byte swap is incorrect!\n", 4679157642Sps __FILE__, __LINE__); 4680157642Sps rc = ENODEV; 4681157642Sps goto bce_reset_exit; 4682157642Sps } 4683157642Sps 4684157642Sps /* Just completed a reset, assume that firmware is running again. */ 4685157642Sps sc->bce_fw_timed_out = 0; 4686157642Sps 4687157642Sps /* Wait for the firmware to finish its initialization. */ 4688157642Sps rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT1 | reset_code); 4689157642Sps if (rc) 4690169271Sdavidch BCE_PRINTF("%s(%d): Firmware did not complete initialization!\n", 4691157642Sps __FILE__, __LINE__); 4692157642Sps 4693157642Spsbce_reset_exit: 4694179771Sdavidch DBEXIT(BCE_VERBOSE_RESET); 4695157642Sps return (rc); 4696157642Sps} 4697157642Sps 4698157642Sps 4699157642Spsstatic int 4700157642Spsbce_chipinit(struct bce_softc *sc) 4701157642Sps{ 4702157642Sps u32 val; 4703157642Sps int rc = 0; 4704157642Sps 4705179771Sdavidch DBENTER(BCE_VERBOSE_RESET); 4706157642Sps 4707179771Sdavidch bce_disable_intr(sc); 4708157642Sps 4709179771Sdavidch /* 4710169632Sdavidch * Initialize DMA byte/word swapping, configure the number of DMA 4711170392Sdavidch * channels and PCI clock compensation delay. 4712169632Sdavidch */ 4713157642Sps val = BCE_DMA_CONFIG_DATA_BYTE_SWAP | 4714157642Sps BCE_DMA_CONFIG_DATA_WORD_SWAP | 4715157642Sps#if BYTE_ORDER == BIG_ENDIAN 4716157642Sps BCE_DMA_CONFIG_CNTL_BYTE_SWAP | 4717157642Sps#endif 4718157642Sps BCE_DMA_CONFIG_CNTL_WORD_SWAP | 4719157642Sps DMA_READ_CHANS << 12 | 4720157642Sps DMA_WRITE_CHANS << 16; 4721157642Sps 4722157642Sps val |= (0x2 << 20) | BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY; 4723157642Sps 4724157642Sps if ((sc->bce_flags & BCE_PCIX_FLAG) && (sc->bus_speed_mhz == 133)) 4725157642Sps val |= BCE_DMA_CONFIG_PCI_FAST_CLK_CMP; 4726157642Sps 4727157642Sps /* 4728157642Sps * This setting resolves a problem observed on certain Intel PCI 4729157642Sps * chipsets that cannot handle multiple outstanding DMA operations. 4730157642Sps * See errata E9_5706A1_65. 4731157642Sps */ 4732157642Sps if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) && 4733157642Sps (BCE_CHIP_ID(sc) != BCE_CHIP_ID_5706_A0) && 4734157642Sps !(sc->bce_flags & BCE_PCIX_FLAG)) 4735157642Sps val |= BCE_DMA_CONFIG_CNTL_PING_PONG_DMA; 4736157642Sps 4737157642Sps REG_WR(sc, BCE_DMA_CONFIG, val); 4738157642Sps 4739157642Sps /* Enable the RX_V2P and Context state machines before access. */ 4740157642Sps REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 4741157642Sps BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE | 4742157642Sps BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE | 4743157642Sps BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE); 4744157642Sps 4745157642Sps /* Initialize context mapping and zero out the quick contexts. */ 4746176448Sdavidch bce_init_ctx(sc); 4747157642Sps 4748157642Sps /* Initialize the on-boards CPUs */ 4749157642Sps bce_init_cpus(sc); 4750157642Sps 4751202717Sdavidch /* Enable management frames (NC-SI) to flow to the MCP. */ 4752202717Sdavidch if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 4753202717Sdavidch val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) | BCE_RPM_MGMT_PKT_CTRL_MGMT_EN; 4754202717Sdavidch REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val); 4755202717Sdavidch } 4756202717Sdavidch 4757157642Sps /* Prepare NVRAM for access. */ 4758157642Sps if (bce_init_nvram(sc)) { 4759157642Sps rc = ENODEV; 4760157642Sps goto bce_chipinit_exit; 4761157642Sps } 4762157642Sps 4763157642Sps /* Set the kernel bypass block size */ 4764157642Sps val = REG_RD(sc, BCE_MQ_CONFIG); 4765157642Sps val &= ~BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE; 4766157642Sps val |= BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256; 4767179771Sdavidch 4768182293Sdavidch /* Enable bins used on the 5709. */ 4769182293Sdavidch if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 4770182293Sdavidch (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 4771179771Sdavidch val |= BCE_MQ_CONFIG_BIN_MQ_MODE; 4772179771Sdavidch if (BCE_CHIP_ID(sc) == BCE_CHIP_ID_5709_A1) 4773179771Sdavidch val |= BCE_MQ_CONFIG_HALT_DIS; 4774179771Sdavidch } 4775179771Sdavidch 4776157642Sps REG_WR(sc, BCE_MQ_CONFIG, val); 4777157642Sps 4778157642Sps val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE); 4779157642Sps REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val); 4780157642Sps REG_WR(sc, BCE_MQ_KNL_WIND_END, val); 4781170392Sdavidch 4782169271Sdavidch /* Set the page size and clear the RV2P processor stall bits. */ 4783157642Sps val = (BCM_PAGE_BITS - 8) << 24; 4784157642Sps REG_WR(sc, BCE_RV2P_CONFIG, val); 4785157642Sps 4786157642Sps /* Configure page size. */ 4787157642Sps val = REG_RD(sc, BCE_TBDR_CONFIG); 4788157642Sps val &= ~BCE_TBDR_CONFIG_PAGE_SIZE; 4789157642Sps val |= (BCM_PAGE_BITS - 8) << 24 | 0x40; 4790157642Sps REG_WR(sc, BCE_TBDR_CONFIG, val); 4791157642Sps 4792179771Sdavidch /* Set the perfect match control register to default. */ 4793179771Sdavidch REG_WR_IND(sc, BCE_RXP_PM_CTRL, 0); 4794179771Sdavidch 4795157642Spsbce_chipinit_exit: 4796179771Sdavidch DBEXIT(BCE_VERBOSE_RESET); 4797157642Sps 4798157642Sps return(rc); 4799157642Sps} 4800157642Sps 4801157642Sps 4802157642Sps/****************************************************************************/ 4803157642Sps/* Initialize the controller in preparation to send/receive traffic. */ 4804157642Sps/* */ 4805157642Sps/* Returns: */ 4806157642Sps/* 0 for success, positive value for failure. */ 4807157642Sps/****************************************************************************/ 4808157642Spsstatic int 4809157642Spsbce_blockinit(struct bce_softc *sc) 4810157642Sps{ 4811157642Sps u32 reg, val; 4812157642Sps int rc = 0; 4813157642Sps 4814179771Sdavidch DBENTER(BCE_VERBOSE_RESET); 4815157642Sps 4816157642Sps /* Load the hardware default MAC address. */ 4817157642Sps bce_set_mac_addr(sc); 4818157642Sps 4819157642Sps /* Set the Ethernet backoff seed value */ 4820157642Sps val = sc->eaddr[0] + (sc->eaddr[1] << 8) + 4821157642Sps (sc->eaddr[2] << 16) + (sc->eaddr[3] ) + 4822157642Sps (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16); 4823157642Sps REG_WR(sc, BCE_EMAC_BACKOFF_SEED, val); 4824157642Sps 4825157642Sps sc->last_status_idx = 0; 4826157642Sps sc->rx_mode = BCE_EMAC_RX_MODE_SORT_MODE; 4827157642Sps 4828157642Sps /* Set up link change interrupt generation. */ 4829157642Sps REG_WR(sc, BCE_EMAC_ATTENTION_ENA, BCE_EMAC_ATTENTION_ENA_LINK); 4830157642Sps 4831157642Sps /* Program the physical address of the status block. */ 4832157642Sps REG_WR(sc, BCE_HC_STATUS_ADDR_L, 4833157642Sps BCE_ADDR_LO(sc->status_block_paddr)); 4834157642Sps REG_WR(sc, BCE_HC_STATUS_ADDR_H, 4835157642Sps BCE_ADDR_HI(sc->status_block_paddr)); 4836157642Sps 4837157642Sps /* Program the physical address of the statistics block. */ 4838157642Sps REG_WR(sc, BCE_HC_STATISTICS_ADDR_L, 4839157642Sps BCE_ADDR_LO(sc->stats_block_paddr)); 4840157642Sps REG_WR(sc, BCE_HC_STATISTICS_ADDR_H, 4841157642Sps BCE_ADDR_HI(sc->stats_block_paddr)); 4842157642Sps 4843157642Sps /* Program various host coalescing parameters. */ 4844157642Sps REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP, 4845157642Sps (sc->bce_tx_quick_cons_trip_int << 16) | sc->bce_tx_quick_cons_trip); 4846157642Sps REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP, 4847157642Sps (sc->bce_rx_quick_cons_trip_int << 16) | sc->bce_rx_quick_cons_trip); 4848157642Sps REG_WR(sc, BCE_HC_COMP_PROD_TRIP, 4849157642Sps (sc->bce_comp_prod_trip_int << 16) | sc->bce_comp_prod_trip); 4850157642Sps REG_WR(sc, BCE_HC_TX_TICKS, 4851157642Sps (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks); 4852157642Sps REG_WR(sc, BCE_HC_RX_TICKS, 4853157642Sps (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks); 4854157642Sps REG_WR(sc, BCE_HC_COM_TICKS, 4855157642Sps (sc->bce_com_ticks_int << 16) | sc->bce_com_ticks); 4856157642Sps REG_WR(sc, BCE_HC_CMD_TICKS, 4857157642Sps (sc->bce_cmd_ticks_int << 16) | sc->bce_cmd_ticks); 4858157642Sps REG_WR(sc, BCE_HC_STATS_TICKS, 4859157642Sps (sc->bce_stats_ticks & 0xffff00)); 4860179771Sdavidch REG_WR(sc, BCE_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */ 4861157642Sps 4862179771Sdavidch /* Configure the Host Coalescing block. */ 4863179771Sdavidch val = BCE_HC_CONFIG_RX_TMR_MODE | BCE_HC_CONFIG_TX_TMR_MODE | 4864179771Sdavidch BCE_HC_CONFIG_COLLECT_STATS; 4865179771Sdavidch 4866179771Sdavidch#if 0 4867179771Sdavidch /* ToDo: Add MSI-X support. */ 4868179771Sdavidch if (sc->bce_flags & BCE_USING_MSIX_FLAG) { 4869179771Sdavidch u32 base = ((BCE_TX_VEC - 1) * BCE_HC_SB_CONFIG_SIZE) + 4870179771Sdavidch BCE_HC_SB_CONFIG_1; 4871179771Sdavidch 4872179771Sdavidch REG_WR(sc, BCE_HC_MSIX_BIT_VECTOR, BCE_HC_MSIX_BIT_VECTOR_VAL); 4873179771Sdavidch 4874179771Sdavidch REG_WR(sc, base, BCE_HC_SB_CONFIG_1_TX_TMR_MODE | 4875179771Sdavidch BCE_HC_SB_CONFIG_1_ONE_SHOT); 4876179771Sdavidch 4877179771Sdavidch REG_WR(sc, base + BCE_HC_TX_QUICK_CONS_TRIP_OFF, 4878179771Sdavidch (sc->tx_quick_cons_trip_int << 16) | 4879179771Sdavidch sc->tx_quick_cons_trip); 4880179771Sdavidch 4881179771Sdavidch REG_WR(sc, base + BCE_HC_TX_TICKS_OFF, 4882179771Sdavidch (sc->tx_ticks_int << 16) | sc->tx_ticks); 4883179771Sdavidch 4884179771Sdavidch val |= BCE_HC_CONFIG_SB_ADDR_INC_128B; 4885179771Sdavidch } 4886179771Sdavidch 4887179771Sdavidch /* 4888179771Sdavidch * Tell the HC block to automatically set the 4889179771Sdavidch * INT_MASK bit after an MSI/MSI-X interrupt 4890179771Sdavidch * is generated so the driver doesn't have to. 4891179771Sdavidch */ 4892179771Sdavidch if (sc->bce_flags & BCE_ONE_SHOT_MSI_FLAG) 4893179771Sdavidch val |= BCE_HC_CONFIG_ONE_SHOT; 4894179771Sdavidch 4895179771Sdavidch /* Set the MSI-X status blocks to 128 byte boundaries. */ 4896179771Sdavidch if (sc->bce_flags & BCE_USING_MSIX_FLAG) 4897179771Sdavidch val |= BCE_HC_CONFIG_SB_ADDR_INC_128B; 4898179771Sdavidch#endif 4899179771Sdavidch 4900179771Sdavidch REG_WR(sc, BCE_HC_CONFIG, val); 4901179771Sdavidch 4902157642Sps /* Clear the internal statistics counters. */ 4903157642Sps REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW); 4904157642Sps 4905157642Sps /* Verify that bootcode is running. */ 4906194781Sdavidch reg = bce_shmem_rd(sc, BCE_DEV_INFO_SIGNATURE); 4907157642Sps 4908189325Sdavidch DBRUNIF(DB_RANDOMTRUE(bootcode_running_failure_sim_control), 4909169271Sdavidch BCE_PRINTF("%s(%d): Simulating bootcode failure.\n", 4910157642Sps __FILE__, __LINE__); 4911157642Sps reg = 0); 4912157642Sps 4913157642Sps if ((reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK) != 4914157642Sps BCE_DEV_INFO_SIGNATURE_MAGIC) { 4915169271Sdavidch BCE_PRINTF("%s(%d): Bootcode not running! Found: 0x%08X, " 4916157642Sps "Expected: 08%08X\n", __FILE__, __LINE__, 4917157642Sps (reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK), 4918157642Sps BCE_DEV_INFO_SIGNATURE_MAGIC); 4919157642Sps rc = ENODEV; 4920157642Sps goto bce_blockinit_exit; 4921157642Sps } 4922157642Sps 4923179771Sdavidch /* Enable DMA */ 4924182293Sdavidch if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 4925182293Sdavidch (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 4926179771Sdavidch val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL); 4927179771Sdavidch val |= BCE_MISC_NEW_CORE_CTL_DMA_ENABLE; 4928179771Sdavidch REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val); 4929179771Sdavidch } 4930179771Sdavidch 4931157642Sps /* Allow bootcode to apply any additional fixes before enabling MAC. */ 4932157642Sps rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT2 | BCE_DRV_MSG_CODE_RESET); 4933157642Sps 4934157642Sps /* Enable link state change interrupt generation. */ 4935157642Sps REG_WR(sc, BCE_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE); 4936157642Sps 4937202717Sdavidch /* Enable the RXP. */ 4938202717Sdavidch bce_start_rxp_cpu(sc); 4939202717Sdavidch 4940202717Sdavidch /* Disable management frames (NC-SI) from flowing to the MCP. */ 4941202717Sdavidch if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 4942202717Sdavidch val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) & ~BCE_RPM_MGMT_PKT_CTRL_MGMT_EN; 4943202717Sdavidch REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val); 4944202717Sdavidch } 4945202717Sdavidch 4946157642Sps /* Enable all remaining blocks in the MAC. */ 4947182293Sdavidch if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 4948182293Sdavidch (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) 4949182293Sdavidch REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT_XI); 4950182293Sdavidch else 4951182293Sdavidch REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT); 4952182293Sdavidch 4953157642Sps REG_RD(sc, BCE_MISC_ENABLE_SET_BITS); 4954157642Sps DELAY(20); 4955157642Sps 4956179771Sdavidch /* Save the current host coalescing block settings. */ 4957179771Sdavidch sc->hc_command = REG_RD(sc, BCE_HC_COMMAND); 4958179771Sdavidch 4959157642Spsbce_blockinit_exit: 4960179771Sdavidch DBEXIT(BCE_VERBOSE_RESET); 4961157642Sps 4962157642Sps return (rc); 4963157642Sps} 4964157642Sps 4965157642Sps 4966157642Sps/****************************************************************************/ 4967176448Sdavidch/* Encapsulate an mbuf into the rx_bd chain. */ 4968157642Sps/* */ 4969157642Sps/* Returns: */ 4970157642Sps/* 0 for success, positive value for failure. */ 4971157642Sps/****************************************************************************/ 4972157642Spsstatic int 4973176448Sdavidchbce_get_rx_buf(struct bce_softc *sc, struct mbuf *m, u16 *prod, 4974176448Sdavidch u16 *chain_prod, u32 *prod_bseq) 4975157642Sps{ 4976171667Sdavidch bus_dmamap_t map; 4977171667Sdavidch bus_dma_segment_t segs[BCE_MAX_SEGMENTS]; 4978157642Sps struct mbuf *m_new = NULL; 4979171667Sdavidch struct rx_bd *rxbd; 4980176448Sdavidch int nsegs, error, rc = 0; 4981157642Sps#ifdef BCE_DEBUG 4982157642Sps u16 debug_chain_prod = *chain_prod; 4983157642Sps#endif 4984157642Sps 4985179771Sdavidch DBENTER(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 4986157642Sps 4987157642Sps /* Make sure the inputs are valid. */ 4988157642Sps DBRUNIF((*chain_prod > MAX_RX_BD), 4989169271Sdavidch BCE_PRINTF("%s(%d): RX producer out of range: 0x%04X > 0x%04X\n", 4990157642Sps __FILE__, __LINE__, *chain_prod, (u16) MAX_RX_BD)); 4991157642Sps 4992179771Sdavidch DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): prod = 0x%04X, chain_prod = 0x%04X, " 4993157642Sps "prod_bseq = 0x%08X\n", __FUNCTION__, *prod, *chain_prod, *prod_bseq); 4994157642Sps 4995176448Sdavidch /* Update some debug statistic counters */ 4996179771Sdavidch DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 4997176448Sdavidch sc->rx_low_watermark = sc->free_rx_bd); 4998176448Sdavidch DBRUNIF((sc->free_rx_bd == sc->max_rx_bd), sc->rx_empty_count++); 4999176448Sdavidch 5000171667Sdavidch /* Check whether this is a new mbuf allocation. */ 5001157642Sps if (m == NULL) { 5002157642Sps 5003171667Sdavidch /* Simulate an mbuf allocation failure. */ 5004189325Sdavidch DBRUNIF(DB_RANDOMTRUE(mbuf_alloc_failed_sim_control), 5005189325Sdavidch sc->mbuf_alloc_failed_count++; 5006189325Sdavidch sc->mbuf_alloc_failed_sim_count++; 5007157642Sps rc = ENOBUFS; 5008176448Sdavidch goto bce_get_rx_buf_exit); 5009157642Sps 5010157642Sps /* This is a new mbuf allocation. */ 5011198320Sstas#ifdef BCE_JUMBO_HDRSPLIT 5012157642Sps MGETHDR(m_new, M_DONTWAIT, MT_DATA); 5013178853Sscottl#else 5014179771Sdavidch if (sc->rx_bd_mbuf_alloc_size <= MCLBYTES) 5015179771Sdavidch m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 5016179771Sdavidch else 5017179695Sdavidch m_new = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, sc->rx_bd_mbuf_alloc_size); 5018178853Sscottl#endif 5019179771Sdavidch 5020157642Sps if (m_new == NULL) { 5021189325Sdavidch sc->mbuf_alloc_failed_count++; 5022157642Sps rc = ENOBUFS; 5023176448Sdavidch goto bce_get_rx_buf_exit; 5024157642Sps } 5025157642Sps 5026176448Sdavidch DBRUN(sc->debug_rx_mbuf_alloc++); 5027157642Sps } else { 5028171667Sdavidch /* Reuse an existing mbuf. */ 5029157642Sps m_new = m; 5030157642Sps } 5031157642Sps 5032179771Sdavidch /* Make sure we have a valid packet header. */ 5033176448Sdavidch M_ASSERTPKTHDR(m_new); 5034176448Sdavidch 5035179771Sdavidch /* Initialize the mbuf size and pad if necessary for alignment. */ 5036179771Sdavidch m_new->m_pkthdr.len = m_new->m_len = sc->rx_bd_mbuf_alloc_size; 5037179695Sdavidch m_adj(m_new, sc->rx_bd_mbuf_align_pad); 5038176448Sdavidch 5039176448Sdavidch /* ToDo: Consider calling m_fragment() to test error handling. */ 5040176448Sdavidch 5041157642Sps /* Map the mbuf cluster into device memory. */ 5042157642Sps map = sc->rx_mbuf_map[*chain_prod]; 5043157642Sps error = bus_dmamap_load_mbuf_sg(sc->rx_mbuf_tag, map, m_new, 5044157642Sps segs, &nsegs, BUS_DMA_NOWAIT); 5045157642Sps 5046171667Sdavidch /* Handle any mapping errors. */ 5047157642Sps if (error) { 5048179695Sdavidch BCE_PRINTF("%s(%d): Error mapping mbuf into RX chain (%d)!\n", 5049179695Sdavidch __FILE__, __LINE__, error); 5050157642Sps 5051189325Sdavidch sc->dma_map_addr_rx_failed_count++; 5052157642Sps m_freem(m_new); 5053189325Sdavidch 5054176448Sdavidch DBRUN(sc->debug_rx_mbuf_alloc--); 5055157642Sps 5056157642Sps rc = ENOBUFS; 5057176448Sdavidch goto bce_get_rx_buf_exit; 5058157642Sps } 5059179771Sdavidch 5060176448Sdavidch /* All mbufs must map to a single segment. */ 5061176448Sdavidch KASSERT(nsegs == 1, ("%s(): Too many segments returned (%d)!", 5062176448Sdavidch __FUNCTION__, nsegs)); 5063157642Sps 5064192281Sdelphij /* ToDo: Do we need bus_dmamap_sync(,,BUS_DMASYNC_PREREAD) here? */ 5065170392Sdavidch 5066176448Sdavidch /* Setup the rx_bd for the segment. */ 5067157642Sps rxbd = &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)]; 5068157642Sps 5069157642Sps rxbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[0].ds_addr)); 5070157642Sps rxbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[0].ds_addr)); 5071157642Sps rxbd->rx_bd_len = htole32(segs[0].ds_len); 5072176448Sdavidch rxbd->rx_bd_flags = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END); 5073179771Sdavidch *prod_bseq += segs[0].ds_len; 5074157642Sps 5075176448Sdavidch /* Save the mbuf and update our counter. */ 5076176448Sdavidch sc->rx_mbuf_ptr[*chain_prod] = m_new; 5077176448Sdavidch sc->free_rx_bd -= nsegs; 5078182293Sdavidch 5079179771Sdavidch DBRUNMSG(BCE_INSANE_RECV, bce_dump_rx_mbuf_chain(sc, debug_chain_prod, 5080176448Sdavidch nsegs)); 5081157642Sps 5082179771Sdavidch DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): prod = 0x%04X, chain_prod = 0x%04X, " 5083176448Sdavidch "prod_bseq = 0x%08X\n", __FUNCTION__, *prod, *chain_prod, *prod_bseq); 5084157642Sps 5085176448Sdavidchbce_get_rx_buf_exit: 5086179771Sdavidch DBEXIT(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5087176448Sdavidch 5088176448Sdavidch return(rc); 5089176448Sdavidch} 5090176448Sdavidch 5091176448Sdavidch 5092198320Sstas#ifdef BCE_JUMBO_HDRSPLIT 5093176448Sdavidch/****************************************************************************/ 5094176448Sdavidch/* Encapsulate an mbuf cluster into the page chain. */ 5095176448Sdavidch/* */ 5096176448Sdavidch/* Returns: */ 5097176448Sdavidch/* 0 for success, positive value for failure. */ 5098176448Sdavidch/****************************************************************************/ 5099176448Sdavidchstatic int 5100176448Sdavidchbce_get_pg_buf(struct bce_softc *sc, struct mbuf *m, u16 *prod, 5101176448Sdavidch u16 *prod_idx) 5102176448Sdavidch{ 5103176448Sdavidch bus_dmamap_t map; 5104176448Sdavidch bus_addr_t busaddr; 5105176448Sdavidch struct mbuf *m_new = NULL; 5106176448Sdavidch struct rx_bd *pgbd; 5107176448Sdavidch int error, rc = 0; 5108176448Sdavidch#ifdef BCE_DEBUG 5109176448Sdavidch u16 debug_prod_idx = *prod_idx; 5110176448Sdavidch#endif 5111176448Sdavidch 5112179771Sdavidch DBENTER(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5113176448Sdavidch 5114176448Sdavidch /* Make sure the inputs are valid. */ 5115176448Sdavidch DBRUNIF((*prod_idx > MAX_PG_BD), 5116176448Sdavidch BCE_PRINTF("%s(%d): page producer out of range: 0x%04X > 0x%04X\n", 5117176448Sdavidch __FILE__, __LINE__, *prod_idx, (u16) MAX_PG_BD)); 5118176448Sdavidch 5119179771Sdavidch DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): prod = 0x%04X, " 5120176448Sdavidch "chain_prod = 0x%04X\n", __FUNCTION__, *prod, *prod_idx); 5121176448Sdavidch 5122176448Sdavidch /* Update counters if we've hit a new low or run out of pages. */ 5123179771Sdavidch DBRUNIF((sc->free_pg_bd < sc->pg_low_watermark), 5124176448Sdavidch sc->pg_low_watermark = sc->free_pg_bd); 5125176448Sdavidch DBRUNIF((sc->free_pg_bd == sc->max_pg_bd), sc->pg_empty_count++); 5126176448Sdavidch 5127176448Sdavidch /* Check whether this is a new mbuf allocation. */ 5128176448Sdavidch if (m == NULL) { 5129176448Sdavidch 5130176448Sdavidch /* Simulate an mbuf allocation failure. */ 5131189325Sdavidch DBRUNIF(DB_RANDOMTRUE(mbuf_alloc_failed_sim_control), 5132189325Sdavidch sc->mbuf_alloc_failed_count++; 5133189325Sdavidch sc->mbuf_alloc_failed_sim_count++; 5134176448Sdavidch rc = ENOBUFS; 5135176448Sdavidch goto bce_get_pg_buf_exit); 5136176448Sdavidch 5137176448Sdavidch /* This is a new mbuf allocation. */ 5138176448Sdavidch m_new = m_getcl(M_DONTWAIT, MT_DATA, 0); 5139176448Sdavidch if (m_new == NULL) { 5140189325Sdavidch sc->mbuf_alloc_failed_count++; 5141176448Sdavidch rc = ENOBUFS; 5142176448Sdavidch goto bce_get_pg_buf_exit; 5143176448Sdavidch } 5144176448Sdavidch 5145176448Sdavidch DBRUN(sc->debug_pg_mbuf_alloc++); 5146176448Sdavidch } else { 5147176448Sdavidch /* Reuse an existing mbuf. */ 5148176448Sdavidch m_new = m; 5149176448Sdavidch m_new->m_data = m_new->m_ext.ext_buf; 5150157642Sps } 5151157642Sps 5152176448Sdavidch m_new->m_len = sc->pg_bd_mbuf_alloc_size; 5153157642Sps 5154176448Sdavidch /* ToDo: Consider calling m_fragment() to test error handling. */ 5155176448Sdavidch 5156176448Sdavidch /* Map the mbuf cluster into device memory. */ 5157176448Sdavidch map = sc->pg_mbuf_map[*prod_idx]; 5158176448Sdavidch error = bus_dmamap_load(sc->pg_mbuf_tag, map, mtod(m_new, void *), 5159176448Sdavidch sc->pg_bd_mbuf_alloc_size, bce_dma_map_addr, &busaddr, BUS_DMA_NOWAIT); 5160176448Sdavidch 5161176448Sdavidch /* Handle any mapping errors. */ 5162176448Sdavidch if (error) { 5163176448Sdavidch BCE_PRINTF("%s(%d): Error mapping mbuf into page chain!\n", 5164176448Sdavidch __FILE__, __LINE__); 5165176448Sdavidch 5166176448Sdavidch m_freem(m_new); 5167176448Sdavidch DBRUN(sc->debug_pg_mbuf_alloc--); 5168176448Sdavidch 5169176448Sdavidch rc = ENOBUFS; 5170176448Sdavidch goto bce_get_pg_buf_exit; 5171176448Sdavidch } 5172176448Sdavidch 5173192281Sdelphij /* ToDo: Do we need bus_dmamap_sync(,,BUS_DMASYNC_PREREAD) here? */ 5174176448Sdavidch 5175179771Sdavidch /* 5176176448Sdavidch * The page chain uses the same rx_bd data structure 5177176448Sdavidch * as the receive chain but doesn't require a byte sequence (bseq). 5178176448Sdavidch */ 5179176448Sdavidch pgbd = &sc->pg_bd_chain[PG_PAGE(*prod_idx)][PG_IDX(*prod_idx)]; 5180176448Sdavidch 5181176448Sdavidch pgbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(busaddr)); 5182176448Sdavidch pgbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(busaddr)); 5183176448Sdavidch pgbd->rx_bd_len = htole32(sc->pg_bd_mbuf_alloc_size); 5184176448Sdavidch pgbd->rx_bd_flags = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END); 5185176448Sdavidch 5186157642Sps /* Save the mbuf and update our counter. */ 5187176448Sdavidch sc->pg_mbuf_ptr[*prod_idx] = m_new; 5188176448Sdavidch sc->free_pg_bd--; 5189157642Sps 5190179771Sdavidch DBRUNMSG(BCE_INSANE_RECV, bce_dump_pg_mbuf_chain(sc, debug_prod_idx, 5191176448Sdavidch 1)); 5192157642Sps 5193179771Sdavidch DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): prod = 0x%04X, " 5194176448Sdavidch "prod_idx = 0x%04X\n", __FUNCTION__, *prod, *prod_idx); 5195157642Sps 5196176448Sdavidchbce_get_pg_buf_exit: 5197179771Sdavidch DBEXIT(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5198157642Sps 5199157642Sps return(rc); 5200157642Sps} 5201198320Sstas#endif /* BCE_JUMBO_HDRSPLIT */ 5202157642Sps 5203179771Sdavidch/****************************************************************************/ 5204179771Sdavidch/* Initialize the TX context memory. */ 5205179771Sdavidch/* */ 5206179771Sdavidch/* Returns: */ 5207179771Sdavidch/* Nothing */ 5208179771Sdavidch/****************************************************************************/ 5209179771Sdavidchstatic void 5210179771Sdavidchbce_init_tx_context(struct bce_softc *sc) 5211179771Sdavidch{ 5212179771Sdavidch u32 val; 5213157642Sps 5214179771Sdavidch DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 5215179771Sdavidch 5216179771Sdavidch /* Initialize the context ID for an L2 TX chain. */ 5217182293Sdavidch if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 5218182293Sdavidch (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 5219179771Sdavidch /* Set the CID type to support an L2 connection. */ 5220182293Sdavidch val = BCE_L2CTX_TX_TYPE_TYPE_L2_XI | BCE_L2CTX_TX_TYPE_SIZE_L2_XI; 5221182293Sdavidch CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE_XI, val); 5222182293Sdavidch val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2_XI | (8 << 16); 5223182293Sdavidch CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_CMD_TYPE_XI, val); 5224179771Sdavidch 5225179771Sdavidch /* Point the hardware to the first page in the chain. */ 5226179771Sdavidch val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]); 5227182293Sdavidch CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TBDR_BHADDR_HI_XI, val); 5228179771Sdavidch val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]); 5229182293Sdavidch CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TBDR_BHADDR_LO_XI, val); 5230179771Sdavidch } else { 5231179771Sdavidch /* Set the CID type to support an L2 connection. */ 5232182293Sdavidch val = BCE_L2CTX_TX_TYPE_TYPE_L2 | BCE_L2CTX_TX_TYPE_SIZE_L2; 5233182293Sdavidch CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE, val); 5234182293Sdavidch val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2 | (8 << 16); 5235182293Sdavidch CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_CMD_TYPE, val); 5236179771Sdavidch 5237179771Sdavidch /* Point the hardware to the first page in the chain. */ 5238179771Sdavidch val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]); 5239182293Sdavidch CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TBDR_BHADDR_HI, val); 5240179771Sdavidch val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]); 5241182293Sdavidch CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TBDR_BHADDR_LO, val); 5242179771Sdavidch } 5243179771Sdavidch 5244179771Sdavidch DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 5245179771Sdavidch} 5246179771Sdavidch 5247182293Sdavidch 5248157642Sps/****************************************************************************/ 5249157642Sps/* Allocate memory and initialize the TX data structures. */ 5250157642Sps/* */ 5251157642Sps/* Returns: */ 5252157642Sps/* 0 for success, positive value for failure. */ 5253157642Sps/****************************************************************************/ 5254157642Spsstatic int 5255157642Spsbce_init_tx_chain(struct bce_softc *sc) 5256157642Sps{ 5257157642Sps struct tx_bd *txbd; 5258157642Sps int i, rc = 0; 5259157642Sps 5260179771Sdavidch DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_LOAD); 5261157642Sps 5262157642Sps /* Set the initial TX producer/consumer indices. */ 5263157642Sps sc->tx_prod = 0; 5264157642Sps sc->tx_cons = 0; 5265157642Sps sc->tx_prod_bseq = 0; 5266170392Sdavidch sc->used_tx_bd = 0; 5267169632Sdavidch sc->max_tx_bd = USABLE_TX_BD; 5268176448Sdavidch DBRUN(sc->tx_hi_watermark = USABLE_TX_BD); 5269176448Sdavidch DBRUN(sc->tx_full_count = 0); 5270157642Sps 5271157642Sps /* 5272157642Sps * The NetXtreme II supports a linked-list structre called 5273157642Sps * a Buffer Descriptor Chain (or BD chain). A BD chain 5274157642Sps * consists of a series of 1 or more chain pages, each of which 5275157642Sps * consists of a fixed number of BD entries. 5276157642Sps * The last BD entry on each page is a pointer to the next page 5277157642Sps * in the chain, and the last pointer in the BD chain 5278157642Sps * points back to the beginning of the chain. 5279157642Sps */ 5280157642Sps 5281157642Sps /* Set the TX next pointer chain entries. */ 5282157642Sps for (i = 0; i < TX_PAGES; i++) { 5283157642Sps int j; 5284157642Sps 5285157642Sps txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE]; 5286157642Sps 5287157642Sps /* Check if we've reached the last page. */ 5288157642Sps if (i == (TX_PAGES - 1)) 5289157642Sps j = 0; 5290157642Sps else 5291157642Sps j = i + 1; 5292157642Sps 5293157642Sps txbd->tx_bd_haddr_hi = htole32(BCE_ADDR_HI(sc->tx_bd_chain_paddr[j])); 5294157642Sps txbd->tx_bd_haddr_lo = htole32(BCE_ADDR_LO(sc->tx_bd_chain_paddr[j])); 5295157642Sps } 5296157642Sps 5297179771Sdavidch bce_init_tx_context(sc); 5298157642Sps 5299179771Sdavidch DBRUNMSG(BCE_INSANE_SEND, bce_dump_tx_chain(sc, 0, TOTAL_TX_BD)); 5300179771Sdavidch DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_LOAD); 5301157642Sps 5302157642Sps return(rc); 5303157642Sps} 5304157642Sps 5305157642Sps 5306157642Sps/****************************************************************************/ 5307157642Sps/* Free memory and clear the TX data structures. */ 5308157642Sps/* */ 5309157642Sps/* Returns: */ 5310157642Sps/* Nothing. */ 5311157642Sps/****************************************************************************/ 5312157642Spsstatic void 5313157642Spsbce_free_tx_chain(struct bce_softc *sc) 5314157642Sps{ 5315157642Sps int i; 5316157642Sps 5317179771Sdavidch DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_UNLOAD); 5318157642Sps 5319157642Sps /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */ 5320157642Sps for (i = 0; i < TOTAL_TX_BD; i++) { 5321157642Sps if (sc->tx_mbuf_ptr[i] != NULL) { 5322186168Sdelphij if (sc->tx_mbuf_map[i] != NULL) 5323157642Sps bus_dmamap_sync(sc->tx_mbuf_tag, sc->tx_mbuf_map[i], 5324157642Sps BUS_DMASYNC_POSTWRITE); 5325157642Sps m_freem(sc->tx_mbuf_ptr[i]); 5326157642Sps sc->tx_mbuf_ptr[i] = NULL; 5327176448Sdavidch DBRUN(sc->debug_tx_mbuf_alloc--); 5328179771Sdavidch } 5329157642Sps } 5330157642Sps 5331157642Sps /* Clear each TX chain page. */ 5332157642Sps for (i = 0; i < TX_PAGES; i++) 5333157642Sps bzero((char *)sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ); 5334157642Sps 5335171667Sdavidch sc->used_tx_bd = 0; 5336171667Sdavidch 5337157642Sps /* Check if we lost any mbufs in the process. */ 5338176448Sdavidch DBRUNIF((sc->debug_tx_mbuf_alloc), 5339169271Sdavidch BCE_PRINTF("%s(%d): Memory leak! Lost %d mbufs " 5340157642Sps "from tx chain!\n", 5341176448Sdavidch __FILE__, __LINE__, sc->debug_tx_mbuf_alloc)); 5342157642Sps 5343179771Sdavidch DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_UNLOAD); 5344157642Sps} 5345157642Sps 5346157642Sps 5347157642Sps/****************************************************************************/ 5348179771Sdavidch/* Initialize the RX context memory. */ 5349179771Sdavidch/* */ 5350179771Sdavidch/* Returns: */ 5351179771Sdavidch/* Nothing */ 5352179771Sdavidch/****************************************************************************/ 5353179771Sdavidchstatic void 5354179771Sdavidchbce_init_rx_context(struct bce_softc *sc) 5355179771Sdavidch{ 5356179771Sdavidch u32 val; 5357179771Sdavidch 5358179771Sdavidch DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_CTX); 5359179771Sdavidch 5360182293Sdavidch /* Initialize the type, size, and BD cache levels for the RX context. */ 5361182293Sdavidch val = BCE_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE | 5362182293Sdavidch BCE_L2CTX_RX_CTX_TYPE_SIZE_L2 | 5363182293Sdavidch (0x02 << BCE_L2CTX_RX_BD_PRE_READ_SHIFT); 5364179771Sdavidch 5365182293Sdavidch /* 5366182293Sdavidch * Set the level for generating pause frames 5367182293Sdavidch * when the number of available rx_bd's gets 5368182293Sdavidch * too low (the low watermark) and the level 5369182293Sdavidch * when pause frames can be stopped (the high 5370182293Sdavidch * watermark). 5371182293Sdavidch */ 5372182293Sdavidch if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 5373182293Sdavidch (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 5374179771Sdavidch u32 lo_water, hi_water; 5375179771Sdavidch 5376182293Sdavidch lo_water = BCE_L2CTX_RX_LO_WATER_MARK_DEFAULT; 5377179771Sdavidch hi_water = USABLE_RX_BD / 4; 5378179771Sdavidch 5379182293Sdavidch lo_water /= BCE_L2CTX_RX_LO_WATER_MARK_SCALE; 5380182293Sdavidch hi_water /= BCE_L2CTX_RX_HI_WATER_MARK_SCALE; 5381179771Sdavidch 5382179771Sdavidch if (hi_water > 0xf) 5383179771Sdavidch hi_water = 0xf; 5384179771Sdavidch else if (hi_water == 0) 5385179771Sdavidch lo_water = 0; 5386182293Sdavidch val |= (lo_water << BCE_L2CTX_RX_LO_WATER_MARK_SHIFT) | 5387182293Sdavidch (hi_water << BCE_L2CTX_RX_HI_WATER_MARK_SHIFT); 5388182293Sdavidch } 5389179771Sdavidch 5390182293Sdavidch CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_CTX_TYPE, val); 5391179771Sdavidch 5392182293Sdavidch /* Setup the MQ BIN mapping for l2_ctx_host_bseq. */ 5393182293Sdavidch if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 5394182293Sdavidch (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 5395179771Sdavidch val = REG_RD(sc, BCE_MQ_MAP_L2_5); 5396179771Sdavidch REG_WR(sc, BCE_MQ_MAP_L2_5, val | BCE_MQ_MAP_L2_5_ARM); 5397179771Sdavidch } 5398182293Sdavidch 5399179771Sdavidch /* Point the hardware to the first page in the chain. */ 5400179771Sdavidch val = BCE_ADDR_HI(sc->rx_bd_chain_paddr[0]); 5401182293Sdavidch CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_HI, val); 5402179771Sdavidch val = BCE_ADDR_LO(sc->rx_bd_chain_paddr[0]); 5403182293Sdavidch CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_LO, val); 5404179771Sdavidch 5405179771Sdavidch DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_CTX); 5406179771Sdavidch} 5407179771Sdavidch 5408179771Sdavidch 5409179771Sdavidch/****************************************************************************/ 5410157642Sps/* Allocate memory and initialize the RX data structures. */ 5411157642Sps/* */ 5412157642Sps/* Returns: */ 5413157642Sps/* 0 for success, positive value for failure. */ 5414157642Sps/****************************************************************************/ 5415157642Spsstatic int 5416157642Spsbce_init_rx_chain(struct bce_softc *sc) 5417157642Sps{ 5418157642Sps struct rx_bd *rxbd; 5419157642Sps int i, rc = 0; 5420157642Sps 5421179771Sdavidch DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 5422179771Sdavidch BCE_VERBOSE_CTX); 5423157642Sps 5424157642Sps /* Initialize the RX producer and consumer indices. */ 5425157642Sps sc->rx_prod = 0; 5426157642Sps sc->rx_cons = 0; 5427157642Sps sc->rx_prod_bseq = 0; 5428170392Sdavidch sc->free_rx_bd = USABLE_RX_BD; 5429178132Sdavidch sc->max_rx_bd = USABLE_RX_BD; 5430176448Sdavidch DBRUN(sc->rx_low_watermark = sc->max_rx_bd); 5431176448Sdavidch DBRUN(sc->rx_empty_count = 0); 5432157642Sps 5433157642Sps /* Initialize the RX next pointer chain entries. */ 5434157642Sps for (i = 0; i < RX_PAGES; i++) { 5435157642Sps int j; 5436157642Sps 5437157642Sps rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE]; 5438157642Sps 5439157642Sps /* Check if we've reached the last page. */ 5440157642Sps if (i == (RX_PAGES - 1)) 5441157642Sps j = 0; 5442157642Sps else 5443157642Sps j = i + 1; 5444157642Sps 5445157642Sps /* Setup the chain page pointers. */ 5446157642Sps rxbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(sc->rx_bd_chain_paddr[j])); 5447157642Sps rxbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(sc->rx_bd_chain_paddr[j])); 5448157642Sps } 5449157642Sps 5450192281Sdelphij /* Fill up the RX chain. */ 5451171667Sdavidch bce_fill_rx_chain(sc); 5452157642Sps 5453157642Sps for (i = 0; i < RX_PAGES; i++) { 5454192281Sdelphij bus_dmamap_sync(sc->rx_bd_chain_tag, sc->rx_bd_chain_map[i], 5455157642Sps BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 5456157642Sps } 5457157642Sps 5458179771Sdavidch bce_init_rx_context(sc); 5459157642Sps 5460179771Sdavidch DBRUNMSG(BCE_EXTREME_RECV, bce_dump_rx_chain(sc, 0, TOTAL_RX_BD)); 5461179771Sdavidch DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 5462179771Sdavidch BCE_VERBOSE_CTX); 5463179771Sdavidch /* ToDo: Are there possible failure modes here? */ 5464157642Sps return(rc); 5465157642Sps} 5466157642Sps 5467157642Sps 5468157642Sps/****************************************************************************/ 5469176448Sdavidch/* Add mbufs to the RX chain until its full or an mbuf allocation error */ 5470176448Sdavidch/* occurs. */ 5471176448Sdavidch/* */ 5472176448Sdavidch/* Returns: */ 5473176448Sdavidch/* Nothing */ 5474176448Sdavidch/****************************************************************************/ 5475176448Sdavidchstatic void 5476176448Sdavidchbce_fill_rx_chain(struct bce_softc *sc) 5477176448Sdavidch{ 5478176448Sdavidch u16 prod, prod_idx; 5479176448Sdavidch u32 prod_bseq; 5480176448Sdavidch 5481179771Sdavidch DBENTER(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 5482179771Sdavidch BCE_VERBOSE_CTX); 5483176448Sdavidch 5484179771Sdavidch /* Get the RX chain producer indices. */ 5485176448Sdavidch prod = sc->rx_prod; 5486176448Sdavidch prod_bseq = sc->rx_prod_bseq; 5487176448Sdavidch 5488176448Sdavidch /* Keep filling the RX chain until it's full. */ 5489176448Sdavidch while (sc->free_rx_bd > 0) { 5490176448Sdavidch prod_idx = RX_CHAIN_IDX(prod); 5491176448Sdavidch if (bce_get_rx_buf(sc, NULL, &prod, &prod_idx, &prod_bseq)) { 5492176448Sdavidch /* Bail out if we can't add an mbuf to the chain. */ 5493176448Sdavidch break; 5494176448Sdavidch } 5495176448Sdavidch prod = NEXT_RX_BD(prod); 5496176448Sdavidch } 5497176448Sdavidch 5498179771Sdavidch /* Save the RX chain producer indices. */ 5499176448Sdavidch sc->rx_prod = prod; 5500176448Sdavidch sc->rx_prod_bseq = prod_bseq; 5501176448Sdavidch 5502178132Sdavidch DBRUNIF(((prod & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE), 5503179771Sdavidch BCE_PRINTF("%s(): Invalid rx_prod value: 0x%04X\n", 5504178132Sdavidch __FUNCTION__, sc->rx_prod)); 5505178132Sdavidch 5506179771Sdavidch /* Write the mailbox and tell the chip about the waiting rx_bd's. */ 5507182293Sdavidch REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BDIDX, 5508179771Sdavidch sc->rx_prod); 5509182293Sdavidch REG_WR(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BSEQ, 5510179771Sdavidch sc->rx_prod_bseq); 5511176448Sdavidch 5512179771Sdavidch DBEXIT(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 5513179771Sdavidch BCE_VERBOSE_CTX); 5514176448Sdavidch} 5515176448Sdavidch 5516176448Sdavidch 5517176448Sdavidch/****************************************************************************/ 5518157642Sps/* Free memory and clear the RX data structures. */ 5519157642Sps/* */ 5520157642Sps/* Returns: */ 5521157642Sps/* Nothing. */ 5522157642Sps/****************************************************************************/ 5523157642Spsstatic void 5524157642Spsbce_free_rx_chain(struct bce_softc *sc) 5525157642Sps{ 5526157642Sps int i; 5527157642Sps 5528179771Sdavidch DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 5529182293Sdavidch 5530157642Sps /* Free any mbufs still in the RX mbuf chain. */ 5531157642Sps for (i = 0; i < TOTAL_RX_BD; i++) { 5532157642Sps if (sc->rx_mbuf_ptr[i] != NULL) { 5533157642Sps if (sc->rx_mbuf_map[i] != NULL) 5534157642Sps bus_dmamap_sync(sc->rx_mbuf_tag, sc->rx_mbuf_map[i], 5535157642Sps BUS_DMASYNC_POSTREAD); 5536157642Sps m_freem(sc->rx_mbuf_ptr[i]); 5537157642Sps sc->rx_mbuf_ptr[i] = NULL; 5538176448Sdavidch DBRUN(sc->debug_rx_mbuf_alloc--); 5539157642Sps } 5540157642Sps } 5541157642Sps 5542157642Sps /* Clear each RX chain page. */ 5543157642Sps for (i = 0; i < RX_PAGES; i++) 5544157642Sps bzero((char *)sc->rx_bd_chain[i], BCE_RX_CHAIN_PAGE_SZ); 5545157642Sps 5546171667Sdavidch sc->free_rx_bd = sc->max_rx_bd; 5547171667Sdavidch 5548157642Sps /* Check if we lost any mbufs in the process. */ 5549176448Sdavidch DBRUNIF((sc->debug_rx_mbuf_alloc), 5550176448Sdavidch BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from rx chain!\n", 5551176448Sdavidch __FUNCTION__, sc->debug_rx_mbuf_alloc)); 5552157642Sps 5553179771Sdavidch DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 5554157642Sps} 5555157642Sps 5556157642Sps 5557198320Sstas#ifdef BCE_JUMBO_HDRSPLIT 5558157642Sps/****************************************************************************/ 5559176448Sdavidch/* Allocate memory and initialize the page data structures. */ 5560176448Sdavidch/* Assumes that bce_init_rx_chain() has not already been called. */ 5561176448Sdavidch/* */ 5562176448Sdavidch/* Returns: */ 5563176448Sdavidch/* 0 for success, positive value for failure. */ 5564176448Sdavidch/****************************************************************************/ 5565176448Sdavidchstatic int 5566176448Sdavidchbce_init_pg_chain(struct bce_softc *sc) 5567176448Sdavidch{ 5568176448Sdavidch struct rx_bd *pgbd; 5569176448Sdavidch int i, rc = 0; 5570176448Sdavidch u32 val; 5571176448Sdavidch 5572179771Sdavidch DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 5573179771Sdavidch BCE_VERBOSE_CTX); 5574176448Sdavidch 5575176448Sdavidch /* Initialize the page producer and consumer indices. */ 5576176448Sdavidch sc->pg_prod = 0; 5577176448Sdavidch sc->pg_cons = 0; 5578176448Sdavidch sc->free_pg_bd = USABLE_PG_BD; 5579176448Sdavidch sc->max_pg_bd = USABLE_PG_BD; 5580176448Sdavidch DBRUN(sc->pg_low_watermark = sc->max_pg_bd); 5581176448Sdavidch DBRUN(sc->pg_empty_count = 0); 5582176448Sdavidch 5583176448Sdavidch /* Initialize the page next pointer chain entries. */ 5584176448Sdavidch for (i = 0; i < PG_PAGES; i++) { 5585176448Sdavidch int j; 5586176448Sdavidch 5587176448Sdavidch pgbd = &sc->pg_bd_chain[i][USABLE_PG_BD_PER_PAGE]; 5588176448Sdavidch 5589176448Sdavidch /* Check if we've reached the last page. */ 5590176448Sdavidch if (i == (PG_PAGES - 1)) 5591176448Sdavidch j = 0; 5592176448Sdavidch else 5593176448Sdavidch j = i + 1; 5594176448Sdavidch 5595176448Sdavidch /* Setup the chain page pointers. */ 5596176448Sdavidch pgbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(sc->pg_bd_chain_paddr[j])); 5597176448Sdavidch pgbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(sc->pg_bd_chain_paddr[j])); 5598176448Sdavidch } 5599176448Sdavidch 5600182293Sdavidch /* Setup the MQ BIN mapping for host_pg_bidx. */ 5601182293Sdavidch if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 5602182293Sdavidch (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) 5603179771Sdavidch REG_WR(sc, BCE_MQ_MAP_L2_3, BCE_MQ_MAP_L2_3_DEFAULT); 5604176448Sdavidch 5605182293Sdavidch CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_PG_BUF_SIZE, 0); 5606179771Sdavidch 5607176448Sdavidch /* Configure the rx_bd and page chain mbuf cluster size. */ 5608179771Sdavidch val = (sc->rx_bd_mbuf_data_len << 16) | sc->pg_bd_mbuf_alloc_size; 5609182293Sdavidch CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_PG_BUF_SIZE, val); 5610176448Sdavidch 5611176448Sdavidch /* Configure the context reserved for jumbo support. */ 5612182293Sdavidch CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_RBDC_KEY, 5613182293Sdavidch BCE_L2CTX_RX_RBDC_JUMBO_KEY); 5614176448Sdavidch 5615179771Sdavidch /* Point the hardware to the first page in the page chain. */ 5616179771Sdavidch val = BCE_ADDR_HI(sc->pg_bd_chain_paddr[0]); 5617182293Sdavidch CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_PG_BDHADDR_HI, val); 5618179771Sdavidch val = BCE_ADDR_LO(sc->pg_bd_chain_paddr[0]); 5619182293Sdavidch CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_PG_BDHADDR_LO, val); 5620179771Sdavidch 5621176448Sdavidch /* Fill up the page chain. */ 5622176448Sdavidch bce_fill_pg_chain(sc); 5623176448Sdavidch 5624176448Sdavidch for (i = 0; i < PG_PAGES; i++) { 5625192281Sdelphij bus_dmamap_sync(sc->pg_bd_chain_tag, sc->pg_bd_chain_map[i], 5626176448Sdavidch BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 5627176448Sdavidch } 5628176448Sdavidch 5629179771Sdavidch DBRUNMSG(BCE_EXTREME_RECV, bce_dump_pg_chain(sc, 0, TOTAL_PG_BD)); 5630179771Sdavidch DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 5631179771Sdavidch BCE_VERBOSE_CTX); 5632176448Sdavidch return(rc); 5633176448Sdavidch} 5634176448Sdavidch 5635179771Sdavidch 5636176448Sdavidch/****************************************************************************/ 5637176448Sdavidch/* Add mbufs to the page chain until its full or an mbuf allocation error */ 5638176448Sdavidch/* occurs. */ 5639176448Sdavidch/* */ 5640176448Sdavidch/* Returns: */ 5641176448Sdavidch/* Nothing */ 5642176448Sdavidch/****************************************************************************/ 5643176448Sdavidchstatic void 5644176448Sdavidchbce_fill_pg_chain(struct bce_softc *sc) 5645176448Sdavidch{ 5646178132Sdavidch u16 prod, prod_idx; 5647176448Sdavidch 5648179771Sdavidch DBENTER(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 5649179771Sdavidch BCE_VERBOSE_CTX); 5650176448Sdavidch 5651179771Sdavidch /* Get the page chain prodcuer index. */ 5652176448Sdavidch prod = sc->pg_prod; 5653176448Sdavidch 5654176448Sdavidch /* Keep filling the page chain until it's full. */ 5655176448Sdavidch while (sc->free_pg_bd > 0) { 5656176448Sdavidch prod_idx = PG_CHAIN_IDX(prod); 5657176448Sdavidch if (bce_get_pg_buf(sc, NULL, &prod, &prod_idx)) { 5658176448Sdavidch /* Bail out if we can't add an mbuf to the chain. */ 5659176448Sdavidch break; 5660178132Sdavidch } 5661176448Sdavidch prod = NEXT_PG_BD(prod); 5662176448Sdavidch } 5663176448Sdavidch 5664176448Sdavidch /* Save the page chain producer index. */ 5665176448Sdavidch sc->pg_prod = prod; 5666176448Sdavidch 5667178132Sdavidch DBRUNIF(((prod & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE), 5668179771Sdavidch BCE_PRINTF("%s(): Invalid pg_prod value: 0x%04X\n", 5669178132Sdavidch __FUNCTION__, sc->pg_prod)); 5670176448Sdavidch 5671179771Sdavidch /* 5672179771Sdavidch * Write the mailbox and tell the chip about 5673179771Sdavidch * the new rx_bd's in the page chain. 5674179771Sdavidch */ 5675182293Sdavidch REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_PG_BDIDX, 5676179771Sdavidch sc->pg_prod); 5677178132Sdavidch 5678179771Sdavidch DBEXIT(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 5679179771Sdavidch BCE_VERBOSE_CTX); 5680176448Sdavidch} 5681176448Sdavidch 5682176448Sdavidch 5683176448Sdavidch/****************************************************************************/ 5684176448Sdavidch/* Free memory and clear the RX data structures. */ 5685176448Sdavidch/* */ 5686176448Sdavidch/* Returns: */ 5687176448Sdavidch/* Nothing. */ 5688176448Sdavidch/****************************************************************************/ 5689176448Sdavidchstatic void 5690176448Sdavidchbce_free_pg_chain(struct bce_softc *sc) 5691176448Sdavidch{ 5692176448Sdavidch int i; 5693176448Sdavidch 5694179771Sdavidch DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 5695176448Sdavidch 5696176448Sdavidch /* Free any mbufs still in the mbuf page chain. */ 5697176448Sdavidch for (i = 0; i < TOTAL_PG_BD; i++) { 5698176448Sdavidch if (sc->pg_mbuf_ptr[i] != NULL) { 5699176448Sdavidch if (sc->pg_mbuf_map[i] != NULL) 5700176448Sdavidch bus_dmamap_sync(sc->pg_mbuf_tag, sc->pg_mbuf_map[i], 5701176448Sdavidch BUS_DMASYNC_POSTREAD); 5702176448Sdavidch m_freem(sc->pg_mbuf_ptr[i]); 5703176448Sdavidch sc->pg_mbuf_ptr[i] = NULL; 5704178132Sdavidch DBRUN(sc->debug_pg_mbuf_alloc--); 5705176448Sdavidch } 5706176448Sdavidch } 5707176448Sdavidch 5708176448Sdavidch /* Clear each page chain pages. */ 5709176448Sdavidch for (i = 0; i < PG_PAGES; i++) 5710176448Sdavidch bzero((char *)sc->pg_bd_chain[i], BCE_PG_CHAIN_PAGE_SZ); 5711176448Sdavidch 5712176448Sdavidch sc->free_pg_bd = sc->max_pg_bd; 5713176448Sdavidch 5714176448Sdavidch /* Check if we lost any mbufs in the process. */ 5715176448Sdavidch DBRUNIF((sc->debug_pg_mbuf_alloc), 5716176448Sdavidch BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from page chain!\n", 5717176448Sdavidch __FUNCTION__, sc->debug_pg_mbuf_alloc)); 5718176448Sdavidch 5719179771Sdavidch DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 5720176448Sdavidch} 5721198320Sstas#endif /* BCE_JUMBO_HDRSPLIT */ 5722176448Sdavidch 5723176448Sdavidch 5724176448Sdavidch/****************************************************************************/ 5725157642Sps/* Set media options. */ 5726157642Sps/* */ 5727157642Sps/* Returns: */ 5728157642Sps/* 0 for success, positive value for failure. */ 5729157642Sps/****************************************************************************/ 5730157642Spsstatic int 5731157642Spsbce_ifmedia_upd(struct ifnet *ifp) 5732157642Sps{ 5733179771Sdavidch struct bce_softc *sc = ifp->if_softc; 5734165994Sjhb 5735179771Sdavidch DBENTER(BCE_VERBOSE); 5736179771Sdavidch 5737165994Sjhb BCE_LOCK(sc); 5738165994Sjhb bce_ifmedia_upd_locked(ifp); 5739165994Sjhb BCE_UNLOCK(sc); 5740179771Sdavidch 5741179771Sdavidch DBEXIT(BCE_VERBOSE); 5742165994Sjhb return (0); 5743165994Sjhb} 5744165994Sjhb 5745170392Sdavidch 5746169632Sdavidch/****************************************************************************/ 5747169632Sdavidch/* Set media options. */ 5748169632Sdavidch/* */ 5749169632Sdavidch/* Returns: */ 5750169632Sdavidch/* Nothing. */ 5751169632Sdavidch/****************************************************************************/ 5752165994Sjhbstatic void 5753165994Sjhbbce_ifmedia_upd_locked(struct ifnet *ifp) 5754165994Sjhb{ 5755179771Sdavidch struct bce_softc *sc = ifp->if_softc; 5756157642Sps struct mii_data *mii; 5757170392Sdavidch 5758179771Sdavidch DBENTER(BCE_VERBOSE); 5759179771Sdavidch 5760165994Sjhb BCE_LOCK_ASSERT(sc); 5761157642Sps 5762157642Sps mii = device_get_softc(sc->bce_miibus); 5763170392Sdavidch 5764170392Sdavidch /* Make sure the MII bus has been enumerated. */ 5765170392Sdavidch if (mii) { 5766169271Sdavidch sc->bce_link = 0; 5767169271Sdavidch if (mii->mii_instance) { 5768169271Sdavidch struct mii_softc *miisc; 5769165994Sjhb 5770169271Sdavidch LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 5771169271Sdavidch mii_phy_reset(miisc); 5772169271Sdavidch } 5773170392Sdavidch mii_mediachg(mii); 5774157642Sps } 5775179771Sdavidch 5776179771Sdavidch DBEXIT(BCE_VERBOSE); 5777157642Sps} 5778157642Sps 5779157642Sps 5780157642Sps/****************************************************************************/ 5781157642Sps/* Reports current media status. */ 5782157642Sps/* */ 5783157642Sps/* Returns: */ 5784157642Sps/* Nothing. */ 5785157642Sps/****************************************************************************/ 5786157642Spsstatic void 5787157642Spsbce_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 5788157642Sps{ 5789179771Sdavidch struct bce_softc *sc = ifp->if_softc; 5790157642Sps struct mii_data *mii; 5791157642Sps 5792179771Sdavidch DBENTER(BCE_VERBOSE); 5793157642Sps 5794157642Sps BCE_LOCK(sc); 5795157642Sps 5796157642Sps mii = device_get_softc(sc->bce_miibus); 5797157642Sps 5798157642Sps mii_pollstat(mii); 5799157642Sps ifmr->ifm_active = mii->mii_media_active; 5800157642Sps ifmr->ifm_status = mii->mii_media_status; 5801157642Sps 5802157642Sps BCE_UNLOCK(sc); 5803179771Sdavidch 5804179771Sdavidch DBEXIT(BCE_VERBOSE); 5805157642Sps} 5806157642Sps 5807157642Sps 5808157642Sps/****************************************************************************/ 5809157642Sps/* Handles PHY generated interrupt events. */ 5810157642Sps/* */ 5811157642Sps/* Returns: */ 5812157642Sps/* Nothing. */ 5813157642Sps/****************************************************************************/ 5814157642Spsstatic void 5815157642Spsbce_phy_intr(struct bce_softc *sc) 5816157642Sps{ 5817157642Sps u32 new_link_state, old_link_state; 5818157642Sps 5819179771Sdavidch DBENTER(BCE_VERBOSE_PHY | BCE_VERBOSE_INTR); 5820179771Sdavidch 5821157642Sps new_link_state = sc->status_block->status_attn_bits & 5822157642Sps STATUS_ATTN_BITS_LINK_STATE; 5823157642Sps old_link_state = sc->status_block->status_attn_bits_ack & 5824157642Sps STATUS_ATTN_BITS_LINK_STATE; 5825157642Sps 5826157642Sps /* Handle any changes if the link state has changed. */ 5827157642Sps if (new_link_state != old_link_state) { 5828157642Sps 5829157642Sps /* Update the status_attn_bits_ack field in the status block. */ 5830157642Sps if (new_link_state) { 5831157642Sps REG_WR(sc, BCE_PCICFG_STATUS_BIT_SET_CMD, 5832157642Sps STATUS_ATTN_BITS_LINK_STATE); 5833179771Sdavidch DBPRINT(sc, BCE_INFO_PHY, "%s(): Link is now UP.\n", 5834179771Sdavidch __FUNCTION__); 5835157642Sps } 5836157642Sps else { 5837157642Sps REG_WR(sc, BCE_PCICFG_STATUS_BIT_CLEAR_CMD, 5838157642Sps STATUS_ATTN_BITS_LINK_STATE); 5839179771Sdavidch DBPRINT(sc, BCE_INFO_PHY, "%s(): Link is now DOWN.\n", 5840179771Sdavidch __FUNCTION__); 5841157642Sps } 5842157642Sps 5843179771Sdavidch /* 5844179771Sdavidch * Assume link is down and allow 5845179771Sdavidch * tick routine to update the state 5846179771Sdavidch * based on the actual media state. 5847179771Sdavidch */ 5848179771Sdavidch sc->bce_link = 0; 5849179771Sdavidch callout_stop(&sc->bce_tick_callout); 5850179771Sdavidch bce_tick(sc); 5851157642Sps } 5852157642Sps 5853157642Sps /* Acknowledge the link change interrupt. */ 5854157642Sps REG_WR(sc, BCE_EMAC_STATUS, BCE_EMAC_STATUS_LINK_CHANGE); 5855179771Sdavidch 5856179771Sdavidch DBEXIT(BCE_VERBOSE_PHY | BCE_VERBOSE_INTR); 5857157642Sps} 5858157642Sps 5859157642Sps 5860157642Sps/****************************************************************************/ 5861178132Sdavidch/* Reads the receive consumer value from the status block (skipping over */ 5862176448Sdavidch/* chain page pointer if necessary). */ 5863176448Sdavidch/* */ 5864176448Sdavidch/* Returns: */ 5865176448Sdavidch/* hw_cons */ 5866176448Sdavidch/****************************************************************************/ 5867176448Sdavidchstatic inline u16 5868176448Sdavidchbce_get_hw_rx_cons(struct bce_softc *sc) 5869176448Sdavidch{ 5870182293Sdavidch u16 hw_cons; 5871176448Sdavidch 5872182293Sdavidch rmb(); 5873182293Sdavidch hw_cons = sc->status_block->status_rx_quick_consumer_index0; 5874176448Sdavidch if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 5875176448Sdavidch hw_cons++; 5876176448Sdavidch 5877176448Sdavidch return hw_cons; 5878176448Sdavidch} 5879176448Sdavidch 5880176448Sdavidch/****************************************************************************/ 5881157642Sps/* Handles received frame interrupt events. */ 5882157642Sps/* */ 5883157642Sps/* Returns: */ 5884157642Sps/* Nothing. */ 5885157642Sps/****************************************************************************/ 5886157642Spsstatic void 5887157642Spsbce_rx_intr(struct bce_softc *sc) 5888157642Sps{ 5889178132Sdavidch struct ifnet *ifp = sc->bce_ifp; 5890178132Sdavidch struct l2_fhdr *l2fhdr; 5891204368Syongari struct ether_vlan_header *vh; 5892179695Sdavidch unsigned int pkt_len; 5893179771Sdavidch u16 sw_rx_cons, sw_rx_cons_idx, hw_rx_cons; 5894178132Sdavidch u32 status; 5895198320Sstas#ifdef BCE_JUMBO_HDRSPLIT 5896179771Sdavidch unsigned int rem_len; 5897179771Sdavidch u16 sw_pg_cons, sw_pg_cons_idx; 5898179695Sdavidch#endif 5899178132Sdavidch 5900179771Sdavidch DBENTER(BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 5901179771Sdavidch DBRUN(sc->rx_interrupts++); 5902179771Sdavidch DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): rx_prod = 0x%04X, " 5903179771Sdavidch "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n", 5904179771Sdavidch __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq); 5905178132Sdavidch 5906157642Sps /* Prepare the RX chain pages to be accessed by the host CPU. */ 5907157642Sps for (int i = 0; i < RX_PAGES; i++) 5908157642Sps bus_dmamap_sync(sc->rx_bd_chain_tag, 5909192281Sdelphij sc->rx_bd_chain_map[i], BUS_DMASYNC_POSTREAD); 5910157642Sps 5911198320Sstas#ifdef BCE_JUMBO_HDRSPLIT 5912176448Sdavidch /* Prepare the page chain pages to be accessed by the host CPU. */ 5913176448Sdavidch for (int i = 0; i < PG_PAGES; i++) 5914176448Sdavidch bus_dmamap_sync(sc->pg_bd_chain_tag, 5915192281Sdelphij sc->pg_bd_chain_map[i], BUS_DMASYNC_POSTREAD); 5916179695Sdavidch#endif 5917176448Sdavidch 5918157642Sps /* Get the hardware's view of the RX consumer index. */ 5919176448Sdavidch hw_rx_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc); 5920157642Sps 5921176448Sdavidch /* Get working copies of the driver's view of the consumer indices. */ 5922176448Sdavidch sw_rx_cons = sc->rx_cons; 5923198320Sstas#ifdef BCE_JUMBO_HDRSPLIT 5924179771Sdavidch sw_pg_cons = sc->pg_cons; 5925179695Sdavidch#endif 5926157642Sps 5927170392Sdavidch /* Update some debug statistics counters */ 5928157642Sps DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 5929170392Sdavidch sc->rx_low_watermark = sc->free_rx_bd); 5930176448Sdavidch DBRUNIF((sc->free_rx_bd == sc->max_rx_bd), sc->rx_empty_count++); 5931157642Sps 5932178132Sdavidch /* Scan through the receive chain as long as there is work to do */ 5933176448Sdavidch /* ToDo: Consider setting a limit on the number of packets processed. */ 5934182293Sdavidch rmb(); 5935176448Sdavidch while (sw_rx_cons != hw_rx_cons) { 5936176448Sdavidch struct mbuf *m0; 5937179771Sdavidch 5938157642Sps /* Convert the producer/consumer indices to an actual rx_bd index. */ 5939176448Sdavidch sw_rx_cons_idx = RX_CHAIN_IDX(sw_rx_cons); 5940157642Sps 5941176448Sdavidch /* Unmap the mbuf from DMA space. */ 5942192281Sdelphij bus_dmamap_sync(sc->rx_mbuf_tag, sc->rx_mbuf_map[sw_rx_cons_idx], 5943192281Sdelphij BUS_DMASYNC_POSTREAD); 5944176448Sdavidch bus_dmamap_unload(sc->rx_mbuf_tag, 5945176448Sdavidch sc->rx_mbuf_map[sw_rx_cons_idx]); 5946157642Sps 5947176448Sdavidch /* Remove the mbuf from the RX chain. */ 5948176448Sdavidch m0 = sc->rx_mbuf_ptr[sw_rx_cons_idx]; 5949176448Sdavidch sc->rx_mbuf_ptr[sw_rx_cons_idx] = NULL; 5950176448Sdavidch DBRUN(sc->debug_rx_mbuf_alloc--); 5951176448Sdavidch sc->free_rx_bd++; 5952179771Sdavidch 5953202717Sdavidch if(m0 == NULL) { 5954202717Sdavidch DBPRINT(sc, BCE_EXTREME_RECV, "%s(): Oops! Empty mbuf pointer " 5955202717Sdavidch "found in sc->rx_mbuf_ptr[0x%04X]!\n", 5956202717Sdavidch __FUNCTION__, sw_rx_cons_idx); 5957202717Sdavidch goto bce_rx_int_next_rx; 5958202717Sdavidch } 5959202717Sdavidch 5960202717Sdavidch /* 5961202717Sdavidch * Frames received on the NetXteme II are prepended with an 5962202717Sdavidch * l2_fhdr structure which provides status information about 5963202717Sdavidch * the received frame (including VLAN tags and checksum info). 5964202717Sdavidch * The frames are also automatically adjusted to align the IP 5965202717Sdavidch * header (i.e. two null bytes are inserted before the Ethernet 5966202717Sdavidch * header). As a result the data DMA'd by the controller into 5967202717Sdavidch * the mbuf is as follows: 5968202717Sdavidch * 5969202717Sdavidch * +---------+-----+---------------------+-----+ 5970202717Sdavidch * | l2_fhdr | pad | packet data | FCS | 5971202717Sdavidch * +---------+-----+---------------------+-----+ 5972202717Sdavidch * 5973202717Sdavidch * The l2_fhdr needs to be checked and skipped and the FCS needs 5974202717Sdavidch * to be stripped before sending the packet up the stack. 5975202717Sdavidch */ 5976176448Sdavidch l2fhdr = mtod(m0, struct l2_fhdr *); 5977157642Sps 5978176448Sdavidch /* Get the packet data + FCS length and the status. */ 5979176448Sdavidch pkt_len = l2fhdr->l2_fhdr_pkt_len; 5980176448Sdavidch status = l2fhdr->l2_fhdr_status; 5981178132Sdavidch 5982176448Sdavidch /* 5983178132Sdavidch * Skip over the l2_fhdr and pad, resulting in the 5984179771Sdavidch * following data in the mbuf: 5985178132Sdavidch * +---------------------+-----+ 5986178132Sdavidch * | packet data | FCS | 5987178132Sdavidch * +---------------------+-----+ 5988178132Sdavidch */ 5989176448Sdavidch m_adj(m0, sizeof(struct l2_fhdr) + ETHER_ALIGN); 5990178132Sdavidch 5991198320Sstas#ifdef BCE_JUMBO_HDRSPLIT 5992178132Sdavidch /* 5993178132Sdavidch * Check whether the received frame fits in a single 5994179771Sdavidch * mbuf or not (i.e. packet data + FCS <= 5995179695Sdavidch * sc->rx_bd_mbuf_data_len bytes). 5996176448Sdavidch */ 5997176448Sdavidch if (pkt_len > m0->m_len) { 5998170392Sdavidch /* 5999178132Sdavidch * The received frame is larger than a single mbuf. 6000178132Sdavidch * If the frame was a TCP frame then only the TCP 6001179771Sdavidch * header is placed in the mbuf, the remaining 6002178132Sdavidch * payload (including FCS) is placed in the page 6003178132Sdavidch * chain, the SPLIT flag is set, and the header 6004178132Sdavidch * length is placed in the IP checksum field. 6005178132Sdavidch * If the frame is not a TCP frame then the mbuf 6006179771Sdavidch * is filled and the remaining bytes are placed 6007178132Sdavidch * in the page chain. 6008169632Sdavidch */ 6009178132Sdavidch 6010178132Sdavidch DBPRINT(sc, BCE_INFO_RECV, "%s(): Found a large packet.\n", 6011178132Sdavidch __FUNCTION__); 6012178132Sdavidch 6013182293Sdavidch /* 6014182293Sdavidch * When the page chain is enabled and the TCP 6015182293Sdavidch * header has been split from the TCP payload, 6016182293Sdavidch * the ip_xsum structure will reflect the length 6017182293Sdavidch * of the TCP header, not the IP checksum. Set 6018182293Sdavidch * the packet length of the mbuf accordingly. 6019182293Sdavidch */ 6020178132Sdavidch if (status & L2_FHDR_STATUS_SPLIT) 6021178132Sdavidch m0->m_len = l2fhdr->l2_fhdr_ip_xsum; 6022178132Sdavidch 6023178132Sdavidch rem_len = pkt_len - m0->m_len; 6024178132Sdavidch 6025176448Sdavidch /* Pull mbufs off the page chain for the remaining data. */ 6026178132Sdavidch while (rem_len > 0) { 6027178132Sdavidch struct mbuf *m_pg; 6028179771Sdavidch 6029178132Sdavidch sw_pg_cons_idx = PG_CHAIN_IDX(sw_pg_cons); 6030178132Sdavidch 6031176448Sdavidch /* Remove the mbuf from the page chain. */ 6032176448Sdavidch m_pg = sc->pg_mbuf_ptr[sw_pg_cons_idx]; 6033176448Sdavidch sc->pg_mbuf_ptr[sw_pg_cons_idx] = NULL; 6034176448Sdavidch DBRUN(sc->debug_pg_mbuf_alloc--); 6035176448Sdavidch sc->free_pg_bd++; 6036157642Sps 6037176448Sdavidch /* Unmap the page chain mbuf from DMA space. */ 6038179771Sdavidch bus_dmamap_sync(sc->pg_mbuf_tag, 6039176448Sdavidch sc->pg_mbuf_map[sw_pg_cons_idx], 6040176448Sdavidch BUS_DMASYNC_POSTREAD); 6041176448Sdavidch bus_dmamap_unload(sc->pg_mbuf_tag, 6042176448Sdavidch sc->pg_mbuf_map[sw_pg_cons_idx]); 6043157642Sps 6044178132Sdavidch /* Adjust the mbuf length. */ 6045176448Sdavidch if (rem_len < m_pg->m_len) { 6046176448Sdavidch /* The mbuf chain is complete. */ 6047176448Sdavidch m_pg->m_len = rem_len; 6048176448Sdavidch rem_len = 0; 6049178132Sdavidch } else { 6050178132Sdavidch /* More packet data is waiting. */ 6051176448Sdavidch rem_len -= m_pg->m_len; 6052178132Sdavidch } 6053178132Sdavidch 6054176448Sdavidch /* Concatenate the mbuf cluster to the mbuf. */ 6055176448Sdavidch m_cat(m0, m_pg); 6056157642Sps 6057178132Sdavidch sw_pg_cons = NEXT_PG_BD(sw_pg_cons); 6058176448Sdavidch } 6059176448Sdavidch 6060178132Sdavidch /* Set the total packet length. */ 6061178132Sdavidch m0->m_pkthdr.len = pkt_len; 6062178132Sdavidch 6063176448Sdavidch } else { 6064157642Sps /* 6065176448Sdavidch * The received packet is small and fits in a 6066178132Sdavidch * single mbuf (i.e. the l2_fhdr + pad + packet + 6067178132Sdavidch * FCS <= MHLEN). In other words, the packet is 6068176448Sdavidch * 154 bytes or less in size. 6069157642Sps */ 6070157642Sps 6071178132Sdavidch DBPRINT(sc, BCE_INFO_RECV, "%s(): Found a small packet.\n", 6072178132Sdavidch __FUNCTION__); 6073178132Sdavidch 6074176448Sdavidch /* Set the total packet length. */ 6075176448Sdavidch m0->m_pkthdr.len = m0->m_len = pkt_len; 6076179771Sdavidch } 6077191923Sdavidch#else 6078191923Sdavidch /* Set the total packet length. */ 6079191923Sdavidch m0->m_pkthdr.len = m0->m_len = pkt_len; 6080179695Sdavidch#endif 6081178132Sdavidch 6082178132Sdavidch /* Remove the trailing Ethernet FCS. */ 6083178132Sdavidch m_adj(m0, -ETHER_CRC_LEN); 6084178132Sdavidch 6085176448Sdavidch /* Check that the resulting mbuf chain is valid. */ 6086176448Sdavidch DBRUN(m_sanity(m0, FALSE)); 6087179771Sdavidch DBRUNIF(((m0->m_len < ETHER_HDR_LEN) | 6088179771Sdavidch (m0->m_pkthdr.len > BCE_MAX_JUMBO_ETHER_MTU_VLAN)), 6089179771Sdavidch BCE_PRINTF("Invalid Ethernet frame size!\n"); 6090179771Sdavidch m_print(m0, 128)); 6091157642Sps 6092189325Sdavidch DBRUNIF(DB_RANDOMTRUE(l2fhdr_error_sim_control), 6093176448Sdavidch BCE_PRINTF("Simulating l2_fhdr status error.\n"); 6094189325Sdavidch sc->l2fhdr_error_sim_count++; 6095176448Sdavidch status = status | L2_FHDR_ERRORS_PHY_DECODE); 6096157642Sps 6097176448Sdavidch /* Check the received frame for errors. */ 6098179771Sdavidch if (status & (L2_FHDR_ERRORS_BAD_CRC | 6099179771Sdavidch L2_FHDR_ERRORS_PHY_DECODE | L2_FHDR_ERRORS_ALIGNMENT | 6100176448Sdavidch L2_FHDR_ERRORS_TOO_SHORT | L2_FHDR_ERRORS_GIANT_FRAME)) { 6101157642Sps 6102176448Sdavidch /* Log the error and release the mbuf. */ 6103176448Sdavidch ifp->if_ierrors++; 6104189325Sdavidch sc->l2fhdr_error_count++; 6105179771Sdavidch 6106176448Sdavidch m_freem(m0); 6107176448Sdavidch m0 = NULL; 6108176448Sdavidch goto bce_rx_int_next_rx; 6109176448Sdavidch } 6110157642Sps 6111176448Sdavidch /* Send the packet to the appropriate interface. */ 6112176448Sdavidch m0->m_pkthdr.rcvif = ifp; 6113178132Sdavidch 6114178132Sdavidch /* Assume no hardware checksum. */ 6115176448Sdavidch m0->m_pkthdr.csum_flags = 0; 6116178132Sdavidch 6117176448Sdavidch /* Validate the checksum if offload enabled. */ 6118176448Sdavidch if (ifp->if_capenable & IFCAP_RXCSUM) { 6119157642Sps 6120176448Sdavidch /* Check for an IP datagram. */ 6121178132Sdavidch if (!(status & L2_FHDR_STATUS_SPLIT) && 6122176448Sdavidch (status & L2_FHDR_STATUS_IP_DATAGRAM)) { 6123176448Sdavidch m0->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 6124157642Sps 6125176448Sdavidch /* Check if the IP checksum is valid. */ 6126176448Sdavidch if ((l2fhdr->l2_fhdr_ip_xsum ^ 0xffff) == 0) 6127176448Sdavidch m0->m_pkthdr.csum_flags |= CSUM_IP_VALID; 6128178132Sdavidch } 6129157642Sps 6130176448Sdavidch /* Check for a valid TCP/UDP frame. */ 6131176448Sdavidch if (status & (L2_FHDR_STATUS_TCP_SEGMENT | 6132176448Sdavidch L2_FHDR_STATUS_UDP_DATAGRAM)) { 6133157642Sps 6134176448Sdavidch /* Check for a good TCP/UDP checksum. */ 6135176448Sdavidch if ((status & (L2_FHDR_ERRORS_TCP_XSUM | 6136176448Sdavidch L2_FHDR_ERRORS_UDP_XSUM)) == 0) { 6137176448Sdavidch m0->m_pkthdr.csum_data = 6138176448Sdavidch l2fhdr->l2_fhdr_tcp_udp_xsum; 6139179771Sdavidch m0->m_pkthdr.csum_flags |= (CSUM_DATA_VALID 6140176448Sdavidch | CSUM_PSEUDO_HDR); 6141157642Sps } 6142176448Sdavidch } 6143179771Sdavidch } 6144157642Sps 6145189325Sdavidch /* Attach the VLAN tag. */ 6146176448Sdavidch if (status & L2_FHDR_STATUS_L2_VLAN_TAG) { 6147204368Syongari if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) { 6148157642Sps#if __FreeBSD_version < 700000 6149204368Syongari VLAN_INPUT_TAG(ifp, m0, 6150204368Syongari l2fhdr->l2_fhdr_vlan_tag, continue); 6151157642Sps#else 6152204368Syongari m0->m_pkthdr.ether_vtag = 6153204368Syongari l2fhdr->l2_fhdr_vlan_tag; 6154204368Syongari m0->m_flags |= M_VLANTAG; 6155179771Sdavidch#endif 6156204368Syongari } else { 6157204368Syongari /* 6158204368Syongari * bce(4) controllers can't disable VLAN 6159204368Syongari * tag stripping if management firmware 6160204368Syongari * (ASF/IPMI/UMP) is running. So we always 6161204368Syongari * strip VLAN tag and manually reconstruct 6162204368Syongari * the VLAN frame by appending stripped 6163204368Syongari * VLAN tag in driver if VLAN tag stripping 6164204368Syongari * was disabled. 6165204368Syongari * 6166204368Syongari * TODO: LLC SNAP handling. 6167204368Syongari */ 6168204368Syongari bcopy(mtod(m0, uint8_t *), 6169204368Syongari mtod(m0, uint8_t *) - ETHER_VLAN_ENCAP_LEN, 6170204368Syongari ETHER_ADDR_LEN * 2); 6171204368Syongari m0->m_data -= ETHER_VLAN_ENCAP_LEN; 6172204368Syongari vh = mtod(m0, struct ether_vlan_header *); 6173204368Syongari vh->evl_encap_proto = htons(ETHERTYPE_VLAN); 6174204368Syongari vh->evl_tag = htons(l2fhdr->l2_fhdr_vlan_tag); 6175204368Syongari m0->m_pkthdr.len += ETHER_VLAN_ENCAP_LEN; 6176204368Syongari m0->m_len += ETHER_VLAN_ENCAP_LEN; 6177204368Syongari } 6178176448Sdavidch } 6179157642Sps 6180189325Sdavidch /* Increment received packet statistics. */ 6181176448Sdavidch ifp->if_ipackets++; 6182157642Sps 6183157642Spsbce_rx_int_next_rx: 6184176448Sdavidch sw_rx_cons = NEXT_RX_BD(sw_rx_cons); 6185157642Sps 6186170392Sdavidch /* If we have a packet, pass it up the stack */ 6187176448Sdavidch if (m0) { 6188170392Sdavidch /* Make sure we don't lose our place when we release the lock. */ 6189178132Sdavidch sc->rx_cons = sw_rx_cons; 6190198320Sstas#ifdef BCE_JUMBO_HDRSPLIT 6191179771Sdavidch sc->pg_cons = sw_pg_cons; 6192179695Sdavidch#endif 6193170392Sdavidch 6194169271Sdavidch BCE_UNLOCK(sc); 6195176448Sdavidch (*ifp->if_input)(ifp, m0); 6196170392Sdavidch BCE_LOCK(sc); 6197179771Sdavidch 6198170392Sdavidch /* Recover our place. */ 6199178132Sdavidch sw_rx_cons = sc->rx_cons; 6200198320Sstas#ifdef BCE_JUMBO_HDRSPLIT 6201179771Sdavidch sw_pg_cons = sc->pg_cons; 6202179695Sdavidch#endif 6203170392Sdavidch } 6204170392Sdavidch 6205157642Sps /* Refresh hw_cons to see if there's new work */ 6206176448Sdavidch if (sw_rx_cons == hw_rx_cons) 6207176448Sdavidch hw_rx_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc); 6208157642Sps } 6209157642Sps 6210176448Sdavidch /* No new packets to process. Refill the RX and page chains and exit. */ 6211198320Sstas#ifdef BCE_JUMBO_HDRSPLIT 6212176448Sdavidch sc->pg_cons = sw_pg_cons; 6213179771Sdavidch bce_fill_pg_chain(sc); 6214179695Sdavidch#endif 6215176448Sdavidch 6216176448Sdavidch sc->rx_cons = sw_rx_cons; 6217171667Sdavidch bce_fill_rx_chain(sc); 6218171667Sdavidch 6219192281Sdelphij /* Prepare the page chain pages to be accessed by the NIC. */ 6220157642Sps for (int i = 0; i < RX_PAGES; i++) 6221157642Sps bus_dmamap_sync(sc->rx_bd_chain_tag, 6222157642Sps sc->rx_bd_chain_map[i], BUS_DMASYNC_PREWRITE); 6223157642Sps 6224198320Sstas#ifdef BCE_JUMBO_HDRSPLIT 6225176448Sdavidch for (int i = 0; i < PG_PAGES; i++) 6226176448Sdavidch bus_dmamap_sync(sc->pg_bd_chain_tag, 6227179771Sdavidch sc->pg_bd_chain_map[i], BUS_DMASYNC_PREWRITE); 6228179695Sdavidch#endif 6229176448Sdavidch 6230179771Sdavidch DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): rx_prod = 0x%04X, " 6231157642Sps "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n", 6232178132Sdavidch __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq); 6233179771Sdavidch DBEXIT(BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 6234157642Sps} 6235157642Sps 6236157642Sps 6237157642Sps/****************************************************************************/ 6238178132Sdavidch/* Reads the transmit consumer value from the status block (skipping over */ 6239178132Sdavidch/* chain page pointer if necessary). */ 6240178132Sdavidch/* */ 6241178132Sdavidch/* Returns: */ 6242178132Sdavidch/* hw_cons */ 6243178132Sdavidch/****************************************************************************/ 6244178132Sdavidchstatic inline u16 6245178132Sdavidchbce_get_hw_tx_cons(struct bce_softc *sc) 6246178132Sdavidch{ 6247182293Sdavidch u16 hw_cons; 6248178132Sdavidch 6249182293Sdavidch mb(); 6250182293Sdavidch hw_cons = sc->status_block->status_tx_quick_consumer_index0; 6251178132Sdavidch if ((hw_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 6252178132Sdavidch hw_cons++; 6253178132Sdavidch 6254178132Sdavidch return hw_cons; 6255178132Sdavidch} 6256178132Sdavidch 6257178132Sdavidch 6258178132Sdavidch/****************************************************************************/ 6259157642Sps/* Handles transmit completion interrupt events. */ 6260157642Sps/* */ 6261157642Sps/* Returns: */ 6262157642Sps/* Nothing. */ 6263157642Sps/****************************************************************************/ 6264157642Spsstatic void 6265157642Spsbce_tx_intr(struct bce_softc *sc) 6266157642Sps{ 6267157642Sps struct ifnet *ifp = sc->bce_ifp; 6268157642Sps u16 hw_tx_cons, sw_tx_cons, sw_tx_chain_cons; 6269178132Sdavidch 6270179771Sdavidch DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_INTR); 6271179771Sdavidch DBRUN(sc->tx_interrupts++); 6272179771Sdavidch DBPRINT(sc, BCE_EXTREME_SEND, "%s(enter): tx_prod = 0x%04X, " 6273179771Sdavidch "tx_cons = 0x%04X, tx_prod_bseq = 0x%08X\n", 6274179771Sdavidch __FUNCTION__, sc->tx_prod, sc->tx_cons, sc->tx_prod_bseq); 6275157642Sps 6276157642Sps BCE_LOCK_ASSERT(sc); 6277157642Sps 6278157642Sps /* Get the hardware's view of the TX consumer index. */ 6279178132Sdavidch hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc); 6280157642Sps sw_tx_cons = sc->tx_cons; 6281157642Sps 6282157642Sps /* Prevent speculative reads from getting ahead of the status block. */ 6283179771Sdavidch bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 6284157642Sps BUS_SPACE_BARRIER_READ); 6285157642Sps 6286157642Sps /* Cycle through any completed TX chain page entries. */ 6287157642Sps while (sw_tx_cons != hw_tx_cons) { 6288157642Sps#ifdef BCE_DEBUG 6289157642Sps struct tx_bd *txbd = NULL; 6290157642Sps#endif 6291157642Sps sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons); 6292157642Sps 6293157642Sps DBPRINT(sc, BCE_INFO_SEND, 6294157642Sps "%s(): hw_tx_cons = 0x%04X, sw_tx_cons = 0x%04X, " 6295157642Sps "sw_tx_chain_cons = 0x%04X\n", 6296157642Sps __FUNCTION__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons); 6297157642Sps 6298157642Sps DBRUNIF((sw_tx_chain_cons > MAX_TX_BD), 6299169271Sdavidch BCE_PRINTF("%s(%d): TX chain consumer out of range! " 6300179771Sdavidch " 0x%04X > 0x%04X\n", __FILE__, __LINE__, sw_tx_chain_cons, 6301157642Sps (int) MAX_TX_BD); 6302157642Sps bce_breakpoint(sc)); 6303157642Sps 6304176448Sdavidch DBRUN(txbd = &sc->tx_bd_chain[TX_PAGE(sw_tx_chain_cons)] 6305157642Sps [TX_IDX(sw_tx_chain_cons)]); 6306179771Sdavidch 6307157642Sps DBRUNIF((txbd == NULL), 6308179771Sdavidch BCE_PRINTF("%s(%d): Unexpected NULL tx_bd[0x%04X]!\n", 6309157642Sps __FILE__, __LINE__, sw_tx_chain_cons); 6310157642Sps bce_breakpoint(sc)); 6311157642Sps 6312176448Sdavidch DBRUNMSG(BCE_INFO_SEND, BCE_PRINTF("%s(): ", __FUNCTION__); 6313157642Sps bce_dump_txbd(sc, sw_tx_chain_cons, txbd)); 6314157642Sps 6315157642Sps /* 6316157642Sps * Free the associated mbuf. Remember 6317157642Sps * that only the last tx_bd of a packet 6318157642Sps * has an mbuf pointer and DMA map. 6319157642Sps */ 6320157642Sps if (sc->tx_mbuf_ptr[sw_tx_chain_cons] != NULL) { 6321157642Sps 6322157642Sps /* Validate that this is the last tx_bd. */ 6323164329Sscottl DBRUNIF((!(txbd->tx_bd_flags & TX_BD_FLAGS_END)), 6324169271Sdavidch BCE_PRINTF("%s(%d): tx_bd END flag not set but " 6325157642Sps "txmbuf == NULL!\n", __FILE__, __LINE__); 6326157642Sps bce_breakpoint(sc)); 6327157642Sps 6328179771Sdavidch DBRUNMSG(BCE_INFO_SEND, 6329169271Sdavidch BCE_PRINTF("%s(): Unloading map/freeing mbuf " 6330157642Sps "from tx_bd[0x%04X]\n", __FUNCTION__, sw_tx_chain_cons)); 6331157642Sps 6332157642Sps /* Unmap the mbuf. */ 6333157642Sps bus_dmamap_unload(sc->tx_mbuf_tag, 6334157642Sps sc->tx_mbuf_map[sw_tx_chain_cons]); 6335179771Sdavidch 6336157642Sps /* Free the mbuf. */ 6337157642Sps m_freem(sc->tx_mbuf_ptr[sw_tx_chain_cons]); 6338157642Sps sc->tx_mbuf_ptr[sw_tx_chain_cons] = NULL; 6339176448Sdavidch DBRUN(sc->debug_tx_mbuf_alloc--); 6340157642Sps 6341157642Sps ifp->if_opackets++; 6342157642Sps } 6343157642Sps 6344157642Sps sc->used_tx_bd--; 6345157642Sps sw_tx_cons = NEXT_TX_BD(sw_tx_cons); 6346157642Sps 6347157642Sps /* Refresh hw_cons to see if there's new work. */ 6348178132Sdavidch hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc); 6349157642Sps 6350157642Sps /* Prevent speculative reads from getting ahead of the status block. */ 6351179771Sdavidch bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 6352157642Sps BUS_SPACE_BARRIER_READ); 6353157642Sps } 6354157642Sps 6355157642Sps /* Clear the TX timeout timer. */ 6356165933Sdelphij sc->watchdog_timer = 0; 6357157642Sps 6358157642Sps /* Clear the tx hardware queue full flag. */ 6359169632Sdavidch if (sc->used_tx_bd < sc->max_tx_bd) { 6360169632Sdavidch DBRUNIF((ifp->if_drv_flags & IFF_DRV_OACTIVE), 6361179771Sdavidch DBPRINT(sc, BCE_INFO_SEND, 6362179771Sdavidch "%s(): Open TX chain! %d/%d (used/total)\n", 6363169632Sdavidch __FUNCTION__, sc->used_tx_bd, sc->max_tx_bd)); 6364157642Sps ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 6365157642Sps } 6366157642Sps 6367157642Sps sc->tx_cons = sw_tx_cons; 6368179771Sdavidch 6369179771Sdavidch DBPRINT(sc, BCE_EXTREME_SEND, "%s(exit): tx_prod = 0x%04X, " 6370179771Sdavidch "tx_cons = 0x%04X, tx_prod_bseq = 0x%08X\n", 6371179771Sdavidch __FUNCTION__, sc->tx_prod, sc->tx_cons, sc->tx_prod_bseq); 6372179771Sdavidch DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_INTR); 6373157642Sps} 6374157642Sps 6375157642Sps 6376157642Sps/****************************************************************************/ 6377157642Sps/* Disables interrupt generation. */ 6378157642Sps/* */ 6379157642Sps/* Returns: */ 6380157642Sps/* Nothing. */ 6381157642Sps/****************************************************************************/ 6382157642Spsstatic void 6383157642Spsbce_disable_intr(struct bce_softc *sc) 6384157642Sps{ 6385179771Sdavidch DBENTER(BCE_VERBOSE_INTR); 6386179771Sdavidch 6387179771Sdavidch REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT); 6388157642Sps REG_RD(sc, BCE_PCICFG_INT_ACK_CMD); 6389179771Sdavidch 6390179771Sdavidch DBEXIT(BCE_VERBOSE_INTR); 6391157642Sps} 6392157642Sps 6393157642Sps 6394157642Sps/****************************************************************************/ 6395157642Sps/* Enables interrupt generation. */ 6396157642Sps/* */ 6397157642Sps/* Returns: */ 6398157642Sps/* Nothing. */ 6399157642Sps/****************************************************************************/ 6400157642Spsstatic void 6401179771Sdavidchbce_enable_intr(struct bce_softc *sc, int coal_now) 6402157642Sps{ 6403179771Sdavidch DBENTER(BCE_VERBOSE_INTR); 6404157642Sps 6405157642Sps REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 6406157642Sps BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | 6407157642Sps BCE_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx); 6408157642Sps 6409157642Sps REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 6410157642Sps BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx); 6411157642Sps 6412179771Sdavidch /* Force an immediate interrupt (whether there is new data or not). */ 6413179771Sdavidch if (coal_now) 6414179771Sdavidch REG_WR(sc, BCE_HC_COMMAND, sc->hc_command | BCE_HC_COMMAND_COAL_NOW); 6415179771Sdavidch 6416179771Sdavidch DBEXIT(BCE_VERBOSE_INTR); 6417157642Sps} 6418157642Sps 6419157642Sps 6420157642Sps/****************************************************************************/ 6421157642Sps/* Handles controller initialization. */ 6422157642Sps/* */ 6423157642Sps/* Returns: */ 6424157642Sps/* Nothing. */ 6425157642Sps/****************************************************************************/ 6426157642Spsstatic void 6427157642Spsbce_init_locked(struct bce_softc *sc) 6428157642Sps{ 6429157642Sps struct ifnet *ifp; 6430176448Sdavidch u32 ether_mtu = 0; 6431157642Sps 6432179771Sdavidch DBENTER(BCE_VERBOSE_RESET); 6433157642Sps 6434157642Sps BCE_LOCK_ASSERT(sc); 6435157642Sps 6436157642Sps ifp = sc->bce_ifp; 6437157642Sps 6438157642Sps /* Check if the driver is still running and bail out if it is. */ 6439157642Sps if (ifp->if_drv_flags & IFF_DRV_RUNNING) 6440157642Sps goto bce_init_locked_exit; 6441157642Sps 6442157642Sps bce_stop(sc); 6443157642Sps 6444157642Sps if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) { 6445179771Sdavidch BCE_PRINTF("%s(%d): Controller reset failed!\n", 6446157642Sps __FILE__, __LINE__); 6447157642Sps goto bce_init_locked_exit; 6448157642Sps } 6449157642Sps 6450157642Sps if (bce_chipinit(sc)) { 6451179771Sdavidch BCE_PRINTF("%s(%d): Controller initialization failed!\n", 6452157642Sps __FILE__, __LINE__); 6453157642Sps goto bce_init_locked_exit; 6454157642Sps } 6455157642Sps 6456157642Sps if (bce_blockinit(sc)) { 6457179771Sdavidch BCE_PRINTF("%s(%d): Block initialization failed!\n", 6458157642Sps __FILE__, __LINE__); 6459157642Sps goto bce_init_locked_exit; 6460157642Sps } 6461157642Sps 6462157642Sps /* Load our MAC address. */ 6463157642Sps bcopy(IF_LLADDR(sc->bce_ifp), sc->eaddr, ETHER_ADDR_LEN); 6464157642Sps bce_set_mac_addr(sc); 6465157642Sps 6466182293Sdavidch /* 6467182293Sdavidch * Calculate and program the hardware Ethernet MTU 6468179771Sdavidch * size. Be generous on the receive if we have room. 6469179695Sdavidch */ 6470198320Sstas#ifdef BCE_JUMBO_HDRSPLIT 6471179695Sdavidch if (ifp->if_mtu <= (sc->rx_bd_mbuf_data_len + sc->pg_bd_mbuf_alloc_size)) 6472179695Sdavidch ether_mtu = sc->rx_bd_mbuf_data_len + sc->pg_bd_mbuf_alloc_size; 6473179771Sdavidch#else 6474179695Sdavidch if (ifp->if_mtu <= sc->rx_bd_mbuf_data_len) 6475179695Sdavidch ether_mtu = sc->rx_bd_mbuf_data_len; 6476179695Sdavidch#endif 6477178132Sdavidch else 6478179771Sdavidch ether_mtu = ifp->if_mtu; 6479178132Sdavidch 6480176448Sdavidch ether_mtu += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN; 6481157642Sps 6482179771Sdavidch DBPRINT(sc, BCE_INFO_MISC, "%s(): setting h/w mtu = %d\n", __FUNCTION__, 6483176448Sdavidch ether_mtu); 6484157642Sps 6485176448Sdavidch /* Program the mtu, enabling jumbo frame support if necessary. */ 6486176448Sdavidch if (ether_mtu > (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN)) 6487179771Sdavidch REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, 6488179771Sdavidch min(ether_mtu, BCE_MAX_JUMBO_ETHER_MTU) | 6489157642Sps BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA); 6490176448Sdavidch else 6491157642Sps REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, ether_mtu); 6492157642Sps 6493182293Sdavidch DBPRINT(sc, BCE_INFO_LOAD, 6494179771Sdavidch "%s(): rx_bd_mbuf_alloc_size = %d, rx_bce_mbuf_data_len = %d, " 6495189325Sdavidch "rx_bd_mbuf_align_pad = %d\n", __FUNCTION__, 6496189325Sdavidch sc->rx_bd_mbuf_alloc_size, sc->rx_bd_mbuf_data_len, 6497189325Sdavidch sc->rx_bd_mbuf_align_pad); 6498157642Sps 6499157642Sps /* Program appropriate promiscuous/multicast filtering. */ 6500157642Sps bce_set_rx_mode(sc); 6501157642Sps 6502198320Sstas#ifdef BCE_JUMBO_HDRSPLIT 6503189325Sdavidch DBPRINT(sc, BCE_INFO_LOAD, "%s(): pg_bd_mbuf_alloc_size = %d\n", 6504189325Sdavidch __FUNCTION__, sc->pg_bd_mbuf_alloc_size); 6505189325Sdavidch 6506176448Sdavidch /* Init page buffer descriptor chain. */ 6507179771Sdavidch bce_init_pg_chain(sc); 6508179695Sdavidch#endif 6509176448Sdavidch 6510157642Sps /* Init RX buffer descriptor chain. */ 6511157642Sps bce_init_rx_chain(sc); 6512179771Sdavidch 6513157642Sps /* Init TX buffer descriptor chain. */ 6514157642Sps bce_init_tx_chain(sc); 6515157642Sps 6516157642Sps /* Enable host interrupts. */ 6517179771Sdavidch bce_enable_intr(sc, 1); 6518157642Sps 6519165994Sjhb bce_ifmedia_upd_locked(ifp); 6520157642Sps 6521202717Sdavidch /* Let the OS know the driver is up and running. */ 6522157642Sps ifp->if_drv_flags |= IFF_DRV_RUNNING; 6523157642Sps ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 6524157642Sps 6525170810Sdavidch callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc); 6526157642Sps 6527157642Spsbce_init_locked_exit: 6528179771Sdavidch DBEXIT(BCE_VERBOSE_RESET); 6529157642Sps} 6530157642Sps 6531170392Sdavidch 6532169271Sdavidch/****************************************************************************/ 6533170392Sdavidch/* Initialize the controller just enough so that any management firmware */ 6534170810Sdavidch/* running on the device will continue to operate correctly. */ 6535169271Sdavidch/* */ 6536169271Sdavidch/* Returns: */ 6537169271Sdavidch/* Nothing. */ 6538169271Sdavidch/****************************************************************************/ 6539162474Sambriskostatic void 6540162474Sambriskobce_mgmt_init_locked(struct bce_softc *sc) 6541162474Sambrisko{ 6542162474Sambrisko struct ifnet *ifp; 6543157642Sps 6544179771Sdavidch DBENTER(BCE_VERBOSE_RESET); 6545162474Sambrisko 6546162474Sambrisko BCE_LOCK_ASSERT(sc); 6547162474Sambrisko 6548170810Sdavidch /* Bail out if management firmware is not running. */ 6549170810Sdavidch if (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG)) { 6550179771Sdavidch DBPRINT(sc, BCE_VERBOSE_SPECIAL, 6551170810Sdavidch "No management firmware running...\n"); 6552162474Sambrisko goto bce_mgmt_init_locked_exit; 6553170810Sdavidch } 6554162474Sambrisko 6555170810Sdavidch ifp = sc->bce_ifp; 6556162474Sambrisko 6557162474Sambrisko /* Enable all critical blocks in the MAC. */ 6558179771Sdavidch REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT); 6559162474Sambrisko REG_RD(sc, BCE_MISC_ENABLE_SET_BITS); 6560162474Sambrisko DELAY(20); 6561162474Sambrisko 6562165994Sjhb bce_ifmedia_upd_locked(ifp); 6563179771Sdavidch 6564162474Sambriskobce_mgmt_init_locked_exit: 6565179771Sdavidch DBEXIT(BCE_VERBOSE_RESET); 6566162474Sambrisko} 6567162474Sambrisko 6568162474Sambrisko 6569157642Sps/****************************************************************************/ 6570157642Sps/* Handles controller initialization when called from an unlocked routine. */ 6571157642Sps/* */ 6572157642Sps/* Returns: */ 6573157642Sps/* Nothing. */ 6574157642Sps/****************************************************************************/ 6575157642Spsstatic void 6576157642Spsbce_init(void *xsc) 6577157642Sps{ 6578178132Sdavidch struct bce_softc *sc = xsc; 6579157642Sps 6580179771Sdavidch DBENTER(BCE_VERBOSE_RESET); 6581179771Sdavidch 6582157642Sps BCE_LOCK(sc); 6583157642Sps bce_init_locked(sc); 6584157642Sps BCE_UNLOCK(sc); 6585179771Sdavidch 6586179771Sdavidch DBEXIT(BCE_VERBOSE_RESET); 6587157642Sps} 6588157642Sps 6589157642Sps 6590204373Syongaristatic struct mbuf * 6591204373Syongaribce_tso_setup(struct bce_softc *sc, struct mbuf **m_head, u16 *flags) 6592204373Syongari{ 6593204373Syongari struct mbuf *m; 6594204373Syongari struct ether_header *eh; 6595204373Syongari struct ip *ip; 6596204373Syongari struct tcphdr *th; 6597204373Syongari u16 etype; 6598204373Syongari int hdr_len, ip_hlen = 0, tcp_hlen = 0, ip_len = 0; 6599204373Syongari 6600204373Syongari DBRUN(sc->requested_tso_frames++); 6601204373Syongari /* Controller requires to monify mbuf chains. */ 6602204373Syongari if (M_WRITABLE(*m_head) == 0) { 6603204373Syongari m = m_dup(*m_head, M_DONTWAIT); 6604204373Syongari m_freem(*m_head); 6605204373Syongari if (m == NULL) { 6606204373Syongari sc->mbuf_alloc_failed_count++; 6607204373Syongari *m_head = NULL; 6608204373Syongari return (NULL); 6609204373Syongari } 6610204373Syongari *m_head = m; 6611204373Syongari } 6612204373Syongari /* 6613204373Syongari * For TSO the controller needs two pieces of info, 6614204373Syongari * the MSS and the IP+TCP options length. 6615204373Syongari */ 6616204373Syongari m = m_pullup(*m_head, sizeof(struct ether_header) + sizeof(struct ip)); 6617204373Syongari if (m == NULL) { 6618204373Syongari *m_head = NULL; 6619204373Syongari return (NULL); 6620204373Syongari } 6621204373Syongari eh = mtod(m, struct ether_header *); 6622204373Syongari etype = ntohs(eh->ether_type); 6623204373Syongari 6624204373Syongari /* Check for supported TSO Ethernet types (only IPv4 for now) */ 6625204373Syongari switch (etype) { 6626204373Syongari case ETHERTYPE_IP: 6627204373Syongari ip = (struct ip *)(m->m_data + sizeof(struct ether_header)); 6628204373Syongari /* TSO only supported for TCP protocol. */ 6629204373Syongari if (ip->ip_p != IPPROTO_TCP) { 6630204373Syongari BCE_PRINTF("%s(%d): TSO enabled for non-TCP frame!.\n", 6631204373Syongari __FILE__, __LINE__); 6632204373Syongari m_freem(*m_head); 6633204373Syongari *m_head = NULL; 6634204373Syongari return (NULL); 6635204373Syongari } 6636204373Syongari 6637204373Syongari /* Get IP header length in bytes (min 20) */ 6638204373Syongari ip_hlen = ip->ip_hl << 2; 6639204373Syongari m = m_pullup(*m_head, sizeof(struct ether_header) + ip_hlen + 6640204373Syongari sizeof(struct tcphdr)); 6641204373Syongari if (m == NULL) { 6642204373Syongari *m_head = NULL; 6643204373Syongari return (NULL); 6644204373Syongari } 6645204373Syongari 6646204373Syongari /* Get the TCP header length in bytes (min 20) */ 6647204373Syongari th = (struct tcphdr *)((caddr_t)ip + ip_hlen); 6648204373Syongari tcp_hlen = (th->th_off << 2); 6649204373Syongari 6650204373Syongari /* Make sure all IP/TCP options live in the same buffer. */ 6651204373Syongari m = m_pullup(*m_head, sizeof(struct ether_header)+ ip_hlen + 6652204373Syongari tcp_hlen); 6653204373Syongari if (m == NULL) { 6654204373Syongari *m_head = NULL; 6655204373Syongari return (NULL); 6656204373Syongari } 6657204373Syongari 6658204373Syongari /* IP header length and checksum will be calc'd by hardware */ 6659204373Syongari ip_len = ip->ip_len; 6660204373Syongari ip->ip_len = 0; 6661204373Syongari ip->ip_sum = 0; 6662204373Syongari break; 6663204373Syongari case ETHERTYPE_IPV6: 6664204373Syongari BCE_PRINTF("%s(%d): TSO over IPv6 not supported!.\n", 6665204373Syongari __FILE__, __LINE__); 6666204373Syongari m_freem(*m_head); 6667204373Syongari *m_head = NULL; 6668204373Syongari return (NULL); 6669204373Syongari /* NOT REACHED */ 6670204373Syongari default: 6671204373Syongari BCE_PRINTF("%s(%d): TSO enabled for unsupported protocol!.\n", 6672204373Syongari __FILE__, __LINE__); 6673204373Syongari m_freem(*m_head); 6674204373Syongari *m_head = NULL; 6675204373Syongari return (NULL); 6676204373Syongari } 6677204373Syongari 6678204373Syongari hdr_len = sizeof(struct ether_header) + ip_hlen + tcp_hlen; 6679204373Syongari 6680204373Syongari DBPRINT(sc, BCE_EXTREME_SEND, "%s(): hdr_len = %d, e_hlen = %d, " 6681204373Syongari "ip_hlen = %d, tcp_hlen = %d, ip_len = %d\n", 6682204373Syongari __FUNCTION__, hdr_len, sizeof(struct ether_header), ip_hlen, 6683204373Syongari tcp_hlen, ip_len); 6684204373Syongari 6685204373Syongari /* Set the LSO flag in the TX BD */ 6686204373Syongari *flags |= TX_BD_FLAGS_SW_LSO; 6687204373Syongari /* Set the length of IP + TCP options (in 32 bit words) */ 6688204373Syongari *flags |= (((ip_hlen + tcp_hlen - sizeof(struct ip) - 6689204373Syongari sizeof(struct tcphdr)) >> 2) << 8); 6690204373Syongari return (*m_head); 6691204373Syongari} 6692204373Syongari 6693204373Syongari 6694157642Sps/****************************************************************************/ 6695157642Sps/* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */ 6696157642Sps/* memory visible to the controller. */ 6697157642Sps/* */ 6698157642Sps/* Returns: */ 6699157642Sps/* 0 for success, positive value for failure. */ 6700171667Sdavidch/* Modified: */ 6701171667Sdavidch/* m_head: May be set to NULL if MBUF is excessively fragmented. */ 6702157642Sps/****************************************************************************/ 6703157642Spsstatic int 6704163393Sscottlbce_tx_encap(struct bce_softc *sc, struct mbuf **m_head) 6705157642Sps{ 6706163393Sscottl bus_dma_segment_t segs[BCE_MAX_SEGMENTS]; 6707163393Sscottl bus_dmamap_t map; 6708163393Sscottl struct tx_bd *txbd = NULL; 6709163393Sscottl struct mbuf *m0; 6710204373Syongari u16 prod, chain_prod, mss = 0, vlan_tag = 0, flags = 0; 6711170392Sdavidch u32 prod_bseq; 6712157642Sps 6713163393Sscottl#ifdef BCE_DEBUG 6714163393Sscottl u16 debug_prod; 6715163393Sscottl#endif 6716163393Sscottl int i, error, nsegs, rc = 0; 6717163393Sscottl 6718179771Sdavidch DBENTER(BCE_VERBOSE_SEND); 6719179771Sdavidch DBPRINT(sc, BCE_INFO_SEND, 6720179771Sdavidch "%s(enter): tx_prod = 0x%04X, tx_chain_prod = %04X, " 6721179771Sdavidch "tx_prod_bseq = 0x%08X\n", 6722179771Sdavidch __FUNCTION__, sc->tx_prod, (u16) TX_CHAIN_IDX(sc->tx_prod), 6723179771Sdavidch sc->tx_prod_bseq); 6724179771Sdavidch 6725157642Sps /* Transfer any checksum offload flags to the bd. */ 6726163393Sscottl m0 = *m_head; 6727163393Sscottl if (m0->m_pkthdr.csum_flags) { 6728170392Sdavidch if (m0->m_pkthdr.csum_flags & CSUM_TSO) { 6729204373Syongari m0 = bce_tso_setup(sc, m_head, &flags); 6730204373Syongari if (m0 == NULL) 6731204373Syongari goto bce_tx_encap_exit; 6732170392Sdavidch mss = htole16(m0->m_pkthdr.tso_segsz); 6733204373Syongari } else { 6734204373Syongari if (m0->m_pkthdr.csum_flags & CSUM_IP) 6735204373Syongari flags |= TX_BD_FLAGS_IP_CKSUM; 6736204373Syongari if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 6737204373Syongari flags |= TX_BD_FLAGS_TCP_UDP_CKSUM; 6738169632Sdavidch } 6739157642Sps } 6740157642Sps 6741157642Sps /* Transfer any VLAN tags to the bd. */ 6742164329Sscottl if (m0->m_flags & M_VLANTAG) { 6743164329Sscottl flags |= TX_BD_FLAGS_VLAN_TAG; 6744164329Sscottl vlan_tag = m0->m_pkthdr.ether_vtag; 6745164329Sscottl } 6746157642Sps 6747157642Sps /* Map the mbuf into DMAable memory. */ 6748163393Sscottl prod = sc->tx_prod; 6749163393Sscottl chain_prod = TX_CHAIN_IDX(prod); 6750163339Sscottl map = sc->tx_mbuf_map[chain_prod]; 6751157642Sps 6752157642Sps /* Map the mbuf into our DMA address space. */ 6753163393Sscottl error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag, map, m0, 6754163393Sscottl segs, &nsegs, BUS_DMA_NOWAIT); 6755157642Sps 6756170392Sdavidch /* Check if the DMA mapping was successful */ 6757163393Sscottl if (error == EFBIG) { 6758179771Sdavidch 6759189325Sdavidch sc->fragmented_mbuf_count++; 6760170392Sdavidch 6761171667Sdavidch /* Try to defrag the mbuf. */ 6762204372Syongari m0 = m_collapse(*m_head, M_DONTWAIT, BCE_MAX_SEGMENTS); 6763171667Sdavidch if (m0 == NULL) { 6764169632Sdavidch /* Defrag was unsuccessful */ 6765163499Sscottl m_freem(*m_head); 6766163499Sscottl *m_head = NULL; 6767189325Sdavidch sc->mbuf_alloc_failed_count++; 6768179771Sdavidch rc = ENOBUFS; 6769179771Sdavidch goto bce_tx_encap_exit; 6770163499Sscottl } 6771159411Sdavidch 6772170392Sdavidch /* Defrag was successful, try mapping again */ 6773163499Sscottl *m_head = m0; 6774163499Sscottl error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag, map, m0, 6775163499Sscottl segs, &nsegs, BUS_DMA_NOWAIT); 6776163499Sscottl 6777163393Sscottl /* Still getting an error after a defrag. */ 6778163499Sscottl if (error == ENOMEM) { 6779171667Sdavidch /* Insufficient DMA buffers available. */ 6780189325Sdavidch sc->dma_map_addr_tx_failed_count++; 6781179771Sdavidch rc = error; 6782179771Sdavidch goto bce_tx_encap_exit; 6783163499Sscottl } else if (error != 0) { 6784171667Sdavidch /* Still can't map the mbuf, release it and return an error. */ 6785169271Sdavidch BCE_PRINTF( 6786169632Sdavidch "%s(%d): Unknown error mapping mbuf into TX chain!\n", 6787163393Sscottl __FILE__, __LINE__); 6788163499Sscottl m_freem(m0); 6789163499Sscottl *m_head = NULL; 6790189325Sdavidch sc->dma_map_addr_tx_failed_count++; 6791179771Sdavidch rc = ENOBUFS; 6792179771Sdavidch goto bce_tx_encap_exit; 6793163393Sscottl } 6794163499Sscottl } else if (error == ENOMEM) { 6795171667Sdavidch /* Insufficient DMA buffers available. */ 6796189325Sdavidch sc->dma_map_addr_tx_failed_count++; 6797179771Sdavidch rc = error; 6798179771Sdavidch goto bce_tx_encap_exit; 6799163499Sscottl } else if (error != 0) { 6800163499Sscottl m_freem(m0); 6801163499Sscottl *m_head = NULL; 6802189325Sdavidch sc->dma_map_addr_tx_failed_count++; 6803179771Sdavidch rc = error; 6804179771Sdavidch goto bce_tx_encap_exit; 6805163499Sscottl } 6806170392Sdavidch 6807169632Sdavidch /* Make sure there's room in the chain */ 6808169632Sdavidch if (nsegs > (sc->max_tx_bd - sc->used_tx_bd)) { 6809163558Sscottl bus_dmamap_unload(sc->tx_mbuf_tag, map); 6810179771Sdavidch rc = ENOBUFS; 6811179771Sdavidch goto bce_tx_encap_exit; 6812163558Sscottl } 6813163393Sscottl 6814163393Sscottl /* prod points to an empty tx_bd at this point. */ 6815163393Sscottl prod_bseq = sc->tx_prod_bseq; 6816163393Sscottl 6817163393Sscottl#ifdef BCE_DEBUG 6818163393Sscottl debug_prod = chain_prod; 6819163393Sscottl#endif 6820163393Sscottl 6821163393Sscottl DBPRINT(sc, BCE_INFO_SEND, 6822178132Sdavidch "%s(start): prod = 0x%04X, chain_prod = 0x%04X, " 6823163393Sscottl "prod_bseq = 0x%08X\n", 6824164968Sjhb __FUNCTION__, prod, chain_prod, prod_bseq); 6825163393Sscottl 6826163393Sscottl /* 6827163393Sscottl * Cycle through each mbuf segment that makes up 6828163393Sscottl * the outgoing frame, gathering the mapping info 6829176448Sdavidch * for that segment and creating a tx_bd for 6830163393Sscottl * the mbuf. 6831163393Sscottl */ 6832163393Sscottl for (i = 0; i < nsegs ; i++) { 6833163393Sscottl 6834163393Sscottl chain_prod = TX_CHAIN_IDX(prod); 6835163393Sscottl txbd= &sc->tx_bd_chain[TX_PAGE(chain_prod)][TX_IDX(chain_prod)]; 6836163393Sscottl 6837163393Sscottl txbd->tx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[i].ds_addr)); 6838163393Sscottl txbd->tx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[i].ds_addr)); 6839169632Sdavidch txbd->tx_bd_mss_nbytes = htole32(mss << 16) | htole16(segs[i].ds_len); 6840164329Sscottl txbd->tx_bd_vlan_tag = htole16(vlan_tag); 6841164329Sscottl txbd->tx_bd_flags = htole16(flags); 6842163393Sscottl prod_bseq += segs[i].ds_len; 6843163393Sscottl if (i == 0) 6844170392Sdavidch txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_START); 6845163393Sscottl prod = NEXT_TX_BD(prod); 6846157642Sps } 6847157642Sps 6848163393Sscottl /* Set the END flag on the last TX buffer descriptor. */ 6849164329Sscottl txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_END); 6850163393Sscottl 6851179771Sdavidch DBRUNMSG(BCE_EXTREME_SEND, bce_dump_tx_chain(sc, debug_prod, nsegs)); 6852163393Sscottl 6853163393Sscottl DBPRINT(sc, BCE_INFO_SEND, 6854178132Sdavidch "%s( end ): prod = 0x%04X, chain_prod = 0x%04X, " 6855163393Sscottl "prod_bseq = 0x%08X\n", 6856163393Sscottl __FUNCTION__, prod, chain_prod, prod_bseq); 6857163393Sscottl 6858157642Sps /* 6859164327Sjdp * Ensure that the mbuf pointer for this transmission 6860157642Sps * is placed at the array index of the last 6861157642Sps * descriptor in this chain. This is done 6862179771Sdavidch * because a single map is used for all 6863157642Sps * segments of the mbuf and we don't want to 6864164327Sjdp * unload the map before all of the segments 6865157642Sps * have been freed. 6866157642Sps */ 6867163393Sscottl sc->tx_mbuf_ptr[chain_prod] = m0; 6868163393Sscottl sc->used_tx_bd += nsegs; 6869157642Sps 6870170392Sdavidch /* Update some debug statistic counters */ 6871179771Sdavidch DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark), 6872170392Sdavidch sc->tx_hi_watermark = sc->used_tx_bd); 6873169632Sdavidch DBRUNIF((sc->used_tx_bd == sc->max_tx_bd), sc->tx_full_count++); 6874176448Sdavidch DBRUNIF(sc->debug_tx_mbuf_alloc++); 6875157642Sps 6876179771Sdavidch DBRUNMSG(BCE_EXTREME_SEND, bce_dump_tx_mbuf_chain(sc, chain_prod, 1)); 6877157642Sps 6878164327Sjdp /* prod points to the next free tx_bd at this point. */ 6879163393Sscottl sc->tx_prod = prod; 6880163393Sscottl sc->tx_prod_bseq = prod_bseq; 6881157642Sps 6882179771Sdavidch DBPRINT(sc, BCE_INFO_SEND, 6883179771Sdavidch "%s(exit): prod = 0x%04X, chain_prod = %04X, " 6884179771Sdavidch "prod_bseq = 0x%08X\n", 6885179771Sdavidch __FUNCTION__, sc->tx_prod, (u16) TX_CHAIN_IDX(sc->tx_prod), 6886179771Sdavidch sc->tx_prod_bseq); 6887179771Sdavidch 6888179771Sdavidchbce_tx_encap_exit: 6889179771Sdavidch DBEXIT(BCE_VERBOSE_SEND); 6890157642Sps return(rc); 6891157642Sps} 6892157642Sps 6893157642Sps 6894157642Sps/****************************************************************************/ 6895157642Sps/* Main transmit routine when called from another routine with a lock. */ 6896157642Sps/* */ 6897157642Sps/* Returns: */ 6898157642Sps/* Nothing. */ 6899157642Sps/****************************************************************************/ 6900157642Spsstatic void 6901157642Spsbce_start_locked(struct ifnet *ifp) 6902157642Sps{ 6903157642Sps struct bce_softc *sc = ifp->if_softc; 6904157642Sps struct mbuf *m_head = NULL; 6905157642Sps int count = 0; 6906157642Sps u16 tx_prod, tx_chain_prod; 6907157642Sps 6908179771Sdavidch DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 6909179771Sdavidch 6910179771Sdavidch BCE_LOCK_ASSERT(sc); 6911179771Sdavidch 6912157642Sps /* prod points to the next free tx_bd. */ 6913157642Sps tx_prod = sc->tx_prod; 6914157642Sps tx_chain_prod = TX_CHAIN_IDX(tx_prod); 6915157642Sps 6916157642Sps DBPRINT(sc, BCE_INFO_SEND, 6917178132Sdavidch "%s(enter): tx_prod = 0x%04X, tx_chain_prod = 0x%04X, " 6918157642Sps "tx_prod_bseq = 0x%08X\n", 6919163339Sscottl __FUNCTION__, tx_prod, tx_chain_prod, sc->tx_prod_bseq); 6920157642Sps 6921178132Sdavidch /* If there's no link or the transmit queue is empty then just exit. */ 6922178132Sdavidch if (!sc->bce_link) { 6923179771Sdavidch DBPRINT(sc, BCE_INFO_SEND, "%s(): No link.\n", 6924178132Sdavidch __FUNCTION__); 6925178132Sdavidch goto bce_start_locked_exit; 6926178132Sdavidch } 6927178132Sdavidch 6928178132Sdavidch if (IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 6929179771Sdavidch DBPRINT(sc, BCE_INFO_SEND, "%s(): Transmit queue empty.\n", 6930178132Sdavidch __FUNCTION__); 6931178132Sdavidch goto bce_start_locked_exit; 6932178132Sdavidch } 6933178132Sdavidch 6934164327Sjdp /* 6935169632Sdavidch * Keep adding entries while there is space in the ring. 6936164327Sjdp */ 6937169632Sdavidch while (sc->used_tx_bd < sc->max_tx_bd) { 6938157642Sps 6939157642Sps /* Check for any frames to send. */ 6940157642Sps IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 6941179771Sdavidch 6942179771Sdavidch /* Stop when the transmit queue is empty. */ 6943157642Sps if (m_head == NULL) 6944157642Sps break; 6945157642Sps 6946157642Sps /* 6947157642Sps * Pack the data into the transmit ring. If we 6948157642Sps * don't have room, place the mbuf back at the 6949157642Sps * head of the queue and set the OACTIVE flag 6950157642Sps * to wait for the NIC to drain the chain. 6951157642Sps */ 6952163393Sscottl if (bce_tx_encap(sc, &m_head)) { 6953179771Sdavidch /* No room, put the frame back on the transmit queue. */ 6954171667Sdavidch if (m_head != NULL) 6955171667Sdavidch IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 6956157642Sps ifp->if_drv_flags |= IFF_DRV_OACTIVE; 6957157642Sps DBPRINT(sc, BCE_INFO_SEND, 6958179771Sdavidch "TX chain is closed for business! Total tx_bd used = %d\n", 6959157642Sps sc->used_tx_bd); 6960157642Sps break; 6961157642Sps } 6962157642Sps 6963157642Sps count++; 6964157642Sps 6965157642Sps /* Send a copy of the frame to any BPF listeners. */ 6966167190Scsjp ETHER_BPF_MTAP(ifp, m_head); 6967157642Sps } 6968157642Sps 6969179771Sdavidch /* Exit if no packets were dequeued. */ 6970157642Sps if (count == 0) { 6971179771Sdavidch DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): No packets were dequeued\n", 6972157642Sps __FUNCTION__); 6973157642Sps goto bce_start_locked_exit; 6974157642Sps } 6975157642Sps 6976179771Sdavidch DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): Inserted %d frames into send queue.\n", 6977179771Sdavidch __FUNCTION__, count); 6978157642Sps 6979179771Sdavidch REG_WR(sc, BCE_MQ_COMMAND, REG_RD(sc, BCE_MQ_COMMAND) | BCE_MQ_COMMAND_NO_MAP_ERROR); 6980157642Sps 6981182293Sdavidch /* Write the mailbox and tell the chip about the waiting tx_bd's. */ 6982182293Sdavidch DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): MB_GET_CID_ADDR(TX_CID) = 0x%08X; " 6983182293Sdavidch "BCE_L2MQ_TX_HOST_BIDX = 0x%08X, sc->tx_prod = 0x%04X\n", 6984182293Sdavidch __FUNCTION__, 6985182293Sdavidch MB_GET_CID_ADDR(TX_CID), BCE_L2MQ_TX_HOST_BIDX, sc->tx_prod); 6986182293Sdavidch REG_WR16(sc, MB_GET_CID_ADDR(TX_CID) + BCE_L2MQ_TX_HOST_BIDX, sc->tx_prod); 6987182293Sdavidch DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): MB_GET_CID_ADDR(TX_CID) = 0x%08X; " 6988182293Sdavidch "BCE_L2MQ_TX_HOST_BSEQ = 0x%08X, sc->tx_prod_bseq = 0x%04X\n", 6989182293Sdavidch __FUNCTION__, 6990182293Sdavidch MB_GET_CID_ADDR(TX_CID), BCE_L2MQ_TX_HOST_BSEQ, sc->tx_prod_bseq); 6991182293Sdavidch REG_WR(sc, MB_GET_CID_ADDR(TX_CID) + BCE_L2MQ_TX_HOST_BSEQ, sc->tx_prod_bseq); 6992182293Sdavidch 6993157642Sps /* Set the tx timeout. */ 6994165933Sdelphij sc->watchdog_timer = BCE_TX_TIMEOUT; 6995157642Sps 6996182293Sdavidch DBRUNMSG(BCE_VERBOSE_SEND, bce_dump_ctx(sc, TX_CID)); 6997179771Sdavidch DBRUNMSG(BCE_VERBOSE_SEND, bce_dump_mq_regs(sc)); 6998179771Sdavidch 6999157642Spsbce_start_locked_exit: 7000179771Sdavidch DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 7001157642Sps return; 7002157642Sps} 7003157642Sps 7004157642Sps 7005157642Sps/****************************************************************************/ 7006157642Sps/* Main transmit routine when called from another routine without a lock. */ 7007157642Sps/* */ 7008157642Sps/* Returns: */ 7009157642Sps/* Nothing. */ 7010157642Sps/****************************************************************************/ 7011157642Spsstatic void 7012157642Spsbce_start(struct ifnet *ifp) 7013157642Sps{ 7014157642Sps struct bce_softc *sc = ifp->if_softc; 7015157642Sps 7016179771Sdavidch DBENTER(BCE_VERBOSE_SEND); 7017179771Sdavidch 7018157642Sps BCE_LOCK(sc); 7019157642Sps bce_start_locked(ifp); 7020157642Sps BCE_UNLOCK(sc); 7021179771Sdavidch 7022179771Sdavidch DBEXIT(BCE_VERBOSE_SEND); 7023157642Sps} 7024157642Sps 7025157642Sps 7026157642Sps/****************************************************************************/ 7027157642Sps/* Handles any IOCTL calls from the operating system. */ 7028157642Sps/* */ 7029157642Sps/* Returns: */ 7030157642Sps/* 0 for success, positive value for failure. */ 7031157642Sps/****************************************************************************/ 7032157642Spsstatic int 7033157642Spsbce_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 7034157642Sps{ 7035157642Sps struct bce_softc *sc = ifp->if_softc; 7036157642Sps struct ifreq *ifr = (struct ifreq *) data; 7037157642Sps struct mii_data *mii; 7038204370Syongari int mask, error = 0, reinit; 7039157642Sps 7040179771Sdavidch DBENTER(BCE_VERBOSE_MISC); 7041179771Sdavidch 7042157642Sps switch(command) { 7043157642Sps 7044170810Sdavidch /* Set the interface MTU. */ 7045157642Sps case SIOCSIFMTU: 7046157642Sps /* Check that the MTU setting is supported. */ 7047179771Sdavidch if ((ifr->ifr_mtu < BCE_MIN_MTU) || 7048157642Sps (ifr->ifr_mtu > BCE_MAX_JUMBO_MTU)) { 7049157642Sps error = EINVAL; 7050157642Sps break; 7051157642Sps } 7052157642Sps 7053170810Sdavidch DBPRINT(sc, BCE_INFO_MISC, 7054179771Sdavidch "SIOCSIFMTU: Changing MTU from %d to %d\n", 7055170810Sdavidch (int) ifp->if_mtu, (int) ifr->ifr_mtu); 7056157642Sps 7057160526Sjhb BCE_LOCK(sc); 7058157642Sps ifp->if_mtu = ifr->ifr_mtu; 7059204370Syongari reinit = 0; 7060204370Syongari if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 7061204370Syongari /* 7062204370Syongari * Because allocation size is used in RX 7063204370Syongari * buffer allocation, stop controller if 7064204370Syongari * it is already running. 7065204370Syongari */ 7066204370Syongari bce_stop(sc); 7067204370Syongari reinit = 1; 7068204370Syongari } 7069198320Sstas#ifdef BCE_JUMBO_HDRSPLIT 7070179771Sdavidch /* No buffer allocation size changes are necessary. */ 7071179771Sdavidch#else 7072179771Sdavidch /* Recalculate our buffer allocation sizes. */ 7073179771Sdavidch if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN) > MCLBYTES) { 7074179695Sdavidch sc->rx_bd_mbuf_alloc_size = MJUM9BYTES; 7075179695Sdavidch sc->rx_bd_mbuf_align_pad = roundup2(MJUM9BYTES, 16) - MJUM9BYTES; 7076179771Sdavidch sc->rx_bd_mbuf_data_len = sc->rx_bd_mbuf_alloc_size - 7077179771Sdavidch sc->rx_bd_mbuf_align_pad; 7078179771Sdavidch } else { 7079179695Sdavidch sc->rx_bd_mbuf_alloc_size = MCLBYTES; 7080179695Sdavidch sc->rx_bd_mbuf_align_pad = roundup2(MCLBYTES, 16) - MCLBYTES; 7081179771Sdavidch sc->rx_bd_mbuf_data_len = sc->rx_bd_mbuf_alloc_size - 7082179771Sdavidch sc->rx_bd_mbuf_align_pad; 7083179695Sdavidch } 7084179771Sdavidch#endif 7085179771Sdavidch 7086204370Syongari if (reinit != 0) 7087204370Syongari bce_init_locked(sc); 7088160526Sjhb BCE_UNLOCK(sc); 7089157642Sps break; 7090157642Sps 7091170810Sdavidch /* Set interface flags. */ 7092157642Sps case SIOCSIFFLAGS: 7093170810Sdavidch DBPRINT(sc, BCE_VERBOSE_SPECIAL, "Received SIOCSIFFLAGS\n"); 7094157642Sps 7095157642Sps BCE_LOCK(sc); 7096157642Sps 7097157642Sps /* Check if the interface is up. */ 7098157642Sps if (ifp->if_flags & IFF_UP) { 7099160315Sambrisko if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 7100170810Sdavidch /* Change promiscuous/multicast flags as necessary. */ 7101160315Sambrisko bce_set_rx_mode(sc); 7102160315Sambrisko } else { 7103160315Sambrisko /* Start the HW */ 7104160315Sambrisko bce_init_locked(sc); 7105160315Sambrisko } 7106157642Sps } else { 7107170810Sdavidch /* The interface is down, check if driver is running. */ 7108157642Sps if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 7109157642Sps bce_stop(sc); 7110170810Sdavidch 7111170810Sdavidch /* If MFW is running, restart the controller a bit. */ 7112170810Sdavidch if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 7113170810Sdavidch bce_reset(sc, BCE_DRV_MSG_CODE_RESET); 7114170810Sdavidch bce_chipinit(sc); 7115170810Sdavidch bce_mgmt_init_locked(sc); 7116170810Sdavidch } 7117157642Sps } 7118157642Sps } 7119157642Sps 7120157642Sps BCE_UNLOCK(sc); 7121157642Sps 7122157642Sps break; 7123157642Sps 7124157642Sps /* Add/Delete multicast address */ 7125157642Sps case SIOCADDMULTI: 7126157642Sps case SIOCDELMULTI: 7127170810Sdavidch DBPRINT(sc, BCE_VERBOSE_MISC, "Received SIOCADDMULTI/SIOCDELMULTI\n"); 7128157642Sps 7129160526Sjhb BCE_LOCK(sc); 7130204370Syongari if (ifp->if_drv_flags & IFF_DRV_RUNNING) 7131157642Sps bce_set_rx_mode(sc); 7132160526Sjhb BCE_UNLOCK(sc); 7133157642Sps 7134157642Sps break; 7135157642Sps 7136157642Sps /* Set/Get Interface media */ 7137157642Sps case SIOCSIFMEDIA: 7138157642Sps case SIOCGIFMEDIA: 7139170810Sdavidch DBPRINT(sc, BCE_VERBOSE_MISC, "Received SIOCSIFMEDIA/SIOCGIFMEDIA\n"); 7140157642Sps 7141166261Sdwhite mii = device_get_softc(sc->bce_miibus); 7142166261Sdwhite error = ifmedia_ioctl(ifp, ifr, 7143166261Sdwhite &mii->mii_media, command); 7144157642Sps break; 7145157642Sps 7146157642Sps /* Set interface capability */ 7147157642Sps case SIOCSIFCAP: 7148157642Sps mask = ifr->ifr_reqcap ^ ifp->if_capenable; 7149170810Sdavidch DBPRINT(sc, BCE_INFO_MISC, "Received SIOCSIFCAP = 0x%08X\n", (u32) mask); 7150157642Sps 7151204371Syongari /* Toggle the TX checksum capabilities enable flag. */ 7152204371Syongari if (mask & IFCAP_TXCSUM && 7153204371Syongari ifp->if_capabilities & IFCAP_TXCSUM) { 7154157642Sps ifp->if_capenable ^= IFCAP_TXCSUM; 7155157642Sps if (IFCAP_TXCSUM & ifp->if_capenable) 7156204371Syongari ifp->if_hwassist |= BCE_IF_HWASSIST; 7157157642Sps else 7158204371Syongari ifp->if_hwassist &= ~BCE_IF_HWASSIST; 7159157642Sps } 7160157642Sps 7161157642Sps /* Toggle the RX checksum capabilities enable flag. */ 7162204371Syongari if (mask & IFCAP_RXCSUM && 7163204371Syongari ifp->if_capabilities & IFCAP_RXCSUM) 7164157642Sps ifp->if_capenable ^= IFCAP_RXCSUM; 7165157642Sps 7166169632Sdavidch /* Toggle the TSO capabilities enable flag. */ 7167204371Syongari if (bce_tso_enable && (mask & IFCAP_TSO4) && 7168204371Syongari ifp->if_capabilities & IFCAP_TSO4) { 7169169632Sdavidch ifp->if_capenable ^= IFCAP_TSO4; 7170204371Syongari if (IFCAP_TSO4 & ifp->if_capenable) 7171204371Syongari ifp->if_hwassist |= CSUM_TSO; 7172169632Sdavidch else 7173204371Syongari ifp->if_hwassist &= ~CSUM_TSO; 7174169632Sdavidch } 7175169632Sdavidch 7176204371Syongari if (mask & IFCAP_VLAN_HWCSUM && 7177204371Syongari ifp->if_capabilities & IFCAP_VLAN_HWCSUM) 7178204371Syongari ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 7179204371Syongari 7180204374Syongari if ((mask & IFCAP_VLAN_HWTSO) != 0 && 7181204374Syongari (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 7182204374Syongari ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 7183204368Syongari /* 7184204368Syongari * Don't actually disable VLAN tag stripping as 7185204368Syongari * management firmware (ASF/IPMI/UMP) requires the 7186204368Syongari * feature. If VLAN tag stripping is disabled driver 7187204368Syongari * will manually reconstruct the VLAN frame by 7188204368Syongari * appending stripped VLAN tag. 7189204368Syongari */ 7190204368Syongari if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 7191204374Syongari (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING)) { 7192204368Syongari ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 7193204374Syongari if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 7194204374Syongari == 0) 7195204374Syongari ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 7196204374Syongari } 7197204368Syongari VLAN_CAPABILITIES(ifp); 7198157642Sps break; 7199157642Sps default: 7200157642Sps /* We don't know how to handle the IOCTL, pass it on. */ 7201157642Sps error = ether_ioctl(ifp, command, data); 7202157642Sps break; 7203157642Sps } 7204157642Sps 7205179771Sdavidch DBEXIT(BCE_VERBOSE_MISC); 7206157642Sps return(error); 7207157642Sps} 7208157642Sps 7209157642Sps 7210157642Sps/****************************************************************************/ 7211157642Sps/* Transmit timeout handler. */ 7212157642Sps/* */ 7213157642Sps/* Returns: */ 7214157642Sps/* Nothing. */ 7215157642Sps/****************************************************************************/ 7216157642Spsstatic void 7217165933Sdelphijbce_watchdog(struct bce_softc *sc) 7218157642Sps{ 7219179771Sdavidch DBENTER(BCE_EXTREME_SEND); 7220157642Sps 7221165933Sdelphij BCE_LOCK_ASSERT(sc); 7222165933Sdelphij 7223179771Sdavidch /* If the watchdog timer hasn't expired then just exit. */ 7224165933Sdelphij if (sc->watchdog_timer == 0 || --sc->watchdog_timer) 7225179771Sdavidch goto bce_watchdog_exit; 7226165933Sdelphij 7227179771Sdavidch /* If pause frames are active then don't reset the hardware. */ 7228179771Sdavidch /* ToDo: Should we reset the timer here? */ 7229179771Sdavidch if (REG_RD(sc, BCE_EMAC_TX_STATUS) & BCE_EMAC_TX_STATUS_XOFFED) 7230179771Sdavidch goto bce_watchdog_exit; 7231165933Sdelphij 7232179771Sdavidch BCE_PRINTF("%s(%d): Watchdog timeout occurred, resetting!\n", 7233157642Sps __FILE__, __LINE__); 7234157642Sps 7235179771Sdavidch DBRUNMSG(BCE_INFO, 7236170810Sdavidch bce_dump_driver_state(sc); 7237179771Sdavidch bce_dump_status_block(sc); 7238179771Sdavidch bce_dump_stats_block(sc); 7239179771Sdavidch bce_dump_ftqs(sc); 7240179771Sdavidch bce_dump_txp_state(sc, 0); 7241179771Sdavidch bce_dump_rxp_state(sc, 0); 7242179771Sdavidch bce_dump_tpat_state(sc, 0); 7243179771Sdavidch bce_dump_cp_state(sc, 0); 7244179771Sdavidch bce_dump_com_state(sc, 0)); 7245170810Sdavidch 7246179771Sdavidch DBRUN(bce_breakpoint(sc)); 7247157642Sps 7248165933Sdelphij sc->bce_ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 7249157642Sps 7250160526Sjhb bce_init_locked(sc); 7251165933Sdelphij sc->bce_ifp->if_oerrors++; 7252157642Sps 7253179771Sdavidchbce_watchdog_exit: 7254179771Sdavidch DBEXIT(BCE_EXTREME_SEND); 7255157642Sps} 7256157642Sps 7257157642Sps 7258157642Sps/* 7259157642Sps * Interrupt handler. 7260157642Sps */ 7261157642Sps/****************************************************************************/ 7262157642Sps/* Main interrupt entry point. Verifies that the controller generated the */ 7263157642Sps/* interrupt and then calls a separate routine for handle the various */ 7264157642Sps/* interrupt causes (PHY, TX, RX). */ 7265157642Sps/* */ 7266157642Sps/* Returns: */ 7267157642Sps/* 0 for success, positive value for failure. */ 7268157642Sps/****************************************************************************/ 7269157642Spsstatic void 7270157642Spsbce_intr(void *xsc) 7271157642Sps{ 7272157642Sps struct bce_softc *sc; 7273157642Sps struct ifnet *ifp; 7274157642Sps u32 status_attn_bits; 7275178132Sdavidch u16 hw_rx_cons, hw_tx_cons; 7276157642Sps 7277157642Sps sc = xsc; 7278157642Sps ifp = sc->bce_ifp; 7279157642Sps 7280179771Sdavidch DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 7281179771Sdavidch DBRUNMSG(BCE_VERBOSE_INTR, bce_dump_status_block(sc)); 7282179771Sdavidch 7283157642Sps BCE_LOCK(sc); 7284157642Sps 7285176448Sdavidch DBRUN(sc->interrupts_generated++); 7286157642Sps 7287192281Sdelphij /* Synchnorize before we read from interface's status block */ 7288157642Sps bus_dmamap_sync(sc->status_tag, sc->status_map, 7289192281Sdelphij BUS_DMASYNC_POSTREAD); 7290157642Sps 7291157642Sps /* 7292157642Sps * If the hardware status block index 7293157642Sps * matches the last value read by the 7294157642Sps * driver and we haven't asserted our 7295157642Sps * interrupt then there's nothing to do. 7296157642Sps */ 7297179771Sdavidch if ((sc->status_block->status_idx == sc->last_status_idx) && 7298179771Sdavidch (REG_RD(sc, BCE_PCICFG_MISC_STATUS) & BCE_PCICFG_MISC_STATUS_INTA_VALUE)) { 7299179771Sdavidch DBPRINT(sc, BCE_VERBOSE_INTR, "%s(): Spurious interrupt.\n", 7300179771Sdavidch __FUNCTION__); 7301179771Sdavidch goto bce_intr_exit; 7302179771Sdavidch } 7303157642Sps 7304157642Sps /* Ack the interrupt and stop others from occuring. */ 7305157642Sps REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 7306157642Sps BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM | 7307157642Sps BCE_PCICFG_INT_ACK_CMD_MASK_INT); 7308157642Sps 7309178132Sdavidch /* Check if the hardware has finished any work. */ 7310178132Sdavidch hw_rx_cons = bce_get_hw_rx_cons(sc); 7311178132Sdavidch hw_tx_cons = bce_get_hw_tx_cons(sc); 7312178132Sdavidch 7313157642Sps /* Keep processing data as long as there is work to do. */ 7314157642Sps for (;;) { 7315157642Sps 7316157642Sps status_attn_bits = sc->status_block->status_attn_bits; 7317157642Sps 7318189325Sdavidch DBRUNIF(DB_RANDOMTRUE(unexpected_attention_sim_control), 7319189325Sdavidch BCE_PRINTF("Simulating unexpected status attention bit set."); 7320189325Sdavidch sc->unexpected_attention_sim_count++; 7321189325Sdavidch status_attn_bits = status_attn_bits | STATUS_ATTN_BITS_PARITY_ERROR); 7322157642Sps 7323157642Sps /* Was it a link change interrupt? */ 7324157642Sps if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != 7325185593Sdelphij (sc->status_block->status_attn_bits_ack & STATUS_ATTN_BITS_LINK_STATE)) { 7326157642Sps bce_phy_intr(sc); 7327157642Sps 7328185593Sdelphij /* Clear any transient status updates during link state change. */ 7329185593Sdelphij REG_WR(sc, BCE_HC_COMMAND, 7330185593Sdelphij sc->hc_command | BCE_HC_COMMAND_COAL_NOW_WO_INT); 7331185593Sdelphij REG_RD(sc, BCE_HC_COMMAND); 7332185593Sdelphij } 7333179771Sdavidch 7334157642Sps /* If any other attention is asserted then the chip is toast. */ 7335157642Sps if (((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) != 7336179771Sdavidch (sc->status_block->status_attn_bits_ack & 7337157642Sps ~STATUS_ATTN_BITS_LINK_STATE))) { 7338157642Sps 7339189325Sdavidch sc->unexpected_attention_count++; 7340157642Sps 7341179771Sdavidch BCE_PRINTF("%s(%d): Fatal attention detected: 0x%08X\n", 7342157642Sps __FILE__, __LINE__, sc->status_block->status_attn_bits); 7343157642Sps 7344179771Sdavidch DBRUNMSG(BCE_FATAL, 7345189325Sdavidch if (unexpected_attention_sim_control == 0) 7346157642Sps bce_breakpoint(sc)); 7347157642Sps 7348157642Sps bce_init_locked(sc); 7349157642Sps goto bce_intr_exit; 7350157642Sps } 7351157642Sps 7352157642Sps /* Check for any completed RX frames. */ 7353178132Sdavidch if (hw_rx_cons != sc->hw_rx_cons) 7354157642Sps bce_rx_intr(sc); 7355157642Sps 7356157642Sps /* Check for any completed TX frames. */ 7357178132Sdavidch if (hw_tx_cons != sc->hw_tx_cons) 7358157642Sps bce_tx_intr(sc); 7359157642Sps 7360157642Sps /* Save the status block index value for use during the next interrupt. */ 7361157642Sps sc->last_status_idx = sc->status_block->status_idx; 7362157642Sps 7363157642Sps /* Prevent speculative reads from getting ahead of the status block. */ 7364179771Sdavidch bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 7365157642Sps BUS_SPACE_BARRIER_READ); 7366157642Sps 7367157642Sps /* If there's no work left then exit the interrupt service routine. */ 7368178132Sdavidch hw_rx_cons = bce_get_hw_rx_cons(sc); 7369178132Sdavidch hw_tx_cons = bce_get_hw_tx_cons(sc); 7370178132Sdavidch 7371178132Sdavidch if ((hw_rx_cons == sc->hw_rx_cons) && (hw_tx_cons == sc->hw_tx_cons)) 7372157642Sps break; 7373179771Sdavidch 7374157642Sps } 7375157642Sps 7376157642Sps bus_dmamap_sync(sc->status_tag, sc->status_map, 7377192281Sdelphij BUS_DMASYNC_PREREAD); 7378157642Sps 7379157642Sps /* Re-enable interrupts. */ 7380179771Sdavidch bce_enable_intr(sc, 0); 7381157642Sps 7382157642Sps /* Handle any frames that arrived while handling the interrupt. */ 7383157642Sps if (ifp->if_drv_flags & IFF_DRV_RUNNING && !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 7384157642Sps bce_start_locked(ifp); 7385157642Sps 7386157642Spsbce_intr_exit: 7387157642Sps BCE_UNLOCK(sc); 7388179771Sdavidch 7389179771Sdavidch DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 7390157642Sps} 7391157642Sps 7392157642Sps 7393157642Sps/****************************************************************************/ 7394157642Sps/* Programs the various packet receive modes (broadcast and multicast). */ 7395157642Sps/* */ 7396157642Sps/* Returns: */ 7397157642Sps/* Nothing. */ 7398157642Sps/****************************************************************************/ 7399157642Spsstatic void 7400157642Spsbce_set_rx_mode(struct bce_softc *sc) 7401157642Sps{ 7402157642Sps struct ifnet *ifp; 7403157642Sps struct ifmultiaddr *ifma; 7404166153Sscottl u32 hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 7405157642Sps u32 rx_mode, sort_mode; 7406157642Sps int h, i; 7407157642Sps 7408179771Sdavidch DBENTER(BCE_VERBOSE_MISC); 7409179771Sdavidch 7410157642Sps BCE_LOCK_ASSERT(sc); 7411157642Sps 7412157642Sps ifp = sc->bce_ifp; 7413157642Sps 7414157642Sps /* Initialize receive mode default settings. */ 7415157642Sps rx_mode = sc->rx_mode & ~(BCE_EMAC_RX_MODE_PROMISCUOUS | 7416157642Sps BCE_EMAC_RX_MODE_KEEP_VLAN_TAG); 7417157642Sps sort_mode = 1 | BCE_RPM_SORT_USER0_BC_EN; 7418157642Sps 7419157642Sps /* 7420157642Sps * ASF/IPMI/UMP firmware requires that VLAN tag stripping 7421157642Sps * be enbled. 7422157642Sps */ 7423157642Sps if (!(BCE_IF_CAPABILITIES & IFCAP_VLAN_HWTAGGING) && 7424157642Sps (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG))) 7425157642Sps rx_mode |= BCE_EMAC_RX_MODE_KEEP_VLAN_TAG; 7426157642Sps 7427157642Sps /* 7428157642Sps * Check for promiscuous, all multicast, or selected 7429157642Sps * multicast address filtering. 7430157642Sps */ 7431157642Sps if (ifp->if_flags & IFF_PROMISC) { 7432170810Sdavidch DBPRINT(sc, BCE_INFO_MISC, "Enabling promiscuous mode.\n"); 7433157642Sps 7434157642Sps /* Enable promiscuous mode. */ 7435157642Sps rx_mode |= BCE_EMAC_RX_MODE_PROMISCUOUS; 7436157642Sps sort_mode |= BCE_RPM_SORT_USER0_PROM_EN; 7437157642Sps } else if (ifp->if_flags & IFF_ALLMULTI) { 7438170810Sdavidch DBPRINT(sc, BCE_INFO_MISC, "Enabling all multicast mode.\n"); 7439157642Sps 7440157642Sps /* Enable all multicast addresses. */ 7441157642Sps for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) { 7442157642Sps REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), 0xffffffff); 7443157642Sps } 7444157642Sps sort_mode |= BCE_RPM_SORT_USER0_MC_EN; 7445157642Sps } else { 7446157642Sps /* Accept one or more multicast(s). */ 7447170810Sdavidch DBPRINT(sc, BCE_INFO_MISC, "Enabling selective multicast mode.\n"); 7448157642Sps 7449195049Srwatson if_maddr_rlock(ifp); 7450157642Sps TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 7451157642Sps if (ifma->ifma_addr->sa_family != AF_LINK) 7452157642Sps continue; 7453157642Sps h = ether_crc32_le(LLADDR((struct sockaddr_dl *) 7454166153Sscottl ifma->ifma_addr), ETHER_ADDR_LEN) & 0xFF; 7455166153Sscottl hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F); 7456157642Sps } 7457195049Srwatson if_maddr_runlock(ifp); 7458157642Sps 7459166153Sscottl for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) 7460157642Sps REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), hashes[i]); 7461157642Sps 7462157642Sps sort_mode |= BCE_RPM_SORT_USER0_MC_HSH_EN; 7463157642Sps } 7464157642Sps 7465157642Sps /* Only make changes if the recive mode has actually changed. */ 7466157642Sps if (rx_mode != sc->rx_mode) { 7467179771Sdavidch DBPRINT(sc, BCE_VERBOSE_MISC, "Enabling new receive mode: 0x%08X\n", 7468157642Sps rx_mode); 7469157642Sps 7470157642Sps sc->rx_mode = rx_mode; 7471157642Sps REG_WR(sc, BCE_EMAC_RX_MODE, rx_mode); 7472157642Sps } 7473157642Sps 7474157642Sps /* Disable and clear the exisitng sort before enabling a new sort. */ 7475157642Sps REG_WR(sc, BCE_RPM_SORT_USER0, 0x0); 7476157642Sps REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode); 7477157642Sps REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode | BCE_RPM_SORT_USER0_ENA); 7478179771Sdavidch 7479179771Sdavidch DBEXIT(BCE_VERBOSE_MISC); 7480157642Sps} 7481157642Sps 7482157642Sps 7483157642Sps/****************************************************************************/ 7484157642Sps/* Called periodically to updates statistics from the controllers */ 7485157642Sps/* statistics block. */ 7486157642Sps/* */ 7487157642Sps/* Returns: */ 7488157642Sps/* Nothing. */ 7489157642Sps/****************************************************************************/ 7490157642Spsstatic void 7491157642Spsbce_stats_update(struct bce_softc *sc) 7492157642Sps{ 7493157642Sps struct ifnet *ifp; 7494157642Sps struct statistics_block *stats; 7495157642Sps 7496179771Sdavidch DBENTER(BCE_EXTREME_MISC); 7497157642Sps 7498157642Sps ifp = sc->bce_ifp; 7499157642Sps 7500157642Sps stats = (struct statistics_block *) sc->stats_block; 7501157642Sps 7502179771Sdavidch /* 7503179771Sdavidch * Certain controllers don't report 7504157642Sps * carrier sense errors correctly. 7505179771Sdavidch * See errata E11_5708CA0_1165. 7506157642Sps */ 7507157642Sps if (!(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) && 7508157642Sps !(BCE_CHIP_ID(sc) == BCE_CHIP_ID_5708_A0)) 7509157642Sps ifp->if_oerrors += (u_long) stats->stat_Dot3StatsCarrierSenseErrors; 7510157642Sps 7511157642Sps /* 7512157642Sps * Update the sysctl statistics from the 7513157642Sps * hardware statistics. 7514157642Sps */ 7515179771Sdavidch sc->stat_IfHCInOctets = 7516179771Sdavidch ((u64) stats->stat_IfHCInOctets_hi << 32) + 7517157642Sps (u64) stats->stat_IfHCInOctets_lo; 7518157642Sps 7519157642Sps sc->stat_IfHCInBadOctets = 7520179771Sdavidch ((u64) stats->stat_IfHCInBadOctets_hi << 32) + 7521157642Sps (u64) stats->stat_IfHCInBadOctets_lo; 7522157642Sps 7523157642Sps sc->stat_IfHCOutOctets = 7524157642Sps ((u64) stats->stat_IfHCOutOctets_hi << 32) + 7525157642Sps (u64) stats->stat_IfHCOutOctets_lo; 7526157642Sps 7527157642Sps sc->stat_IfHCOutBadOctets = 7528157642Sps ((u64) stats->stat_IfHCOutBadOctets_hi << 32) + 7529157642Sps (u64) stats->stat_IfHCOutBadOctets_lo; 7530157642Sps 7531157642Sps sc->stat_IfHCInUcastPkts = 7532157642Sps ((u64) stats->stat_IfHCInUcastPkts_hi << 32) + 7533157642Sps (u64) stats->stat_IfHCInUcastPkts_lo; 7534157642Sps 7535157642Sps sc->stat_IfHCInMulticastPkts = 7536157642Sps ((u64) stats->stat_IfHCInMulticastPkts_hi << 32) + 7537157642Sps (u64) stats->stat_IfHCInMulticastPkts_lo; 7538157642Sps 7539157642Sps sc->stat_IfHCInBroadcastPkts = 7540157642Sps ((u64) stats->stat_IfHCInBroadcastPkts_hi << 32) + 7541157642Sps (u64) stats->stat_IfHCInBroadcastPkts_lo; 7542157642Sps 7543157642Sps sc->stat_IfHCOutUcastPkts = 7544157642Sps ((u64) stats->stat_IfHCOutUcastPkts_hi << 32) + 7545157642Sps (u64) stats->stat_IfHCOutUcastPkts_lo; 7546157642Sps 7547157642Sps sc->stat_IfHCOutMulticastPkts = 7548157642Sps ((u64) stats->stat_IfHCOutMulticastPkts_hi << 32) + 7549157642Sps (u64) stats->stat_IfHCOutMulticastPkts_lo; 7550157642Sps 7551157642Sps sc->stat_IfHCOutBroadcastPkts = 7552157642Sps ((u64) stats->stat_IfHCOutBroadcastPkts_hi << 32) + 7553157642Sps (u64) stats->stat_IfHCOutBroadcastPkts_lo; 7554157642Sps 7555157642Sps sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors = 7556157642Sps stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors; 7557157642Sps 7558157642Sps sc->stat_Dot3StatsCarrierSenseErrors = 7559157642Sps stats->stat_Dot3StatsCarrierSenseErrors; 7560157642Sps 7561179771Sdavidch sc->stat_Dot3StatsFCSErrors = 7562157642Sps stats->stat_Dot3StatsFCSErrors; 7563157642Sps 7564157642Sps sc->stat_Dot3StatsAlignmentErrors = 7565157642Sps stats->stat_Dot3StatsAlignmentErrors; 7566157642Sps 7567157642Sps sc->stat_Dot3StatsSingleCollisionFrames = 7568157642Sps stats->stat_Dot3StatsSingleCollisionFrames; 7569157642Sps 7570157642Sps sc->stat_Dot3StatsMultipleCollisionFrames = 7571157642Sps stats->stat_Dot3StatsMultipleCollisionFrames; 7572157642Sps 7573157642Sps sc->stat_Dot3StatsDeferredTransmissions = 7574157642Sps stats->stat_Dot3StatsDeferredTransmissions; 7575157642Sps 7576157642Sps sc->stat_Dot3StatsExcessiveCollisions = 7577157642Sps stats->stat_Dot3StatsExcessiveCollisions; 7578157642Sps 7579157642Sps sc->stat_Dot3StatsLateCollisions = 7580157642Sps stats->stat_Dot3StatsLateCollisions; 7581157642Sps 7582157642Sps sc->stat_EtherStatsCollisions = 7583157642Sps stats->stat_EtherStatsCollisions; 7584157642Sps 7585157642Sps sc->stat_EtherStatsFragments = 7586157642Sps stats->stat_EtherStatsFragments; 7587157642Sps 7588157642Sps sc->stat_EtherStatsJabbers = 7589157642Sps stats->stat_EtherStatsJabbers; 7590157642Sps 7591157642Sps sc->stat_EtherStatsUndersizePkts = 7592157642Sps stats->stat_EtherStatsUndersizePkts; 7593157642Sps 7594189325Sdavidch sc->stat_EtherStatsOversizePkts = 7595189325Sdavidch stats->stat_EtherStatsOversizePkts; 7596157642Sps 7597157642Sps sc->stat_EtherStatsPktsRx64Octets = 7598157642Sps stats->stat_EtherStatsPktsRx64Octets; 7599157642Sps 7600157642Sps sc->stat_EtherStatsPktsRx65Octetsto127Octets = 7601157642Sps stats->stat_EtherStatsPktsRx65Octetsto127Octets; 7602157642Sps 7603157642Sps sc->stat_EtherStatsPktsRx128Octetsto255Octets = 7604157642Sps stats->stat_EtherStatsPktsRx128Octetsto255Octets; 7605157642Sps 7606157642Sps sc->stat_EtherStatsPktsRx256Octetsto511Octets = 7607157642Sps stats->stat_EtherStatsPktsRx256Octetsto511Octets; 7608157642Sps 7609157642Sps sc->stat_EtherStatsPktsRx512Octetsto1023Octets = 7610157642Sps stats->stat_EtherStatsPktsRx512Octetsto1023Octets; 7611157642Sps 7612157642Sps sc->stat_EtherStatsPktsRx1024Octetsto1522Octets = 7613157642Sps stats->stat_EtherStatsPktsRx1024Octetsto1522Octets; 7614157642Sps 7615157642Sps sc->stat_EtherStatsPktsRx1523Octetsto9022Octets = 7616157642Sps stats->stat_EtherStatsPktsRx1523Octetsto9022Octets; 7617157642Sps 7618157642Sps sc->stat_EtherStatsPktsTx64Octets = 7619157642Sps stats->stat_EtherStatsPktsTx64Octets; 7620157642Sps 7621157642Sps sc->stat_EtherStatsPktsTx65Octetsto127Octets = 7622157642Sps stats->stat_EtherStatsPktsTx65Octetsto127Octets; 7623157642Sps 7624157642Sps sc->stat_EtherStatsPktsTx128Octetsto255Octets = 7625157642Sps stats->stat_EtherStatsPktsTx128Octetsto255Octets; 7626157642Sps 7627157642Sps sc->stat_EtherStatsPktsTx256Octetsto511Octets = 7628157642Sps stats->stat_EtherStatsPktsTx256Octetsto511Octets; 7629157642Sps 7630157642Sps sc->stat_EtherStatsPktsTx512Octetsto1023Octets = 7631157642Sps stats->stat_EtherStatsPktsTx512Octetsto1023Octets; 7632157642Sps 7633157642Sps sc->stat_EtherStatsPktsTx1024Octetsto1522Octets = 7634157642Sps stats->stat_EtherStatsPktsTx1024Octetsto1522Octets; 7635157642Sps 7636157642Sps sc->stat_EtherStatsPktsTx1523Octetsto9022Octets = 7637157642Sps stats->stat_EtherStatsPktsTx1523Octetsto9022Octets; 7638157642Sps 7639157642Sps sc->stat_XonPauseFramesReceived = 7640157642Sps stats->stat_XonPauseFramesReceived; 7641157642Sps 7642157642Sps sc->stat_XoffPauseFramesReceived = 7643157642Sps stats->stat_XoffPauseFramesReceived; 7644157642Sps 7645157642Sps sc->stat_OutXonSent = 7646157642Sps stats->stat_OutXonSent; 7647157642Sps 7648157642Sps sc->stat_OutXoffSent = 7649157642Sps stats->stat_OutXoffSent; 7650157642Sps 7651157642Sps sc->stat_FlowControlDone = 7652157642Sps stats->stat_FlowControlDone; 7653157642Sps 7654157642Sps sc->stat_MacControlFramesReceived = 7655157642Sps stats->stat_MacControlFramesReceived; 7656157642Sps 7657157642Sps sc->stat_XoffStateEntered = 7658157642Sps stats->stat_XoffStateEntered; 7659157642Sps 7660157642Sps sc->stat_IfInFramesL2FilterDiscards = 7661157642Sps stats->stat_IfInFramesL2FilterDiscards; 7662157642Sps 7663157642Sps sc->stat_IfInRuleCheckerDiscards = 7664157642Sps stats->stat_IfInRuleCheckerDiscards; 7665157642Sps 7666157642Sps sc->stat_IfInFTQDiscards = 7667157642Sps stats->stat_IfInFTQDiscards; 7668157642Sps 7669157642Sps sc->stat_IfInMBUFDiscards = 7670157642Sps stats->stat_IfInMBUFDiscards; 7671157642Sps 7672157642Sps sc->stat_IfInRuleCheckerP4Hit = 7673157642Sps stats->stat_IfInRuleCheckerP4Hit; 7674157642Sps 7675157642Sps sc->stat_CatchupInRuleCheckerDiscards = 7676157642Sps stats->stat_CatchupInRuleCheckerDiscards; 7677157642Sps 7678157642Sps sc->stat_CatchupInFTQDiscards = 7679157642Sps stats->stat_CatchupInFTQDiscards; 7680157642Sps 7681157642Sps sc->stat_CatchupInMBUFDiscards = 7682157642Sps stats->stat_CatchupInMBUFDiscards; 7683157642Sps 7684157642Sps sc->stat_CatchupInRuleCheckerP4Hit = 7685157642Sps stats->stat_CatchupInRuleCheckerP4Hit; 7686157642Sps 7687170392Sdavidch sc->com_no_buffers = REG_RD_IND(sc, 0x120084); 7688170392Sdavidch 7689179771Sdavidch /* 7690179771Sdavidch * Update the interface statistics from the 7691179771Sdavidch * hardware statistics. 7692179771Sdavidch */ 7693182293Sdavidch ifp->if_collisions = 7694182293Sdavidch (u_long) sc->stat_EtherStatsCollisions; 7695179771Sdavidch 7696182293Sdavidch /* ToDo: This method loses soft errors. */ 7697182293Sdavidch ifp->if_ierrors = 7698182293Sdavidch (u_long) sc->stat_EtherStatsUndersizePkts + 7699189325Sdavidch (u_long) sc->stat_EtherStatsOversizePkts + 7700182293Sdavidch (u_long) sc->stat_IfInMBUFDiscards + 7701182293Sdavidch (u_long) sc->stat_Dot3StatsAlignmentErrors + 7702182293Sdavidch (u_long) sc->stat_Dot3StatsFCSErrors + 7703182293Sdavidch (u_long) sc->stat_IfInRuleCheckerDiscards + 7704182293Sdavidch (u_long) sc->stat_IfInFTQDiscards + 7705182293Sdavidch (u_long) sc->com_no_buffers; 7706179771Sdavidch 7707182293Sdavidch /* ToDo: This method loses soft errors. */ 7708182293Sdavidch ifp->if_oerrors = 7709182293Sdavidch (u_long) sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors + 7710182293Sdavidch (u_long) sc->stat_Dot3StatsExcessiveCollisions + 7711182293Sdavidch (u_long) sc->stat_Dot3StatsLateCollisions; 7712179771Sdavidch 7713182293Sdavidch /* ToDo: Add additional statistics. */ 7714182293Sdavidch 7715179771Sdavidch DBEXIT(BCE_EXTREME_MISC); 7716157642Sps} 7717157642Sps 7718157642Sps 7719169271Sdavidch/****************************************************************************/ 7720170810Sdavidch/* Periodic function to notify the bootcode that the driver is still */ 7721170810Sdavidch/* present. */ 7722170810Sdavidch/* */ 7723170810Sdavidch/* Returns: */ 7724170810Sdavidch/* Nothing. */ 7725170810Sdavidch/****************************************************************************/ 7726170810Sdavidchstatic void 7727170810Sdavidchbce_pulse(void *xsc) 7728170810Sdavidch{ 7729170810Sdavidch struct bce_softc *sc = xsc; 7730170810Sdavidch u32 msg; 7731170810Sdavidch 7732179771Sdavidch DBENTER(BCE_EXTREME_MISC); 7733170810Sdavidch 7734170810Sdavidch BCE_LOCK_ASSERT(sc); 7735170810Sdavidch 7736170810Sdavidch /* Tell the firmware that the driver is still running. */ 7737170810Sdavidch msg = (u32) ++sc->bce_fw_drv_pulse_wr_seq; 7738194781Sdavidch bce_shmem_wr(sc, BCE_DRV_PULSE_MB, msg); 7739170810Sdavidch 7740170810Sdavidch /* Schedule the next pulse. */ 7741170810Sdavidch callout_reset(&sc->bce_pulse_callout, hz, bce_pulse, sc); 7742170810Sdavidch 7743179771Sdavidch DBEXIT(BCE_EXTREME_MISC); 7744170810Sdavidch} 7745170810Sdavidch 7746170810Sdavidch 7747170810Sdavidch/****************************************************************************/ 7748170392Sdavidch/* Periodic function to perform maintenance tasks. */ 7749169271Sdavidch/* */ 7750169271Sdavidch/* Returns: */ 7751169271Sdavidch/* Nothing. */ 7752169271Sdavidch/****************************************************************************/ 7753157642Spsstatic void 7754165933Sdelphijbce_tick(void *xsc) 7755157642Sps{ 7756165933Sdelphij struct bce_softc *sc = xsc; 7757169271Sdavidch struct mii_data *mii; 7758157642Sps struct ifnet *ifp; 7759157642Sps 7760157642Sps ifp = sc->bce_ifp; 7761157642Sps 7762179771Sdavidch DBENTER(BCE_EXTREME_MISC); 7763179771Sdavidch 7764157642Sps BCE_LOCK_ASSERT(sc); 7765157642Sps 7766176448Sdavidch /* Schedule the next tick. */ 7767176448Sdavidch callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc); 7768176448Sdavidch 7769157642Sps /* Update the statistics from the hardware statistics block. */ 7770157642Sps bce_stats_update(sc); 7771157642Sps 7772176448Sdavidch /* Top off the receive and page chains. */ 7773198320Sstas#ifdef BCE_JUMBO_HDRSPLIT 7774179771Sdavidch bce_fill_pg_chain(sc); 7775179695Sdavidch#endif 7776176448Sdavidch bce_fill_rx_chain(sc); 7777176448Sdavidch 7778169271Sdavidch /* Check that chip hasn't hung. */ 7779165933Sdelphij bce_watchdog(sc); 7780165933Sdelphij 7781157642Sps /* If link is up already up then we're done. */ 7782157642Sps if (sc->bce_link) 7783179771Sdavidch goto bce_tick_exit; 7784157642Sps 7785182293Sdavidch /* Link is down. Check what the PHY's doing. */ 7786157642Sps mii = device_get_softc(sc->bce_miibus); 7787157642Sps mii_tick(mii); 7788157642Sps 7789157642Sps /* Check if the link has come up. */ 7790179771Sdavidch if ((mii->mii_media_status & IFM_ACTIVE) && 7791179771Sdavidch (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)) { 7792179771Sdavidch DBPRINT(sc, BCE_VERBOSE_MISC, "%s(): Link up!\n", __FUNCTION__); 7793157642Sps sc->bce_link++; 7794157642Sps if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 7795157642Sps IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) && 7796157642Sps bootverbose) 7797179771Sdavidch BCE_PRINTF("Gigabit link up!\n"); 7798157642Sps /* Now that link is up, handle any outstanding TX traffic. */ 7799179771Sdavidch if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 7800179771Sdavidch DBPRINT(sc, BCE_VERBOSE_MISC, "%s(): Found pending TX traffic.\n", 7801179771Sdavidch __FUNCTION__); 7802157642Sps bce_start_locked(ifp); 7803179771Sdavidch } 7804157642Sps } 7805157642Sps 7806179771Sdavidchbce_tick_exit: 7807179771Sdavidch DBEXIT(BCE_EXTREME_MISC); 7808157642Sps return; 7809157642Sps} 7810157642Sps 7811157642Sps 7812157642Sps#ifdef BCE_DEBUG 7813157642Sps/****************************************************************************/ 7814157642Sps/* Allows the driver state to be dumped through the sysctl interface. */ 7815157642Sps/* */ 7816157642Sps/* Returns: */ 7817157642Sps/* 0 for success, positive value for failure. */ 7818157642Sps/****************************************************************************/ 7819157642Spsstatic int 7820157642Spsbce_sysctl_driver_state(SYSCTL_HANDLER_ARGS) 7821157642Sps{ 7822157642Sps int error; 7823157642Sps int result; 7824157642Sps struct bce_softc *sc; 7825157642Sps 7826157642Sps result = -1; 7827157642Sps error = sysctl_handle_int(oidp, &result, 0, req); 7828157642Sps 7829157642Sps if (error || !req->newptr) 7830157642Sps return (error); 7831157642Sps 7832157642Sps if (result == 1) { 7833157642Sps sc = (struct bce_softc *)arg1; 7834157642Sps bce_dump_driver_state(sc); 7835157642Sps } 7836157642Sps 7837157642Sps return error; 7838157642Sps} 7839157642Sps 7840157642Sps 7841157642Sps/****************************************************************************/ 7842157642Sps/* Allows the hardware state to be dumped through the sysctl interface. */ 7843157642Sps/* */ 7844157642Sps/* Returns: */ 7845157642Sps/* 0 for success, positive value for failure. */ 7846157642Sps/****************************************************************************/ 7847157642Spsstatic int 7848157642Spsbce_sysctl_hw_state(SYSCTL_HANDLER_ARGS) 7849157642Sps{ 7850157642Sps int error; 7851157642Sps int result; 7852157642Sps struct bce_softc *sc; 7853157642Sps 7854157642Sps result = -1; 7855157642Sps error = sysctl_handle_int(oidp, &result, 0, req); 7856157642Sps 7857157642Sps if (error || !req->newptr) 7858157642Sps return (error); 7859157642Sps 7860157642Sps if (result == 1) { 7861157642Sps sc = (struct bce_softc *)arg1; 7862157642Sps bce_dump_hw_state(sc); 7863157642Sps } 7864157642Sps 7865157642Sps return error; 7866157642Sps} 7867157642Sps 7868157642Sps 7869157642Sps/****************************************************************************/ 7870170810Sdavidch/* Allows the bootcode state to be dumped through the sysctl interface. */ 7871157642Sps/* */ 7872157642Sps/* Returns: */ 7873157642Sps/* 0 for success, positive value for failure. */ 7874157642Sps/****************************************************************************/ 7875157642Spsstatic int 7876170810Sdavidchbce_sysctl_bc_state(SYSCTL_HANDLER_ARGS) 7877170810Sdavidch{ 7878170810Sdavidch int error; 7879170810Sdavidch int result; 7880170810Sdavidch struct bce_softc *sc; 7881170810Sdavidch 7882170810Sdavidch result = -1; 7883170810Sdavidch error = sysctl_handle_int(oidp, &result, 0, req); 7884170810Sdavidch 7885170810Sdavidch if (error || !req->newptr) 7886170810Sdavidch return (error); 7887170810Sdavidch 7888170810Sdavidch if (result == 1) { 7889170810Sdavidch sc = (struct bce_softc *)arg1; 7890170810Sdavidch bce_dump_bc_state(sc); 7891170810Sdavidch } 7892170810Sdavidch 7893170810Sdavidch return error; 7894170810Sdavidch} 7895170810Sdavidch 7896170810Sdavidch 7897170810Sdavidch/****************************************************************************/ 7898170810Sdavidch/* Provides a sysctl interface to allow dumping the RX chain. */ 7899170810Sdavidch/* */ 7900170810Sdavidch/* Returns: */ 7901170810Sdavidch/* 0 for success, positive value for failure. */ 7902170810Sdavidch/****************************************************************************/ 7903170810Sdavidchstatic int 7904157642Spsbce_sysctl_dump_rx_chain(SYSCTL_HANDLER_ARGS) 7905157642Sps{ 7906157642Sps int error; 7907157642Sps int result; 7908157642Sps struct bce_softc *sc; 7909157642Sps 7910157642Sps result = -1; 7911157642Sps error = sysctl_handle_int(oidp, &result, 0, req); 7912157642Sps 7913157642Sps if (error || !req->newptr) 7914157642Sps return (error); 7915157642Sps 7916157642Sps if (result == 1) { 7917157642Sps sc = (struct bce_softc *)arg1; 7918176448Sdavidch bce_dump_rx_chain(sc, 0, TOTAL_RX_BD); 7919157642Sps } 7920157642Sps 7921157642Sps return error; 7922157642Sps} 7923157642Sps 7924157642Sps 7925157642Sps/****************************************************************************/ 7926170810Sdavidch/* Provides a sysctl interface to allow dumping the TX chain. */ 7927157642Sps/* */ 7928169271Sdavidch/* Returns: */ 7929169271Sdavidch/* 0 for success, positive value for failure. */ 7930169271Sdavidch/****************************************************************************/ 7931169271Sdavidchstatic int 7932169271Sdavidchbce_sysctl_dump_tx_chain(SYSCTL_HANDLER_ARGS) 7933169271Sdavidch{ 7934169271Sdavidch int error; 7935169271Sdavidch int result; 7936169271Sdavidch struct bce_softc *sc; 7937169271Sdavidch 7938169271Sdavidch result = -1; 7939169271Sdavidch error = sysctl_handle_int(oidp, &result, 0, req); 7940169271Sdavidch 7941169271Sdavidch if (error || !req->newptr) 7942169271Sdavidch return (error); 7943169271Sdavidch 7944169271Sdavidch if (result == 1) { 7945169271Sdavidch sc = (struct bce_softc *)arg1; 7946169271Sdavidch bce_dump_tx_chain(sc, 0, USABLE_TX_BD); 7947169271Sdavidch } 7948169271Sdavidch 7949169271Sdavidch return error; 7950169271Sdavidch} 7951169271Sdavidch 7952169271Sdavidch 7953198320Sstas#ifdef BCE_JUMBO_HDRSPLIT 7954169271Sdavidch/****************************************************************************/ 7955176448Sdavidch/* Provides a sysctl interface to allow dumping the page chain. */ 7956176448Sdavidch/* */ 7957176448Sdavidch/* Returns: */ 7958176448Sdavidch/* 0 for success, positive value for failure. */ 7959176448Sdavidch/****************************************************************************/ 7960176448Sdavidchstatic int 7961176448Sdavidchbce_sysctl_dump_pg_chain(SYSCTL_HANDLER_ARGS) 7962176448Sdavidch{ 7963176448Sdavidch int error; 7964176448Sdavidch int result; 7965176448Sdavidch struct bce_softc *sc; 7966176448Sdavidch 7967176448Sdavidch result = -1; 7968176448Sdavidch error = sysctl_handle_int(oidp, &result, 0, req); 7969176448Sdavidch 7970176448Sdavidch if (error || !req->newptr) 7971176448Sdavidch return (error); 7972176448Sdavidch 7973176448Sdavidch if (result == 1) { 7974176448Sdavidch sc = (struct bce_softc *)arg1; 7975176448Sdavidch bce_dump_pg_chain(sc, 0, TOTAL_PG_BD); 7976176448Sdavidch } 7977176448Sdavidch 7978176448Sdavidch return error; 7979179771Sdavidch} 7980179695Sdavidch#endif 7981176448Sdavidch 7982179771Sdavidch/****************************************************************************/ 7983179771Sdavidch/* Provides a sysctl interface to allow reading arbitrary NVRAM offsets in */ 7984179771Sdavidch/* the device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 7985179771Sdavidch/* */ 7986179771Sdavidch/* Returns: */ 7987179771Sdavidch/* 0 for success, positive value for failure. */ 7988179771Sdavidch/****************************************************************************/ 7989179771Sdavidchstatic int 7990179771Sdavidchbce_sysctl_nvram_read(SYSCTL_HANDLER_ARGS) 7991179771Sdavidch{ 7992179771Sdavidch struct bce_softc *sc = (struct bce_softc *)arg1; 7993179771Sdavidch int error; 7994182293Sdavidch u32 result; 7995182293Sdavidch u32 val[1]; 7996179771Sdavidch u8 *data = (u8 *) val; 7997176448Sdavidch 7998179771Sdavidch result = -1; 7999179771Sdavidch error = sysctl_handle_int(oidp, &result, 0, req); 8000179771Sdavidch if (error || (req->newptr == NULL)) 8001179771Sdavidch return (error); 8002179771Sdavidch 8003179771Sdavidch bce_nvram_read(sc, result, data, 4); 8004179771Sdavidch BCE_PRINTF("offset 0x%08X = 0x%08X\n", result, bce_be32toh(val[0])); 8005182293Sdavidch 8006179771Sdavidch return (error); 8007179771Sdavidch} 8008182293Sdavidch 8009182293Sdavidch 8010176448Sdavidch/****************************************************************************/ 8011170392Sdavidch/* Provides a sysctl interface to allow reading arbitrary registers in the */ 8012170392Sdavidch/* device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8013157642Sps/* */ 8014157642Sps/* Returns: */ 8015157642Sps/* 0 for success, positive value for failure. */ 8016157642Sps/****************************************************************************/ 8017157642Spsstatic int 8018169271Sdavidchbce_sysctl_reg_read(SYSCTL_HANDLER_ARGS) 8019169271Sdavidch{ 8020179771Sdavidch struct bce_softc *sc = (struct bce_softc *)arg1; 8021169271Sdavidch int error; 8022170810Sdavidch u32 val, result; 8023179771Sdavidch 8024169271Sdavidch result = -1; 8025169271Sdavidch error = sysctl_handle_int(oidp, &result, 0, req); 8026169271Sdavidch if (error || (req->newptr == NULL)) 8027169271Sdavidch return (error); 8028179771Sdavidch 8029170392Sdavidch /* Make sure the register is accessible. */ 8030169271Sdavidch if (result < 0x8000) { 8031169271Sdavidch val = REG_RD(sc, result); 8032169271Sdavidch BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val); 8033169271Sdavidch } else if (result < 0x0280000) { 8034169271Sdavidch val = REG_RD_IND(sc, result); 8035170392Sdavidch BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val); 8036169271Sdavidch } 8037179771Sdavidch 8038169271Sdavidch return (error); 8039169271Sdavidch} 8040170392Sdavidch 8041179771Sdavidch 8042169271Sdavidch/****************************************************************************/ 8043170392Sdavidch/* Provides a sysctl interface to allow reading arbitrary PHY registers in */ 8044170392Sdavidch/* the device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8045169632Sdavidch/* */ 8046169632Sdavidch/* Returns: */ 8047169632Sdavidch/* 0 for success, positive value for failure. */ 8048169632Sdavidch/****************************************************************************/ 8049169632Sdavidchstatic int 8050169632Sdavidchbce_sysctl_phy_read(SYSCTL_HANDLER_ARGS) 8051169632Sdavidch{ 8052170392Sdavidch struct bce_softc *sc; 8053169632Sdavidch device_t dev; 8054169632Sdavidch int error, result; 8055169632Sdavidch u16 val; 8056169632Sdavidch 8057169632Sdavidch result = -1; 8058169632Sdavidch error = sysctl_handle_int(oidp, &result, 0, req); 8059169632Sdavidch if (error || (req->newptr == NULL)) 8060169632Sdavidch return (error); 8061169632Sdavidch 8062170392Sdavidch /* Make sure the register is accessible. */ 8063169632Sdavidch if (result < 0x20) { 8064170392Sdavidch sc = (struct bce_softc *)arg1; 8065169632Sdavidch dev = sc->bce_dev; 8066169632Sdavidch val = bce_miibus_read_reg(dev, sc->bce_phy_addr, result); 8067169632Sdavidch BCE_PRINTF("phy 0x%02X = 0x%04X\n", result, val); 8068169632Sdavidch } 8069169632Sdavidch return (error); 8070169632Sdavidch} 8071170392Sdavidch 8072170392Sdavidch 8073169632Sdavidch/****************************************************************************/ 8074179771Sdavidch/* Provides a sysctl interface to allow reading a CID. */ 8075179771Sdavidch/* */ 8076179771Sdavidch/* Returns: */ 8077179771Sdavidch/* 0 for success, positive value for failure. */ 8078179771Sdavidch/****************************************************************************/ 8079179771Sdavidchstatic int 8080179771Sdavidchbce_sysctl_dump_ctx(SYSCTL_HANDLER_ARGS) 8081179771Sdavidch{ 8082179771Sdavidch struct bce_softc *sc; 8083179771Sdavidch int error; 8084179771Sdavidch u16 result; 8085179771Sdavidch 8086179771Sdavidch result = -1; 8087179771Sdavidch error = sysctl_handle_int(oidp, &result, 0, req); 8088179771Sdavidch if (error || (req->newptr == NULL)) 8089179771Sdavidch return (error); 8090179771Sdavidch 8091179771Sdavidch /* Make sure the register is accessible. */ 8092179771Sdavidch if (result <= TX_CID) { 8093179771Sdavidch sc = (struct bce_softc *)arg1; 8094179771Sdavidch bce_dump_ctx(sc, result); 8095179771Sdavidch } 8096179771Sdavidch 8097179771Sdavidch return (error); 8098179771Sdavidch} 8099179771Sdavidch 8100179771Sdavidch 8101179771Sdavidch /****************************************************************************/ 8102170392Sdavidch/* Provides a sysctl interface to forcing the driver to dump state and */ 8103169271Sdavidch/* enter the debugger. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8104169271Sdavidch/* */ 8105169271Sdavidch/* Returns: */ 8106169271Sdavidch/* 0 for success, positive value for failure. */ 8107169271Sdavidch/****************************************************************************/ 8108169271Sdavidchstatic int 8109157642Spsbce_sysctl_breakpoint(SYSCTL_HANDLER_ARGS) 8110157642Sps{ 8111157642Sps int error; 8112157642Sps int result; 8113157642Sps struct bce_softc *sc; 8114157642Sps 8115157642Sps result = -1; 8116157642Sps error = sysctl_handle_int(oidp, &result, 0, req); 8117157642Sps 8118157642Sps if (error || !req->newptr) 8119157642Sps return (error); 8120157642Sps 8121157642Sps if (result == 1) { 8122157642Sps sc = (struct bce_softc *)arg1; 8123157642Sps bce_breakpoint(sc); 8124157642Sps } 8125157642Sps 8126157642Sps return error; 8127157642Sps} 8128157642Sps#endif 8129157642Sps 8130157642Sps 8131157642Sps/****************************************************************************/ 8132157642Sps/* Adds any sysctl parameters for tuning or debugging purposes. */ 8133157642Sps/* */ 8134157642Sps/* Returns: */ 8135157642Sps/* 0 for success, positive value for failure. */ 8136157642Sps/****************************************************************************/ 8137157642Spsstatic void 8138157642Spsbce_add_sysctls(struct bce_softc *sc) 8139157642Sps{ 8140157642Sps struct sysctl_ctx_list *ctx; 8141157642Sps struct sysctl_oid_list *children; 8142157642Sps 8143179771Sdavidch DBENTER(BCE_VERBOSE_MISC); 8144179771Sdavidch 8145157642Sps ctx = device_get_sysctl_ctx(sc->bce_dev); 8146157642Sps children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bce_dev)); 8147157642Sps 8148157642Sps#ifdef BCE_DEBUG 8149179771Sdavidch SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8150189325Sdavidch "l2fhdr_error_sim_control", 8151189325Sdavidch CTLFLAG_RW, &l2fhdr_error_sim_control, 8152189325Sdavidch 0, "Debug control to force l2fhdr errors"); 8153189325Sdavidch 8154189325Sdavidch SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8155189325Sdavidch "l2fhdr_error_sim_count", 8156189325Sdavidch CTLFLAG_RD, &sc->l2fhdr_error_sim_count, 8157189325Sdavidch 0, "Number of simulated l2_fhdr errors"); 8158189325Sdavidch#endif 8159189325Sdavidch 8160189325Sdavidch SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8161189325Sdavidch "l2fhdr_error_count", 8162189325Sdavidch CTLFLAG_RD, &sc->l2fhdr_error_count, 8163189325Sdavidch 0, "Number of l2_fhdr errors"); 8164189325Sdavidch 8165189325Sdavidch#ifdef BCE_DEBUG 8166189325Sdavidch SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8167189325Sdavidch "mbuf_alloc_failed_sim_control", 8168189325Sdavidch CTLFLAG_RW, &mbuf_alloc_failed_sim_control, 8169189325Sdavidch 0, "Debug control to force mbuf allocation failures"); 8170189325Sdavidch 8171189325Sdavidch SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8172189325Sdavidch "mbuf_alloc_failed_sim_count", 8173189325Sdavidch CTLFLAG_RD, &sc->mbuf_alloc_failed_sim_count, 8174189325Sdavidch 0, "Number of simulated mbuf cluster allocation failures"); 8175189325Sdavidch#endif 8176189325Sdavidch 8177189325Sdavidch SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8178189325Sdavidch "mbuf_alloc_failed_count", 8179189325Sdavidch CTLFLAG_RD, &sc->mbuf_alloc_failed_count, 8180189325Sdavidch 0, "Number of mbuf allocation failures"); 8181189325Sdavidch 8182189325Sdavidch SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8183189325Sdavidch "fragmented_mbuf_count", 8184189325Sdavidch CTLFLAG_RD, &sc->fragmented_mbuf_count, 8185189325Sdavidch 0, "Number of fragmented mbufs"); 8186189325Sdavidch 8187189325Sdavidch#ifdef BCE_DEBUG 8188189325Sdavidch SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8189189325Sdavidch "dma_map_addr_failed_sim_control", 8190189325Sdavidch CTLFLAG_RW, &dma_map_addr_failed_sim_control, 8191189325Sdavidch 0, "Debug control to force DMA mapping failures"); 8192189325Sdavidch 8193189325Sdavidch /* ToDo: Figure out how to update this value in bce_dma_map_addr(). */ 8194189325Sdavidch SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8195189325Sdavidch "dma_map_addr_failed_sim_count", 8196189325Sdavidch CTLFLAG_RD, &sc->dma_map_addr_failed_sim_count, 8197189325Sdavidch 0, "Number of simulated DMA mapping failures"); 8198189325Sdavidch 8199189325Sdavidch#endif 8200189325Sdavidch 8201189325Sdavidch SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8202189325Sdavidch "dma_map_addr_rx_failed_count", 8203189325Sdavidch CTLFLAG_RD, &sc->dma_map_addr_rx_failed_count, 8204189325Sdavidch 0, "Number of RX DMA mapping failures"); 8205189325Sdavidch 8206189325Sdavidch SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8207189325Sdavidch "dma_map_addr_tx_failed_count", 8208189325Sdavidch CTLFLAG_RD, &sc->dma_map_addr_tx_failed_count, 8209189325Sdavidch 0, "Number of TX DMA mapping failures"); 8210189325Sdavidch 8211189325Sdavidch#ifdef BCE_DEBUG 8212189325Sdavidch SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8213189325Sdavidch "unexpected_attention_sim_control", 8214189325Sdavidch CTLFLAG_RW, &unexpected_attention_sim_control, 8215189325Sdavidch 0, "Debug control to simulate unexpected attentions"); 8216189325Sdavidch 8217189325Sdavidch SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8218189325Sdavidch "unexpected_attention_sim_count", 8219189325Sdavidch CTLFLAG_RW, &sc->unexpected_attention_sim_count, 8220189325Sdavidch 0, "Number of simulated unexpected attentions"); 8221189325Sdavidch#endif 8222189325Sdavidch 8223189325Sdavidch SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8224189325Sdavidch "unexpected_attention_count", 8225189325Sdavidch CTLFLAG_RW, &sc->unexpected_attention_count, 8226189325Sdavidch 0, "Number of unexpected attentions"); 8227189325Sdavidch 8228189325Sdavidch#ifdef BCE_DEBUG 8229189325Sdavidch SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8230189325Sdavidch "debug_bootcode_running_failure", 8231189325Sdavidch CTLFLAG_RW, &bootcode_running_failure_sim_control, 8232189325Sdavidch 0, "Debug control to force bootcode running failures"); 8233189325Sdavidch 8234189325Sdavidch SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8235157642Sps "rx_low_watermark", 8236157642Sps CTLFLAG_RD, &sc->rx_low_watermark, 8237157642Sps 0, "Lowest level of free rx_bd's"); 8238157642Sps 8239179771Sdavidch SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8240169632Sdavidch "rx_empty_count", 8241169632Sdavidch CTLFLAG_RD, &sc->rx_empty_count, 8242169632Sdavidch 0, "Number of times the RX chain was empty"); 8243169632Sdavidch 8244179771Sdavidch SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8245157642Sps "tx_hi_watermark", 8246157642Sps CTLFLAG_RD, &sc->tx_hi_watermark, 8247157642Sps 0, "Highest level of used tx_bd's"); 8248157642Sps 8249179771Sdavidch SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8250169632Sdavidch "tx_full_count", 8251169632Sdavidch CTLFLAG_RD, &sc->tx_full_count, 8252169632Sdavidch 0, "Number of times the TX chain was full"); 8253169632Sdavidch 8254179771Sdavidch SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8255169632Sdavidch "requested_tso_frames", 8256169632Sdavidch CTLFLAG_RD, &sc->requested_tso_frames, 8257176448Sdavidch 0, "Number of TSO frames received"); 8258171667Sdavidch 8259179771Sdavidch SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8260176448Sdavidch "rx_interrupts", 8261176448Sdavidch CTLFLAG_RD, &sc->rx_interrupts, 8262176448Sdavidch 0, "Number of RX interrupts"); 8263171667Sdavidch 8264179771Sdavidch SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8265176448Sdavidch "tx_interrupts", 8266176448Sdavidch CTLFLAG_RD, &sc->tx_interrupts, 8267176448Sdavidch 0, "Number of TX interrupts"); 8268171667Sdavidch 8269179771Sdavidch SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 8270176448Sdavidch "rx_intr_time", 8271176448Sdavidch CTLFLAG_RD, &sc->rx_intr_time, 8272176448Sdavidch "RX interrupt time"); 8273171667Sdavidch 8274179771Sdavidch SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 8275176448Sdavidch "tx_intr_time", 8276176448Sdavidch CTLFLAG_RD, &sc->tx_intr_time, 8277176448Sdavidch "TX interrupt time"); 8278179771Sdavidch#endif 8279171667Sdavidch 8280179771Sdavidch SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 8281157642Sps "stat_IfHcInOctets", 8282157642Sps CTLFLAG_RD, &sc->stat_IfHCInOctets, 8283157642Sps "Bytes received"); 8284157642Sps 8285179771Sdavidch SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 8286157642Sps "stat_IfHCInBadOctets", 8287157642Sps CTLFLAG_RD, &sc->stat_IfHCInBadOctets, 8288157642Sps "Bad bytes received"); 8289157642Sps 8290179771Sdavidch SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 8291157642Sps "stat_IfHCOutOctets", 8292157642Sps CTLFLAG_RD, &sc->stat_IfHCOutOctets, 8293157642Sps "Bytes sent"); 8294157642Sps 8295179771Sdavidch SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 8296157642Sps "stat_IfHCOutBadOctets", 8297157642Sps CTLFLAG_RD, &sc->stat_IfHCOutBadOctets, 8298157642Sps "Bad bytes sent"); 8299157642Sps 8300179771Sdavidch SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 8301157642Sps "stat_IfHCInUcastPkts", 8302157642Sps CTLFLAG_RD, &sc->stat_IfHCInUcastPkts, 8303157642Sps "Unicast packets received"); 8304157642Sps 8305179771Sdavidch SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 8306157642Sps "stat_IfHCInMulticastPkts", 8307157642Sps CTLFLAG_RD, &sc->stat_IfHCInMulticastPkts, 8308157642Sps "Multicast packets received"); 8309157642Sps 8310179771Sdavidch SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 8311157642Sps "stat_IfHCInBroadcastPkts", 8312157642Sps CTLFLAG_RD, &sc->stat_IfHCInBroadcastPkts, 8313157642Sps "Broadcast packets received"); 8314157642Sps 8315179771Sdavidch SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 8316157642Sps "stat_IfHCOutUcastPkts", 8317157642Sps CTLFLAG_RD, &sc->stat_IfHCOutUcastPkts, 8318157642Sps "Unicast packets sent"); 8319157642Sps 8320179771Sdavidch SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 8321157642Sps "stat_IfHCOutMulticastPkts", 8322157642Sps CTLFLAG_RD, &sc->stat_IfHCOutMulticastPkts, 8323157642Sps "Multicast packets sent"); 8324157642Sps 8325179771Sdavidch SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 8326157642Sps "stat_IfHCOutBroadcastPkts", 8327157642Sps CTLFLAG_RD, &sc->stat_IfHCOutBroadcastPkts, 8328157642Sps "Broadcast packets sent"); 8329157642Sps 8330179771Sdavidch SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8331157642Sps "stat_emac_tx_stat_dot3statsinternalmactransmiterrors", 8332157642Sps CTLFLAG_RD, &sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors, 8333157642Sps 0, "Internal MAC transmit errors"); 8334157642Sps 8335179771Sdavidch SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8336157642Sps "stat_Dot3StatsCarrierSenseErrors", 8337157642Sps CTLFLAG_RD, &sc->stat_Dot3StatsCarrierSenseErrors, 8338157642Sps 0, "Carrier sense errors"); 8339157642Sps 8340179771Sdavidch SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8341157642Sps "stat_Dot3StatsFCSErrors", 8342157642Sps CTLFLAG_RD, &sc->stat_Dot3StatsFCSErrors, 8343157642Sps 0, "Frame check sequence errors"); 8344157642Sps 8345179771Sdavidch SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8346157642Sps "stat_Dot3StatsAlignmentErrors", 8347157642Sps CTLFLAG_RD, &sc->stat_Dot3StatsAlignmentErrors, 8348157642Sps 0, "Alignment errors"); 8349157642Sps 8350179771Sdavidch SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8351157642Sps "stat_Dot3StatsSingleCollisionFrames", 8352157642Sps CTLFLAG_RD, &sc->stat_Dot3StatsSingleCollisionFrames, 8353157642Sps 0, "Single Collision Frames"); 8354157642Sps 8355179771Sdavidch SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8356157642Sps "stat_Dot3StatsMultipleCollisionFrames", 8357157642Sps CTLFLAG_RD, &sc->stat_Dot3StatsMultipleCollisionFrames, 8358157642Sps 0, "Multiple Collision Frames"); 8359157642Sps 8360179771Sdavidch SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8361157642Sps "stat_Dot3StatsDeferredTransmissions", 8362157642Sps CTLFLAG_RD, &sc->stat_Dot3StatsDeferredTransmissions, 8363157642Sps 0, "Deferred Transmissions"); 8364157642Sps 8365179771Sdavidch SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8366157642Sps "stat_Dot3StatsExcessiveCollisions", 8367157642Sps CTLFLAG_RD, &sc->stat_Dot3StatsExcessiveCollisions, 8368157642Sps 0, "Excessive Collisions"); 8369157642Sps 8370179771Sdavidch SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8371157642Sps "stat_Dot3StatsLateCollisions", 8372157642Sps CTLFLAG_RD, &sc->stat_Dot3StatsLateCollisions, 8373157642Sps 0, "Late Collisions"); 8374157642Sps 8375179771Sdavidch SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8376157642Sps "stat_EtherStatsCollisions", 8377157642Sps CTLFLAG_RD, &sc->stat_EtherStatsCollisions, 8378157642Sps 0, "Collisions"); 8379157642Sps 8380179771Sdavidch SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8381157642Sps "stat_EtherStatsFragments", 8382157642Sps CTLFLAG_RD, &sc->stat_EtherStatsFragments, 8383157642Sps 0, "Fragments"); 8384157642Sps 8385179771Sdavidch SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8386157642Sps "stat_EtherStatsJabbers", 8387157642Sps CTLFLAG_RD, &sc->stat_EtherStatsJabbers, 8388157642Sps 0, "Jabbers"); 8389157642Sps 8390179771Sdavidch SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8391157642Sps "stat_EtherStatsUndersizePkts", 8392157642Sps CTLFLAG_RD, &sc->stat_EtherStatsUndersizePkts, 8393157642Sps 0, "Undersize packets"); 8394157642Sps 8395179771Sdavidch SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8396189325Sdavidch "stat_EtherStatsOversizePkts", 8397189325Sdavidch CTLFLAG_RD, &sc->stat_EtherStatsOversizePkts, 8398189325Sdavidch 0, "stat_EtherStatsOversizePkts"); 8399157642Sps 8400179771Sdavidch SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8401157642Sps "stat_EtherStatsPktsRx64Octets", 8402157642Sps CTLFLAG_RD, &sc->stat_EtherStatsPktsRx64Octets, 8403157642Sps 0, "Bytes received in 64 byte packets"); 8404157642Sps 8405179771Sdavidch SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8406157642Sps "stat_EtherStatsPktsRx65Octetsto127Octets", 8407157642Sps CTLFLAG_RD, &sc->stat_EtherStatsPktsRx65Octetsto127Octets, 8408157642Sps 0, "Bytes received in 65 to 127 byte packets"); 8409157642Sps 8410179771Sdavidch SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8411157642Sps "stat_EtherStatsPktsRx128Octetsto255Octets", 8412157642Sps CTLFLAG_RD, &sc->stat_EtherStatsPktsRx128Octetsto255Octets, 8413157642Sps 0, "Bytes received in 128 to 255 byte packets"); 8414157642Sps 8415179771Sdavidch SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8416157642Sps "stat_EtherStatsPktsRx256Octetsto511Octets", 8417157642Sps CTLFLAG_RD, &sc->stat_EtherStatsPktsRx256Octetsto511Octets, 8418157642Sps 0, "Bytes received in 256 to 511 byte packets"); 8419157642Sps 8420179771Sdavidch SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8421157642Sps "stat_EtherStatsPktsRx512Octetsto1023Octets", 8422157642Sps CTLFLAG_RD, &sc->stat_EtherStatsPktsRx512Octetsto1023Octets, 8423157642Sps 0, "Bytes received in 512 to 1023 byte packets"); 8424157642Sps 8425179771Sdavidch SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8426157642Sps "stat_EtherStatsPktsRx1024Octetsto1522Octets", 8427157642Sps CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1024Octetsto1522Octets, 8428157642Sps 0, "Bytes received in 1024 t0 1522 byte packets"); 8429157642Sps 8430179771Sdavidch SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8431157642Sps "stat_EtherStatsPktsRx1523Octetsto9022Octets", 8432157642Sps CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1523Octetsto9022Octets, 8433157642Sps 0, "Bytes received in 1523 to 9022 byte packets"); 8434157642Sps 8435179771Sdavidch SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8436157642Sps "stat_EtherStatsPktsTx64Octets", 8437157642Sps CTLFLAG_RD, &sc->stat_EtherStatsPktsTx64Octets, 8438157642Sps 0, "Bytes sent in 64 byte packets"); 8439157642Sps 8440179771Sdavidch SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8441157642Sps "stat_EtherStatsPktsTx65Octetsto127Octets", 8442157642Sps CTLFLAG_RD, &sc->stat_EtherStatsPktsTx65Octetsto127Octets, 8443157642Sps 0, "Bytes sent in 65 to 127 byte packets"); 8444157642Sps 8445179771Sdavidch SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8446157642Sps "stat_EtherStatsPktsTx128Octetsto255Octets", 8447157642Sps CTLFLAG_RD, &sc->stat_EtherStatsPktsTx128Octetsto255Octets, 8448157642Sps 0, "Bytes sent in 128 to 255 byte packets"); 8449157642Sps 8450179771Sdavidch SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8451157642Sps "stat_EtherStatsPktsTx256Octetsto511Octets", 8452157642Sps CTLFLAG_RD, &sc->stat_EtherStatsPktsTx256Octetsto511Octets, 8453157642Sps 0, "Bytes sent in 256 to 511 byte packets"); 8454157642Sps 8455179771Sdavidch SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8456157642Sps "stat_EtherStatsPktsTx512Octetsto1023Octets", 8457157642Sps CTLFLAG_RD, &sc->stat_EtherStatsPktsTx512Octetsto1023Octets, 8458157642Sps 0, "Bytes sent in 512 to 1023 byte packets"); 8459157642Sps 8460179771Sdavidch SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8461157642Sps "stat_EtherStatsPktsTx1024Octetsto1522Octets", 8462157642Sps CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1024Octetsto1522Octets, 8463157642Sps 0, "Bytes sent in 1024 to 1522 byte packets"); 8464157642Sps 8465179771Sdavidch SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8466157642Sps "stat_EtherStatsPktsTx1523Octetsto9022Octets", 8467157642Sps CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1523Octetsto9022Octets, 8468157642Sps 0, "Bytes sent in 1523 to 9022 byte packets"); 8469157642Sps 8470179771Sdavidch SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8471157642Sps "stat_XonPauseFramesReceived", 8472157642Sps CTLFLAG_RD, &sc->stat_XonPauseFramesReceived, 8473157642Sps 0, "XON pause frames receved"); 8474157642Sps 8475179771Sdavidch SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8476157642Sps "stat_XoffPauseFramesReceived", 8477157642Sps CTLFLAG_RD, &sc->stat_XoffPauseFramesReceived, 8478157642Sps 0, "XOFF pause frames received"); 8479157642Sps 8480179771Sdavidch SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8481157642Sps "stat_OutXonSent", 8482157642Sps CTLFLAG_RD, &sc->stat_OutXonSent, 8483157642Sps 0, "XON pause frames sent"); 8484157642Sps 8485179771Sdavidch SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8486157642Sps "stat_OutXoffSent", 8487157642Sps CTLFLAG_RD, &sc->stat_OutXoffSent, 8488157642Sps 0, "XOFF pause frames sent"); 8489157642Sps 8490179771Sdavidch SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8491157642Sps "stat_FlowControlDone", 8492157642Sps CTLFLAG_RD, &sc->stat_FlowControlDone, 8493157642Sps 0, "Flow control done"); 8494157642Sps 8495179771Sdavidch SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8496157642Sps "stat_MacControlFramesReceived", 8497157642Sps CTLFLAG_RD, &sc->stat_MacControlFramesReceived, 8498157642Sps 0, "MAC control frames received"); 8499157642Sps 8500179771Sdavidch SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8501157642Sps "stat_XoffStateEntered", 8502157642Sps CTLFLAG_RD, &sc->stat_XoffStateEntered, 8503157642Sps 0, "XOFF state entered"); 8504157642Sps 8505179771Sdavidch SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8506157642Sps "stat_IfInFramesL2FilterDiscards", 8507157642Sps CTLFLAG_RD, &sc->stat_IfInFramesL2FilterDiscards, 8508157642Sps 0, "Received L2 packets discarded"); 8509157642Sps 8510179771Sdavidch SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8511157642Sps "stat_IfInRuleCheckerDiscards", 8512157642Sps CTLFLAG_RD, &sc->stat_IfInRuleCheckerDiscards, 8513157642Sps 0, "Received packets discarded by rule"); 8514157642Sps 8515179771Sdavidch SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8516157642Sps "stat_IfInFTQDiscards", 8517157642Sps CTLFLAG_RD, &sc->stat_IfInFTQDiscards, 8518157642Sps 0, "Received packet FTQ discards"); 8519157642Sps 8520179771Sdavidch SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8521157642Sps "stat_IfInMBUFDiscards", 8522157642Sps CTLFLAG_RD, &sc->stat_IfInMBUFDiscards, 8523157642Sps 0, "Received packets discarded due to lack of controller buffer memory"); 8524157642Sps 8525179771Sdavidch SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8526157642Sps "stat_IfInRuleCheckerP4Hit", 8527157642Sps CTLFLAG_RD, &sc->stat_IfInRuleCheckerP4Hit, 8528157642Sps 0, "Received packets rule checker hits"); 8529157642Sps 8530179771Sdavidch SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8531157642Sps "stat_CatchupInRuleCheckerDiscards", 8532157642Sps CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerDiscards, 8533157642Sps 0, "Received packets discarded in Catchup path"); 8534157642Sps 8535179771Sdavidch SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8536157642Sps "stat_CatchupInFTQDiscards", 8537157642Sps CTLFLAG_RD, &sc->stat_CatchupInFTQDiscards, 8538157642Sps 0, "Received packets discarded in FTQ in Catchup path"); 8539157642Sps 8540179771Sdavidch SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8541157642Sps "stat_CatchupInMBUFDiscards", 8542157642Sps CTLFLAG_RD, &sc->stat_CatchupInMBUFDiscards, 8543157642Sps 0, "Received packets discarded in controller buffer memory in Catchup path"); 8544157642Sps 8545179771Sdavidch SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8546157642Sps "stat_CatchupInRuleCheckerP4Hit", 8547157642Sps CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerP4Hit, 8548157642Sps 0, "Received packets rule checker hits in Catchup path"); 8549157642Sps 8550179771Sdavidch SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8551169271Sdavidch "com_no_buffers", 8552169271Sdavidch CTLFLAG_RD, &sc->com_no_buffers, 8553169271Sdavidch 0, "Valid packets received but no RX buffers available"); 8554169271Sdavidch 8555157642Sps#ifdef BCE_DEBUG 8556157642Sps SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8557157642Sps "driver_state", CTLTYPE_INT | CTLFLAG_RW, 8558157642Sps (void *)sc, 0, 8559157642Sps bce_sysctl_driver_state, "I", "Drive state information"); 8560157642Sps 8561157642Sps SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8562157642Sps "hw_state", CTLTYPE_INT | CTLFLAG_RW, 8563157642Sps (void *)sc, 0, 8564157642Sps bce_sysctl_hw_state, "I", "Hardware state information"); 8565157642Sps 8566157642Sps SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8567170810Sdavidch "bc_state", CTLTYPE_INT | CTLFLAG_RW, 8568170810Sdavidch (void *)sc, 0, 8569170810Sdavidch bce_sysctl_bc_state, "I", "Bootcode state information"); 8570170810Sdavidch 8571170810Sdavidch SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8572157642Sps "dump_rx_chain", CTLTYPE_INT | CTLFLAG_RW, 8573157642Sps (void *)sc, 0, 8574157642Sps bce_sysctl_dump_rx_chain, "I", "Dump rx_bd chain"); 8575157642Sps 8576157642Sps SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8577169271Sdavidch "dump_tx_chain", CTLTYPE_INT | CTLFLAG_RW, 8578169271Sdavidch (void *)sc, 0, 8579169271Sdavidch bce_sysctl_dump_tx_chain, "I", "Dump tx_bd chain"); 8580169271Sdavidch 8581198320Sstas#ifdef BCE_JUMBO_HDRSPLIT 8582169271Sdavidch SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8583176448Sdavidch "dump_pg_chain", CTLTYPE_INT | CTLFLAG_RW, 8584176448Sdavidch (void *)sc, 0, 8585179771Sdavidch bce_sysctl_dump_pg_chain, "I", "Dump page chain"); 8586179695Sdavidch#endif 8587179771Sdavidch SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8588179771Sdavidch "dump_ctx", CTLTYPE_INT | CTLFLAG_RW, 8589179771Sdavidch (void *)sc, 0, 8590179771Sdavidch bce_sysctl_dump_ctx, "I", "Dump context memory"); 8591176448Sdavidch 8592176448Sdavidch SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8593157642Sps "breakpoint", CTLTYPE_INT | CTLFLAG_RW, 8594157642Sps (void *)sc, 0, 8595157642Sps bce_sysctl_breakpoint, "I", "Driver breakpoint"); 8596170392Sdavidch 8597179771Sdavidch SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8598179771Sdavidch "reg_read", CTLTYPE_INT | CTLFLAG_RW, 8599179771Sdavidch (void *)sc, 0, 8600169632Sdavidch bce_sysctl_reg_read, "I", "Register read"); 8601169271Sdavidch 8602179771Sdavidch SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8603179771Sdavidch "nvram_read", CTLTYPE_INT | CTLFLAG_RW, 8604179771Sdavidch (void *)sc, 0, 8605179771Sdavidch bce_sysctl_nvram_read, "I", "NVRAM read"); 8606179771Sdavidch 8607179771Sdavidch SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8608179771Sdavidch "phy_read", CTLTYPE_INT | CTLFLAG_RW, 8609179771Sdavidch (void *)sc, 0, 8610169632Sdavidch bce_sysctl_phy_read, "I", "PHY register read"); 8611169632Sdavidch 8612157642Sps#endif 8613157642Sps 8614179771Sdavidch DBEXIT(BCE_VERBOSE_MISC); 8615157642Sps} 8616157642Sps 8617157642Sps 8618157642Sps/****************************************************************************/ 8619157642Sps/* BCE Debug Routines */ 8620157642Sps/****************************************************************************/ 8621157642Sps#ifdef BCE_DEBUG 8622170392Sdavidch 8623169632Sdavidch/****************************************************************************/ 8624169632Sdavidch/* Freezes the controller to allow for a cohesive state dump. */ 8625169632Sdavidch/* */ 8626169632Sdavidch/* Returns: */ 8627169632Sdavidch/* Nothing. */ 8628169632Sdavidch/****************************************************************************/ 8629169632Sdavidchstatic void 8630169632Sdavidchbce_freeze_controller(struct bce_softc *sc) 8631169632Sdavidch{ 8632169632Sdavidch u32 val; 8633170392Sdavidch val = REG_RD(sc, BCE_MISC_COMMAND); 8634170392Sdavidch val |= BCE_MISC_COMMAND_DISABLE_ALL; 8635169632Sdavidch REG_WR(sc, BCE_MISC_COMMAND, val); 8636170392Sdavidch} 8637157642Sps 8638170392Sdavidch 8639157642Sps/****************************************************************************/ 8640170392Sdavidch/* Unfreezes the controller after a freeze operation. This may not always */ 8641169632Sdavidch/* work and the controller will require a reset! */ 8642169632Sdavidch/* */ 8643169632Sdavidch/* Returns: */ 8644169632Sdavidch/* Nothing. */ 8645169632Sdavidch/****************************************************************************/ 8646169632Sdavidchstatic void 8647169632Sdavidchbce_unfreeze_controller(struct bce_softc *sc) 8648169632Sdavidch{ 8649169632Sdavidch u32 val; 8650170392Sdavidch val = REG_RD(sc, BCE_MISC_COMMAND); 8651170392Sdavidch val |= BCE_MISC_COMMAND_ENABLE_ALL; 8652169632Sdavidch REG_WR(sc, BCE_MISC_COMMAND, val); 8653170392Sdavidch} 8654170392Sdavidch 8655182293Sdavidch 8656169632Sdavidch/****************************************************************************/ 8657182293Sdavidch/* Prints out Ethernet frame information from an mbuf. */ 8658182293Sdavidch/* */ 8659182293Sdavidch/* Partially decode an Ethernet frame to look at some important headers. */ 8660182293Sdavidch/* */ 8661182293Sdavidch/* Returns: */ 8662182293Sdavidch/* Nothing. */ 8663182293Sdavidch/****************************************************************************/ 8664182293Sdavidchstatic void 8665182293Sdavidchbce_dump_enet(struct bce_softc *sc, struct mbuf *m) 8666182293Sdavidch{ 8667182293Sdavidch struct ether_vlan_header *eh; 8668182293Sdavidch u16 etype; 8669182293Sdavidch int ehlen; 8670182293Sdavidch struct ip *ip; 8671182293Sdavidch struct tcphdr *th; 8672182293Sdavidch struct udphdr *uh; 8673182293Sdavidch struct arphdr *ah; 8674182293Sdavidch 8675182293Sdavidch BCE_PRINTF( 8676182293Sdavidch "-----------------------------" 8677182293Sdavidch " Frame Decode " 8678182293Sdavidch "-----------------------------\n"); 8679182293Sdavidch 8680182293Sdavidch eh = mtod(m, struct ether_vlan_header *); 8681182293Sdavidch 8682182293Sdavidch /* Handle VLAN encapsulation if present. */ 8683182293Sdavidch if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 8684182293Sdavidch etype = ntohs(eh->evl_proto); 8685182293Sdavidch ehlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 8686182293Sdavidch } else { 8687182293Sdavidch etype = ntohs(eh->evl_encap_proto); 8688182293Sdavidch ehlen = ETHER_HDR_LEN; 8689182293Sdavidch } 8690182293Sdavidch 8691182293Sdavidch /* ToDo: Add VLAN output. */ 8692182293Sdavidch BCE_PRINTF("enet: dest = %6D, src = %6D, type = 0x%04X, hlen = %d\n", 8693182293Sdavidch eh->evl_dhost, ":", eh->evl_shost, ":", etype, ehlen); 8694182293Sdavidch 8695182293Sdavidch switch (etype) { 8696182293Sdavidch case ETHERTYPE_IP: 8697182293Sdavidch ip = (struct ip *)(m->m_data + ehlen); 8698182293Sdavidch BCE_PRINTF("--ip: dest = 0x%08X , src = 0x%08X, len = %d bytes, " 8699182293Sdavidch "protocol = 0x%02X, xsum = 0x%04X\n", 8700182293Sdavidch ntohl(ip->ip_dst.s_addr), ntohl(ip->ip_src.s_addr), 8701182293Sdavidch ntohs(ip->ip_len), ip->ip_p, ntohs(ip->ip_sum)); 8702182293Sdavidch 8703182293Sdavidch switch (ip->ip_p) { 8704182293Sdavidch case IPPROTO_TCP: 8705182293Sdavidch th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 8706182293Sdavidch BCE_PRINTF("-tcp: dest = %d, src = %d, hlen = %d bytes, " 8707182293Sdavidch "flags = 0x%b, csum = 0x%04X\n", 8708182293Sdavidch ntohs(th->th_dport), ntohs(th->th_sport), (th->th_off << 2), 8709182293Sdavidch th->th_flags, "\20\10CWR\07ECE\06URG\05ACK\04PSH\03RST\02SYN\01FIN", 8710182293Sdavidch ntohs(th->th_sum)); 8711182293Sdavidch break; 8712182293Sdavidch case IPPROTO_UDP: 8713182293Sdavidch uh = (struct udphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 8714182293Sdavidch BCE_PRINTF("-udp: dest = %d, src = %d, len = %d bytes, " 8715182293Sdavidch "csum = 0x%04X\n", ntohs(uh->uh_dport), ntohs(uh->uh_sport), 8716182293Sdavidch ntohs(uh->uh_ulen), ntohs(uh->uh_sum)); 8717182293Sdavidch break; 8718182293Sdavidch case IPPROTO_ICMP: 8719182293Sdavidch BCE_PRINTF("icmp:\n"); 8720182293Sdavidch break; 8721182293Sdavidch default: 8722182293Sdavidch BCE_PRINTF("----: Other IP protocol.\n"); 8723182293Sdavidch } 8724182293Sdavidch break; 8725182293Sdavidch case ETHERTYPE_IPV6: 8726182293Sdavidch BCE_PRINTF("ipv6: No decode supported.\n"); 8727182293Sdavidch break; 8728182293Sdavidch case ETHERTYPE_ARP: 8729182293Sdavidch BCE_PRINTF("-arp: "); 8730182293Sdavidch ah = (struct arphdr *) (m->m_data + ehlen); 8731182293Sdavidch switch (ntohs(ah->ar_op)) { 8732182293Sdavidch case ARPOP_REVREQUEST: 8733182293Sdavidch printf("reverse ARP request\n"); 8734182293Sdavidch break; 8735182293Sdavidch case ARPOP_REVREPLY: 8736182293Sdavidch printf("reverse ARP reply\n"); 8737182293Sdavidch break; 8738182293Sdavidch case ARPOP_REQUEST: 8739182293Sdavidch printf("ARP request\n"); 8740182293Sdavidch break; 8741182293Sdavidch case ARPOP_REPLY: 8742182293Sdavidch printf("ARP reply\n"); 8743182293Sdavidch break; 8744182293Sdavidch default: 8745182293Sdavidch printf("other ARP operation\n"); 8746182293Sdavidch } 8747182293Sdavidch break; 8748182293Sdavidch default: 8749182293Sdavidch BCE_PRINTF("----: Other protocol.\n"); 8750182293Sdavidch } 8751182293Sdavidch 8752182293Sdavidch BCE_PRINTF( 8753182293Sdavidch "-----------------------------" 8754182293Sdavidch "--------------" 8755182293Sdavidch "-----------------------------\n"); 8756182293Sdavidch} 8757182293Sdavidch 8758182293Sdavidch 8759182293Sdavidch/****************************************************************************/ 8760157642Sps/* Prints out information about an mbuf. */ 8761157642Sps/* */ 8762157642Sps/* Returns: */ 8763157642Sps/* Nothing. */ 8764157642Sps/****************************************************************************/ 8765179771Sdavidchstatic __attribute__ ((noinline)) void 8766157642Spsbce_dump_mbuf(struct bce_softc *sc, struct mbuf *m) 8767157642Sps{ 8768157642Sps struct mbuf *mp = m; 8769157642Sps 8770157642Sps if (m == NULL) { 8771169632Sdavidch BCE_PRINTF("mbuf: null pointer\n"); 8772157642Sps return; 8773157642Sps } 8774157642Sps 8775157642Sps while (mp) { 8776179771Sdavidch BCE_PRINTF("mbuf: %p, m_len = %d, m_flags = 0x%b, m_data = %p\n", 8777179771Sdavidch mp, mp->m_len, mp->m_flags, 8778176448Sdavidch "\20\1M_EXT\2M_PKTHDR\3M_EOR\4M_RDONLY", 8779176448Sdavidch mp->m_data); 8780157642Sps 8781170392Sdavidch if (mp->m_flags & M_PKTHDR) { 8782179771Sdavidch BCE_PRINTF("- m_pkthdr: len = %d, flags = 0x%b, csum_flags = %b\n", 8783176448Sdavidch mp->m_pkthdr.len, mp->m_flags, 8784176448Sdavidch "\20\12M_BCAST\13M_MCAST\14M_FRAG\15M_FIRSTFRAG" 8785176448Sdavidch "\16M_LASTFRAG\21M_VLANTAG\22M_PROMISC\23M_NOFREE", 8786176448Sdavidch mp->m_pkthdr.csum_flags, 8787176448Sdavidch "\20\1CSUM_IP\2CSUM_TCP\3CSUM_UDP\4CSUM_IP_FRAGS" 8788176448Sdavidch "\5CSUM_FRAGMENT\6CSUM_TSO\11CSUM_IP_CHECKED" 8789176448Sdavidch "\12CSUM_IP_VALID\13CSUM_DATA_VALID\14CSUM_PSEUDO_HDR"); 8790170392Sdavidch } 8791169632Sdavidch 8792157642Sps if (mp->m_flags & M_EXT) { 8793179771Sdavidch BCE_PRINTF("- m_ext: %p, ext_size = %d, type = ", 8794176448Sdavidch mp->m_ext.ext_buf, mp->m_ext.ext_size); 8795170392Sdavidch switch (mp->m_ext.ext_type) { 8796170392Sdavidch case EXT_CLUSTER: printf("EXT_CLUSTER\n"); break; 8797170392Sdavidch case EXT_SFBUF: printf("EXT_SFBUF\n"); break; 8798170392Sdavidch case EXT_JUMBO9: printf("EXT_JUMBO9\n"); break; 8799170392Sdavidch case EXT_JUMBO16: printf("EXT_JUMBO16\n"); break; 8800170392Sdavidch case EXT_PACKET: printf("EXT_PACKET\n"); break; 8801170392Sdavidch case EXT_MBUF: printf("EXT_MBUF\n"); break; 8802170392Sdavidch case EXT_NET_DRV: printf("EXT_NET_DRV\n"); break; 8803170392Sdavidch case EXT_MOD_TYPE: printf("EXT_MDD_TYPE\n"); break; 8804170392Sdavidch case EXT_DISPOSABLE: printf("EXT_DISPOSABLE\n"); break; 8805170392Sdavidch case EXT_EXTREF: printf("EXT_EXTREF\n"); break; 8806170392Sdavidch default: printf("UNKNOWN\n"); 8807170392Sdavidch } 8808157642Sps } 8809157642Sps 8810157642Sps mp = mp->m_next; 8811157642Sps } 8812157642Sps} 8813157642Sps 8814157642Sps 8815157642Sps/****************************************************************************/ 8816157642Sps/* Prints out the mbufs in the TX mbuf chain. */ 8817157642Sps/* */ 8818157642Sps/* Returns: */ 8819157642Sps/* Nothing. */ 8820157642Sps/****************************************************************************/ 8821179771Sdavidchstatic __attribute__ ((noinline)) void 8822176448Sdavidchbce_dump_tx_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count) 8823157642Sps{ 8824157642Sps struct mbuf *m; 8825157642Sps 8826169271Sdavidch BCE_PRINTF( 8827157642Sps "----------------------------" 8828157642Sps " tx mbuf data " 8829157642Sps "----------------------------\n"); 8830157642Sps 8831157642Sps for (int i = 0; i < count; i++) { 8832157642Sps m = sc->tx_mbuf_ptr[chain_prod]; 8833176448Sdavidch BCE_PRINTF("txmbuf[0x%04X]\n", chain_prod); 8834157642Sps bce_dump_mbuf(sc, m); 8835157642Sps chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod)); 8836157642Sps } 8837157642Sps 8838169271Sdavidch BCE_PRINTF( 8839157642Sps "----------------------------" 8840157642Sps "----------------" 8841157642Sps "----------------------------\n"); 8842157642Sps} 8843157642Sps 8844157642Sps 8845169271Sdavidch/****************************************************************************/ 8846169271Sdavidch/* Prints out the mbufs in the RX mbuf chain. */ 8847169271Sdavidch/* */ 8848169271Sdavidch/* Returns: */ 8849169271Sdavidch/* Nothing. */ 8850169271Sdavidch/****************************************************************************/ 8851179771Sdavidchstatic __attribute__ ((noinline)) void 8852176448Sdavidchbce_dump_rx_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count) 8853157642Sps{ 8854157642Sps struct mbuf *m; 8855157642Sps 8856169271Sdavidch BCE_PRINTF( 8857157642Sps "----------------------------" 8858157642Sps " rx mbuf data " 8859157642Sps "----------------------------\n"); 8860157642Sps 8861157642Sps for (int i = 0; i < count; i++) { 8862157642Sps m = sc->rx_mbuf_ptr[chain_prod]; 8863169271Sdavidch BCE_PRINTF("rxmbuf[0x%04X]\n", chain_prod); 8864157642Sps bce_dump_mbuf(sc, m); 8865157642Sps chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod)); 8866157642Sps } 8867157642Sps 8868157642Sps 8869169271Sdavidch BCE_PRINTF( 8870157642Sps "----------------------------" 8871157642Sps "----------------" 8872157642Sps "----------------------------\n"); 8873157642Sps} 8874157642Sps 8875157642Sps 8876198320Sstas#ifdef BCE_JUMBO_HDRSPLIT 8877169271Sdavidch/****************************************************************************/ 8878176448Sdavidch/* Prints out the mbufs in the mbuf page chain. */ 8879176448Sdavidch/* */ 8880176448Sdavidch/* Returns: */ 8881176448Sdavidch/* Nothing. */ 8882176448Sdavidch/****************************************************************************/ 8883179771Sdavidchstatic __attribute__ ((noinline)) void 8884176448Sdavidchbce_dump_pg_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count) 8885176448Sdavidch{ 8886176448Sdavidch struct mbuf *m; 8887176448Sdavidch 8888176448Sdavidch BCE_PRINTF( 8889176448Sdavidch "----------------------------" 8890176448Sdavidch " pg mbuf data " 8891176448Sdavidch "----------------------------\n"); 8892176448Sdavidch 8893176448Sdavidch for (int i = 0; i < count; i++) { 8894176448Sdavidch m = sc->pg_mbuf_ptr[chain_prod]; 8895176448Sdavidch BCE_PRINTF("pgmbuf[0x%04X]\n", chain_prod); 8896176448Sdavidch bce_dump_mbuf(sc, m); 8897176448Sdavidch chain_prod = PG_CHAIN_IDX(NEXT_PG_BD(chain_prod)); 8898176448Sdavidch } 8899176448Sdavidch 8900176448Sdavidch 8901176448Sdavidch BCE_PRINTF( 8902176448Sdavidch "----------------------------" 8903176448Sdavidch "----------------" 8904176448Sdavidch "----------------------------\n"); 8905179771Sdavidch} 8906179695Sdavidch#endif 8907176448Sdavidch 8908176448Sdavidch 8909176448Sdavidch/****************************************************************************/ 8910169271Sdavidch/* Prints out a tx_bd structure. */ 8911169271Sdavidch/* */ 8912169271Sdavidch/* Returns: */ 8913169271Sdavidch/* Nothing. */ 8914169271Sdavidch/****************************************************************************/ 8915179771Sdavidchstatic __attribute__ ((noinline)) void 8916157642Spsbce_dump_txbd(struct bce_softc *sc, int idx, struct tx_bd *txbd) 8917157642Sps{ 8918157642Sps if (idx > MAX_TX_BD) 8919157642Sps /* Index out of range. */ 8920169271Sdavidch BCE_PRINTF("tx_bd[0x%04X]: Invalid tx_bd index!\n", idx); 8921157642Sps else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 8922157642Sps /* TX Chain page pointer. */ 8923179771Sdavidch BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page pointer\n", 8924157642Sps idx, txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo); 8925169271Sdavidch else { 8926169271Sdavidch /* Normal tx_bd entry. */ 8927169271Sdavidch BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = 0x%08X, " 8928179771Sdavidch "vlan tag= 0x%04X, flags = 0x%04X (", idx, 8929169271Sdavidch txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo, 8930169271Sdavidch txbd->tx_bd_mss_nbytes, txbd->tx_bd_vlan_tag, 8931169271Sdavidch txbd->tx_bd_flags); 8932170392Sdavidch 8933170392Sdavidch if (txbd->tx_bd_flags & TX_BD_FLAGS_CONN_FAULT) 8934170392Sdavidch printf(" CONN_FAULT"); 8935170392Sdavidch 8936170392Sdavidch if (txbd->tx_bd_flags & TX_BD_FLAGS_TCP_UDP_CKSUM) 8937170392Sdavidch printf(" TCP_UDP_CKSUM"); 8938170392Sdavidch 8939170392Sdavidch if (txbd->tx_bd_flags & TX_BD_FLAGS_IP_CKSUM) 8940170392Sdavidch printf(" IP_CKSUM"); 8941170392Sdavidch 8942170392Sdavidch if (txbd->tx_bd_flags & TX_BD_FLAGS_VLAN_TAG) 8943170392Sdavidch printf(" VLAN"); 8944170392Sdavidch 8945170392Sdavidch if (txbd->tx_bd_flags & TX_BD_FLAGS_COAL_NOW) 8946170392Sdavidch printf(" COAL_NOW"); 8947170392Sdavidch 8948170392Sdavidch if (txbd->tx_bd_flags & TX_BD_FLAGS_DONT_GEN_CRC) 8949170392Sdavidch printf(" DONT_GEN_CRC"); 8950170392Sdavidch 8951170392Sdavidch if (txbd->tx_bd_flags & TX_BD_FLAGS_START) 8952170392Sdavidch printf(" START"); 8953170392Sdavidch 8954170392Sdavidch if (txbd->tx_bd_flags & TX_BD_FLAGS_END) 8955170392Sdavidch printf(" END"); 8956170392Sdavidch 8957170392Sdavidch if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_LSO) 8958170392Sdavidch printf(" LSO"); 8959170392Sdavidch 8960170392Sdavidch if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_OPTION_WORD) 8961170392Sdavidch printf(" OPTION_WORD"); 8962170392Sdavidch 8963170392Sdavidch if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_FLAGS) 8964170392Sdavidch printf(" FLAGS"); 8965170392Sdavidch 8966170392Sdavidch if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_SNAP) 8967170392Sdavidch printf(" SNAP"); 8968170392Sdavidch 8969170392Sdavidch printf(" )\n"); 8970170392Sdavidch } 8971179771Sdavidch 8972157642Sps} 8973157642Sps 8974157642Sps 8975169271Sdavidch/****************************************************************************/ 8976169271Sdavidch/* Prints out a rx_bd structure. */ 8977169271Sdavidch/* */ 8978169271Sdavidch/* Returns: */ 8979169271Sdavidch/* Nothing. */ 8980169271Sdavidch/****************************************************************************/ 8981179771Sdavidchstatic __attribute__ ((noinline)) void 8982157642Spsbce_dump_rxbd(struct bce_softc *sc, int idx, struct rx_bd *rxbd) 8983157642Sps{ 8984157642Sps if (idx > MAX_RX_BD) 8985157642Sps /* Index out of range. */ 8986169271Sdavidch BCE_PRINTF("rx_bd[0x%04X]: Invalid rx_bd index!\n", idx); 8987157642Sps else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 8988176448Sdavidch /* RX Chain page pointer. */ 8989179771Sdavidch BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page pointer\n", 8990157642Sps idx, rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo); 8991157642Sps else 8992176448Sdavidch /* Normal rx_bd entry. */ 8993169271Sdavidch BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = 0x%08X, " 8994179771Sdavidch "flags = 0x%08X\n", idx, 8995157642Sps rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo, 8996157642Sps rxbd->rx_bd_len, rxbd->rx_bd_flags); 8997157642Sps} 8998157642Sps 8999157642Sps 9000198320Sstas#ifdef BCE_JUMBO_HDRSPLIT 9001169271Sdavidch/****************************************************************************/ 9002176448Sdavidch/* Prints out a rx_bd structure in the page chain. */ 9003176448Sdavidch/* */ 9004176448Sdavidch/* Returns: */ 9005176448Sdavidch/* Nothing. */ 9006176448Sdavidch/****************************************************************************/ 9007179771Sdavidchstatic __attribute__ ((noinline)) void 9008176448Sdavidchbce_dump_pgbd(struct bce_softc *sc, int idx, struct rx_bd *pgbd) 9009176448Sdavidch{ 9010176448Sdavidch if (idx > MAX_PG_BD) 9011176448Sdavidch /* Index out of range. */ 9012176448Sdavidch BCE_PRINTF("pg_bd[0x%04X]: Invalid pg_bd index!\n", idx); 9013176448Sdavidch else if ((idx & USABLE_PG_BD_PER_PAGE) == USABLE_PG_BD_PER_PAGE) 9014176448Sdavidch /* Page Chain page pointer. */ 9015179771Sdavidch BCE_PRINTF("px_bd[0x%04X]: haddr = 0x%08X:%08X, chain page pointer\n", 9016176448Sdavidch idx, pgbd->rx_bd_haddr_hi, pgbd->rx_bd_haddr_lo); 9017176448Sdavidch else 9018176448Sdavidch /* Normal rx_bd entry. */ 9019176448Sdavidch BCE_PRINTF("pg_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = 0x%08X, " 9020179771Sdavidch "flags = 0x%08X\n", idx, 9021176448Sdavidch pgbd->rx_bd_haddr_hi, pgbd->rx_bd_haddr_lo, 9022176448Sdavidch pgbd->rx_bd_len, pgbd->rx_bd_flags); 9023179771Sdavidch} 9024179695Sdavidch#endif 9025176448Sdavidch 9026176448Sdavidch 9027176448Sdavidch/****************************************************************************/ 9028170810Sdavidch/* Prints out a l2_fhdr structure. */ 9029169271Sdavidch/* */ 9030169271Sdavidch/* Returns: */ 9031169271Sdavidch/* Nothing. */ 9032169271Sdavidch/****************************************************************************/ 9033179771Sdavidchstatic __attribute__ ((noinline)) void 9034157642Spsbce_dump_l2fhdr(struct bce_softc *sc, int idx, struct l2_fhdr *l2fhdr) 9035157642Sps{ 9036176448Sdavidch BCE_PRINTF("l2_fhdr[0x%04X]: status = 0x%b, " 9037176448Sdavidch "pkt_len = %d, vlan = 0x%04x, ip_xsum/hdr_len = 0x%04X, " 9038157642Sps "tcp_udp_xsum = 0x%04X\n", idx, 9039179771Sdavidch l2fhdr->l2_fhdr_status, BCE_L2FHDR_PRINTFB, 9040179771Sdavidch l2fhdr->l2_fhdr_pkt_len, l2fhdr->l2_fhdr_vlan_tag, 9041176448Sdavidch l2fhdr->l2_fhdr_ip_xsum, l2fhdr->l2_fhdr_tcp_udp_xsum); 9042157642Sps} 9043157642Sps 9044157642Sps 9045169271Sdavidch/****************************************************************************/ 9046179771Sdavidch/* Prints out context memory info. (Only useful for CID 0 to 16.) */ 9047176448Sdavidch/* */ 9048176448Sdavidch/* Returns: */ 9049176448Sdavidch/* Nothing. */ 9050176448Sdavidch/****************************************************************************/ 9051179771Sdavidchstatic __attribute__ ((noinline)) void 9052176448Sdavidchbce_dump_ctx(struct bce_softc *sc, u16 cid) 9053176448Sdavidch{ 9054179771Sdavidch if (cid <= TX_CID) { 9055176448Sdavidch BCE_PRINTF( 9056176448Sdavidch "----------------------------" 9057176448Sdavidch " CTX Data " 9058176448Sdavidch "----------------------------\n"); 9059178132Sdavidch 9060176448Sdavidch BCE_PRINTF(" 0x%04X - (CID) Context ID\n", cid); 9061182293Sdavidch 9062179771Sdavidch if (cid == RX_CID) { 9063182293Sdavidch BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_BDIDX) host rx " 9064182293Sdavidch "producer index\n", 9065182293Sdavidch CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_HOST_BDIDX)); 9066182293Sdavidch BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_BSEQ) host byte sequence\n", 9067182293Sdavidch CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_HOST_BSEQ)); 9068182293Sdavidch BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BSEQ) h/w byte sequence\n", 9069182293Sdavidch CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BSEQ)); 9070182293Sdavidch BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDHADDR_HI) h/w buffer " 9071182293Sdavidch "descriptor address\n", 9072182293Sdavidch CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BDHADDR_HI)); 9073182293Sdavidch BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDHADDR_LO) h/w buffer " 9074182293Sdavidch "descriptor address\n", 9075182293Sdavidch CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BDHADDR_LO)); 9076182293Sdavidch BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDIDX) h/w rx consumer index\n", 9077182293Sdavidch CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BDIDX)); 9078182293Sdavidch BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_PG_BDIDX) host page " 9079182293Sdavidch "producer index\n", 9080182293Sdavidch CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_HOST_PG_BDIDX)); 9081182293Sdavidch BCE_PRINTF(" 0x%08X - (L2CTX_RX_PG_BUF_SIZE) host rx_bd/page " 9082182293Sdavidch "buffer size\n", 9083182293Sdavidch CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_PG_BUF_SIZE)); 9084182293Sdavidch BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDHADDR_HI) h/w page " 9085182293Sdavidch "chain address\n", 9086182293Sdavidch CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_PG_BDHADDR_HI)); 9087182293Sdavidch BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDHADDR_LO) h/w page " 9088182293Sdavidch "chain address\n", 9089182293Sdavidch CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_PG_BDHADDR_LO)); 9090182293Sdavidch BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDIDX) h/w page " 9091182293Sdavidch "consumer index\n", 9092182293Sdavidch CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_PG_BDIDX)); 9093179771Sdavidch } else if (cid == TX_CID) { 9094182293Sdavidch if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 9095182293Sdavidch (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 9096182293Sdavidch BCE_PRINTF(" 0x%08X - (L2CTX_TX_TYPE_XI) ctx type\n", 9097182293Sdavidch CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_TX_TYPE_XI)); 9098182293Sdavidch BCE_PRINTF(" 0x%08X - (L2CTX_CMD_TX_TYPE_XI) ctx cmd\n", 9099182293Sdavidch CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_TX_CMD_TYPE_XI)); 9100182293Sdavidch BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BDHADDR_HI_XI) h/w buffer " 9101182293Sdavidch "descriptor address\n", CTX_RD(sc, 9102182293Sdavidch GET_CID_ADDR(cid), BCE_L2CTX_TX_TBDR_BHADDR_HI_XI)); 9103182293Sdavidch BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BHADDR_LO_XI) h/w buffer " 9104182293Sdavidch "descriptor address\n", CTX_RD(sc, 9105182293Sdavidch GET_CID_ADDR(cid), BCE_L2CTX_TX_TBDR_BHADDR_LO_XI)); 9106182293Sdavidch BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BIDX_XI) host producer " 9107182293Sdavidch "index\n", CTX_RD(sc, GET_CID_ADDR(cid), 9108182293Sdavidch BCE_L2CTX_TX_HOST_BIDX_XI)); 9109182293Sdavidch BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BSEQ_XI) host byte " 9110182293Sdavidch "sequence\n", CTX_RD(sc, GET_CID_ADDR(cid), 9111182293Sdavidch BCE_L2CTX_TX_HOST_BSEQ_XI)); 9112179771Sdavidch } else { 9113182293Sdavidch BCE_PRINTF(" 0x%08X - (L2CTX_TX_TYPE) ctx type\n", 9114182293Sdavidch CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_TX_TYPE)); 9115182293Sdavidch BCE_PRINTF(" 0x%08X - (L2CTX_TX_CMD_TYPE) ctx cmd\n", 9116182293Sdavidch CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_TX_CMD_TYPE)); 9117182293Sdavidch BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BDHADDR_HI) h/w buffer " 9118182293Sdavidch "descriptor address\n", CTX_RD(sc, GET_CID_ADDR(cid), 9119182293Sdavidch BCE_L2CTX_TX_TBDR_BHADDR_HI)); 9120182293Sdavidch BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BHADDR_LO) h/w buffer " 9121182293Sdavidch "descriptor address\n", CTX_RD(sc, GET_CID_ADDR(cid), 9122182293Sdavidch BCE_L2CTX_TX_TBDR_BHADDR_LO)); 9123182293Sdavidch BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BIDX) host producer " 9124182293Sdavidch "index\n", CTX_RD(sc, GET_CID_ADDR(cid), 9125182293Sdavidch BCE_L2CTX_TX_HOST_BIDX)); 9126182293Sdavidch BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BSEQ) host byte " 9127182293Sdavidch "sequence\n", CTX_RD(sc, GET_CID_ADDR(cid), 9128182293Sdavidch BCE_L2CTX_TX_HOST_BSEQ)); 9129179771Sdavidch } 9130179771Sdavidch } else 9131182293Sdavidch BCE_PRINTF(" Unknown CID\n"); 9132176448Sdavidch 9133176448Sdavidch BCE_PRINTF( 9134176448Sdavidch "----------------------------" 9135179771Sdavidch " Raw CTX " 9136179771Sdavidch "----------------------------\n"); 9137179771Sdavidch 9138179771Sdavidch for (int i = 0x0; i < 0x300; i += 0x10) { 9139182293Sdavidch BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", i, 9140182293Sdavidch CTX_RD(sc, GET_CID_ADDR(cid), i), 9141182293Sdavidch CTX_RD(sc, GET_CID_ADDR(cid), i + 0x4), 9142182293Sdavidch CTX_RD(sc, GET_CID_ADDR(cid), i + 0x8), 9143179771Sdavidch CTX_RD(sc, GET_CID_ADDR(cid), i + 0xc)); 9144179771Sdavidch } 9145179771Sdavidch 9146179771Sdavidch 9147179771Sdavidch BCE_PRINTF( 9148179771Sdavidch "----------------------------" 9149176448Sdavidch "----------------" 9150178132Sdavidch "----------------------------\n"); 9151176448Sdavidch } 9152176448Sdavidch} 9153176448Sdavidch 9154176448Sdavidch 9155176448Sdavidch/****************************************************************************/ 9156176448Sdavidch/* Prints out the FTQ data. */ 9157176448Sdavidch/* */ 9158176448Sdavidch/* Returns: */ 9159176448Sdavidch/* Nothing. */ 9160176448Sdavidch/****************************************************************************/ 9161179771Sdavidchstatic __attribute__ ((noinline)) void 9162176448Sdavidchbce_dump_ftqs(struct bce_softc *sc) 9163178132Sdavidch{ 9164179771Sdavidch u32 cmd, ctl, cur_depth, max_depth, valid_cnt, val; 9165176448Sdavidch 9166176448Sdavidch BCE_PRINTF( 9167176448Sdavidch "----------------------------" 9168176448Sdavidch " FTQ Data " 9169176448Sdavidch "----------------------------\n"); 9170176448Sdavidch 9171179771Sdavidch BCE_PRINTF(" FTQ Command Control Depth_Now Max_Depth Valid_Cnt \n"); 9172179771Sdavidch BCE_PRINTF(" ------- ---------- ---------- ---------- ---------- ----------\n"); 9173178132Sdavidch 9174178132Sdavidch /* Setup the generic statistic counters for the FTQ valid count. */ 9175179771Sdavidch val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT << 24) | 9176179771Sdavidch (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT << 16) | 9177179771Sdavidch (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT << 8) | 9178179771Sdavidch (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT); 9179179771Sdavidch REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val); 9180182293Sdavidch 9181179771Sdavidch val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT << 24) | 9182179771Sdavidch (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT << 16) | 9183179771Sdavidch (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT << 8) | 9184179771Sdavidch (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT); 9185179771Sdavidch REG_WR(sc, BCE_HC_STAT_GEN_SEL_1, val); 9186182293Sdavidch 9187179771Sdavidch val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT << 24) | 9188179771Sdavidch (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT << 16) | 9189179771Sdavidch (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT << 8) | 9190179771Sdavidch (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT); 9191179771Sdavidch REG_WR(sc, BCE_HC_STAT_GEN_SEL_2, val); 9192182293Sdavidch 9193179771Sdavidch val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT << 24) | 9194179771Sdavidch (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT << 16) | 9195179771Sdavidch (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT << 8) | 9196179771Sdavidch (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT); 9197179771Sdavidch REG_WR(sc, BCE_HC_STAT_GEN_SEL_3, val); 9198178132Sdavidch 9199182293Sdavidch /* Input queue to the Receive Lookup state machine */ 9200178132Sdavidch cmd = REG_RD(sc, BCE_RLUP_FTQ_CMD); 9201178132Sdavidch ctl = REG_RD(sc, BCE_RLUP_FTQ_CTL); 9202178132Sdavidch cur_depth = (ctl & BCE_RLUP_FTQ_CTL_CUR_DEPTH) >> 22; 9203178132Sdavidch max_depth = (ctl & BCE_RLUP_FTQ_CTL_MAX_DEPTH) >> 12; 9204178132Sdavidch valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0); 9205179771Sdavidch BCE_PRINTF(" RLUP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9206176448Sdavidch cmd, ctl, cur_depth, max_depth, valid_cnt); 9207178132Sdavidch 9208182293Sdavidch /* Input queue to the Receive Processor */ 9209178132Sdavidch cmd = REG_RD_IND(sc, BCE_RXP_FTQ_CMD); 9210178132Sdavidch ctl = REG_RD_IND(sc, BCE_RXP_FTQ_CTL); 9211178132Sdavidch cur_depth = (ctl & BCE_RXP_FTQ_CTL_CUR_DEPTH) >> 22; 9212178132Sdavidch max_depth = (ctl & BCE_RXP_FTQ_CTL_MAX_DEPTH) >> 12; 9213178132Sdavidch valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1); 9214179771Sdavidch BCE_PRINTF(" RXP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9215176448Sdavidch cmd, ctl, cur_depth, max_depth, valid_cnt); 9216178132Sdavidch 9217182293Sdavidch /* Input queue to the Recevie Processor */ 9218178132Sdavidch cmd = REG_RD_IND(sc, BCE_RXP_CFTQ_CMD); 9219178132Sdavidch ctl = REG_RD_IND(sc, BCE_RXP_CFTQ_CTL); 9220178132Sdavidch cur_depth = (ctl & BCE_RXP_CFTQ_CTL_CUR_DEPTH) >> 22; 9221178132Sdavidch max_depth = (ctl & BCE_RXP_CFTQ_CTL_MAX_DEPTH) >> 12; 9222178132Sdavidch valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2); 9223179771Sdavidch BCE_PRINTF(" RXPC 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9224176448Sdavidch cmd, ctl, cur_depth, max_depth, valid_cnt); 9225178132Sdavidch 9226182293Sdavidch /* Input queue to the Receive Virtual to Physical state machine */ 9227178132Sdavidch cmd = REG_RD(sc, BCE_RV2P_PFTQ_CMD); 9228178132Sdavidch ctl = REG_RD(sc, BCE_RV2P_PFTQ_CTL); 9229178132Sdavidch cur_depth = (ctl & BCE_RV2P_PFTQ_CTL_CUR_DEPTH) >> 22; 9230178132Sdavidch max_depth = (ctl & BCE_RV2P_PFTQ_CTL_MAX_DEPTH) >> 12; 9231178132Sdavidch valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT3); 9232179771Sdavidch BCE_PRINTF(" RV2PP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9233176448Sdavidch cmd, ctl, cur_depth, max_depth, valid_cnt); 9234178132Sdavidch 9235182293Sdavidch /* Input queue to the Recevie Virtual to Physical state machine */ 9236178132Sdavidch cmd = REG_RD(sc, BCE_RV2P_MFTQ_CMD); 9237178132Sdavidch ctl = REG_RD(sc, BCE_RV2P_MFTQ_CTL); 9238178132Sdavidch cur_depth = (ctl & BCE_RV2P_MFTQ_CTL_CUR_DEPTH) >> 22; 9239178132Sdavidch max_depth = (ctl & BCE_RV2P_MFTQ_CTL_MAX_DEPTH) >> 12; 9240178132Sdavidch valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT4); 9241179771Sdavidch BCE_PRINTF(" RV2PM 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9242176448Sdavidch cmd, ctl, cur_depth, max_depth, valid_cnt); 9243178132Sdavidch 9244182293Sdavidch /* Input queue to the Receive Virtual to Physical state machine */ 9245178132Sdavidch cmd = REG_RD(sc, BCE_RV2P_TFTQ_CMD); 9246178132Sdavidch ctl = REG_RD(sc, BCE_RV2P_TFTQ_CTL); 9247178132Sdavidch cur_depth = (ctl & BCE_RV2P_TFTQ_CTL_CUR_DEPTH) >> 22; 9248178132Sdavidch max_depth = (ctl & BCE_RV2P_TFTQ_CTL_MAX_DEPTH) >> 12; 9249178132Sdavidch valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT5); 9250179771Sdavidch BCE_PRINTF(" RV2PT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9251176448Sdavidch cmd, ctl, cur_depth, max_depth, valid_cnt); 9252178132Sdavidch 9253182293Sdavidch /* Input queue to the Receive DMA state machine */ 9254178132Sdavidch cmd = REG_RD(sc, BCE_RDMA_FTQ_CMD); 9255178132Sdavidch ctl = REG_RD(sc, BCE_RDMA_FTQ_CTL); 9256178132Sdavidch cur_depth = (ctl & BCE_RDMA_FTQ_CTL_CUR_DEPTH) >> 22; 9257178132Sdavidch max_depth = (ctl & BCE_RDMA_FTQ_CTL_MAX_DEPTH) >> 12; 9258178132Sdavidch valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT6); 9259179771Sdavidch BCE_PRINTF(" RDMA 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9260176448Sdavidch cmd, ctl, cur_depth, max_depth, valid_cnt); 9261178132Sdavidch 9262182293Sdavidch /* Input queue to the Transmit Scheduler state machine */ 9263178132Sdavidch cmd = REG_RD(sc, BCE_TSCH_FTQ_CMD); 9264178132Sdavidch ctl = REG_RD(sc, BCE_TSCH_FTQ_CTL); 9265178132Sdavidch cur_depth = (ctl & BCE_TSCH_FTQ_CTL_CUR_DEPTH) >> 22; 9266178132Sdavidch max_depth = (ctl & BCE_TSCH_FTQ_CTL_MAX_DEPTH) >> 12; 9267178132Sdavidch valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT7); 9268179771Sdavidch BCE_PRINTF(" TSCH 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9269176448Sdavidch cmd, ctl, cur_depth, max_depth, valid_cnt); 9270178132Sdavidch 9271182293Sdavidch /* Input queue to the Transmit Buffer Descriptor state machine */ 9272178132Sdavidch cmd = REG_RD(sc, BCE_TBDR_FTQ_CMD); 9273178132Sdavidch ctl = REG_RD(sc, BCE_TBDR_FTQ_CTL); 9274178132Sdavidch cur_depth = (ctl & BCE_TBDR_FTQ_CTL_CUR_DEPTH) >> 22; 9275178132Sdavidch max_depth = (ctl & BCE_TBDR_FTQ_CTL_MAX_DEPTH) >> 12; 9276178132Sdavidch valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT8); 9277179771Sdavidch BCE_PRINTF(" TBDR 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9278176448Sdavidch cmd, ctl, cur_depth, max_depth, valid_cnt); 9279178132Sdavidch 9280182293Sdavidch /* Input queue to the Transmit Processor */ 9281178132Sdavidch cmd = REG_RD_IND(sc, BCE_TXP_FTQ_CMD); 9282178132Sdavidch ctl = REG_RD_IND(sc, BCE_TXP_FTQ_CTL); 9283178132Sdavidch cur_depth = (ctl & BCE_TXP_FTQ_CTL_CUR_DEPTH) >> 22; 9284178132Sdavidch max_depth = (ctl & BCE_TXP_FTQ_CTL_MAX_DEPTH) >> 12; 9285178132Sdavidch valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT9); 9286179771Sdavidch BCE_PRINTF(" TXP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9287176448Sdavidch cmd, ctl, cur_depth, max_depth, valid_cnt); 9288178132Sdavidch 9289182293Sdavidch /* Input queue to the Transmit DMA state machine */ 9290178132Sdavidch cmd = REG_RD(sc, BCE_TDMA_FTQ_CMD); 9291178132Sdavidch ctl = REG_RD(sc, BCE_TDMA_FTQ_CTL); 9292178132Sdavidch cur_depth = (ctl & BCE_TDMA_FTQ_CTL_CUR_DEPTH) >> 22; 9293178132Sdavidch max_depth = (ctl & BCE_TDMA_FTQ_CTL_MAX_DEPTH) >> 12; 9294178132Sdavidch valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT10); 9295179771Sdavidch BCE_PRINTF(" TDMA 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9296176448Sdavidch cmd, ctl, cur_depth, max_depth, valid_cnt); 9297178132Sdavidch 9298182293Sdavidch /* Input queue to the Transmit Patch-Up Processor */ 9299178132Sdavidch cmd = REG_RD_IND(sc, BCE_TPAT_FTQ_CMD); 9300178132Sdavidch ctl = REG_RD_IND(sc, BCE_TPAT_FTQ_CTL); 9301178132Sdavidch cur_depth = (ctl & BCE_TPAT_FTQ_CTL_CUR_DEPTH) >> 22; 9302178132Sdavidch max_depth = (ctl & BCE_TPAT_FTQ_CTL_MAX_DEPTH) >> 12; 9303178132Sdavidch valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT11); 9304179771Sdavidch BCE_PRINTF(" TPAT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9305176448Sdavidch cmd, ctl, cur_depth, max_depth, valid_cnt); 9306178132Sdavidch 9307182293Sdavidch /* Input queue to the Transmit Assembler state machine */ 9308178132Sdavidch cmd = REG_RD_IND(sc, BCE_TAS_FTQ_CMD); 9309178132Sdavidch ctl = REG_RD_IND(sc, BCE_TAS_FTQ_CTL); 9310178132Sdavidch cur_depth = (ctl & BCE_TAS_FTQ_CTL_CUR_DEPTH) >> 22; 9311178132Sdavidch max_depth = (ctl & BCE_TAS_FTQ_CTL_MAX_DEPTH) >> 12; 9312178132Sdavidch valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT12); 9313179771Sdavidch BCE_PRINTF(" TAS 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9314176448Sdavidch cmd, ctl, cur_depth, max_depth, valid_cnt); 9315178132Sdavidch 9316182293Sdavidch /* Input queue to the Completion Processor */ 9317178132Sdavidch cmd = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CMD); 9318178132Sdavidch ctl = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CTL); 9319178132Sdavidch cur_depth = (ctl & BCE_COM_COMXQ_FTQ_CTL_CUR_DEPTH) >> 22; 9320178132Sdavidch max_depth = (ctl & BCE_COM_COMXQ_FTQ_CTL_MAX_DEPTH) >> 12; 9321178132Sdavidch valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT13); 9322179771Sdavidch BCE_PRINTF(" COMX 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9323176448Sdavidch cmd, ctl, cur_depth, max_depth, valid_cnt); 9324178132Sdavidch 9325182293Sdavidch /* Input queue to the Completion Processor */ 9326178132Sdavidch cmd = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CMD); 9327178132Sdavidch ctl = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CTL); 9328178132Sdavidch cur_depth = (ctl & BCE_COM_COMTQ_FTQ_CTL_CUR_DEPTH) >> 22; 9329178132Sdavidch max_depth = (ctl & BCE_COM_COMTQ_FTQ_CTL_MAX_DEPTH) >> 12; 9330178132Sdavidch valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT14); 9331179771Sdavidch BCE_PRINTF(" COMT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9332176448Sdavidch cmd, ctl, cur_depth, max_depth, valid_cnt); 9333178132Sdavidch 9334182293Sdavidch /* Input queue to the Completion Processor */ 9335178132Sdavidch cmd = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CMD); 9336178132Sdavidch ctl = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CTL); 9337178132Sdavidch cur_depth = (ctl & BCE_COM_COMQ_FTQ_CTL_CUR_DEPTH) >> 22; 9338178132Sdavidch max_depth = (ctl & BCE_COM_COMQ_FTQ_CTL_MAX_DEPTH) >> 12; 9339178132Sdavidch valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT15); 9340179771Sdavidch BCE_PRINTF(" COMX 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9341176448Sdavidch cmd, ctl, cur_depth, max_depth, valid_cnt); 9342178132Sdavidch 9343178132Sdavidch /* Setup the generic statistic counters for the FTQ valid count. */ 9344179771Sdavidch val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT << 16) | 9345179771Sdavidch (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT << 8) | 9346179771Sdavidch (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT); 9347182293Sdavidch 9348182293Sdavidch if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 9349182293Sdavidch (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) 9350179771Sdavidch val = val | (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCSQ_VALID_CNT_XI << 24); 9351182293Sdavidch REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val); 9352182293Sdavidch 9353182293Sdavidch /* Input queue to the Management Control Processor */ 9354178132Sdavidch cmd = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CMD); 9355178132Sdavidch ctl = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CTL); 9356178132Sdavidch cur_depth = (ctl & BCE_MCP_MCPQ_FTQ_CTL_CUR_DEPTH) >> 22; 9357178132Sdavidch max_depth = (ctl & BCE_MCP_MCPQ_FTQ_CTL_MAX_DEPTH) >> 12; 9358178132Sdavidch valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0); 9359179771Sdavidch BCE_PRINTF(" MCP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9360176448Sdavidch cmd, ctl, cur_depth, max_depth, valid_cnt); 9361178132Sdavidch 9362182293Sdavidch /* Input queue to the Command Processor */ 9363178132Sdavidch cmd = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CMD); 9364178132Sdavidch ctl = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CTL); 9365178132Sdavidch cur_depth = (ctl & BCE_CP_CPQ_FTQ_CTL_CUR_DEPTH) >> 22; 9366178132Sdavidch max_depth = (ctl & BCE_CP_CPQ_FTQ_CTL_MAX_DEPTH) >> 12; 9367178132Sdavidch valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1); 9368179771Sdavidch BCE_PRINTF(" CP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9369176448Sdavidch cmd, ctl, cur_depth, max_depth, valid_cnt); 9370178132Sdavidch 9371182293Sdavidch /* Input queue to the Completion Scheduler state machine */ 9372178132Sdavidch cmd = REG_RD(sc, BCE_CSCH_CH_FTQ_CMD); 9373178132Sdavidch ctl = REG_RD(sc, BCE_CSCH_CH_FTQ_CTL); 9374178132Sdavidch cur_depth = (ctl & BCE_CSCH_CH_FTQ_CTL_CUR_DEPTH) >> 22; 9375178132Sdavidch max_depth = (ctl & BCE_CSCH_CH_FTQ_CTL_MAX_DEPTH) >> 12; 9376178132Sdavidch valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2); 9377179771Sdavidch BCE_PRINTF(" CS 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9378176448Sdavidch cmd, ctl, cur_depth, max_depth, valid_cnt); 9379178132Sdavidch 9380182293Sdavidch if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 9381182293Sdavidch (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 9382182293Sdavidch /* Input queue to the Receive Virtual to Physical Command Scheduler */ 9383179771Sdavidch cmd = REG_RD(sc, BCE_RV2PCSR_FTQ_CMD); 9384179771Sdavidch ctl = REG_RD(sc, BCE_RV2PCSR_FTQ_CTL); 9385179771Sdavidch cur_depth = (ctl & 0xFFC00000) >> 22; 9386179771Sdavidch max_depth = (ctl & 0x003FF000) >> 12; 9387179771Sdavidch valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT3); 9388179771Sdavidch BCE_PRINTF(" RV2PCSR 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9389182293Sdavidch cmd, ctl, cur_depth, max_depth, valid_cnt); 9390179771Sdavidch } 9391182293Sdavidch 9392176448Sdavidch BCE_PRINTF( 9393176448Sdavidch "----------------------------" 9394176448Sdavidch "----------------" 9395176448Sdavidch "----------------------------\n"); 9396176448Sdavidch} 9397176448Sdavidch 9398176448Sdavidch 9399176448Sdavidch/****************************************************************************/ 9400170810Sdavidch/* Prints out the TX chain. */ 9401169271Sdavidch/* */ 9402169271Sdavidch/* Returns: */ 9403169271Sdavidch/* Nothing. */ 9404169271Sdavidch/****************************************************************************/ 9405179771Sdavidchstatic __attribute__ ((noinline)) void 9406176448Sdavidchbce_dump_tx_chain(struct bce_softc *sc, u16 tx_prod, int count) 9407157642Sps{ 9408157642Sps struct tx_bd *txbd; 9409157642Sps 9410157642Sps /* First some info about the tx_bd chain structure. */ 9411169271Sdavidch BCE_PRINTF( 9412157642Sps "----------------------------" 9413157642Sps " tx_bd chain " 9414157642Sps "----------------------------\n"); 9415157642Sps 9416169271Sdavidch BCE_PRINTF("page size = 0x%08X, tx chain pages = 0x%08X\n", 9417157642Sps (u32) BCM_PAGE_SIZE, (u32) TX_PAGES); 9418157642Sps 9419169271Sdavidch BCE_PRINTF("tx_bd per page = 0x%08X, usable tx_bd per page = 0x%08X\n", 9420157642Sps (u32) TOTAL_TX_BD_PER_PAGE, (u32) USABLE_TX_BD_PER_PAGE); 9421157642Sps 9422169271Sdavidch BCE_PRINTF("total tx_bd = 0x%08X\n", (u32) TOTAL_TX_BD); 9423157642Sps 9424170810Sdavidch BCE_PRINTF( 9425169271Sdavidch "----------------------------" 9426169632Sdavidch " tx_bd data " 9427169271Sdavidch "----------------------------\n"); 9428157642Sps 9429157642Sps /* Now print out the tx_bd's themselves. */ 9430157642Sps for (int i = 0; i < count; i++) { 9431157642Sps txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)]; 9432157642Sps bce_dump_txbd(sc, tx_prod, txbd); 9433176448Sdavidch tx_prod = NEXT_TX_BD(tx_prod); 9434157642Sps } 9435157642Sps 9436169271Sdavidch BCE_PRINTF( 9437169271Sdavidch "----------------------------" 9438169271Sdavidch "----------------" 9439169271Sdavidch "----------------------------\n"); 9440157642Sps} 9441157642Sps 9442157642Sps 9443169271Sdavidch/****************************************************************************/ 9444170810Sdavidch/* Prints out the RX chain. */ 9445169271Sdavidch/* */ 9446169271Sdavidch/* Returns: */ 9447169271Sdavidch/* Nothing. */ 9448169271Sdavidch/****************************************************************************/ 9449179771Sdavidchstatic __attribute__ ((noinline)) void 9450176448Sdavidchbce_dump_rx_chain(struct bce_softc *sc, u16 rx_prod, int count) 9451157642Sps{ 9452157642Sps struct rx_bd *rxbd; 9453157642Sps 9454176448Sdavidch /* First some info about the rx_bd chain structure. */ 9455169271Sdavidch BCE_PRINTF( 9456157642Sps "----------------------------" 9457157642Sps " rx_bd chain " 9458157642Sps "----------------------------\n"); 9459157642Sps 9460169271Sdavidch BCE_PRINTF("page size = 0x%08X, rx chain pages = 0x%08X\n", 9461157642Sps (u32) BCM_PAGE_SIZE, (u32) RX_PAGES); 9462157642Sps 9463169271Sdavidch BCE_PRINTF("rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n", 9464157642Sps (u32) TOTAL_RX_BD_PER_PAGE, (u32) USABLE_RX_BD_PER_PAGE); 9465157642Sps 9466169271Sdavidch BCE_PRINTF("total rx_bd = 0x%08X\n", (u32) TOTAL_RX_BD); 9467157642Sps 9468169271Sdavidch BCE_PRINTF( 9469157642Sps "----------------------------" 9470157642Sps " rx_bd data " 9471157642Sps "----------------------------\n"); 9472157642Sps 9473157642Sps /* Now print out the rx_bd's themselves. */ 9474157642Sps for (int i = 0; i < count; i++) { 9475157642Sps rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)]; 9476157642Sps bce_dump_rxbd(sc, rx_prod, rxbd); 9477176448Sdavidch rx_prod = RX_CHAIN_IDX(rx_prod + 1); 9478157642Sps } 9479157642Sps 9480169271Sdavidch BCE_PRINTF( 9481157642Sps "----------------------------" 9482169271Sdavidch "----------------" 9483157642Sps "----------------------------\n"); 9484157642Sps} 9485157642Sps 9486157642Sps 9487198320Sstas#ifdef BCE_JUMBO_HDRSPLIT 9488169271Sdavidch/****************************************************************************/ 9489176448Sdavidch/* Prints out the page chain. */ 9490176448Sdavidch/* */ 9491176448Sdavidch/* Returns: */ 9492176448Sdavidch/* Nothing. */ 9493176448Sdavidch/****************************************************************************/ 9494179771Sdavidchstatic __attribute__ ((noinline)) void 9495176448Sdavidchbce_dump_pg_chain(struct bce_softc *sc, u16 pg_prod, int count) 9496176448Sdavidch{ 9497176448Sdavidch struct rx_bd *pgbd; 9498176448Sdavidch 9499176448Sdavidch /* First some info about the page chain structure. */ 9500176448Sdavidch BCE_PRINTF( 9501176448Sdavidch "----------------------------" 9502176448Sdavidch " page chain " 9503176448Sdavidch "----------------------------\n"); 9504176448Sdavidch 9505176448Sdavidch BCE_PRINTF("page size = 0x%08X, pg chain pages = 0x%08X\n", 9506176448Sdavidch (u32) BCM_PAGE_SIZE, (u32) PG_PAGES); 9507176448Sdavidch 9508176448Sdavidch BCE_PRINTF("rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n", 9509176448Sdavidch (u32) TOTAL_PG_BD_PER_PAGE, (u32) USABLE_PG_BD_PER_PAGE); 9510176448Sdavidch 9511178132Sdavidch BCE_PRINTF("total rx_bd = 0x%08X, max_pg_bd = 0x%08X\n", 9512176448Sdavidch (u32) TOTAL_PG_BD, (u32) MAX_PG_BD); 9513176448Sdavidch 9514176448Sdavidch BCE_PRINTF( 9515176448Sdavidch "----------------------------" 9516176448Sdavidch " page data " 9517176448Sdavidch "----------------------------\n"); 9518176448Sdavidch 9519176448Sdavidch /* Now print out the rx_bd's themselves. */ 9520176448Sdavidch for (int i = 0; i < count; i++) { 9521178132Sdavidch pgbd = &sc->pg_bd_chain[PG_PAGE(pg_prod)][PG_IDX(pg_prod)]; 9522176448Sdavidch bce_dump_pgbd(sc, pg_prod, pgbd); 9523176448Sdavidch pg_prod = PG_CHAIN_IDX(pg_prod + 1); 9524176448Sdavidch } 9525176448Sdavidch 9526176448Sdavidch BCE_PRINTF( 9527176448Sdavidch "----------------------------" 9528176448Sdavidch "----------------" 9529176448Sdavidch "----------------------------\n"); 9530179771Sdavidch} 9531179695Sdavidch#endif 9532176448Sdavidch 9533176448Sdavidch 9534176448Sdavidch/****************************************************************************/ 9535169271Sdavidch/* Prints out the status block from host memory. */ 9536169271Sdavidch/* */ 9537169271Sdavidch/* Returns: */ 9538169271Sdavidch/* Nothing. */ 9539169271Sdavidch/****************************************************************************/ 9540179771Sdavidchstatic __attribute__ ((noinline)) void 9541157642Spsbce_dump_status_block(struct bce_softc *sc) 9542157642Sps{ 9543157642Sps struct status_block *sblk; 9544157642Sps 9545157642Sps sblk = sc->status_block; 9546157642Sps 9547169271Sdavidch BCE_PRINTF( 9548169271Sdavidch "----------------------------" 9549169271Sdavidch " Status Block " 9550169271Sdavidch "----------------------------\n"); 9551170392Sdavidch 9552169632Sdavidch BCE_PRINTF(" 0x%08X - attn_bits\n", 9553169632Sdavidch sblk->status_attn_bits); 9554157642Sps 9555169632Sdavidch BCE_PRINTF(" 0x%08X - attn_bits_ack\n", 9556169632Sdavidch sblk->status_attn_bits_ack); 9557157642Sps 9558169632Sdavidch BCE_PRINTF("0x%04X(0x%04X) - rx_cons0\n", 9559179771Sdavidch sblk->status_rx_quick_consumer_index0, 9560169632Sdavidch (u16) RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index0)); 9561170392Sdavidch 9562169632Sdavidch BCE_PRINTF("0x%04X(0x%04X) - tx_cons0\n", 9563179771Sdavidch sblk->status_tx_quick_consumer_index0, 9564169632Sdavidch (u16) TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index0)); 9565157642Sps 9566169632Sdavidch BCE_PRINTF(" 0x%04X - status_idx\n", sblk->status_idx); 9567169632Sdavidch 9568157642Sps /* Theses indices are not used for normal L2 drivers. */ 9569169632Sdavidch if (sblk->status_rx_quick_consumer_index1) 9570169632Sdavidch BCE_PRINTF("0x%04X(0x%04X) - rx_cons1\n", 9571157642Sps sblk->status_rx_quick_consumer_index1, 9572169632Sdavidch (u16) RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index1)); 9573170392Sdavidch 9574169632Sdavidch if (sblk->status_tx_quick_consumer_index1) 9575169632Sdavidch BCE_PRINTF("0x%04X(0x%04X) - tx_cons1\n", 9576169632Sdavidch sblk->status_tx_quick_consumer_index1, 9577169632Sdavidch (u16) TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index1)); 9578157642Sps 9579169632Sdavidch if (sblk->status_rx_quick_consumer_index2) 9580169632Sdavidch BCE_PRINTF("0x%04X(0x%04X)- rx_cons2\n", 9581157642Sps sblk->status_rx_quick_consumer_index2, 9582169632Sdavidch (u16) RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index2)); 9583170392Sdavidch 9584169632Sdavidch if (sblk->status_tx_quick_consumer_index2) 9585169632Sdavidch BCE_PRINTF("0x%04X(0x%04X) - tx_cons2\n", 9586169632Sdavidch sblk->status_tx_quick_consumer_index2, 9587169632Sdavidch (u16) TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index2)); 9588170392Sdavidch 9589169632Sdavidch if (sblk->status_rx_quick_consumer_index3) 9590169632Sdavidch BCE_PRINTF("0x%04X(0x%04X) - rx_cons3\n", 9591157642Sps sblk->status_rx_quick_consumer_index3, 9592169632Sdavidch (u16) RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index3)); 9593170392Sdavidch 9594169632Sdavidch if (sblk->status_tx_quick_consumer_index3) 9595169632Sdavidch BCE_PRINTF("0x%04X(0x%04X) - tx_cons3\n", 9596169632Sdavidch sblk->status_tx_quick_consumer_index3, 9597169632Sdavidch (u16) TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index3)); 9598170392Sdavidch 9599179771Sdavidch if (sblk->status_rx_quick_consumer_index4 || 9600157642Sps sblk->status_rx_quick_consumer_index5) 9601169271Sdavidch BCE_PRINTF("rx_cons4 = 0x%08X, rx_cons5 = 0x%08X\n", 9602157642Sps sblk->status_rx_quick_consumer_index4, 9603157642Sps sblk->status_rx_quick_consumer_index5); 9604157642Sps 9605179771Sdavidch if (sblk->status_rx_quick_consumer_index6 || 9606157642Sps sblk->status_rx_quick_consumer_index7) 9607169271Sdavidch BCE_PRINTF("rx_cons6 = 0x%08X, rx_cons7 = 0x%08X\n", 9608157642Sps sblk->status_rx_quick_consumer_index6, 9609157642Sps sblk->status_rx_quick_consumer_index7); 9610157642Sps 9611179771Sdavidch if (sblk->status_rx_quick_consumer_index8 || 9612157642Sps sblk->status_rx_quick_consumer_index9) 9613169271Sdavidch BCE_PRINTF("rx_cons8 = 0x%08X, rx_cons9 = 0x%08X\n", 9614157642Sps sblk->status_rx_quick_consumer_index8, 9615157642Sps sblk->status_rx_quick_consumer_index9); 9616157642Sps 9617179771Sdavidch if (sblk->status_rx_quick_consumer_index10 || 9618157642Sps sblk->status_rx_quick_consumer_index11) 9619169271Sdavidch BCE_PRINTF("rx_cons10 = 0x%08X, rx_cons11 = 0x%08X\n", 9620157642Sps sblk->status_rx_quick_consumer_index10, 9621157642Sps sblk->status_rx_quick_consumer_index11); 9622157642Sps 9623179771Sdavidch if (sblk->status_rx_quick_consumer_index12 || 9624157642Sps sblk->status_rx_quick_consumer_index13) 9625169271Sdavidch BCE_PRINTF("rx_cons12 = 0x%08X, rx_cons13 = 0x%08X\n", 9626157642Sps sblk->status_rx_quick_consumer_index12, 9627157642Sps sblk->status_rx_quick_consumer_index13); 9628157642Sps 9629179771Sdavidch if (sblk->status_rx_quick_consumer_index14 || 9630157642Sps sblk->status_rx_quick_consumer_index15) 9631169271Sdavidch BCE_PRINTF("rx_cons14 = 0x%08X, rx_cons15 = 0x%08X\n", 9632157642Sps sblk->status_rx_quick_consumer_index14, 9633157642Sps sblk->status_rx_quick_consumer_index15); 9634157642Sps 9635179771Sdavidch if (sblk->status_completion_producer_index || 9636157642Sps sblk->status_cmd_consumer_index) 9637169271Sdavidch BCE_PRINTF("com_prod = 0x%08X, cmd_cons = 0x%08X\n", 9638157642Sps sblk->status_completion_producer_index, 9639157642Sps sblk->status_cmd_consumer_index); 9640170392Sdavidch 9641169271Sdavidch BCE_PRINTF( 9642169271Sdavidch "----------------------------" 9643169271Sdavidch "----------------" 9644169271Sdavidch "----------------------------\n"); 9645157642Sps} 9646157642Sps 9647157642Sps 9648169271Sdavidch/****************************************************************************/ 9649170810Sdavidch/* Prints out the statistics block from host memory. */ 9650169271Sdavidch/* */ 9651169271Sdavidch/* Returns: */ 9652169271Sdavidch/* Nothing. */ 9653169271Sdavidch/****************************************************************************/ 9654179771Sdavidchstatic __attribute__ ((noinline)) void 9655157642Spsbce_dump_stats_block(struct bce_softc *sc) 9656157642Sps{ 9657157642Sps struct statistics_block *sblk; 9658157642Sps 9659157642Sps sblk = sc->stats_block; 9660170392Sdavidch 9661169271Sdavidch BCE_PRINTF( 9662169632Sdavidch "---------------" 9663169632Sdavidch " Stats Block (All Stats Not Shown Are 0) " 9664169632Sdavidch "---------------\n"); 9665157642Sps 9666179771Sdavidch if (sblk->stat_IfHCInOctets_hi 9667169632Sdavidch || sblk->stat_IfHCInOctets_lo) 9668169632Sdavidch BCE_PRINTF("0x%08X:%08X : " 9669179771Sdavidch "IfHcInOctets\n", 9670179771Sdavidch sblk->stat_IfHCInOctets_hi, 9671170392Sdavidch sblk->stat_IfHCInOctets_lo); 9672170392Sdavidch 9673179771Sdavidch if (sblk->stat_IfHCInBadOctets_hi 9674169632Sdavidch || sblk->stat_IfHCInBadOctets_lo) 9675169632Sdavidch BCE_PRINTF("0x%08X:%08X : " 9676179771Sdavidch "IfHcInBadOctets\n", 9677179771Sdavidch sblk->stat_IfHCInBadOctets_hi, 9678170392Sdavidch sblk->stat_IfHCInBadOctets_lo); 9679170392Sdavidch 9680179771Sdavidch if (sblk->stat_IfHCOutOctets_hi 9681169632Sdavidch || sblk->stat_IfHCOutOctets_lo) 9682169632Sdavidch BCE_PRINTF("0x%08X:%08X : " 9683179771Sdavidch "IfHcOutOctets\n", 9684179771Sdavidch sblk->stat_IfHCOutOctets_hi, 9685170392Sdavidch sblk->stat_IfHCOutOctets_lo); 9686170392Sdavidch 9687179771Sdavidch if (sblk->stat_IfHCOutBadOctets_hi 9688169632Sdavidch || sblk->stat_IfHCOutBadOctets_lo) 9689169632Sdavidch BCE_PRINTF("0x%08X:%08X : " 9690179771Sdavidch "IfHcOutBadOctets\n", 9691179771Sdavidch sblk->stat_IfHCOutBadOctets_hi, 9692170392Sdavidch sblk->stat_IfHCOutBadOctets_lo); 9693170392Sdavidch 9694179771Sdavidch if (sblk->stat_IfHCInUcastPkts_hi 9695169632Sdavidch || sblk->stat_IfHCInUcastPkts_lo) 9696169632Sdavidch BCE_PRINTF("0x%08X:%08X : " 9697179771Sdavidch "IfHcInUcastPkts\n", 9698179771Sdavidch sblk->stat_IfHCInUcastPkts_hi, 9699170392Sdavidch sblk->stat_IfHCInUcastPkts_lo); 9700170392Sdavidch 9701179771Sdavidch if (sblk->stat_IfHCInBroadcastPkts_hi 9702169632Sdavidch || sblk->stat_IfHCInBroadcastPkts_lo) 9703169632Sdavidch BCE_PRINTF("0x%08X:%08X : " 9704179771Sdavidch "IfHcInBroadcastPkts\n", 9705179771Sdavidch sblk->stat_IfHCInBroadcastPkts_hi, 9706170392Sdavidch sblk->stat_IfHCInBroadcastPkts_lo); 9707170392Sdavidch 9708179771Sdavidch if (sblk->stat_IfHCInMulticastPkts_hi 9709169632Sdavidch || sblk->stat_IfHCInMulticastPkts_lo) 9710169632Sdavidch BCE_PRINTF("0x%08X:%08X : " 9711179771Sdavidch "IfHcInMulticastPkts\n", 9712179771Sdavidch sblk->stat_IfHCInMulticastPkts_hi, 9713170392Sdavidch sblk->stat_IfHCInMulticastPkts_lo); 9714170392Sdavidch 9715179771Sdavidch if (sblk->stat_IfHCOutUcastPkts_hi 9716169632Sdavidch || sblk->stat_IfHCOutUcastPkts_lo) 9717169632Sdavidch BCE_PRINTF("0x%08X:%08X : " 9718179771Sdavidch "IfHcOutUcastPkts\n", 9719179771Sdavidch sblk->stat_IfHCOutUcastPkts_hi, 9720170392Sdavidch sblk->stat_IfHCOutUcastPkts_lo); 9721170392Sdavidch 9722179771Sdavidch if (sblk->stat_IfHCOutBroadcastPkts_hi 9723169632Sdavidch || sblk->stat_IfHCOutBroadcastPkts_lo) 9724169632Sdavidch BCE_PRINTF("0x%08X:%08X : " 9725179771Sdavidch "IfHcOutBroadcastPkts\n", 9726179771Sdavidch sblk->stat_IfHCOutBroadcastPkts_hi, 9727170392Sdavidch sblk->stat_IfHCOutBroadcastPkts_lo); 9728170392Sdavidch 9729179771Sdavidch if (sblk->stat_IfHCOutMulticastPkts_hi 9730169632Sdavidch || sblk->stat_IfHCOutMulticastPkts_lo) 9731169632Sdavidch BCE_PRINTF("0x%08X:%08X : " 9732179771Sdavidch "IfHcOutMulticastPkts\n", 9733179771Sdavidch sblk->stat_IfHCOutMulticastPkts_hi, 9734170392Sdavidch sblk->stat_IfHCOutMulticastPkts_lo); 9735170392Sdavidch 9736157642Sps if (sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors) 9737169632Sdavidch BCE_PRINTF(" 0x%08X : " 9738179771Sdavidch "emac_tx_stat_dot3statsinternalmactransmiterrors\n", 9739169632Sdavidch sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors); 9740157642Sps 9741157642Sps if (sblk->stat_Dot3StatsCarrierSenseErrors) 9742169632Sdavidch BCE_PRINTF(" 0x%08X : Dot3StatsCarrierSenseErrors\n", 9743157642Sps sblk->stat_Dot3StatsCarrierSenseErrors); 9744157642Sps 9745157642Sps if (sblk->stat_Dot3StatsFCSErrors) 9746169632Sdavidch BCE_PRINTF(" 0x%08X : Dot3StatsFCSErrors\n", 9747157642Sps sblk->stat_Dot3StatsFCSErrors); 9748157642Sps 9749157642Sps if (sblk->stat_Dot3StatsAlignmentErrors) 9750169632Sdavidch BCE_PRINTF(" 0x%08X : Dot3StatsAlignmentErrors\n", 9751157642Sps sblk->stat_Dot3StatsAlignmentErrors); 9752157642Sps 9753157642Sps if (sblk->stat_Dot3StatsSingleCollisionFrames) 9754169632Sdavidch BCE_PRINTF(" 0x%08X : Dot3StatsSingleCollisionFrames\n", 9755157642Sps sblk->stat_Dot3StatsSingleCollisionFrames); 9756157642Sps 9757157642Sps if (sblk->stat_Dot3StatsMultipleCollisionFrames) 9758169632Sdavidch BCE_PRINTF(" 0x%08X : Dot3StatsMultipleCollisionFrames\n", 9759157642Sps sblk->stat_Dot3StatsMultipleCollisionFrames); 9760179771Sdavidch 9761157642Sps if (sblk->stat_Dot3StatsDeferredTransmissions) 9762169632Sdavidch BCE_PRINTF(" 0x%08X : Dot3StatsDeferredTransmissions\n", 9763157642Sps sblk->stat_Dot3StatsDeferredTransmissions); 9764157642Sps 9765157642Sps if (sblk->stat_Dot3StatsExcessiveCollisions) 9766169632Sdavidch BCE_PRINTF(" 0x%08X : Dot3StatsExcessiveCollisions\n", 9767157642Sps sblk->stat_Dot3StatsExcessiveCollisions); 9768157642Sps 9769157642Sps if (sblk->stat_Dot3StatsLateCollisions) 9770169632Sdavidch BCE_PRINTF(" 0x%08X : Dot3StatsLateCollisions\n", 9771157642Sps sblk->stat_Dot3StatsLateCollisions); 9772157642Sps 9773157642Sps if (sblk->stat_EtherStatsCollisions) 9774169632Sdavidch BCE_PRINTF(" 0x%08X : EtherStatsCollisions\n", 9775157642Sps sblk->stat_EtherStatsCollisions); 9776157642Sps 9777179771Sdavidch if (sblk->stat_EtherStatsFragments) 9778169632Sdavidch BCE_PRINTF(" 0x%08X : EtherStatsFragments\n", 9779157642Sps sblk->stat_EtherStatsFragments); 9780157642Sps 9781157642Sps if (sblk->stat_EtherStatsJabbers) 9782169632Sdavidch BCE_PRINTF(" 0x%08X : EtherStatsJabbers\n", 9783157642Sps sblk->stat_EtherStatsJabbers); 9784157642Sps 9785157642Sps if (sblk->stat_EtherStatsUndersizePkts) 9786169632Sdavidch BCE_PRINTF(" 0x%08X : EtherStatsUndersizePkts\n", 9787157642Sps sblk->stat_EtherStatsUndersizePkts); 9788157642Sps 9789189325Sdavidch if (sblk->stat_EtherStatsOversizePkts) 9790169632Sdavidch BCE_PRINTF(" 0x%08X : EtherStatsOverrsizePkts\n", 9791189325Sdavidch sblk->stat_EtherStatsOversizePkts); 9792157642Sps 9793157642Sps if (sblk->stat_EtherStatsPktsRx64Octets) 9794169632Sdavidch BCE_PRINTF(" 0x%08X : EtherStatsPktsRx64Octets\n", 9795157642Sps sblk->stat_EtherStatsPktsRx64Octets); 9796157642Sps 9797157642Sps if (sblk->stat_EtherStatsPktsRx65Octetsto127Octets) 9798169632Sdavidch BCE_PRINTF(" 0x%08X : EtherStatsPktsRx65Octetsto127Octets\n", 9799157642Sps sblk->stat_EtherStatsPktsRx65Octetsto127Octets); 9800157642Sps 9801157642Sps if (sblk->stat_EtherStatsPktsRx128Octetsto255Octets) 9802169632Sdavidch BCE_PRINTF(" 0x%08X : EtherStatsPktsRx128Octetsto255Octets\n", 9803157642Sps sblk->stat_EtherStatsPktsRx128Octetsto255Octets); 9804157642Sps 9805157642Sps if (sblk->stat_EtherStatsPktsRx256Octetsto511Octets) 9806169632Sdavidch BCE_PRINTF(" 0x%08X : EtherStatsPktsRx256Octetsto511Octets\n", 9807157642Sps sblk->stat_EtherStatsPktsRx256Octetsto511Octets); 9808157642Sps 9809157642Sps if (sblk->stat_EtherStatsPktsRx512Octetsto1023Octets) 9810169632Sdavidch BCE_PRINTF(" 0x%08X : EtherStatsPktsRx512Octetsto1023Octets\n", 9811157642Sps sblk->stat_EtherStatsPktsRx512Octetsto1023Octets); 9812157642Sps 9813157642Sps if (sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets) 9814169632Sdavidch BCE_PRINTF(" 0x%08X : EtherStatsPktsRx1024Octetsto1522Octets\n", 9815157642Sps sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets); 9816157642Sps 9817157642Sps if (sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets) 9818169632Sdavidch BCE_PRINTF(" 0x%08X : EtherStatsPktsRx1523Octetsto9022Octets\n", 9819157642Sps sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets); 9820157642Sps 9821157642Sps if (sblk->stat_EtherStatsPktsTx64Octets) 9822169632Sdavidch BCE_PRINTF(" 0x%08X : EtherStatsPktsTx64Octets\n", 9823157642Sps sblk->stat_EtherStatsPktsTx64Octets); 9824157642Sps 9825157642Sps if (sblk->stat_EtherStatsPktsTx65Octetsto127Octets) 9826169632Sdavidch BCE_PRINTF(" 0x%08X : EtherStatsPktsTx65Octetsto127Octets\n", 9827157642Sps sblk->stat_EtherStatsPktsTx65Octetsto127Octets); 9828157642Sps 9829157642Sps if (sblk->stat_EtherStatsPktsTx128Octetsto255Octets) 9830169632Sdavidch BCE_PRINTF(" 0x%08X : EtherStatsPktsTx128Octetsto255Octets\n", 9831157642Sps sblk->stat_EtherStatsPktsTx128Octetsto255Octets); 9832157642Sps 9833157642Sps if (sblk->stat_EtherStatsPktsTx256Octetsto511Octets) 9834169632Sdavidch BCE_PRINTF(" 0x%08X : EtherStatsPktsTx256Octetsto511Octets\n", 9835157642Sps sblk->stat_EtherStatsPktsTx256Octetsto511Octets); 9836157642Sps 9837157642Sps if (sblk->stat_EtherStatsPktsTx512Octetsto1023Octets) 9838169632Sdavidch BCE_PRINTF(" 0x%08X : EtherStatsPktsTx512Octetsto1023Octets\n", 9839157642Sps sblk->stat_EtherStatsPktsTx512Octetsto1023Octets); 9840157642Sps 9841157642Sps if (sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets) 9842169632Sdavidch BCE_PRINTF(" 0x%08X : EtherStatsPktsTx1024Octetsto1522Octets\n", 9843157642Sps sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets); 9844157642Sps 9845157642Sps if (sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets) 9846169632Sdavidch BCE_PRINTF(" 0x%08X : EtherStatsPktsTx1523Octetsto9022Octets\n", 9847157642Sps sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets); 9848157642Sps 9849157642Sps if (sblk->stat_XonPauseFramesReceived) 9850169632Sdavidch BCE_PRINTF(" 0x%08X : XonPauseFramesReceived\n", 9851157642Sps sblk->stat_XonPauseFramesReceived); 9852157642Sps 9853157642Sps if (sblk->stat_XoffPauseFramesReceived) 9854169632Sdavidch BCE_PRINTF(" 0x%08X : XoffPauseFramesReceived\n", 9855157642Sps sblk->stat_XoffPauseFramesReceived); 9856157642Sps 9857157642Sps if (sblk->stat_OutXonSent) 9858169632Sdavidch BCE_PRINTF(" 0x%08X : OutXonSent\n", 9859157642Sps sblk->stat_OutXonSent); 9860157642Sps 9861157642Sps if (sblk->stat_OutXoffSent) 9862169632Sdavidch BCE_PRINTF(" 0x%08X : OutXoffSent\n", 9863157642Sps sblk->stat_OutXoffSent); 9864157642Sps 9865157642Sps if (sblk->stat_FlowControlDone) 9866169632Sdavidch BCE_PRINTF(" 0x%08X : FlowControlDone\n", 9867157642Sps sblk->stat_FlowControlDone); 9868157642Sps 9869157642Sps if (sblk->stat_MacControlFramesReceived) 9870169632Sdavidch BCE_PRINTF(" 0x%08X : MacControlFramesReceived\n", 9871157642Sps sblk->stat_MacControlFramesReceived); 9872157642Sps 9873157642Sps if (sblk->stat_XoffStateEntered) 9874169632Sdavidch BCE_PRINTF(" 0x%08X : XoffStateEntered\n", 9875157642Sps sblk->stat_XoffStateEntered); 9876157642Sps 9877157642Sps if (sblk->stat_IfInFramesL2FilterDiscards) 9878169632Sdavidch BCE_PRINTF(" 0x%08X : IfInFramesL2FilterDiscards\n", 9879157642Sps sblk->stat_IfInFramesL2FilterDiscards); 9880157642Sps 9881157642Sps if (sblk->stat_IfInRuleCheckerDiscards) 9882169632Sdavidch BCE_PRINTF(" 0x%08X : IfInRuleCheckerDiscards\n", 9883157642Sps sblk->stat_IfInRuleCheckerDiscards); 9884157642Sps 9885157642Sps if (sblk->stat_IfInFTQDiscards) 9886169632Sdavidch BCE_PRINTF(" 0x%08X : IfInFTQDiscards\n", 9887157642Sps sblk->stat_IfInFTQDiscards); 9888157642Sps 9889157642Sps if (sblk->stat_IfInMBUFDiscards) 9890169632Sdavidch BCE_PRINTF(" 0x%08X : IfInMBUFDiscards\n", 9891157642Sps sblk->stat_IfInMBUFDiscards); 9892157642Sps 9893157642Sps if (sblk->stat_IfInRuleCheckerP4Hit) 9894169632Sdavidch BCE_PRINTF(" 0x%08X : IfInRuleCheckerP4Hit\n", 9895157642Sps sblk->stat_IfInRuleCheckerP4Hit); 9896157642Sps 9897157642Sps if (sblk->stat_CatchupInRuleCheckerDiscards) 9898169632Sdavidch BCE_PRINTF(" 0x%08X : CatchupInRuleCheckerDiscards\n", 9899157642Sps sblk->stat_CatchupInRuleCheckerDiscards); 9900157642Sps 9901157642Sps if (sblk->stat_CatchupInFTQDiscards) 9902169632Sdavidch BCE_PRINTF(" 0x%08X : CatchupInFTQDiscards\n", 9903157642Sps sblk->stat_CatchupInFTQDiscards); 9904157642Sps 9905157642Sps if (sblk->stat_CatchupInMBUFDiscards) 9906169632Sdavidch BCE_PRINTF(" 0x%08X : CatchupInMBUFDiscards\n", 9907157642Sps sblk->stat_CatchupInMBUFDiscards); 9908157642Sps 9909157642Sps if (sblk->stat_CatchupInRuleCheckerP4Hit) 9910169632Sdavidch BCE_PRINTF(" 0x%08X : CatchupInRuleCheckerP4Hit\n", 9911157642Sps sblk->stat_CatchupInRuleCheckerP4Hit); 9912157642Sps 9913169271Sdavidch BCE_PRINTF( 9914169271Sdavidch "----------------------------" 9915169271Sdavidch "----------------" 9916169271Sdavidch "----------------------------\n"); 9917157642Sps} 9918157642Sps 9919157642Sps 9920169271Sdavidch/****************************************************************************/ 9921169271Sdavidch/* Prints out a summary of the driver state. */ 9922169271Sdavidch/* */ 9923169271Sdavidch/* Returns: */ 9924169271Sdavidch/* Nothing. */ 9925169271Sdavidch/****************************************************************************/ 9926179771Sdavidchstatic __attribute__ ((noinline)) void 9927157642Spsbce_dump_driver_state(struct bce_softc *sc) 9928157642Sps{ 9929157642Sps u32 val_hi, val_lo; 9930157642Sps 9931169271Sdavidch BCE_PRINTF( 9932157642Sps "-----------------------------" 9933157642Sps " Driver State " 9934157642Sps "-----------------------------\n"); 9935157642Sps 9936157642Sps val_hi = BCE_ADDR_HI(sc); 9937157642Sps val_lo = BCE_ADDR_LO(sc); 9938169271Sdavidch BCE_PRINTF("0x%08X:%08X - (sc) driver softc structure virtual address\n", 9939157642Sps val_hi, val_lo); 9940157642Sps 9941157642Sps val_hi = BCE_ADDR_HI(sc->bce_vhandle); 9942157642Sps val_lo = BCE_ADDR_LO(sc->bce_vhandle); 9943169271Sdavidch BCE_PRINTF("0x%08X:%08X - (sc->bce_vhandle) PCI BAR virtual address\n", 9944157642Sps val_hi, val_lo); 9945157642Sps 9946157642Sps val_hi = BCE_ADDR_HI(sc->status_block); 9947157642Sps val_lo = BCE_ADDR_LO(sc->status_block); 9948169271Sdavidch BCE_PRINTF("0x%08X:%08X - (sc->status_block) status block virtual address\n", 9949157642Sps val_hi, val_lo); 9950157642Sps 9951157642Sps val_hi = BCE_ADDR_HI(sc->stats_block); 9952157642Sps val_lo = BCE_ADDR_LO(sc->stats_block); 9953169271Sdavidch BCE_PRINTF("0x%08X:%08X - (sc->stats_block) statistics block virtual address\n", 9954157642Sps val_hi, val_lo); 9955157642Sps 9956157642Sps val_hi = BCE_ADDR_HI(sc->tx_bd_chain); 9957157642Sps val_lo = BCE_ADDR_LO(sc->tx_bd_chain); 9958169271Sdavidch BCE_PRINTF( 9959157642Sps "0x%08X:%08X - (sc->tx_bd_chain) tx_bd chain virtual adddress\n", 9960157642Sps val_hi, val_lo); 9961157642Sps 9962157642Sps val_hi = BCE_ADDR_HI(sc->rx_bd_chain); 9963157642Sps val_lo = BCE_ADDR_LO(sc->rx_bd_chain); 9964169271Sdavidch BCE_PRINTF( 9965157642Sps "0x%08X:%08X - (sc->rx_bd_chain) rx_bd chain virtual address\n", 9966157642Sps val_hi, val_lo); 9967157642Sps 9968198320Sstas#ifdef BCE_JUMBO_HDRSPLIT 9969176448Sdavidch val_hi = BCE_ADDR_HI(sc->pg_bd_chain); 9970176448Sdavidch val_lo = BCE_ADDR_LO(sc->pg_bd_chain); 9971176448Sdavidch BCE_PRINTF( 9972176448Sdavidch "0x%08X:%08X - (sc->pg_bd_chain) page chain virtual address\n", 9973179771Sdavidch val_hi, val_lo); 9974179695Sdavidch#endif 9975176448Sdavidch 9976157642Sps val_hi = BCE_ADDR_HI(sc->tx_mbuf_ptr); 9977157642Sps val_lo = BCE_ADDR_LO(sc->tx_mbuf_ptr); 9978169271Sdavidch BCE_PRINTF( 9979157642Sps "0x%08X:%08X - (sc->tx_mbuf_ptr) tx mbuf chain virtual address\n", 9980157642Sps val_hi, val_lo); 9981157642Sps 9982157642Sps val_hi = BCE_ADDR_HI(sc->rx_mbuf_ptr); 9983157642Sps val_lo = BCE_ADDR_LO(sc->rx_mbuf_ptr); 9984179771Sdavidch BCE_PRINTF( 9985157642Sps "0x%08X:%08X - (sc->rx_mbuf_ptr) rx mbuf chain virtual address\n", 9986157642Sps val_hi, val_lo); 9987157642Sps 9988198320Sstas#ifdef BCE_JUMBO_HDRSPLIT 9989176448Sdavidch val_hi = BCE_ADDR_HI(sc->pg_mbuf_ptr); 9990176448Sdavidch val_lo = BCE_ADDR_LO(sc->pg_mbuf_ptr); 9991179771Sdavidch BCE_PRINTF( 9992176448Sdavidch "0x%08X:%08X - (sc->pg_mbuf_ptr) page mbuf chain virtual address\n", 9993179771Sdavidch val_hi, val_lo); 9994179695Sdavidch#endif 9995176448Sdavidch 9996169271Sdavidch BCE_PRINTF(" 0x%08X - (sc->interrupts_generated) h/w intrs\n", 9997157642Sps sc->interrupts_generated); 9998179771Sdavidch 9999169271Sdavidch BCE_PRINTF(" 0x%08X - (sc->rx_interrupts) rx interrupts handled\n", 10000157642Sps sc->rx_interrupts); 10001157642Sps 10002169271Sdavidch BCE_PRINTF(" 0x%08X - (sc->tx_interrupts) tx interrupts handled\n", 10003157642Sps sc->tx_interrupts); 10004157642Sps 10005169271Sdavidch BCE_PRINTF(" 0x%08X - (sc->last_status_idx) status block index\n", 10006157642Sps sc->last_status_idx); 10007157642Sps 10008169632Sdavidch BCE_PRINTF(" 0x%04X(0x%04X) - (sc->tx_prod) tx producer index\n", 10009169632Sdavidch sc->tx_prod, (u16) TX_CHAIN_IDX(sc->tx_prod)); 10010157642Sps 10011169632Sdavidch BCE_PRINTF(" 0x%04X(0x%04X) - (sc->tx_cons) tx consumer index\n", 10012169632Sdavidch sc->tx_cons, (u16) TX_CHAIN_IDX(sc->tx_cons)); 10013157642Sps 10014169271Sdavidch BCE_PRINTF(" 0x%08X - (sc->tx_prod_bseq) tx producer bseq index\n", 10015157642Sps sc->tx_prod_bseq); 10016157642Sps 10017176448Sdavidch BCE_PRINTF(" 0x%08X - (sc->debug_tx_mbuf_alloc) tx mbufs allocated\n", 10018176448Sdavidch sc->debug_tx_mbuf_alloc); 10019171667Sdavidch 10020171667Sdavidch BCE_PRINTF(" 0x%08X - (sc->used_tx_bd) used tx_bd's\n", 10021171667Sdavidch sc->used_tx_bd); 10022171667Sdavidch 10023171667Sdavidch BCE_PRINTF("0x%08X/%08X - (sc->tx_hi_watermark) tx hi watermark\n", 10024171667Sdavidch sc->tx_hi_watermark, sc->max_tx_bd); 10025171667Sdavidch 10026169632Sdavidch BCE_PRINTF(" 0x%04X(0x%04X) - (sc->rx_prod) rx producer index\n", 10027169632Sdavidch sc->rx_prod, (u16) RX_CHAIN_IDX(sc->rx_prod)); 10028157642Sps 10029169632Sdavidch BCE_PRINTF(" 0x%04X(0x%04X) - (sc->rx_cons) rx consumer index\n", 10030169632Sdavidch sc->rx_cons, (u16) RX_CHAIN_IDX(sc->rx_cons)); 10031157642Sps 10032169271Sdavidch BCE_PRINTF(" 0x%08X - (sc->rx_prod_bseq) rx producer bseq index\n", 10033157642Sps sc->rx_prod_bseq); 10034157642Sps 10035176448Sdavidch BCE_PRINTF(" 0x%08X - (sc->debug_rx_mbuf_alloc) rx mbufs allocated\n", 10036176448Sdavidch sc->debug_rx_mbuf_alloc); 10037157642Sps 10038169271Sdavidch BCE_PRINTF(" 0x%08X - (sc->free_rx_bd) free rx_bd's\n", 10039157642Sps sc->free_rx_bd); 10040157642Sps 10041198320Sstas#ifdef BCE_JUMBO_HDRSPLIT 10042176448Sdavidch BCE_PRINTF(" 0x%04X(0x%04X) - (sc->pg_prod) page producer index\n", 10043176448Sdavidch sc->pg_prod, (u16) PG_CHAIN_IDX(sc->pg_prod)); 10044157642Sps 10045176448Sdavidch BCE_PRINTF(" 0x%04X(0x%04X) - (sc->pg_cons) page consumer index\n", 10046176448Sdavidch sc->pg_cons, (u16) PG_CHAIN_IDX(sc->pg_cons)); 10047176448Sdavidch 10048176448Sdavidch BCE_PRINTF(" 0x%08X - (sc->debug_pg_mbuf_alloc) page mbufs allocated\n", 10049176448Sdavidch sc->debug_pg_mbuf_alloc); 10050176448Sdavidch 10051176448Sdavidch BCE_PRINTF(" 0x%08X - (sc->free_pg_bd) free page rx_bd's\n", 10052176448Sdavidch sc->free_pg_bd); 10053176448Sdavidch 10054176448Sdavidch BCE_PRINTF("0x%08X/%08X - (sc->pg_low_watermark) page low watermark\n", 10055176448Sdavidch sc->pg_low_watermark, sc->max_pg_bd); 10056179771Sdavidch#endif 10057176448Sdavidch 10058189325Sdavidch BCE_PRINTF(" 0x%08X - (sc->mbuf_alloc_failed_count) " 10059171667Sdavidch "mbuf alloc failures\n", 10060189325Sdavidch sc->mbuf_alloc_failed_count); 10061157642Sps 10062179771Sdavidch BCE_PRINTF(" 0x%08X - (sc->bce_flags) bce mac flags\n", 10063179771Sdavidch sc->bce_flags); 10064179771Sdavidch 10065179771Sdavidch BCE_PRINTF(" 0x%08X - (sc->bce_phy_flags) bce phy flags\n", 10066179771Sdavidch sc->bce_phy_flags); 10067179771Sdavidch 10068169271Sdavidch BCE_PRINTF( 10069169271Sdavidch "----------------------------" 10070169271Sdavidch "----------------" 10071169271Sdavidch "----------------------------\n"); 10072157642Sps} 10073157642Sps 10074170392Sdavidch 10075169271Sdavidch/****************************************************************************/ 10076170810Sdavidch/* Prints out the hardware state through a summary of important register, */ 10077169271Sdavidch/* followed by a complete register dump. */ 10078169271Sdavidch/* */ 10079169271Sdavidch/* Returns: */ 10080169271Sdavidch/* Nothing. */ 10081169271Sdavidch/****************************************************************************/ 10082179771Sdavidchstatic __attribute__ ((noinline)) void 10083157642Spsbce_dump_hw_state(struct bce_softc *sc) 10084157642Sps{ 10085176448Sdavidch u32 val; 10086157642Sps 10087169271Sdavidch BCE_PRINTF( 10088157642Sps "----------------------------" 10089157642Sps " Hardware State " 10090157642Sps "----------------------------\n"); 10091157642Sps 10092194781Sdavidch BCE_PRINTF("%s - bootcode version\n", sc->bce_bc_ver); 10093157642Sps 10094176448Sdavidch val = REG_RD(sc, BCE_MISC_ENABLE_STATUS_BITS); 10095169632Sdavidch BCE_PRINTF("0x%08X - (0x%06X) misc_enable_status_bits\n", 10096176448Sdavidch val, BCE_MISC_ENABLE_STATUS_BITS); 10097157642Sps 10098176448Sdavidch val = REG_RD(sc, BCE_DMA_STATUS); 10099176448Sdavidch BCE_PRINTF("0x%08X - (0x%06X) dma_status\n", val, BCE_DMA_STATUS); 10100157642Sps 10101176448Sdavidch val = REG_RD(sc, BCE_CTX_STATUS); 10102176448Sdavidch BCE_PRINTF("0x%08X - (0x%06X) ctx_status\n", val, BCE_CTX_STATUS); 10103157642Sps 10104176448Sdavidch val = REG_RD(sc, BCE_EMAC_STATUS); 10105176448Sdavidch BCE_PRINTF("0x%08X - (0x%06X) emac_status\n", val, BCE_EMAC_STATUS); 10106157642Sps 10107176448Sdavidch val = REG_RD(sc, BCE_RPM_STATUS); 10108176448Sdavidch BCE_PRINTF("0x%08X - (0x%06X) rpm_status\n", val, BCE_RPM_STATUS); 10109157642Sps 10110176448Sdavidch val = REG_RD(sc, 0x2004); 10111176448Sdavidch BCE_PRINTF("0x%08X - (0x%06X) rlup_status\n", val, 0x2004); 10112157642Sps 10113176448Sdavidch val = REG_RD(sc, BCE_RV2P_STATUS); 10114176448Sdavidch BCE_PRINTF("0x%08X - (0x%06X) rv2p_status\n", val, BCE_RV2P_STATUS); 10115157642Sps 10116176448Sdavidch val = REG_RD(sc, 0x2c04); 10117176448Sdavidch BCE_PRINTF("0x%08X - (0x%06X) rdma_status\n", val, 0x2c04); 10118157642Sps 10119176448Sdavidch val = REG_RD(sc, BCE_TBDR_STATUS); 10120176448Sdavidch BCE_PRINTF("0x%08X - (0x%06X) tbdr_status\n", val, BCE_TBDR_STATUS); 10121169632Sdavidch 10122176448Sdavidch val = REG_RD(sc, BCE_TDMA_STATUS); 10123176448Sdavidch BCE_PRINTF("0x%08X - (0x%06X) tdma_status\n", val, BCE_TDMA_STATUS); 10124169632Sdavidch 10125176448Sdavidch val = REG_RD(sc, BCE_HC_STATUS); 10126176448Sdavidch BCE_PRINTF("0x%08X - (0x%06X) hc_status\n", val, BCE_HC_STATUS); 10127169632Sdavidch 10128176448Sdavidch val = REG_RD_IND(sc, BCE_TXP_CPU_STATE); 10129176448Sdavidch BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n", val, BCE_TXP_CPU_STATE); 10130169632Sdavidch 10131176448Sdavidch val = REG_RD_IND(sc, BCE_TPAT_CPU_STATE); 10132176448Sdavidch BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n", val, BCE_TPAT_CPU_STATE); 10133169632Sdavidch 10134176448Sdavidch val = REG_RD_IND(sc, BCE_RXP_CPU_STATE); 10135176448Sdavidch BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n", val, BCE_RXP_CPU_STATE); 10136169632Sdavidch 10137176448Sdavidch val = REG_RD_IND(sc, BCE_COM_CPU_STATE); 10138176448Sdavidch BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n", val, BCE_COM_CPU_STATE); 10139176448Sdavidch 10140176448Sdavidch val = REG_RD_IND(sc, BCE_MCP_CPU_STATE); 10141176448Sdavidch BCE_PRINTF("0x%08X - (0x%06X) mcp_cpu_state\n", val, BCE_MCP_CPU_STATE); 10142176448Sdavidch 10143176448Sdavidch val = REG_RD_IND(sc, BCE_CP_CPU_STATE); 10144176448Sdavidch BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n", val, BCE_CP_CPU_STATE); 10145176448Sdavidch 10146179771Sdavidch BCE_PRINTF( 10147157642Sps "----------------------------" 10148157642Sps "----------------" 10149157642Sps "----------------------------\n"); 10150157642Sps 10151179771Sdavidch BCE_PRINTF( 10152157642Sps "----------------------------" 10153157642Sps " Register Dump " 10154157642Sps "----------------------------\n"); 10155170392Sdavidch 10156178132Sdavidch for (int i = 0x400; i < 0x8000; i += 0x10) { 10157169271Sdavidch BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 10158157642Sps i, REG_RD(sc, i), REG_RD(sc, i + 0x4), 10159178132Sdavidch REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC)); 10160176448Sdavidch } 10161157642Sps 10162179771Sdavidch BCE_PRINTF( 10163157642Sps "----------------------------" 10164157642Sps "----------------" 10165157642Sps "----------------------------\n"); 10166157642Sps} 10167157642Sps 10168157642Sps 10169169271Sdavidch/****************************************************************************/ 10170179771Sdavidch/* Prints out the mailbox queue registers. */ 10171179771Sdavidch/* */ 10172179771Sdavidch/* Returns: */ 10173179771Sdavidch/* Nothing. */ 10174179771Sdavidch/****************************************************************************/ 10175179771Sdavidchstatic __attribute__ ((noinline)) void 10176179771Sdavidchbce_dump_mq_regs(struct bce_softc *sc) 10177179771Sdavidch{ 10178179771Sdavidch BCE_PRINTF( 10179179771Sdavidch "----------------------------" 10180179771Sdavidch " MQ Regs " 10181179771Sdavidch "----------------------------\n"); 10182179771Sdavidch 10183179771Sdavidch BCE_PRINTF( 10184179771Sdavidch "----------------------------" 10185179771Sdavidch "----------------" 10186179771Sdavidch "----------------------------\n"); 10187179771Sdavidch 10188179771Sdavidch for (int i = 0x3c00; i < 0x4000; i += 0x10) { 10189179771Sdavidch BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 10190179771Sdavidch i, REG_RD(sc, i), REG_RD(sc, i + 0x4), 10191179771Sdavidch REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC)); 10192179771Sdavidch } 10193179771Sdavidch 10194179771Sdavidch BCE_PRINTF( 10195179771Sdavidch "----------------------------" 10196179771Sdavidch "----------------" 10197179771Sdavidch "----------------------------\n"); 10198179771Sdavidch} 10199179771Sdavidch 10200179771Sdavidch 10201179771Sdavidch/****************************************************************************/ 10202170810Sdavidch/* Prints out the bootcode state. */ 10203170810Sdavidch/* */ 10204170810Sdavidch/* Returns: */ 10205170810Sdavidch/* Nothing. */ 10206170810Sdavidch/****************************************************************************/ 10207179771Sdavidchstatic __attribute__ ((noinline)) void 10208170810Sdavidchbce_dump_bc_state(struct bce_softc *sc) 10209170810Sdavidch{ 10210170810Sdavidch u32 val; 10211170810Sdavidch 10212170810Sdavidch BCE_PRINTF( 10213170810Sdavidch "----------------------------" 10214170810Sdavidch " Bootcode State " 10215170810Sdavidch "----------------------------\n"); 10216170810Sdavidch 10217194781Sdavidch BCE_PRINTF("%s - bootcode version\n", sc->bce_bc_ver); 10218170810Sdavidch 10219194781Sdavidch val = bce_shmem_rd(sc, BCE_BC_RESET_TYPE); 10220170810Sdavidch BCE_PRINTF("0x%08X - (0x%06X) reset_type\n", 10221170810Sdavidch val, BCE_BC_RESET_TYPE); 10222170810Sdavidch 10223194781Sdavidch val = bce_shmem_rd(sc, BCE_BC_STATE); 10224170810Sdavidch BCE_PRINTF("0x%08X - (0x%06X) state\n", 10225170810Sdavidch val, BCE_BC_STATE); 10226170810Sdavidch 10227202717Sdavidch val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); 10228170810Sdavidch BCE_PRINTF("0x%08X - (0x%06X) condition\n", 10229202717Sdavidch val, BCE_BC_STATE_CONDITION); 10230170810Sdavidch 10231194781Sdavidch val = bce_shmem_rd(sc, BCE_BC_STATE_DEBUG_CMD); 10232170810Sdavidch BCE_PRINTF("0x%08X - (0x%06X) debug_cmd\n", 10233170810Sdavidch val, BCE_BC_STATE_DEBUG_CMD); 10234170810Sdavidch 10235179771Sdavidch BCE_PRINTF( 10236170810Sdavidch "----------------------------" 10237170810Sdavidch "----------------" 10238170810Sdavidch "----------------------------\n"); 10239170810Sdavidch} 10240170810Sdavidch 10241170810Sdavidch 10242170810Sdavidch/****************************************************************************/ 10243179771Sdavidch/* Prints out the TXP processor state. */ 10244169632Sdavidch/* */ 10245169632Sdavidch/* Returns: */ 10246169632Sdavidch/* Nothing. */ 10247169632Sdavidch/****************************************************************************/ 10248179771Sdavidchstatic __attribute__ ((noinline)) void 10249179771Sdavidchbce_dump_txp_state(struct bce_softc *sc, int regs) 10250169632Sdavidch{ 10251179771Sdavidch u32 val; 10252182293Sdavidch u32 fw_version[3]; 10253169632Sdavidch 10254169632Sdavidch BCE_PRINTF( 10255169632Sdavidch "----------------------------" 10256169632Sdavidch " TXP State " 10257169632Sdavidch "----------------------------\n"); 10258169632Sdavidch 10259182293Sdavidch for (int i = 0; i < 3; i++) 10260182293Sdavidch fw_version[i] = htonl(REG_RD_IND(sc, 10261182293Sdavidch (BCE_TXP_SCRATCH + 0x10 + i * 4))); 10262182293Sdavidch BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 10263182293Sdavidch 10264179771Sdavidch val = REG_RD_IND(sc, BCE_TXP_CPU_MODE); 10265179771Sdavidch BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_mode\n", val, BCE_TXP_CPU_MODE); 10266169632Sdavidch 10267179771Sdavidch val = REG_RD_IND(sc, BCE_TXP_CPU_STATE); 10268179771Sdavidch BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n", val, BCE_TXP_CPU_STATE); 10269169632Sdavidch 10270179771Sdavidch val = REG_RD_IND(sc, BCE_TXP_CPU_EVENT_MASK); 10271179771Sdavidch BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_event_mask\n", val, 10272179771Sdavidch BCE_TXP_CPU_EVENT_MASK); 10273169632Sdavidch 10274179771Sdavidch if (regs) { 10275179771Sdavidch BCE_PRINTF( 10276179771Sdavidch "----------------------------" 10277179771Sdavidch " Register Dump " 10278179771Sdavidch "----------------------------\n"); 10279170392Sdavidch 10280179771Sdavidch for (int i = BCE_TXP_CPU_MODE; i < 0x68000; i += 0x10) { 10281179771Sdavidch /* Skip the big blank spaces */ 10282179771Sdavidch if (i < 0x454000 && i > 0x5ffff) 10283179771Sdavidch BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 10284179771Sdavidch i, REG_RD_IND(sc, i), REG_RD_IND(sc, i + 0x4), 10285179771Sdavidch REG_RD_IND(sc, i + 0x8), REG_RD_IND(sc, i + 0xC)); 10286179771Sdavidch } 10287169632Sdavidch } 10288169632Sdavidch 10289179771Sdavidch BCE_PRINTF( 10290169632Sdavidch "----------------------------" 10291169632Sdavidch "----------------" 10292169632Sdavidch "----------------------------\n"); 10293169632Sdavidch} 10294169632Sdavidch 10295169632Sdavidch 10296169632Sdavidch/****************************************************************************/ 10297179771Sdavidch/* Prints out the RXP processor state. */ 10298169632Sdavidch/* */ 10299169632Sdavidch/* Returns: */ 10300169632Sdavidch/* Nothing. */ 10301169632Sdavidch/****************************************************************************/ 10302179771Sdavidchstatic __attribute__ ((noinline)) void 10303179771Sdavidchbce_dump_rxp_state(struct bce_softc *sc, int regs) 10304169632Sdavidch{ 10305179771Sdavidch u32 val; 10306182293Sdavidch u32 fw_version[3]; 10307169632Sdavidch 10308169632Sdavidch BCE_PRINTF( 10309169632Sdavidch "----------------------------" 10310169632Sdavidch " RXP State " 10311169632Sdavidch "----------------------------\n"); 10312169632Sdavidch 10313182293Sdavidch for (int i = 0; i < 3; i++) 10314182293Sdavidch fw_version[i] = htonl(REG_RD_IND(sc, 10315182293Sdavidch (BCE_RXP_SCRATCH + 0x10 + i * 4))); 10316182293Sdavidch BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 10317182293Sdavidch 10318179771Sdavidch val = REG_RD_IND(sc, BCE_RXP_CPU_MODE); 10319179771Sdavidch BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_mode\n", val, BCE_RXP_CPU_MODE); 10320169632Sdavidch 10321179771Sdavidch val = REG_RD_IND(sc, BCE_RXP_CPU_STATE); 10322179771Sdavidch BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n", val, BCE_RXP_CPU_STATE); 10323169632Sdavidch 10324179771Sdavidch val = REG_RD_IND(sc, BCE_RXP_CPU_EVENT_MASK); 10325179771Sdavidch BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_event_mask\n", val, 10326179771Sdavidch BCE_RXP_CPU_EVENT_MASK); 10327169632Sdavidch 10328179771Sdavidch if (regs) { 10329179771Sdavidch BCE_PRINTF( 10330179771Sdavidch "----------------------------" 10331179771Sdavidch " Register Dump " 10332179771Sdavidch "----------------------------\n"); 10333179771Sdavidch 10334179771Sdavidch for (int i = BCE_RXP_CPU_MODE; i < 0xe8fff; i += 0x10) { 10335179771Sdavidch /* Skip the big blank sapces */ 10336179771Sdavidch if (i < 0xc5400 && i > 0xdffff) 10337179771Sdavidch BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 10338179771Sdavidch i, REG_RD_IND(sc, i), REG_RD_IND(sc, i + 0x4), 10339179771Sdavidch REG_RD_IND(sc, i + 0x8), REG_RD_IND(sc, i + 0xC)); 10340179771Sdavidch } 10341179771Sdavidch } 10342179771Sdavidch 10343179771Sdavidch BCE_PRINTF( 10344169632Sdavidch "----------------------------" 10345179771Sdavidch "----------------" 10346169632Sdavidch "----------------------------\n"); 10347179771Sdavidch} 10348170392Sdavidch 10349179771Sdavidch 10350179771Sdavidch/****************************************************************************/ 10351179771Sdavidch/* Prints out the TPAT processor state. */ 10352179771Sdavidch/* */ 10353179771Sdavidch/* Returns: */ 10354179771Sdavidch/* Nothing. */ 10355179771Sdavidch/****************************************************************************/ 10356179771Sdavidchstatic __attribute__ ((noinline)) void 10357179771Sdavidchbce_dump_tpat_state(struct bce_softc *sc, int regs) 10358179771Sdavidch{ 10359179771Sdavidch u32 val; 10360182293Sdavidch u32 fw_version[3]; 10361179771Sdavidch 10362179771Sdavidch BCE_PRINTF( 10363179771Sdavidch "----------------------------" 10364179771Sdavidch " TPAT State " 10365179771Sdavidch "----------------------------\n"); 10366179771Sdavidch 10367182293Sdavidch for (int i = 0; i < 3; i++) 10368182293Sdavidch fw_version[i] = htonl(REG_RD_IND(sc, 10369182293Sdavidch (BCE_TPAT_SCRATCH + 0x410 + i * 4))); 10370182293Sdavidch BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 10371182293Sdavidch 10372179771Sdavidch val = REG_RD_IND(sc, BCE_TPAT_CPU_MODE); 10373179771Sdavidch BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_mode\n", val, BCE_TPAT_CPU_MODE); 10374179771Sdavidch 10375179771Sdavidch val = REG_RD_IND(sc, BCE_TPAT_CPU_STATE); 10376179771Sdavidch BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n", val, BCE_TPAT_CPU_STATE); 10377179771Sdavidch 10378179771Sdavidch val = REG_RD_IND(sc, BCE_TPAT_CPU_EVENT_MASK); 10379179771Sdavidch BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_event_mask\n", val, 10380179771Sdavidch BCE_TPAT_CPU_EVENT_MASK); 10381179771Sdavidch 10382179771Sdavidch if (regs) { 10383179771Sdavidch BCE_PRINTF( 10384179771Sdavidch "----------------------------" 10385179771Sdavidch " Register Dump " 10386179771Sdavidch "----------------------------\n"); 10387179771Sdavidch 10388179771Sdavidch for (int i = BCE_TPAT_CPU_MODE; i < 0xa3fff; i += 0x10) { 10389179771Sdavidch /* Skip the big blank spaces */ 10390179771Sdavidch if (i < 0x854000 && i > 0x9ffff) 10391179771Sdavidch BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 10392179771Sdavidch i, REG_RD_IND(sc, i), REG_RD_IND(sc, i + 0x4), 10393179771Sdavidch REG_RD_IND(sc, i + 0x8), REG_RD_IND(sc, i + 0xC)); 10394179771Sdavidch } 10395169632Sdavidch } 10396169632Sdavidch 10397179771Sdavidch BCE_PRINTF( 10398169632Sdavidch "----------------------------" 10399169632Sdavidch "----------------" 10400169632Sdavidch "----------------------------\n"); 10401169632Sdavidch} 10402169632Sdavidch 10403169632Sdavidch 10404169632Sdavidch/****************************************************************************/ 10405179771Sdavidch/* Prints out the Command Procesor (CP) state. */ 10406169632Sdavidch/* */ 10407169632Sdavidch/* Returns: */ 10408169632Sdavidch/* Nothing. */ 10409169632Sdavidch/****************************************************************************/ 10410179771Sdavidchstatic __attribute__ ((noinline)) void 10411179771Sdavidchbce_dump_cp_state(struct bce_softc *sc, int regs) 10412169632Sdavidch{ 10413179771Sdavidch u32 val; 10414182293Sdavidch u32 fw_version[3]; 10415169632Sdavidch 10416169632Sdavidch BCE_PRINTF( 10417169632Sdavidch "----------------------------" 10418179771Sdavidch " CP State " 10419169632Sdavidch "----------------------------\n"); 10420169632Sdavidch 10421182293Sdavidch for (int i = 0; i < 3; i++) 10422182293Sdavidch fw_version[i] = htonl(REG_RD_IND(sc, 10423182293Sdavidch (BCE_CP_SCRATCH + 0x10 + i * 4))); 10424182293Sdavidch BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 10425182293Sdavidch 10426179771Sdavidch val = REG_RD_IND(sc, BCE_CP_CPU_MODE); 10427179771Sdavidch BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_mode\n", val, BCE_CP_CPU_MODE); 10428169632Sdavidch 10429179771Sdavidch val = REG_RD_IND(sc, BCE_CP_CPU_STATE); 10430179771Sdavidch BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n", val, BCE_CP_CPU_STATE); 10431169632Sdavidch 10432179771Sdavidch val = REG_RD_IND(sc, BCE_CP_CPU_EVENT_MASK); 10433179771Sdavidch BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_event_mask\n", val, 10434179771Sdavidch BCE_CP_CPU_EVENT_MASK); 10435169632Sdavidch 10436179771Sdavidch if (regs) { 10437179771Sdavidch BCE_PRINTF( 10438179771Sdavidch "----------------------------" 10439179771Sdavidch " Register Dump " 10440179771Sdavidch "----------------------------\n"); 10441179771Sdavidch 10442179771Sdavidch for (int i = BCE_CP_CPU_MODE; i < 0x1aa000; i += 0x10) { 10443179771Sdavidch /* Skip the big blank spaces */ 10444179771Sdavidch if (i < 0x185400 && i > 0x19ffff) 10445179771Sdavidch BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 10446179771Sdavidch i, REG_RD_IND(sc, i), REG_RD_IND(sc, i + 0x4), 10447179771Sdavidch REG_RD_IND(sc, i + 0x8), REG_RD_IND(sc, i + 0xC)); 10448179771Sdavidch } 10449179771Sdavidch } 10450179771Sdavidch 10451179771Sdavidch BCE_PRINTF( 10452169632Sdavidch "----------------------------" 10453179771Sdavidch "----------------" 10454169632Sdavidch "----------------------------\n"); 10455179771Sdavidch} 10456170392Sdavidch 10457179771Sdavidch 10458179771Sdavidch/****************************************************************************/ 10459179771Sdavidch/* Prints out the Completion Procesor (COM) state. */ 10460179771Sdavidch/* */ 10461179771Sdavidch/* Returns: */ 10462179771Sdavidch/* Nothing. */ 10463179771Sdavidch/****************************************************************************/ 10464179771Sdavidchstatic __attribute__ ((noinline)) void 10465179771Sdavidchbce_dump_com_state(struct bce_softc *sc, int regs) 10466179771Sdavidch{ 10467179771Sdavidch u32 val; 10468182293Sdavidch u32 fw_version[3]; 10469179771Sdavidch 10470179771Sdavidch BCE_PRINTF( 10471179771Sdavidch "----------------------------" 10472179771Sdavidch " COM State " 10473179771Sdavidch "----------------------------\n"); 10474179771Sdavidch 10475182293Sdavidch for (int i = 0; i < 3; i++) 10476182293Sdavidch fw_version[i] = htonl(REG_RD_IND(sc, 10477182293Sdavidch (BCE_COM_SCRATCH + 0x10 + i * 4))); 10478182293Sdavidch BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 10479182293Sdavidch 10480179771Sdavidch val = REG_RD_IND(sc, BCE_COM_CPU_MODE); 10481179771Sdavidch BCE_PRINTF("0x%08X - (0x%06X) com_cpu_mode\n", val, BCE_COM_CPU_MODE); 10482179771Sdavidch 10483179771Sdavidch val = REG_RD_IND(sc, BCE_COM_CPU_STATE); 10484179771Sdavidch BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n", val, BCE_COM_CPU_STATE); 10485179771Sdavidch 10486179771Sdavidch val = REG_RD_IND(sc, BCE_COM_CPU_EVENT_MASK); 10487179771Sdavidch BCE_PRINTF("0x%08X - (0x%06X) com_cpu_event_mask\n", val, 10488179771Sdavidch BCE_COM_CPU_EVENT_MASK); 10489179771Sdavidch 10490179771Sdavidch if (regs) { 10491179771Sdavidch BCE_PRINTF( 10492179771Sdavidch "----------------------------" 10493179771Sdavidch " Register Dump " 10494179771Sdavidch "----------------------------\n"); 10495179771Sdavidch 10496179771Sdavidch for (int i = BCE_COM_CPU_MODE; i < 0x1053e8; i += 0x10) { 10497169632Sdavidch BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 10498169632Sdavidch i, REG_RD_IND(sc, i), REG_RD_IND(sc, i + 0x4), 10499170392Sdavidch REG_RD_IND(sc, i + 0x8), REG_RD_IND(sc, i + 0xC)); 10500179771Sdavidch } 10501169632Sdavidch } 10502169632Sdavidch 10503179771Sdavidch BCE_PRINTF( 10504169632Sdavidch "----------------------------" 10505169632Sdavidch "----------------" 10506169632Sdavidch "----------------------------\n"); 10507169632Sdavidch} 10508169632Sdavidch 10509169632Sdavidch 10510169632Sdavidch/****************************************************************************/ 10511170392Sdavidch/* Prints out the driver state and then enters the debugger. */ 10512169271Sdavidch/* */ 10513169271Sdavidch/* Returns: */ 10514169271Sdavidch/* Nothing. */ 10515169271Sdavidch/****************************************************************************/ 10516157642Spsstatic void 10517157642Spsbce_breakpoint(struct bce_softc *sc) 10518157642Sps{ 10519157642Sps 10520179771Sdavidch /* 10521179771Sdavidch * Unreachable code to silence compiler warnings 10522179771Sdavidch * about unused functions. 10523176448Sdavidch */ 10524157642Sps if (0) { 10525170392Sdavidch bce_freeze_controller(sc); 10526170392Sdavidch bce_unfreeze_controller(sc); 10527182293Sdavidch bce_dump_enet(sc, NULL); 10528157642Sps bce_dump_txbd(sc, 0, NULL); 10529157642Sps bce_dump_rxbd(sc, 0, NULL); 10530157642Sps bce_dump_tx_mbuf_chain(sc, 0, USABLE_TX_BD); 10531176448Sdavidch bce_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD); 10532157642Sps bce_dump_l2fhdr(sc, 0, NULL); 10533176448Sdavidch bce_dump_ctx(sc, RX_CID); 10534176448Sdavidch bce_dump_ftqs(sc); 10535157642Sps bce_dump_tx_chain(sc, 0, USABLE_TX_BD); 10536176448Sdavidch bce_dump_rx_chain(sc, 0, USABLE_RX_BD); 10537157642Sps bce_dump_status_block(sc); 10538157642Sps bce_dump_stats_block(sc); 10539157642Sps bce_dump_driver_state(sc); 10540157642Sps bce_dump_hw_state(sc); 10541170810Sdavidch bce_dump_bc_state(sc); 10542179771Sdavidch bce_dump_txp_state(sc, 0); 10543179771Sdavidch bce_dump_rxp_state(sc, 0); 10544179771Sdavidch bce_dump_tpat_state(sc, 0); 10545179771Sdavidch bce_dump_cp_state(sc, 0); 10546182293Sdavidch bce_dump_com_state(sc, 0); 10547198320Sstas#ifdef BCE_JUMBO_HDRSPLIT 10548179695Sdavidch bce_dump_pgbd(sc, 0, NULL); 10549179771Sdavidch bce_dump_pg_mbuf_chain(sc, 0, USABLE_PG_BD); 10550179695Sdavidch bce_dump_pg_chain(sc, 0, USABLE_PG_BD); 10551179695Sdavidch#endif 10552157642Sps } 10553157642Sps 10554176448Sdavidch bce_dump_status_block(sc); 10555157642Sps bce_dump_driver_state(sc); 10556178132Sdavidch 10557157642Sps /* Call the debugger. */ 10558157642Sps breakpoint(); 10559157642Sps 10560157642Sps return; 10561157642Sps} 10562157642Sps#endif 10563170810Sdavidch 10564