if_ath_tdma.c revision 243614
1/*- 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: head/sys/dev/ath/if_ath_tdma.c 243614 2012-11-27 11:30:39Z adrian $"); 32 33/* 34 * Driver for the Atheros Wireless LAN controller. 35 * 36 * This software is derived from work of Atsushi Onoe; his contribution 37 * is greatly appreciated. 38 */ 39 40#include "opt_inet.h" 41#include "opt_ath.h" 42/* 43 * This is needed for register operations which are performed 44 * by the driver - eg, calls to ath_hal_gettsf32(). 45 * 46 * It's also required for any AH_DEBUG checks in here, eg the 47 * module dependencies. 48 */ 49#include "opt_ah.h" 50#include "opt_wlan.h" 51 52#include <sys/param.h> 53#include <sys/systm.h> 54#include <sys/sysctl.h> 55#include <sys/mbuf.h> 56#include <sys/malloc.h> 57#include <sys/lock.h> 58#include <sys/mutex.h> 59#include <sys/kernel.h> 60#include <sys/socket.h> 61#include <sys/sockio.h> 62#include <sys/errno.h> 63#include <sys/callout.h> 64#include <sys/bus.h> 65#include <sys/endian.h> 66#include <sys/kthread.h> 67#include <sys/taskqueue.h> 68#include <sys/priv.h> 69#include <sys/module.h> 70#include <sys/ktr.h> 71#include <sys/smp.h> /* for mp_ncpus */ 72 73#include <machine/bus.h> 74 75#include <net/if.h> 76#include <net/if_dl.h> 77#include <net/if_media.h> 78#include <net/if_types.h> 79#include <net/if_arp.h> 80#include <net/ethernet.h> 81#include <net/if_llc.h> 82 83#include <net80211/ieee80211_var.h> 84#include <net80211/ieee80211_regdomain.h> 85#ifdef IEEE80211_SUPPORT_SUPERG 86#include <net80211/ieee80211_superg.h> 87#endif 88#ifdef IEEE80211_SUPPORT_TDMA 89#include <net80211/ieee80211_tdma.h> 90#endif 91 92#include <net/bpf.h> 93 94#ifdef INET 95#include <netinet/in.h> 96#include <netinet/if_ether.h> 97#endif 98 99#include <dev/ath/if_athvar.h> 100#include <dev/ath/ath_hal/ah_devid.h> /* XXX for softled */ 101#include <dev/ath/ath_hal/ah_diagcodes.h> 102 103#include <dev/ath/if_ath_debug.h> 104#include <dev/ath/if_ath_misc.h> 105#include <dev/ath/if_ath_tsf.h> 106#include <dev/ath/if_ath_tx.h> 107#include <dev/ath/if_ath_sysctl.h> 108#include <dev/ath/if_ath_led.h> 109#include <dev/ath/if_ath_keycache.h> 110#include <dev/ath/if_ath_rx.h> 111#include <dev/ath/if_ath_beacon.h> 112#include <dev/ath/if_athdfs.h> 113 114#ifdef ATH_TX99_DIAG 115#include <dev/ath/ath_tx99/ath_tx99.h> 116#endif 117 118#ifdef ATH_DEBUG_ALQ 119#include <dev/ath/if_ath_alq.h> 120#endif 121 122#ifdef IEEE80211_SUPPORT_TDMA 123#include <dev/ath/if_ath_tdma.h> 124 125static void ath_tdma_settimers(struct ath_softc *sc, u_int32_t nexttbtt, 126 u_int32_t bintval); 127static void ath_tdma_bintvalsetup(struct ath_softc *sc, 128 const struct ieee80211_tdma_state *tdma); 129#endif /* IEEE80211_SUPPORT_TDMA */ 130 131#ifdef IEEE80211_SUPPORT_TDMA 132static void 133ath_tdma_settimers(struct ath_softc *sc, u_int32_t nexttbtt, u_int32_t bintval) 134{ 135 struct ath_hal *ah = sc->sc_ah; 136 HAL_BEACON_TIMERS bt; 137 138 bt.bt_intval = bintval | HAL_BEACON_ENA; 139 bt.bt_nexttbtt = nexttbtt; 140 bt.bt_nextdba = (nexttbtt<<3) - sc->sc_tdmadbaprep; 141 bt.bt_nextswba = (nexttbtt<<3) - sc->sc_tdmaswbaprep; 142 bt.bt_nextatim = nexttbtt+1; 143 /* Enables TBTT, DBA, SWBA timers by default */ 144 bt.bt_flags = 0; 145#if 0 146 DPRINTF(sc, ATH_DEBUG_TDMA_TIMER, 147 "%s: intval=%d (0x%08x) nexttbtt=%u (0x%08x), nextdba=%u (0x%08x), nextswba=%u (0x%08x),nextatim=%u (0x%08x)\n", 148 __func__, 149 bt.bt_intval, 150 bt.bt_intval, 151 bt.bt_nexttbtt, 152 bt.bt_nexttbtt, 153 bt.bt_nextdba, 154 bt.bt_nextdba, 155 bt.bt_nextswba, 156 bt.bt_nextswba, 157 bt.bt_nextatim, 158 bt.bt_nextatim); 159#endif 160 161#ifdef ATH_DEBUG_ALQ 162 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_TDMA_TIMER_SET)) { 163 struct if_ath_alq_tdma_timer_set t; 164 t.bt_intval = htobe32(bt.bt_intval); 165 t.bt_nexttbtt = htobe32(bt.bt_nexttbtt); 166 t.bt_nextdba = htobe32(bt.bt_nextdba); 167 t.bt_nextswba = htobe32(bt.bt_nextswba); 168 t.bt_nextatim = htobe32(bt.bt_nextatim); 169 t.bt_flags = htobe32(bt.bt_flags); 170 t.sc_tdmadbaprep = htobe32(sc->sc_tdmadbaprep); 171 t.sc_tdmaswbaprep = htobe32(sc->sc_tdmaswbaprep); 172 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_TDMA_TIMER_SET, 173 sizeof(t), (char *) &t); 174 } 175#endif 176 177 DPRINTF(sc, ATH_DEBUG_TDMA_TIMER, 178 "%s: nexttbtt=%u (0x%08x), nexttbtt tsf=%lld (0x%08llx)\n", 179 __func__, 180 bt.bt_nexttbtt, 181 bt.bt_nexttbtt, 182 (long long) ( ((u_int64_t) (bt.bt_nexttbtt)) << 10), 183 (long long) ( ((u_int64_t) (bt.bt_nexttbtt)) << 10)); 184 ath_hal_beaconsettimers(ah, &bt); 185} 186 187/* 188 * Calculate the beacon interval. This is periodic in the 189 * superframe for the bss. We assume each station is configured 190 * identically wrt transmit rate so the guard time we calculate 191 * above will be the same on all stations. Note we need to 192 * factor in the xmit time because the hardware will schedule 193 * a frame for transmit if the start of the frame is within 194 * the burst time. When we get hardware that properly kills 195 * frames in the PCU we can reduce/eliminate the guard time. 196 * 197 * Roundup to 1024 is so we have 1 TU buffer in the guard time 198 * to deal with the granularity of the nexttbtt timer. 11n MAC's 199 * with 1us timer granularity should allow us to reduce/eliminate 200 * this. 201 */ 202static void 203ath_tdma_bintvalsetup(struct ath_softc *sc, 204 const struct ieee80211_tdma_state *tdma) 205{ 206 /* copy from vap state (XXX check all vaps have same value?) */ 207 sc->sc_tdmaslotlen = tdma->tdma_slotlen; 208 209 sc->sc_tdmabintval = roundup((sc->sc_tdmaslotlen+sc->sc_tdmaguard) * 210 tdma->tdma_slotcnt, 1024); 211 sc->sc_tdmabintval >>= 10; /* TSF -> TU */ 212 if (sc->sc_tdmabintval & 1) 213 sc->sc_tdmabintval++; 214 215 if (tdma->tdma_slot == 0) { 216 /* 217 * Only slot 0 beacons; other slots respond. 218 */ 219 sc->sc_imask |= HAL_INT_SWBA; 220 sc->sc_tdmaswba = 0; /* beacon immediately */ 221 } else { 222 /* XXX all vaps must be slot 0 or slot !0 */ 223 sc->sc_imask &= ~HAL_INT_SWBA; 224 } 225} 226 227/* 228 * Max 802.11 overhead. This assumes no 4-address frames and 229 * the encapsulation done by ieee80211_encap (llc). We also 230 * include potential crypto overhead. 231 */ 232#define IEEE80211_MAXOVERHEAD \ 233 (sizeof(struct ieee80211_qosframe) \ 234 + sizeof(struct llc) \ 235 + IEEE80211_ADDR_LEN \ 236 + IEEE80211_WEP_IVLEN \ 237 + IEEE80211_WEP_KIDLEN \ 238 + IEEE80211_WEP_CRCLEN \ 239 + IEEE80211_WEP_MICLEN \ 240 + IEEE80211_CRC_LEN) 241 242/* 243 * Setup initially for tdma operation. Start the beacon 244 * timers and enable SWBA if we are slot 0. Otherwise 245 * we wait for slot 0 to arrive so we can sync up before 246 * starting to transmit. 247 */ 248void 249ath_tdma_config(struct ath_softc *sc, struct ieee80211vap *vap) 250{ 251 struct ath_hal *ah = sc->sc_ah; 252 struct ifnet *ifp = sc->sc_ifp; 253 struct ieee80211com *ic = ifp->if_l2com; 254 const struct ieee80211_txparam *tp; 255 const struct ieee80211_tdma_state *tdma = NULL; 256 int rix; 257 258 if (vap == NULL) { 259 vap = TAILQ_FIRST(&ic->ic_vaps); /* XXX */ 260 if (vap == NULL) { 261 if_printf(ifp, "%s: no vaps?\n", __func__); 262 return; 263 } 264 } 265 /* XXX should take a locked ref to iv_bss */ 266 tp = vap->iv_bss->ni_txparms; 267 /* 268 * Calculate the guard time for each slot. This is the 269 * time to send a maximal-size frame according to the 270 * fixed/lowest transmit rate. Note that the interface 271 * mtu does not include the 802.11 overhead so we must 272 * tack that on (ath_hal_computetxtime includes the 273 * preamble and plcp in it's calculation). 274 */ 275 tdma = vap->iv_tdma; 276 if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) 277 rix = ath_tx_findrix(sc, tp->ucastrate); 278 else 279 rix = ath_tx_findrix(sc, tp->mcastrate); 280 /* XXX short preamble assumed */ 281 sc->sc_tdmaguard = ath_hal_computetxtime(ah, sc->sc_currates, 282 ifp->if_mtu + IEEE80211_MAXOVERHEAD, rix, AH_TRUE); 283 284 ath_hal_intrset(ah, 0); 285 286 ath_beaconq_config(sc); /* setup h/w beacon q */ 287 if (sc->sc_setcca) 288 ath_hal_setcca(ah, AH_FALSE); /* disable CCA */ 289 ath_tdma_bintvalsetup(sc, tdma); /* calculate beacon interval */ 290 ath_tdma_settimers(sc, sc->sc_tdmabintval, 291 sc->sc_tdmabintval | HAL_BEACON_RESET_TSF); 292 sc->sc_syncbeacon = 0; 293 294 sc->sc_avgtsfdeltap = TDMA_DUMMY_MARKER; 295 sc->sc_avgtsfdeltam = TDMA_DUMMY_MARKER; 296 297 ath_hal_intrset(ah, sc->sc_imask); 298 299 DPRINTF(sc, ATH_DEBUG_TDMA, "%s: slot %u len %uus cnt %u " 300 "bsched %u guard %uus bintval %u TU dba prep %u\n", __func__, 301 tdma->tdma_slot, tdma->tdma_slotlen, tdma->tdma_slotcnt, 302 tdma->tdma_bintval, sc->sc_tdmaguard, sc->sc_tdmabintval, 303 sc->sc_tdmadbaprep); 304 305#ifdef ATH_DEBUG_ALQ 306 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_TDMA_TIMER_CONFIG)) { 307 struct if_ath_alq_tdma_timer_config t; 308 309 t.tdma_slot = htobe32(tdma->tdma_slot); 310 t.tdma_slotlen = htobe32(tdma->tdma_slotlen); 311 t.tdma_slotcnt = htobe32(tdma->tdma_slotcnt); 312 t.tdma_bintval = htobe32(tdma->tdma_bintval); 313 t.tdma_guard = htobe32(sc->sc_tdmaguard); 314 t.tdma_scbintval = htobe32(sc->sc_tdmabintval); 315 t.tdma_dbaprep = htobe32(sc->sc_tdmadbaprep); 316 317 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_TDMA_TIMER_CONFIG, 318 sizeof(t), (char *) &t); 319 } 320#endif /* ATH_DEBUG_ALQ */ 321} 322 323/* 324 * Update tdma operation. Called from the 802.11 layer 325 * when a beacon is received from the TDMA station operating 326 * in the slot immediately preceding us in the bss. Use 327 * the rx timestamp for the beacon frame to update our 328 * beacon timers so we follow their schedule. Note that 329 * by using the rx timestamp we implicitly include the 330 * propagation delay in our schedule. 331 * 332 * XXX TODO: since the changes for the AR5416 and later chips 333 * involved changing the TSF/TU calculations, we need to make 334 * sure that various calculations wrap consistently. 335 * 336 * A lot of the problems stemmed from the calculations wrapping 337 * at 65,535 TU. Since a lot of the math is still being done in 338 * TU, please audit it to ensure that when the TU values programmed 339 * into the timers wrap at (2^31)-1 TSF, all the various terms 340 * wrap consistently. 341 */ 342void 343ath_tdma_update(struct ieee80211_node *ni, 344 const struct ieee80211_tdma_param *tdma, int changed) 345{ 346#define TSF_TO_TU(_h,_l) \ 347 ((((u_int32_t)(_h)) << 22) | (((u_int32_t)(_l)) >> 10)) 348#define TU_TO_TSF(_tu) (((u_int64_t)(_tu)) << 10) 349 struct ieee80211vap *vap = ni->ni_vap; 350 struct ieee80211com *ic = ni->ni_ic; 351 struct ath_softc *sc = ic->ic_ifp->if_softc; 352 struct ath_hal *ah = sc->sc_ah; 353 const HAL_RATE_TABLE *rt = sc->sc_currates; 354 u_int64_t tsf, rstamp, nextslot, nexttbtt, nexttbtt_full; 355 u_int32_t txtime, nextslottu; 356 int32_t tudelta, tsfdelta; 357 const struct ath_rx_status *rs; 358 int rix; 359 360 sc->sc_stats.ast_tdma_update++; 361 362 /* 363 * Check for and adopt configuration changes. 364 */ 365 if (changed != 0) { 366 const struct ieee80211_tdma_state *ts = vap->iv_tdma; 367 368 ath_tdma_bintvalsetup(sc, ts); 369 if (changed & TDMA_UPDATE_SLOTLEN) 370 ath_wme_update(ic); 371 372 DPRINTF(sc, ATH_DEBUG_TDMA, 373 "%s: adopt slot %u slotcnt %u slotlen %u us " 374 "bintval %u TU\n", __func__, 375 ts->tdma_slot, ts->tdma_slotcnt, ts->tdma_slotlen, 376 sc->sc_tdmabintval); 377 378 /* XXX right? */ 379 ath_hal_intrset(ah, sc->sc_imask); 380 /* NB: beacon timers programmed below */ 381 } 382 383 /* extend rx timestamp to 64 bits */ 384 rs = sc->sc_lastrs; 385 tsf = ath_hal_gettsf64(ah); 386 rstamp = ath_extend_tsf(sc, rs->rs_tstamp, tsf); 387 /* 388 * The rx timestamp is set by the hardware on completing 389 * reception (at the point where the rx descriptor is DMA'd 390 * to the host). To find the start of our next slot we 391 * must adjust this time by the time required to send 392 * the packet just received. 393 */ 394 rix = rt->rateCodeToIndex[rs->rs_rate]; 395 txtime = ath_hal_computetxtime(ah, rt, rs->rs_datalen, rix, 396 rt->info[rix].shortPreamble); 397 /* NB: << 9 is to cvt to TU and /2 */ 398 nextslot = (rstamp - txtime) + (sc->sc_tdmabintval << 9); 399 400 /* 401 * For 802.11n chips: nextslottu needs to be the full TSF space, 402 * not just 0..65535 TU. 403 */ 404 nextslottu = TSF_TO_TU(nextslot>>32, nextslot); 405 DPRINTF(sc, ATH_DEBUG_TDMA_TIMER, 406 "rs->rstamp %llu rstamp %llu tsf %llu txtime %d, nextslot %llu, nextslottu %d, nextslottume %d\n", 407 (unsigned long long) rs->rs_tstamp, rstamp, tsf, txtime, nextslot, nextslottu, TSF_TO_TU(nextslot >> 32, nextslot)); 408 DPRINTF(sc, ATH_DEBUG_TDMA, 409 " beacon tstamp: %llu (0x%016llx)\n", 410 le64toh(ni->ni_tstamp.tsf), 411 le64toh(ni->ni_tstamp.tsf)); 412 413#ifdef ATH_DEBUG_ALQ 414 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_TDMA_BEACON_STATE)) { 415 struct if_ath_alq_tdma_beacon_state t; 416 t.rx_tsf = htobe64(rstamp); 417 t.beacon_tsf = htobe64(le64toh(ni->ni_tstamp.tsf)); 418 t.tsf64 = htobe64(tsf); 419 t.nextslot_tsf = htobe64(nextslot); 420 t.nextslot_tu = htobe32(nextslottu); 421 t.txtime = htobe32(txtime); 422 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_TDMA_BEACON_STATE, 423 sizeof(t), (char *) &t); 424 } 425#endif 426 427 /* 428 * Retrieve the hardware NextTBTT in usecs 429 * and calculate the difference between what the 430 * other station thinks and what we have programmed. This 431 * lets us figure how to adjust our timers to match. The 432 * adjustments are done by pulling the TSF forward and possibly 433 * rewriting the beacon timers. 434 */ 435 /* 436 * The logic here assumes the nexttbtt counter is in TSF 437 * but the prr-11n NICs are in TU. The HAL shifts them 438 * to TSF but there's two important differences: 439 * 440 * + The TU->TSF values have 0's for the low 9 bits, and 441 * + The counter wraps at TU_TO_TSF(HAL_BEACON_PERIOD + 1) for 442 * the pre-11n NICs, but not for the 11n NICs. 443 * 444 * So for now, just make sure the nexttbtt value we get 445 * matches the second issue or once nexttbtt exceeds this 446 * value, tsfdelta ends up becoming very negative and all 447 * of the adjustments get very messed up. 448 */ 449 450 /* 451 * We need to track the full nexttbtt rather than having it 452 * truncated at HAL_BEACON_PERIOD, as programming the 453 * nexttbtt (and related) registers for the 11n chips is 454 * actually going to take the full 32 bit space, rather than 455 * just 0..65535 TU. 456 */ 457 nexttbtt_full = ath_hal_getnexttbtt(ah); 458 nexttbtt = nexttbtt_full % (TU_TO_TSF(HAL_BEACON_PERIOD + 1)); 459 tsfdelta = (int32_t)((nextslot % TU_TO_TSF(HAL_BEACON_PERIOD + 1)) - nexttbtt); 460 461 DPRINTF(sc, ATH_DEBUG_TDMA_TIMER, 462 "nexttbtt %llu (0x%08llx) tsfdelta %d avg +%d/-%d\n", 463 nexttbtt, 464 (long long) nexttbtt, 465 tsfdelta, 466 TDMA_AVG(sc->sc_avgtsfdeltap), TDMA_AVG(sc->sc_avgtsfdeltam)); 467 468#ifdef ATH_DEBUG_ALQ 469 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_TDMA_SLOT_CALC)) { 470 struct if_ath_alq_tdma_slot_calc t; 471 472 t.nexttbtt = htobe64(nexttbtt_full); 473 t.next_slot = htobe64(nextslot); 474 t.tsfdelta = htobe32(tsfdelta); 475 t.avg_plus = htobe32(TDMA_AVG(sc->sc_avgtsfdeltap)); 476 t.avg_minus = htobe32(TDMA_AVG(sc->sc_avgtsfdeltam)); 477 478 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_TDMA_SLOT_CALC, 479 sizeof(t), (char *) &t); 480 } 481#endif 482 483 if (tsfdelta < 0) { 484 TDMA_SAMPLE(sc->sc_avgtsfdeltap, 0); 485 TDMA_SAMPLE(sc->sc_avgtsfdeltam, -tsfdelta); 486 tsfdelta = -tsfdelta % 1024; 487 nextslottu++; 488 } else if (tsfdelta > 0) { 489 TDMA_SAMPLE(sc->sc_avgtsfdeltap, tsfdelta); 490 TDMA_SAMPLE(sc->sc_avgtsfdeltam, 0); 491 tsfdelta = 1024 - (tsfdelta % 1024); 492 nextslottu++; 493 } else { 494 TDMA_SAMPLE(sc->sc_avgtsfdeltap, 0); 495 TDMA_SAMPLE(sc->sc_avgtsfdeltam, 0); 496 } 497 tudelta = nextslottu - TSF_TO_TU(nexttbtt_full >> 32, nexttbtt_full); 498 499 /* 500 * Copy sender's timetstamp into tdma ie so they can 501 * calculate roundtrip time. We submit a beacon frame 502 * below after any timer adjustment. The frame goes out 503 * at the next TBTT so the sender can calculate the 504 * roundtrip by inspecting the tdma ie in our beacon frame. 505 * 506 * NB: This tstamp is subtlely preserved when 507 * IEEE80211_BEACON_TDMA is marked (e.g. when the 508 * slot position changes) because ieee80211_add_tdma 509 * skips over the data. 510 */ 511 memcpy(ATH_VAP(vap)->av_boff.bo_tdma + 512 __offsetof(struct ieee80211_tdma_param, tdma_tstamp), 513 &ni->ni_tstamp.data, 8); 514#if 0 515 DPRINTF(sc, ATH_DEBUG_TDMA_TIMER, 516 "tsf %llu nextslot %llu (%d, %d) nextslottu %u nexttbtt %llu (%d)\n", 517 (unsigned long long) tsf, (unsigned long long) nextslot, 518 (int)(nextslot - tsf), tsfdelta, nextslottu, nexttbtt, tudelta); 519#endif 520 /* 521 * Adjust the beacon timers only when pulling them forward 522 * or when going back by less than the beacon interval. 523 * Negative jumps larger than the beacon interval seem to 524 * cause the timers to stop and generally cause instability. 525 * This basically filters out jumps due to missed beacons. 526 */ 527 if (tudelta != 0 && (tudelta > 0 || -tudelta < sc->sc_tdmabintval)) { 528 DPRINTF(sc, ATH_DEBUG_TDMA_TIMER, 529 "%s: calling ath_tdma_settimers; nextslottu=%d, bintval=%d\n", 530 __func__, 531 nextslottu, 532 sc->sc_tdmabintval); 533 ath_tdma_settimers(sc, nextslottu, sc->sc_tdmabintval); 534 sc->sc_stats.ast_tdma_timers++; 535 } 536 if (tsfdelta > 0) { 537 uint64_t tsf; 538 539 /* XXX should just teach ath_hal_adjusttsf() to do this */ 540 tsf = ath_hal_gettsf64(ah); 541 ath_hal_settsf64(ah, tsf + tsfdelta); 542 DPRINTF(sc, ATH_DEBUG_TDMA_TIMER, 543 "%s: calling ath_hal_adjusttsf: TSF=%llu, tsfdelta=%d\n", 544 __func__, 545 tsf, 546 tsfdelta); 547 548#ifdef ATH_DEBUG_ALQ 549 if (if_ath_alq_checkdebug(&sc->sc_alq, 550 ATH_ALQ_TDMA_TSF_ADJUST)) { 551 struct if_ath_alq_tdma_tsf_adjust t; 552 553 t.tsfdelta = htobe32(tsfdelta); 554 t.tsf64_old = htobe64(tsf); 555 t.tsf64_new = htobe64(tsf + tsfdelta); 556 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_TDMA_TSF_ADJUST, 557 sizeof(t), (char *) &t); 558 } 559#endif /* ATH_DEBUG_ALQ */ 560 sc->sc_stats.ast_tdma_tsf++; 561 } 562 ath_tdma_beacon_send(sc, vap); /* prepare response */ 563#undef TU_TO_TSF 564#undef TSF_TO_TU 565} 566 567/* 568 * Transmit a beacon frame at SWBA. Dynamic updates 569 * to the frame contents are done as needed. 570 */ 571void 572ath_tdma_beacon_send(struct ath_softc *sc, struct ieee80211vap *vap) 573{ 574 struct ath_hal *ah = sc->sc_ah; 575 struct ath_buf *bf; 576 int otherant; 577 578 /* 579 * Check if the previous beacon has gone out. If 580 * not don't try to post another, skip this period 581 * and wait for the next. Missed beacons indicate 582 * a problem and should not occur. If we miss too 583 * many consecutive beacons reset the device. 584 */ 585 if (ath_hal_numtxpending(ah, sc->sc_bhalq) != 0) { 586 sc->sc_bmisscount++; 587 DPRINTF(sc, ATH_DEBUG_BEACON, 588 "%s: missed %u consecutive beacons\n", 589 __func__, sc->sc_bmisscount); 590 if (sc->sc_bmisscount >= ath_bstuck_threshold) 591 taskqueue_enqueue(sc->sc_tq, &sc->sc_bstucktask); 592 return; 593 } 594 if (sc->sc_bmisscount != 0) { 595 DPRINTF(sc, ATH_DEBUG_BEACON, 596 "%s: resume beacon xmit after %u misses\n", 597 __func__, sc->sc_bmisscount); 598 sc->sc_bmisscount = 0; 599 } 600 601 /* 602 * Check recent per-antenna transmit statistics and flip 603 * the default antenna if noticeably more frames went out 604 * on the non-default antenna. 605 * XXX assumes 2 anntenae 606 */ 607 if (!sc->sc_diversity) { 608 otherant = sc->sc_defant & 1 ? 2 : 1; 609 if (sc->sc_ant_tx[otherant] > sc->sc_ant_tx[sc->sc_defant] + 2) 610 ath_setdefantenna(sc, otherant); 611 sc->sc_ant_tx[1] = sc->sc_ant_tx[2] = 0; 612 } 613 614 bf = ath_beacon_generate(sc, vap); 615 if (bf != NULL) { 616 /* 617 * Stop any current dma and put the new frame on the queue. 618 * This should never fail since we check above that no frames 619 * are still pending on the queue. 620 */ 621 if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) { 622 DPRINTF(sc, ATH_DEBUG_ANY, 623 "%s: beacon queue %u did not stop?\n", 624 __func__, sc->sc_bhalq); 625 /* NB: the HAL still stops DMA, so proceed */ 626 } 627 ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr); 628 ath_hal_txstart(ah, sc->sc_bhalq); 629 630 sc->sc_stats.ast_be_xmit++; /* XXX per-vap? */ 631 632 /* 633 * Record local TSF for our last send for use 634 * in arbitrating slot collisions. 635 */ 636 /* XXX should take a locked ref to iv_bss */ 637 vap->iv_bss->ni_tstamp.tsf = ath_hal_gettsf64(ah); 638 } 639} 640#endif /* IEEE80211_SUPPORT_TDMA */ 641