ar9287_reset.c revision 222301
1/* 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar9002/ar9287_reset.c 222301 2011-05-26 09:15:33Z adrian $ 18 */ 19 20#include "opt_ah.h" 21 22#include "ah.h" 23#include "ah_internal.h" 24#include "ah_devid.h" 25 26#include "ah_eeprom_v14.h" 27#include "ah_eeprom_9287.h" 28 29#include "ar5416/ar5416.h" 30#include "ar5416/ar5416reg.h" 31#include "ar5416/ar5416phy.h" 32 33#include "ar9002/ar9287phy.h" 34#include "ar9002/ar9287an.h" 35 36#include "ar9002/ar9287_reset.h" 37 38HAL_BOOL 39ar9287SetTransmitPower(struct ath_hal *ah, 40 const struct ieee80211_channel *chan, uint16_t *rfXpdGain) 41{ 42 /* XXX TODO */ 43 return AH_TRUE; 44} 45 46/* 47 * Read EEPROM header info and program the device for correct operation 48 * given the channel value. 49 */ 50HAL_BOOL 51ar9287SetBoardValues(struct ath_hal *ah, const struct ieee80211_channel *chan) 52{ 53 const HAL_EEPROM_9287 *ee = AH_PRIVATE(ah)->ah_eeprom; 54 const struct ar9287_eeprom *eep = &ee->ee_base; 55 const struct modal_eep_ar9287_header *pModal = &eep->modalHeader; 56 uint16_t antWrites[AR9287_ANT_16S]; 57 uint32_t regChainOffset, regval; 58 uint8_t txRxAttenLocal; 59 int i, j, offset_num; 60 61 pModal = &eep->modalHeader; 62 63 antWrites[0] = (uint16_t)((pModal->antCtrlCommon >> 28) & 0xF); 64 antWrites[1] = (uint16_t)((pModal->antCtrlCommon >> 24) & 0xF); 65 antWrites[2] = (uint16_t)((pModal->antCtrlCommon >> 20) & 0xF); 66 antWrites[3] = (uint16_t)((pModal->antCtrlCommon >> 16) & 0xF); 67 antWrites[4] = (uint16_t)((pModal->antCtrlCommon >> 12) & 0xF); 68 antWrites[5] = (uint16_t)((pModal->antCtrlCommon >> 8) & 0xF); 69 antWrites[6] = (uint16_t)((pModal->antCtrlCommon >> 4) & 0xF); 70 antWrites[7] = (uint16_t)(pModal->antCtrlCommon & 0xF); 71 72 offset_num = 8; 73 74 for (i = 0, j = offset_num; i < AR9287_MAX_CHAINS; i++) { 75 antWrites[j++] = (uint16_t)((pModal->antCtrlChain[i] >> 28) & 0xf); 76 antWrites[j++] = (uint16_t)((pModal->antCtrlChain[i] >> 10) & 0x3); 77 antWrites[j++] = (uint16_t)((pModal->antCtrlChain[i] >> 8) & 0x3); 78 antWrites[j++] = 0; 79 antWrites[j++] = (uint16_t)((pModal->antCtrlChain[i] >> 6) & 0x3); 80 antWrites[j++] = (uint16_t)((pModal->antCtrlChain[i] >> 4) & 0x3); 81 antWrites[j++] = (uint16_t)((pModal->antCtrlChain[i] >> 2) & 0x3); 82 antWrites[j++] = (uint16_t)(pModal->antCtrlChain[i] & 0x3); 83 } 84 85 OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon); 86 87 for (i = 0; i < AR9287_MAX_CHAINS; i++) { 88 regChainOffset = i * 0x1000; 89 90 OS_REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset, 91 pModal->antCtrlChain[i]); 92 93 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0) + regChainOffset, 94 (OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0) + regChainOffset) 95 & ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF | 96 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) | 97 SM(pModal->iqCalICh[i], 98 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) | 99 SM(pModal->iqCalQCh[i], 100 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF)); 101 102 txRxAttenLocal = pModal->txRxAttenCh[i]; 103 104 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, 105 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, 106 pModal->bswMargin[i]); 107 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, 108 AR_PHY_GAIN_2GHZ_XATTEN1_DB, 109 pModal->bswAtten[i]); 110 OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset, 111 AR9280_PHY_RXGAIN_TXRX_ATTEN, 112 txRxAttenLocal); 113 OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset, 114 AR9280_PHY_RXGAIN_TXRX_MARGIN, 115 pModal->rxTxMarginCh[i]); 116 } 117 118 119 if (IEEE80211_IS_CHAN_HT40(chan)) 120 OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, 121 AR_PHY_SETTLING_SWITCH, pModal->swSettleHt40); 122 else 123 OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, 124 AR_PHY_SETTLING_SWITCH, pModal->switchSettling); 125 126 OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, 127 AR_PHY_DESIRED_SZ_ADC, pModal->adcDesiredSize); 128 129 OS_REG_WRITE(ah, AR_PHY_RF_CTL4, 130 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF) 131 | SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF) 132 | SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON) 133 | SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON)); 134 135 OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, 136 AR_PHY_TX_END_TO_A2_RX_ON, pModal->txEndToRxOn); 137 138 OS_REG_RMW_FIELD(ah, AR_PHY_CCA, 139 AR9280_PHY_CCA_THRESH62, pModal->thresh62); 140 OS_REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, 141 AR_PHY_EXT_CCA0_THRESH62, pModal->thresh62); 142 143 regval = OS_REG_READ(ah, AR9287_AN_RF2G3_CH0); 144 regval &= ~(AR9287_AN_RF2G3_DB1 | 145 AR9287_AN_RF2G3_DB2 | 146 AR9287_AN_RF2G3_OB_CCK | 147 AR9287_AN_RF2G3_OB_PSK | 148 AR9287_AN_RF2G3_OB_QAM | 149 AR9287_AN_RF2G3_OB_PAL_OFF); 150 regval |= (SM(pModal->db1, AR9287_AN_RF2G3_DB1) | 151 SM(pModal->db2, AR9287_AN_RF2G3_DB2) | 152 SM(pModal->ob_cck, AR9287_AN_RF2G3_OB_CCK) | 153 SM(pModal->ob_psk, AR9287_AN_RF2G3_OB_PSK) | 154 SM(pModal->ob_qam, AR9287_AN_RF2G3_OB_QAM) | 155 SM(pModal->ob_pal_off, AR9287_AN_RF2G3_OB_PAL_OFF)); 156 157 OS_REG_WRITE(ah, AR9287_AN_RF2G3_CH0, regval); 158 OS_DELAY(100); /* analog write */ 159 160 regval = OS_REG_READ(ah, AR9287_AN_RF2G3_CH1); 161 regval &= ~(AR9287_AN_RF2G3_DB1 | 162 AR9287_AN_RF2G3_DB2 | 163 AR9287_AN_RF2G3_OB_CCK | 164 AR9287_AN_RF2G3_OB_PSK | 165 AR9287_AN_RF2G3_OB_QAM | 166 AR9287_AN_RF2G3_OB_PAL_OFF); 167 regval |= (SM(pModal->db1, AR9287_AN_RF2G3_DB1) | 168 SM(pModal->db2, AR9287_AN_RF2G3_DB2) | 169 SM(pModal->ob_cck, AR9287_AN_RF2G3_OB_CCK) | 170 SM(pModal->ob_psk, AR9287_AN_RF2G3_OB_PSK) | 171 SM(pModal->ob_qam, AR9287_AN_RF2G3_OB_QAM) | 172 SM(pModal->ob_pal_off, AR9287_AN_RF2G3_OB_PAL_OFF)); 173 174 OS_REG_WRITE(ah, AR9287_AN_RF2G3_CH1, regval); 175 OS_DELAY(100); /* analog write */ 176 177 OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, 178 AR_PHY_TX_FRAME_TO_DATA_START, pModal->txFrameToDataStart); 179 OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, 180 AR_PHY_TX_FRAME_TO_PA_ON, pModal->txFrameToPaOn); 181 182 OS_A_REG_RMW_FIELD(ah, AR9287_AN_TOP2, 183 AR9287_AN_TOP2_XPABIAS_LVL, pModal->xpaBiasLvl); 184 185 return AH_TRUE; 186} 187