ar9285_reset.c revision 249580
1/* 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar9002/ar9285_reset.c 249580 2013-04-17 07:31:53Z adrian $ 18 */ 19 20/* 21 * This is almost the same as ar5416_reset.c but uses the v4k EEPROM and 22 * supports only 2Ghz operation. 23 */ 24 25#include "opt_ah.h" 26 27#include "ah.h" 28#include "ah_internal.h" 29#include "ah_devid.h" 30 31#include "ah_eeprom_v14.h" 32#include "ah_eeprom_v4k.h" 33 34#include "ar9002/ar9285.h" 35#include "ar5416/ar5416.h" 36#include "ar5416/ar5416reg.h" 37#include "ar5416/ar5416phy.h" 38#include "ar9002/ar9002phy.h" 39#include "ar9002/ar9285phy.h" 40#include "ar9002/ar9285an.h" 41 42/* Eeprom versioning macros. Returns true if the version is equal or newer than the ver specified */ 43#define EEP_MINOR(_ah) \ 44 (AH_PRIVATE(_ah)->ah_eeversion & AR5416_EEP_VER_MINOR_MASK) 45#define IS_EEP_MINOR_V2(_ah) (EEP_MINOR(_ah) >= AR5416_EEP_MINOR_VER_2) 46#define IS_EEP_MINOR_V3(_ah) (EEP_MINOR(_ah) >= AR5416_EEP_MINOR_VER_3) 47 48/* Additional Time delay to wait after activiting the Base band */ 49#define BASE_ACTIVATE_DELAY 100 /* 100 usec */ 50#define PLL_SETTLE_DELAY 300 /* 300 usec */ 51#define RTC_PLL_SETTLE_DELAY 1000 /* 1 ms */ 52 53static HAL_BOOL ar9285SetPowerPerRateTable(struct ath_hal *ah, 54 struct ar5416eeprom_4k *pEepData, 55 const struct ieee80211_channel *chan, int16_t *ratesArray, 56 uint16_t cfgCtl, uint16_t AntennaReduction, 57 uint16_t twiceMaxRegulatoryPower, 58 uint16_t powerLimit); 59static HAL_BOOL ar9285SetPowerCalTable(struct ath_hal *ah, 60 struct ar5416eeprom_4k *pEepData, 61 const struct ieee80211_channel *chan, 62 int16_t *pTxPowerIndexOffset); 63static void ar9285GetGainBoundariesAndPdadcs(struct ath_hal *ah, 64 const struct ieee80211_channel *chan, CAL_DATA_PER_FREQ_4K *pRawDataSet, 65 uint8_t * bChans, uint16_t availPiers, 66 uint16_t tPdGainOverlap, int16_t *pMinCalPower, 67 uint16_t * pPdGainBoundaries, uint8_t * pPDADCValues, 68 uint16_t numXpdGains); 69 70HAL_BOOL 71ar9285SetTransmitPower(struct ath_hal *ah, 72 const struct ieee80211_channel *chan, uint16_t *rfXpdGain) 73{ 74#define POW_SM(_r, _s) (((_r) & 0x3f) << (_s)) 75#define N(a) (sizeof (a) / sizeof (a[0])) 76 77 MODAL_EEP4K_HEADER *pModal; 78 struct ath_hal_5212 *ahp = AH5212(ah); 79 int16_t txPowerIndexOffset = 0; 80 int i; 81 82 uint16_t cfgCtl; 83 uint16_t powerLimit; 84 uint16_t twiceAntennaReduction; 85 uint16_t twiceMaxRegulatoryPower; 86 int16_t maxPower; 87 HAL_EEPROM_v4k *ee = AH_PRIVATE(ah)->ah_eeprom; 88 struct ar5416eeprom_4k *pEepData = &ee->ee_base; 89 90 HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER14_1); 91 92 AH5416(ah)->ah_ht40PowerIncForPdadc = 2; 93 94 /* Setup info for the actual eeprom */ 95 OS_MEMZERO(AH5416(ah)->ah_ratesArray, sizeof(AH5416(ah)->ah_ratesArray)); 96 cfgCtl = ath_hal_getctl(ah, chan); 97 powerLimit = chan->ic_maxregpower * 2; 98 twiceAntennaReduction = chan->ic_maxantgain; 99 twiceMaxRegulatoryPower = AH_MIN(MAX_RATE_POWER, AH_PRIVATE(ah)->ah_powerLimit); 100 pModal = &pEepData->modalHeader; 101 HALDEBUG(ah, HAL_DEBUG_RESET, "%s Channel=%u CfgCtl=%u\n", 102 __func__,chan->ic_freq, cfgCtl ); 103 104 if (IS_EEP_MINOR_V2(ah)) { 105 AH5416(ah)->ah_ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc; 106 } 107 108 if (!ar9285SetPowerPerRateTable(ah, pEepData, chan, 109 &AH5416(ah)->ah_ratesArray[0],cfgCtl, 110 twiceAntennaReduction, 111 twiceMaxRegulatoryPower, powerLimit)) { 112 HALDEBUG(ah, HAL_DEBUG_ANY, 113 "%s: unable to set tx power per rate table\n", __func__); 114 return AH_FALSE; 115 } 116 117 if (!ar9285SetPowerCalTable(ah, pEepData, chan, &txPowerIndexOffset)) { 118 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unable to set power table\n", 119 __func__); 120 return AH_FALSE; 121 } 122 123 maxPower = AH_MAX(AH5416(ah)->ah_ratesArray[rate6mb], 124 AH5416(ah)->ah_ratesArray[rateHt20_0]); 125 maxPower = AH_MAX(maxPower, AH5416(ah)->ah_ratesArray[rate1l]); 126 127 if (IEEE80211_IS_CHAN_HT40(chan)) { 128 maxPower = AH_MAX(maxPower, AH5416(ah)->ah_ratesArray[rateHt40_0]); 129 } 130 131 ahp->ah_tx6PowerInHalfDbm = maxPower; 132 AH_PRIVATE(ah)->ah_maxPowerLevel = maxPower; 133 ahp->ah_txPowerIndexOffset = txPowerIndexOffset; 134 135 /* 136 * txPowerIndexOffset is set by the SetPowerTable() call - 137 * adjust the rate table (0 offset if rates EEPROM not loaded) 138 */ 139 for (i = 0; i < N(AH5416(ah)->ah_ratesArray); i++) { 140 AH5416(ah)->ah_ratesArray[i] = (int16_t)(txPowerIndexOffset + AH5416(ah)->ah_ratesArray[i]); 141 /* -5 dBm offset for Merlin and later; this includes Kite */ 142 AH5416(ah)->ah_ratesArray[i] -= AR5416_PWR_TABLE_OFFSET_DB * 2; 143 if (AH5416(ah)->ah_ratesArray[i] > AR5416_MAX_RATE_POWER) 144 AH5416(ah)->ah_ratesArray[i] = AR5416_MAX_RATE_POWER; 145 if (AH5416(ah)->ah_ratesArray[i] < 0) 146 AH5416(ah)->ah_ratesArray[i] = 0; 147 } 148 149#ifdef AH_EEPROM_DUMP 150 ar5416PrintPowerPerRate(ah, AH5416(ah)->ah_ratesArray); 151#endif 152 153 /* 154 * Adjust the HT40 power to meet the correct target TX power 155 * for 40MHz mode, based on TX power curves that are established 156 * for 20MHz mode. 157 * 158 * XXX handle overflow/too high power level? 159 */ 160 if (IEEE80211_IS_CHAN_HT40(chan)) { 161 AH5416(ah)->ah_ratesArray[rateHt40_0] += 162 AH5416(ah)->ah_ht40PowerIncForPdadc; 163 AH5416(ah)->ah_ratesArray[rateHt40_1] += 164 AH5416(ah)->ah_ht40PowerIncForPdadc; 165 AH5416(ah)->ah_ratesArray[rateHt40_2] += 166 AH5416(ah)->ah_ht40PowerIncForPdadc; 167 AH5416(ah)->ah_ratesArray[rateHt40_3] += 168 AH5416(ah)->ah_ht40PowerIncForPdadc; 169 AH5416(ah)->ah_ratesArray[rateHt40_4] += 170 AH5416(ah)->ah_ht40PowerIncForPdadc; 171 AH5416(ah)->ah_ratesArray[rateHt40_5] += 172 AH5416(ah)->ah_ht40PowerIncForPdadc; 173 AH5416(ah)->ah_ratesArray[rateHt40_6] += 174 AH5416(ah)->ah_ht40PowerIncForPdadc; 175 AH5416(ah)->ah_ratesArray[rateHt40_7] += 176 AH5416(ah)->ah_ht40PowerIncForPdadc; 177 } 178 179 /* Write the TX power rate registers */ 180 ar5416WriteTxPowerRateRegisters(ah, chan, AH5416(ah)->ah_ratesArray); 181 182 return AH_TRUE; 183#undef POW_SM 184#undef N 185} 186 187static void 188ar9285SetBoardGain(struct ath_hal *ah, const MODAL_EEP4K_HEADER *pModal, 189 const struct ar5416eeprom_4k *eep, uint8_t txRxAttenLocal) 190{ 191 OS_REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0, 192 pModal->antCtrlChain[0]); 193 194 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0), 195 (OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0)) & 196 ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF | 197 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) | 198 SM(pModal->iqCalICh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) | 199 SM(pModal->iqCalQCh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF)); 200 201 if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= 202 AR5416_EEP_MINOR_VER_3) { 203 txRxAttenLocal = pModal->txRxAttenCh[0]; 204 205 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, 206 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, pModal->bswMargin[0]); 207 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, 208 AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]); 209 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, 210 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN, pModal->xatten2Margin[0]); 211 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, 212 AR_PHY_GAIN_2GHZ_XATTEN2_DB, pModal->xatten2Db[0]); 213 214 /* Set the block 1 value to block 0 value */ 215 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000, 216 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, 217 pModal->bswMargin[0]); 218 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000, 219 AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]); 220 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000, 221 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN, 222 pModal->xatten2Margin[0]); 223 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000, 224 AR_PHY_GAIN_2GHZ_XATTEN2_DB, pModal->xatten2Db[0]); 225 } 226 227 OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN, 228 AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal); 229 OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN, 230 AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]); 231 232 OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000, 233 AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal); 234 OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000, 235 AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]); 236} 237 238/* 239 * Read EEPROM header info and program the device for correct operation 240 * given the channel value. 241 */ 242HAL_BOOL 243ar9285SetBoardValues(struct ath_hal *ah, const struct ieee80211_channel *chan) 244{ 245 const HAL_EEPROM_v4k *ee = AH_PRIVATE(ah)->ah_eeprom; 246 const struct ar5416eeprom_4k *eep = &ee->ee_base; 247 const MODAL_EEP4K_HEADER *pModal; 248 uint8_t txRxAttenLocal; 249 uint8_t ob[5], db1[5], db2[5]; 250 251 pModal = &eep->modalHeader; 252 txRxAttenLocal = 23; 253 254 OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon); 255 256 /* Single chain for 4K EEPROM*/ 257 ar9285SetBoardGain(ah, pModal, eep, txRxAttenLocal); 258 259 /* Initialize Ant Diversity settings if supported */ 260 (void) ar9285SetAntennaSwitch(ah, AH5212(ah)->ah_antControl); 261 262 /* Configure TX power calibration */ 263 if (pModal->version >= 2) { 264 ob[0] = pModal->ob_0; 265 ob[1] = pModal->ob_1; 266 ob[2] = pModal->ob_2; 267 ob[3] = pModal->ob_3; 268 ob[4] = pModal->ob_4; 269 270 db1[0] = pModal->db1_0; 271 db1[1] = pModal->db1_1; 272 db1[2] = pModal->db1_2; 273 db1[3] = pModal->db1_3; 274 db1[4] = pModal->db1_4; 275 276 db2[0] = pModal->db2_0; 277 db2[1] = pModal->db2_1; 278 db2[2] = pModal->db2_2; 279 db2[3] = pModal->db2_3; 280 db2[4] = pModal->db2_4; 281 } else if (pModal->version == 1) { 282 ob[0] = pModal->ob_0; 283 ob[1] = ob[2] = ob[3] = ob[4] = pModal->ob_1; 284 db1[0] = pModal->db1_0; 285 db1[1] = db1[2] = db1[3] = db1[4] = pModal->db1_1; 286 db2[0] = pModal->db2_0; 287 db2[1] = db2[2] = db2[3] = db2[4] = pModal->db2_1; 288 } else { 289 int i; 290 291 for (i = 0; i < 5; i++) { 292 ob[i] = pModal->ob_0; 293 db1[i] = pModal->db1_0; 294 db2[i] = pModal->db1_0; 295 } 296 } 297 298 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_OB_0, ob[0]); 299 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_OB_1, ob[1]); 300 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_OB_2, ob[2]); 301 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_OB_3, ob[3]); 302 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_OB_4, ob[4]); 303 304 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_DB1_0, db1[0]); 305 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_DB1_1, db1[1]); 306 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_DB1_2, db1[2]); 307 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G4, AR9285_AN_RF2G4_DB1_3, db1[3]); 308 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G4, AR9285_AN_RF2G4_DB1_4, db1[4]); 309 310 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G4, AR9285_AN_RF2G4_DB2_0, db2[0]); 311 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G4, AR9285_AN_RF2G4_DB2_1, db2[1]); 312 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G4, AR9285_AN_RF2G4_DB2_2, db2[2]); 313 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G4, AR9285_AN_RF2G4_DB2_3, db2[3]); 314 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G4, AR9285_AN_RF2G4_DB2_4, db2[4]); 315 316 OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH, 317 pModal->switchSettling); 318 OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC, 319 pModal->adcDesiredSize); 320 321 OS_REG_WRITE(ah, AR_PHY_RF_CTL4, 322 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF) | 323 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF) | 324 SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON) | 325 SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON)); 326 327 OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON, 328 pModal->txEndToRxOn); 329 330 OS_REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62, 331 pModal->thresh62); 332 OS_REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62, 333 pModal->thresh62); 334 335 if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= 336 AR5416_EEP_MINOR_VER_2) { 337 OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_FRAME_TO_DATA_START, 338 pModal->txFrameToDataStart); 339 OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_FRAME_TO_PA_ON, 340 pModal->txFrameToPaOn); 341 } 342 343 if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= 344 AR5416_EEP_MINOR_VER_3) { 345 if (IEEE80211_IS_CHAN_HT40(chan)) 346 OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, 347 AR_PHY_SETTLING_SWITCH, pModal->swSettleHt40); 348 } 349 350 /* 351 * Program the CCK TX gain factor appropriately if needed. 352 * The AR9285/AR9271 has a non-constant PA tx gain behaviour 353 * for CCK versus OFDM rates; other chips deal with this 354 * differently. 355 * 356 * The mask/shift/multiply hackery is done so place the same 357 * value (bb_desired_scale) into multiple 5-bit fields. 358 * For example, AR_PHY_TX_PWRCTRL9 has bb_desired_scale written 359 * to three fields: (0..4), (5..9) and (10..14). 360 */ 361 if (AR_SREV_9271(ah) || AR_SREV_KITE(ah)) { 362 uint8_t bb_desired_scale = (pModal->bb_scale_smrt_antenna & EEP_4K_BB_DESIRED_SCALE_MASK); 363 if ((eep->baseEepHeader.txGainType == 0) && (bb_desired_scale != 0)) { 364 ath_hal_printf(ah, "[ath]: adjusting cck tx gain factor\n"); 365 uint32_t pwrctrl, mask, clr; 366 367 mask = (1<<0) | (1<<5) | (1<<10) | (1<<15) | (1<<20) | (1<<25); 368 pwrctrl = mask * bb_desired_scale; 369 clr = mask * 0x1f; 370 OS_REG_RMW(ah, AR_PHY_TX_PWRCTRL8, pwrctrl, clr); 371 OS_REG_RMW(ah, AR_PHY_TX_PWRCTRL10, pwrctrl, clr); 372 OS_REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL12, pwrctrl, clr); 373 374 mask = (1<<0) | (1<<5) | (1<<15); 375 pwrctrl = mask * bb_desired_scale; 376 clr = mask * 0x1f; 377 OS_REG_RMW(ah, AR_PHY_TX_PWRCTRL9, pwrctrl, clr); 378 379 mask = (1<<0) | (1<<5); 380 pwrctrl = mask * bb_desired_scale; 381 clr = mask * 0x1f; 382 OS_REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL11, pwrctrl, clr); 383 OS_REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL13, pwrctrl, clr); 384 } 385 } 386 387 return AH_TRUE; 388} 389 390/* 391 * Helper functions common for AP/CB/XB 392 */ 393 394static HAL_BOOL 395ar9285SetPowerPerRateTable(struct ath_hal *ah, struct ar5416eeprom_4k *pEepData, 396 const struct ieee80211_channel *chan, 397 int16_t *ratesArray, uint16_t cfgCtl, 398 uint16_t AntennaReduction, 399 uint16_t twiceMaxRegulatoryPower, 400 uint16_t powerLimit) 401{ 402#define N(a) (sizeof(a)/sizeof(a[0])) 403/* Local defines to distinguish between extension and control CTL's */ 404#define EXT_ADDITIVE (0x8000) 405#define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE) 406#define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE) 407 408 uint16_t twiceMaxEdgePower = AR5416_MAX_RATE_POWER; 409 int i; 410 int16_t twiceLargestAntenna; 411 CAL_CTL_DATA_4K *rep; 412 CAL_TARGET_POWER_LEG targetPowerOfdm, targetPowerCck = {0, {0, 0, 0, 0}}; 413 CAL_TARGET_POWER_LEG targetPowerOfdmExt = {0, {0, 0, 0, 0}}, targetPowerCckExt = {0, {0, 0, 0, 0}}; 414 CAL_TARGET_POWER_HT targetPowerHt20, targetPowerHt40 = {0, {0, 0, 0, 0}}; 415 int16_t scaledPower, minCtlPower; 416 417#define SUB_NUM_CTL_MODES_AT_2G_40 3 /* excluding HT40, EXT-OFDM, EXT-CCK */ 418 static const uint16_t ctlModesFor11g[] = { 419 CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40 420 }; 421 const uint16_t *pCtlMode; 422 uint16_t numCtlModes, ctlMode, freq; 423 CHAN_CENTERS centers; 424 425 ar5416GetChannelCenters(ah, chan, ¢ers); 426 427 /* Compute TxPower reduction due to Antenna Gain */ 428 429 twiceLargestAntenna = pEepData->modalHeader.antennaGainCh[0]; 430 twiceLargestAntenna = (int16_t)AH_MIN((AntennaReduction) - twiceLargestAntenna, 0); 431 432 /* XXX setup for 5212 use (really used?) */ 433 ath_hal_eepromSet(ah, AR_EEP_ANTGAINMAX_2, twiceLargestAntenna); 434 435 /* 436 * scaledPower is the minimum of the user input power level and 437 * the regulatory allowed power level 438 */ 439 scaledPower = AH_MIN(powerLimit, twiceMaxRegulatoryPower + twiceLargestAntenna); 440 441 /* Get target powers from EEPROM - our baseline for TX Power */ 442 /* Setup for CTL modes */ 443 numCtlModes = N(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40; /* CTL_11B, CTL_11G, CTL_2GHT20 */ 444 pCtlMode = ctlModesFor11g; 445 446 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPowerCck, 447 AR5416_4K_NUM_2G_CCK_TARGET_POWERS, &targetPowerCck, 4, AH_FALSE); 448 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower2G, 449 AR5416_4K_NUM_2G_20_TARGET_POWERS, &targetPowerOfdm, 4, AH_FALSE); 450 ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower2GHT20, 451 AR5416_4K_NUM_2G_20_TARGET_POWERS, &targetPowerHt20, 8, AH_FALSE); 452 453 if (IEEE80211_IS_CHAN_HT40(chan)) { 454 numCtlModes = N(ctlModesFor11g); /* All 2G CTL's */ 455 456 ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower2GHT40, 457 AR5416_4K_NUM_2G_40_TARGET_POWERS, &targetPowerHt40, 8, AH_TRUE); 458 /* Get target powers for extension channels */ 459 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPowerCck, 460 AR5416_4K_NUM_2G_CCK_TARGET_POWERS, &targetPowerCckExt, 4, AH_TRUE); 461 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower2G, 462 AR5416_4K_NUM_2G_20_TARGET_POWERS, &targetPowerOfdmExt, 4, AH_TRUE); 463 } 464 465 /* 466 * For MIMO, need to apply regulatory caps individually across dynamically 467 * running modes: CCK, OFDM, HT20, HT40 468 * 469 * The outer loop walks through each possible applicable runtime mode. 470 * The inner loop walks through each ctlIndex entry in EEPROM. 471 * The ctl value is encoded as [7:4] == test group, [3:0] == test mode. 472 * 473 */ 474 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) { 475 HAL_BOOL isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) || 476 (pCtlMode[ctlMode] == CTL_2GHT40); 477 if (isHt40CtlMode) { 478 freq = centers.ctl_center; 479 } else if (pCtlMode[ctlMode] & EXT_ADDITIVE) { 480 freq = centers.ext_center; 481 } else { 482 freq = centers.ctl_center; 483 } 484 485 /* walk through each CTL index stored in EEPROM */ 486 for (i = 0; (i < AR5416_4K_NUM_CTLS) && pEepData->ctlIndex[i]; i++) { 487 uint16_t twiceMinEdgePower; 488 489 /* compare test group from regulatory channel list with test mode from pCtlMode list */ 490 if ((((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == pEepData->ctlIndex[i]) || 491 (((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == 492 ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))) { 493 rep = &(pEepData->ctlData[i]); 494 twiceMinEdgePower = ar5416GetMaxEdgePower(freq, 495 rep->ctlEdges[ 496 owl_get_ntxchains(AH5416(ah)->ah_tx_chainmask) - 1], AH_TRUE); 497 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) { 498 /* Find the minimum of all CTL edge powers that apply to this channel */ 499 twiceMaxEdgePower = AH_MIN(twiceMaxEdgePower, twiceMinEdgePower); 500 } else { 501 /* specific */ 502 twiceMaxEdgePower = twiceMinEdgePower; 503 break; 504 } 505 } 506 } 507 minCtlPower = (uint8_t)AH_MIN(twiceMaxEdgePower, scaledPower); 508 /* Apply ctl mode to correct target power set */ 509 switch(pCtlMode[ctlMode]) { 510 case CTL_11B: 511 for (i = 0; i < N(targetPowerCck.tPow2x); i++) { 512 targetPowerCck.tPow2x[i] = (uint8_t)AH_MIN(targetPowerCck.tPow2x[i], minCtlPower); 513 } 514 break; 515 case CTL_11A: 516 case CTL_11G: 517 for (i = 0; i < N(targetPowerOfdm.tPow2x); i++) { 518 targetPowerOfdm.tPow2x[i] = (uint8_t)AH_MIN(targetPowerOfdm.tPow2x[i], minCtlPower); 519 } 520 break; 521 case CTL_5GHT20: 522 case CTL_2GHT20: 523 for (i = 0; i < N(targetPowerHt20.tPow2x); i++) { 524 targetPowerHt20.tPow2x[i] = (uint8_t)AH_MIN(targetPowerHt20.tPow2x[i], minCtlPower); 525 } 526 break; 527 case CTL_11B_EXT: 528 targetPowerCckExt.tPow2x[0] = (uint8_t)AH_MIN(targetPowerCckExt.tPow2x[0], minCtlPower); 529 break; 530 case CTL_11G_EXT: 531 targetPowerOfdmExt.tPow2x[0] = (uint8_t)AH_MIN(targetPowerOfdmExt.tPow2x[0], minCtlPower); 532 break; 533 case CTL_5GHT40: 534 case CTL_2GHT40: 535 for (i = 0; i < N(targetPowerHt40.tPow2x); i++) { 536 targetPowerHt40.tPow2x[i] = (uint8_t)AH_MIN(targetPowerHt40.tPow2x[i], minCtlPower); 537 } 538 break; 539 default: 540 return AH_FALSE; 541 break; 542 } 543 } /* end ctl mode checking */ 544 545 /* Set rates Array from collected data */ 546 ar5416SetRatesArrayFromTargetPower(ah, chan, ratesArray, 547 &targetPowerCck, 548 &targetPowerCckExt, 549 &targetPowerOfdm, 550 &targetPowerOfdmExt, 551 &targetPowerHt20, 552 &targetPowerHt40); 553 554 return AH_TRUE; 555#undef EXT_ADDITIVE 556#undef CTL_11G_EXT 557#undef CTL_11B_EXT 558#undef SUB_NUM_CTL_MODES_AT_2G_40 559#undef N 560} 561 562static HAL_BOOL 563ar9285SetPowerCalTable(struct ath_hal *ah, struct ar5416eeprom_4k *pEepData, 564 const struct ieee80211_channel *chan, int16_t *pTxPowerIndexOffset) 565{ 566 CAL_DATA_PER_FREQ_4K *pRawDataset; 567 uint8_t *pCalBChans = AH_NULL; 568 uint16_t pdGainOverlap_t2; 569 static uint8_t pdadcValues[AR5416_NUM_PDADC_VALUES]; 570 uint16_t gainBoundaries[AR5416_PD_GAINS_IN_MASK]; 571 uint16_t numPiers, i; 572 int16_t tMinCalPower; 573 uint16_t numXpdGain, xpdMask; 574 uint16_t xpdGainValues[4]; /* v4k eeprom has 2; the other two stay 0 */ 575 uint32_t regChainOffset; 576 577 OS_MEMZERO(xpdGainValues, sizeof(xpdGainValues)); 578 579 xpdMask = pEepData->modalHeader.xpdGain; 580 581 if (IS_EEP_MINOR_V2(ah)) { 582 pdGainOverlap_t2 = pEepData->modalHeader.pdGainOverlap; 583 } else { 584 pdGainOverlap_t2 = (uint16_t)(MS(OS_REG_READ(ah, AR_PHY_TPCRG5), AR_PHY_TPCRG5_PD_GAIN_OVERLAP)); 585 } 586 587 pCalBChans = pEepData->calFreqPier2G; 588 numPiers = AR5416_4K_NUM_2G_CAL_PIERS; 589 numXpdGain = 0; 590 591 /* Calculate the value of xpdgains from the xpdGain Mask */ 592 for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) { 593 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) { 594 if (numXpdGain >= AR5416_4K_NUM_PD_GAINS) { 595 HALASSERT(0); 596 break; 597 } 598 xpdGainValues[numXpdGain] = (uint16_t)(AR5416_PD_GAINS_IN_MASK - i); 599 numXpdGain++; 600 } 601 } 602 603 /* Write the detector gain biases and their number */ 604 ar5416WriteDetectorGainBiases(ah, numXpdGain, xpdGainValues); 605 606 for (i = 0; i < AR5416_MAX_CHAINS; i++) { 607 regChainOffset = ar5416GetRegChainOffset(ah, i); 608 if (pEepData->baseEepHeader.txMask & (1 << i)) { 609 pRawDataset = pEepData->calPierData2G[i]; 610 611 ar9285GetGainBoundariesAndPdadcs(ah, chan, pRawDataset, 612 pCalBChans, numPiers, 613 pdGainOverlap_t2, 614 &tMinCalPower, gainBoundaries, 615 pdadcValues, numXpdGain); 616 617 if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah)) { 618 /* 619 * Note the pdadc table may not start at 0 dBm power, could be 620 * negative or greater than 0. Need to offset the power 621 * values by the amount of minPower for griffin 622 */ 623 ar5416SetGainBoundariesClosedLoop(ah, i, pdGainOverlap_t2, gainBoundaries); 624 } 625 626 /* Write the power values into the baseband power table */ 627 ar5416WritePdadcValues(ah, i, pdadcValues); 628 } 629 } 630 *pTxPowerIndexOffset = 0; 631 632 return AH_TRUE; 633} 634 635static void 636ar9285GetGainBoundariesAndPdadcs(struct ath_hal *ah, 637 const struct ieee80211_channel *chan, 638 CAL_DATA_PER_FREQ_4K *pRawDataSet, 639 uint8_t * bChans, uint16_t availPiers, 640 uint16_t tPdGainOverlap, int16_t *pMinCalPower, uint16_t * pPdGainBoundaries, 641 uint8_t * pPDADCValues, uint16_t numXpdGains) 642{ 643 644 int i, j, k; 645 int16_t ss; /* potentially -ve index for taking care of pdGainOverlap */ 646 uint16_t idxL, idxR, numPiers; /* Pier indexes */ 647 648 /* filled out Vpd table for all pdGains (chanL) */ 649 static uint8_t vpdTableL[AR5416_4K_NUM_PD_GAINS][AR5416_MAX_PWR_RANGE_IN_HALF_DB]; 650 651 /* filled out Vpd table for all pdGains (chanR) */ 652 static uint8_t vpdTableR[AR5416_4K_NUM_PD_GAINS][AR5416_MAX_PWR_RANGE_IN_HALF_DB]; 653 654 /* filled out Vpd table for all pdGains (interpolated) */ 655 static uint8_t vpdTableI[AR5416_4K_NUM_PD_GAINS][AR5416_MAX_PWR_RANGE_IN_HALF_DB]; 656 657 uint8_t *pVpdL, *pVpdR, *pPwrL, *pPwrR; 658 uint8_t minPwrT4[AR5416_4K_NUM_PD_GAINS]; 659 uint8_t maxPwrT4[AR5416_4K_NUM_PD_GAINS]; 660 int16_t vpdStep; 661 int16_t tmpVal; 662 uint16_t sizeCurrVpdTable, maxIndex, tgtIndex; 663 HAL_BOOL match; 664 int16_t minDelta = 0; 665 CHAN_CENTERS centers; 666 667 ar5416GetChannelCenters(ah, chan, ¢ers); 668 669 /* Trim numPiers for the number of populated channel Piers */ 670 for (numPiers = 0; numPiers < availPiers; numPiers++) { 671 if (bChans[numPiers] == AR5416_BCHAN_UNUSED) { 672 break; 673 } 674 } 675 676 /* Find pier indexes around the current channel */ 677 match = ath_ee_getLowerUpperIndex((uint8_t)FREQ2FBIN(centers.synth_center, 678 IEEE80211_IS_CHAN_2GHZ(chan)), bChans, numPiers, &idxL, &idxR); 679 680 if (match) { 681 /* Directly fill both vpd tables from the matching index */ 682 for (i = 0; i < numXpdGains; i++) { 683 minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0]; 684 maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4]; 685 ath_ee_FillVpdTable(minPwrT4[i], maxPwrT4[i], 686 pRawDataSet[idxL].pwrPdg[i], 687 pRawDataSet[idxL].vpdPdg[i], 688 AR5416_PD_GAIN_ICEPTS, vpdTableI[i]); 689 } 690 } else { 691 for (i = 0; i < numXpdGains; i++) { 692 pVpdL = pRawDataSet[idxL].vpdPdg[i]; 693 pPwrL = pRawDataSet[idxL].pwrPdg[i]; 694 pVpdR = pRawDataSet[idxR].vpdPdg[i]; 695 pPwrR = pRawDataSet[idxR].pwrPdg[i]; 696 697 /* Start Vpd interpolation from the max of the minimum powers */ 698 minPwrT4[i] = AH_MAX(pPwrL[0], pPwrR[0]); 699 700 /* End Vpd interpolation from the min of the max powers */ 701 maxPwrT4[i] = AH_MIN(pPwrL[AR5416_PD_GAIN_ICEPTS - 1], pPwrR[AR5416_PD_GAIN_ICEPTS - 1]); 702 HALASSERT(maxPwrT4[i] > minPwrT4[i]); 703 704 /* Fill pier Vpds */ 705 ath_ee_FillVpdTable(minPwrT4[i], maxPwrT4[i], pPwrL, pVpdL, 706 AR5416_PD_GAIN_ICEPTS, vpdTableL[i]); 707 ath_ee_FillVpdTable(minPwrT4[i], maxPwrT4[i], pPwrR, pVpdR, 708 AR5416_PD_GAIN_ICEPTS, vpdTableR[i]); 709 710 /* Interpolate the final vpd */ 711 for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) { 712 vpdTableI[i][j] = (uint8_t)(ath_ee_interpolate((uint16_t)FREQ2FBIN(centers.synth_center, 713 IEEE80211_IS_CHAN_2GHZ(chan)), 714 bChans[idxL], bChans[idxR], vpdTableL[i][j], vpdTableR[i][j])); 715 } 716 } 717 } 718 *pMinCalPower = (int16_t)(minPwrT4[0] / 2); 719 720 k = 0; /* index for the final table */ 721 for (i = 0; i < numXpdGains; i++) { 722 if (i == (numXpdGains - 1)) { 723 pPdGainBoundaries[i] = (uint16_t)(maxPwrT4[i] / 2); 724 } else { 725 pPdGainBoundaries[i] = (uint16_t)((maxPwrT4[i] + minPwrT4[i+1]) / 4); 726 } 727 728 pPdGainBoundaries[i] = (uint16_t)AH_MIN(AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]); 729 730 /* NB: only applies to owl 1.0 */ 731 if ((i == 0) && !AR_SREV_5416_V20_OR_LATER(ah) ) { 732 /* 733 * fix the gain delta, but get a delta that can be applied to min to 734 * keep the upper power values accurate, don't think max needs to 735 * be adjusted because should not be at that area of the table? 736 */ 737 minDelta = pPdGainBoundaries[0] - 23; 738 pPdGainBoundaries[0] = 23; 739 } 740 else { 741 minDelta = 0; 742 } 743 744 /* Find starting index for this pdGain */ 745 if (i == 0) { 746 if (AR_SREV_MERLIN_20_OR_LATER(ah)) 747 ss = (int16_t)(0 - (minPwrT4[i] / 2)); 748 else 749 ss = 0; /* for the first pdGain, start from index 0 */ 750 } else { 751 /* need overlap entries extrapolated below. */ 752 ss = (int16_t)((pPdGainBoundaries[i-1] - (minPwrT4[i] / 2)) - tPdGainOverlap + 1 + minDelta); 753 } 754 vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]); 755 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep); 756 /* 757 *-ve ss indicates need to extrapolate data below for this pdGain 758 */ 759 while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) { 760 tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep); 761 pPDADCValues[k++] = (uint8_t)((tmpVal < 0) ? 0 : tmpVal); 762 ss++; 763 } 764 765 sizeCurrVpdTable = (uint8_t)((maxPwrT4[i] - minPwrT4[i]) / 2 +1); 766 tgtIndex = (uint8_t)(pPdGainBoundaries[i] + tPdGainOverlap - (minPwrT4[i] / 2)); 767 maxIndex = (tgtIndex < sizeCurrVpdTable) ? tgtIndex : sizeCurrVpdTable; 768 769 while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) { 770 pPDADCValues[k++] = vpdTableI[i][ss++]; 771 } 772 773 vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] - vpdTableI[i][sizeCurrVpdTable - 2]); 774 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep); 775 /* 776 * for last gain, pdGainBoundary == Pmax_t2, so will 777 * have to extrapolate 778 */ 779 if (tgtIndex >= maxIndex) { /* need to extrapolate above */ 780 while ((ss <= tgtIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) { 781 tmpVal = (int16_t)((vpdTableI[i][sizeCurrVpdTable - 1] + 782 (ss - maxIndex +1) * vpdStep)); 783 pPDADCValues[k++] = (uint8_t)((tmpVal > 255) ? 255 : tmpVal); 784 ss++; 785 } 786 } /* extrapolated above */ 787 } /* for all pdGainUsed */ 788 789 /* Fill out pdGainBoundaries - only up to 2 allowed here, but hardware allows up to 4 */ 790 while (i < AR5416_PD_GAINS_IN_MASK) { 791 pPdGainBoundaries[i] = AR5416_4K_EEP_PD_GAIN_BOUNDARY_DEFAULT; 792 i++; 793 } 794 795 while (k < AR5416_NUM_PDADC_VALUES) { 796 pPDADCValues[k] = pPDADCValues[k-1]; 797 k++; 798 } 799 return; 800} 801