ar9285_reset.c revision 221574
1/* 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar9002/ar9285_reset.c 221574 2011-05-07 02:59:24Z adrian $ 18 */ 19 20/* 21 * This is almost the same as ar5416_reset.c but uses the v4k EEPROM and 22 * supports only 2Ghz operation. 23 */ 24 25#include "opt_ah.h" 26 27#include "ah.h" 28#include "ah_internal.h" 29#include "ah_devid.h" 30 31#include "ah_eeprom_v14.h" 32#include "ah_eeprom_v4k.h" 33 34#include "ar9002/ar9285.h" 35#include "ar5416/ar5416.h" 36#include "ar5416/ar5416reg.h" 37#include "ar5416/ar5416phy.h" 38#include "ar9002/ar9002phy.h" 39#include "ar9002/ar9285phy.h" 40 41/* Eeprom versioning macros. Returns true if the version is equal or newer than the ver specified */ 42#define EEP_MINOR(_ah) \ 43 (AH_PRIVATE(_ah)->ah_eeversion & AR5416_EEP_VER_MINOR_MASK) 44#define IS_EEP_MINOR_V2(_ah) (EEP_MINOR(_ah) >= AR5416_EEP_MINOR_VER_2) 45#define IS_EEP_MINOR_V3(_ah) (EEP_MINOR(_ah) >= AR5416_EEP_MINOR_VER_3) 46 47/* Additional Time delay to wait after activiting the Base band */ 48#define BASE_ACTIVATE_DELAY 100 /* 100 usec */ 49#define PLL_SETTLE_DELAY 300 /* 300 usec */ 50#define RTC_PLL_SETTLE_DELAY 1000 /* 1 ms */ 51 52static HAL_BOOL ar9285SetPowerPerRateTable(struct ath_hal *ah, 53 struct ar5416eeprom_4k *pEepData, 54 const struct ieee80211_channel *chan, int16_t *ratesArray, 55 uint16_t cfgCtl, uint16_t AntennaReduction, 56 uint16_t twiceMaxRegulatoryPower, 57 uint16_t powerLimit); 58static HAL_BOOL ar9285SetPowerCalTable(struct ath_hal *ah, 59 struct ar5416eeprom_4k *pEepData, 60 const struct ieee80211_channel *chan, 61 int16_t *pTxPowerIndexOffset); 62static void ar9285GetGainBoundariesAndPdadcs(struct ath_hal *ah, 63 const struct ieee80211_channel *chan, CAL_DATA_PER_FREQ_4K *pRawDataSet, 64 uint8_t * bChans, uint16_t availPiers, 65 uint16_t tPdGainOverlap, int16_t *pMinCalPower, 66 uint16_t * pPdGainBoundaries, uint8_t * pPDADCValues, 67 uint16_t numXpdGains); 68 69HAL_BOOL 70ar9285SetTransmitPower(struct ath_hal *ah, 71 const struct ieee80211_channel *chan, uint16_t *rfXpdGain) 72{ 73#define POW_SM(_r, _s) (((_r) & 0x3f) << (_s)) 74#define N(a) (sizeof (a) / sizeof (a[0])) 75 76 MODAL_EEP4K_HEADER *pModal; 77 struct ath_hal_5212 *ahp = AH5212(ah); 78 int16_t ratesArray[Ar5416RateSize]; 79 int16_t txPowerIndexOffset = 0; 80 uint8_t ht40PowerIncForPdadc = 2; 81 int i; 82 83 uint16_t cfgCtl; 84 uint16_t powerLimit; 85 uint16_t twiceAntennaReduction; 86 uint16_t twiceMaxRegulatoryPower; 87 int16_t maxPower; 88 HAL_EEPROM_v4k *ee = AH_PRIVATE(ah)->ah_eeprom; 89 struct ar5416eeprom_4k *pEepData = &ee->ee_base; 90 91 HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER14_1); 92 93 /* Setup info for the actual eeprom */ 94 OS_MEMZERO(ratesArray, sizeof(ratesArray)); 95 cfgCtl = ath_hal_getctl(ah, chan); 96 powerLimit = chan->ic_maxregpower * 2; 97 twiceAntennaReduction = chan->ic_maxantgain; 98 twiceMaxRegulatoryPower = AH_MIN(MAX_RATE_POWER, AH_PRIVATE(ah)->ah_powerLimit); 99 pModal = &pEepData->modalHeader; 100 HALDEBUG(ah, HAL_DEBUG_RESET, "%s Channel=%u CfgCtl=%u\n", 101 __func__,chan->ic_freq, cfgCtl ); 102 103 if (IS_EEP_MINOR_V2(ah)) { 104 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc; 105 } 106 107 if (!ar9285SetPowerPerRateTable(ah, pEepData, chan, 108 &ratesArray[0],cfgCtl, 109 twiceAntennaReduction, 110 twiceMaxRegulatoryPower, powerLimit)) { 111 HALDEBUG(ah, HAL_DEBUG_ANY, 112 "%s: unable to set tx power per rate table\n", __func__); 113 return AH_FALSE; 114 } 115 116 if (!ar9285SetPowerCalTable(ah, pEepData, chan, &txPowerIndexOffset)) { 117 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unable to set power table\n", 118 __func__); 119 return AH_FALSE; 120 } 121 122 maxPower = AH_MAX(ratesArray[rate6mb], ratesArray[rateHt20_0]); 123 maxPower = AH_MAX(maxPower, ratesArray[rate1l]); 124 125 if (IEEE80211_IS_CHAN_HT40(chan)) { 126 maxPower = AH_MAX(maxPower, ratesArray[rateHt40_0]); 127 } 128 129 ahp->ah_tx6PowerInHalfDbm = maxPower; 130 AH_PRIVATE(ah)->ah_maxPowerLevel = maxPower; 131 ahp->ah_txPowerIndexOffset = txPowerIndexOffset; 132 133 /* 134 * txPowerIndexOffset is set by the SetPowerTable() call - 135 * adjust the rate table (0 offset if rates EEPROM not loaded) 136 */ 137 for (i = 0; i < N(ratesArray); i++) { 138 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]); 139 /* -5 dBm offset for Merlin and later; this includes Kite */ 140 ratesArray[i] -= AR5416_PWR_TABLE_OFFSET_DB * 2; 141 if (ratesArray[i] > AR5416_MAX_RATE_POWER) 142 ratesArray[i] = AR5416_MAX_RATE_POWER; 143 if (ratesArray[i] < 0) 144 ratesArray[i] = 0; 145 } 146 147#ifdef AH_EEPROM_DUMP 148 ar5416PrintPowerPerRate(ah, ratesArray); 149#endif 150 151 /* 152 * Adjust the HT40 power to meet the correct target TX power 153 * for 40MHz mode, based on TX power curves that are established 154 * for 20MHz mode. 155 * 156 * XXX handle overflow/too high power level? 157 */ 158 if (IEEE80211_IS_CHAN_HT40(chan)) { 159 ratesArray[rateHt40_0] += ht40PowerIncForPdadc; 160 ratesArray[rateHt40_1] += ht40PowerIncForPdadc; 161 ratesArray[rateHt40_2] += ht40PowerIncForPdadc; 162 ratesArray[rateHt40_3] += ht40PowerIncForPdadc; 163 ratesArray[rateHt40_4] += ht40PowerIncForPdadc; 164 ratesArray[rateHt40_5] += ht40PowerIncForPdadc; 165 ratesArray[rateHt40_6] += ht40PowerIncForPdadc; 166 ratesArray[rateHt40_7] += ht40PowerIncForPdadc; 167 } 168 169 /* Write the TX power rate registers */ 170 ar5416WriteTxPowerRateRegisters(ah, chan, ratesArray); 171 172 return AH_TRUE; 173#undef POW_SM 174#undef N 175} 176 177static void 178ar9285SetBoardGain(struct ath_hal *ah, const MODAL_EEP4K_HEADER *pModal, 179 const struct ar5416eeprom_4k *eep, uint8_t txRxAttenLocal) 180{ 181 OS_REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0, 182 pModal->antCtrlChain[0]); 183 184 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0), 185 (OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0)) & 186 ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF | 187 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) | 188 SM(pModal->iqCalICh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) | 189 SM(pModal->iqCalQCh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF)); 190 191 if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= 192 AR5416_EEP_MINOR_VER_3) { 193 txRxAttenLocal = pModal->txRxAttenCh[0]; 194 195 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, 196 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, pModal->bswMargin[0]); 197 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, 198 AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]); 199 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, 200 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN, pModal->xatten2Margin[0]); 201 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, 202 AR_PHY_GAIN_2GHZ_XATTEN2_DB, pModal->xatten2Db[0]); 203 204 /* Set the block 1 value to block 0 value */ 205 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000, 206 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, 207 pModal->bswMargin[0]); 208 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000, 209 AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]); 210 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000, 211 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN, 212 pModal->xatten2Margin[0]); 213 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000, 214 AR_PHY_GAIN_2GHZ_XATTEN2_DB, pModal->xatten2Db[0]); 215 } 216 217 OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN, 218 AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal); 219 OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN, 220 AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]); 221 222 OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000, 223 AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal); 224 OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000, 225 AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]); 226} 227 228/* 229 * Read EEPROM header info and program the device for correct operation 230 * given the channel value. 231 */ 232HAL_BOOL 233ar9285SetBoardValues(struct ath_hal *ah, const struct ieee80211_channel *chan) 234{ 235 const HAL_EEPROM_v4k *ee = AH_PRIVATE(ah)->ah_eeprom; 236 const struct ar5416eeprom_4k *eep = &ee->ee_base; 237 const MODAL_EEP4K_HEADER *pModal; 238 uint8_t txRxAttenLocal; 239 uint8_t ob[5], db1[5], db2[5]; 240 uint8_t ant_div_control1, ant_div_control2; 241 uint32_t regVal; 242 243 pModal = &eep->modalHeader; 244 txRxAttenLocal = 23; 245 246 OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon); 247 248 /* Single chain for 4K EEPROM*/ 249 ar9285SetBoardGain(ah, pModal, eep, txRxAttenLocal); 250 251 /* Initialize Ant Diversity settings from EEPROM */ 252 if (pModal->version >= 3) { 253 ant_div_control1 = pModal->antdiv_ctl1; 254 ant_div_control2 = pModal->antdiv_ctl2; 255 256 regVal = OS_REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); 257 regVal &= (~(AR_PHY_9285_ANT_DIV_CTL_ALL)); 258 259 regVal |= SM(ant_div_control1, 260 AR_PHY_9285_ANT_DIV_CTL); 261 regVal |= SM(ant_div_control2, 262 AR_PHY_9285_ANT_DIV_ALT_LNACONF); 263 regVal |= SM((ant_div_control2 >> 2), 264 AR_PHY_9285_ANT_DIV_MAIN_LNACONF); 265 regVal |= SM((ant_div_control1 >> 1), 266 AR_PHY_9285_ANT_DIV_ALT_GAINTB); 267 regVal |= SM((ant_div_control1 >> 2), 268 AR_PHY_9285_ANT_DIV_MAIN_GAINTB); 269 270 OS_REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regVal); 271 regVal = OS_REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); 272 regVal = OS_REG_READ(ah, AR_PHY_CCK_DETECT); 273 regVal &= (~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV); 274 regVal |= SM((ant_div_control1 >> 3), 275 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV); 276 277 OS_REG_WRITE(ah, AR_PHY_CCK_DETECT, regVal); 278 regVal = OS_REG_READ(ah, AR_PHY_CCK_DETECT); 279 } 280 281 if (pModal->version >= 2) { 282 ob[0] = pModal->ob_0; 283 ob[1] = pModal->ob_1; 284 ob[2] = pModal->ob_2; 285 ob[3] = pModal->ob_3; 286 ob[4] = pModal->ob_4; 287 288 db1[0] = pModal->db1_0; 289 db1[1] = pModal->db1_1; 290 db1[2] = pModal->db1_2; 291 db1[3] = pModal->db1_3; 292 db1[4] = pModal->db1_4; 293 294 db2[0] = pModal->db2_0; 295 db2[1] = pModal->db2_1; 296 db2[2] = pModal->db2_2; 297 db2[3] = pModal->db2_3; 298 db2[4] = pModal->db2_4; 299 } else if (pModal->version == 1) { 300 ob[0] = pModal->ob_0; 301 ob[1] = ob[2] = ob[3] = ob[4] = pModal->ob_1; 302 db1[0] = pModal->db1_0; 303 db1[1] = db1[2] = db1[3] = db1[4] = pModal->db1_1; 304 db2[0] = pModal->db2_0; 305 db2[1] = db2[2] = db2[3] = db2[4] = pModal->db2_1; 306 } else { 307 int i; 308 309 for (i = 0; i < 5; i++) { 310 ob[i] = pModal->ob_0; 311 db1[i] = pModal->db1_0; 312 db2[i] = pModal->db1_0; 313 } 314 } 315 316 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_OB_0, ob[0]); 317 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_OB_1, ob[1]); 318 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_OB_2, ob[2]); 319 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_OB_3, ob[3]); 320 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_OB_4, ob[4]); 321 322 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_DB1_0, db1[0]); 323 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_DB1_1, db1[1]); 324 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_DB1_2, db1[2]); 325 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G4, AR9285_AN_RF2G4_DB1_3, db1[3]); 326 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G4, AR9285_AN_RF2G4_DB1_4, db1[4]); 327 328 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G4, AR9285_AN_RF2G4_DB2_0, db2[0]); 329 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G4, AR9285_AN_RF2G4_DB2_1, db2[1]); 330 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G4, AR9285_AN_RF2G4_DB2_2, db2[2]); 331 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G4, AR9285_AN_RF2G4_DB2_3, db2[3]); 332 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G4, AR9285_AN_RF2G4_DB2_4, db2[4]); 333 334 OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH, 335 pModal->switchSettling); 336 OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC, 337 pModal->adcDesiredSize); 338 339 OS_REG_WRITE(ah, AR_PHY_RF_CTL4, 340 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF) | 341 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF) | 342 SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON) | 343 SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON)); 344 345 OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON, 346 pModal->txEndToRxOn); 347 348 OS_REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62, 349 pModal->thresh62); 350 OS_REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62, 351 pModal->thresh62); 352 353 if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= 354 AR5416_EEP_MINOR_VER_2) { 355 OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_FRAME_TO_DATA_START, 356 pModal->txFrameToDataStart); 357 OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_FRAME_TO_PA_ON, 358 pModal->txFrameToPaOn); 359 } 360 361 if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= 362 AR5416_EEP_MINOR_VER_3) { 363 if (IEEE80211_IS_CHAN_HT40(chan)) 364 OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, 365 AR_PHY_SETTLING_SWITCH, pModal->swSettleHt40); 366 } 367 368 /* 369 * Program the CCK TX gain factor appropriately if needed. 370 * The AR9285/AR9271 has a non-constant PA tx gain behaviour 371 * for CCK versus OFDM rates; other chips deal with this 372 * differently. 373 * 374 * The mask/shift/multiply hackery is done so place the same 375 * value (bb_desired_scale) into multiple 5-bit fields. 376 * For example, AR_PHY_TX_PWRCTRL9 has bb_desired_scale written 377 * to three fields: (0..4), (5..9) and (10..14). 378 */ 379 if (AR_SREV_9271(ah) || AR_SREV_KITE(ah)) { 380 uint8_t bb_desired_scale = (pModal->bb_scale_smrt_antenna & EEP_4K_BB_DESIRED_SCALE_MASK); 381 if ((eep->baseEepHeader.txGainType == 0) && (bb_desired_scale != 0)) { 382 uint32_t pwrctrl, mask, clr; 383 384 mask = (1<<0) | (1<<5) | (1<<10) | (1<<15) | (1<<20) | (1<<25); 385 pwrctrl = mask * bb_desired_scale; 386 clr = mask * 0x1f; 387 OS_REG_RMW(ah, AR_PHY_TX_PWRCTRL8, pwrctrl, clr); 388 OS_REG_RMW(ah, AR_PHY_TX_PWRCTRL10, pwrctrl, clr); 389 OS_REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL12, pwrctrl, clr); 390 391 mask = (1<<0) | (1<<5) | (1<<15); 392 pwrctrl = mask * bb_desired_scale; 393 clr = mask * 0x1f; 394 OS_REG_RMW(ah, AR_PHY_TX_PWRCTRL9, pwrctrl, clr); 395 396 mask = (1<<0) | (1<<5); 397 pwrctrl = mask * bb_desired_scale; 398 clr = mask * 0x1f; 399 OS_REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL11, pwrctrl, clr); 400 OS_REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL13, pwrctrl, clr); 401 } 402 } 403 404 return AH_TRUE; 405} 406 407/* 408 * Helper functions common for AP/CB/XB 409 */ 410 411static HAL_BOOL 412ar9285SetPowerPerRateTable(struct ath_hal *ah, struct ar5416eeprom_4k *pEepData, 413 const struct ieee80211_channel *chan, 414 int16_t *ratesArray, uint16_t cfgCtl, 415 uint16_t AntennaReduction, 416 uint16_t twiceMaxRegulatoryPower, 417 uint16_t powerLimit) 418{ 419#define N(a) (sizeof(a)/sizeof(a[0])) 420/* Local defines to distinguish between extension and control CTL's */ 421#define EXT_ADDITIVE (0x8000) 422#define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE) 423#define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE) 424 425 uint16_t twiceMaxEdgePower = AR5416_MAX_RATE_POWER; 426 int i; 427 int16_t twiceLargestAntenna; 428 CAL_CTL_DATA_4K *rep; 429 CAL_TARGET_POWER_LEG targetPowerOfdm, targetPowerCck = {0, {0, 0, 0, 0}}; 430 CAL_TARGET_POWER_LEG targetPowerOfdmExt = {0, {0, 0, 0, 0}}, targetPowerCckExt = {0, {0, 0, 0, 0}}; 431 CAL_TARGET_POWER_HT targetPowerHt20, targetPowerHt40 = {0, {0, 0, 0, 0}}; 432 int16_t scaledPower, minCtlPower; 433 434#define SUB_NUM_CTL_MODES_AT_2G_40 3 /* excluding HT40, EXT-OFDM, EXT-CCK */ 435 static const uint16_t ctlModesFor11g[] = { 436 CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40 437 }; 438 const uint16_t *pCtlMode; 439 uint16_t numCtlModes, ctlMode, freq; 440 CHAN_CENTERS centers; 441 442 ar5416GetChannelCenters(ah, chan, ¢ers); 443 444 /* Compute TxPower reduction due to Antenna Gain */ 445 446 twiceLargestAntenna = pEepData->modalHeader.antennaGainCh[0]; 447 twiceLargestAntenna = (int16_t)AH_MIN((AntennaReduction) - twiceLargestAntenna, 0); 448 449 /* XXX setup for 5212 use (really used?) */ 450 ath_hal_eepromSet(ah, AR_EEP_ANTGAINMAX_2, twiceLargestAntenna); 451 452 /* 453 * scaledPower is the minimum of the user input power level and 454 * the regulatory allowed power level 455 */ 456 scaledPower = AH_MIN(powerLimit, twiceMaxRegulatoryPower + twiceLargestAntenna); 457 458 /* Get target powers from EEPROM - our baseline for TX Power */ 459 /* Setup for CTL modes */ 460 numCtlModes = N(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40; /* CTL_11B, CTL_11G, CTL_2GHT20 */ 461 pCtlMode = ctlModesFor11g; 462 463 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPowerCck, 464 AR5416_4K_NUM_2G_CCK_TARGET_POWERS, &targetPowerCck, 4, AH_FALSE); 465 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower2G, 466 AR5416_4K_NUM_2G_20_TARGET_POWERS, &targetPowerOfdm, 4, AH_FALSE); 467 ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower2GHT20, 468 AR5416_4K_NUM_2G_20_TARGET_POWERS, &targetPowerHt20, 8, AH_FALSE); 469 470 if (IEEE80211_IS_CHAN_HT40(chan)) { 471 numCtlModes = N(ctlModesFor11g); /* All 2G CTL's */ 472 473 ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower2GHT40, 474 AR5416_4K_NUM_2G_40_TARGET_POWERS, &targetPowerHt40, 8, AH_TRUE); 475 /* Get target powers for extension channels */ 476 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPowerCck, 477 AR5416_4K_NUM_2G_CCK_TARGET_POWERS, &targetPowerCckExt, 4, AH_TRUE); 478 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower2G, 479 AR5416_4K_NUM_2G_20_TARGET_POWERS, &targetPowerOfdmExt, 4, AH_TRUE); 480 } 481 482 /* 483 * For MIMO, need to apply regulatory caps individually across dynamically 484 * running modes: CCK, OFDM, HT20, HT40 485 * 486 * The outer loop walks through each possible applicable runtime mode. 487 * The inner loop walks through each ctlIndex entry in EEPROM. 488 * The ctl value is encoded as [7:4] == test group, [3:0] == test mode. 489 * 490 */ 491 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) { 492 HAL_BOOL isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) || 493 (pCtlMode[ctlMode] == CTL_2GHT40); 494 if (isHt40CtlMode) { 495 freq = centers.ctl_center; 496 } else if (pCtlMode[ctlMode] & EXT_ADDITIVE) { 497 freq = centers.ext_center; 498 } else { 499 freq = centers.ctl_center; 500 } 501 502 /* walk through each CTL index stored in EEPROM */ 503 for (i = 0; (i < AR5416_4K_NUM_CTLS) && pEepData->ctlIndex[i]; i++) { 504 uint16_t twiceMinEdgePower; 505 506 /* compare test group from regulatory channel list with test mode from pCtlMode list */ 507 if ((((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == pEepData->ctlIndex[i]) || 508 (((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == 509 ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))) { 510 rep = &(pEepData->ctlData[i]); 511 twiceMinEdgePower = ar5416GetMaxEdgePower(freq, 512 rep->ctlEdges[ 513 owl_get_ntxchains(AH5416(ah)->ah_tx_chainmask) - 1], AH_TRUE); 514 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) { 515 /* Find the minimum of all CTL edge powers that apply to this channel */ 516 twiceMaxEdgePower = AH_MIN(twiceMaxEdgePower, twiceMinEdgePower); 517 } else { 518 /* specific */ 519 twiceMaxEdgePower = twiceMinEdgePower; 520 break; 521 } 522 } 523 } 524 minCtlPower = (uint8_t)AH_MIN(twiceMaxEdgePower, scaledPower); 525 /* Apply ctl mode to correct target power set */ 526 switch(pCtlMode[ctlMode]) { 527 case CTL_11B: 528 for (i = 0; i < N(targetPowerCck.tPow2x); i++) { 529 targetPowerCck.tPow2x[i] = (uint8_t)AH_MIN(targetPowerCck.tPow2x[i], minCtlPower); 530 } 531 break; 532 case CTL_11A: 533 case CTL_11G: 534 for (i = 0; i < N(targetPowerOfdm.tPow2x); i++) { 535 targetPowerOfdm.tPow2x[i] = (uint8_t)AH_MIN(targetPowerOfdm.tPow2x[i], minCtlPower); 536 } 537 break; 538 case CTL_5GHT20: 539 case CTL_2GHT20: 540 for (i = 0; i < N(targetPowerHt20.tPow2x); i++) { 541 targetPowerHt20.tPow2x[i] = (uint8_t)AH_MIN(targetPowerHt20.tPow2x[i], minCtlPower); 542 } 543 break; 544 case CTL_11B_EXT: 545 targetPowerCckExt.tPow2x[0] = (uint8_t)AH_MIN(targetPowerCckExt.tPow2x[0], minCtlPower); 546 break; 547 case CTL_11G_EXT: 548 targetPowerOfdmExt.tPow2x[0] = (uint8_t)AH_MIN(targetPowerOfdmExt.tPow2x[0], minCtlPower); 549 break; 550 case CTL_5GHT40: 551 case CTL_2GHT40: 552 for (i = 0; i < N(targetPowerHt40.tPow2x); i++) { 553 targetPowerHt40.tPow2x[i] = (uint8_t)AH_MIN(targetPowerHt40.tPow2x[i], minCtlPower); 554 } 555 break; 556 default: 557 return AH_FALSE; 558 break; 559 } 560 } /* end ctl mode checking */ 561 562 /* Set rates Array from collected data */ 563 ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] = ratesArray[rate18mb] = ratesArray[rate24mb] = targetPowerOfdm.tPow2x[0]; 564 ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1]; 565 ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2]; 566 ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3]; 567 ratesArray[rateXr] = targetPowerOfdm.tPow2x[0]; 568 569 for (i = 0; i < N(targetPowerHt20.tPow2x); i++) { 570 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i]; 571 } 572 573 ratesArray[rate1l] = targetPowerCck.tPow2x[0]; 574 ratesArray[rate2s] = ratesArray[rate2l] = targetPowerCck.tPow2x[1]; 575 ratesArray[rate5_5s] = ratesArray[rate5_5l] = targetPowerCck.tPow2x[2]; 576 ratesArray[rate11s] = ratesArray[rate11l] = targetPowerCck.tPow2x[3]; 577 if (IEEE80211_IS_CHAN_HT40(chan)) { 578 for (i = 0; i < N(targetPowerHt40.tPow2x); i++) { 579 ratesArray[rateHt40_0 + i] = targetPowerHt40.tPow2x[i]; 580 } 581 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0]; 582 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0]; 583 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0]; 584 if (IEEE80211_IS_CHAN_2GHZ(chan)) { 585 ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0]; 586 } 587 } 588 return AH_TRUE; 589#undef EXT_ADDITIVE 590#undef CTL_11G_EXT 591#undef CTL_11B_EXT 592#undef SUB_NUM_CTL_MODES_AT_2G_40 593#undef N 594} 595 596static HAL_BOOL 597ar9285SetPowerCalTable(struct ath_hal *ah, struct ar5416eeprom_4k *pEepData, 598 const struct ieee80211_channel *chan, int16_t *pTxPowerIndexOffset) 599{ 600 CAL_DATA_PER_FREQ_4K *pRawDataset; 601 uint8_t *pCalBChans = AH_NULL; 602 uint16_t pdGainOverlap_t2; 603 static uint8_t pdadcValues[AR5416_NUM_PDADC_VALUES]; 604 uint16_t gainBoundaries[AR5416_PD_GAINS_IN_MASK]; 605 uint16_t numPiers, i; 606 int16_t tMinCalPower; 607 uint16_t numXpdGain, xpdMask; 608 uint16_t xpdGainValues[4]; /* v4k eeprom has 2; the other two stay 0 */ 609 uint32_t regChainOffset; 610 611 OS_MEMZERO(xpdGainValues, sizeof(xpdGainValues)); 612 613 xpdMask = pEepData->modalHeader.xpdGain; 614 615 if (IS_EEP_MINOR_V2(ah)) { 616 pdGainOverlap_t2 = pEepData->modalHeader.pdGainOverlap; 617 } else { 618 pdGainOverlap_t2 = (uint16_t)(MS(OS_REG_READ(ah, AR_PHY_TPCRG5), AR_PHY_TPCRG5_PD_GAIN_OVERLAP)); 619 } 620 621 pCalBChans = pEepData->calFreqPier2G; 622 numPiers = AR5416_4K_NUM_2G_CAL_PIERS; 623 numXpdGain = 0; 624 625 /* Calculate the value of xpdgains from the xpdGain Mask */ 626 for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) { 627 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) { 628 if (numXpdGain >= AR5416_4K_NUM_PD_GAINS) { 629 HALASSERT(0); 630 break; 631 } 632 xpdGainValues[numXpdGain] = (uint16_t)(AR5416_PD_GAINS_IN_MASK - i); 633 numXpdGain++; 634 } 635 } 636 637 /* Write the detector gain biases and their number */ 638 ar5416WriteDetectorGainBiases(ah, numXpdGain, xpdGainValues); 639 640 for (i = 0; i < AR5416_MAX_CHAINS; i++) { 641 regChainOffset = ar5416GetRegChainOffset(ah, i); 642 if (pEepData->baseEepHeader.txMask & (1 << i)) { 643 pRawDataset = pEepData->calPierData2G[i]; 644 645 ar9285GetGainBoundariesAndPdadcs(ah, chan, pRawDataset, 646 pCalBChans, numPiers, 647 pdGainOverlap_t2, 648 &tMinCalPower, gainBoundaries, 649 pdadcValues, numXpdGain); 650 651 if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah)) { 652 /* 653 * Note the pdadc table may not start at 0 dBm power, could be 654 * negative or greater than 0. Need to offset the power 655 * values by the amount of minPower for griffin 656 */ 657 ar5416SetGainBoundariesClosedLoop(ah, i, pdGainOverlap_t2, gainBoundaries); 658 } 659 660 /* Write the power values into the baseband power table */ 661 ar5416WritePdadcValues(ah, i, pdadcValues); 662 } 663 } 664 *pTxPowerIndexOffset = 0; 665 666 return AH_TRUE; 667} 668 669static void 670ar9285GetGainBoundariesAndPdadcs(struct ath_hal *ah, 671 const struct ieee80211_channel *chan, 672 CAL_DATA_PER_FREQ_4K *pRawDataSet, 673 uint8_t * bChans, uint16_t availPiers, 674 uint16_t tPdGainOverlap, int16_t *pMinCalPower, uint16_t * pPdGainBoundaries, 675 uint8_t * pPDADCValues, uint16_t numXpdGains) 676{ 677 678 int i, j, k; 679 int16_t ss; /* potentially -ve index for taking care of pdGainOverlap */ 680 uint16_t idxL, idxR, numPiers; /* Pier indexes */ 681 682 /* filled out Vpd table for all pdGains (chanL) */ 683 static uint8_t vpdTableL[AR5416_4K_NUM_PD_GAINS][AR5416_MAX_PWR_RANGE_IN_HALF_DB]; 684 685 /* filled out Vpd table for all pdGains (chanR) */ 686 static uint8_t vpdTableR[AR5416_4K_NUM_PD_GAINS][AR5416_MAX_PWR_RANGE_IN_HALF_DB]; 687 688 /* filled out Vpd table for all pdGains (interpolated) */ 689 static uint8_t vpdTableI[AR5416_4K_NUM_PD_GAINS][AR5416_MAX_PWR_RANGE_IN_HALF_DB]; 690 691 uint8_t *pVpdL, *pVpdR, *pPwrL, *pPwrR; 692 uint8_t minPwrT4[AR5416_4K_NUM_PD_GAINS]; 693 uint8_t maxPwrT4[AR5416_4K_NUM_PD_GAINS]; 694 int16_t vpdStep; 695 int16_t tmpVal; 696 uint16_t sizeCurrVpdTable, maxIndex, tgtIndex; 697 HAL_BOOL match; 698 int16_t minDelta = 0; 699 CHAN_CENTERS centers; 700 701 ar5416GetChannelCenters(ah, chan, ¢ers); 702 703 /* Trim numPiers for the number of populated channel Piers */ 704 for (numPiers = 0; numPiers < availPiers; numPiers++) { 705 if (bChans[numPiers] == AR5416_BCHAN_UNUSED) { 706 break; 707 } 708 } 709 710 /* Find pier indexes around the current channel */ 711 match = ath_ee_getLowerUpperIndex((uint8_t)FREQ2FBIN(centers.synth_center, 712 IEEE80211_IS_CHAN_2GHZ(chan)), bChans, numPiers, &idxL, &idxR); 713 714 if (match) { 715 /* Directly fill both vpd tables from the matching index */ 716 for (i = 0; i < numXpdGains; i++) { 717 minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0]; 718 maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4]; 719 ath_ee_FillVpdTable(minPwrT4[i], maxPwrT4[i], 720 pRawDataSet[idxL].pwrPdg[i], 721 pRawDataSet[idxL].vpdPdg[i], 722 AR5416_PD_GAIN_ICEPTS, vpdTableI[i]); 723 } 724 } else { 725 for (i = 0; i < numXpdGains; i++) { 726 pVpdL = pRawDataSet[idxL].vpdPdg[i]; 727 pPwrL = pRawDataSet[idxL].pwrPdg[i]; 728 pVpdR = pRawDataSet[idxR].vpdPdg[i]; 729 pPwrR = pRawDataSet[idxR].pwrPdg[i]; 730 731 /* Start Vpd interpolation from the max of the minimum powers */ 732 minPwrT4[i] = AH_MAX(pPwrL[0], pPwrR[0]); 733 734 /* End Vpd interpolation from the min of the max powers */ 735 maxPwrT4[i] = AH_MIN(pPwrL[AR5416_PD_GAIN_ICEPTS - 1], pPwrR[AR5416_PD_GAIN_ICEPTS - 1]); 736 HALASSERT(maxPwrT4[i] > minPwrT4[i]); 737 738 /* Fill pier Vpds */ 739 ath_ee_FillVpdTable(minPwrT4[i], maxPwrT4[i], pPwrL, pVpdL, 740 AR5416_PD_GAIN_ICEPTS, vpdTableL[i]); 741 ath_ee_FillVpdTable(minPwrT4[i], maxPwrT4[i], pPwrR, pVpdR, 742 AR5416_PD_GAIN_ICEPTS, vpdTableR[i]); 743 744 /* Interpolate the final vpd */ 745 for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) { 746 vpdTableI[i][j] = (uint8_t)(ath_ee_interpolate((uint16_t)FREQ2FBIN(centers.synth_center, 747 IEEE80211_IS_CHAN_2GHZ(chan)), 748 bChans[idxL], bChans[idxR], vpdTableL[i][j], vpdTableR[i][j])); 749 } 750 } 751 } 752 *pMinCalPower = (int16_t)(minPwrT4[0] / 2); 753 754 k = 0; /* index for the final table */ 755 for (i = 0; i < numXpdGains; i++) { 756 if (i == (numXpdGains - 1)) { 757 pPdGainBoundaries[i] = (uint16_t)(maxPwrT4[i] / 2); 758 } else { 759 pPdGainBoundaries[i] = (uint16_t)((maxPwrT4[i] + minPwrT4[i+1]) / 4); 760 } 761 762 pPdGainBoundaries[i] = (uint16_t)AH_MIN(AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]); 763 764 /* NB: only applies to owl 1.0 */ 765 if ((i == 0) && !AR_SREV_5416_V20_OR_LATER(ah) ) { 766 /* 767 * fix the gain delta, but get a delta that can be applied to min to 768 * keep the upper power values accurate, don't think max needs to 769 * be adjusted because should not be at that area of the table? 770 */ 771 minDelta = pPdGainBoundaries[0] - 23; 772 pPdGainBoundaries[0] = 23; 773 } 774 else { 775 minDelta = 0; 776 } 777 778 /* Find starting index for this pdGain */ 779 if (i == 0) { 780 if (AR_SREV_MERLIN_20_OR_LATER(ah)) 781 ss = (int16_t)(0 - (minPwrT4[i] / 2)); 782 else 783 ss = 0; /* for the first pdGain, start from index 0 */ 784 } else { 785 /* need overlap entries extrapolated below. */ 786 ss = (int16_t)((pPdGainBoundaries[i-1] - (minPwrT4[i] / 2)) - tPdGainOverlap + 1 + minDelta); 787 } 788 vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]); 789 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep); 790 /* 791 *-ve ss indicates need to extrapolate data below for this pdGain 792 */ 793 while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) { 794 tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep); 795 pPDADCValues[k++] = (uint8_t)((tmpVal < 0) ? 0 : tmpVal); 796 ss++; 797 } 798 799 sizeCurrVpdTable = (uint8_t)((maxPwrT4[i] - minPwrT4[i]) / 2 +1); 800 tgtIndex = (uint8_t)(pPdGainBoundaries[i] + tPdGainOverlap - (minPwrT4[i] / 2)); 801 maxIndex = (tgtIndex < sizeCurrVpdTable) ? tgtIndex : sizeCurrVpdTable; 802 803 while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) { 804 pPDADCValues[k++] = vpdTableI[i][ss++]; 805 } 806 807 vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] - vpdTableI[i][sizeCurrVpdTable - 2]); 808 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep); 809 /* 810 * for last gain, pdGainBoundary == Pmax_t2, so will 811 * have to extrapolate 812 */ 813 if (tgtIndex >= maxIndex) { /* need to extrapolate above */ 814 while ((ss <= tgtIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) { 815 tmpVal = (int16_t)((vpdTableI[i][sizeCurrVpdTable - 1] + 816 (ss - maxIndex +1) * vpdStep)); 817 pPDADCValues[k++] = (uint8_t)((tmpVal > 255) ? 255 : tmpVal); 818 ss++; 819 } 820 } /* extrapolated above */ 821 } /* for all pdGainUsed */ 822 823 /* Fill out pdGainBoundaries - only up to 2 allowed here, but hardware allows up to 4 */ 824 while (i < AR5416_PD_GAINS_IN_MASK) { 825 pPdGainBoundaries[i] = AR5416_4K_EEP_PD_GAIN_BOUNDARY_DEFAULT; 826 i++; 827 } 828 829 while (k < AR5416_NUM_PDADC_VALUES) { 830 pPDADCValues[k] = pPDADCValues[k-1]; 831 k++; 832 } 833 return; 834} 835