ar9285_reset.c revision 220713
1/* 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar9002/ar9285_reset.c 220713 2011-04-16 11:59:37Z adrian $ 18 */ 19 20/* 21 * This is almost the same as ar5416_reset.c but uses the v4k EEPROM and 22 * supports only 2Ghz operation. 23 */ 24 25#include "opt_ah.h" 26 27#include "ah.h" 28#include "ah_internal.h" 29#include "ah_devid.h" 30 31#include "ah_eeprom_v14.h" 32#include "ah_eeprom_v4k.h" 33 34#include "ar9002/ar9285.h" 35#include "ar5416/ar5416.h" 36#include "ar5416/ar5416reg.h" 37#include "ar5416/ar5416phy.h" 38#include "ar9002/ar9002phy.h" 39#include "ar9002/ar9285phy.h" 40 41/* Eeprom versioning macros. Returns true if the version is equal or newer than the ver specified */ 42#define EEP_MINOR(_ah) \ 43 (AH_PRIVATE(_ah)->ah_eeversion & AR5416_EEP_VER_MINOR_MASK) 44#define IS_EEP_MINOR_V2(_ah) (EEP_MINOR(_ah) >= AR5416_EEP_MINOR_VER_2) 45#define IS_EEP_MINOR_V3(_ah) (EEP_MINOR(_ah) >= AR5416_EEP_MINOR_VER_3) 46 47/* Additional Time delay to wait after activiting the Base band */ 48#define BASE_ACTIVATE_DELAY 100 /* 100 usec */ 49#define PLL_SETTLE_DELAY 300 /* 300 usec */ 50#define RTC_PLL_SETTLE_DELAY 1000 /* 1 ms */ 51 52static HAL_BOOL ar9285SetPowerPerRateTable(struct ath_hal *ah, 53 struct ar5416eeprom_4k *pEepData, 54 const struct ieee80211_channel *chan, int16_t *ratesArray, 55 uint16_t cfgCtl, uint16_t AntennaReduction, 56 uint16_t twiceMaxRegulatoryPower, 57 uint16_t powerLimit); 58static HAL_BOOL ar9285SetPowerCalTable(struct ath_hal *ah, 59 struct ar5416eeprom_4k *pEepData, 60 const struct ieee80211_channel *chan, 61 int16_t *pTxPowerIndexOffset); 62static void ar9285GetGainBoundariesAndPdadcs(struct ath_hal *ah, 63 const struct ieee80211_channel *chan, CAL_DATA_PER_FREQ_4K *pRawDataSet, 64 uint8_t * bChans, uint16_t availPiers, 65 uint16_t tPdGainOverlap, int16_t *pMinCalPower, 66 uint16_t * pPdGainBoundaries, uint8_t * pPDADCValues, 67 uint16_t numXpdGains); 68 69HAL_BOOL 70ar9285SetTransmitPower(struct ath_hal *ah, 71 const struct ieee80211_channel *chan, uint16_t *rfXpdGain) 72{ 73#define POW_SM(_r, _s) (((_r) & 0x3f) << (_s)) 74#define N(a) (sizeof (a) / sizeof (a[0])) 75 76 MODAL_EEP4K_HEADER *pModal; 77 struct ath_hal_5212 *ahp = AH5212(ah); 78 int16_t ratesArray[Ar5416RateSize]; 79 int16_t txPowerIndexOffset = 0; 80 uint8_t ht40PowerIncForPdadc = 2; 81 int i; 82 83 uint16_t cfgCtl; 84 uint16_t powerLimit; 85 uint16_t twiceAntennaReduction; 86 uint16_t twiceMaxRegulatoryPower; 87 int16_t maxPower; 88 HAL_EEPROM_v4k *ee = AH_PRIVATE(ah)->ah_eeprom; 89 struct ar5416eeprom_4k *pEepData = &ee->ee_base; 90 91 HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER14_1); 92 93 /* Setup info for the actual eeprom */ 94 OS_MEMZERO(ratesArray, sizeof(ratesArray)); 95 cfgCtl = ath_hal_getctl(ah, chan); 96 powerLimit = chan->ic_maxregpower * 2; 97 twiceAntennaReduction = chan->ic_maxantgain; 98 twiceMaxRegulatoryPower = AH_MIN(MAX_RATE_POWER, AH_PRIVATE(ah)->ah_powerLimit); 99 pModal = &pEepData->modalHeader; 100 HALDEBUG(ah, HAL_DEBUG_RESET, "%s Channel=%u CfgCtl=%u\n", 101 __func__,chan->ic_freq, cfgCtl ); 102 103 if (IS_EEP_MINOR_V2(ah)) { 104 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc; 105 } 106 107 if (!ar9285SetPowerPerRateTable(ah, pEepData, chan, 108 &ratesArray[0],cfgCtl, 109 twiceAntennaReduction, 110 twiceMaxRegulatoryPower, powerLimit)) { 111 HALDEBUG(ah, HAL_DEBUG_ANY, 112 "%s: unable to set tx power per rate table\n", __func__); 113 return AH_FALSE; 114 } 115 116 if (!ar9285SetPowerCalTable(ah, pEepData, chan, &txPowerIndexOffset)) { 117 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unable to set power table\n", 118 __func__); 119 return AH_FALSE; 120 } 121 122 maxPower = AH_MAX(ratesArray[rate6mb], ratesArray[rateHt20_0]); 123 maxPower = AH_MAX(maxPower, ratesArray[rate1l]); 124 125 if (IEEE80211_IS_CHAN_HT40(chan)) { 126 maxPower = AH_MAX(maxPower, ratesArray[rateHt40_0]); 127 } 128 129 ahp->ah_tx6PowerInHalfDbm = maxPower; 130 AH_PRIVATE(ah)->ah_maxPowerLevel = maxPower; 131 ahp->ah_txPowerIndexOffset = txPowerIndexOffset; 132 133 /* 134 * txPowerIndexOffset is set by the SetPowerTable() call - 135 * adjust the rate table (0 offset if rates EEPROM not loaded) 136 */ 137 for (i = 0; i < N(ratesArray); i++) { 138 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]); 139 /* -5 dBm offset for Merlin and later; this includes Kite */ 140 ratesArray[i] -= AR5416_PWR_TABLE_OFFSET_DB * 2; 141 if (ratesArray[i] > AR5416_MAX_RATE_POWER) 142 ratesArray[i] = AR5416_MAX_RATE_POWER; 143 if (ratesArray[i] < 0) 144 ratesArray[i] = 0; 145 } 146 147#ifdef AH_EEPROM_DUMP 148 ar5416PrintPowerPerRate(ah, ratesArray); 149#endif 150 151 /* Write the OFDM power per rate set */ 152 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE1, 153 POW_SM(ratesArray[rate18mb], 24) 154 | POW_SM(ratesArray[rate12mb], 16) 155 | POW_SM(ratesArray[rate9mb], 8) 156 | POW_SM(ratesArray[rate6mb], 0) 157 ); 158 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE2, 159 POW_SM(ratesArray[rate54mb], 24) 160 | POW_SM(ratesArray[rate48mb], 16) 161 | POW_SM(ratesArray[rate36mb], 8) 162 | POW_SM(ratesArray[rate24mb], 0) 163 ); 164 165 /* Write the CCK power per rate set */ 166 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE3, 167 POW_SM(ratesArray[rate2s], 24) 168 | POW_SM(ratesArray[rate2l], 16) 169 | POW_SM(ratesArray[rateXr], 8) /* XR target power */ 170 | POW_SM(ratesArray[rate1l], 0) 171 ); 172 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE4, 173 POW_SM(ratesArray[rate11s], 24) 174 | POW_SM(ratesArray[rate11l], 16) 175 | POW_SM(ratesArray[rate5_5s], 8) 176 | POW_SM(ratesArray[rate5_5l], 0) 177 ); 178 HALDEBUG(ah, HAL_DEBUG_RESET, 179 "%s AR_PHY_POWER_TX_RATE3=0x%x AR_PHY_POWER_TX_RATE4=0x%x\n", 180 __func__, OS_REG_READ(ah,AR_PHY_POWER_TX_RATE3), 181 OS_REG_READ(ah,AR_PHY_POWER_TX_RATE4)); 182 183 /* Write the HT20 power per rate set */ 184 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE5, 185 POW_SM(ratesArray[rateHt20_3], 24) 186 | POW_SM(ratesArray[rateHt20_2], 16) 187 | POW_SM(ratesArray[rateHt20_1], 8) 188 | POW_SM(ratesArray[rateHt20_0], 0) 189 ); 190 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE6, 191 POW_SM(ratesArray[rateHt20_7], 24) 192 | POW_SM(ratesArray[rateHt20_6], 16) 193 | POW_SM(ratesArray[rateHt20_5], 8) 194 | POW_SM(ratesArray[rateHt20_4], 0) 195 ); 196 197 if (IEEE80211_IS_CHAN_HT40(chan)) { 198 /* Write the HT40 power per rate set */ 199 /* Correct PAR difference between HT40 and HT20/LEGACY */ 200 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE7, 201 POW_SM(ratesArray[rateHt40_3] + ht40PowerIncForPdadc, 24) 202 | POW_SM(ratesArray[rateHt40_2] + ht40PowerIncForPdadc, 16) 203 | POW_SM(ratesArray[rateHt40_1] + ht40PowerIncForPdadc, 8) 204 | POW_SM(ratesArray[rateHt40_0] + ht40PowerIncForPdadc, 0) 205 ); 206 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE8, 207 POW_SM(ratesArray[rateHt40_7] + ht40PowerIncForPdadc, 24) 208 | POW_SM(ratesArray[rateHt40_6] + ht40PowerIncForPdadc, 16) 209 | POW_SM(ratesArray[rateHt40_5] + ht40PowerIncForPdadc, 8) 210 | POW_SM(ratesArray[rateHt40_4] + ht40PowerIncForPdadc, 0) 211 ); 212 /* Write the Dup/Ext 40 power per rate set */ 213 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE9, 214 POW_SM(ratesArray[rateExtOfdm], 24) 215 | POW_SM(ratesArray[rateExtCck], 16) 216 | POW_SM(ratesArray[rateDupOfdm], 8) 217 | POW_SM(ratesArray[rateDupCck], 0) 218 ); 219 } 220 221 return AH_TRUE; 222#undef POW_SM 223#undef N 224} 225 226static void 227ar9285SetBoardGain(struct ath_hal *ah, const MODAL_EEP4K_HEADER *pModal, 228 const struct ar5416eeprom_4k *eep, uint8_t txRxAttenLocal) 229{ 230 OS_REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0, 231 pModal->antCtrlChain[0]); 232 233 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0), 234 (OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0)) & 235 ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF | 236 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) | 237 SM(pModal->iqCalICh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) | 238 SM(pModal->iqCalQCh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF)); 239 240 if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= 241 AR5416_EEP_MINOR_VER_3) { 242 txRxAttenLocal = pModal->txRxAttenCh[0]; 243 244 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, 245 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, pModal->bswMargin[0]); 246 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, 247 AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]); 248 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, 249 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN, pModal->xatten2Margin[0]); 250 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, 251 AR_PHY_GAIN_2GHZ_XATTEN2_DB, pModal->xatten2Db[0]); 252 253 /* Set the block 1 value to block 0 value */ 254 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000, 255 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, 256 pModal->bswMargin[0]); 257 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000, 258 AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]); 259 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000, 260 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN, 261 pModal->xatten2Margin[0]); 262 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000, 263 AR_PHY_GAIN_2GHZ_XATTEN2_DB, pModal->xatten2Db[0]); 264 } 265 266 OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN, 267 AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal); 268 OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN, 269 AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]); 270 271 OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000, 272 AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal); 273 OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000, 274 AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]); 275} 276 277/* 278 * Read EEPROM header info and program the device for correct operation 279 * given the channel value. 280 */ 281HAL_BOOL 282ar9285SetBoardValues(struct ath_hal *ah, const struct ieee80211_channel *chan) 283{ 284 const HAL_EEPROM_v4k *ee = AH_PRIVATE(ah)->ah_eeprom; 285 const struct ar5416eeprom_4k *eep = &ee->ee_base; 286 const MODAL_EEP4K_HEADER *pModal; 287 uint8_t txRxAttenLocal; 288 uint8_t ob[5], db1[5], db2[5]; 289 uint8_t ant_div_control1, ant_div_control2; 290 uint32_t regVal; 291 292 pModal = &eep->modalHeader; 293 txRxAttenLocal = 23; 294 295 OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon); 296 297 /* Single chain for 4K EEPROM*/ 298 ar9285SetBoardGain(ah, pModal, eep, txRxAttenLocal); 299 300 /* Initialize Ant Diversity settings from EEPROM */ 301 if (pModal->version >= 3) { 302 ant_div_control1 = pModal->antdiv_ctl1; 303 ant_div_control2 = pModal->antdiv_ctl2; 304 305 regVal = OS_REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); 306 regVal &= (~(AR_PHY_9285_ANT_DIV_CTL_ALL)); 307 308 regVal |= SM(ant_div_control1, 309 AR_PHY_9285_ANT_DIV_CTL); 310 regVal |= SM(ant_div_control2, 311 AR_PHY_9285_ANT_DIV_ALT_LNACONF); 312 regVal |= SM((ant_div_control2 >> 2), 313 AR_PHY_9285_ANT_DIV_MAIN_LNACONF); 314 regVal |= SM((ant_div_control1 >> 1), 315 AR_PHY_9285_ANT_DIV_ALT_GAINTB); 316 regVal |= SM((ant_div_control1 >> 2), 317 AR_PHY_9285_ANT_DIV_MAIN_GAINTB); 318 319 OS_REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regVal); 320 regVal = OS_REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); 321 regVal = OS_REG_READ(ah, AR_PHY_CCK_DETECT); 322 regVal &= (~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV); 323 regVal |= SM((ant_div_control1 >> 3), 324 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV); 325 326 OS_REG_WRITE(ah, AR_PHY_CCK_DETECT, regVal); 327 regVal = OS_REG_READ(ah, AR_PHY_CCK_DETECT); 328 } 329 330 if (pModal->version >= 2) { 331 ob[0] = pModal->ob_0; 332 ob[1] = pModal->ob_1; 333 ob[2] = pModal->ob_2; 334 ob[3] = pModal->ob_3; 335 ob[4] = pModal->ob_4; 336 337 db1[0] = pModal->db1_0; 338 db1[1] = pModal->db1_1; 339 db1[2] = pModal->db1_2; 340 db1[3] = pModal->db1_3; 341 db1[4] = pModal->db1_4; 342 343 db2[0] = pModal->db2_0; 344 db2[1] = pModal->db2_1; 345 db2[2] = pModal->db2_2; 346 db2[3] = pModal->db2_3; 347 db2[4] = pModal->db2_4; 348 } else if (pModal->version == 1) { 349 ob[0] = pModal->ob_0; 350 ob[1] = ob[2] = ob[3] = ob[4] = pModal->ob_1; 351 db1[0] = pModal->db1_0; 352 db1[1] = db1[2] = db1[3] = db1[4] = pModal->db1_1; 353 db2[0] = pModal->db2_0; 354 db2[1] = db2[2] = db2[3] = db2[4] = pModal->db2_1; 355 } else { 356 int i; 357 358 for (i = 0; i < 5; i++) { 359 ob[i] = pModal->ob_0; 360 db1[i] = pModal->db1_0; 361 db2[i] = pModal->db1_0; 362 } 363 } 364 365 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_OB_0, ob[0]); 366 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_OB_1, ob[1]); 367 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_OB_2, ob[2]); 368 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_OB_3, ob[3]); 369 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_OB_4, ob[4]); 370 371 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_DB1_0, db1[0]); 372 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_DB1_1, db1[1]); 373 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_DB1_2, db1[2]); 374 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G4, AR9285_AN_RF2G4_DB1_3, db1[3]); 375 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G4, AR9285_AN_RF2G4_DB1_4, db1[4]); 376 377 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G4, AR9285_AN_RF2G4_DB2_0, db2[0]); 378 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G4, AR9285_AN_RF2G4_DB2_1, db2[1]); 379 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G4, AR9285_AN_RF2G4_DB2_2, db2[2]); 380 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G4, AR9285_AN_RF2G4_DB2_3, db2[3]); 381 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G4, AR9285_AN_RF2G4_DB2_4, db2[4]); 382 383 OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH, 384 pModal->switchSettling); 385 OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC, 386 pModal->adcDesiredSize); 387 388 OS_REG_WRITE(ah, AR_PHY_RF_CTL4, 389 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF) | 390 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF) | 391 SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON) | 392 SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON)); 393 394 OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON, 395 pModal->txEndToRxOn); 396 397 OS_REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62, 398 pModal->thresh62); 399 OS_REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62, 400 pModal->thresh62); 401 402 if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= 403 AR5416_EEP_MINOR_VER_2) { 404 OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_FRAME_TO_DATA_START, 405 pModal->txFrameToDataStart); 406 OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_FRAME_TO_PA_ON, 407 pModal->txFrameToPaOn); 408 } 409 410 if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= 411 AR5416_EEP_MINOR_VER_3) { 412 if (IEEE80211_IS_CHAN_HT40(chan)) 413 OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, 414 AR_PHY_SETTLING_SWITCH, pModal->swSettleHt40); 415 } 416 417 /* 418 * Program the CCK TX gain factor appropriately if needed. 419 * The AR9285/AR9271 has a non-constant PA tx gain behaviour 420 * for CCK versus OFDM rates; other chips deal with this 421 * differently. 422 * 423 * The mask/shift/multiply hackery is done so place the same 424 * value (bb_desired_scale) into multiple 5-bit fields. 425 * For example, AR_PHY_TX_PWRCTRL9 has bb_desired_scale written 426 * to three fields: (0..4), (5..9) and (10..14). 427 */ 428 if (AR_SREV_9271(ah) || AR_SREV_KITE(ah)) { 429 uint8_t bb_desired_scale = (pModal->bb_scale_smrt_antenna & EEP_4K_BB_DESIRED_SCALE_MASK); 430 if ((eep->baseEepHeader.txGainType == 0) && (bb_desired_scale != 0)) { 431 uint32_t pwrctrl, mask, clr; 432 433 mask = (1<<0) | (1<<5) | (1<<10) | (1<<15) | (1<<20) | (1<<25); 434 pwrctrl = mask * bb_desired_scale; 435 clr = mask * 0x1f; 436 OS_REG_RMW(ah, AR_PHY_TX_PWRCTRL8, pwrctrl, clr); 437 OS_REG_RMW(ah, AR_PHY_TX_PWRCTRL10, pwrctrl, clr); 438 OS_REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL12, pwrctrl, clr); 439 440 mask = (1<<0) | (1<<5) | (1<<15); 441 pwrctrl = mask * bb_desired_scale; 442 clr = mask * 0x1f; 443 OS_REG_RMW(ah, AR_PHY_TX_PWRCTRL9, pwrctrl, clr); 444 445 mask = (1<<0) | (1<<5); 446 pwrctrl = mask * bb_desired_scale; 447 clr = mask * 0x1f; 448 OS_REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL11, pwrctrl, clr); 449 OS_REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL13, pwrctrl, clr); 450 } 451 } 452 453 return AH_TRUE; 454} 455 456/* 457 * Helper functions common for AP/CB/XB 458 */ 459 460static HAL_BOOL 461ar9285SetPowerPerRateTable(struct ath_hal *ah, struct ar5416eeprom_4k *pEepData, 462 const struct ieee80211_channel *chan, 463 int16_t *ratesArray, uint16_t cfgCtl, 464 uint16_t AntennaReduction, 465 uint16_t twiceMaxRegulatoryPower, 466 uint16_t powerLimit) 467{ 468#define N(a) (sizeof(a)/sizeof(a[0])) 469/* Local defines to distinguish between extension and control CTL's */ 470#define EXT_ADDITIVE (0x8000) 471#define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE) 472#define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE) 473 474 uint16_t twiceMaxEdgePower = AR5416_MAX_RATE_POWER; 475 int i; 476 int16_t twiceLargestAntenna; 477 CAL_CTL_DATA_4K *rep; 478 CAL_TARGET_POWER_LEG targetPowerOfdm, targetPowerCck = {0, {0, 0, 0, 0}}; 479 CAL_TARGET_POWER_LEG targetPowerOfdmExt = {0, {0, 0, 0, 0}}, targetPowerCckExt = {0, {0, 0, 0, 0}}; 480 CAL_TARGET_POWER_HT targetPowerHt20, targetPowerHt40 = {0, {0, 0, 0, 0}}; 481 int16_t scaledPower, minCtlPower; 482 483#define SUB_NUM_CTL_MODES_AT_2G_40 3 /* excluding HT40, EXT-OFDM, EXT-CCK */ 484 static const uint16_t ctlModesFor11g[] = { 485 CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40 486 }; 487 const uint16_t *pCtlMode; 488 uint16_t numCtlModes, ctlMode, freq; 489 CHAN_CENTERS centers; 490 491 ar5416GetChannelCenters(ah, chan, ¢ers); 492 493 /* Compute TxPower reduction due to Antenna Gain */ 494 495 twiceLargestAntenna = pEepData->modalHeader.antennaGainCh[0]; 496 twiceLargestAntenna = (int16_t)AH_MIN((AntennaReduction) - twiceLargestAntenna, 0); 497 498 /* XXX setup for 5212 use (really used?) */ 499 ath_hal_eepromSet(ah, AR_EEP_ANTGAINMAX_2, twiceLargestAntenna); 500 501 /* 502 * scaledPower is the minimum of the user input power level and 503 * the regulatory allowed power level 504 */ 505 scaledPower = AH_MIN(powerLimit, twiceMaxRegulatoryPower + twiceLargestAntenna); 506 507 /* Get target powers from EEPROM - our baseline for TX Power */ 508 /* Setup for CTL modes */ 509 numCtlModes = N(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40; /* CTL_11B, CTL_11G, CTL_2GHT20 */ 510 pCtlMode = ctlModesFor11g; 511 512 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPowerCck, 513 AR5416_4K_NUM_2G_CCK_TARGET_POWERS, &targetPowerCck, 4, AH_FALSE); 514 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower2G, 515 AR5416_4K_NUM_2G_20_TARGET_POWERS, &targetPowerOfdm, 4, AH_FALSE); 516 ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower2GHT20, 517 AR5416_4K_NUM_2G_20_TARGET_POWERS, &targetPowerHt20, 8, AH_FALSE); 518 519 if (IEEE80211_IS_CHAN_HT40(chan)) { 520 numCtlModes = N(ctlModesFor11g); /* All 2G CTL's */ 521 522 ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower2GHT40, 523 AR5416_4K_NUM_2G_40_TARGET_POWERS, &targetPowerHt40, 8, AH_TRUE); 524 /* Get target powers for extension channels */ 525 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPowerCck, 526 AR5416_4K_NUM_2G_CCK_TARGET_POWERS, &targetPowerCckExt, 4, AH_TRUE); 527 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower2G, 528 AR5416_4K_NUM_2G_20_TARGET_POWERS, &targetPowerOfdmExt, 4, AH_TRUE); 529 } 530 531 /* 532 * For MIMO, need to apply regulatory caps individually across dynamically 533 * running modes: CCK, OFDM, HT20, HT40 534 * 535 * The outer loop walks through each possible applicable runtime mode. 536 * The inner loop walks through each ctlIndex entry in EEPROM. 537 * The ctl value is encoded as [7:4] == test group, [3:0] == test mode. 538 * 539 */ 540 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) { 541 HAL_BOOL isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) || 542 (pCtlMode[ctlMode] == CTL_2GHT40); 543 if (isHt40CtlMode) { 544 freq = centers.ctl_center; 545 } else if (pCtlMode[ctlMode] & EXT_ADDITIVE) { 546 freq = centers.ext_center; 547 } else { 548 freq = centers.ctl_center; 549 } 550 551 /* walk through each CTL index stored in EEPROM */ 552 for (i = 0; (i < AR5416_4K_NUM_CTLS) && pEepData->ctlIndex[i]; i++) { 553 uint16_t twiceMinEdgePower; 554 555 /* compare test group from regulatory channel list with test mode from pCtlMode list */ 556 if ((((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == pEepData->ctlIndex[i]) || 557 (((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == 558 ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))) { 559 rep = &(pEepData->ctlData[i]); 560 twiceMinEdgePower = ar5416GetMaxEdgePower(freq, 561 rep->ctlEdges[ 562 owl_get_ntxchains(AH5416(ah)->ah_tx_chainmask) - 1], AH_TRUE); 563 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) { 564 /* Find the minimum of all CTL edge powers that apply to this channel */ 565 twiceMaxEdgePower = AH_MIN(twiceMaxEdgePower, twiceMinEdgePower); 566 } else { 567 /* specific */ 568 twiceMaxEdgePower = twiceMinEdgePower; 569 break; 570 } 571 } 572 } 573 minCtlPower = (uint8_t)AH_MIN(twiceMaxEdgePower, scaledPower); 574 /* Apply ctl mode to correct target power set */ 575 switch(pCtlMode[ctlMode]) { 576 case CTL_11B: 577 for (i = 0; i < N(targetPowerCck.tPow2x); i++) { 578 targetPowerCck.tPow2x[i] = (uint8_t)AH_MIN(targetPowerCck.tPow2x[i], minCtlPower); 579 } 580 break; 581 case CTL_11A: 582 case CTL_11G: 583 for (i = 0; i < N(targetPowerOfdm.tPow2x); i++) { 584 targetPowerOfdm.tPow2x[i] = (uint8_t)AH_MIN(targetPowerOfdm.tPow2x[i], minCtlPower); 585 } 586 break; 587 case CTL_5GHT20: 588 case CTL_2GHT20: 589 for (i = 0; i < N(targetPowerHt20.tPow2x); i++) { 590 targetPowerHt20.tPow2x[i] = (uint8_t)AH_MIN(targetPowerHt20.tPow2x[i], minCtlPower); 591 } 592 break; 593 case CTL_11B_EXT: 594 targetPowerCckExt.tPow2x[0] = (uint8_t)AH_MIN(targetPowerCckExt.tPow2x[0], minCtlPower); 595 break; 596 case CTL_11G_EXT: 597 targetPowerOfdmExt.tPow2x[0] = (uint8_t)AH_MIN(targetPowerOfdmExt.tPow2x[0], minCtlPower); 598 break; 599 case CTL_5GHT40: 600 case CTL_2GHT40: 601 for (i = 0; i < N(targetPowerHt40.tPow2x); i++) { 602 targetPowerHt40.tPow2x[i] = (uint8_t)AH_MIN(targetPowerHt40.tPow2x[i], minCtlPower); 603 } 604 break; 605 default: 606 return AH_FALSE; 607 break; 608 } 609 } /* end ctl mode checking */ 610 611 /* Set rates Array from collected data */ 612 ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] = ratesArray[rate18mb] = ratesArray[rate24mb] = targetPowerOfdm.tPow2x[0]; 613 ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1]; 614 ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2]; 615 ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3]; 616 ratesArray[rateXr] = targetPowerOfdm.tPow2x[0]; 617 618 for (i = 0; i < N(targetPowerHt20.tPow2x); i++) { 619 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i]; 620 } 621 622 ratesArray[rate1l] = targetPowerCck.tPow2x[0]; 623 ratesArray[rate2s] = ratesArray[rate2l] = targetPowerCck.tPow2x[1]; 624 ratesArray[rate5_5s] = ratesArray[rate5_5l] = targetPowerCck.tPow2x[2]; 625 ratesArray[rate11s] = ratesArray[rate11l] = targetPowerCck.tPow2x[3]; 626 if (IEEE80211_IS_CHAN_HT40(chan)) { 627 for (i = 0; i < N(targetPowerHt40.tPow2x); i++) { 628 ratesArray[rateHt40_0 + i] = targetPowerHt40.tPow2x[i]; 629 } 630 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0]; 631 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0]; 632 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0]; 633 if (IEEE80211_IS_CHAN_2GHZ(chan)) { 634 ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0]; 635 } 636 } 637 return AH_TRUE; 638#undef EXT_ADDITIVE 639#undef CTL_11G_EXT 640#undef CTL_11B_EXT 641#undef SUB_NUM_CTL_MODES_AT_2G_40 642#undef N 643} 644 645static HAL_BOOL 646ar9285SetPowerCalTable(struct ath_hal *ah, struct ar5416eeprom_4k *pEepData, 647 const struct ieee80211_channel *chan, int16_t *pTxPowerIndexOffset) 648{ 649 CAL_DATA_PER_FREQ_4K *pRawDataset; 650 uint8_t *pCalBChans = AH_NULL; 651 uint16_t pdGainOverlap_t2; 652 static uint8_t pdadcValues[AR5416_NUM_PDADC_VALUES]; 653 uint16_t gainBoundaries[AR5416_PD_GAINS_IN_MASK]; 654 uint16_t numPiers, i; 655 int16_t tMinCalPower; 656 uint16_t numXpdGain, xpdMask; 657 uint16_t xpdGainValues[4]; /* v4k eeprom has 2; the other two stay 0 */ 658 uint32_t regChainOffset; 659 660 OS_MEMZERO(xpdGainValues, sizeof(xpdGainValues)); 661 662 xpdMask = pEepData->modalHeader.xpdGain; 663 664 if (IS_EEP_MINOR_V2(ah)) { 665 pdGainOverlap_t2 = pEepData->modalHeader.pdGainOverlap; 666 } else { 667 pdGainOverlap_t2 = (uint16_t)(MS(OS_REG_READ(ah, AR_PHY_TPCRG5), AR_PHY_TPCRG5_PD_GAIN_OVERLAP)); 668 } 669 670 pCalBChans = pEepData->calFreqPier2G; 671 numPiers = AR5416_4K_NUM_2G_CAL_PIERS; 672 numXpdGain = 0; 673 674 /* Calculate the value of xpdgains from the xpdGain Mask */ 675 for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) { 676 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) { 677 if (numXpdGain >= AR5416_4K_NUM_PD_GAINS) { 678 HALASSERT(0); 679 break; 680 } 681 xpdGainValues[numXpdGain] = (uint16_t)(AR5416_PD_GAINS_IN_MASK - i); 682 numXpdGain++; 683 } 684 } 685 686 /* Write the detector gain biases and their number */ 687 ar5416WriteDetectorGainBiases(ah, numXpdGain, xpdGainValues); 688 689 for (i = 0; i < AR5416_MAX_CHAINS; i++) { 690 regChainOffset = ar5416GetRegChainOffset(ah, i); 691 if (pEepData->baseEepHeader.txMask & (1 << i)) { 692 pRawDataset = pEepData->calPierData2G[i]; 693 694 ar9285GetGainBoundariesAndPdadcs(ah, chan, pRawDataset, 695 pCalBChans, numPiers, 696 pdGainOverlap_t2, 697 &tMinCalPower, gainBoundaries, 698 pdadcValues, numXpdGain); 699 700 if ((i == 0) || AR_SREV_OWL_20_OR_LATER(ah)) { 701 /* 702 * Note the pdadc table may not start at 0 dBm power, could be 703 * negative or greater than 0. Need to offset the power 704 * values by the amount of minPower for griffin 705 */ 706 ar5416SetGainBoundariesClosedLoop(ah, i, pdGainOverlap_t2, gainBoundaries); 707 } 708 709 /* Write the power values into the baseband power table */ 710 ar5416WritePdadcValues(ah, i, pdadcValues); 711 } 712 } 713 *pTxPowerIndexOffset = 0; 714 715 return AH_TRUE; 716} 717 718static void 719ar9285GetGainBoundariesAndPdadcs(struct ath_hal *ah, 720 const struct ieee80211_channel *chan, 721 CAL_DATA_PER_FREQ_4K *pRawDataSet, 722 uint8_t * bChans, uint16_t availPiers, 723 uint16_t tPdGainOverlap, int16_t *pMinCalPower, uint16_t * pPdGainBoundaries, 724 uint8_t * pPDADCValues, uint16_t numXpdGains) 725{ 726 727 int i, j, k; 728 int16_t ss; /* potentially -ve index for taking care of pdGainOverlap */ 729 uint16_t idxL, idxR, numPiers; /* Pier indexes */ 730 731 /* filled out Vpd table for all pdGains (chanL) */ 732 static uint8_t vpdTableL[AR5416_4K_NUM_PD_GAINS][AR5416_MAX_PWR_RANGE_IN_HALF_DB]; 733 734 /* filled out Vpd table for all pdGains (chanR) */ 735 static uint8_t vpdTableR[AR5416_4K_NUM_PD_GAINS][AR5416_MAX_PWR_RANGE_IN_HALF_DB]; 736 737 /* filled out Vpd table for all pdGains (interpolated) */ 738 static uint8_t vpdTableI[AR5416_4K_NUM_PD_GAINS][AR5416_MAX_PWR_RANGE_IN_HALF_DB]; 739 740 uint8_t *pVpdL, *pVpdR, *pPwrL, *pPwrR; 741 uint8_t minPwrT4[AR5416_4K_NUM_PD_GAINS]; 742 uint8_t maxPwrT4[AR5416_4K_NUM_PD_GAINS]; 743 int16_t vpdStep; 744 int16_t tmpVal; 745 uint16_t sizeCurrVpdTable, maxIndex, tgtIndex; 746 HAL_BOOL match; 747 int16_t minDelta = 0; 748 CHAN_CENTERS centers; 749 750 ar5416GetChannelCenters(ah, chan, ¢ers); 751 752 /* Trim numPiers for the number of populated channel Piers */ 753 for (numPiers = 0; numPiers < availPiers; numPiers++) { 754 if (bChans[numPiers] == AR5416_BCHAN_UNUSED) { 755 break; 756 } 757 } 758 759 /* Find pier indexes around the current channel */ 760 match = ath_ee_getLowerUpperIndex((uint8_t)FREQ2FBIN(centers.synth_center, 761 IEEE80211_IS_CHAN_2GHZ(chan)), bChans, numPiers, &idxL, &idxR); 762 763 if (match) { 764 /* Directly fill both vpd tables from the matching index */ 765 for (i = 0; i < numXpdGains; i++) { 766 minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0]; 767 maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4]; 768 ath_ee_FillVpdTable(minPwrT4[i], maxPwrT4[i], 769 pRawDataSet[idxL].pwrPdg[i], 770 pRawDataSet[idxL].vpdPdg[i], 771 AR5416_PD_GAIN_ICEPTS, vpdTableI[i]); 772 } 773 } else { 774 for (i = 0; i < numXpdGains; i++) { 775 pVpdL = pRawDataSet[idxL].vpdPdg[i]; 776 pPwrL = pRawDataSet[idxL].pwrPdg[i]; 777 pVpdR = pRawDataSet[idxR].vpdPdg[i]; 778 pPwrR = pRawDataSet[idxR].pwrPdg[i]; 779 780 /* Start Vpd interpolation from the max of the minimum powers */ 781 minPwrT4[i] = AH_MAX(pPwrL[0], pPwrR[0]); 782 783 /* End Vpd interpolation from the min of the max powers */ 784 maxPwrT4[i] = AH_MIN(pPwrL[AR5416_PD_GAIN_ICEPTS - 1], pPwrR[AR5416_PD_GAIN_ICEPTS - 1]); 785 HALASSERT(maxPwrT4[i] > minPwrT4[i]); 786 787 /* Fill pier Vpds */ 788 ath_ee_FillVpdTable(minPwrT4[i], maxPwrT4[i], pPwrL, pVpdL, 789 AR5416_PD_GAIN_ICEPTS, vpdTableL[i]); 790 ath_ee_FillVpdTable(minPwrT4[i], maxPwrT4[i], pPwrR, pVpdR, 791 AR5416_PD_GAIN_ICEPTS, vpdTableR[i]); 792 793 /* Interpolate the final vpd */ 794 for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) { 795 vpdTableI[i][j] = (uint8_t)(ath_ee_interpolate((uint16_t)FREQ2FBIN(centers.synth_center, 796 IEEE80211_IS_CHAN_2GHZ(chan)), 797 bChans[idxL], bChans[idxR], vpdTableL[i][j], vpdTableR[i][j])); 798 } 799 } 800 } 801 *pMinCalPower = (int16_t)(minPwrT4[0] / 2); 802 803 k = 0; /* index for the final table */ 804 for (i = 0; i < numXpdGains; i++) { 805 if (i == (numXpdGains - 1)) { 806 pPdGainBoundaries[i] = (uint16_t)(maxPwrT4[i] / 2); 807 } else { 808 pPdGainBoundaries[i] = (uint16_t)((maxPwrT4[i] + minPwrT4[i+1]) / 4); 809 } 810 811 pPdGainBoundaries[i] = (uint16_t)AH_MIN(AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]); 812 813 /* NB: only applies to owl 1.0 */ 814 if ((i == 0) && !AR_SREV_OWL_20_OR_LATER(ah) ) { 815 /* 816 * fix the gain delta, but get a delta that can be applied to min to 817 * keep the upper power values accurate, don't think max needs to 818 * be adjusted because should not be at that area of the table? 819 */ 820 minDelta = pPdGainBoundaries[0] - 23; 821 pPdGainBoundaries[0] = 23; 822 } 823 else { 824 minDelta = 0; 825 } 826 827 /* Find starting index for this pdGain */ 828 if (i == 0) { 829 if (AR_SREV_MERLIN_20_OR_LATER(ah)) 830 ss = (int16_t)(0 - (minPwrT4[i] / 2)); 831 else 832 ss = 0; /* for the first pdGain, start from index 0 */ 833 } else { 834 /* need overlap entries extrapolated below. */ 835 ss = (int16_t)((pPdGainBoundaries[i-1] - (minPwrT4[i] / 2)) - tPdGainOverlap + 1 + minDelta); 836 } 837 vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]); 838 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep); 839 /* 840 *-ve ss indicates need to extrapolate data below for this pdGain 841 */ 842 while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) { 843 tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep); 844 pPDADCValues[k++] = (uint8_t)((tmpVal < 0) ? 0 : tmpVal); 845 ss++; 846 } 847 848 sizeCurrVpdTable = (uint8_t)((maxPwrT4[i] - minPwrT4[i]) / 2 +1); 849 tgtIndex = (uint8_t)(pPdGainBoundaries[i] + tPdGainOverlap - (minPwrT4[i] / 2)); 850 maxIndex = (tgtIndex < sizeCurrVpdTable) ? tgtIndex : sizeCurrVpdTable; 851 852 while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) { 853 pPDADCValues[k++] = vpdTableI[i][ss++]; 854 } 855 856 vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] - vpdTableI[i][sizeCurrVpdTable - 2]); 857 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep); 858 /* 859 * for last gain, pdGainBoundary == Pmax_t2, so will 860 * have to extrapolate 861 */ 862 if (tgtIndex >= maxIndex) { /* need to extrapolate above */ 863 while ((ss <= tgtIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) { 864 tmpVal = (int16_t)((vpdTableI[i][sizeCurrVpdTable - 1] + 865 (ss - maxIndex +1) * vpdStep)); 866 pPDADCValues[k++] = (uint8_t)((tmpVal > 255) ? 255 : tmpVal); 867 ss++; 868 } 869 } /* extrapolated above */ 870 } /* for all pdGainUsed */ 871 872 /* Fill out pdGainBoundaries - only up to 2 allowed here, but hardware allows up to 4 */ 873 while (i < AR5416_PD_GAINS_IN_MASK) { 874 pPdGainBoundaries[i] = pPdGainBoundaries[i-1]; 875 i++; 876 } 877 878 while (k < AR5416_NUM_PDADC_VALUES) { 879 pPDADCValues[k] = pPDADCValues[k-1]; 880 k++; 881 } 882 return; 883} 884