ar9285_reset.c revision 220590
1139749Simp/* 265176Sdfr * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 365176Sdfr * Copyright (c) 2002-2008 Atheros Communications, Inc. 465176Sdfr * 565176Sdfr * Permission to use, copy, modify, and/or distribute this software for any 665176Sdfr * purpose with or without fee is hereby granted, provided that the above 765176Sdfr * copyright notice and this permission notice appear in all copies. 865176Sdfr * 965176Sdfr * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 1065176Sdfr * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 1165176Sdfr * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 1265176Sdfr * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 1365176Sdfr * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 1465176Sdfr * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 1565176Sdfr * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 1665176Sdfr * 1765176Sdfr * $FreeBSD: head/sys/dev/ath/ath_hal/ar9002/ar9285_reset.c 220590 2011-04-13 04:40:59Z adrian $ 1865176Sdfr */ 1965176Sdfr 2065176Sdfr/* 2165176Sdfr * This is almost the same as ar5416_reset.c but uses the v4k EEPROM and 2265176Sdfr * supports only 2Ghz operation. 2365176Sdfr */ 2465176Sdfr 2565176Sdfr#include "opt_ah.h" 2665176Sdfr 2765176Sdfr#include "ah.h" 2865176Sdfr#include "ah_internal.h" 2965176Sdfr#include "ah_devid.h" 30279470Srstone 31145026Simp#include "ah_eeprom_v14.h" 32279470Srstone#include "ah_eeprom_v4k.h" 3365176Sdfr 3465176Sdfr#include "ar9002/ar9285.h" 3565176Sdfr#include "ar5416/ar5416.h" 36145019Simp#include "ar5416/ar5416reg.h" 37145019Simp#include "ar5416/ar5416phy.h" 38145019Simp#include "ar9002/ar9002phy.h" 39145019Simp#include "ar9002/ar9285phy.h" 40145019Simp 41145019Simp/* Eeprom versioning macros. Returns true if the version is equal or newer than the ver specified */ 42145019Simp#define EEP_MINOR(_ah) \ 43145019Simp (AH_PRIVATE(_ah)->ah_eeversion & AR5416_EEP_VER_MINOR_MASK) 4465176Sdfr#define IS_EEP_MINOR_V2(_ah) (EEP_MINOR(_ah) >= AR5416_EEP_MINOR_VER_2) 4565176Sdfr#define IS_EEP_MINOR_V3(_ah) (EEP_MINOR(_ah) >= AR5416_EEP_MINOR_VER_3) 4665176Sdfr 4765176Sdfr/* Additional Time delay to wait after activiting the Base band */ 4865176Sdfr#define BASE_ACTIVATE_DELAY 100 /* 100 usec */ 4965176Sdfr#define PLL_SETTLE_DELAY 300 /* 300 usec */ 5065176Sdfr#define RTC_PLL_SETTLE_DELAY 1000 /* 1 ms */ 5165176Sdfr 52279470Srstonestatic HAL_BOOL ar9285SetPowerPerRateTable(struct ath_hal *ah, 53279470Srstone struct ar5416eeprom_4k *pEepData, 54279470Srstone const struct ieee80211_channel *chan, int16_t *ratesArray, 55279470Srstone uint16_t cfgCtl, uint16_t AntennaReduction, 56279470Srstone uint16_t twiceMaxRegulatoryPower, 57279470Srstone uint16_t powerLimit); 58279470Srstonestatic HAL_BOOL ar9285SetPowerCalTable(struct ath_hal *ah, 59279470Srstone struct ar5416eeprom_4k *pEepData, 6065176Sdfr const struct ieee80211_channel *chan, 6165176Sdfr int16_t *pTxPowerIndexOffset); 6265176Sdfrstatic void ar9285GetGainBoundariesAndPdadcs(struct ath_hal *ah, 6365176Sdfr const struct ieee80211_channel *chan, CAL_DATA_PER_FREQ_4K *pRawDataSet, 6465176Sdfr uint8_t * bChans, uint16_t availPiers, 6565176Sdfr uint16_t tPdGainOverlap, int16_t *pMinCalPower, 6665176Sdfr uint16_t * pPdGainBoundaries, uint8_t * pPDADCValues, 6765176Sdfr uint16_t numXpdGains); 6869480Sgallatinstatic uint16_t ar9285GetMaxEdgePower(uint16_t, CAL_CTL_EDGES *); 6969480Sgallatin 7069480SgallatinHAL_BOOL 7169480Sgallatinar9285SetTransmitPower(struct ath_hal *ah, 7265176Sdfr const struct ieee80211_channel *chan, uint16_t *rfXpdGain) 7365176Sdfr{ 7465176Sdfr#define POW_SM(_r, _s) (((_r) & 0x3f) << (_s)) 7565176Sdfr#define N(a) (sizeof (a) / sizeof (a[0])) 7665176Sdfr 7765176Sdfr MODAL_EEP4K_HEADER *pModal; 7865176Sdfr struct ath_hal_5212 *ahp = AH5212(ah); 7965176Sdfr int16_t ratesArray[Ar5416RateSize]; 8065176Sdfr int16_t txPowerIndexOffset = 0; 8165176Sdfr uint8_t ht40PowerIncForPdadc = 2; 8265176Sdfr int i; 8365176Sdfr 8469480Sgallatin uint16_t cfgCtl; 8569480Sgallatin uint16_t powerLimit; 8669480Sgallatin uint16_t twiceAntennaReduction; 8769480Sgallatin uint16_t twiceMaxRegulatoryPower; 8865176Sdfr int16_t maxPower; 8965176Sdfr HAL_EEPROM_v4k *ee = AH_PRIVATE(ah)->ah_eeprom; 9065176Sdfr struct ar5416eeprom_4k *pEepData = &ee->ee_base; 9167222Simp 9267222Simp HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER14_1); 9367222Simp 9467222Simp /* Setup info for the actual eeprom */ 9567222Simp OS_MEMZERO(ratesArray, sizeof(ratesArray)); 9667222Simp cfgCtl = ath_hal_getctl(ah, chan); 97164067Sjhb powerLimit = chan->ic_maxregpower * 2; 98164067Sjhb twiceAntennaReduction = chan->ic_maxantgain; 99164067Sjhb twiceMaxRegulatoryPower = AH_MIN(MAX_RATE_POWER, AH_PRIVATE(ah)->ah_powerLimit); 100145026Simp pModal = &pEepData->modalHeader; 101164264Sjhb HALDEBUG(ah, HAL_DEBUG_RESET, "%s Channel=%u CfgCtl=%u\n", 102164264Sjhb __func__,chan->ic_freq, cfgCtl ); 103164264Sjhb 104164264Sjhb if (IS_EEP_MINOR_V2(ah)) { 105164264Sjhb ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc; 106164264Sjhb } 107164264Sjhb 108164264Sjhb if (!ar9285SetPowerPerRateTable(ah, pEepData, chan, 109164264Sjhb &ratesArray[0],cfgCtl, 110164264Sjhb twiceAntennaReduction, 111164264Sjhb twiceMaxRegulatoryPower, powerLimit)) { 112164264Sjhb HALDEBUG(ah, HAL_DEBUG_ANY, 113164264Sjhb "%s: unable to set tx power per rate table\n", __func__); 114164264Sjhb return AH_FALSE; 115164264Sjhb } 116164264Sjhb 117164264Sjhb if (!ar9285SetPowerCalTable(ah, pEepData, chan, &txPowerIndexOffset)) { 118169221Sjhb HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unable to set power table\n", 119169221Sjhb __func__); 120164264Sjhb return AH_FALSE; 121164264Sjhb } 122164264Sjhb 123164264Sjhb maxPower = AH_MAX(ratesArray[rate6mb], ratesArray[rateHt20_0]); 124164264Sjhb maxPower = AH_MAX(maxPower, ratesArray[rate1l]); 125164264Sjhb 126164264Sjhb if (IEEE80211_IS_CHAN_HT40(chan)) { 127164264Sjhb maxPower = AH_MAX(maxPower, ratesArray[rateHt40_0]); 128164264Sjhb } 129164264Sjhb 130164264Sjhb ahp->ah_tx6PowerInHalfDbm = maxPower; 131164264Sjhb AH_PRIVATE(ah)->ah_maxPowerLevel = maxPower; 132164264Sjhb ahp->ah_txPowerIndexOffset = txPowerIndexOffset; 133164264Sjhb 134164264Sjhb /* 135164264Sjhb * txPowerIndexOffset is set by the SetPowerTable() call - 136164264Sjhb * adjust the rate table (0 offset if rates EEPROM not loaded) 137164264Sjhb */ 138169221Sjhb for (i = 0; i < N(ratesArray); i++) { 139166176Sjhb ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]); 140169221Sjhb /* -5 dBm offset for Merlin and later; this includes Kite */ 141166176Sjhb ratesArray[i] -= AR5416_PWR_TABLE_OFFSET_DB * 2; 142166176Sjhb if (ratesArray[i] > AR5416_MAX_RATE_POWER) 143166176Sjhb ratesArray[i] = AR5416_MAX_RATE_POWER; 144166176Sjhb if (ratesArray[i] < 0) 145166176Sjhb ratesArray[i] = 0; 146166176Sjhb } 147169221Sjhb 148169221Sjhb#ifdef AH_EEPROM_DUMP 149164264Sjhb ar5416PrintPowerPerRate(ah, ratesArray); 150169221Sjhb#endif 151164264Sjhb 152164264Sjhb /* Write the OFDM power per rate set */ 153164264Sjhb OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE1, 154169221Sjhb POW_SM(ratesArray[rate18mb], 24) 155169221Sjhb | POW_SM(ratesArray[rate12mb], 16) 156164264Sjhb | POW_SM(ratesArray[rate9mb], 8) 157211430Sjhb | POW_SM(ratesArray[rate6mb], 0) 158211430Sjhb ); 159211430Sjhb OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE2, 160211430Sjhb POW_SM(ratesArray[rate54mb], 24) 161211430Sjhb | POW_SM(ratesArray[rate48mb], 16) 162211430Sjhb | POW_SM(ratesArray[rate36mb], 8) 163211430Sjhb | POW_SM(ratesArray[rate24mb], 0) 164211430Sjhb ); 165211430Sjhb 166211430Sjhb /* Write the CCK power per rate set */ 167279470Srstone OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE3, 168279470Srstone POW_SM(ratesArray[rate2s], 24) 169279470Srstone | POW_SM(ratesArray[rate2l], 16) 170279470Srstone | POW_SM(ratesArray[rateXr], 8) /* XR target power */ 171279470Srstone | POW_SM(ratesArray[rate1l], 0) 172279472Srstone ); 173279472Srstone OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE4, 174279470Srstone POW_SM(ratesArray[rate11s], 24) 175279470Srstone | POW_SM(ratesArray[rate11l], 16) 176279470Srstone | POW_SM(ratesArray[rate5_5s], 8) 177279470Srstone | POW_SM(ratesArray[rate5_5l], 0) 178279470Srstone ); 179279470Srstone HALDEBUG(ah, HAL_DEBUG_RESET, 180279470Srstone "%s AR_PHY_POWER_TX_RATE3=0x%x AR_PHY_POWER_TX_RATE4=0x%x\n", 181279470Srstone __func__, OS_REG_READ(ah,AR_PHY_POWER_TX_RATE3), 182279470Srstone OS_REG_READ(ah,AR_PHY_POWER_TX_RATE4)); 183279470Srstone 184279470Srstone /* Write the HT20 power per rate set */ 185 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE5, 186 POW_SM(ratesArray[rateHt20_3], 24) 187 | POW_SM(ratesArray[rateHt20_2], 16) 188 | POW_SM(ratesArray[rateHt20_1], 8) 189 | POW_SM(ratesArray[rateHt20_0], 0) 190 ); 191 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE6, 192 POW_SM(ratesArray[rateHt20_7], 24) 193 | POW_SM(ratesArray[rateHt20_6], 16) 194 | POW_SM(ratesArray[rateHt20_5], 8) 195 | POW_SM(ratesArray[rateHt20_4], 0) 196 ); 197 198 if (IEEE80211_IS_CHAN_HT40(chan)) { 199 /* Write the HT40 power per rate set */ 200 /* Correct PAR difference between HT40 and HT20/LEGACY */ 201 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE7, 202 POW_SM(ratesArray[rateHt40_3] + ht40PowerIncForPdadc, 24) 203 | POW_SM(ratesArray[rateHt40_2] + ht40PowerIncForPdadc, 16) 204 | POW_SM(ratesArray[rateHt40_1] + ht40PowerIncForPdadc, 8) 205 | POW_SM(ratesArray[rateHt40_0] + ht40PowerIncForPdadc, 0) 206 ); 207 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE8, 208 POW_SM(ratesArray[rateHt40_7] + ht40PowerIncForPdadc, 24) 209 | POW_SM(ratesArray[rateHt40_6] + ht40PowerIncForPdadc, 16) 210 | POW_SM(ratesArray[rateHt40_5] + ht40PowerIncForPdadc, 8) 211 | POW_SM(ratesArray[rateHt40_4] + ht40PowerIncForPdadc, 0) 212 ); 213 /* Write the Dup/Ext 40 power per rate set */ 214 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE9, 215 POW_SM(ratesArray[rateExtOfdm], 24) 216 | POW_SM(ratesArray[rateExtCck], 16) 217 | POW_SM(ratesArray[rateDupOfdm], 8) 218 | POW_SM(ratesArray[rateDupCck], 0) 219 ); 220 } 221 222 return AH_TRUE; 223#undef POW_SM 224#undef N 225} 226 227static void 228ar9285SetBoardGain(struct ath_hal *ah, const MODAL_EEP4K_HEADER *pModal, 229 const struct ar5416eeprom_4k *eep, uint8_t txRxAttenLocal) 230{ 231 OS_REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0, 232 pModal->antCtrlChain[0]); 233 234 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0), 235 (OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0)) & 236 ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF | 237 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) | 238 SM(pModal->iqCalICh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) | 239 SM(pModal->iqCalQCh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF)); 240 241 if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= 242 AR5416_EEP_MINOR_VER_3) { 243 txRxAttenLocal = pModal->txRxAttenCh[0]; 244 245 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, 246 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, pModal->bswMargin[0]); 247 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, 248 AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]); 249 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, 250 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN, pModal->xatten2Margin[0]); 251 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, 252 AR_PHY_GAIN_2GHZ_XATTEN2_DB, pModal->xatten2Db[0]); 253 254 /* Set the block 1 value to block 0 value */ 255 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000, 256 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, 257 pModal->bswMargin[0]); 258 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000, 259 AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]); 260 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000, 261 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN, 262 pModal->xatten2Margin[0]); 263 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000, 264 AR_PHY_GAIN_2GHZ_XATTEN2_DB, pModal->xatten2Db[0]); 265 } 266 267 OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN, 268 AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal); 269 OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN, 270 AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]); 271 272 OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000, 273 AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal); 274 OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000, 275 AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]); 276} 277 278/* 279 * Read EEPROM header info and program the device for correct operation 280 * given the channel value. 281 */ 282HAL_BOOL 283ar9285SetBoardValues(struct ath_hal *ah, const struct ieee80211_channel *chan) 284{ 285 const HAL_EEPROM_v4k *ee = AH_PRIVATE(ah)->ah_eeprom; 286 const struct ar5416eeprom_4k *eep = &ee->ee_base; 287 const MODAL_EEP4K_HEADER *pModal; 288 uint8_t txRxAttenLocal; 289 uint8_t ob[5], db1[5], db2[5]; 290 uint8_t ant_div_control1, ant_div_control2; 291 uint32_t regVal; 292 293 pModal = &eep->modalHeader; 294 txRxAttenLocal = 23; 295 296 OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon); 297 298 /* Single chain for 4K EEPROM*/ 299 ar9285SetBoardGain(ah, pModal, eep, txRxAttenLocal); 300 301 /* Initialize Ant Diversity settings from EEPROM */ 302 if (pModal->version >= 3) { 303 ant_div_control1 = pModal->antdiv_ctl1; 304 ant_div_control2 = pModal->antdiv_ctl2; 305 306 regVal = OS_REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); 307 regVal &= (~(AR_PHY_9285_ANT_DIV_CTL_ALL)); 308 309 regVal |= SM(ant_div_control1, 310 AR_PHY_9285_ANT_DIV_CTL); 311 regVal |= SM(ant_div_control2, 312 AR_PHY_9285_ANT_DIV_ALT_LNACONF); 313 regVal |= SM((ant_div_control2 >> 2), 314 AR_PHY_9285_ANT_DIV_MAIN_LNACONF); 315 regVal |= SM((ant_div_control1 >> 1), 316 AR_PHY_9285_ANT_DIV_ALT_GAINTB); 317 regVal |= SM((ant_div_control1 >> 2), 318 AR_PHY_9285_ANT_DIV_MAIN_GAINTB); 319 320 OS_REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regVal); 321 regVal = OS_REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); 322 regVal = OS_REG_READ(ah, AR_PHY_CCK_DETECT); 323 regVal &= (~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV); 324 regVal |= SM((ant_div_control1 >> 3), 325 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV); 326 327 OS_REG_WRITE(ah, AR_PHY_CCK_DETECT, regVal); 328 regVal = OS_REG_READ(ah, AR_PHY_CCK_DETECT); 329 } 330 331 if (pModal->version >= 2) { 332 ob[0] = pModal->ob_0; 333 ob[1] = pModal->ob_1; 334 ob[2] = pModal->ob_2; 335 ob[3] = pModal->ob_3; 336 ob[4] = pModal->ob_4; 337 338 db1[0] = pModal->db1_0; 339 db1[1] = pModal->db1_1; 340 db1[2] = pModal->db1_2; 341 db1[3] = pModal->db1_3; 342 db1[4] = pModal->db1_4; 343 344 db2[0] = pModal->db2_0; 345 db2[1] = pModal->db2_1; 346 db2[2] = pModal->db2_2; 347 db2[3] = pModal->db2_3; 348 db2[4] = pModal->db2_4; 349 } else if (pModal->version == 1) { 350 ob[0] = pModal->ob_0; 351 ob[1] = ob[2] = ob[3] = ob[4] = pModal->ob_1; 352 db1[0] = pModal->db1_0; 353 db1[1] = db1[2] = db1[3] = db1[4] = pModal->db1_1; 354 db2[0] = pModal->db2_0; 355 db2[1] = db2[2] = db2[3] = db2[4] = pModal->db2_1; 356 } else { 357 int i; 358 359 for (i = 0; i < 5; i++) { 360 ob[i] = pModal->ob_0; 361 db1[i] = pModal->db1_0; 362 db2[i] = pModal->db1_0; 363 } 364 } 365 366 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_OB_0, ob[0]); 367 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_OB_1, ob[1]); 368 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_OB_2, ob[2]); 369 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_OB_3, ob[3]); 370 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_OB_4, ob[4]); 371 372 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_DB1_0, db1[0]); 373 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_DB1_1, db1[1]); 374 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_DB1_2, db1[2]); 375 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G4, AR9285_AN_RF2G4_DB1_3, db1[3]); 376 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G4, AR9285_AN_RF2G4_DB1_4, db1[4]); 377 378 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G4, AR9285_AN_RF2G4_DB2_0, db2[0]); 379 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G4, AR9285_AN_RF2G4_DB2_1, db2[1]); 380 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G4, AR9285_AN_RF2G4_DB2_2, db2[2]); 381 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G4, AR9285_AN_RF2G4_DB2_3, db2[3]); 382 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G4, AR9285_AN_RF2G4_DB2_4, db2[4]); 383 384 OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH, 385 pModal->switchSettling); 386 OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC, 387 pModal->adcDesiredSize); 388 389 OS_REG_WRITE(ah, AR_PHY_RF_CTL4, 390 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF) | 391 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF) | 392 SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON) | 393 SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON)); 394 395 OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON, 396 pModal->txEndToRxOn); 397 398 OS_REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62, 399 pModal->thresh62); 400 OS_REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62, 401 pModal->thresh62); 402 403 if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= 404 AR5416_EEP_MINOR_VER_2) { 405 OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_FRAME_TO_DATA_START, 406 pModal->txFrameToDataStart); 407 OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_FRAME_TO_PA_ON, 408 pModal->txFrameToPaOn); 409 } 410 411 if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= 412 AR5416_EEP_MINOR_VER_3) { 413 if (IEEE80211_IS_CHAN_HT40(chan)) 414 OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, 415 AR_PHY_SETTLING_SWITCH, pModal->swSettleHt40); 416 } 417 418 /* 419 * Program the CCK TX gain factor appropriately if needed. 420 * The AR9285/AR9271 has a non-constant PA tx gain behaviour 421 * for CCK versus OFDM rates; other chips deal with this 422 * differently. 423 * 424 * The mask/shift/multiply hackery is done so place the same 425 * value (bb_desired_scale) into multiple 5-bit fields. 426 * For example, AR_PHY_TX_PWRCTRL9 has bb_desired_scale written 427 * to three fields: (0..4), (5..9) and (10..14). 428 */ 429 if (AR_SREV_9271(ah) || AR_SREV_KITE(ah)) { 430 uint8_t bb_desired_scale = (pModal->bb_scale_smrt_antenna & EEP_4K_BB_DESIRED_SCALE_MASK); 431 if ((eep->baseEepHeader.txGainType == 0) && (bb_desired_scale != 0)) { 432 uint32_t pwrctrl, mask, clr; 433 434 mask = (1<<0) | (1<<5) | (1<<10) | (1<<15) | (1<<20) | (1<<25); 435 pwrctrl = mask * bb_desired_scale; 436 clr = mask * 0x1f; 437 OS_REG_RMW(ah, AR_PHY_TX_PWRCTRL8, pwrctrl, clr); 438 OS_REG_RMW(ah, AR_PHY_TX_PWRCTRL10, pwrctrl, clr); 439 OS_REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL12, pwrctrl, clr); 440 441 mask = (1<<0) | (1<<5) | (1<<15); 442 pwrctrl = mask * bb_desired_scale; 443 clr = mask * 0x1f; 444 OS_REG_RMW(ah, AR_PHY_TX_PWRCTRL9, pwrctrl, clr); 445 446 mask = (1<<0) | (1<<5); 447 pwrctrl = mask * bb_desired_scale; 448 clr = mask * 0x1f; 449 OS_REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL11, pwrctrl, clr); 450 OS_REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL13, pwrctrl, clr); 451 } 452 } 453 454 return AH_TRUE; 455} 456 457/* 458 * Helper functions common for AP/CB/XB 459 */ 460 461static HAL_BOOL 462ar9285SetPowerPerRateTable(struct ath_hal *ah, struct ar5416eeprom_4k *pEepData, 463 const struct ieee80211_channel *chan, 464 int16_t *ratesArray, uint16_t cfgCtl, 465 uint16_t AntennaReduction, 466 uint16_t twiceMaxRegulatoryPower, 467 uint16_t powerLimit) 468{ 469#define N(a) (sizeof(a)/sizeof(a[0])) 470/* Local defines to distinguish between extension and control CTL's */ 471#define EXT_ADDITIVE (0x8000) 472#define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE) 473#define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE) 474 475 uint16_t twiceMaxEdgePower = AR5416_MAX_RATE_POWER; 476 int i; 477 int16_t twiceLargestAntenna; 478 CAL_CTL_DATA_4K *rep; 479 CAL_TARGET_POWER_LEG targetPowerOfdm, targetPowerCck = {0, {0, 0, 0, 0}}; 480 CAL_TARGET_POWER_LEG targetPowerOfdmExt = {0, {0, 0, 0, 0}}, targetPowerCckExt = {0, {0, 0, 0, 0}}; 481 CAL_TARGET_POWER_HT targetPowerHt20, targetPowerHt40 = {0, {0, 0, 0, 0}}; 482 int16_t scaledPower, minCtlPower; 483 484#define SUB_NUM_CTL_MODES_AT_2G_40 3 /* excluding HT40, EXT-OFDM, EXT-CCK */ 485 static const uint16_t ctlModesFor11g[] = { 486 CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40 487 }; 488 const uint16_t *pCtlMode; 489 uint16_t numCtlModes, ctlMode, freq; 490 CHAN_CENTERS centers; 491 492 ar5416GetChannelCenters(ah, chan, ¢ers); 493 494 /* Compute TxPower reduction due to Antenna Gain */ 495 496 twiceLargestAntenna = pEepData->modalHeader.antennaGainCh[0]; 497 twiceLargestAntenna = (int16_t)AH_MIN((AntennaReduction) - twiceLargestAntenna, 0); 498 499 /* XXX setup for 5212 use (really used?) */ 500 ath_hal_eepromSet(ah, AR_EEP_ANTGAINMAX_2, twiceLargestAntenna); 501 502 /* 503 * scaledPower is the minimum of the user input power level and 504 * the regulatory allowed power level 505 */ 506 scaledPower = AH_MIN(powerLimit, twiceMaxRegulatoryPower + twiceLargestAntenna); 507 508 /* Get target powers from EEPROM - our baseline for TX Power */ 509 /* Setup for CTL modes */ 510 numCtlModes = N(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40; /* CTL_11B, CTL_11G, CTL_2GHT20 */ 511 pCtlMode = ctlModesFor11g; 512 513 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPowerCck, 514 AR5416_4K_NUM_2G_CCK_TARGET_POWERS, &targetPowerCck, 4, AH_FALSE); 515 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower2G, 516 AR5416_4K_NUM_2G_20_TARGET_POWERS, &targetPowerOfdm, 4, AH_FALSE); 517 ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower2GHT20, 518 AR5416_4K_NUM_2G_20_TARGET_POWERS, &targetPowerHt20, 8, AH_FALSE); 519 520 if (IEEE80211_IS_CHAN_HT40(chan)) { 521 numCtlModes = N(ctlModesFor11g); /* All 2G CTL's */ 522 523 ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower2GHT40, 524 AR5416_4K_NUM_2G_40_TARGET_POWERS, &targetPowerHt40, 8, AH_TRUE); 525 /* Get target powers for extension channels */ 526 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPowerCck, 527 AR5416_4K_NUM_2G_CCK_TARGET_POWERS, &targetPowerCckExt, 4, AH_TRUE); 528 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower2G, 529 AR5416_4K_NUM_2G_20_TARGET_POWERS, &targetPowerOfdmExt, 4, AH_TRUE); 530 } 531 532 /* 533 * For MIMO, need to apply regulatory caps individually across dynamically 534 * running modes: CCK, OFDM, HT20, HT40 535 * 536 * The outer loop walks through each possible applicable runtime mode. 537 * The inner loop walks through each ctlIndex entry in EEPROM. 538 * The ctl value is encoded as [7:4] == test group, [3:0] == test mode. 539 * 540 */ 541 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) { 542 HAL_BOOL isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) || 543 (pCtlMode[ctlMode] == CTL_2GHT40); 544 if (isHt40CtlMode) { 545 freq = centers.ctl_center; 546 } else if (pCtlMode[ctlMode] & EXT_ADDITIVE) { 547 freq = centers.ext_center; 548 } else { 549 freq = centers.ctl_center; 550 } 551 552 /* walk through each CTL index stored in EEPROM */ 553 for (i = 0; (i < AR5416_4K_NUM_CTLS) && pEepData->ctlIndex[i]; i++) { 554 uint16_t twiceMinEdgePower; 555 556 /* compare test group from regulatory channel list with test mode from pCtlMode list */ 557 if ((((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == pEepData->ctlIndex[i]) || 558 (((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == 559 ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))) { 560 rep = &(pEepData->ctlData[i]); 561 twiceMinEdgePower = ar9285GetMaxEdgePower(freq, 562 rep->ctlEdges[ 563 owl_get_ntxchains(AH5416(ah)->ah_tx_chainmask) - 1]); 564 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) { 565 /* Find the minimum of all CTL edge powers that apply to this channel */ 566 twiceMaxEdgePower = AH_MIN(twiceMaxEdgePower, twiceMinEdgePower); 567 } else { 568 /* specific */ 569 twiceMaxEdgePower = twiceMinEdgePower; 570 break; 571 } 572 } 573 } 574 minCtlPower = (uint8_t)AH_MIN(twiceMaxEdgePower, scaledPower); 575 /* Apply ctl mode to correct target power set */ 576 switch(pCtlMode[ctlMode]) { 577 case CTL_11B: 578 for (i = 0; i < N(targetPowerCck.tPow2x); i++) { 579 targetPowerCck.tPow2x[i] = (uint8_t)AH_MIN(targetPowerCck.tPow2x[i], minCtlPower); 580 } 581 break; 582 case CTL_11A: 583 case CTL_11G: 584 for (i = 0; i < N(targetPowerOfdm.tPow2x); i++) { 585 targetPowerOfdm.tPow2x[i] = (uint8_t)AH_MIN(targetPowerOfdm.tPow2x[i], minCtlPower); 586 } 587 break; 588 case CTL_5GHT20: 589 case CTL_2GHT20: 590 for (i = 0; i < N(targetPowerHt20.tPow2x); i++) { 591 targetPowerHt20.tPow2x[i] = (uint8_t)AH_MIN(targetPowerHt20.tPow2x[i], minCtlPower); 592 } 593 break; 594 case CTL_11B_EXT: 595 targetPowerCckExt.tPow2x[0] = (uint8_t)AH_MIN(targetPowerCckExt.tPow2x[0], minCtlPower); 596 break; 597 case CTL_11G_EXT: 598 targetPowerOfdmExt.tPow2x[0] = (uint8_t)AH_MIN(targetPowerOfdmExt.tPow2x[0], minCtlPower); 599 break; 600 case CTL_5GHT40: 601 case CTL_2GHT40: 602 for (i = 0; i < N(targetPowerHt40.tPow2x); i++) { 603 targetPowerHt40.tPow2x[i] = (uint8_t)AH_MIN(targetPowerHt40.tPow2x[i], minCtlPower); 604 } 605 break; 606 default: 607 return AH_FALSE; 608 break; 609 } 610 } /* end ctl mode checking */ 611 612 /* Set rates Array from collected data */ 613 ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] = ratesArray[rate18mb] = ratesArray[rate24mb] = targetPowerOfdm.tPow2x[0]; 614 ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1]; 615 ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2]; 616 ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3]; 617 ratesArray[rateXr] = targetPowerOfdm.tPow2x[0]; 618 619 for (i = 0; i < N(targetPowerHt20.tPow2x); i++) { 620 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i]; 621 } 622 623 ratesArray[rate1l] = targetPowerCck.tPow2x[0]; 624 ratesArray[rate2s] = ratesArray[rate2l] = targetPowerCck.tPow2x[1]; 625 ratesArray[rate5_5s] = ratesArray[rate5_5l] = targetPowerCck.tPow2x[2]; 626 ratesArray[rate11s] = ratesArray[rate11l] = targetPowerCck.tPow2x[3]; 627 if (IEEE80211_IS_CHAN_HT40(chan)) { 628 for (i = 0; i < N(targetPowerHt40.tPow2x); i++) { 629 ratesArray[rateHt40_0 + i] = targetPowerHt40.tPow2x[i]; 630 } 631 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0]; 632 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0]; 633 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0]; 634 if (IEEE80211_IS_CHAN_2GHZ(chan)) { 635 ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0]; 636 } 637 } 638 return AH_TRUE; 639#undef EXT_ADDITIVE 640#undef CTL_11G_EXT 641#undef CTL_11B_EXT 642#undef SUB_NUM_CTL_MODES_AT_2G_40 643#undef N 644} 645 646/************************************************************************** 647 * fbin2freq 648 * 649 * Get channel value from binary representation held in eeprom 650 * RETURNS: the frequency in MHz 651 */ 652static uint16_t 653fbin2freq(uint8_t fbin) 654{ 655 /* 656 * Reserved value 0xFF provides an empty definition both as 657 * an fbin and as a frequency - do not convert 658 */ 659 if (fbin == AR5416_BCHAN_UNUSED) { 660 return fbin; 661 } 662 663 return (uint16_t)(2300 + fbin); 664} 665 666/* 667 * XXX almost the same as ar5416GetMaxEdgePower. 668 */ 669static uint16_t 670ar9285GetMaxEdgePower(uint16_t freq, CAL_CTL_EDGES *pRdEdgesPower) 671{ 672 uint16_t twiceMaxEdgePower = AR5416_MAX_RATE_POWER; 673 int i; 674 675 /* Get the edge power */ 676 for (i = 0; (i < AR5416_NUM_BAND_EDGES) && (pRdEdgesPower[i].bChannel != AR5416_BCHAN_UNUSED) ; i++) { 677 /* 678 * If there's an exact channel match or an inband flag set 679 * on the lower channel use the given rdEdgePower 680 */ 681 if (freq == fbin2freq(pRdEdgesPower[i].bChannel)) { 682 twiceMaxEdgePower = MS(pRdEdgesPower[i].tPowerFlag, CAL_CTL_EDGES_POWER); 683 break; 684 } else if ((i > 0) && (freq < fbin2freq(pRdEdgesPower[i].bChannel))) { 685 if (fbin2freq(pRdEdgesPower[i - 1].bChannel) < freq && (pRdEdgesPower[i - 1].tPowerFlag & CAL_CTL_EDGES_FLAG) != 0) { 686 twiceMaxEdgePower = MS(pRdEdgesPower[i - 1].tPowerFlag, CAL_CTL_EDGES_POWER); 687 } 688 /* Leave loop - no more affecting edges possible in this monotonic increasing list */ 689 break; 690 } 691 } 692 HALASSERT(twiceMaxEdgePower > 0); 693 return twiceMaxEdgePower; 694} 695 696 697 698static HAL_BOOL 699ar9285SetPowerCalTable(struct ath_hal *ah, struct ar5416eeprom_4k *pEepData, 700 const struct ieee80211_channel *chan, int16_t *pTxPowerIndexOffset) 701{ 702 CAL_DATA_PER_FREQ_4K *pRawDataset; 703 uint8_t *pCalBChans = AH_NULL; 704 uint16_t pdGainOverlap_t2; 705 static uint8_t pdadcValues[AR5416_NUM_PDADC_VALUES]; 706 uint16_t gainBoundaries[AR5416_PD_GAINS_IN_MASK]; 707 uint16_t numPiers, i; 708 int16_t tMinCalPower; 709 uint16_t numXpdGain, xpdMask; 710 uint16_t xpdGainValues[4]; /* v4k eeprom has 2; the other two stay 0 */ 711 uint32_t regChainOffset; 712 713 OS_MEMZERO(xpdGainValues, sizeof(xpdGainValues)); 714 715 xpdMask = pEepData->modalHeader.xpdGain; 716 717 if (IS_EEP_MINOR_V2(ah)) { 718 pdGainOverlap_t2 = pEepData->modalHeader.pdGainOverlap; 719 } else { 720 pdGainOverlap_t2 = (uint16_t)(MS(OS_REG_READ(ah, AR_PHY_TPCRG5), AR_PHY_TPCRG5_PD_GAIN_OVERLAP)); 721 } 722 723 pCalBChans = pEepData->calFreqPier2G; 724 numPiers = AR5416_4K_NUM_2G_CAL_PIERS; 725 numXpdGain = 0; 726 727 /* Calculate the value of xpdgains from the xpdGain Mask */ 728 for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) { 729 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) { 730 if (numXpdGain >= AR5416_4K_NUM_PD_GAINS) { 731 HALASSERT(0); 732 break; 733 } 734 xpdGainValues[numXpdGain] = (uint16_t)(AR5416_PD_GAINS_IN_MASK - i); 735 numXpdGain++; 736 } 737 } 738 739 /* Write the detector gain biases and their number */ 740 ar5416WriteDetectorGainBiases(ah, numXpdGain, xpdGainValues); 741 742 for (i = 0; i < AR5416_MAX_CHAINS; i++) { 743 regChainOffset = ar5416GetRegChainOffset(ah, i); 744 if (pEepData->baseEepHeader.txMask & (1 << i)) { 745 pRawDataset = pEepData->calPierData2G[i]; 746 747 ar9285GetGainBoundariesAndPdadcs(ah, chan, pRawDataset, 748 pCalBChans, numPiers, 749 pdGainOverlap_t2, 750 &tMinCalPower, gainBoundaries, 751 pdadcValues, numXpdGain); 752 753 if ((i == 0) || AR_SREV_OWL_20_OR_LATER(ah)) { 754 /* 755 * Note the pdadc table may not start at 0 dBm power, could be 756 * negative or greater than 0. Need to offset the power 757 * values by the amount of minPower for griffin 758 */ 759 ar5416SetGainBoundariesClosedLoop(ah, i, pdGainOverlap_t2, gainBoundaries); 760 } 761 762 /* Write the power values into the baseband power table */ 763 ar5416WritePdadcValues(ah, i, pdadcValues); 764 } 765 } 766 *pTxPowerIndexOffset = 0; 767 768 return AH_TRUE; 769} 770 771static void 772ar9285GetGainBoundariesAndPdadcs(struct ath_hal *ah, 773 const struct ieee80211_channel *chan, 774 CAL_DATA_PER_FREQ_4K *pRawDataSet, 775 uint8_t * bChans, uint16_t availPiers, 776 uint16_t tPdGainOverlap, int16_t *pMinCalPower, uint16_t * pPdGainBoundaries, 777 uint8_t * pPDADCValues, uint16_t numXpdGains) 778{ 779 780 int i, j, k; 781 int16_t ss; /* potentially -ve index for taking care of pdGainOverlap */ 782 uint16_t idxL, idxR, numPiers; /* Pier indexes */ 783 784 /* filled out Vpd table for all pdGains (chanL) */ 785 static uint8_t vpdTableL[AR5416_4K_NUM_PD_GAINS][AR5416_MAX_PWR_RANGE_IN_HALF_DB]; 786 787 /* filled out Vpd table for all pdGains (chanR) */ 788 static uint8_t vpdTableR[AR5416_4K_NUM_PD_GAINS][AR5416_MAX_PWR_RANGE_IN_HALF_DB]; 789 790 /* filled out Vpd table for all pdGains (interpolated) */ 791 static uint8_t vpdTableI[AR5416_4K_NUM_PD_GAINS][AR5416_MAX_PWR_RANGE_IN_HALF_DB]; 792 793 uint8_t *pVpdL, *pVpdR, *pPwrL, *pPwrR; 794 uint8_t minPwrT4[AR5416_4K_NUM_PD_GAINS]; 795 uint8_t maxPwrT4[AR5416_4K_NUM_PD_GAINS]; 796 int16_t vpdStep; 797 int16_t tmpVal; 798 uint16_t sizeCurrVpdTable, maxIndex, tgtIndex; 799 HAL_BOOL match; 800 int16_t minDelta = 0; 801 CHAN_CENTERS centers; 802 803 ar5416GetChannelCenters(ah, chan, ¢ers); 804 805 /* Trim numPiers for the number of populated channel Piers */ 806 for (numPiers = 0; numPiers < availPiers; numPiers++) { 807 if (bChans[numPiers] == AR5416_BCHAN_UNUSED) { 808 break; 809 } 810 } 811 812 /* Find pier indexes around the current channel */ 813 match = ath_ee_getLowerUpperIndex((uint8_t)FREQ2FBIN(centers.synth_center, 814 IEEE80211_IS_CHAN_2GHZ(chan)), bChans, numPiers, &idxL, &idxR); 815 816 if (match) { 817 /* Directly fill both vpd tables from the matching index */ 818 for (i = 0; i < numXpdGains; i++) { 819 minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0]; 820 maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4]; 821 ath_ee_FillVpdTable(minPwrT4[i], maxPwrT4[i], 822 pRawDataSet[idxL].pwrPdg[i], 823 pRawDataSet[idxL].vpdPdg[i], 824 AR5416_PD_GAIN_ICEPTS, vpdTableI[i]); 825 } 826 } else { 827 for (i = 0; i < numXpdGains; i++) { 828 pVpdL = pRawDataSet[idxL].vpdPdg[i]; 829 pPwrL = pRawDataSet[idxL].pwrPdg[i]; 830 pVpdR = pRawDataSet[idxR].vpdPdg[i]; 831 pPwrR = pRawDataSet[idxR].pwrPdg[i]; 832 833 /* Start Vpd interpolation from the max of the minimum powers */ 834 minPwrT4[i] = AH_MAX(pPwrL[0], pPwrR[0]); 835 836 /* End Vpd interpolation from the min of the max powers */ 837 maxPwrT4[i] = AH_MIN(pPwrL[AR5416_PD_GAIN_ICEPTS - 1], pPwrR[AR5416_PD_GAIN_ICEPTS - 1]); 838 HALASSERT(maxPwrT4[i] > minPwrT4[i]); 839 840 /* Fill pier Vpds */ 841 ath_ee_FillVpdTable(minPwrT4[i], maxPwrT4[i], pPwrL, pVpdL, 842 AR5416_PD_GAIN_ICEPTS, vpdTableL[i]); 843 ath_ee_FillVpdTable(minPwrT4[i], maxPwrT4[i], pPwrR, pVpdR, 844 AR5416_PD_GAIN_ICEPTS, vpdTableR[i]); 845 846 /* Interpolate the final vpd */ 847 for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) { 848 vpdTableI[i][j] = (uint8_t)(ath_ee_interpolate((uint16_t)FREQ2FBIN(centers.synth_center, 849 IEEE80211_IS_CHAN_2GHZ(chan)), 850 bChans[idxL], bChans[idxR], vpdTableL[i][j], vpdTableR[i][j])); 851 } 852 } 853 } 854 *pMinCalPower = (int16_t)(minPwrT4[0] / 2); 855 856 k = 0; /* index for the final table */ 857 for (i = 0; i < numXpdGains; i++) { 858 if (i == (numXpdGains - 1)) { 859 pPdGainBoundaries[i] = (uint16_t)(maxPwrT4[i] / 2); 860 } else { 861 pPdGainBoundaries[i] = (uint16_t)((maxPwrT4[i] + minPwrT4[i+1]) / 4); 862 } 863 864 pPdGainBoundaries[i] = (uint16_t)AH_MIN(AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]); 865 866 /* NB: only applies to owl 1.0 */ 867 if ((i == 0) && !AR_SREV_OWL_20_OR_LATER(ah) ) { 868 /* 869 * fix the gain delta, but get a delta that can be applied to min to 870 * keep the upper power values accurate, don't think max needs to 871 * be adjusted because should not be at that area of the table? 872 */ 873 minDelta = pPdGainBoundaries[0] - 23; 874 pPdGainBoundaries[0] = 23; 875 } 876 else { 877 minDelta = 0; 878 } 879 880 /* Find starting index for this pdGain */ 881 if (i == 0) { 882 if (AR_SREV_MERLIN_20_OR_LATER(ah)) 883 ss = (int16_t)(0 - (minPwrT4[i] / 2)); 884 else 885 ss = 0; /* for the first pdGain, start from index 0 */ 886 } else { 887 /* need overlap entries extrapolated below. */ 888 ss = (int16_t)((pPdGainBoundaries[i-1] - (minPwrT4[i] / 2)) - tPdGainOverlap + 1 + minDelta); 889 } 890 vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]); 891 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep); 892 /* 893 *-ve ss indicates need to extrapolate data below for this pdGain 894 */ 895 while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) { 896 tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep); 897 pPDADCValues[k++] = (uint8_t)((tmpVal < 0) ? 0 : tmpVal); 898 ss++; 899 } 900 901 sizeCurrVpdTable = (uint8_t)((maxPwrT4[i] - minPwrT4[i]) / 2 +1); 902 tgtIndex = (uint8_t)(pPdGainBoundaries[i] + tPdGainOverlap - (minPwrT4[i] / 2)); 903 maxIndex = (tgtIndex < sizeCurrVpdTable) ? tgtIndex : sizeCurrVpdTable; 904 905 while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) { 906 pPDADCValues[k++] = vpdTableI[i][ss++]; 907 } 908 909 vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] - vpdTableI[i][sizeCurrVpdTable - 2]); 910 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep); 911 /* 912 * for last gain, pdGainBoundary == Pmax_t2, so will 913 * have to extrapolate 914 */ 915 if (tgtIndex >= maxIndex) { /* need to extrapolate above */ 916 while ((ss <= tgtIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) { 917 tmpVal = (int16_t)((vpdTableI[i][sizeCurrVpdTable - 1] + 918 (ss - maxIndex +1) * vpdStep)); 919 pPDADCValues[k++] = (uint8_t)((tmpVal > 255) ? 255 : tmpVal); 920 ss++; 921 } 922 } /* extrapolated above */ 923 } /* for all pdGainUsed */ 924 925 /* Fill out pdGainBoundaries - only up to 2 allowed here, but hardware allows up to 4 */ 926 while (i < AR5416_PD_GAINS_IN_MASK) { 927 pPdGainBoundaries[i] = pPdGainBoundaries[i-1]; 928 i++; 929 } 930 931 while (k < AR5416_NUM_PDADC_VALUES) { 932 pPDADCValues[k] = pPDADCValues[k-1]; 933 k++; 934 } 935 return; 936} 937