ar9285_reset.c revision 220539
1/* 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar9002/ar9285_reset.c 220539 2011-04-11 11:15:34Z adrian $ 18 */ 19 20/* 21 * This is almost the same as ar5416_reset.c but uses the v4k EEPROM and 22 * supports only 2Ghz operation. 23 */ 24 25#include "opt_ah.h" 26 27#include "ah.h" 28#include "ah_internal.h" 29#include "ah_devid.h" 30 31#include "ah_eeprom_v14.h" 32#include "ah_eeprom_v4k.h" 33 34#include "ar9002/ar9285.h" 35#include "ar5416/ar5416.h" 36#include "ar5416/ar5416reg.h" 37#include "ar5416/ar5416phy.h" 38 39#include "ar9002/ar9285phy.h" 40 41/* Eeprom versioning macros. Returns true if the version is equal or newer than the ver specified */ 42#define EEP_MINOR(_ah) \ 43 (AH_PRIVATE(_ah)->ah_eeversion & AR5416_EEP_VER_MINOR_MASK) 44#define IS_EEP_MINOR_V2(_ah) (EEP_MINOR(_ah) >= AR5416_EEP_MINOR_VER_2) 45#define IS_EEP_MINOR_V3(_ah) (EEP_MINOR(_ah) >= AR5416_EEP_MINOR_VER_3) 46 47/* Additional Time delay to wait after activiting the Base band */ 48#define BASE_ACTIVATE_DELAY 100 /* 100 usec */ 49#define PLL_SETTLE_DELAY 300 /* 300 usec */ 50#define RTC_PLL_SETTLE_DELAY 1000 /* 1 ms */ 51 52static HAL_BOOL ar9285SetPowerPerRateTable(struct ath_hal *ah, 53 struct ar5416eeprom_4k *pEepData, 54 const struct ieee80211_channel *chan, int16_t *ratesArray, 55 uint16_t cfgCtl, uint16_t AntennaReduction, 56 uint16_t twiceMaxRegulatoryPower, 57 uint16_t powerLimit); 58static HAL_BOOL ar9285SetPowerCalTable(struct ath_hal *ah, 59 struct ar5416eeprom_4k *pEepData, 60 const struct ieee80211_channel *chan, 61 int16_t *pTxPowerIndexOffset); 62static void ar9285GetGainBoundariesAndPdadcs(struct ath_hal *ah, 63 const struct ieee80211_channel *chan, CAL_DATA_PER_FREQ_4K *pRawDataSet, 64 uint8_t * bChans, uint16_t availPiers, 65 uint16_t tPdGainOverlap, int16_t *pMinCalPower, 66 uint16_t * pPdGainBoundaries, uint8_t * pPDADCValues, 67 uint16_t numXpdGains); 68static uint16_t ar9285GetMaxEdgePower(uint16_t, CAL_CTL_EDGES *); 69 70HAL_BOOL 71ar9285SetTransmitPower(struct ath_hal *ah, 72 const struct ieee80211_channel *chan, uint16_t *rfXpdGain) 73{ 74#define POW_SM(_r, _s) (((_r) & 0x3f) << (_s)) 75#define N(a) (sizeof (a) / sizeof (a[0])) 76 77 MODAL_EEP4K_HEADER *pModal; 78 struct ath_hal_5212 *ahp = AH5212(ah); 79 int16_t ratesArray[Ar5416RateSize]; 80 int16_t txPowerIndexOffset = 0; 81 uint8_t ht40PowerIncForPdadc = 2; 82 int i; 83 84 uint16_t cfgCtl; 85 uint16_t powerLimit; 86 uint16_t twiceAntennaReduction; 87 uint16_t twiceMaxRegulatoryPower; 88 int16_t maxPower; 89 HAL_EEPROM_v4k *ee = AH_PRIVATE(ah)->ah_eeprom; 90 struct ar5416eeprom_4k *pEepData = &ee->ee_base; 91 92 HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER14_1); 93 94 /* Setup info for the actual eeprom */ 95 OS_MEMZERO(ratesArray, sizeof(ratesArray)); 96 cfgCtl = ath_hal_getctl(ah, chan); 97 powerLimit = chan->ic_maxregpower * 2; 98 twiceAntennaReduction = chan->ic_maxantgain; 99 twiceMaxRegulatoryPower = AH_MIN(MAX_RATE_POWER, AH_PRIVATE(ah)->ah_powerLimit); 100 pModal = &pEepData->modalHeader; 101 HALDEBUG(ah, HAL_DEBUG_RESET, "%s Channel=%u CfgCtl=%u\n", 102 __func__,chan->ic_freq, cfgCtl ); 103 104 if (IS_EEP_MINOR_V2(ah)) { 105 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc; 106 } 107 108 if (!ar9285SetPowerPerRateTable(ah, pEepData, chan, 109 &ratesArray[0],cfgCtl, 110 twiceAntennaReduction, 111 twiceMaxRegulatoryPower, powerLimit)) { 112 HALDEBUG(ah, HAL_DEBUG_ANY, 113 "%s: unable to set tx power per rate table\n", __func__); 114 return AH_FALSE; 115 } 116 117 if (!ar9285SetPowerCalTable(ah, pEepData, chan, &txPowerIndexOffset)) { 118 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unable to set power table\n", 119 __func__); 120 return AH_FALSE; 121 } 122 123 maxPower = AH_MAX(ratesArray[rate6mb], ratesArray[rateHt20_0]); 124 maxPower = AH_MAX(maxPower, ratesArray[rate1l]); 125 126 if (IEEE80211_IS_CHAN_HT40(chan)) { 127 maxPower = AH_MAX(maxPower, ratesArray[rateHt40_0]); 128 } 129 130 ahp->ah_tx6PowerInHalfDbm = maxPower; 131 AH_PRIVATE(ah)->ah_maxPowerLevel = maxPower; 132 ahp->ah_txPowerIndexOffset = txPowerIndexOffset; 133 134 /* 135 * txPowerIndexOffset is set by the SetPowerTable() call - 136 * adjust the rate table (0 offset if rates EEPROM not loaded) 137 */ 138 for (i = 0; i < N(ratesArray); i++) { 139 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]); 140 /* -5 dBm offset for Merlin and later; this includes Kite */ 141 ratesArray[i] -= AR5416_PWR_TABLE_OFFSET_DB * 2; 142 if (ratesArray[i] > AR5416_MAX_RATE_POWER) 143 ratesArray[i] = AR5416_MAX_RATE_POWER; 144 if (ratesArray[i] < 0) 145 ratesArray[i] = 0; 146 } 147 148#ifdef AH_EEPROM_DUMP 149 ar5416PrintPowerPerRate(ah, ratesArray); 150#endif 151 152 /* Write the OFDM power per rate set */ 153 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE1, 154 POW_SM(ratesArray[rate18mb], 24) 155 | POW_SM(ratesArray[rate12mb], 16) 156 | POW_SM(ratesArray[rate9mb], 8) 157 | POW_SM(ratesArray[rate6mb], 0) 158 ); 159 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE2, 160 POW_SM(ratesArray[rate54mb], 24) 161 | POW_SM(ratesArray[rate48mb], 16) 162 | POW_SM(ratesArray[rate36mb], 8) 163 | POW_SM(ratesArray[rate24mb], 0) 164 ); 165 166 /* Write the CCK power per rate set */ 167 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE3, 168 POW_SM(ratesArray[rate2s], 24) 169 | POW_SM(ratesArray[rate2l], 16) 170 | POW_SM(ratesArray[rateXr], 8) /* XR target power */ 171 | POW_SM(ratesArray[rate1l], 0) 172 ); 173 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE4, 174 POW_SM(ratesArray[rate11s], 24) 175 | POW_SM(ratesArray[rate11l], 16) 176 | POW_SM(ratesArray[rate5_5s], 8) 177 | POW_SM(ratesArray[rate5_5l], 0) 178 ); 179 HALDEBUG(ah, HAL_DEBUG_RESET, 180 "%s AR_PHY_POWER_TX_RATE3=0x%x AR_PHY_POWER_TX_RATE4=0x%x\n", 181 __func__, OS_REG_READ(ah,AR_PHY_POWER_TX_RATE3), 182 OS_REG_READ(ah,AR_PHY_POWER_TX_RATE4)); 183 184 /* Write the HT20 power per rate set */ 185 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE5, 186 POW_SM(ratesArray[rateHt20_3], 24) 187 | POW_SM(ratesArray[rateHt20_2], 16) 188 | POW_SM(ratesArray[rateHt20_1], 8) 189 | POW_SM(ratesArray[rateHt20_0], 0) 190 ); 191 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE6, 192 POW_SM(ratesArray[rateHt20_7], 24) 193 | POW_SM(ratesArray[rateHt20_6], 16) 194 | POW_SM(ratesArray[rateHt20_5], 8) 195 | POW_SM(ratesArray[rateHt20_4], 0) 196 ); 197 198 if (IEEE80211_IS_CHAN_HT40(chan)) { 199 /* Write the HT40 power per rate set */ 200 /* Correct PAR difference between HT40 and HT20/LEGACY */ 201 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE7, 202 POW_SM(ratesArray[rateHt40_3] + ht40PowerIncForPdadc, 24) 203 | POW_SM(ratesArray[rateHt40_2] + ht40PowerIncForPdadc, 16) 204 | POW_SM(ratesArray[rateHt40_1] + ht40PowerIncForPdadc, 8) 205 | POW_SM(ratesArray[rateHt40_0] + ht40PowerIncForPdadc, 0) 206 ); 207 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE8, 208 POW_SM(ratesArray[rateHt40_7] + ht40PowerIncForPdadc, 24) 209 | POW_SM(ratesArray[rateHt40_6] + ht40PowerIncForPdadc, 16) 210 | POW_SM(ratesArray[rateHt40_5] + ht40PowerIncForPdadc, 8) 211 | POW_SM(ratesArray[rateHt40_4] + ht40PowerIncForPdadc, 0) 212 ); 213 /* Write the Dup/Ext 40 power per rate set */ 214 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE9, 215 POW_SM(ratesArray[rateExtOfdm], 24) 216 | POW_SM(ratesArray[rateExtCck], 16) 217 | POW_SM(ratesArray[rateDupOfdm], 8) 218 | POW_SM(ratesArray[rateDupCck], 0) 219 ); 220 } 221 222 return AH_TRUE; 223#undef POW_SM 224#undef N 225} 226 227static void 228ar9285SetBoardGain(struct ath_hal *ah, const MODAL_EEP4K_HEADER *pModal, 229 const struct ar5416eeprom_4k *eep, uint8_t txRxAttenLocal) 230{ 231 OS_REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0, 232 pModal->antCtrlChain[0]); 233 234 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0), 235 (OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0)) & 236 ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF | 237 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) | 238 SM(pModal->iqCalICh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) | 239 SM(pModal->iqCalQCh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF)); 240 241 if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= 242 AR5416_EEP_MINOR_VER_3) { 243 txRxAttenLocal = pModal->txRxAttenCh[0]; 244 245 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, 246 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, pModal->bswMargin[0]); 247 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, 248 AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]); 249 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, 250 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN, pModal->xatten2Margin[0]); 251 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, 252 AR_PHY_GAIN_2GHZ_XATTEN2_DB, pModal->xatten2Db[0]); 253 254 /* Set the block 1 value to block 0 value */ 255 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000, 256 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, 257 pModal->bswMargin[0]); 258 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000, 259 AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]); 260 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000, 261 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN, 262 pModal->xatten2Margin[0]); 263 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000, 264 AR_PHY_GAIN_2GHZ_XATTEN2_DB, pModal->xatten2Db[0]); 265 } 266 267 OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN, 268 AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal); 269 OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN, 270 AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]); 271 272 OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000, 273 AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal); 274 OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000, 275 AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]); 276} 277 278/* 279 * Read EEPROM header info and program the device for correct operation 280 * given the channel value. 281 */ 282HAL_BOOL 283ar9285SetBoardValues(struct ath_hal *ah, const struct ieee80211_channel *chan) 284{ 285 const HAL_EEPROM_v4k *ee = AH_PRIVATE(ah)->ah_eeprom; 286 const struct ar5416eeprom_4k *eep = &ee->ee_base; 287 const MODAL_EEP4K_HEADER *pModal; 288 uint8_t txRxAttenLocal; 289 uint8_t ob[5], db1[5], db2[5]; 290 uint8_t ant_div_control1, ant_div_control2; 291 uint32_t regVal; 292 293 pModal = &eep->modalHeader; 294 txRxAttenLocal = 23; 295 296 OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon); 297 298 /* Single chain for 4K EEPROM*/ 299 ar9285SetBoardGain(ah, pModal, eep, txRxAttenLocal); 300 301 /* Initialize Ant Diversity settings from EEPROM */ 302 if (pModal->version >= 3) { 303 ant_div_control1 = pModal->antdiv_ctl1; 304 ant_div_control2 = pModal->antdiv_ctl2; 305 306 regVal = OS_REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); 307 regVal &= (~(AR_PHY_9285_ANT_DIV_CTL_ALL)); 308 309 regVal |= SM(ant_div_control1, 310 AR_PHY_9285_ANT_DIV_CTL); 311 regVal |= SM(ant_div_control2, 312 AR_PHY_9285_ANT_DIV_ALT_LNACONF); 313 regVal |= SM((ant_div_control2 >> 2), 314 AR_PHY_9285_ANT_DIV_MAIN_LNACONF); 315 regVal |= SM((ant_div_control1 >> 1), 316 AR_PHY_9285_ANT_DIV_ALT_GAINTB); 317 regVal |= SM((ant_div_control1 >> 2), 318 AR_PHY_9285_ANT_DIV_MAIN_GAINTB); 319 320 OS_REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regVal); 321 regVal = OS_REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); 322 regVal = OS_REG_READ(ah, AR_PHY_CCK_DETECT); 323 regVal &= (~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV); 324 regVal |= SM((ant_div_control1 >> 3), 325 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV); 326 327 OS_REG_WRITE(ah, AR_PHY_CCK_DETECT, regVal); 328 regVal = OS_REG_READ(ah, AR_PHY_CCK_DETECT); 329 } 330 331 if (pModal->version >= 2) { 332 ob[0] = pModal->ob_0; 333 ob[1] = pModal->ob_1; 334 ob[2] = pModal->ob_2; 335 ob[3] = pModal->ob_3; 336 ob[4] = pModal->ob_4; 337 338 db1[0] = pModal->db1_0; 339 db1[1] = pModal->db1_1; 340 db1[2] = pModal->db1_2; 341 db1[3] = pModal->db1_3; 342 db1[4] = pModal->db1_4; 343 344 db2[0] = pModal->db2_0; 345 db2[1] = pModal->db2_1; 346 db2[2] = pModal->db2_2; 347 db2[3] = pModal->db2_3; 348 db2[4] = pModal->db2_4; 349 } else if (pModal->version == 1) { 350 ob[0] = pModal->ob_0; 351 ob[1] = ob[2] = ob[3] = ob[4] = pModal->ob_1; 352 db1[0] = pModal->db1_0; 353 db1[1] = db1[2] = db1[3] = db1[4] = pModal->db1_1; 354 db2[0] = pModal->db2_0; 355 db2[1] = db2[2] = db2[3] = db2[4] = pModal->db2_1; 356 } else { 357 int i; 358 359 for (i = 0; i < 5; i++) { 360 ob[i] = pModal->ob_0; 361 db1[i] = pModal->db1_0; 362 db2[i] = pModal->db1_0; 363 } 364 } 365 366 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_OB_0, ob[0]); 367 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_OB_1, ob[1]); 368 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_OB_2, ob[2]); 369 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_OB_3, ob[3]); 370 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_OB_4, ob[4]); 371 372 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_DB1_0, db1[0]); 373 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_DB1_1, db1[1]); 374 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_DB1_2, db1[2]); 375 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G4, AR9285_AN_RF2G4_DB1_3, db1[3]); 376 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G4, AR9285_AN_RF2G4_DB1_4, db1[4]); 377 378 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G4, AR9285_AN_RF2G4_DB2_0, db2[0]); 379 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G4, AR9285_AN_RF2G4_DB2_1, db2[1]); 380 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G4, AR9285_AN_RF2G4_DB2_2, db2[2]); 381 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G4, AR9285_AN_RF2G4_DB2_3, db2[3]); 382 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G4, AR9285_AN_RF2G4_DB2_4, db2[4]); 383 384 OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH, 385 pModal->switchSettling); 386 OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC, 387 pModal->adcDesiredSize); 388 389 OS_REG_WRITE(ah, AR_PHY_RF_CTL4, 390 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF) | 391 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF) | 392 SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON) | 393 SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON)); 394 395 OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON, 396 pModal->txEndToRxOn); 397 398 OS_REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62, 399 pModal->thresh62); 400 OS_REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62, 401 pModal->thresh62); 402 403 if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= 404 AR5416_EEP_MINOR_VER_2) { 405 OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_FRAME_TO_DATA_START, 406 pModal->txFrameToDataStart); 407 OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_FRAME_TO_PA_ON, 408 pModal->txFrameToPaOn); 409 } 410 411 if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= 412 AR5416_EEP_MINOR_VER_3) { 413 if (IEEE80211_IS_CHAN_HT40(chan)) 414 OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, 415 AR_PHY_SETTLING_SWITCH, pModal->swSettleHt40); 416 } 417 418 return AH_TRUE; 419} 420 421/* 422 * Helper functions common for AP/CB/XB 423 */ 424 425static HAL_BOOL 426ar9285SetPowerPerRateTable(struct ath_hal *ah, struct ar5416eeprom_4k *pEepData, 427 const struct ieee80211_channel *chan, 428 int16_t *ratesArray, uint16_t cfgCtl, 429 uint16_t AntennaReduction, 430 uint16_t twiceMaxRegulatoryPower, 431 uint16_t powerLimit) 432{ 433#define N(a) (sizeof(a)/sizeof(a[0])) 434/* Local defines to distinguish between extension and control CTL's */ 435#define EXT_ADDITIVE (0x8000) 436#define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE) 437#define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE) 438 439 uint16_t twiceMaxEdgePower = AR5416_MAX_RATE_POWER; 440 int i; 441 int16_t twiceLargestAntenna; 442 CAL_CTL_DATA_4K *rep; 443 CAL_TARGET_POWER_LEG targetPowerOfdm, targetPowerCck = {0, {0, 0, 0, 0}}; 444 CAL_TARGET_POWER_LEG targetPowerOfdmExt = {0, {0, 0, 0, 0}}, targetPowerCckExt = {0, {0, 0, 0, 0}}; 445 CAL_TARGET_POWER_HT targetPowerHt20, targetPowerHt40 = {0, {0, 0, 0, 0}}; 446 int16_t scaledPower, minCtlPower; 447 448#define SUB_NUM_CTL_MODES_AT_2G_40 3 /* excluding HT40, EXT-OFDM, EXT-CCK */ 449 static const uint16_t ctlModesFor11g[] = { 450 CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40 451 }; 452 const uint16_t *pCtlMode; 453 uint16_t numCtlModes, ctlMode, freq; 454 CHAN_CENTERS centers; 455 456 ar5416GetChannelCenters(ah, chan, ¢ers); 457 458 /* Compute TxPower reduction due to Antenna Gain */ 459 460 twiceLargestAntenna = pEepData->modalHeader.antennaGainCh[0]; 461 twiceLargestAntenna = (int16_t)AH_MIN((AntennaReduction) - twiceLargestAntenna, 0); 462 463 /* XXX setup for 5212 use (really used?) */ 464 ath_hal_eepromSet(ah, AR_EEP_ANTGAINMAX_2, twiceLargestAntenna); 465 466 /* 467 * scaledPower is the minimum of the user input power level and 468 * the regulatory allowed power level 469 */ 470 scaledPower = AH_MIN(powerLimit, twiceMaxRegulatoryPower + twiceLargestAntenna); 471 472 /* Get target powers from EEPROM - our baseline for TX Power */ 473 /* Setup for CTL modes */ 474 numCtlModes = N(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40; /* CTL_11B, CTL_11G, CTL_2GHT20 */ 475 pCtlMode = ctlModesFor11g; 476 477 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPowerCck, 478 AR5416_4K_NUM_2G_CCK_TARGET_POWERS, &targetPowerCck, 4, AH_FALSE); 479 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower2G, 480 AR5416_4K_NUM_2G_20_TARGET_POWERS, &targetPowerOfdm, 4, AH_FALSE); 481 ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower2GHT20, 482 AR5416_4K_NUM_2G_20_TARGET_POWERS, &targetPowerHt20, 8, AH_FALSE); 483 484 if (IEEE80211_IS_CHAN_HT40(chan)) { 485 numCtlModes = N(ctlModesFor11g); /* All 2G CTL's */ 486 487 ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower2GHT40, 488 AR5416_4K_NUM_2G_40_TARGET_POWERS, &targetPowerHt40, 8, AH_TRUE); 489 /* Get target powers for extension channels */ 490 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPowerCck, 491 AR5416_4K_NUM_2G_CCK_TARGET_POWERS, &targetPowerCckExt, 4, AH_TRUE); 492 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower2G, 493 AR5416_4K_NUM_2G_20_TARGET_POWERS, &targetPowerOfdmExt, 4, AH_TRUE); 494 } 495 496 /* 497 * For MIMO, need to apply regulatory caps individually across dynamically 498 * running modes: CCK, OFDM, HT20, HT40 499 * 500 * The outer loop walks through each possible applicable runtime mode. 501 * The inner loop walks through each ctlIndex entry in EEPROM. 502 * The ctl value is encoded as [7:4] == test group, [3:0] == test mode. 503 * 504 */ 505 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) { 506 HAL_BOOL isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) || 507 (pCtlMode[ctlMode] == CTL_2GHT40); 508 if (isHt40CtlMode) { 509 freq = centers.ctl_center; 510 } else if (pCtlMode[ctlMode] & EXT_ADDITIVE) { 511 freq = centers.ext_center; 512 } else { 513 freq = centers.ctl_center; 514 } 515 516 /* walk through each CTL index stored in EEPROM */ 517 for (i = 0; (i < AR5416_4K_NUM_CTLS) && pEepData->ctlIndex[i]; i++) { 518 uint16_t twiceMinEdgePower; 519 520 /* compare test group from regulatory channel list with test mode from pCtlMode list */ 521 if ((((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == pEepData->ctlIndex[i]) || 522 (((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == 523 ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))) { 524 rep = &(pEepData->ctlData[i]); 525 twiceMinEdgePower = ar9285GetMaxEdgePower(freq, 526 rep->ctlEdges[ 527 owl_get_ntxchains(AH5416(ah)->ah_tx_chainmask) - 1]); 528 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) { 529 /* Find the minimum of all CTL edge powers that apply to this channel */ 530 twiceMaxEdgePower = AH_MIN(twiceMaxEdgePower, twiceMinEdgePower); 531 } else { 532 /* specific */ 533 twiceMaxEdgePower = twiceMinEdgePower; 534 break; 535 } 536 } 537 } 538 minCtlPower = (uint8_t)AH_MIN(twiceMaxEdgePower, scaledPower); 539 /* Apply ctl mode to correct target power set */ 540 switch(pCtlMode[ctlMode]) { 541 case CTL_11B: 542 for (i = 0; i < N(targetPowerCck.tPow2x); i++) { 543 targetPowerCck.tPow2x[i] = (uint8_t)AH_MIN(targetPowerCck.tPow2x[i], minCtlPower); 544 } 545 break; 546 case CTL_11A: 547 case CTL_11G: 548 for (i = 0; i < N(targetPowerOfdm.tPow2x); i++) { 549 targetPowerOfdm.tPow2x[i] = (uint8_t)AH_MIN(targetPowerOfdm.tPow2x[i], minCtlPower); 550 } 551 break; 552 case CTL_5GHT20: 553 case CTL_2GHT20: 554 for (i = 0; i < N(targetPowerHt20.tPow2x); i++) { 555 targetPowerHt20.tPow2x[i] = (uint8_t)AH_MIN(targetPowerHt20.tPow2x[i], minCtlPower); 556 } 557 break; 558 case CTL_11B_EXT: 559 targetPowerCckExt.tPow2x[0] = (uint8_t)AH_MIN(targetPowerCckExt.tPow2x[0], minCtlPower); 560 break; 561 case CTL_11G_EXT: 562 targetPowerOfdmExt.tPow2x[0] = (uint8_t)AH_MIN(targetPowerOfdmExt.tPow2x[0], minCtlPower); 563 break; 564 case CTL_5GHT40: 565 case CTL_2GHT40: 566 for (i = 0; i < N(targetPowerHt40.tPow2x); i++) { 567 targetPowerHt40.tPow2x[i] = (uint8_t)AH_MIN(targetPowerHt40.tPow2x[i], minCtlPower); 568 } 569 break; 570 default: 571 return AH_FALSE; 572 break; 573 } 574 } /* end ctl mode checking */ 575 576 /* Set rates Array from collected data */ 577 ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] = ratesArray[rate18mb] = ratesArray[rate24mb] = targetPowerOfdm.tPow2x[0]; 578 ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1]; 579 ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2]; 580 ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3]; 581 ratesArray[rateXr] = targetPowerOfdm.tPow2x[0]; 582 583 for (i = 0; i < N(targetPowerHt20.tPow2x); i++) { 584 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i]; 585 } 586 587 ratesArray[rate1l] = targetPowerCck.tPow2x[0]; 588 ratesArray[rate2s] = ratesArray[rate2l] = targetPowerCck.tPow2x[1]; 589 ratesArray[rate5_5s] = ratesArray[rate5_5l] = targetPowerCck.tPow2x[2]; 590 ratesArray[rate11s] = ratesArray[rate11l] = targetPowerCck.tPow2x[3]; 591 if (IEEE80211_IS_CHAN_HT40(chan)) { 592 for (i = 0; i < N(targetPowerHt40.tPow2x); i++) { 593 ratesArray[rateHt40_0 + i] = targetPowerHt40.tPow2x[i]; 594 } 595 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0]; 596 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0]; 597 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0]; 598 if (IEEE80211_IS_CHAN_2GHZ(chan)) { 599 ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0]; 600 } 601 } 602 return AH_TRUE; 603#undef EXT_ADDITIVE 604#undef CTL_11G_EXT 605#undef CTL_11B_EXT 606#undef SUB_NUM_CTL_MODES_AT_2G_40 607#undef N 608} 609 610/************************************************************************** 611 * fbin2freq 612 * 613 * Get channel value from binary representation held in eeprom 614 * RETURNS: the frequency in MHz 615 */ 616static uint16_t 617fbin2freq(uint8_t fbin) 618{ 619 /* 620 * Reserved value 0xFF provides an empty definition both as 621 * an fbin and as a frequency - do not convert 622 */ 623 if (fbin == AR5416_BCHAN_UNUSED) { 624 return fbin; 625 } 626 627 return (uint16_t)(2300 + fbin); 628} 629 630/* 631 * XXX almost the same as ar5416GetMaxEdgePower. 632 */ 633static uint16_t 634ar9285GetMaxEdgePower(uint16_t freq, CAL_CTL_EDGES *pRdEdgesPower) 635{ 636 uint16_t twiceMaxEdgePower = AR5416_MAX_RATE_POWER; 637 int i; 638 639 /* Get the edge power */ 640 for (i = 0; (i < AR5416_NUM_BAND_EDGES) && (pRdEdgesPower[i].bChannel != AR5416_BCHAN_UNUSED) ; i++) { 641 /* 642 * If there's an exact channel match or an inband flag set 643 * on the lower channel use the given rdEdgePower 644 */ 645 if (freq == fbin2freq(pRdEdgesPower[i].bChannel)) { 646 twiceMaxEdgePower = MS(pRdEdgesPower[i].tPowerFlag, CAL_CTL_EDGES_POWER); 647 break; 648 } else if ((i > 0) && (freq < fbin2freq(pRdEdgesPower[i].bChannel))) { 649 if (fbin2freq(pRdEdgesPower[i - 1].bChannel) < freq && (pRdEdgesPower[i - 1].tPowerFlag & CAL_CTL_EDGES_FLAG) != 0) { 650 twiceMaxEdgePower = MS(pRdEdgesPower[i - 1].tPowerFlag, CAL_CTL_EDGES_POWER); 651 } 652 /* Leave loop - no more affecting edges possible in this monotonic increasing list */ 653 break; 654 } 655 } 656 HALASSERT(twiceMaxEdgePower > 0); 657 return twiceMaxEdgePower; 658} 659 660 661 662static HAL_BOOL 663ar9285SetPowerCalTable(struct ath_hal *ah, struct ar5416eeprom_4k *pEepData, 664 const struct ieee80211_channel *chan, int16_t *pTxPowerIndexOffset) 665{ 666 CAL_DATA_PER_FREQ_4K *pRawDataset; 667 uint8_t *pCalBChans = AH_NULL; 668 uint16_t pdGainOverlap_t2; 669 static uint8_t pdadcValues[AR5416_NUM_PDADC_VALUES]; 670 uint16_t gainBoundaries[AR5416_PD_GAINS_IN_MASK]; 671 uint16_t numPiers, i; 672 int16_t tMinCalPower; 673 uint16_t numXpdGain, xpdMask; 674 uint16_t xpdGainValues[4]; /* v4k eeprom has 2; the other two stay 0 */ 675 uint32_t regChainOffset; 676 677 OS_MEMZERO(xpdGainValues, sizeof(xpdGainValues)); 678 679 xpdMask = pEepData->modalHeader.xpdGain; 680 681 if (IS_EEP_MINOR_V2(ah)) { 682 pdGainOverlap_t2 = pEepData->modalHeader.pdGainOverlap; 683 } else { 684 pdGainOverlap_t2 = (uint16_t)(MS(OS_REG_READ(ah, AR_PHY_TPCRG5), AR_PHY_TPCRG5_PD_GAIN_OVERLAP)); 685 } 686 687 pCalBChans = pEepData->calFreqPier2G; 688 numPiers = AR5416_4K_NUM_2G_CAL_PIERS; 689 numXpdGain = 0; 690 691 /* Calculate the value of xpdgains from the xpdGain Mask */ 692 for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) { 693 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) { 694 if (numXpdGain >= AR5416_4K_NUM_PD_GAINS) { 695 HALASSERT(0); 696 break; 697 } 698 xpdGainValues[numXpdGain] = (uint16_t)(AR5416_PD_GAINS_IN_MASK - i); 699 numXpdGain++; 700 } 701 } 702 703 /* Write the detector gain biases and their number */ 704 ar5416WriteDetectorGainBiases(ah, numXpdGain, xpdGainValues); 705 706 for (i = 0; i < AR5416_MAX_CHAINS; i++) { 707 regChainOffset = ar5416GetRegChainOffset(ah, i); 708 if (pEepData->baseEepHeader.txMask & (1 << i)) { 709 pRawDataset = pEepData->calPierData2G[i]; 710 711 ar9285GetGainBoundariesAndPdadcs(ah, chan, pRawDataset, 712 pCalBChans, numPiers, 713 pdGainOverlap_t2, 714 &tMinCalPower, gainBoundaries, 715 pdadcValues, numXpdGain); 716 717 if ((i == 0) || AR_SREV_OWL_20_OR_LATER(ah)) { 718 /* 719 * Note the pdadc table may not start at 0 dBm power, could be 720 * negative or greater than 0. Need to offset the power 721 * values by the amount of minPower for griffin 722 */ 723 ar5416SetGainBoundariesClosedLoop(ah, i, pdGainOverlap_t2, gainBoundaries); 724 } 725 726 /* Write the power values into the baseband power table */ 727 ar5416WritePdadcValues(ah, i, pdadcValues); 728 } 729 } 730 *pTxPowerIndexOffset = 0; 731 732 return AH_TRUE; 733} 734 735static void 736ar9285GetGainBoundariesAndPdadcs(struct ath_hal *ah, 737 const struct ieee80211_channel *chan, 738 CAL_DATA_PER_FREQ_4K *pRawDataSet, 739 uint8_t * bChans, uint16_t availPiers, 740 uint16_t tPdGainOverlap, int16_t *pMinCalPower, uint16_t * pPdGainBoundaries, 741 uint8_t * pPDADCValues, uint16_t numXpdGains) 742{ 743 744 int i, j, k; 745 int16_t ss; /* potentially -ve index for taking care of pdGainOverlap */ 746 uint16_t idxL, idxR, numPiers; /* Pier indexes */ 747 748 /* filled out Vpd table for all pdGains (chanL) */ 749 static uint8_t vpdTableL[AR5416_4K_NUM_PD_GAINS][AR5416_MAX_PWR_RANGE_IN_HALF_DB]; 750 751 /* filled out Vpd table for all pdGains (chanR) */ 752 static uint8_t vpdTableR[AR5416_4K_NUM_PD_GAINS][AR5416_MAX_PWR_RANGE_IN_HALF_DB]; 753 754 /* filled out Vpd table for all pdGains (interpolated) */ 755 static uint8_t vpdTableI[AR5416_4K_NUM_PD_GAINS][AR5416_MAX_PWR_RANGE_IN_HALF_DB]; 756 757 uint8_t *pVpdL, *pVpdR, *pPwrL, *pPwrR; 758 uint8_t minPwrT4[AR5416_4K_NUM_PD_GAINS]; 759 uint8_t maxPwrT4[AR5416_4K_NUM_PD_GAINS]; 760 int16_t vpdStep; 761 int16_t tmpVal; 762 uint16_t sizeCurrVpdTable, maxIndex, tgtIndex; 763 HAL_BOOL match; 764 int16_t minDelta = 0; 765 CHAN_CENTERS centers; 766 767 ar5416GetChannelCenters(ah, chan, ¢ers); 768 769 /* Trim numPiers for the number of populated channel Piers */ 770 for (numPiers = 0; numPiers < availPiers; numPiers++) { 771 if (bChans[numPiers] == AR5416_BCHAN_UNUSED) { 772 break; 773 } 774 } 775 776 /* Find pier indexes around the current channel */ 777 match = ath_ee_getLowerUpperIndex((uint8_t)FREQ2FBIN(centers.synth_center, 778 IEEE80211_IS_CHAN_2GHZ(chan)), bChans, numPiers, &idxL, &idxR); 779 780 if (match) { 781 /* Directly fill both vpd tables from the matching index */ 782 for (i = 0; i < numXpdGains; i++) { 783 minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0]; 784 maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4]; 785 ath_ee_FillVpdTable(minPwrT4[i], maxPwrT4[i], 786 pRawDataSet[idxL].pwrPdg[i], 787 pRawDataSet[idxL].vpdPdg[i], 788 AR5416_PD_GAIN_ICEPTS, vpdTableI[i]); 789 } 790 } else { 791 for (i = 0; i < numXpdGains; i++) { 792 pVpdL = pRawDataSet[idxL].vpdPdg[i]; 793 pPwrL = pRawDataSet[idxL].pwrPdg[i]; 794 pVpdR = pRawDataSet[idxR].vpdPdg[i]; 795 pPwrR = pRawDataSet[idxR].pwrPdg[i]; 796 797 /* Start Vpd interpolation from the max of the minimum powers */ 798 minPwrT4[i] = AH_MAX(pPwrL[0], pPwrR[0]); 799 800 /* End Vpd interpolation from the min of the max powers */ 801 maxPwrT4[i] = AH_MIN(pPwrL[AR5416_PD_GAIN_ICEPTS - 1], pPwrR[AR5416_PD_GAIN_ICEPTS - 1]); 802 HALASSERT(maxPwrT4[i] > minPwrT4[i]); 803 804 /* Fill pier Vpds */ 805 ath_ee_FillVpdTable(minPwrT4[i], maxPwrT4[i], pPwrL, pVpdL, 806 AR5416_PD_GAIN_ICEPTS, vpdTableL[i]); 807 ath_ee_FillVpdTable(minPwrT4[i], maxPwrT4[i], pPwrR, pVpdR, 808 AR5416_PD_GAIN_ICEPTS, vpdTableR[i]); 809 810 /* Interpolate the final vpd */ 811 for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) { 812 vpdTableI[i][j] = (uint8_t)(ath_ee_interpolate((uint16_t)FREQ2FBIN(centers.synth_center, 813 IEEE80211_IS_CHAN_2GHZ(chan)), 814 bChans[idxL], bChans[idxR], vpdTableL[i][j], vpdTableR[i][j])); 815 } 816 } 817 } 818 *pMinCalPower = (int16_t)(minPwrT4[0] / 2); 819 820 k = 0; /* index for the final table */ 821 for (i = 0; i < numXpdGains; i++) { 822 if (i == (numXpdGains - 1)) { 823 pPdGainBoundaries[i] = (uint16_t)(maxPwrT4[i] / 2); 824 } else { 825 pPdGainBoundaries[i] = (uint16_t)((maxPwrT4[i] + minPwrT4[i+1]) / 4); 826 } 827 828 pPdGainBoundaries[i] = (uint16_t)AH_MIN(AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]); 829 830 /* NB: only applies to owl 1.0 */ 831 if ((i == 0) && !AR_SREV_OWL_20_OR_LATER(ah) ) { 832 /* 833 * fix the gain delta, but get a delta that can be applied to min to 834 * keep the upper power values accurate, don't think max needs to 835 * be adjusted because should not be at that area of the table? 836 */ 837 minDelta = pPdGainBoundaries[0] - 23; 838 pPdGainBoundaries[0] = 23; 839 } 840 else { 841 minDelta = 0; 842 } 843 844 /* Find starting index for this pdGain */ 845 if (i == 0) { 846 if (AR_SREV_MERLIN_20_OR_LATER(ah)) 847 ss = (int16_t)(0 - (minPwrT4[i] / 2)); 848 else 849 ss = 0; /* for the first pdGain, start from index 0 */ 850 } else { 851 /* need overlap entries extrapolated below. */ 852 ss = (int16_t)((pPdGainBoundaries[i-1] - (minPwrT4[i] / 2)) - tPdGainOverlap + 1 + minDelta); 853 } 854 vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]); 855 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep); 856 /* 857 *-ve ss indicates need to extrapolate data below for this pdGain 858 */ 859 while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) { 860 tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep); 861 pPDADCValues[k++] = (uint8_t)((tmpVal < 0) ? 0 : tmpVal); 862 ss++; 863 } 864 865 sizeCurrVpdTable = (uint8_t)((maxPwrT4[i] - minPwrT4[i]) / 2 +1); 866 tgtIndex = (uint8_t)(pPdGainBoundaries[i] + tPdGainOverlap - (minPwrT4[i] / 2)); 867 maxIndex = (tgtIndex < sizeCurrVpdTable) ? tgtIndex : sizeCurrVpdTable; 868 869 while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) { 870 pPDADCValues[k++] = vpdTableI[i][ss++]; 871 } 872 873 vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] - vpdTableI[i][sizeCurrVpdTable - 2]); 874 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep); 875 /* 876 * for last gain, pdGainBoundary == Pmax_t2, so will 877 * have to extrapolate 878 */ 879 if (tgtIndex >= maxIndex) { /* need to extrapolate above */ 880 while ((ss <= tgtIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) { 881 tmpVal = (int16_t)((vpdTableI[i][sizeCurrVpdTable - 1] + 882 (ss - maxIndex +1) * vpdStep)); 883 pPDADCValues[k++] = (uint8_t)((tmpVal > 255) ? 255 : tmpVal); 884 ss++; 885 } 886 } /* extrapolated above */ 887 } /* for all pdGainUsed */ 888 889 /* Fill out pdGainBoundaries - only up to 2 allowed here, but hardware allows up to 4 */ 890 while (i < AR5416_PD_GAINS_IN_MASK) { 891 pPdGainBoundaries[i] = pPdGainBoundaries[i-1]; 892 i++; 893 } 894 895 while (k < AR5416_NUM_PDADC_VALUES) { 896 pPDADCValues[k] = pPDADCValues[k-1]; 897 k++; 898 } 899 return; 900} 901