ar9285_reset.c revision 219475
1/* 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar9002/ar9285_reset.c 219475 2011-03-11 04:31:00Z adrian $ 18 */ 19 20/* 21 * This is almost the same as ar5416_reset.c but uses the v4k EEPROM and 22 * supports only 2Ghz operation. 23 */ 24 25#include "opt_ah.h" 26 27#include "ah.h" 28#include "ah_internal.h" 29#include "ah_devid.h" 30 31#include "ah_eeprom_v14.h" 32#include "ah_eeprom_v4k.h" 33 34#include "ar9002/ar9285.h" 35#include "ar5416/ar5416.h" 36#include "ar5416/ar5416reg.h" 37#include "ar5416/ar5416phy.h" 38 39/* Eeprom versioning macros. Returns true if the version is equal or newer than the ver specified */ 40#define EEP_MINOR(_ah) \ 41 (AH_PRIVATE(_ah)->ah_eeversion & AR5416_EEP_VER_MINOR_MASK) 42#define IS_EEP_MINOR_V2(_ah) (EEP_MINOR(_ah) >= AR5416_EEP_MINOR_VER_2) 43#define IS_EEP_MINOR_V3(_ah) (EEP_MINOR(_ah) >= AR5416_EEP_MINOR_VER_3) 44 45/* Additional Time delay to wait after activiting the Base band */ 46#define BASE_ACTIVATE_DELAY 100 /* 100 usec */ 47#define PLL_SETTLE_DELAY 300 /* 300 usec */ 48#define RTC_PLL_SETTLE_DELAY 1000 /* 1 ms */ 49 50static HAL_BOOL ar9285SetPowerPerRateTable(struct ath_hal *ah, 51 struct ar5416eeprom_4k *pEepData, 52 const struct ieee80211_channel *chan, int16_t *ratesArray, 53 uint16_t cfgCtl, uint16_t AntennaReduction, 54 uint16_t twiceMaxRegulatoryPower, 55 uint16_t powerLimit); 56static HAL_BOOL ar9285SetPowerCalTable(struct ath_hal *ah, 57 struct ar5416eeprom_4k *pEepData, 58 const struct ieee80211_channel *chan, 59 int16_t *pTxPowerIndexOffset); 60static int16_t interpolate(uint16_t target, uint16_t srcLeft, 61 uint16_t srcRight, int16_t targetLeft, int16_t targetRight); 62static HAL_BOOL ar9285FillVpdTable(uint8_t, uint8_t, uint8_t *, uint8_t *, 63 uint16_t, uint8_t *); 64static void ar9285GetGainBoundariesAndPdadcs(struct ath_hal *ah, 65 const struct ieee80211_channel *chan, CAL_DATA_PER_FREQ_4K *pRawDataSet, 66 uint8_t * bChans, uint16_t availPiers, 67 uint16_t tPdGainOverlap, int16_t *pMinCalPower, 68 uint16_t * pPdGainBoundaries, uint8_t * pPDADCValues, 69 uint16_t numXpdGains); 70static uint16_t ar9285GetMaxEdgePower(uint16_t, CAL_CTL_EDGES *); 71 72/* XXX gag, this is sick */ 73typedef enum Ar5416_Rates { 74 rate6mb, rate9mb, rate12mb, rate18mb, 75 rate24mb, rate36mb, rate48mb, rate54mb, 76 rate1l, rate2l, rate2s, rate5_5l, 77 rate5_5s, rate11l, rate11s, rateXr, 78 rateHt20_0, rateHt20_1, rateHt20_2, rateHt20_3, 79 rateHt20_4, rateHt20_5, rateHt20_6, rateHt20_7, 80 rateHt40_0, rateHt40_1, rateHt40_2, rateHt40_3, 81 rateHt40_4, rateHt40_5, rateHt40_6, rateHt40_7, 82 rateDupCck, rateDupOfdm, rateExtCck, rateExtOfdm, 83 Ar5416RateSize 84} AR5416_RATES; 85 86HAL_BOOL 87ar9285SetTransmitPower(struct ath_hal *ah, 88 const struct ieee80211_channel *chan, uint16_t *rfXpdGain) 89{ 90#define POW_SM(_r, _s) (((_r) & 0x3f) << (_s)) 91#define N(a) (sizeof (a) / sizeof (a[0])) 92 93 MODAL_EEP4K_HEADER *pModal; 94 struct ath_hal_5212 *ahp = AH5212(ah); 95 int16_t ratesArray[Ar5416RateSize]; 96 int16_t txPowerIndexOffset = 0; 97 uint8_t ht40PowerIncForPdadc = 2; 98 int i; 99 100 uint16_t cfgCtl; 101 uint16_t powerLimit; 102 uint16_t twiceAntennaReduction; 103 uint16_t twiceMaxRegulatoryPower; 104 int16_t maxPower; 105 HAL_EEPROM_v4k *ee = AH_PRIVATE(ah)->ah_eeprom; 106 struct ar5416eeprom_4k *pEepData = &ee->ee_base; 107 108 HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER14_1); 109 110 /* Setup info for the actual eeprom */ 111 OS_MEMZERO(ratesArray, sizeof(ratesArray)); 112 cfgCtl = ath_hal_getctl(ah, chan); 113 powerLimit = chan->ic_maxregpower * 2; 114 twiceAntennaReduction = chan->ic_maxantgain; 115 twiceMaxRegulatoryPower = AH_MIN(MAX_RATE_POWER, AH_PRIVATE(ah)->ah_powerLimit); 116 pModal = &pEepData->modalHeader; 117 HALDEBUG(ah, HAL_DEBUG_RESET, "%s Channel=%u CfgCtl=%u\n", 118 __func__,chan->ic_freq, cfgCtl ); 119 120 if (IS_EEP_MINOR_V2(ah)) { 121 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc; 122 } 123 124 if (!ar9285SetPowerPerRateTable(ah, pEepData, chan, 125 &ratesArray[0],cfgCtl, 126 twiceAntennaReduction, 127 twiceMaxRegulatoryPower, powerLimit)) { 128 HALDEBUG(ah, HAL_DEBUG_ANY, 129 "%s: unable to set tx power per rate table\n", __func__); 130 return AH_FALSE; 131 } 132 133 if (!ar9285SetPowerCalTable(ah, pEepData, chan, &txPowerIndexOffset)) { 134 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unable to set power table\n", 135 __func__); 136 return AH_FALSE; 137 } 138 139 maxPower = AH_MAX(ratesArray[rate6mb], ratesArray[rateHt20_0]); 140 maxPower = AH_MAX(maxPower, ratesArray[rate1l]); 141 142 if (IEEE80211_IS_CHAN_HT40(chan)) { 143 maxPower = AH_MAX(maxPower, ratesArray[rateHt40_0]); 144 } 145 146 ahp->ah_tx6PowerInHalfDbm = maxPower; 147 AH_PRIVATE(ah)->ah_maxPowerLevel = maxPower; 148 ahp->ah_txPowerIndexOffset = txPowerIndexOffset; 149 150 /* 151 * txPowerIndexOffset is set by the SetPowerTable() call - 152 * adjust the rate table (0 offset if rates EEPROM not loaded) 153 */ 154 for (i = 0; i < N(ratesArray); i++) { 155 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]); 156 /* -5 dBm offset for Merlin and later; this includes Kite */ 157 ratesArray[i] -= AR5416_PWR_TABLE_OFFSET_DB * 2; 158 if (ratesArray[i] > AR5416_MAX_RATE_POWER) 159 ratesArray[i] = AR5416_MAX_RATE_POWER; 160 if (ratesArray[i] < 0) 161 ratesArray[i] = 0; 162 } 163 164#ifdef AH_EEPROM_DUMP 165 ar5416PrintPowerPerRate(ah, ratesArray); 166#endif 167 168 /* Write the OFDM power per rate set */ 169 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE1, 170 POW_SM(ratesArray[rate18mb], 24) 171 | POW_SM(ratesArray[rate12mb], 16) 172 | POW_SM(ratesArray[rate9mb], 8) 173 | POW_SM(ratesArray[rate6mb], 0) 174 ); 175 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE2, 176 POW_SM(ratesArray[rate54mb], 24) 177 | POW_SM(ratesArray[rate48mb], 16) 178 | POW_SM(ratesArray[rate36mb], 8) 179 | POW_SM(ratesArray[rate24mb], 0) 180 ); 181 182 /* Write the CCK power per rate set */ 183 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE3, 184 POW_SM(ratesArray[rate2s], 24) 185 | POW_SM(ratesArray[rate2l], 16) 186 | POW_SM(ratesArray[rateXr], 8) /* XR target power */ 187 | POW_SM(ratesArray[rate1l], 0) 188 ); 189 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE4, 190 POW_SM(ratesArray[rate11s], 24) 191 | POW_SM(ratesArray[rate11l], 16) 192 | POW_SM(ratesArray[rate5_5s], 8) 193 | POW_SM(ratesArray[rate5_5l], 0) 194 ); 195 HALDEBUG(ah, HAL_DEBUG_RESET, 196 "%s AR_PHY_POWER_TX_RATE3=0x%x AR_PHY_POWER_TX_RATE4=0x%x\n", 197 __func__, OS_REG_READ(ah,AR_PHY_POWER_TX_RATE3), 198 OS_REG_READ(ah,AR_PHY_POWER_TX_RATE4)); 199 200 /* Write the HT20 power per rate set */ 201 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE5, 202 POW_SM(ratesArray[rateHt20_3], 24) 203 | POW_SM(ratesArray[rateHt20_2], 16) 204 | POW_SM(ratesArray[rateHt20_1], 8) 205 | POW_SM(ratesArray[rateHt20_0], 0) 206 ); 207 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE6, 208 POW_SM(ratesArray[rateHt20_7], 24) 209 | POW_SM(ratesArray[rateHt20_6], 16) 210 | POW_SM(ratesArray[rateHt20_5], 8) 211 | POW_SM(ratesArray[rateHt20_4], 0) 212 ); 213 214 if (IEEE80211_IS_CHAN_HT40(chan)) { 215 /* Write the HT40 power per rate set */ 216 /* Correct PAR difference between HT40 and HT20/LEGACY */ 217 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE7, 218 POW_SM(ratesArray[rateHt40_3] + ht40PowerIncForPdadc, 24) 219 | POW_SM(ratesArray[rateHt40_2] + ht40PowerIncForPdadc, 16) 220 | POW_SM(ratesArray[rateHt40_1] + ht40PowerIncForPdadc, 8) 221 | POW_SM(ratesArray[rateHt40_0] + ht40PowerIncForPdadc, 0) 222 ); 223 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE8, 224 POW_SM(ratesArray[rateHt40_7] + ht40PowerIncForPdadc, 24) 225 | POW_SM(ratesArray[rateHt40_6] + ht40PowerIncForPdadc, 16) 226 | POW_SM(ratesArray[rateHt40_5] + ht40PowerIncForPdadc, 8) 227 | POW_SM(ratesArray[rateHt40_4] + ht40PowerIncForPdadc, 0) 228 ); 229 /* Write the Dup/Ext 40 power per rate set */ 230 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE9, 231 POW_SM(ratesArray[rateExtOfdm], 24) 232 | POW_SM(ratesArray[rateExtCck], 16) 233 | POW_SM(ratesArray[rateDupOfdm], 8) 234 | POW_SM(ratesArray[rateDupCck], 0) 235 ); 236 } 237 238 return AH_TRUE; 239#undef POW_SM 240#undef N 241} 242 243HAL_BOOL 244ar9285SetBoardValues(struct ath_hal *ah, const struct ieee80211_channel *chan) 245{ 246 const HAL_EEPROM_v4k *ee = AH_PRIVATE(ah)->ah_eeprom; 247 const struct ar5416eeprom_4k *eep = &ee->ee_base; 248 const MODAL_EEP4K_HEADER *pModal; 249 uint8_t txRxAttenLocal = 23; 250 251 HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER14_1); 252 pModal = &eep->modalHeader; 253 254 OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon); 255 OS_REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0, pModal->antCtrlChain[0]); 256 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4, 257 (OS_REG_READ(ah, AR_PHY_TIMING_CTRL4) & 258 ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF | AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) | 259 SM(pModal->iqCalICh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) | 260 SM(pModal->iqCalQCh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF)); 261 262 if (IS_EEP_MINOR_V3(ah)) { 263 if (IEEE80211_IS_CHAN_HT40(chan)) { 264 /* Overwrite switch settling with HT40 value */ 265 OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH, 266 pModal->swSettleHt40); 267 } 268 txRxAttenLocal = pModal->txRxAttenCh[0]; 269 270 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, 271 pModal->bswMargin[0]); 272 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, AR_PHY_GAIN_2GHZ_XATTEN1_DB, 273 pModal->bswAtten[0]); 274 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN, 275 pModal->xatten2Margin[0]); 276 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, AR_PHY_GAIN_2GHZ_XATTEN2_DB, 277 pModal->xatten2Db[0]); 278 279 /* block 1 has the same values as block 0 */ 280 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000, 281 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, pModal->bswMargin[0]); 282 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000, 283 AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]); 284 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000, 285 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN, pModal->xatten2Margin[0]); 286 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000, 287 AR_PHY_GAIN_2GHZ_XATTEN2_DB, pModal->xatten2Db[0]); 288 289 } 290 OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN, 291 AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal); 292 OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN, 293 AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]); 294 295 OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000, 296 AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal); 297 OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000, 298 AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]); 299 300 if (AR_SREV_KITE_11(ah)) 301 OS_REG_WRITE(ah, AR9285_AN_TOP4, (AR9285_AN_TOP4_DEFAULT | 0x14)); 302 303 return AH_TRUE; 304} 305 306/* 307 * Helper functions common for AP/CB/XB 308 */ 309 310static HAL_BOOL 311ar9285SetPowerPerRateTable(struct ath_hal *ah, struct ar5416eeprom_4k *pEepData, 312 const struct ieee80211_channel *chan, 313 int16_t *ratesArray, uint16_t cfgCtl, 314 uint16_t AntennaReduction, 315 uint16_t twiceMaxRegulatoryPower, 316 uint16_t powerLimit) 317{ 318#define N(a) (sizeof(a)/sizeof(a[0])) 319/* Local defines to distinguish between extension and control CTL's */ 320#define EXT_ADDITIVE (0x8000) 321#define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE) 322#define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE) 323 324 uint16_t twiceMaxEdgePower = AR5416_MAX_RATE_POWER; 325 int i; 326 int16_t twiceLargestAntenna; 327 CAL_CTL_DATA_4K *rep; 328 CAL_TARGET_POWER_LEG targetPowerOfdm, targetPowerCck = {0, {0, 0, 0, 0}}; 329 CAL_TARGET_POWER_LEG targetPowerOfdmExt = {0, {0, 0, 0, 0}}, targetPowerCckExt = {0, {0, 0, 0, 0}}; 330 CAL_TARGET_POWER_HT targetPowerHt20, targetPowerHt40 = {0, {0, 0, 0, 0}}; 331 int16_t scaledPower, minCtlPower; 332 333#define SUB_NUM_CTL_MODES_AT_2G_40 3 /* excluding HT40, EXT-OFDM, EXT-CCK */ 334 static const uint16_t ctlModesFor11g[] = { 335 CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40 336 }; 337 const uint16_t *pCtlMode; 338 uint16_t numCtlModes, ctlMode, freq; 339 CHAN_CENTERS centers; 340 341 ar5416GetChannelCenters(ah, chan, ¢ers); 342 343 /* Compute TxPower reduction due to Antenna Gain */ 344 345 twiceLargestAntenna = pEepData->modalHeader.antennaGainCh[0]; 346 twiceLargestAntenna = (int16_t)AH_MIN((AntennaReduction) - twiceLargestAntenna, 0); 347 348 /* XXX setup for 5212 use (really used?) */ 349 ath_hal_eepromSet(ah, AR_EEP_ANTGAINMAX_2, twiceLargestAntenna); 350 351 /* 352 * scaledPower is the minimum of the user input power level and 353 * the regulatory allowed power level 354 */ 355 scaledPower = AH_MIN(powerLimit, twiceMaxRegulatoryPower + twiceLargestAntenna); 356 357 /* Get target powers from EEPROM - our baseline for TX Power */ 358 /* Setup for CTL modes */ 359 numCtlModes = N(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40; /* CTL_11B, CTL_11G, CTL_2GHT20 */ 360 pCtlMode = ctlModesFor11g; 361 362 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPowerCck, 363 AR5416_4K_NUM_2G_CCK_TARGET_POWERS, &targetPowerCck, 4, AH_FALSE); 364 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower2G, 365 AR5416_4K_NUM_2G_20_TARGET_POWERS, &targetPowerOfdm, 4, AH_FALSE); 366 ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower2GHT20, 367 AR5416_4K_NUM_2G_20_TARGET_POWERS, &targetPowerHt20, 8, AH_FALSE); 368 369 if (IEEE80211_IS_CHAN_HT40(chan)) { 370 numCtlModes = N(ctlModesFor11g); /* All 2G CTL's */ 371 372 ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower2GHT40, 373 AR5416_4K_NUM_2G_40_TARGET_POWERS, &targetPowerHt40, 8, AH_TRUE); 374 /* Get target powers for extension channels */ 375 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPowerCck, 376 AR5416_4K_NUM_2G_CCK_TARGET_POWERS, &targetPowerCckExt, 4, AH_TRUE); 377 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower2G, 378 AR5416_4K_NUM_2G_20_TARGET_POWERS, &targetPowerOfdmExt, 4, AH_TRUE); 379 } 380 381 /* 382 * For MIMO, need to apply regulatory caps individually across dynamically 383 * running modes: CCK, OFDM, HT20, HT40 384 * 385 * The outer loop walks through each possible applicable runtime mode. 386 * The inner loop walks through each ctlIndex entry in EEPROM. 387 * The ctl value is encoded as [7:4] == test group, [3:0] == test mode. 388 * 389 */ 390 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) { 391 HAL_BOOL isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) || 392 (pCtlMode[ctlMode] == CTL_2GHT40); 393 if (isHt40CtlMode) { 394 freq = centers.ctl_center; 395 } else if (pCtlMode[ctlMode] & EXT_ADDITIVE) { 396 freq = centers.ext_center; 397 } else { 398 freq = centers.ctl_center; 399 } 400 401 /* walk through each CTL index stored in EEPROM */ 402 for (i = 0; (i < AR5416_4K_NUM_CTLS) && pEepData->ctlIndex[i]; i++) { 403 uint16_t twiceMinEdgePower; 404 405 /* compare test group from regulatory channel list with test mode from pCtlMode list */ 406 if ((((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == pEepData->ctlIndex[i]) || 407 (((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == 408 ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))) { 409 rep = &(pEepData->ctlData[i]); 410 twiceMinEdgePower = ar9285GetMaxEdgePower(freq, 411 rep->ctlEdges[ 412 owl_get_ntxchains(AH5416(ah)->ah_tx_chainmask) - 1]); 413 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) { 414 /* Find the minimum of all CTL edge powers that apply to this channel */ 415 twiceMaxEdgePower = AH_MIN(twiceMaxEdgePower, twiceMinEdgePower); 416 } else { 417 /* specific */ 418 twiceMaxEdgePower = twiceMinEdgePower; 419 break; 420 } 421 } 422 } 423 minCtlPower = (uint8_t)AH_MIN(twiceMaxEdgePower, scaledPower); 424 /* Apply ctl mode to correct target power set */ 425 switch(pCtlMode[ctlMode]) { 426 case CTL_11B: 427 for (i = 0; i < N(targetPowerCck.tPow2x); i++) { 428 targetPowerCck.tPow2x[i] = (uint8_t)AH_MIN(targetPowerCck.tPow2x[i], minCtlPower); 429 } 430 break; 431 case CTL_11A: 432 case CTL_11G: 433 for (i = 0; i < N(targetPowerOfdm.tPow2x); i++) { 434 targetPowerOfdm.tPow2x[i] = (uint8_t)AH_MIN(targetPowerOfdm.tPow2x[i], minCtlPower); 435 } 436 break; 437 case CTL_5GHT20: 438 case CTL_2GHT20: 439 for (i = 0; i < N(targetPowerHt20.tPow2x); i++) { 440 targetPowerHt20.tPow2x[i] = (uint8_t)AH_MIN(targetPowerHt20.tPow2x[i], minCtlPower); 441 } 442 break; 443 case CTL_11B_EXT: 444 targetPowerCckExt.tPow2x[0] = (uint8_t)AH_MIN(targetPowerCckExt.tPow2x[0], minCtlPower); 445 break; 446 case CTL_11G_EXT: 447 targetPowerOfdmExt.tPow2x[0] = (uint8_t)AH_MIN(targetPowerOfdmExt.tPow2x[0], minCtlPower); 448 break; 449 case CTL_5GHT40: 450 case CTL_2GHT40: 451 for (i = 0; i < N(targetPowerHt40.tPow2x); i++) { 452 targetPowerHt40.tPow2x[i] = (uint8_t)AH_MIN(targetPowerHt40.tPow2x[i], minCtlPower); 453 } 454 break; 455 default: 456 return AH_FALSE; 457 break; 458 } 459 } /* end ctl mode checking */ 460 461 /* Set rates Array from collected data */ 462 ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] = ratesArray[rate18mb] = ratesArray[rate24mb] = targetPowerOfdm.tPow2x[0]; 463 ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1]; 464 ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2]; 465 ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3]; 466 ratesArray[rateXr] = targetPowerOfdm.tPow2x[0]; 467 468 for (i = 0; i < N(targetPowerHt20.tPow2x); i++) { 469 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i]; 470 } 471 472 ratesArray[rate1l] = targetPowerCck.tPow2x[0]; 473 ratesArray[rate2s] = ratesArray[rate2l] = targetPowerCck.tPow2x[1]; 474 ratesArray[rate5_5s] = ratesArray[rate5_5l] = targetPowerCck.tPow2x[2]; 475 ratesArray[rate11s] = ratesArray[rate11l] = targetPowerCck.tPow2x[3]; 476 if (IEEE80211_IS_CHAN_HT40(chan)) { 477 for (i = 0; i < N(targetPowerHt40.tPow2x); i++) { 478 ratesArray[rateHt40_0 + i] = targetPowerHt40.tPow2x[i]; 479 } 480 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0]; 481 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0]; 482 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0]; 483 if (IEEE80211_IS_CHAN_2GHZ(chan)) { 484 ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0]; 485 } 486 } 487 return AH_TRUE; 488#undef EXT_ADDITIVE 489#undef CTL_11G_EXT 490#undef CTL_11B_EXT 491#undef SUB_NUM_CTL_MODES_AT_2G_40 492#undef N 493} 494 495/************************************************************************** 496 * fbin2freq 497 * 498 * Get channel value from binary representation held in eeprom 499 * RETURNS: the frequency in MHz 500 */ 501static uint16_t 502fbin2freq(uint8_t fbin) 503{ 504 /* 505 * Reserved value 0xFF provides an empty definition both as 506 * an fbin and as a frequency - do not convert 507 */ 508 if (fbin == AR5416_BCHAN_UNUSED) { 509 return fbin; 510 } 511 512 return (uint16_t)(2300 + fbin); 513} 514 515/* 516 * XXX almost the same as ar5416GetMaxEdgePower. 517 */ 518static uint16_t 519ar9285GetMaxEdgePower(uint16_t freq, CAL_CTL_EDGES *pRdEdgesPower) 520{ 521 uint16_t twiceMaxEdgePower = AR5416_MAX_RATE_POWER; 522 int i; 523 524 /* Get the edge power */ 525 for (i = 0; (i < AR5416_NUM_BAND_EDGES) && (pRdEdgesPower[i].bChannel != AR5416_BCHAN_UNUSED) ; i++) { 526 /* 527 * If there's an exact channel match or an inband flag set 528 * on the lower channel use the given rdEdgePower 529 */ 530 if (freq == fbin2freq(pRdEdgesPower[i].bChannel)) { 531 twiceMaxEdgePower = MS(pRdEdgesPower[i].tPowerFlag, CAL_CTL_EDGES_POWER); 532 break; 533 } else if ((i > 0) && (freq < fbin2freq(pRdEdgesPower[i].bChannel))) { 534 if (fbin2freq(pRdEdgesPower[i - 1].bChannel) < freq && (pRdEdgesPower[i - 1].tPowerFlag & CAL_CTL_EDGES_FLAG) != 0) { 535 twiceMaxEdgePower = MS(pRdEdgesPower[i - 1].tPowerFlag, CAL_CTL_EDGES_POWER); 536 } 537 /* Leave loop - no more affecting edges possible in this monotonic increasing list */ 538 break; 539 } 540 } 541 HALASSERT(twiceMaxEdgePower > 0); 542 return twiceMaxEdgePower; 543} 544 545 546 547static HAL_BOOL 548ar9285SetPowerCalTable(struct ath_hal *ah, struct ar5416eeprom_4k *pEepData, 549 const struct ieee80211_channel *chan, int16_t *pTxPowerIndexOffset) 550{ 551 CAL_DATA_PER_FREQ_4K *pRawDataset; 552 uint8_t *pCalBChans = AH_NULL; 553 uint16_t pdGainOverlap_t2; 554 static uint8_t pdadcValues[AR5416_NUM_PDADC_VALUES]; 555 uint16_t gainBoundaries[AR5416_PD_GAINS_IN_MASK]; 556 uint16_t numPiers, i; 557 int16_t tMinCalPower; 558 uint16_t numXpdGain, xpdMask; 559 uint16_t xpdGainValues[4]; /* v4k eeprom has 2; the other two stay 0 */ 560 uint32_t regChainOffset; 561 562 OS_MEMZERO(xpdGainValues, sizeof(xpdGainValues)); 563 564 xpdMask = pEepData->modalHeader.xpdGain; 565 566 if (IS_EEP_MINOR_V2(ah)) { 567 pdGainOverlap_t2 = pEepData->modalHeader.pdGainOverlap; 568 } else { 569 pdGainOverlap_t2 = (uint16_t)(MS(OS_REG_READ(ah, AR_PHY_TPCRG5), AR_PHY_TPCRG5_PD_GAIN_OVERLAP)); 570 } 571 572 pCalBChans = pEepData->calFreqPier2G; 573 numPiers = AR5416_4K_NUM_2G_CAL_PIERS; 574 numXpdGain = 0; 575 576 /* Calculate the value of xpdgains from the xpdGain Mask */ 577 for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) { 578 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) { 579 if (numXpdGain >= AR5416_4K_NUM_PD_GAINS) { 580 HALASSERT(0); 581 break; 582 } 583 xpdGainValues[numXpdGain] = (uint16_t)(AR5416_PD_GAINS_IN_MASK - i); 584 numXpdGain++; 585 } 586 } 587 588 /* Write the detector gain biases and their number */ 589 ar5416WriteDetectorGainBiases(ah, numXpdGain, xpdGainValues); 590 591 for (i = 0; i < AR5416_MAX_CHAINS; i++) { 592 regChainOffset = ar5416GetRegChainOffset(ah, i); 593 if (pEepData->baseEepHeader.txMask & (1 << i)) { 594 pRawDataset = pEepData->calPierData2G[i]; 595 596 ar9285GetGainBoundariesAndPdadcs(ah, chan, pRawDataset, 597 pCalBChans, numPiers, 598 pdGainOverlap_t2, 599 &tMinCalPower, gainBoundaries, 600 pdadcValues, numXpdGain); 601 602 if ((i == 0) || AR_SREV_OWL_20_OR_LATER(ah)) { 603 /* 604 * Note the pdadc table may not start at 0 dBm power, could be 605 * negative or greater than 0. Need to offset the power 606 * values by the amount of minPower for griffin 607 */ 608 ar5416SetGainBoundariesClosedLoop(ah, regChainOffset, pdGainOverlap_t2, gainBoundaries); 609 } 610 611 /* Write the power values into the baseband power table */ 612 ar5416WritePdadcValues(ah, regChainOffset, pdadcValues); 613 } 614 } 615 *pTxPowerIndexOffset = 0; 616 617 return AH_TRUE; 618} 619 620static void 621ar9285GetGainBoundariesAndPdadcs(struct ath_hal *ah, 622 const struct ieee80211_channel *chan, 623 CAL_DATA_PER_FREQ_4K *pRawDataSet, 624 uint8_t * bChans, uint16_t availPiers, 625 uint16_t tPdGainOverlap, int16_t *pMinCalPower, uint16_t * pPdGainBoundaries, 626 uint8_t * pPDADCValues, uint16_t numXpdGains) 627{ 628 629 int i, j, k; 630 int16_t ss; /* potentially -ve index for taking care of pdGainOverlap */ 631 uint16_t idxL, idxR, numPiers; /* Pier indexes */ 632 633 /* filled out Vpd table for all pdGains (chanL) */ 634 static uint8_t vpdTableL[AR5416_4K_NUM_PD_GAINS][AR5416_MAX_PWR_RANGE_IN_HALF_DB]; 635 636 /* filled out Vpd table for all pdGains (chanR) */ 637 static uint8_t vpdTableR[AR5416_4K_NUM_PD_GAINS][AR5416_MAX_PWR_RANGE_IN_HALF_DB]; 638 639 /* filled out Vpd table for all pdGains (interpolated) */ 640 static uint8_t vpdTableI[AR5416_4K_NUM_PD_GAINS][AR5416_MAX_PWR_RANGE_IN_HALF_DB]; 641 642 uint8_t *pVpdL, *pVpdR, *pPwrL, *pPwrR; 643 uint8_t minPwrT4[AR5416_4K_NUM_PD_GAINS]; 644 uint8_t maxPwrT4[AR5416_4K_NUM_PD_GAINS]; 645 int16_t vpdStep; 646 int16_t tmpVal; 647 uint16_t sizeCurrVpdTable, maxIndex, tgtIndex; 648 HAL_BOOL match; 649 int16_t minDelta = 0; 650 CHAN_CENTERS centers; 651 652 ar5416GetChannelCenters(ah, chan, ¢ers); 653 654 /* Trim numPiers for the number of populated channel Piers */ 655 for (numPiers = 0; numPiers < availPiers; numPiers++) { 656 if (bChans[numPiers] == AR5416_BCHAN_UNUSED) { 657 break; 658 } 659 } 660 661 /* Find pier indexes around the current channel */ 662 match = getLowerUpperIndex((uint8_t)FREQ2FBIN(centers.synth_center, IEEE80211_IS_CHAN_2GHZ(chan)), 663 bChans, numPiers, &idxL, &idxR); 664 665 if (match) { 666 /* Directly fill both vpd tables from the matching index */ 667 for (i = 0; i < numXpdGains; i++) { 668 minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0]; 669 maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4]; 670 ar9285FillVpdTable(minPwrT4[i], maxPwrT4[i], 671 pRawDataSet[idxL].pwrPdg[i], 672 pRawDataSet[idxL].vpdPdg[i], 673 AR5416_PD_GAIN_ICEPTS, vpdTableI[i]); 674 } 675 } else { 676 for (i = 0; i < numXpdGains; i++) { 677 pVpdL = pRawDataSet[idxL].vpdPdg[i]; 678 pPwrL = pRawDataSet[idxL].pwrPdg[i]; 679 pVpdR = pRawDataSet[idxR].vpdPdg[i]; 680 pPwrR = pRawDataSet[idxR].pwrPdg[i]; 681 682 /* Start Vpd interpolation from the max of the minimum powers */ 683 minPwrT4[i] = AH_MAX(pPwrL[0], pPwrR[0]); 684 685 /* End Vpd interpolation from the min of the max powers */ 686 maxPwrT4[i] = AH_MIN(pPwrL[AR5416_PD_GAIN_ICEPTS - 1], pPwrR[AR5416_PD_GAIN_ICEPTS - 1]); 687 HALASSERT(maxPwrT4[i] > minPwrT4[i]); 688 689 /* Fill pier Vpds */ 690 ar9285FillVpdTable(minPwrT4[i], maxPwrT4[i], pPwrL, pVpdL, 691 AR5416_PD_GAIN_ICEPTS, vpdTableL[i]); 692 ar9285FillVpdTable(minPwrT4[i], maxPwrT4[i], pPwrR, pVpdR, 693 AR5416_PD_GAIN_ICEPTS, vpdTableR[i]); 694 695 /* Interpolate the final vpd */ 696 for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) { 697 vpdTableI[i][j] = (uint8_t)(interpolate((uint16_t)FREQ2FBIN(centers.synth_center, IEEE80211_IS_CHAN_2GHZ(chan)), 698 bChans[idxL], bChans[idxR], vpdTableL[i][j], vpdTableR[i][j])); 699 } 700 } 701 } 702 *pMinCalPower = (int16_t)(minPwrT4[0] / 2); 703 704 k = 0; /* index for the final table */ 705 for (i = 0; i < numXpdGains; i++) { 706 if (i == (numXpdGains - 1)) { 707 pPdGainBoundaries[i] = (uint16_t)(maxPwrT4[i] / 2); 708 } else { 709 pPdGainBoundaries[i] = (uint16_t)((maxPwrT4[i] + minPwrT4[i+1]) / 4); 710 } 711 712 pPdGainBoundaries[i] = (uint16_t)AH_MIN(AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]); 713 714 /* NB: only applies to owl 1.0 */ 715 if ((i == 0) && !AR_SREV_OWL_20_OR_LATER(ah) ) { 716 /* 717 * fix the gain delta, but get a delta that can be applied to min to 718 * keep the upper power values accurate, don't think max needs to 719 * be adjusted because should not be at that area of the table? 720 */ 721 minDelta = pPdGainBoundaries[0] - 23; 722 pPdGainBoundaries[0] = 23; 723 } 724 else { 725 minDelta = 0; 726 } 727 728 /* Find starting index for this pdGain */ 729 if (i == 0) { 730 if (AR_SREV_MERLIN_20_OR_LATER(ah)) 731 ss = (int16_t)(0 - (minPwrT4[i] / 2)); 732 else 733 ss = 0; /* for the first pdGain, start from index 0 */ 734 } else { 735 /* need overlap entries extrapolated below. */ 736 ss = (int16_t)((pPdGainBoundaries[i-1] - (minPwrT4[i] / 2)) - tPdGainOverlap + 1 + minDelta); 737 } 738 vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]); 739 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep); 740 /* 741 *-ve ss indicates need to extrapolate data below for this pdGain 742 */ 743 while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) { 744 tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep); 745 pPDADCValues[k++] = (uint8_t)((tmpVal < 0) ? 0 : tmpVal); 746 ss++; 747 } 748 749 sizeCurrVpdTable = (uint8_t)((maxPwrT4[i] - minPwrT4[i]) / 2 +1); 750 tgtIndex = (uint8_t)(pPdGainBoundaries[i] + tPdGainOverlap - (minPwrT4[i] / 2)); 751 maxIndex = (tgtIndex < sizeCurrVpdTable) ? tgtIndex : sizeCurrVpdTable; 752 753 while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) { 754 pPDADCValues[k++] = vpdTableI[i][ss++]; 755 } 756 757 vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] - vpdTableI[i][sizeCurrVpdTable - 2]); 758 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep); 759 /* 760 * for last gain, pdGainBoundary == Pmax_t2, so will 761 * have to extrapolate 762 */ 763 if (tgtIndex >= maxIndex) { /* need to extrapolate above */ 764 while ((ss <= tgtIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) { 765 tmpVal = (int16_t)((vpdTableI[i][sizeCurrVpdTable - 1] + 766 (ss - maxIndex +1) * vpdStep)); 767 pPDADCValues[k++] = (uint8_t)((tmpVal > 255) ? 255 : tmpVal); 768 ss++; 769 } 770 } /* extrapolated above */ 771 } /* for all pdGainUsed */ 772 773 /* Fill out pdGainBoundaries - only up to 2 allowed here, but hardware allows up to 4 */ 774 while (i < AR5416_PD_GAINS_IN_MASK) { 775 pPdGainBoundaries[i] = pPdGainBoundaries[i-1]; 776 i++; 777 } 778 779 while (k < AR5416_NUM_PDADC_VALUES) { 780 pPDADCValues[k] = pPDADCValues[k-1]; 781 k++; 782 } 783 return; 784} 785/* 786 * XXX same as ar5416FillVpdTable 787 */ 788static HAL_BOOL 789ar9285FillVpdTable(uint8_t pwrMin, uint8_t pwrMax, uint8_t *pPwrList, 790 uint8_t *pVpdList, uint16_t numIntercepts, uint8_t *pRetVpdList) 791{ 792 uint16_t i, k; 793 uint8_t currPwr = pwrMin; 794 uint16_t idxL, idxR; 795 796 HALASSERT(pwrMax > pwrMin); 797 for (i = 0; i <= (pwrMax - pwrMin) / 2; i++) { 798 getLowerUpperIndex(currPwr, pPwrList, numIntercepts, 799 &(idxL), &(idxR)); 800 if (idxR < 1) 801 idxR = 1; /* extrapolate below */ 802 if (idxL == numIntercepts - 1) 803 idxL = (uint16_t)(numIntercepts - 2); /* extrapolate above */ 804 if (pPwrList[idxL] == pPwrList[idxR]) 805 k = pVpdList[idxL]; 806 else 807 k = (uint16_t)( ((currPwr - pPwrList[idxL]) * pVpdList[idxR] + (pPwrList[idxR] - currPwr) * pVpdList[idxL]) / 808 (pPwrList[idxR] - pPwrList[idxL]) ); 809 HALASSERT(k < 256); 810 pRetVpdList[i] = (uint8_t)k; 811 currPwr += 2; /* half dB steps */ 812 } 813 814 return AH_TRUE; 815} 816static int16_t 817interpolate(uint16_t target, uint16_t srcLeft, uint16_t srcRight, 818 int16_t targetLeft, int16_t targetRight) 819{ 820 int16_t rv; 821 822 if (srcRight == srcLeft) { 823 rv = targetLeft; 824 } else { 825 rv = (int16_t)( ((target - srcLeft) * targetRight + 826 (srcRight - target) * targetLeft) / (srcRight - srcLeft) ); 827 } 828 return rv; 829} 830