ar9285_reset.c revision 208712
1/* 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar5416/ar9285_reset.c 208712 2010-06-01 15:47:57Z rpaulo $ 18 */ 19 20/* 21 * This is almost the same as ar5416_reset.c but uses the v4k EEPROM and 22 * supports only 2Ghz operation. 23 */ 24 25#include "opt_ah.h" 26 27#include "ah.h" 28#include "ah_internal.h" 29#include "ah_devid.h" 30 31#include "ah_eeprom_v14.h" 32#include "ah_eeprom_v4k.h" 33 34#include "ar5416/ar9285.h" 35#include "ar5416/ar5416.h" 36#include "ar5416/ar5416reg.h" 37#include "ar5416/ar5416phy.h" 38 39/* Eeprom versioning macros. Returns true if the version is equal or newer than the ver specified */ 40#define EEP_MINOR(_ah) \ 41 (AH_PRIVATE(_ah)->ah_eeversion & AR5416_EEP_VER_MINOR_MASK) 42#define IS_EEP_MINOR_V2(_ah) (EEP_MINOR(_ah) >= AR5416_EEP_MINOR_VER_2) 43#define IS_EEP_MINOR_V3(_ah) (EEP_MINOR(_ah) >= AR5416_EEP_MINOR_VER_3) 44 45/* Additional Time delay to wait after activiting the Base band */ 46#define BASE_ACTIVATE_DELAY 100 /* 100 usec */ 47#define PLL_SETTLE_DELAY 300 /* 300 usec */ 48#define RTC_PLL_SETTLE_DELAY 1000 /* 1 ms */ 49 50static HAL_BOOL ar9285SetPowerPerRateTable(struct ath_hal *ah, 51 struct ar5416eeprom_4k *pEepData, 52 const struct ieee80211_channel *chan, int16_t *ratesArray, 53 uint16_t cfgCtl, uint16_t AntennaReduction, 54 uint16_t twiceMaxRegulatoryPower, 55 uint16_t powerLimit); 56static HAL_BOOL ar9285SetPowerCalTable(struct ath_hal *ah, 57 struct ar5416eeprom_4k *pEepData, 58 const struct ieee80211_channel *chan, 59 int16_t *pTxPowerIndexOffset); 60static int16_t interpolate(uint16_t target, uint16_t srcLeft, 61 uint16_t srcRight, int16_t targetLeft, int16_t targetRight); 62static HAL_BOOL ar9285FillVpdTable(uint8_t, uint8_t, uint8_t *, uint8_t *, 63 uint16_t, uint8_t *); 64static void ar9285GetGainBoundariesAndPdadcs(struct ath_hal *ah, 65 const struct ieee80211_channel *chan, CAL_DATA_PER_FREQ_4K *pRawDataSet, 66 uint8_t * bChans, uint16_t availPiers, 67 uint16_t tPdGainOverlap, int16_t *pMinCalPower, 68 uint16_t * pPdGainBoundaries, uint8_t * pPDADCValues, 69 uint16_t numXpdGains); 70static HAL_BOOL getLowerUpperIndex(uint8_t target, uint8_t *pList, 71 uint16_t listSize, uint16_t *indexL, uint16_t *indexR); 72static uint16_t ar9285GetMaxEdgePower(uint16_t, CAL_CTL_EDGES *); 73 74/* XXX gag, this is sick */ 75typedef enum Ar5416_Rates { 76 rate6mb, rate9mb, rate12mb, rate18mb, 77 rate24mb, rate36mb, rate48mb, rate54mb, 78 rate1l, rate2l, rate2s, rate5_5l, 79 rate5_5s, rate11l, rate11s, rateXr, 80 rateHt20_0, rateHt20_1, rateHt20_2, rateHt20_3, 81 rateHt20_4, rateHt20_5, rateHt20_6, rateHt20_7, 82 rateHt40_0, rateHt40_1, rateHt40_2, rateHt40_3, 83 rateHt40_4, rateHt40_5, rateHt40_6, rateHt40_7, 84 rateDupCck, rateDupOfdm, rateExtCck, rateExtOfdm, 85 Ar5416RateSize 86} AR5416_RATES; 87 88HAL_BOOL 89ar9285SetTransmitPower(struct ath_hal *ah, 90 const struct ieee80211_channel *chan, uint16_t *rfXpdGain) 91{ 92#define POW_SM(_r, _s) (((_r) & 0x3f) << (_s)) 93#define N(a) (sizeof (a) / sizeof (a[0])) 94 95 MODAL_EEP4K_HEADER *pModal; 96 struct ath_hal_5212 *ahp = AH5212(ah); 97 int16_t ratesArray[Ar5416RateSize]; 98 int16_t txPowerIndexOffset = 0; 99 uint8_t ht40PowerIncForPdadc = 2; 100 int i; 101 102 uint16_t cfgCtl; 103 uint16_t powerLimit; 104 uint16_t twiceAntennaReduction; 105 uint16_t twiceMaxRegulatoryPower; 106 int16_t maxPower; 107 HAL_EEPROM_v4k *ee = AH_PRIVATE(ah)->ah_eeprom; 108 struct ar5416eeprom_4k *pEepData = &ee->ee_base; 109 110 HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER14_1); 111 112 /* Setup info for the actual eeprom */ 113 OS_MEMZERO(ratesArray, sizeof(ratesArray)); 114 cfgCtl = ath_hal_getctl(ah, chan); 115 powerLimit = chan->ic_maxregpower * 2; 116 twiceAntennaReduction = chan->ic_maxantgain; 117 twiceMaxRegulatoryPower = AH_MIN(MAX_RATE_POWER, AH_PRIVATE(ah)->ah_powerLimit); 118 pModal = &pEepData->modalHeader; 119 HALDEBUG(ah, HAL_DEBUG_RESET, "%s Channel=%u CfgCtl=%u\n", 120 __func__,chan->ic_freq, cfgCtl ); 121 122 if (IS_EEP_MINOR_V2(ah)) { 123 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc; 124 } 125 126 if (!ar9285SetPowerPerRateTable(ah, pEepData, chan, 127 &ratesArray[0],cfgCtl, 128 twiceAntennaReduction, 129 twiceMaxRegulatoryPower, powerLimit)) { 130 HALDEBUG(ah, HAL_DEBUG_ANY, 131 "%s: unable to set tx power per rate table\n", __func__); 132 return AH_FALSE; 133 } 134 135 if (!ar9285SetPowerCalTable(ah, pEepData, chan, &txPowerIndexOffset)) { 136 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unable to set power table\n", 137 __func__); 138 return AH_FALSE; 139 } 140 141 maxPower = AH_MAX(ratesArray[rate6mb], ratesArray[rateHt20_0]); 142 maxPower = AH_MAX(maxPower, ratesArray[rate1l]); 143 144 if (IEEE80211_IS_CHAN_HT40(chan)) { 145 maxPower = AH_MAX(maxPower, ratesArray[rateHt40_0]); 146 } 147 148 ahp->ah_tx6PowerInHalfDbm = maxPower; 149 AH_PRIVATE(ah)->ah_maxPowerLevel = maxPower; 150 ahp->ah_txPowerIndexOffset = txPowerIndexOffset; 151 152 /* 153 * txPowerIndexOffset is set by the SetPowerTable() call - 154 * adjust the rate table (0 offset if rates EEPROM not loaded) 155 */ 156 for (i = 0; i < N(ratesArray); i++) { 157 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]); 158 if (ratesArray[i] > AR5416_MAX_RATE_POWER) 159 ratesArray[i] = AR5416_MAX_RATE_POWER; 160 ratesArray[i] -= AR5416_PWR_TABLE_OFFSET_DB * 2; 161 } 162 163#ifdef AH_EEPROM_DUMP 164 ar5416PrintPowerPerRate(ah, ratesArray); 165#endif 166 167 /* Write the OFDM power per rate set */ 168 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE1, 169 POW_SM(ratesArray[rate18mb], 24) 170 | POW_SM(ratesArray[rate12mb], 16) 171 | POW_SM(ratesArray[rate9mb], 8) 172 | POW_SM(ratesArray[rate6mb], 0) 173 ); 174 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE2, 175 POW_SM(ratesArray[rate54mb], 24) 176 | POW_SM(ratesArray[rate48mb], 16) 177 | POW_SM(ratesArray[rate36mb], 8) 178 | POW_SM(ratesArray[rate24mb], 0) 179 ); 180 181 /* Write the CCK power per rate set */ 182 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE3, 183 POW_SM(ratesArray[rate2s], 24) 184 | POW_SM(ratesArray[rate2l], 16) 185 | POW_SM(ratesArray[rateXr], 8) /* XR target power */ 186 | POW_SM(ratesArray[rate1l], 0) 187 ); 188 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE4, 189 POW_SM(ratesArray[rate11s], 24) 190 | POW_SM(ratesArray[rate11l], 16) 191 | POW_SM(ratesArray[rate5_5s], 8) 192 | POW_SM(ratesArray[rate5_5l], 0) 193 ); 194 HALDEBUG(ah, HAL_DEBUG_RESET, 195 "%s AR_PHY_POWER_TX_RATE3=0x%x AR_PHY_POWER_TX_RATE4=0x%x\n", 196 __func__, OS_REG_READ(ah,AR_PHY_POWER_TX_RATE3), 197 OS_REG_READ(ah,AR_PHY_POWER_TX_RATE4)); 198 199 /* Write the HT20 power per rate set */ 200 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE5, 201 POW_SM(ratesArray[rateHt20_3], 24) 202 | POW_SM(ratesArray[rateHt20_2], 16) 203 | POW_SM(ratesArray[rateHt20_1], 8) 204 | POW_SM(ratesArray[rateHt20_0], 0) 205 ); 206 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE6, 207 POW_SM(ratesArray[rateHt20_7], 24) 208 | POW_SM(ratesArray[rateHt20_6], 16) 209 | POW_SM(ratesArray[rateHt20_5], 8) 210 | POW_SM(ratesArray[rateHt20_4], 0) 211 ); 212 213 if (IEEE80211_IS_CHAN_HT40(chan)) { 214 /* Write the HT40 power per rate set */ 215 /* Correct PAR difference between HT40 and HT20/LEGACY */ 216 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE7, 217 POW_SM(ratesArray[rateHt40_3] + ht40PowerIncForPdadc, 24) 218 | POW_SM(ratesArray[rateHt40_2] + ht40PowerIncForPdadc, 16) 219 | POW_SM(ratesArray[rateHt40_1] + ht40PowerIncForPdadc, 8) 220 | POW_SM(ratesArray[rateHt40_0] + ht40PowerIncForPdadc, 0) 221 ); 222 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE8, 223 POW_SM(ratesArray[rateHt40_7] + ht40PowerIncForPdadc, 24) 224 | POW_SM(ratesArray[rateHt40_6] + ht40PowerIncForPdadc, 16) 225 | POW_SM(ratesArray[rateHt40_5] + ht40PowerIncForPdadc, 8) 226 | POW_SM(ratesArray[rateHt40_4] + ht40PowerIncForPdadc, 0) 227 ); 228 /* Write the Dup/Ext 40 power per rate set */ 229 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE9, 230 POW_SM(ratesArray[rateExtOfdm], 24) 231 | POW_SM(ratesArray[rateExtCck], 16) 232 | POW_SM(ratesArray[rateDupOfdm], 8) 233 | POW_SM(ratesArray[rateDupCck], 0) 234 ); 235 } 236 237 return AH_TRUE; 238#undef POW_SM 239#undef N 240} 241 242HAL_BOOL 243ar9285SetBoardValues(struct ath_hal *ah, const struct ieee80211_channel *chan) 244{ 245 const HAL_EEPROM_v4k *ee = AH_PRIVATE(ah)->ah_eeprom; 246 const struct ar5416eeprom_4k *eep = &ee->ee_base; 247 const MODAL_EEP4K_HEADER *pModal; 248 uint8_t txRxAttenLocal = 23; 249 250 HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER14_1); 251 pModal = &eep->modalHeader; 252 253 OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon); 254 OS_REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0, pModal->antCtrlChain[0]); 255 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4, 256 (OS_REG_READ(ah, AR_PHY_TIMING_CTRL4) & 257 ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF | AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) | 258 SM(pModal->iqCalICh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) | 259 SM(pModal->iqCalQCh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF)); 260 261 if (IS_EEP_MINOR_V3(ah)) { 262 if (IEEE80211_IS_CHAN_HT40(chan)) { 263 /* Overwrite switch settling with HT40 value */ 264 OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH, 265 pModal->swSettleHt40); 266 } 267 txRxAttenLocal = pModal->txRxAttenCh[0]; 268 269 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, 270 pModal->bswMargin[0]); 271 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, AR_PHY_GAIN_2GHZ_XATTEN1_DB, 272 pModal->bswAtten[0]); 273 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN, 274 pModal->xatten2Margin[0]); 275 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, AR_PHY_GAIN_2GHZ_XATTEN2_DB, 276 pModal->xatten2Db[0]); 277 278 /* block 1 has the same values as block 0 */ 279 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000, 280 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, pModal->bswMargin[0]); 281 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000, 282 AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]); 283 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000, 284 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN, pModal->xatten2Margin[0]); 285 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000, 286 AR_PHY_GAIN_2GHZ_XATTEN2_DB, pModal->xatten2Db[0]); 287 288 } 289 OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN, 290 AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal); 291 OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN, 292 AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]); 293 294 OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000, 295 AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal); 296 OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000, 297 AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]); 298 299 if (AR_SREV_KITE_11(ah)) 300 OS_REG_WRITE(ah, AR9285_AN_TOP4, (AR9285_AN_TOP4_DEFAULT | 0x14)); 301 302 return AH_TRUE; 303} 304 305/* 306 * Helper functions common for AP/CB/XB 307 */ 308 309static HAL_BOOL 310ar9285SetPowerPerRateTable(struct ath_hal *ah, struct ar5416eeprom_4k *pEepData, 311 const struct ieee80211_channel *chan, 312 int16_t *ratesArray, uint16_t cfgCtl, 313 uint16_t AntennaReduction, 314 uint16_t twiceMaxRegulatoryPower, 315 uint16_t powerLimit) 316{ 317#define N(a) (sizeof(a)/sizeof(a[0])) 318/* Local defines to distinguish between extension and control CTL's */ 319#define EXT_ADDITIVE (0x8000) 320#define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE) 321#define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE) 322 323 uint16_t twiceMaxEdgePower = AR5416_MAX_RATE_POWER; 324 int i; 325 int16_t twiceLargestAntenna; 326 CAL_CTL_DATA_4K *rep; 327 CAL_TARGET_POWER_LEG targetPowerOfdm, targetPowerCck = {0, {0, 0, 0, 0}}; 328 CAL_TARGET_POWER_LEG targetPowerOfdmExt = {0, {0, 0, 0, 0}}, targetPowerCckExt = {0, {0, 0, 0, 0}}; 329 CAL_TARGET_POWER_HT targetPowerHt20, targetPowerHt40 = {0, {0, 0, 0, 0}}; 330 int16_t scaledPower, minCtlPower; 331 332#define SUB_NUM_CTL_MODES_AT_2G_40 3 /* excluding HT40, EXT-OFDM, EXT-CCK */ 333 static const uint16_t ctlModesFor11g[] = { 334 CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40 335 }; 336 const uint16_t *pCtlMode; 337 uint16_t numCtlModes, ctlMode, freq; 338 CHAN_CENTERS centers; 339 340 ar5416GetChannelCenters(ah, chan, ¢ers); 341 342 /* Compute TxPower reduction due to Antenna Gain */ 343 344 twiceLargestAntenna = pEepData->modalHeader.antennaGainCh[0]; 345 twiceLargestAntenna = (int16_t)AH_MIN((AntennaReduction) - twiceLargestAntenna, 0); 346 347 /* XXX setup for 5212 use (really used?) */ 348 ath_hal_eepromSet(ah, AR_EEP_ANTGAINMAX_2, twiceLargestAntenna); 349 350 /* 351 * scaledPower is the minimum of the user input power level and 352 * the regulatory allowed power level 353 */ 354 scaledPower = AH_MIN(powerLimit, twiceMaxRegulatoryPower + twiceLargestAntenna); 355 356 /* Get target powers from EEPROM - our baseline for TX Power */ 357 /* Setup for CTL modes */ 358 numCtlModes = N(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40; /* CTL_11B, CTL_11G, CTL_2GHT20 */ 359 pCtlMode = ctlModesFor11g; 360 361 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPowerCck, 362 AR5416_4K_NUM_2G_CCK_TARGET_POWERS, &targetPowerCck, 4, AH_FALSE); 363 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower2G, 364 AR5416_4K_NUM_2G_20_TARGET_POWERS, &targetPowerOfdm, 4, AH_FALSE); 365 ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower2GHT20, 366 AR5416_4K_NUM_2G_20_TARGET_POWERS, &targetPowerHt20, 8, AH_FALSE); 367 368 if (IEEE80211_IS_CHAN_HT40(chan)) { 369 numCtlModes = N(ctlModesFor11g); /* All 2G CTL's */ 370 371 ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower2GHT40, 372 AR5416_4K_NUM_2G_40_TARGET_POWERS, &targetPowerHt40, 8, AH_TRUE); 373 /* Get target powers for extension channels */ 374 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPowerCck, 375 AR5416_4K_NUM_2G_CCK_TARGET_POWERS, &targetPowerCckExt, 4, AH_TRUE); 376 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower2G, 377 AR5416_4K_NUM_2G_20_TARGET_POWERS, &targetPowerOfdmExt, 4, AH_TRUE); 378 } 379 380 /* 381 * For MIMO, need to apply regulatory caps individually across dynamically 382 * running modes: CCK, OFDM, HT20, HT40 383 * 384 * The outer loop walks through each possible applicable runtime mode. 385 * The inner loop walks through each ctlIndex entry in EEPROM. 386 * The ctl value is encoded as [7:4] == test group, [3:0] == test mode. 387 * 388 */ 389 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) { 390 HAL_BOOL isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) || 391 (pCtlMode[ctlMode] == CTL_2GHT40); 392 if (isHt40CtlMode) { 393 freq = centers.ctl_center; 394 } else if (pCtlMode[ctlMode] & EXT_ADDITIVE) { 395 freq = centers.ext_center; 396 } else { 397 freq = centers.ctl_center; 398 } 399 400 /* walk through each CTL index stored in EEPROM */ 401 for (i = 0; (i < AR5416_4K_NUM_CTLS) && pEepData->ctlIndex[i]; i++) { 402 uint16_t twiceMinEdgePower; 403 404 /* compare test group from regulatory channel list with test mode from pCtlMode list */ 405 if ((((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == pEepData->ctlIndex[i]) || 406 (((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == 407 ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))) { 408 rep = &(pEepData->ctlData[i]); 409 twiceMinEdgePower = ar9285GetMaxEdgePower(freq, 410 rep->ctlEdges[ 411 owl_get_ntxchains(AH5416(ah)->ah_tx_chainmask) - 1]); 412 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) { 413 /* Find the minimum of all CTL edge powers that apply to this channel */ 414 twiceMaxEdgePower = AH_MIN(twiceMaxEdgePower, twiceMinEdgePower); 415 } else { 416 /* specific */ 417 twiceMaxEdgePower = twiceMinEdgePower; 418 break; 419 } 420 } 421 } 422 minCtlPower = (uint8_t)AH_MIN(twiceMaxEdgePower, scaledPower); 423 /* Apply ctl mode to correct target power set */ 424 switch(pCtlMode[ctlMode]) { 425 case CTL_11B: 426 for (i = 0; i < N(targetPowerCck.tPow2x); i++) { 427 targetPowerCck.tPow2x[i] = (uint8_t)AH_MIN(targetPowerCck.tPow2x[i], minCtlPower); 428 } 429 break; 430 case CTL_11A: 431 case CTL_11G: 432 for (i = 0; i < N(targetPowerOfdm.tPow2x); i++) { 433 targetPowerOfdm.tPow2x[i] = (uint8_t)AH_MIN(targetPowerOfdm.tPow2x[i], minCtlPower); 434 } 435 break; 436 case CTL_5GHT20: 437 case CTL_2GHT20: 438 for (i = 0; i < N(targetPowerHt20.tPow2x); i++) { 439 targetPowerHt20.tPow2x[i] = (uint8_t)AH_MIN(targetPowerHt20.tPow2x[i], minCtlPower); 440 } 441 break; 442 case CTL_11B_EXT: 443 targetPowerCckExt.tPow2x[0] = (uint8_t)AH_MIN(targetPowerCckExt.tPow2x[0], minCtlPower); 444 break; 445 case CTL_11G_EXT: 446 targetPowerOfdmExt.tPow2x[0] = (uint8_t)AH_MIN(targetPowerOfdmExt.tPow2x[0], minCtlPower); 447 break; 448 case CTL_5GHT40: 449 case CTL_2GHT40: 450 for (i = 0; i < N(targetPowerHt40.tPow2x); i++) { 451 targetPowerHt40.tPow2x[i] = (uint8_t)AH_MIN(targetPowerHt40.tPow2x[i], minCtlPower); 452 } 453 break; 454 default: 455 return AH_FALSE; 456 break; 457 } 458 } /* end ctl mode checking */ 459 460 /* Set rates Array from collected data */ 461 ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] = ratesArray[rate18mb] = ratesArray[rate24mb] = targetPowerOfdm.tPow2x[0]; 462 ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1]; 463 ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2]; 464 ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3]; 465 ratesArray[rateXr] = targetPowerOfdm.tPow2x[0]; 466 467 for (i = 0; i < N(targetPowerHt20.tPow2x); i++) { 468 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i]; 469 } 470 471 ratesArray[rate1l] = targetPowerCck.tPow2x[0]; 472 ratesArray[rate2s] = ratesArray[rate2l] = targetPowerCck.tPow2x[1]; 473 ratesArray[rate5_5s] = ratesArray[rate5_5l] = targetPowerCck.tPow2x[2]; 474 ratesArray[rate11s] = ratesArray[rate11l] = targetPowerCck.tPow2x[3]; 475 if (IEEE80211_IS_CHAN_HT40(chan)) { 476 for (i = 0; i < N(targetPowerHt40.tPow2x); i++) { 477 ratesArray[rateHt40_0 + i] = targetPowerHt40.tPow2x[i]; 478 } 479 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0]; 480 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0]; 481 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0]; 482 if (IEEE80211_IS_CHAN_2GHZ(chan)) { 483 ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0]; 484 } 485 } 486 return AH_TRUE; 487#undef EXT_ADDITIVE 488#undef CTL_11G_EXT 489#undef CTL_11B_EXT 490#undef SUB_NUM_CTL_MODES_AT_2G_40 491#undef N 492} 493 494/************************************************************************** 495 * fbin2freq 496 * 497 * Get channel value from binary representation held in eeprom 498 * RETURNS: the frequency in MHz 499 */ 500static uint16_t 501fbin2freq(uint8_t fbin) 502{ 503 /* 504 * Reserved value 0xFF provides an empty definition both as 505 * an fbin and as a frequency - do not convert 506 */ 507 if (fbin == AR5416_BCHAN_UNUSED) { 508 return fbin; 509 } 510 511 return (uint16_t)(2300 + fbin); 512} 513 514/* 515 * XXX almost the same as ar5416GetMaxEdgePower. 516 */ 517static uint16_t 518ar9285GetMaxEdgePower(uint16_t freq, CAL_CTL_EDGES *pRdEdgesPower) 519{ 520 uint16_t twiceMaxEdgePower = AR5416_MAX_RATE_POWER; 521 int i; 522 523 /* Get the edge power */ 524 for (i = 0; (i < AR5416_NUM_BAND_EDGES) && (pRdEdgesPower[i].bChannel != AR5416_BCHAN_UNUSED) ; i++) { 525 /* 526 * If there's an exact channel match or an inband flag set 527 * on the lower channel use the given rdEdgePower 528 */ 529 if (freq == fbin2freq(pRdEdgesPower[i].bChannel)) { 530 twiceMaxEdgePower = MS(pRdEdgesPower[i].tPowerFlag, CAL_CTL_EDGES_POWER); 531 break; 532 } else if ((i > 0) && (freq < fbin2freq(pRdEdgesPower[i].bChannel))) { 533 if (fbin2freq(pRdEdgesPower[i - 1].bChannel) < freq && (pRdEdgesPower[i - 1].tPowerFlag & CAL_CTL_EDGES_FLAG) != 0) { 534 twiceMaxEdgePower = MS(pRdEdgesPower[i - 1].tPowerFlag, CAL_CTL_EDGES_POWER); 535 } 536 /* Leave loop - no more affecting edges possible in this monotonic increasing list */ 537 break; 538 } 539 } 540 HALASSERT(twiceMaxEdgePower > 0); 541 return twiceMaxEdgePower; 542} 543 544 545 546static HAL_BOOL 547ar9285SetPowerCalTable(struct ath_hal *ah, struct ar5416eeprom_4k *pEepData, 548 const struct ieee80211_channel *chan, int16_t *pTxPowerIndexOffset) 549{ 550 CAL_DATA_PER_FREQ_4K *pRawDataset; 551 uint8_t *pCalBChans = AH_NULL; 552 uint16_t pdGainOverlap_t2; 553 static uint8_t pdadcValues[AR5416_NUM_PDADC_VALUES]; 554 uint16_t gainBoundaries[AR5416_PD_GAINS_IN_MASK]; 555 uint16_t numPiers, i, j; 556 int16_t tMinCalPower; 557 uint16_t numXpdGain, xpdMask; 558 uint16_t xpdGainValues[AR5416_4K_NUM_PD_GAINS]; 559 uint32_t reg32, regOffset, regChainOffset; 560 561 OS_MEMZERO(xpdGainValues, sizeof(xpdGainValues)); 562 563 xpdMask = pEepData->modalHeader.xpdGain; 564 565 if (IS_EEP_MINOR_V2(ah)) { 566 pdGainOverlap_t2 = pEepData->modalHeader.pdGainOverlap; 567 } else { 568 pdGainOverlap_t2 = (uint16_t)(MS(OS_REG_READ(ah, AR_PHY_TPCRG5), AR_PHY_TPCRG5_PD_GAIN_OVERLAP)); 569 } 570 571 pCalBChans = pEepData->calFreqPier2G; 572 numPiers = AR5416_4K_NUM_2G_CAL_PIERS; 573 numXpdGain = 0; 574 /* Calculate the value of xpdgains from the xpdGain Mask */ 575 for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) { 576 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) { 577 if (numXpdGain >= AR5416_4K_NUM_PD_GAINS) { 578 HALASSERT(0); 579 break; 580 } 581 xpdGainValues[numXpdGain] = (uint16_t)(AR5416_PD_GAINS_IN_MASK - i); 582 numXpdGain++; 583 } 584 } 585 586 /* Write the detector gain biases and their number */ 587 OS_REG_WRITE(ah, AR_PHY_TPCRG1, (OS_REG_READ(ah, AR_PHY_TPCRG1) & 588 ~(AR_PHY_TPCRG1_NUM_PD_GAIN | AR_PHY_TPCRG1_PD_GAIN_1 | AR_PHY_TPCRG1_PD_GAIN_2 | AR_PHY_TPCRG1_PD_GAIN_3)) | 589 SM(numXpdGain - 1, AR_PHY_TPCRG1_NUM_PD_GAIN) | SM(xpdGainValues[0], AR_PHY_TPCRG1_PD_GAIN_1 ) | 590 SM(xpdGainValues[1], AR_PHY_TPCRG1_PD_GAIN_2) | SM(0, AR_PHY_TPCRG1_PD_GAIN_3)); 591 592 for (i = 0; i < AR5416_MAX_CHAINS; i++) { 593 594 if (AR_SREV_OWL_20_OR_LATER(ah) && 595 ( AH5416(ah)->ah_rx_chainmask == 0x5 || AH5416(ah)->ah_tx_chainmask == 0x5) && (i != 0)) { 596 /* Regs are swapped from chain 2 to 1 for 5416 2_0 with 597 * only chains 0 and 2 populated 598 */ 599 regChainOffset = (i == 1) ? 0x2000 : 0x1000; 600 } else { 601 regChainOffset = i * 0x1000; 602 } 603 604 if (pEepData->baseEepHeader.txMask & (1 << i)) { 605 pRawDataset = pEepData->calPierData2G[i]; 606 607 ar9285GetGainBoundariesAndPdadcs(ah, chan, pRawDataset, 608 pCalBChans, numPiers, 609 pdGainOverlap_t2, 610 &tMinCalPower, gainBoundaries, 611 pdadcValues, numXpdGain); 612 613 if ((i == 0) || AR_SREV_OWL_20_OR_LATER(ah)) { 614 /* 615 * Note the pdadc table may not start at 0 dBm power, could be 616 * negative or greater than 0. Need to offset the power 617 * values by the amount of minPower for griffin 618 */ 619 620 OS_REG_WRITE(ah, AR_PHY_TPCRG5 + regChainOffset, 621 SM(pdGainOverlap_t2, AR_PHY_TPCRG5_PD_GAIN_OVERLAP) | 622 SM(gainBoundaries[0], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1) | 623 SM(gainBoundaries[1], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2) | 624 SM(gainBoundaries[2], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3) | 625 SM(gainBoundaries[3], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4)); 626 } 627 628 /* Write the power values into the baseband power table */ 629 regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset; 630 631 for (j = 0; j < 32; j++) { 632 reg32 = ((pdadcValues[4*j + 0] & 0xFF) << 0) | 633 ((pdadcValues[4*j + 1] & 0xFF) << 8) | 634 ((pdadcValues[4*j + 2] & 0xFF) << 16) | 635 ((pdadcValues[4*j + 3] & 0xFF) << 24) ; 636 OS_REG_WRITE(ah, regOffset, reg32); 637 638#ifdef PDADC_DUMP 639 ath_hal_printf(ah, "PDADC: Chain %d | PDADC %3d Value %3d | PDADC %3d Value %3d | PDADC %3d Value %3d | PDADC %3d Value %3d |\n", 640 i, 641 4*j, pdadcValues[4*j], 642 4*j+1, pdadcValues[4*j + 1], 643 4*j+2, pdadcValues[4*j + 2], 644 4*j+3, pdadcValues[4*j + 3]); 645#endif 646 regOffset += 4; 647 } 648 } 649 } 650 *pTxPowerIndexOffset = 0; 651 652 return AH_TRUE; 653} 654 655static void 656ar9285GetGainBoundariesAndPdadcs(struct ath_hal *ah, 657 const struct ieee80211_channel *chan, 658 CAL_DATA_PER_FREQ_4K *pRawDataSet, 659 uint8_t * bChans, uint16_t availPiers, 660 uint16_t tPdGainOverlap, int16_t *pMinCalPower, uint16_t * pPdGainBoundaries, 661 uint8_t * pPDADCValues, uint16_t numXpdGains) 662{ 663 664 int i, j, k; 665 int16_t ss; /* potentially -ve index for taking care of pdGainOverlap */ 666 uint16_t idxL, idxR, numPiers; /* Pier indexes */ 667 668 /* filled out Vpd table for all pdGains (chanL) */ 669 static uint8_t vpdTableL[AR5416_4K_NUM_PD_GAINS][AR5416_MAX_PWR_RANGE_IN_HALF_DB]; 670 671 /* filled out Vpd table for all pdGains (chanR) */ 672 static uint8_t vpdTableR[AR5416_4K_NUM_PD_GAINS][AR5416_MAX_PWR_RANGE_IN_HALF_DB]; 673 674 /* filled out Vpd table for all pdGains (interpolated) */ 675 static uint8_t vpdTableI[AR5416_4K_NUM_PD_GAINS][AR5416_MAX_PWR_RANGE_IN_HALF_DB]; 676 677 uint8_t *pVpdL, *pVpdR, *pPwrL, *pPwrR; 678 uint8_t minPwrT4[AR5416_4K_NUM_PD_GAINS]; 679 uint8_t maxPwrT4[AR5416_4K_NUM_PD_GAINS]; 680 int16_t vpdStep; 681 int16_t tmpVal; 682 uint16_t sizeCurrVpdTable, maxIndex, tgtIndex; 683 HAL_BOOL match; 684 int16_t minDelta = 0; 685 CHAN_CENTERS centers; 686 687 ar5416GetChannelCenters(ah, chan, ¢ers); 688 689 /* Trim numPiers for the number of populated channel Piers */ 690 for (numPiers = 0; numPiers < availPiers; numPiers++) { 691 if (bChans[numPiers] == AR5416_BCHAN_UNUSED) { 692 break; 693 } 694 } 695 696 /* Find pier indexes around the current channel */ 697 match = getLowerUpperIndex((uint8_t)FREQ2FBIN(centers.synth_center, IEEE80211_IS_CHAN_2GHZ(chan)), 698 bChans, numPiers, &idxL, &idxR); 699 700 if (match) { 701 /* Directly fill both vpd tables from the matching index */ 702 for (i = 0; i < numXpdGains; i++) { 703 minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0]; 704 maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4]; 705 ar9285FillVpdTable(minPwrT4[i], maxPwrT4[i], 706 pRawDataSet[idxL].pwrPdg[i], 707 pRawDataSet[idxL].vpdPdg[i], 708 AR5416_PD_GAIN_ICEPTS, vpdTableI[i]); 709 } 710 } else { 711 for (i = 0; i < numXpdGains; i++) { 712 pVpdL = pRawDataSet[idxL].vpdPdg[i]; 713 pPwrL = pRawDataSet[idxL].pwrPdg[i]; 714 pVpdR = pRawDataSet[idxR].vpdPdg[i]; 715 pPwrR = pRawDataSet[idxR].pwrPdg[i]; 716 717 /* Start Vpd interpolation from the max of the minimum powers */ 718 minPwrT4[i] = AH_MAX(pPwrL[0], pPwrR[0]); 719 720 /* End Vpd interpolation from the min of the max powers */ 721 maxPwrT4[i] = AH_MIN(pPwrL[AR5416_PD_GAIN_ICEPTS - 1], pPwrR[AR5416_PD_GAIN_ICEPTS - 1]); 722 HALASSERT(maxPwrT4[i] > minPwrT4[i]); 723 724 /* Fill pier Vpds */ 725 ar9285FillVpdTable(minPwrT4[i], maxPwrT4[i], pPwrL, pVpdL, 726 AR5416_PD_GAIN_ICEPTS, vpdTableL[i]); 727 ar9285FillVpdTable(minPwrT4[i], maxPwrT4[i], pPwrR, pVpdR, 728 AR5416_PD_GAIN_ICEPTS, vpdTableR[i]); 729 730 /* Interpolate the final vpd */ 731 for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) { 732 vpdTableI[i][j] = (uint8_t)(interpolate((uint16_t)FREQ2FBIN(centers.synth_center, IEEE80211_IS_CHAN_2GHZ(chan)), 733 bChans[idxL], bChans[idxR], vpdTableL[i][j], vpdTableR[i][j])); 734 } 735 } 736 } 737 *pMinCalPower = (int16_t)(minPwrT4[0] / 2); 738 739 k = 0; /* index for the final table */ 740 for (i = 0; i < numXpdGains; i++) { 741 if (i == (numXpdGains - 1)) { 742 pPdGainBoundaries[i] = (uint16_t)(maxPwrT4[i] / 2); 743 } else { 744 pPdGainBoundaries[i] = (uint16_t)((maxPwrT4[i] + minPwrT4[i+1]) / 4); 745 } 746 747 pPdGainBoundaries[i] = (uint16_t)AH_MIN(AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]); 748 749 /* NB: only applies to owl 1.0 */ 750 if ((i == 0) && !AR_SREV_OWL_20_OR_LATER(ah) ) { 751 /* 752 * fix the gain delta, but get a delta that can be applied to min to 753 * keep the upper power values accurate, don't think max needs to 754 * be adjusted because should not be at that area of the table? 755 */ 756 minDelta = pPdGainBoundaries[0] - 23; 757 pPdGainBoundaries[0] = 23; 758 } 759 else { 760 minDelta = 0; 761 } 762 763 /* Find starting index for this pdGain */ 764 if (i == 0) { 765 ss = 0; /* for the first pdGain, start from index 0 */ 766 } else { 767 /* need overlap entries extrapolated below. */ 768 ss = (int16_t)((pPdGainBoundaries[i-1] - (minPwrT4[i] / 2)) - tPdGainOverlap + 1 + minDelta); 769 } 770 vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]); 771 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep); 772 /* 773 *-ve ss indicates need to extrapolate data below for this pdGain 774 */ 775 while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) { 776 tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep); 777 pPDADCValues[k++] = (uint8_t)((tmpVal < 0) ? 0 : tmpVal); 778 ss++; 779 } 780 781 sizeCurrVpdTable = (uint8_t)((maxPwrT4[i] - minPwrT4[i]) / 2 +1); 782 tgtIndex = (uint8_t)(pPdGainBoundaries[i] + tPdGainOverlap - (minPwrT4[i] / 2)); 783 maxIndex = (tgtIndex < sizeCurrVpdTable) ? tgtIndex : sizeCurrVpdTable; 784 785 while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) { 786 pPDADCValues[k++] = vpdTableI[i][ss++]; 787 } 788 789 vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] - vpdTableI[i][sizeCurrVpdTable - 2]); 790 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep); 791 /* 792 * for last gain, pdGainBoundary == Pmax_t2, so will 793 * have to extrapolate 794 */ 795 if (tgtIndex > maxIndex) { /* need to extrapolate above */ 796 while ((ss <= tgtIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) { 797 tmpVal = (int16_t)((vpdTableI[i][sizeCurrVpdTable - 1] + 798 (ss - maxIndex +1) * vpdStep)); 799 pPDADCValues[k++] = (uint8_t)((tmpVal > 255) ? 255 : tmpVal); 800 ss++; 801 } 802 } /* extrapolated above */ 803 } /* for all pdGainUsed */ 804 805 /* Fill out pdGainBoundaries - only up to 2 allowed here, but hardware allows up to 4 */ 806 while (i < AR5416_PD_GAINS_IN_MASK) { 807 pPdGainBoundaries[i] = pPdGainBoundaries[i-1]; 808 i++; 809 } 810 811 while (k < AR5416_NUM_PDADC_VALUES) { 812 pPDADCValues[k] = pPDADCValues[k-1]; 813 k++; 814 } 815 return; 816} 817/* 818 * XXX same as ar5416FillVpdTable 819 */ 820static HAL_BOOL 821ar9285FillVpdTable(uint8_t pwrMin, uint8_t pwrMax, uint8_t *pPwrList, 822 uint8_t *pVpdList, uint16_t numIntercepts, uint8_t *pRetVpdList) 823{ 824 uint16_t i, k; 825 uint8_t currPwr = pwrMin; 826 uint16_t idxL, idxR; 827 828 HALASSERT(pwrMax > pwrMin); 829 for (i = 0; i <= (pwrMax - pwrMin) / 2; i++) { 830 getLowerUpperIndex(currPwr, pPwrList, numIntercepts, 831 &(idxL), &(idxR)); 832 if (idxR < 1) 833 idxR = 1; /* extrapolate below */ 834 if (idxL == numIntercepts - 1) 835 idxL = (uint16_t)(numIntercepts - 2); /* extrapolate above */ 836 if (pPwrList[idxL] == pPwrList[idxR]) 837 k = pVpdList[idxL]; 838 else 839 k = (uint16_t)( ((currPwr - pPwrList[idxL]) * pVpdList[idxR] + (pPwrList[idxR] - currPwr) * pVpdList[idxL]) / 840 (pPwrList[idxR] - pPwrList[idxL]) ); 841 HALASSERT(k < 256); 842 pRetVpdList[i] = (uint8_t)k; 843 currPwr += 2; /* half dB steps */ 844 } 845 846 return AH_TRUE; 847} 848static int16_t 849interpolate(uint16_t target, uint16_t srcLeft, uint16_t srcRight, 850 int16_t targetLeft, int16_t targetRight) 851{ 852 int16_t rv; 853 854 if (srcRight == srcLeft) { 855 rv = targetLeft; 856 } else { 857 rv = (int16_t)( ((target - srcLeft) * targetRight + 858 (srcRight - target) * targetLeft) / (srcRight - srcLeft) ); 859 } 860 return rv; 861} 862 863HAL_BOOL 864getLowerUpperIndex(uint8_t target, uint8_t *pList, uint16_t listSize, 865 uint16_t *indexL, uint16_t *indexR) 866{ 867 uint16_t i; 868 869 /* 870 * Check first and last elements for beyond ordered array cases. 871 */ 872 if (target <= pList[0]) { 873 *indexL = *indexR = 0; 874 return AH_TRUE; 875 } 876 if (target >= pList[listSize-1]) { 877 *indexL = *indexR = (uint16_t)(listSize - 1); 878 return AH_TRUE; 879 } 880 881 /* look for value being near or between 2 values in list */ 882 for (i = 0; i < listSize - 1; i++) { 883 /* 884 * If value is close to the current value of the list 885 * then target is not between values, it is one of the values 886 */ 887 if (pList[i] == target) { 888 *indexL = *indexR = i; 889 return AH_TRUE; 890 } 891 /* 892 * Look for value being between current value and next value 893 * if so return these 2 values 894 */ 895 if (target < pList[i + 1]) { 896 *indexL = i; 897 *indexR = (uint16_t)(i + 1); 898 return AH_FALSE; 899 } 900 } 901 HALASSERT(0); 902 *indexL = *indexR = 0; 903 return AH_FALSE; 904} 905