1331722Seadler/* 2220593Sadrian * Copyright (c) 2008-2010 Atheros Communications Inc. 3220593Sadrian * Copyright (c) 2011 Adrian Chadd, Xenion Pty Ltd. 4220593Sadrian * 5220593Sadrian * Redistribution and use in source and binary forms, with or without 6220593Sadrian * modification, are permitted provided that the following conditions 7220593Sadrian * are met: 8220593Sadrian * 1. Redistributions of source code must retain the above copyright 9220593Sadrian * notice, this list of conditions and the following disclaimer. 10220593Sadrian * 2. Redistributions in binary form must reproduce the above copyright 11220593Sadrian * notice, this list of conditions and the following disclaimer in the 12220593Sadrian * documentation and/or other materials provided with the distribution. 13220593Sadrian * 14220593Sadrian * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15220593Sadrian * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16220593Sadrian * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17220593Sadrian * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18220593Sadrian * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19220593Sadrian * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20220593Sadrian * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21220593Sadrian * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22220593Sadrian * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23220593Sadrian * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24220593Sadrian * SUCH DAMAGE. 25220593Sadrian * 26220593Sadrian * $FreeBSD$ 27220593Sadrian */ 28220593Sadrian#include "opt_ah.h" 29220593Sadrian 30220593Sadrian#include "ah.h" 31220593Sadrian#include "ah_desc.h" 32220593Sadrian#include "ah_internal.h" 33220593Sadrian#include "ah_eeprom_v4k.h" 34220593Sadrian 35220593Sadrian#include "ar9002/ar9280.h" 36220593Sadrian#include "ar9002/ar9285.h" 37220593Sadrian#include "ar5416/ar5416reg.h" 38220593Sadrian#include "ar5416/ar5416phy.h" 39220593Sadrian#include "ar9002/ar9285phy.h" 40220593Sadrian#include "ar9002/ar9285_phy.h" 41220593Sadrian 42251655Sadrian#include "ar9002/ar9285_diversity.h" 43220593Sadrian 44220593Sadrian/* 45221694Sadrian * Set the antenna switch to control RX antenna diversity. 46221694Sadrian * 47221694Sadrian * If a fixed configuration is used, the LNA and div bias 48221694Sadrian * settings are fixed and the antenna diversity scanning routine 49221694Sadrian * is disabled. 50221694Sadrian * 51221694Sadrian * If a variable configuration is used, a default is programmed 52221694Sadrian * in and sampling commences per RXed packet. 53221694Sadrian * 54221694Sadrian * Since this is called from ar9285SetBoardValues() to setup 55221694Sadrian * diversity, it means that after a reset or scan, any current 56221694Sadrian * software diversity combining settings will be lost and won't 57221694Sadrian * re-appear until after the first successful sample run. 58221694Sadrian * Please keep this in mind if you're seeing weird performance 59221694Sadrian * that happens to relate to scan/diversity timing. 60221694Sadrian */ 61221694SadrianHAL_BOOL 62221694Sadrianar9285SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING settings) 63221694Sadrian{ 64221694Sadrian int regVal; 65221694Sadrian const HAL_EEPROM_v4k *ee = AH_PRIVATE(ah)->ah_eeprom; 66221694Sadrian const MODAL_EEP4K_HEADER *pModal = &ee->ee_base.modalHeader; 67221694Sadrian uint8_t ant_div_control1, ant_div_control2; 68221694Sadrian 69221694Sadrian if (pModal->version < 3) { 70221694Sadrian HALDEBUG(ah, HAL_DEBUG_DIVERSITY, "%s: not supported\n", 71221694Sadrian __func__); 72221694Sadrian return AH_FALSE; /* Can't do diversity */ 73221694Sadrian } 74221694Sadrian 75221694Sadrian /* Store settings */ 76221694Sadrian AH5212(ah)->ah_antControl = settings; 77221694Sadrian AH5212(ah)->ah_diversity = (settings == HAL_ANT_VARIABLE); 78221694Sadrian 79221694Sadrian /* XXX don't fiddle if the PHY is in sleep mode or ! chan */ 80221694Sadrian 81221694Sadrian /* Begin setting the relevant registers */ 82221694Sadrian 83221694Sadrian ant_div_control1 = pModal->antdiv_ctl1; 84221694Sadrian ant_div_control2 = pModal->antdiv_ctl2; 85221694Sadrian 86221694Sadrian regVal = OS_REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); 87221694Sadrian regVal &= (~(AR_PHY_9285_ANT_DIV_CTL_ALL)); 88221694Sadrian 89221694Sadrian /* enable antenna diversity only if diversityControl == HAL_ANT_VARIABLE */ 90221694Sadrian if (settings == HAL_ANT_VARIABLE) 91221694Sadrian regVal |= SM(ant_div_control1, AR_PHY_9285_ANT_DIV_CTL); 92221694Sadrian 93221694Sadrian if (settings == HAL_ANT_VARIABLE) { 94221694Sadrian HALDEBUG(ah, HAL_DEBUG_DIVERSITY, "%s: HAL_ANT_VARIABLE\n", 95221694Sadrian __func__); 96221694Sadrian regVal |= SM(ant_div_control2, AR_PHY_9285_ANT_DIV_ALT_LNACONF); 97221694Sadrian regVal |= SM((ant_div_control2 >> 2), AR_PHY_9285_ANT_DIV_MAIN_LNACONF); 98221694Sadrian regVal |= SM((ant_div_control1 >> 1), AR_PHY_9285_ANT_DIV_ALT_GAINTB); 99221694Sadrian regVal |= SM((ant_div_control1 >> 2), AR_PHY_9285_ANT_DIV_MAIN_GAINTB); 100221694Sadrian } else { 101221694Sadrian if (settings == HAL_ANT_FIXED_A) { 102221694Sadrian /* Diversity disabled, RX = LNA1 */ 103221694Sadrian HALDEBUG(ah, HAL_DEBUG_DIVERSITY, "%s: HAL_ANT_FIXED_A\n", 104221694Sadrian __func__); 105239890Sadrian regVal |= SM(HAL_ANT_DIV_COMB_LNA2, AR_PHY_9285_ANT_DIV_ALT_LNACONF); 106239890Sadrian regVal |= SM(HAL_ANT_DIV_COMB_LNA1, AR_PHY_9285_ANT_DIV_MAIN_LNACONF); 107221694Sadrian regVal |= SM(AR_PHY_9285_ANT_DIV_GAINTB_0, AR_PHY_9285_ANT_DIV_ALT_GAINTB); 108221694Sadrian regVal |= SM(AR_PHY_9285_ANT_DIV_GAINTB_1, AR_PHY_9285_ANT_DIV_MAIN_GAINTB); 109221694Sadrian } 110221694Sadrian else if (settings == HAL_ANT_FIXED_B) { 111221694Sadrian /* Diversity disabled, RX = LNA2 */ 112221694Sadrian HALDEBUG(ah, HAL_DEBUG_DIVERSITY, "%s: HAL_ANT_FIXED_B\n", 113221694Sadrian __func__); 114239890Sadrian regVal |= SM(HAL_ANT_DIV_COMB_LNA1, AR_PHY_9285_ANT_DIV_ALT_LNACONF); 115239890Sadrian regVal |= SM(HAL_ANT_DIV_COMB_LNA2, AR_PHY_9285_ANT_DIV_MAIN_LNACONF); 116221694Sadrian regVal |= SM(AR_PHY_9285_ANT_DIV_GAINTB_1, AR_PHY_9285_ANT_DIV_ALT_GAINTB); 117221694Sadrian regVal |= SM(AR_PHY_9285_ANT_DIV_GAINTB_0, AR_PHY_9285_ANT_DIV_MAIN_GAINTB); 118221694Sadrian } 119221694Sadrian } 120221694Sadrian 121221694Sadrian OS_REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regVal); 122221694Sadrian regVal = OS_REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); 123221694Sadrian regVal = OS_REG_READ(ah, AR_PHY_CCK_DETECT); 124221694Sadrian regVal &= (~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV); 125221694Sadrian if (settings == HAL_ANT_VARIABLE) 126221694Sadrian regVal |= SM((ant_div_control1 >> 3), AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV); 127221694Sadrian 128221694Sadrian OS_REG_WRITE(ah, AR_PHY_CCK_DETECT, regVal); 129221694Sadrian regVal = OS_REG_READ(ah, AR_PHY_CCK_DETECT); 130221694Sadrian 131221694Sadrian /* 132221694Sadrian * If Diversity combining is available and the diversity setting 133221694Sadrian * is to allow variable diversity, enable it by default. 134221694Sadrian * 135221694Sadrian * This will be eventually overridden by the software antenna 136221694Sadrian * diversity logic. 137221694Sadrian * 138221694Sadrian * Note that yes, this following section overrides the above 139221694Sadrian * settings for the LNA configuration and fast-bias. 140221694Sadrian */ 141221694Sadrian if (ar9285_check_div_comb(ah) && AH5212(ah)->ah_diversity == AH_TRUE) { 142221694Sadrian // If support DivComb, set MAIN to LNA1 and ALT to LNA2 at the first beginning 143221694Sadrian HALDEBUG(ah, HAL_DEBUG_DIVERSITY, 144221694Sadrian "%s: Enable initial settings for combined diversity\n", 145221694Sadrian __func__); 146221694Sadrian regVal = OS_REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); 147221694Sadrian regVal &= (~(AR_PHY_9285_ANT_DIV_MAIN_LNACONF | AR_PHY_9285_ANT_DIV_ALT_LNACONF)); 148239890Sadrian regVal |= (HAL_ANT_DIV_COMB_LNA1 << AR_PHY_9285_ANT_DIV_MAIN_LNACONF_S); 149239890Sadrian regVal |= (HAL_ANT_DIV_COMB_LNA2 << AR_PHY_9285_ANT_DIV_ALT_LNACONF_S); 150221694Sadrian regVal &= (~(AR_PHY_9285_FAST_DIV_BIAS)); 151221694Sadrian regVal |= (0 << AR_PHY_9285_FAST_DIV_BIAS_S); 152221694Sadrian OS_REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regVal); 153221694Sadrian } 154221694Sadrian 155221694Sadrian return AH_TRUE; 156221694Sadrian} 157