ar5416reg.h revision 248129
1316485Sdavidcs/* 2337517Sdavidcs * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3316485Sdavidcs * Copyright (c) 2002-2008 Atheros Communications, Inc. 4316485Sdavidcs * 5316485Sdavidcs * Permission to use, copy, modify, and/or distribute this software for any 6316485Sdavidcs * purpose with or without fee is hereby granted, provided that the above 7316485Sdavidcs * copyright notice and this permission notice appear in all copies. 8316485Sdavidcs * 9316485Sdavidcs * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10316485Sdavidcs * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11316485Sdavidcs * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12316485Sdavidcs * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13316485Sdavidcs * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14316485Sdavidcs * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15316485Sdavidcs * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16316485Sdavidcs * 17316485Sdavidcs * $FreeBSD: head/sys/dev/ath/ath_hal/ar5416/ar5416reg.h 248129 2013-03-10 09:43:01Z adrian $ 18316485Sdavidcs */ 19316485Sdavidcs#ifndef _DEV_ATH_AR5416REG_H 20316485Sdavidcs#define _DEV_ATH_AR5416REG_H 21316485Sdavidcs 22316485Sdavidcs#include <dev/ath/ath_hal/ar5212/ar5212reg.h> 23316485Sdavidcs 24316485Sdavidcs/* 25316485Sdavidcs * Register added starting with the AR5416 26316485Sdavidcs */ 27316485Sdavidcs#define AR_MIRT 0x0020 /* interrupt rate threshold */ 28316485Sdavidcs#define AR_TIMT 0x0028 /* Tx Interrupt mitigation threshold */ 29316485Sdavidcs#define AR_RIMT 0x002C /* Rx Interrupt mitigation threshold */ 30316485Sdavidcs#define AR_GTXTO 0x0064 /* global transmit timeout */ 31320164Sdavidcs#define AR_GTTM 0x0068 /* global transmit timeout mode */ 32316485Sdavidcs#define AR_CST 0x006C /* carrier sense timeout */ 33316485Sdavidcs#define AR_MAC_LED 0x1f04 /* LED control */ 34316485Sdavidcs#define AR_WA 0x4004 /* PCIE work-arounds */ 35316485Sdavidcs#define AR_PCIE_PM_CTRL 0x4014 36316485Sdavidcs#define AR_AHB_MODE 0x4024 /* AHB mode for dma */ 37320164Sdavidcs#define AR_INTR_SYNC_CAUSE_CLR 0x4028 /* clear interrupt */ 38337517Sdavidcs#define AR_INTR_SYNC_CAUSE 0x4028 /* check pending interrupts */ 39316485Sdavidcs#define AR_INTR_SYNC_ENABLE 0x402c /* enable interrupts */ 40320164Sdavidcs#define AR_INTR_ASYNC_MASK 0x4030 /* asynchronous interrupt mask */ 41337517Sdavidcs#define AR_INTR_SYNC_MASK 0x4034 /* synchronous interrupt mask */ 42316485Sdavidcs#define AR_INTR_ASYNC_CAUSE 0x4038 /* check pending interrupts */ 43316485Sdavidcs#define AR_INTR_ASYNC_CAUSE_CLR 0x4038 /* clear pending interrupts */ 44316485Sdavidcs#define AR_INTR_ASYNC_ENABLE 0x403c /* enable interrupts */ 45316485Sdavidcs#define AR5416_PCIE_SERDES 0x4040 46316485Sdavidcs#define AR5416_PCIE_SERDES2 0x4044 47316485Sdavidcs#define AR_GPIO_IN_OUT 0x4048 /* GPIO input/output register */ 48316485Sdavidcs#define AR_GPIO_OE_OUT 0x404c /* GPIO output enable register */ 49316485Sdavidcs#define AR_GPIO_INTR_POL 0x4050 /* GPIO interrupt polarity */ 50316485Sdavidcs 51316485Sdavidcs#define AR_GPIO_INPUT_EN_VAL 0x4054 /* GPIO input enable and value */ 52316485Sdavidcs#define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF 0x00000004 53316485Sdavidcs#define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_S 2 54316485Sdavidcs#define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF 0x00000008 55316485Sdavidcs#define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_S 3 56316485Sdavidcs#define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_DEF 0x00000010 57316485Sdavidcs#define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_S 4 58316485Sdavidcs#define AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF 0x00000080 59316485Sdavidcs#define AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF_S 7 60316485Sdavidcs#define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB 0x00000400 61316485Sdavidcs#define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB_S 10 62316485Sdavidcs#define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_BB 0x00000800 63316485Sdavidcs#define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_BB_S 11 64316485Sdavidcs#define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB 0x00001000 65316485Sdavidcs#define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB_S 12 66316485Sdavidcs#define AR_GPIO_INPUT_EN_VAL_RFSILENT_BB 0x00008000 67316485Sdavidcs#define AR_GPIO_INPUT_EN_VAL_RFSILENT_BB_S 15 68316485Sdavidcs#define AR_GPIO_RTC_RESET_OVERRIDE_ENABLE 0x00010000 69316485Sdavidcs#define AR_GPIO_JTAG_DISABLE 0x00020000 70316485Sdavidcs 71316485Sdavidcs#define AR_GPIO_INPUT_MUX1 0x4058 72316485Sdavidcs#define AR_GPIO_INPUT_MUX1_BT_PRIORITY 0x00000f00 73316485Sdavidcs#define AR_GPIO_INPUT_MUX1_BT_PRIORITY_S 8 74316485Sdavidcs#define AR_GPIO_INPUT_MUX1_BT_FREQUENCY 0x0000f000 75316485Sdavidcs#define AR_GPIO_INPUT_MUX1_BT_FREQUENCY_S 12 76316485Sdavidcs#define AR_GPIO_INPUT_MUX1_BT_ACTIVE 0x000f0000 77316485Sdavidcs#define AR_GPIO_INPUT_MUX1_BT_ACTIVE_S 16 78316485Sdavidcs 79316485Sdavidcs#define AR_GPIO_INPUT_MUX2 0x405c 80316485Sdavidcs#define AR_GPIO_INPUT_MUX2_CLK25 0x0000000f 81316485Sdavidcs#define AR_GPIO_INPUT_MUX2_CLK25_S 0 82316485Sdavidcs#define AR_GPIO_INPUT_MUX2_RFSILENT 0x000000f0 83316485Sdavidcs#define AR_GPIO_INPUT_MUX2_RFSILENT_S 4 84316485Sdavidcs#define AR_GPIO_INPUT_MUX2_RTC_RESET 0x00000f00 85316485Sdavidcs#define AR_GPIO_INPUT_MUX2_RTC_RESET_S 8 86316485Sdavidcs 87316485Sdavidcs#define AR_GPIO_OUTPUT_MUX1 0x4060 88316485Sdavidcs#define AR_GPIO_OUTPUT_MUX2 0x4064 89316485Sdavidcs#define AR_GPIO_OUTPUT_MUX3 0x4068 90316485Sdavidcs 91316485Sdavidcs#define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0 92316485Sdavidcs#define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1 93316485Sdavidcs#define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2 94316485Sdavidcs#define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3 95316485Sdavidcs#define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4 96316485Sdavidcs#define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5 97316485Sdavidcs#define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6 98316485Sdavidcs 99316485Sdavidcs#define AR_EEPROM_STATUS_DATA 0x407c 100316485Sdavidcs#define AR_OBS 0x4080 101316485Sdavidcs#define AR_GPIO_PDPU 0x4088 102316485Sdavidcs 103316485Sdavidcs#ifdef AH_SUPPORT_AR9130 104316485Sdavidcs#define AR_RTC_BASE 0x20000 105316485Sdavidcs#else 106316485Sdavidcs#define AR_RTC_BASE 0x7000 107316485Sdavidcs#endif /* AH_SUPPORT_AR9130 */ 108316485Sdavidcs 109316485Sdavidcs#define AR_RTC_RC AR_RTC_BASE + 0x00 /* reset control */ 110316485Sdavidcs#define AR_RTC_PLL_CONTROL AR_RTC_BASE + 0x14 111316485Sdavidcs#define AR_RTC_RESET AR_RTC_BASE + 0x40 /* RTC reset register */ 112316485Sdavidcs#define AR_RTC_STATUS AR_RTC_BASE + 0x44 /* system sleep status */ 113320164Sdavidcs#define AR_RTC_SLEEP_CLK AR_RTC_BASE + 0x48 114316485Sdavidcs#define AR_RTC_FORCE_WAKE AR_RTC_BASE + 0x4c /* control MAC force wake */ 115316485Sdavidcs#define AR_RTC_INTR_CAUSE AR_RTC_BASE + 0x50 /* RTC interrupt cause/clear */ 116316485Sdavidcs#define AR_RTC_INTR_ENABLE AR_RTC_BASE + 0x54 /* RTC interrupt enable */ 117316485Sdavidcs#define AR_RTC_INTR_MASK AR_RTC_BASE + 0x58 /* RTC interrupt mask */ 118316485Sdavidcs 119320164Sdavidcs#ifdef AH_SUPPORT_AR9130 120316485Sdavidcs/* RTC_DERIVED_* - only for AR9130 */ 121316485Sdavidcs#define AR_RTC_DERIVED_CLK (AR_RTC_BASE + 0x0038) 122316485Sdavidcs#define AR_RTC_DERIVED_CLK_PERIOD 0x0000fffe 123316485Sdavidcs#define AR_RTC_DERIVED_CLK_PERIOD_S 1 124316485Sdavidcs#endif /* AH_SUPPORT_AR9130 */ 125316485Sdavidcs 126316485Sdavidcs/* AR_USEC: 0x801c */ 127316485Sdavidcs#define AR5416_USEC_TX_LAT 0x007FC000 /* tx latency to start of SIGNAL (usec) */ 128316485Sdavidcs#define AR5416_USEC_TX_LAT_S 14 /* tx latency to start of SIGNAL (usec) */ 129316485Sdavidcs#define AR5416_USEC_RX_LAT 0x1F800000 /* rx latency to start of SIGNAL (usec) */ 130337517Sdavidcs#define AR5416_USEC_RX_LAT_S 23 /* rx latency to start of SIGNAL (usec) */ 131337517Sdavidcs 132337517Sdavidcs#define AR_RESET_TSF 0x8020 133337517Sdavidcs 134337517Sdavidcs/* 135337517Sdavidcs * AR_SLEEP1 / AR_SLEEP2 are in the same place as in 136316485Sdavidcs * AR5212, however the fields have changed. 137316485Sdavidcs */ 138316485Sdavidcs#define AR5416_SLEEP1 0x80d4 139316485Sdavidcs#define AR5416_SLEEP2 0x80d8 140316485Sdavidcs#define AR_RXFIFO_CFG 0x8114 141316485Sdavidcs#define AR_PHY_ERR_1 0x812c 142316485Sdavidcs#define AR_PHY_ERR_MASK_1 0x8130 /* mask for AR_PHY_ERR_1 */ 143316485Sdavidcs#define AR_PHY_ERR_2 0x8134 144316485Sdavidcs#define AR_PHY_ERR_MASK_2 0x8138 /* mask for AR_PHY_ERR_2 */ 145316485Sdavidcs#define AR_TSFOOR_THRESHOLD 0x813c 146316485Sdavidcs#define AR_PHY_ERR_3 0x8168 147316485Sdavidcs#define AR_PHY_ERR_MASK_3 0x816c /* mask for AR_PHY_ERR_3 */ 148316485Sdavidcs#define AR_BT_COEX_WEIGHT2 0x81c4 149316485Sdavidcs#define AR_TXOP_X 0x81ec /* txop for legacy non-qos */ 150316485Sdavidcs#define AR_TXOP_0_3 0x81f0 /* txop for various tid's */ 151316485Sdavidcs#define AR_TXOP_4_7 0x81f4 152316485Sdavidcs#define AR_TXOP_8_11 0x81f8 153316485Sdavidcs#define AR_TXOP_12_15 0x81fc 154316485Sdavidcs/* generic timers based on tsf - all uS */ 155316485Sdavidcs#define AR_NEXT_TBTT 0x8200 156316485Sdavidcs#define AR_NEXT_DBA 0x8204 157316485Sdavidcs#define AR_NEXT_SWBA 0x8208 158316485Sdavidcs#define AR_NEXT_CFP 0x8208 159316485Sdavidcs#define AR_NEXT_HCF 0x820C 160316485Sdavidcs#define AR_NEXT_TIM 0x8210 161316485Sdavidcs#define AR_NEXT_DTIM 0x8214 162316485Sdavidcs#define AR_NEXT_QUIET 0x8218 163316485Sdavidcs#define AR_NEXT_NDP 0x821C 164316485Sdavidcs#define AR5416_BEACON_PERIOD 0x8220 165316485Sdavidcs#define AR_DBA_PERIOD 0x8224 166316485Sdavidcs#define AR_SWBA_PERIOD 0x8228 167316485Sdavidcs#define AR_HCF_PERIOD 0x822C 168316485Sdavidcs#define AR_TIM_PERIOD 0x8230 169316485Sdavidcs#define AR_DTIM_PERIOD 0x8234 170316485Sdavidcs#define AR_QUIET_PERIOD 0x8238 171316485Sdavidcs#define AR_NDP_PERIOD 0x823C 172316485Sdavidcs#define AR_TIMER_MODE 0x8240 173316485Sdavidcs#define AR_SLP32_MODE 0x8244 174316485Sdavidcs#define AR_SLP32_WAKE 0x8248 175316485Sdavidcs#define AR_SLP32_INC 0x824c 176316485Sdavidcs#define AR_SLP_CNT 0x8250 /* 32kHz cycles with mac asleep */ 177316485Sdavidcs#define AR_SLP_CYCLE_CNT 0x8254 /* absolute number of 32kHz cycles */ 178316485Sdavidcs#define AR_SLP_MIB_CTRL 0x8258 179316485Sdavidcs#define AR_2040_MODE 0x8318 180316485Sdavidcs#define AR_EXTRCCNT 0x8328 /* extension channel rx clear count */ 181316485Sdavidcs#define AR_SELFGEN_MASK 0x832c /* rx and cal chain masks */ 182316485Sdavidcs#define AR_PHY_ERR_MASK_REG 0x8338 183316485Sdavidcs#define AR_PCU_TXBUF_CTRL 0x8340 184316485Sdavidcs#define AR_PCU_MISC_MODE2 0x8344 185316485Sdavidcs 186316485Sdavidcs/* DMA & PCI Registers in PCI space (usable during sleep)*/ 187316485Sdavidcs#define AR_RC_AHB 0x00000001 /* AHB reset */ 188316485Sdavidcs#define AR_RC_APB 0x00000002 /* APB reset */ 189316485Sdavidcs#define AR_RC_HOSTIF 0x00000100 /* host interface reset */ 190316485Sdavidcs 191316485Sdavidcs#define AR_MIRT_VAL 0x0000ffff /* in uS */ 192316485Sdavidcs#define AR_MIRT_VAL_S 16 193316485Sdavidcs 194316485Sdavidcs#define AR_TIMT_LAST 0x0000ffff /* Last packet threshold */ 195316485Sdavidcs#define AR_TIMT_LAST_S 0 196316485Sdavidcs#define AR_TIMT_FIRST 0xffff0000 /* First packet threshold */ 197316485Sdavidcs#define AR_TIMT_FIRST_S 16 198316485Sdavidcs 199316485Sdavidcs#define AR_RIMT_LAST 0x0000ffff /* Last packet threshold */ 200316485Sdavidcs#define AR_RIMT_LAST_S 0 201316485Sdavidcs#define AR_RIMT_FIRST 0xffff0000 /* First packet threshold */ 202316485Sdavidcs#define AR_RIMT_FIRST_S 16 203316485Sdavidcs 204316485Sdavidcs#define AR_GTXTO_TIMEOUT_COUNTER 0x0000FFFF // Mask for timeout counter (in TUs) 205316485Sdavidcs#define AR_GTXTO_TIMEOUT_LIMIT 0xFFFF0000 // Mask for timeout limit (in TUs) 206316485Sdavidcs#define AR_GTXTO_TIMEOUT_LIMIT_S 16 // Shift for timeout limit 207320164Sdavidcs 208320164Sdavidcs#define AR_GTTM_USEC 0x00000001 // usec strobe 209320164Sdavidcs#define AR_GTTM_IGNORE_IDLE 0x00000002 // ignore channel idle 210320164Sdavidcs#define AR_GTTM_RESET_IDLE 0x00000004 // reset counter on channel idle low 211320164Sdavidcs#define AR_GTTM_CST_USEC 0x00000008 // CST usec strobe 212316485Sdavidcs 213316485Sdavidcs#define AR_CST_TIMEOUT_COUNTER 0x0000FFFF // Mask for timeout counter (in TUs) 214316485Sdavidcs#define AR_CST_TIMEOUT_LIMIT 0xFFFF0000 // Mask for timeout limit (in TUs) 215316485Sdavidcs#define AR_CST_TIMEOUT_LIMIT_S 16 // Shift for timeout limit 216316485Sdavidcs 217316485Sdavidcs/* MAC tx DMA size config */ 218316485Sdavidcs#define AR_TXCFG_DMASZ_MASK 0x00000003 219316485Sdavidcs#define AR_TXCFG_DMASZ_4B 0 220316485Sdavidcs#define AR_TXCFG_DMASZ_8B 1 221316485Sdavidcs#define AR_TXCFG_DMASZ_16B 2 222316485Sdavidcs#define AR_TXCFG_DMASZ_32B 3 223316485Sdavidcs#define AR_TXCFG_DMASZ_64B 4 224316485Sdavidcs#define AR_TXCFG_DMASZ_128B 5 225337517Sdavidcs#define AR_TXCFG_DMASZ_256B 6 226337517Sdavidcs#define AR_TXCFG_DMASZ_512B 7 227316485Sdavidcs#define AR_TXCFG_ATIM_TXPOLICY 0x00000800 228316485Sdavidcs 229316485Sdavidcs/* MAC rx DMA size config */ 230316485Sdavidcs#define AR_RXCFG_DMASZ_MASK 0x00000007 231316485Sdavidcs#define AR_RXCFG_DMASZ_4B 0 232316485Sdavidcs#define AR_RXCFG_DMASZ_8B 1 233316485Sdavidcs#define AR_RXCFG_DMASZ_16B 2 234316485Sdavidcs#define AR_RXCFG_DMASZ_32B 3 235316485Sdavidcs#define AR_RXCFG_DMASZ_64B 4 236316485Sdavidcs#define AR_RXCFG_DMASZ_128B 5 237316485Sdavidcs#define AR_RXCFG_DMASZ_256B 6 238316485Sdavidcs#define AR_RXCFG_DMASZ_512B 7 239316485Sdavidcs 240316485Sdavidcs/* MAC Led registers */ 241316485Sdavidcs#define AR_CFG_SCLK_RATE_IND 0x00000003 /* sleep clock indication */ 242316485Sdavidcs#define AR_CFG_SCLK_RATE_IND_S 0 243316485Sdavidcs#define AR_CFG_SCLK_32MHZ 0x00000000 /* Sleep clock rate */ 244316485Sdavidcs#define AR_CFG_SCLK_4MHZ 0x00000001 /* Sleep clock rate */ 245316485Sdavidcs#define AR_CFG_SCLK_1MHZ 0x00000002 /* Sleep clock rate */ 246316485Sdavidcs#define AR_CFG_SCLK_32KHZ 0x00000003 /* Sleep clock rate */ 247316485Sdavidcs#define AR_MAC_LED_BLINK_SLOW 0x00000008 /* LED slowest blink rate mode */ 248316485Sdavidcs#define AR_MAC_LED_BLINK_THRESH_SEL 0x00000070 /* LED blink threshold select */ 249316485Sdavidcs#define AR_MAC_LED_MODE 0x00000380 /* LED mode select */ 250316485Sdavidcs#define AR_MAC_LED_MODE_S 7 251316485Sdavidcs#define AR_MAC_LED_MODE_PROP 0 /* Blink prop to filtered tx/rx */ 252316485Sdavidcs#define AR_MAC_LED_MODE_RPROP 1 /* Blink prop to unfiltered tx/rx */ 253316485Sdavidcs#define AR_MAC_LED_MODE_SPLIT 2 /* Blink power for tx/net for rx */ 254316485Sdavidcs#define AR_MAC_LED_MODE_RAND 3 /* Blink randomly */ 255316485Sdavidcs#define AR_MAC_LED_MODE_POWON 5 /* Power LED on (s/w control) */ 256316485Sdavidcs#define AR_MAC_LED_MODE_NETON 6 /* Network LED on (s/w control) */ 257316485Sdavidcs#define AR_MAC_LED_ASSOC 0x00000c00 258316485Sdavidcs#define AR_MAC_LED_ASSOC_NONE 0x0 /* STA is not associated or trying */ 259316485Sdavidcs#define AR_MAC_LED_ASSOC_ACTIVE 0x1 /* STA is associated */ 260316485Sdavidcs#define AR_MAC_LED_ASSOC_PEND 0x2 /* STA is trying to associate */ 261316485Sdavidcs#define AR_MAC_LED_ASSOC_S 10 262316485Sdavidcs 263316485Sdavidcs#define AR_WA_BIT6 0x00000040 264316485Sdavidcs#define AR_WA_BIT7 0x00000080 265316485Sdavidcs#define AR_WA_D3_L1_DISABLE 0x00004000 /* */ 266316485Sdavidcs#define AR_WA_UNTIE_RESET_EN 0x00008000 /* ena PCI reset to POR */ 267316485Sdavidcs#define AR_WA_RESET_EN 0x00040000 /* ena AR_WA_UNTIE_RESET_EN */ 268316485Sdavidcs#define AR_WA_ANALOG_SHIFT 0x00100000 269316485Sdavidcs#define AR_WA_POR_SHORT 0x00200000 /* PCIE phy reset control */ 270316485Sdavidcs#define AR_WA_BIT22 0x00400000 271316485Sdavidcs#define AR_WA_BIT23 0x00800000 272316485Sdavidcs 273316485Sdavidcs#define AR_WA_DEFAULT 0x0000073f 274316485Sdavidcs#define AR9280_WA_DEFAULT 0x0040073b /* disable bit 2, see commit */ 275316485Sdavidcs#define AR9285_WA_DEFAULT 0x004a05cb 276316485Sdavidcs 277316485Sdavidcs#define AR_PCIE_PM_CTRL_ENA 0x00080000 278316485Sdavidcs 279316485Sdavidcs#define AR_AHB_EXACT_WR_EN 0x00000000 /* write exact bytes */ 280316485Sdavidcs#define AR_AHB_BUF_WR_EN 0x00000001 /* buffer write upto cacheline*/ 281316485Sdavidcs#define AR_AHB_EXACT_RD_EN 0x00000000 /* read exact bytes */ 282316485Sdavidcs#define AR_AHB_CACHELINE_RD_EN 0x00000002 /* read upto end of cacheline */ 283316485Sdavidcs#define AR_AHB_PREFETCH_RD_EN 0x00000004 /* prefetch upto page boundary*/ 284316485Sdavidcs#define AR_AHB_PAGE_SIZE_1K 0x00000000 /* set page-size as 1k */ 285316485Sdavidcs#define AR_AHB_PAGE_SIZE_2K 0x00000008 /* set page-size as 2k */ 286316485Sdavidcs#define AR_AHB_PAGE_SIZE_4K 0x00000010 /* set page-size as 4k */ 287316485Sdavidcs/* Kiwi */ 288316485Sdavidcs#define AR_AHB_CUSTOM_BURST_EN 0x000000C0 /* set Custom Burst Mode */ 289316485Sdavidcs#define AR_AHB_CUSTOM_BURST_EN_S 6 /* set Custom Burst Mode */ 290316485Sdavidcs#define AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL 3 /* set both bits in Async FIFO mode */ 291316485Sdavidcs 292316485Sdavidcs/* MAC PCU Registers */ 293316485Sdavidcs#define AR_STA_ID1_PRESERVE_SEQNUM 0x20000000 /* Don't replace seq num */ 294316485Sdavidcs 295316485Sdavidcs/* Extended PCU DIAG_SW control fields */ 296316485Sdavidcs#define AR_DIAG_DUAL_CHAIN_INFO 0x01000000 /* dual chain channel info */ 297316485Sdavidcs#define AR_DIAG_RX_ABORT 0x02000000 /* abort rx */ 298316485Sdavidcs#define AR_DIAG_SATURATE_CCNT 0x04000000 /* sat. cycle cnts (no shift) */ 299316485Sdavidcs#define AR_DIAG_OBS_PT_SEL2 0x08000000 /* observation point sel */ 300316485Sdavidcs#define AR_DIAG_RXCLEAR_CTL_LOW 0x10000000 /* force rx_clear(ctl) low/busy */ 301316485Sdavidcs#define AR_DIAG_RXCLEAR_EXT_LOW 0x20000000 /* force rx_clear(ext) low/busy */ 302316485Sdavidcs 303316485Sdavidcs#define AR_TXOP_X_VAL 0x000000FF 304316485Sdavidcs 305316485Sdavidcs#define AR_RESET_TSF_ONCE 0x01000000 /* reset tsf once; self-clears*/ 306316485Sdavidcs 307316485Sdavidcs/* Interrupts */ 308316485Sdavidcs#define AR_ISR_TXMINTR 0x00080000 /* Maximum interrupt tx rate */ 309316485Sdavidcs#define AR_ISR_RXMINTR 0x01000000 /* Maximum interrupt rx rate */ 310316485Sdavidcs#define AR_ISR_GENTMR 0x10000000 /* OR of generic timer bits in S5 */ 311316485Sdavidcs#define AR_ISR_TXINTM 0x40000000 /* Tx int after mitigation */ 312316485Sdavidcs#define AR_ISR_RXINTM 0x80000000 /* Rx int after mitigation */ 313316485Sdavidcs 314316485Sdavidcs#define AR_ISR_S2_CST 0x00400000 /* Carrier sense timeout */ 315316485Sdavidcs#define AR_ISR_S2_GTT 0x00800000 /* Global transmit timeout */ 316316485Sdavidcs#define AR_ISR_S2_TSFOOR 0x40000000 /* RX TSF out of range */ 317316485Sdavidcs 318316485Sdavidcs#define AR_ISR_S5 0x0098 319316485Sdavidcs#define AR_ISR_S5_S 0x00d8 320316485Sdavidcs#define AR_ISR_S5_GENTIMER7 0x00000080 // Mask for timer 7 trigger 321316485Sdavidcs#define AR_ISR_S5_TIM_TIMER 0x00000010 // TIM Timer ISR 322316485Sdavidcs#define AR_ISR_S5_DTIM_TIMER 0x00000020 // DTIM Timer ISR 323316485Sdavidcs#define AR_ISR_S5_GENTIMER_TRIG 0x0000FF80 // ISR for generic timer trigger 7-15 324316485Sdavidcs#define AR_ISR_S5_GENTIMER_TRIG_S 0 325316485Sdavidcs#define AR_ISR_S5_GENTIMER_THRESH 0xFF800000 // ISR for generic timer threshold 7-15 326316485Sdavidcs#define AR_ISR_S5_GENTIMER_THRESH_S 16 327316485Sdavidcs 328316485Sdavidcs#define AR_INTR_SPURIOUS 0xffffffff 329316485Sdavidcs#define AR_INTR_RTC_IRQ 0x00000001 /* rtc in shutdown state */ 330316485Sdavidcs#define AR_INTR_MAC_IRQ 0x00000002 /* pending mac interrupt */ 331316485Sdavidcs#define AR_INTR_EEP_PROT_ACCESS 0x00000004 /* eeprom protected access */ 332316485Sdavidcs#define AR_INTR_MAC_AWAKE 0x00020000 /* mac is awake */ 333316485Sdavidcs#define AR_INTR_MAC_ASLEEP 0x00040000 /* mac is asleep */ 334316485Sdavidcs 335316485Sdavidcs/* Interrupt Mask Registers */ 336316485Sdavidcs#define AR_IMR_TXMINTR 0x00080000 /* Maximum interrupt tx rate */ 337316485Sdavidcs#define AR_IMR_RXMINTR 0x01000000 /* Maximum interrupt rx rate */ 338316485Sdavidcs#define AR_IMR_TXINTM 0x40000000 /* Tx int after mitigation */ 339316485Sdavidcs#define AR_IMR_RXINTM 0x80000000 /* Rx int after mitigation */ 340316485Sdavidcs 341316485Sdavidcs#define AR_IMR_S2_CST 0x00400000 /* Carrier sense timeout */ 342316485Sdavidcs#define AR_IMR_S2_GTT 0x00800000 /* Global transmit timeout */ 343316485Sdavidcs 344316485Sdavidcs/* synchronous interrupt signals */ 345316485Sdavidcs#define AR_INTR_SYNC_RTC_IRQ 0x00000001 346316485Sdavidcs#define AR_INTR_SYNC_MAC_IRQ 0x00000002 347316485Sdavidcs#define AR_INTR_SYNC_EEPROM_ILLEGAL_ACCESS 0x00000004 348316485Sdavidcs#define AR_INTR_SYNC_APB_TIMEOUT 0x00000008 349316485Sdavidcs#define AR_INTR_SYNC_PCI_MODE_CONFLICT 0x00000010 350316485Sdavidcs#define AR_INTR_SYNC_HOST1_FATAL 0x00000020 351316485Sdavidcs#define AR_INTR_SYNC_HOST1_PERR 0x00000040 352316485Sdavidcs#define AR_INTR_SYNC_TRCV_FIFO_PERR 0x00000080 353316485Sdavidcs#define AR_INTR_SYNC_RADM_CPL_EP 0x00000100 354316485Sdavidcs#define AR_INTR_SYNC_RADM_CPL_DLLP_ABORT 0x00000200 355316485Sdavidcs#define AR_INTR_SYNC_RADM_CPL_TLP_ABORT 0x00000400 356316485Sdavidcs#define AR_INTR_SYNC_RADM_CPL_ECRC_ERR 0x00000800 357316485Sdavidcs#define AR_INTR_SYNC_RADM_CPL_TIMEOUT 0x00001000 358316485Sdavidcs#define AR_INTR_SYNC_LOCAL_TIMEOUT 0x00002000 359316485Sdavidcs#define AR_INTR_SYNC_PM_ACCESS 0x00004000 360316485Sdavidcs#define AR_INTR_SYNC_MAC_AWAKE 0x00008000 361316485Sdavidcs#define AR_INTR_SYNC_MAC_ASLEEP 0x00010000 362316485Sdavidcs#define AR_INTR_SYNC_MAC_SLEEP_ACCESS 0x00020000 363316485Sdavidcs#define AR_INTR_SYNC_ALL 0x0003FFFF 364316485Sdavidcs 365316485Sdavidcs/* default synchronous interrupt signals enabled */ 366316485Sdavidcs#define AR_INTR_SYNC_DEFAULT \ 367316485Sdavidcs (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR | \ 368316485Sdavidcs AR_INTR_SYNC_RADM_CPL_EP | AR_INTR_SYNC_RADM_CPL_DLLP_ABORT | \ 369316485Sdavidcs AR_INTR_SYNC_RADM_CPL_TLP_ABORT | AR_INTR_SYNC_RADM_CPL_ECRC_ERR | \ 370316485Sdavidcs AR_INTR_SYNC_RADM_CPL_TIMEOUT | AR_INTR_SYNC_LOCAL_TIMEOUT | \ 371316485Sdavidcs AR_INTR_SYNC_MAC_SLEEP_ACCESS) 372316485Sdavidcs 373316485Sdavidcs#define AR_INTR_SYNC_MASK_GPIO 0xFFFC0000 374316485Sdavidcs#define AR_INTR_SYNC_MASK_GPIO_S 18 375316485Sdavidcs 376316485Sdavidcs#define AR_INTR_SYNC_ENABLE_GPIO 0xFFFC0000 377316485Sdavidcs#define AR_INTR_SYNC_ENABLE_GPIO_S 18 378316485Sdavidcs 379316485Sdavidcs#define AR_INTR_ASYNC_MASK_GPIO 0xFFFC0000 /* async int mask */ 380316485Sdavidcs#define AR_INTR_ASYNC_MASK_GPIO_S 18 381316485Sdavidcs 382316485Sdavidcs#define AR_INTR_ASYNC_CAUSE_GPIO 0xFFFC0000 /* GPIO interrupts */ 383316485Sdavidcs#define AR_INTR_ASYNC_USED (AR_INTR_MAC_IRQ | AR_INTR_ASYNC_CAUSE_GPIO) 384316485Sdavidcs 385316485Sdavidcs#define AR_INTR_ASYNC_ENABLE_GPIO 0xFFFC0000 /* enable interrupts */ 386316485Sdavidcs#define AR_INTR_ASYNC_ENABLE_GPIO_S 18 387316485Sdavidcs 388316485Sdavidcs/* RTC registers */ 389316485Sdavidcs#define AR_RTC_RC_M 0x00000003 390316485Sdavidcs#define AR_RTC_RC_MAC_WARM 0x00000001 391316485Sdavidcs#define AR_RTC_RC_MAC_COLD 0x00000002 392316485Sdavidcs#ifdef AH_SUPPORT_AR9130 393316485Sdavidcs#define AR_RTC_RC_COLD_RESET 0x00000004 394316485Sdavidcs#define AR_RTC_RC_WARM_RESET 0x00000008 395316485Sdavidcs#endif /* AH_SUPPORT_AR9130 */ 396316485Sdavidcs#define AR_RTC_PLL_DIV 0x0000001f 397337517Sdavidcs#define AR_RTC_PLL_DIV_S 0 398337517Sdavidcs#define AR_RTC_PLL_DIV2 0x00000020 399316485Sdavidcs#define AR_RTC_PLL_REFDIV_5 0x000000c0 400316485Sdavidcs 401316485Sdavidcs#define AR_RTC_SOWL_PLL_DIV 0x000003ff 402316485Sdavidcs#define AR_RTC_SOWL_PLL_DIV_S 0 403316485Sdavidcs#define AR_RTC_SOWL_PLL_REFDIV 0x00003C00 404316485Sdavidcs#define AR_RTC_SOWL_PLL_REFDIV_S 10 405316485Sdavidcs#define AR_RTC_SOWL_PLL_CLKSEL 0x0000C000 406316485Sdavidcs#define AR_RTC_SOWL_PLL_CLKSEL_S 14 407316485Sdavidcs 408316485Sdavidcs#define AR_RTC_RESET_EN 0x00000001 /* Reset RTC bit */ 409316485Sdavidcs 410316485Sdavidcs#define AR_RTC_PM_STATUS_M 0x0000000f /* Pwr Mgmt Status */ 411316485Sdavidcs#ifdef AH_SUPPORT_AR9130 412316485Sdavidcs#define AR_RTC_STATUS_M 0x0000000f /* RTC Status */ 413316485Sdavidcs#else 414316485Sdavidcs#define AR_RTC_STATUS_M 0x0000003f /* RTC Status */ 415316485Sdavidcs#endif /* AH_SUPPORT_AR9130 */ 416316485Sdavidcs#define AR_RTC_STATUS_SHUTDOWN 0x00000001 417316485Sdavidcs#define AR_RTC_STATUS_ON 0x00000002 418316485Sdavidcs#define AR_RTC_STATUS_SLEEP 0x00000004 419316485Sdavidcs#define AR_RTC_STATUS_WAKEUP 0x00000008 420316485Sdavidcs#define AR_RTC_STATUS_COLDRESET 0x00000010 /* Not currently used */ 421316485Sdavidcs#define AR_RTC_STATUS_PLLCHANGE 0x00000020 /* Not currently used */ 422316485Sdavidcs 423316485Sdavidcs#define AR_RTC_SLEEP_DERIVED_CLK 0x2 424316485Sdavidcs 425316485Sdavidcs#define AR_RTC_FORCE_WAKE_EN 0x00000001 /* enable force wake */ 426337517Sdavidcs#define AR_RTC_FORCE_WAKE_ON_INT 0x00000002 /* auto-wake on MAC interrupt */ 427337517Sdavidcs 428337517Sdavidcs#define AR_RTC_PLL_CLKSEL 0x00000300 429337517Sdavidcs#define AR_RTC_PLL_CLKSEL_S 8 430337517Sdavidcs 431337517Sdavidcs/* AR9280: rf long shift registers */ 432337517Sdavidcs#define AR_AN_RF2G1_CH0 0x7810 433316485Sdavidcs#define AR_AN_RF5G1_CH0 0x7818 434316485Sdavidcs#define AR_AN_RF2G1_CH1 0x7834 435316485Sdavidcs#define AR_AN_RF5G1_CH1 0x783C 436316485Sdavidcs#define AR_AN_TOP2 0x7894 437316485Sdavidcs#define AR_AN_SYNTH9 0x7868 438316485Sdavidcs 439316485Sdavidcs#define AR_AN_RF2G1_CH0_OB 0x03800000 440316485Sdavidcs#define AR_AN_RF2G1_CH0_OB_S 23 441316485Sdavidcs#define AR_AN_RF2G1_CH0_DB 0x1C000000 442316485Sdavidcs#define AR_AN_RF2G1_CH0_DB_S 26 443316485Sdavidcs 444316485Sdavidcs#define AR_AN_RF5G1_CH0_OB5 0x00070000 445316485Sdavidcs#define AR_AN_RF5G1_CH0_OB5_S 16 446316485Sdavidcs#define AR_AN_RF5G1_CH0_DB5 0x00380000 447316485Sdavidcs#define AR_AN_RF5G1_CH0_DB5_S 19 448316485Sdavidcs 449316485Sdavidcs#define AR_AN_RF2G1_CH1_OB 0x03800000 450316485Sdavidcs#define AR_AN_RF2G1_CH1_OB_S 23 451316485Sdavidcs#define AR_AN_RF2G1_CH1_DB 0x1C000000 452316485Sdavidcs#define AR_AN_RF2G1_CH1_DB_S 26 453316485Sdavidcs 454316485Sdavidcs#define AR_AN_RF5G1_CH1_OB5 0x00070000 455316485Sdavidcs#define AR_AN_RF5G1_CH1_OB5_S 16 456316485Sdavidcs#define AR_AN_RF5G1_CH1_DB5 0x00380000 457316485Sdavidcs#define AR_AN_RF5G1_CH1_DB5_S 19 458316485Sdavidcs 459316485Sdavidcs#define AR_AN_TOP1 0x7890 460316485Sdavidcs#define AR_AN_TOP1_DACIPMODE 0x00040000 461316485Sdavidcs#define AR_AN_TOP1_DACIPMODE_S 18 462316485Sdavidcs 463316485Sdavidcs#define AR_AN_TOP2_XPABIAS_LVL 0xC0000000 464316485Sdavidcs#define AR_AN_TOP2_XPABIAS_LVL_S 30 465316485Sdavidcs#define AR_AN_TOP2_LOCALBIAS 0x00200000 466316485Sdavidcs#define AR_AN_TOP2_LOCALBIAS_S 21 467316485Sdavidcs#define AR_AN_TOP2_PWDCLKIND 0x00400000 468316485Sdavidcs#define AR_AN_TOP2_PWDCLKIND_S 22 469316485Sdavidcs 470316485Sdavidcs#define AR_AN_SYNTH9_REFDIVA 0xf8000000 471316485Sdavidcs#define AR_AN_SYNTH9_REFDIVA_S 27 472316485Sdavidcs 473316485Sdavidcs#define AR9271_AN_RF2G6_OFFS 0x07f00000 474316485Sdavidcs#define AR9271_AN_RF2G6_OFFS_S 20 475316485Sdavidcs 476316485Sdavidcs/* Sleep control */ 477316485Sdavidcs#define AR5416_SLEEP1_ASSUME_DTIM 0x00080000 478316485Sdavidcs#define AR5416_SLEEP1_CAB_TIMEOUT 0xFFE00000 /* Cab timeout (TU) */ 479316485Sdavidcs#define AR5416_SLEEP1_CAB_TIMEOUT_S 22 480316485Sdavidcs 481316485Sdavidcs#define AR5416_SLEEP2_BEACON_TIMEOUT 0xFFE00000 /* Beacon timeout (TU)*/ 482316485Sdavidcs#define AR5416_SLEEP2_BEACON_TIMEOUT_S 22 483316485Sdavidcs 484316485Sdavidcs/* Sleep Registers */ 485316485Sdavidcs#define AR_SLP32_HALFCLK_LATENCY 0x000FFFFF /* rising <-> falling edge */ 486316485Sdavidcs#define AR_SLP32_ENA 0x00100000 487316485Sdavidcs#define AR_SLP32_TSF_WRITE_STATUS 0x00200000 /* tsf update in progress */ 488316485Sdavidcs 489316485Sdavidcs#define AR_SLP32_WAKE_XTL_TIME 0x0000FFFF /* time to wake crystal */ 490316485Sdavidcs 491316485Sdavidcs#define AR_SLP32_TST_INC 0x000FFFFF 492316485Sdavidcs 493316485Sdavidcs#define AR_SLP_MIB_CLEAR 0x00000001 /* clear pending */ 494316485Sdavidcs#define AR_SLP_MIB_PENDING 0x00000002 /* clear counters */ 495316485Sdavidcs 496316485Sdavidcs#define AR_TIMER_MODE_TBTT 0x00000001 497316485Sdavidcs#define AR_TIMER_MODE_DBA 0x00000002 498316485Sdavidcs#define AR_TIMER_MODE_SWBA 0x00000004 499316485Sdavidcs#define AR_TIMER_MODE_HCF 0x00000008 500316485Sdavidcs#define AR_TIMER_MODE_TIM 0x00000010 501316485Sdavidcs#define AR_TIMER_MODE_DTIM 0x00000020 502316485Sdavidcs#define AR_TIMER_MODE_QUIET 0x00000040 503316485Sdavidcs#define AR_TIMER_MODE_NDP 0x00000080 504316485Sdavidcs#define AR_TIMER_MODE_OVERFLOW_INDEX 0x00000700 505316485Sdavidcs#define AR_TIMER_MODE_OVERFLOW_INDEX_S 8 506316485Sdavidcs#define AR_TIMER_MODE_THRESH 0xFFFFF000 507316485Sdavidcs#define AR_TIMER_MODE_THRESH_S 12 508316485Sdavidcs 509316485Sdavidcs/* PCU Misc modes */ 510316485Sdavidcs#define AR_PCU_FORCE_BSSID_MATCH 0x00000001 /* force bssid to match */ 511316485Sdavidcs#define AR_PCU_MIC_NEW_LOC_ENA 0x00000004 /* tx/rx mic keys together */ 512316485Sdavidcs#define AR_PCU_TX_ADD_TSF 0x00000008 /* add tx_tsf + int_tsf */ 513316485Sdavidcs#define AR_PCU_CCK_SIFS_MODE 0x00000010 /* assume 11b sifs */ 514316485Sdavidcs#define AR_PCU_RX_ANT_UPDT 0x00000800 /* KC_RX_ANT_UPDATE */ 515316485Sdavidcs#define AR_PCU_TXOP_TBTT_LIMIT_ENA 0x00001000 /* enforce txop / tbtt */ 516316485Sdavidcs#define AR_PCU_MISS_BCN_IN_SLEEP 0x00004000 /* count bmiss's when sleeping */ 517316485Sdavidcs#define AR_PCU_BUG_12306_FIX_ENA 0x00020000 /* use rx_clear to count sifs */ 518316485Sdavidcs#define AR_PCU_FORCE_QUIET_COLL 0x00040000 /* kill xmit for channel change */ 519316485Sdavidcs#define AR_PCU_BT_ANT_PREVENT_RX 0x00100000 520316485Sdavidcs#define AR_PCU_BT_ANT_PREVENT_RX_S 20 521316485Sdavidcs#define AR_PCU_TBTT_PROTECT 0x00200000 /* no xmit upto tbtt+20 uS */ 522316485Sdavidcs#define AR_PCU_CLEAR_VMF 0x01000000 /* clear vmf mode (fast cc)*/ 523316485Sdavidcs#define AR_PCU_CLEAR_BA_VALID 0x04000000 /* clear ba state */ 524316485Sdavidcs#define AR_PCU_SEL_EVM 0x08000000 /* select EVM data or PLCP header */ 525316485Sdavidcs 526316485Sdavidcs#define AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE 0x00000002 527316485Sdavidcs#define AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT 0x00000004 528316485Sdavidcs/* 529316485Sdavidcs * This bit enables the Multicast search based on both MAC Address and Key ID. 530316485Sdavidcs * If bit is 0, then Multicast search is based on MAC address only. 531316485Sdavidcs * For Merlin and above only. 532316485Sdavidcs */ 533316485Sdavidcs#define AR_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE 0x00000040 534316485Sdavidcs#define AR_PCU_MISC_MODE2_ENABLE_AGGWEP 0x00020000 /* Kiwi or later? */ 535316485Sdavidcs#define AR_PCU_MISC_MODE2_HWWAR1 0x00100000 536316485Sdavidcs#define AR_PCU_MISC_MODE2_HWWAR2 0x02000000 537316485Sdavidcs 538316485Sdavidcs/* For Kiwi */ 539316485Sdavidcs#define AR_MAC_PCU_ASYNC_FIFO_REG3 0x8358 540316485Sdavidcs#define AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL 0x00000400 541316485Sdavidcs#define AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET 0x80000000 542316485Sdavidcs 543316485Sdavidcs/* TSF2. For Kiwi only */ 544316485Sdavidcs#define AR_TSF2_L32 0x8390 545316485Sdavidcs#define AR_TSF2_U32 0x8394 546337517Sdavidcs 547337517Sdavidcs/* MAC Direct Connect Control. For Kiwi only */ 548337517Sdavidcs#define AR_DIRECT_CONNECT 0x83A0 549337517Sdavidcs#define AR_DC_AP_STA_EN 0x00000001 550337517Sdavidcs 551337517Sdavidcs/* GPIO Interrupt */ 552337517Sdavidcs#define AR_INTR_GPIO 0x3FF00000 /* gpio interrupted */ 553337517Sdavidcs#define AR_INTR_GPIO_S 20 554337517Sdavidcs 555337517Sdavidcs#define AR_GPIO_OUT_CTRL 0x000003FF /* 0 = out, 1 = in */ 556337517Sdavidcs#define AR_GPIO_OUT_VAL 0x000FFC00 557337517Sdavidcs#define AR_GPIO_OUT_VAL_S 10 558337517Sdavidcs#define AR_GPIO_INTR_CTRL 0x3FF00000 559316485Sdavidcs#define AR_GPIO_INTR_CTRL_S 20 560316485Sdavidcs 561316485Sdavidcs#define AR_GPIO_IN_VAL 0x0FFFC000 /* pre-9280 */ 562316485Sdavidcs#define AR_GPIO_IN_VAL_S 14 563316485Sdavidcs#define AR928X_GPIO_IN_VAL 0x000FFC00 564316485Sdavidcs#define AR928X_GPIO_IN_VAL_S 10 565316485Sdavidcs#define AR9285_GPIO_IN_VAL 0x00FFF000 566316485Sdavidcs#define AR9285_GPIO_IN_VAL_S 12 567316485Sdavidcs#define AR9287_GPIO_IN_VAL 0x003FF800 568316485Sdavidcs#define AR9287_GPIO_IN_VAL_S 11 569316485Sdavidcs 570316485Sdavidcs#define AR_GPIO_OE_OUT_DRV 0x3 /* 2 bit mask shifted by 2*bitpos */ 571316485Sdavidcs#define AR_GPIO_OE_OUT_DRV_NO 0x0 /* tristate */ 572337517Sdavidcs#define AR_GPIO_OE_OUT_DRV_LOW 0x1 /* drive if low */ 573316485Sdavidcs#define AR_GPIO_OE_OUT_DRV_HI 0x2 /* drive if high */ 574316485Sdavidcs#define AR_GPIO_OE_OUT_DRV_ALL 0x3 /* drive always */ 575316485Sdavidcs 576316485Sdavidcs#define AR_GPIO_INTR_POL_VAL 0x1FFF 577316485Sdavidcs#define AR_GPIO_INTR_POL_VAL_S 0 578316485Sdavidcs 579316485Sdavidcs#define AR_GPIO_JTAG_DISABLE 0x00020000 580316485Sdavidcs 581316485Sdavidcs#define AR_2040_JOINED_RX_CLEAR 0x00000001 /* use ctl + ext rx_clear for cca */ 582337517Sdavidcs 583316485Sdavidcs#define AR_PCU_TXBUF_CTRL_SIZE_MASK 0x7FF 584316485Sdavidcs#define AR_PCU_TXBUF_CTRL_USABLE_SIZE 0x700 585316485Sdavidcs#define AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE 0x380 586316485Sdavidcs 587316485Sdavidcs/* IFS, SIFS, slot, etc for Async FIFO mode (Kiwi) */ 588316485Sdavidcs#define AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR 0x000003AB 589316485Sdavidcs#define AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR 0x16001D56 590316485Sdavidcs#define AR_USEC_ASYNC_FIFO_DUR 0x12e00074 591316485Sdavidcs#define AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR 0x00000420 592316485Sdavidcs#define AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR 0x0000A5EB 593316485Sdavidcs 594316485Sdavidcs/* Used by Kiwi Async FIFO */ 595316485Sdavidcs#define AR_MAC_PCU_LOGIC_ANALYZER 0x8264 596316485Sdavidcs#define AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768 0x20000000 597316485Sdavidcs 598316485Sdavidcs/* Eeprom defines */ 599316485Sdavidcs#define AR_EEPROM_STATUS_DATA_VAL 0x0000ffff 600316485Sdavidcs#define AR_EEPROM_STATUS_DATA_VAL_S 0 601316485Sdavidcs#define AR_EEPROM_STATUS_DATA_BUSY 0x00010000 602316485Sdavidcs#define AR_EEPROM_STATUS_DATA_BUSY_ACCESS 0x00020000 603316485Sdavidcs#define AR_EEPROM_STATUS_DATA_PROT_ACCESS 0x00040000 604316485Sdavidcs#define AR_EEPROM_STATUS_DATA_ABSENT_ACCESS 0x00080000 605316485Sdavidcs 606316485Sdavidcs/* 607316485Sdavidcs * AR5212 defines the MAC revision mask as 0xF, but both ath9k and 608316485Sdavidcs * the Atheros HAL define it as 0x7. 609316485Sdavidcs * 610316485Sdavidcs * What this means however is AR5416 silicon revisions have 611316485Sdavidcs * changed. The below macros are for what is contained in the 612316485Sdavidcs * lower four bits; if the lower three bits are taken into account 613316485Sdavidcs * the revisions become 1.0 => 0x0, 2.0 => 0x1, 2.2 => 0x2. 614316485Sdavidcs */ 615316485Sdavidcs 616316485Sdavidcs/* These are the legacy revisions, with a four bit AR_SREV_REVISION mask */ 617316485Sdavidcs#define AR_SREV_REVISION_OWL_10 0x08 618316485Sdavidcs#define AR_SREV_REVISION_OWL_20 0x09 619316485Sdavidcs#define AR_SREV_REVISION_OWL_22 0x0a 620316485Sdavidcs 621316485Sdavidcs#define AR_RAD5133_SREV_MAJOR 0xc0 /* Fowl: 2+5G/3x3 */ 622316485Sdavidcs#define AR_RAD2133_SREV_MAJOR 0xd0 /* Fowl: 2G/3x3 */ 623316485Sdavidcs#define AR_RAD5122_SREV_MAJOR 0xe0 /* Fowl: 5G/2x2 */ 624316485Sdavidcs#define AR_RAD2122_SREV_MAJOR 0xf0 /* Fowl: 2+5G/2x2 */ 625316485Sdavidcs 626316485Sdavidcs/* Test macro for owl 1.0 */ 627316485Sdavidcs#define IS_5416V1(_ah) (AR_SREV_OWL((_ah)) && AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_OWL_10) 628316485Sdavidcs#define IS_5416V2(_ah) (AR_SREV_OWL((_ah)) && AH_PRIVATE((_ah))->ah_macRev >= AR_SREV_REVISION_OWL_20) 629316485Sdavidcs#define IS_5416V2_2(_ah) (AR_SREV_OWL((_ah)) && AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_OWL_22) 630316485Sdavidcs 631316485Sdavidcs/* Misc; compatibility with Atheros HAL */ 632316485Sdavidcs#define AR_SREV_5416_V20_OR_LATER(_ah) (AR_SREV_HOWL((_ah)) || AR_SREV_OWL_20_OR_LATER(_ah)) 633316485Sdavidcs#define AR_SREV_5416_V22_OR_LATER(_ah) (AR_SREV_HOWL((_ah)) || AR_SREV_OWL_22_OR_LATER(_ah)) 634316485Sdavidcs 635316485Sdavidcs/* Expanded Mac Silicon Rev (16 bits starting with Sowl) */ 636316485Sdavidcs#define AR_XSREV_ID 0xFFFFFFFF /* Chip ID */ 637316485Sdavidcs#define AR_XSREV_ID_S 0 638316485Sdavidcs#define AR_XSREV_VERSION 0xFFFC0000 /* Chip version */ 639316485Sdavidcs#define AR_XSREV_VERSION_S 18 640316485Sdavidcs#define AR_XSREV_TYPE 0x0003F000 /* Chip type */ 641316485Sdavidcs#define AR_XSREV_TYPE_S 12 642316485Sdavidcs#define AR_XSREV_TYPE_CHAIN 0x00001000 /* Chain Mode (1:3 chains, 643316485Sdavidcs * 0:2 chains) */ 644316485Sdavidcs#define AR_XSREV_TYPE_HOST_MODE 0x00002000 /* Host Mode (1:PCI, 0:PCIe) */ 645316485Sdavidcs#define AR_XSREV_REVISION 0x00000F00 646316485Sdavidcs#define AR_XSREV_REVISION_S 8 647316485Sdavidcs 648316485Sdavidcs#define AR_XSREV_VERSION_OWL_PCI 0x0D 649316485Sdavidcs#define AR_XSREV_VERSION_OWL_PCIE 0x0C 650316485Sdavidcs 651316485Sdavidcs 652316485Sdavidcs/* 653316485Sdavidcs * These are from ath9k/Atheros and assume an AR_SREV version mask 654316485Sdavidcs * of 0x07, rather than 0x0F which is being used in the FreeBSD HAL. 655316485Sdavidcs * Thus, don't use these values as they're incorrect here; use 656316485Sdavidcs * AR_SREV_REVISION_OWL_{10,20,22}. 657316485Sdavidcs */ 658316485Sdavidcs#if 0 659316485Sdavidcs#define AR_XSREV_REVISION_OWL_10 0 /* Owl 1.0 */ 660316485Sdavidcs#define AR_XSREV_REVISION_OWL_20 1 /* Owl 2.0/2.1 */ 661316485Sdavidcs#define AR_XSREV_REVISION_OWL_22 2 /* Owl 2.2 */ 662316485Sdavidcs#endif 663316485Sdavidcs 664316485Sdavidcs#define AR_XSREV_VERSION_HOWL 0x14 /* Howl (AR9130) */ 665316485Sdavidcs#define AR_XSREV_VERSION_SOWL 0x40 /* Sowl (AR9160) */ 666316485Sdavidcs#define AR_XSREV_REVISION_SOWL_10 0 /* Sowl 1.0 */ 667316485Sdavidcs#define AR_XSREV_REVISION_SOWL_11 1 /* Sowl 1.1 */ 668316485Sdavidcs#define AR_XSREV_VERSION_MERLIN 0x80 /* Merlin Version */ 669316485Sdavidcs#define AR_XSREV_REVISION_MERLIN_10 0 /* Merlin 1.0 */ 670316485Sdavidcs#define AR_XSREV_REVISION_MERLIN_20 1 /* Merlin 2.0 */ 671316485Sdavidcs#define AR_XSREV_REVISION_MERLIN_21 2 /* Merlin 2.1 */ 672316485Sdavidcs#define AR_XSREV_VERSION_KITE 0xC0 /* Kite Version */ 673316485Sdavidcs#define AR_XSREV_REVISION_KITE_10 0 /* Kite 1.0 */ 674316485Sdavidcs#define AR_XSREV_REVISION_KITE_11 1 /* Kite 1.1 */ 675316485Sdavidcs#define AR_XSREV_REVISION_KITE_12 2 /* Kite 1.2 */ 676316485Sdavidcs#define AR_XSREV_VERSION_KIWI 0x180 /* Kiwi (AR9287) */ 677316485Sdavidcs#define AR_XSREV_REVISION_KIWI_10 0 /* Kiwi 1.0 */ 678316485Sdavidcs#define AR_XSREV_REVISION_KIWI_11 1 /* Kiwi 1.1 */ 679316485Sdavidcs#define AR_XSREV_REVISION_KIWI_12 2 /* Kiwi 1.2 */ 680316485Sdavidcs#define AR_XSREV_REVISION_KIWI_13 3 /* Kiwi 1.3 */ 681316485Sdavidcs 682316485Sdavidcs/* Owl (AR5416) */ 683316485Sdavidcs#define AR_SREV_OWL(_ah) \ 684316485Sdavidcs ((AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_OWL_PCI) || \ 685316485Sdavidcs (AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_OWL_PCIE)) 686316485Sdavidcs 687316485Sdavidcs#define AR_SREV_OWL_20_OR_LATER(_ah) \ 688316485Sdavidcs ((AR_SREV_OWL(_ah) && \ 689316485Sdavidcs AH_PRIVATE((_ah))->ah_macRev >= AR_SREV_REVISION_OWL_20) || \ 690316485Sdavidcs AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_HOWL) 691316485Sdavidcs 692316485Sdavidcs#define AR_SREV_OWL_22_OR_LATER(_ah) \ 693316485Sdavidcs ((AR_SREV_OWL(_ah) && \ 694316485Sdavidcs AH_PRIVATE((_ah))->ah_macRev >= AR_SREV_REVISION_OWL_22) || \ 695316485Sdavidcs AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_HOWL) 696316485Sdavidcs 697316485Sdavidcs/* Howl (AR9130) */ 698316485Sdavidcs 699316485Sdavidcs#define AR_SREV_HOWL(_ah) \ 700316485Sdavidcs (AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_HOWL) 701316485Sdavidcs 702337517Sdavidcs#define AR_SREV_9100(_ah) AR_SREV_HOWL(_ah) 703316485Sdavidcs 704316485Sdavidcs/* Sowl (AR9160) */ 705316485Sdavidcs 706316485Sdavidcs#define AR_SREV_SOWL(_ah) \ 707316485Sdavidcs (AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_SOWL) 708316485Sdavidcs 709316485Sdavidcs#define AR_SREV_SOWL_10_OR_LATER(_ah) \ 710316485Sdavidcs (AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_SOWL) 711316485Sdavidcs 712316485Sdavidcs#define AR_SREV_SOWL_11(_ah) \ 713316485Sdavidcs (AR_SREV_SOWL(_ah) && \ 714316485Sdavidcs AH_PRIVATE((_ah))->ah_macRev == AR_XSREV_REVISION_SOWL_11) 715 716/* Merlin (AR9280) */ 717 718#define AR_SREV_MERLIN(_ah) \ 719 (AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_MERLIN) 720 721#define AR_SREV_MERLIN_10_OR_LATER(_ah) \ 722 (AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_MERLIN) 723 724#define AR_SREV_MERLIN_20(_ah) \ 725 (AR_SREV_MERLIN(_ah) && \ 726 AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_MERLIN_20) 727 728#define AR_SREV_MERLIN_20_OR_LATER(_ah) \ 729 ((AH_PRIVATE((_ah))->ah_macVersion > AR_XSREV_VERSION_MERLIN) || \ 730 (AR_SREV_MERLIN((_ah)) && \ 731 AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_MERLIN_20)) 732 733/* Kite (AR9285) */ 734 735#define AR_SREV_KITE(_ah) \ 736 (AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_KITE) 737 738#define AR_SREV_KITE_10_OR_LATER(_ah) \ 739 (AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_KITE) 740 741#define AR_SREV_KITE_11(_ah) \ 742 (AR_SREV_KITE(ah) && \ 743 AH_PRIVATE((_ah))->ah_macRev == AR_XSREV_REVISION_KITE_11) 744 745#define AR_SREV_KITE_11_OR_LATER(_ah) \ 746 ((AH_PRIVATE((_ah))->ah_macVersion > AR_XSREV_VERSION_KITE) || \ 747 (AR_SREV_KITE((_ah)) && \ 748 AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_KITE_11)) 749 750#define AR_SREV_KITE_12(_ah) \ 751 (AR_SREV_KITE(ah) && \ 752 AH_PRIVATE((_ah))->ah_macRev == AR_XSREV_REVISION_KITE_12) 753 754#define AR_SREV_KITE_12_OR_LATER(_ah) \ 755 ((AH_PRIVATE((_ah))->ah_macVersion > AR_XSREV_VERSION_KITE) || \ 756 (AR_SREV_KITE((_ah)) && \ 757 AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_KITE_12)) 758 759#define AR_SREV_9285E_20(_ah) \ 760 (AR_SREV_KITE_12_OR_LATER(_ah) && \ 761 ((OS_REG_READ(_ah, AR_AN_SYNTH9) & 0x7) == 0x1)) 762 763#define AR_SREV_KIWI(_ah) \ 764 (AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_KIWI) 765 766#define AR_SREV_KIWI_10_OR_LATER(_ah) \ 767 (AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_KIWI) 768 769/* XXX TODO: make these handle macVersion > Kiwi */ 770#define AR_SREV_KIWI_11_OR_LATER(_ah) \ 771 (AR_SREV_KIWI(_ah) && \ 772 AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_KIWI_11) 773 774#define AR_SREV_KIWI_11(_ah) \ 775 (AR_SREV_KIWI(_ah) && \ 776 AH_PRIVATE((_ah))->ah_macRev == AR_XSREV_REVISION_KIWI_11) 777 778#define AR_SREV_KIWI_12(_ah) \ 779 (AR_SREV_KIWI(_ah) && \ 780 AH_PRIVATE((_ah))->ah_macRev == AR_XSREV_REVISION_KIWI_12) 781 782#define AR_SREV_KIWI_12_OR_LATER(_ah) \ 783 (AR_SREV_KIWI(_ah) && \ 784 AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_KIWI_12) 785 786#define AR_SREV_KIWI_13_OR_LATER(_ah) \ 787 (AR_SREV_KIWI(_ah) && \ 788 AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_KIWI_13) 789 790 791/* Not yet implemented chips */ 792#define AR_SREV_9271(_ah) 0 793 794#endif /* _DEV_ATH_AR5416REG_H */ 795