ar5416reg.h revision 234692
1/* 2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar5416/ar5416reg.h 234692 2012-04-26 02:03:16Z adrian $ 18 */ 19#ifndef _DEV_ATH_AR5416REG_H 20#define _DEV_ATH_AR5416REG_H 21 22#include <dev/ath/ath_hal/ar5212/ar5212reg.h> 23 24/* 25 * Register added starting with the AR5416 26 */ 27#define AR_MIRT 0x0020 /* interrupt rate threshold */ 28#define AR_TIMT 0x0028 /* Tx Interrupt mitigation threshold */ 29#define AR_RIMT 0x002C /* Rx Interrupt mitigation threshold */ 30#define AR_GTXTO 0x0064 /* global transmit timeout */ 31#define AR_GTTM 0x0068 /* global transmit timeout mode */ 32#define AR_CST 0x006C /* carrier sense timeout */ 33#define AR_MAC_LED 0x1f04 /* LED control */ 34#define AR_WA 0x4004 /* PCIE work-arounds */ 35#define AR_PCIE_PM_CTRL 0x4014 36#define AR_AHB_MODE 0x4024 /* AHB mode for dma */ 37#define AR_INTR_SYNC_CAUSE_CLR 0x4028 /* clear interrupt */ 38#define AR_INTR_SYNC_CAUSE 0x4028 /* check pending interrupts */ 39#define AR_INTR_SYNC_ENABLE 0x402c /* enable interrupts */ 40#define AR_INTR_ASYNC_MASK 0x4030 /* asynchronous interrupt mask */ 41#define AR_INTR_SYNC_MASK 0x4034 /* synchronous interrupt mask */ 42#define AR_INTR_ASYNC_CAUSE 0x4038 /* check pending interrupts */ 43#define AR_INTR_ASYNC_CAUSE_CLR 0x4038 /* clear pending interrupts */ 44#define AR_INTR_ASYNC_ENABLE 0x403c /* enable interrupts */ 45#define AR5416_PCIE_SERDES 0x4040 46#define AR5416_PCIE_SERDES2 0x4044 47#define AR_GPIO_IN_OUT 0x4048 /* GPIO input/output register */ 48#define AR_GPIO_OE_OUT 0x404c /* GPIO output enable register */ 49#define AR_GPIO_INTR_POL 0x4050 /* GPIO interrupt polarity */ 50 51#define AR_GPIO_INPUT_EN_VAL 0x4054 /* GPIO input enable and value */ 52#define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF 0x00000004 53#define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_S 2 54#define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF 0x00000008 55#define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_S 3 56#define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_DEF 0x00000010 57#define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_S 4 58#define AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF 0x00000080 59#define AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF_S 7 60#define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB 0x00000400 61#define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB_S 10 62#define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_BB 0x00000800 63#define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_BB_S 11 64#define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB 0x00001000 65#define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB_S 12 66#define AR_GPIO_INPUT_EN_VAL_RFSILENT_BB 0x00008000 67#define AR_GPIO_INPUT_EN_VAL_RFSILENT_BB_S 15 68#define AR_GPIO_RTC_RESET_OVERRIDE_ENABLE 0x00010000 69#define AR_GPIO_JTAG_DISABLE 0x00020000 70 71#define AR_GPIO_INPUT_MUX1 0x4058 72#define AR_GPIO_INPUT_MUX1_BT_PRIORITY 0x00000f00 73#define AR_GPIO_INPUT_MUX1_BT_PRIORITY_S 8 74#define AR_GPIO_INPUT_MUX1_BT_FREQUENCY 0x0000f000 75#define AR_GPIO_INPUT_MUX1_BT_FREQUENCY_S 12 76#define AR_GPIO_INPUT_MUX1_BT_ACTIVE 0x000f0000 77#define AR_GPIO_INPUT_MUX1_BT_ACTIVE_S 16 78 79#define AR_GPIO_INPUT_MUX2 0x405c 80#define AR_GPIO_INPUT_MUX2_CLK25 0x0000000f 81#define AR_GPIO_INPUT_MUX2_CLK25_S 0 82#define AR_GPIO_INPUT_MUX2_RFSILENT 0x000000f0 83#define AR_GPIO_INPUT_MUX2_RFSILENT_S 4 84#define AR_GPIO_INPUT_MUX2_RTC_RESET 0x00000f00 85#define AR_GPIO_INPUT_MUX2_RTC_RESET_S 8 86 87#define AR_GPIO_OUTPUT_MUX1 0x4060 88#define AR_GPIO_OUTPUT_MUX2 0x4064 89#define AR_GPIO_OUTPUT_MUX3 0x4068 90 91#define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0 92#define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1 93#define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2 94#define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3 95#define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4 96#define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5 97#define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6 98 99#define AR_EEPROM_STATUS_DATA 0x407c 100#define AR_OBS 0x4080 101#define AR_GPIO_PDPU 0x4088 102 103#ifdef AH_SUPPORT_AR9130 104#define AR_RTC_BASE 0x20000 105#else 106#define AR_RTC_BASE 0x7000 107#endif /* AH_SUPPORT_AR9130 */ 108 109#define AR_RTC_RC AR_RTC_BASE + 0x00 /* reset control */ 110#define AR_RTC_PLL_CONTROL AR_RTC_BASE + 0x14 111#define AR_RTC_RESET AR_RTC_BASE + 0x40 /* RTC reset register */ 112#define AR_RTC_STATUS AR_RTC_BASE + 0x44 /* system sleep status */ 113#define AR_RTC_SLEEP_CLK AR_RTC_BASE + 0x48 114#define AR_RTC_FORCE_WAKE AR_RTC_BASE + 0x4c /* control MAC force wake */ 115#define AR_RTC_INTR_CAUSE AR_RTC_BASE + 0x50 /* RTC interrupt cause/clear */ 116#define AR_RTC_INTR_ENABLE AR_RTC_BASE + 0x54 /* RTC interrupt enable */ 117#define AR_RTC_INTR_MASK AR_RTC_BASE + 0x58 /* RTC interrupt mask */ 118 119#ifdef AH_SUPPORT_AR9130 120/* RTC_DERIVED_* - only for AR9130 */ 121#define AR_RTC_DERIVED_CLK (AR_RTC_BASE + 0x0038) 122#define AR_RTC_DERIVED_CLK_PERIOD 0x0000fffe 123#define AR_RTC_DERIVED_CLK_PERIOD_S 1 124#endif /* AH_SUPPORT_AR9130 */ 125 126#define AR_RESET_TSF 0x8020 127 128/* 129 * AR_SLEEP1 / AR_SLEEP2 are in the same place as in 130 * AR5212, however the fields have changed. 131 */ 132#define AR5416_SLEEP1 0x80d4 133#define AR5416_SLEEP2 0x80d8 134#define AR_RXFIFO_CFG 0x8114 135#define AR_PHY_ERR_1 0x812c 136#define AR_PHY_ERR_MASK_1 0x8130 /* mask for AR_PHY_ERR_1 */ 137#define AR_PHY_ERR_2 0x8134 138#define AR_PHY_ERR_MASK_2 0x8138 /* mask for AR_PHY_ERR_2 */ 139#define AR_TSFOOR_THRESHOLD 0x813c 140#define AR_PHY_ERR_3 0x8168 141#define AR_PHY_ERR_MASK_3 0x816c /* mask for AR_PHY_ERR_3 */ 142#define AR_BT_COEX_WEIGHT2 0x81c4 143#define AR_TXOP_X 0x81ec /* txop for legacy non-qos */ 144#define AR_TXOP_0_3 0x81f0 /* txop for various tid's */ 145#define AR_TXOP_4_7 0x81f4 146#define AR_TXOP_8_11 0x81f8 147#define AR_TXOP_12_15 0x81fc 148/* generic timers based on tsf - all uS */ 149#define AR_NEXT_TBTT 0x8200 150#define AR_NEXT_DBA 0x8204 151#define AR_NEXT_SWBA 0x8208 152#define AR_NEXT_CFP 0x8208 153#define AR_NEXT_HCF 0x820C 154#define AR_NEXT_TIM 0x8210 155#define AR_NEXT_DTIM 0x8214 156#define AR_NEXT_QUIET 0x8218 157#define AR_NEXT_NDP 0x821C 158#define AR5416_BEACON_PERIOD 0x8220 159#define AR_DBA_PERIOD 0x8224 160#define AR_SWBA_PERIOD 0x8228 161#define AR_HCF_PERIOD 0x822C 162#define AR_TIM_PERIOD 0x8230 163#define AR_DTIM_PERIOD 0x8234 164#define AR_QUIET_PERIOD 0x8238 165#define AR_NDP_PERIOD 0x823C 166#define AR_TIMER_MODE 0x8240 167#define AR_SLP32_MODE 0x8244 168#define AR_SLP32_WAKE 0x8248 169#define AR_SLP32_INC 0x824c 170#define AR_SLP_CNT 0x8250 /* 32kHz cycles with mac asleep */ 171#define AR_SLP_CYCLE_CNT 0x8254 /* absolute number of 32kHz cycles */ 172#define AR_SLP_MIB_CTRL 0x8258 173#define AR_2040_MODE 0x8318 174#define AR_EXTRCCNT 0x8328 /* extension channel rx clear count */ 175#define AR_SELFGEN_MASK 0x832c /* rx and cal chain masks */ 176#define AR_PCU_TXBUF_CTRL 0x8340 177#define AR_PCU_MISC_MODE2 0x8344 178 179/* DMA & PCI Registers in PCI space (usable during sleep)*/ 180#define AR_RC_AHB 0x00000001 /* AHB reset */ 181#define AR_RC_APB 0x00000002 /* APB reset */ 182#define AR_RC_HOSTIF 0x00000100 /* host interface reset */ 183 184#define AR_MIRT_VAL 0x0000ffff /* in uS */ 185#define AR_MIRT_VAL_S 16 186 187#define AR_TIMT_LAST 0x0000ffff /* Last packet threshold */ 188#define AR_TIMT_LAST_S 0 189#define AR_TIMT_FIRST 0xffff0000 /* First packet threshold */ 190#define AR_TIMT_FIRST_S 16 191 192#define AR_RIMT_LAST 0x0000ffff /* Last packet threshold */ 193#define AR_RIMT_LAST_S 0 194#define AR_RIMT_FIRST 0xffff0000 /* First packet threshold */ 195#define AR_RIMT_FIRST_S 16 196 197#define AR_GTXTO_TIMEOUT_COUNTER 0x0000FFFF // Mask for timeout counter (in TUs) 198#define AR_GTXTO_TIMEOUT_LIMIT 0xFFFF0000 // Mask for timeout limit (in TUs) 199#define AR_GTXTO_TIMEOUT_LIMIT_S 16 // Shift for timeout limit 200 201#define AR_GTTM_USEC 0x00000001 // usec strobe 202#define AR_GTTM_IGNORE_IDLE 0x00000002 // ignore channel idle 203#define AR_GTTM_RESET_IDLE 0x00000004 // reset counter on channel idle low 204#define AR_GTTM_CST_USEC 0x00000008 // CST usec strobe 205 206#define AR_CST_TIMEOUT_COUNTER 0x0000FFFF // Mask for timeout counter (in TUs) 207#define AR_CST_TIMEOUT_LIMIT 0xFFFF0000 // Mask for timeout limit (in TUs) 208#define AR_CST_TIMEOUT_LIMIT_S 16 // Shift for timeout limit 209 210/* MAC tx DMA size config */ 211#define AR_TXCFG_DMASZ_MASK 0x00000003 212#define AR_TXCFG_DMASZ_4B 0 213#define AR_TXCFG_DMASZ_8B 1 214#define AR_TXCFG_DMASZ_16B 2 215#define AR_TXCFG_DMASZ_32B 3 216#define AR_TXCFG_DMASZ_64B 4 217#define AR_TXCFG_DMASZ_128B 5 218#define AR_TXCFG_DMASZ_256B 6 219#define AR_TXCFG_DMASZ_512B 7 220#define AR_TXCFG_ATIM_TXPOLICY 0x00000800 221 222/* MAC rx DMA size config */ 223#define AR_RXCFG_DMASZ_MASK 0x00000007 224#define AR_RXCFG_DMASZ_4B 0 225#define AR_RXCFG_DMASZ_8B 1 226#define AR_RXCFG_DMASZ_16B 2 227#define AR_RXCFG_DMASZ_32B 3 228#define AR_RXCFG_DMASZ_64B 4 229#define AR_RXCFG_DMASZ_128B 5 230#define AR_RXCFG_DMASZ_256B 6 231#define AR_RXCFG_DMASZ_512B 7 232 233/* MAC Led registers */ 234#define AR_CFG_SCLK_RATE_IND 0x00000003 /* sleep clock indication */ 235#define AR_CFG_SCLK_RATE_IND_S 0 236#define AR_CFG_SCLK_32MHZ 0x00000000 /* Sleep clock rate */ 237#define AR_CFG_SCLK_4MHZ 0x00000001 /* Sleep clock rate */ 238#define AR_CFG_SCLK_1MHZ 0x00000002 /* Sleep clock rate */ 239#define AR_CFG_SCLK_32KHZ 0x00000003 /* Sleep clock rate */ 240#define AR_MAC_LED_BLINK_SLOW 0x00000008 /* LED slowest blink rate mode */ 241#define AR_MAC_LED_BLINK_THRESH_SEL 0x00000070 /* LED blink threshold select */ 242#define AR_MAC_LED_MODE 0x00000380 /* LED mode select */ 243#define AR_MAC_LED_MODE_S 7 244#define AR_MAC_LED_MODE_PROP 0 /* Blink prop to filtered tx/rx */ 245#define AR_MAC_LED_MODE_RPROP 1 /* Blink prop to unfiltered tx/rx */ 246#define AR_MAC_LED_MODE_SPLIT 2 /* Blink power for tx/net for rx */ 247#define AR_MAC_LED_MODE_RAND 3 /* Blink randomly */ 248#define AR_MAC_LED_MODE_POWON 5 /* Power LED on (s/w control) */ 249#define AR_MAC_LED_MODE_NETON 6 /* Network LED on (s/w control) */ 250#define AR_MAC_LED_ASSOC 0x00000c00 251#define AR_MAC_LED_ASSOC_NONE 0x0 /* STA is not associated or trying */ 252#define AR_MAC_LED_ASSOC_ACTIVE 0x1 /* STA is associated */ 253#define AR_MAC_LED_ASSOC_PEND 0x2 /* STA is trying to associate */ 254#define AR_MAC_LED_ASSOC_S 10 255 256#define AR_WA_UNTIE_RESET_EN 0x00008000 /* ena PCI reset to POR */ 257#define AR_WA_RESET_EN 0x00040000 /* ena AR_WA_UNTIE_RESET_EN */ 258#define AR_WA_ANALOG_SHIFT 0x00100000 259#define AR_WA_POR_SHORT 0x00200000 /* PCIE phy reset control */ 260#define AR_WA_D3_L1_DISABLE 0x00800000 /* bit 23 */ 261 262#define AR_WA_DEFAULT 0x0000073f 263#define AR9280_WA_DEFAULT 0x0040073b /* disable bit 2, see commit */ 264#define AR9285_WA_DEFAULT 0x004a05cb 265 266#define AR_PCIE_PM_CTRL_ENA 0x00080000 267 268#define AR_AHB_EXACT_WR_EN 0x00000000 /* write exact bytes */ 269#define AR_AHB_BUF_WR_EN 0x00000001 /* buffer write upto cacheline*/ 270#define AR_AHB_EXACT_RD_EN 0x00000000 /* read exact bytes */ 271#define AR_AHB_CACHELINE_RD_EN 0x00000002 /* read upto end of cacheline */ 272#define AR_AHB_PREFETCH_RD_EN 0x00000004 /* prefetch upto page boundary*/ 273#define AR_AHB_PAGE_SIZE_1K 0x00000000 /* set page-size as 1k */ 274#define AR_AHB_PAGE_SIZE_2K 0x00000008 /* set page-size as 2k */ 275#define AR_AHB_PAGE_SIZE_4K 0x00000010 /* set page-size as 4k */ 276/* Kiwi */ 277#define AR_AHB_CUSTOM_BURST_EN 0x000000C0 /* set Custom Burst Mode */ 278#define AR_AHB_CUSTOM_BURST_EN_S 6 /* set Custom Burst Mode */ 279#define AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL 3 /* set both bits in Async FIFO mode */ 280 281/* MAC PCU Registers */ 282#define AR_STA_ID1_PRESERVE_SEQNUM 0x20000000 /* Don't replace seq num */ 283 284/* Extended PCU DIAG_SW control fields */ 285#define AR_DIAG_DUAL_CHAIN_INFO 0x01000000 /* dual chain channel info */ 286#define AR_DIAG_RX_ABORT 0x02000000 /* abort rx */ 287#define AR_DIAG_SATURATE_CCNT 0x04000000 /* sat. cycle cnts (no shift) */ 288#define AR_DIAG_OBS_PT_SEL2 0x08000000 /* observation point sel */ 289#define AR_DIAG_RXCLEAR_CTL_LOW 0x10000000 /* force rx_clear(ctl) low/busy */ 290#define AR_DIAG_RXCLEAR_EXT_LOW 0x20000000 /* force rx_clear(ext) low/busy */ 291 292#define AR_TXOP_X_VAL 0x000000FF 293 294#define AR_RESET_TSF_ONCE 0x01000000 /* reset tsf once; self-clears*/ 295 296/* Interrupts */ 297#define AR_ISR_TXMINTR 0x00080000 /* Maximum interrupt tx rate */ 298#define AR_ISR_RXMINTR 0x01000000 /* Maximum interrupt rx rate */ 299#define AR_ISR_GENTMR 0x10000000 /* OR of generic timer bits in S5 */ 300#define AR_ISR_TXINTM 0x40000000 /* Tx int after mitigation */ 301#define AR_ISR_RXINTM 0x80000000 /* Rx int after mitigation */ 302 303#define AR_ISR_S2_CST 0x00400000 /* Carrier sense timeout */ 304#define AR_ISR_S2_GTT 0x00800000 /* Global transmit timeout */ 305#define AR_ISR_S2_TSFOOR 0x40000000 /* RX TSF out of range */ 306 307#define AR_ISR_S5 0x0098 308#define AR_ISR_S5_S 0x00d8 309#define AR_ISR_S5_GENTIMER7 0x00000080 // Mask for timer 7 trigger 310#define AR_ISR_S5_TIM_TIMER 0x00000010 // TIM Timer ISR 311#define AR_ISR_S5_DTIM_TIMER 0x00000020 // DTIM Timer ISR 312#define AR_ISR_S5_GENTIMER_TRIG 0x0000FF80 // ISR for generic timer trigger 7-15 313#define AR_ISR_S5_GENTIMER_TRIG_S 0 314#define AR_ISR_S5_GENTIMER_THRESH 0xFF800000 // ISR for generic timer threshold 7-15 315#define AR_ISR_S5_GENTIMER_THRESH_S 16 316 317#define AR_INTR_SPURIOUS 0xffffffff 318#define AR_INTR_RTC_IRQ 0x00000001 /* rtc in shutdown state */ 319#define AR_INTR_MAC_IRQ 0x00000002 /* pending mac interrupt */ 320#define AR_INTR_EEP_PROT_ACCESS 0x00000004 /* eeprom protected access */ 321#define AR_INTR_MAC_AWAKE 0x00020000 /* mac is awake */ 322#define AR_INTR_MAC_ASLEEP 0x00040000 /* mac is asleep */ 323 324/* Interrupt Mask Registers */ 325#define AR_IMR_TXMINTR 0x00080000 /* Maximum interrupt tx rate */ 326#define AR_IMR_RXMINTR 0x01000000 /* Maximum interrupt rx rate */ 327#define AR_IMR_TXINTM 0x40000000 /* Tx int after mitigation */ 328#define AR_IMR_RXINTM 0x80000000 /* Rx int after mitigation */ 329 330#define AR_IMR_S2_CST 0x00400000 /* Carrier sense timeout */ 331#define AR_IMR_S2_GTT 0x00800000 /* Global transmit timeout */ 332 333/* synchronous interrupt signals */ 334#define AR_INTR_SYNC_RTC_IRQ 0x00000001 335#define AR_INTR_SYNC_MAC_IRQ 0x00000002 336#define AR_INTR_SYNC_EEPROM_ILLEGAL_ACCESS 0x00000004 337#define AR_INTR_SYNC_APB_TIMEOUT 0x00000008 338#define AR_INTR_SYNC_PCI_MODE_CONFLICT 0x00000010 339#define AR_INTR_SYNC_HOST1_FATAL 0x00000020 340#define AR_INTR_SYNC_HOST1_PERR 0x00000040 341#define AR_INTR_SYNC_TRCV_FIFO_PERR 0x00000080 342#define AR_INTR_SYNC_RADM_CPL_EP 0x00000100 343#define AR_INTR_SYNC_RADM_CPL_DLLP_ABORT 0x00000200 344#define AR_INTR_SYNC_RADM_CPL_TLP_ABORT 0x00000400 345#define AR_INTR_SYNC_RADM_CPL_ECRC_ERR 0x00000800 346#define AR_INTR_SYNC_RADM_CPL_TIMEOUT 0x00001000 347#define AR_INTR_SYNC_LOCAL_TIMEOUT 0x00002000 348#define AR_INTR_SYNC_PM_ACCESS 0x00004000 349#define AR_INTR_SYNC_MAC_AWAKE 0x00008000 350#define AR_INTR_SYNC_MAC_ASLEEP 0x00010000 351#define AR_INTR_SYNC_MAC_SLEEP_ACCESS 0x00020000 352#define AR_INTR_SYNC_ALL 0x0003FFFF 353 354/* default synchronous interrupt signals enabled */ 355#define AR_INTR_SYNC_DEFAULT \ 356 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR | \ 357 AR_INTR_SYNC_RADM_CPL_EP | AR_INTR_SYNC_RADM_CPL_DLLP_ABORT | \ 358 AR_INTR_SYNC_RADM_CPL_TLP_ABORT | AR_INTR_SYNC_RADM_CPL_ECRC_ERR | \ 359 AR_INTR_SYNC_RADM_CPL_TIMEOUT | AR_INTR_SYNC_LOCAL_TIMEOUT | \ 360 AR_INTR_SYNC_MAC_SLEEP_ACCESS) 361 362#define AR_INTR_SYNC_MASK_GPIO 0xFFFC0000 363#define AR_INTR_SYNC_MASK_GPIO_S 18 364 365#define AR_INTR_SYNC_ENABLE_GPIO 0xFFFC0000 366#define AR_INTR_SYNC_ENABLE_GPIO_S 18 367 368#define AR_INTR_ASYNC_MASK_GPIO 0xFFFC0000 /* async int mask */ 369#define AR_INTR_ASYNC_MASK_GPIO_S 18 370 371#define AR_INTR_ASYNC_CAUSE_GPIO 0xFFFC0000 /* GPIO interrupts */ 372#define AR_INTR_ASYNC_USED (AR_INTR_MAC_IRQ | AR_INTR_ASYNC_CAUSE_GPIO) 373 374#define AR_INTR_ASYNC_ENABLE_GPIO 0xFFFC0000 /* enable interrupts */ 375#define AR_INTR_ASYNC_ENABLE_GPIO_S 18 376 377/* RTC registers */ 378#define AR_RTC_RC_M 0x00000003 379#define AR_RTC_RC_MAC_WARM 0x00000001 380#define AR_RTC_RC_MAC_COLD 0x00000002 381#ifdef AH_SUPPORT_AR9130 382#define AR_RTC_RC_COLD_RESET 0x00000004 383#define AR_RTC_RC_WARM_RESET 0x00000008 384#endif /* AH_SUPPORT_AR9130 */ 385#define AR_RTC_PLL_DIV 0x0000001f 386#define AR_RTC_PLL_DIV_S 0 387#define AR_RTC_PLL_DIV2 0x00000020 388#define AR_RTC_PLL_REFDIV_5 0x000000c0 389 390#define AR_RTC_SOWL_PLL_DIV 0x000003ff 391#define AR_RTC_SOWL_PLL_DIV_S 0 392#define AR_RTC_SOWL_PLL_REFDIV 0x00003C00 393#define AR_RTC_SOWL_PLL_REFDIV_S 10 394#define AR_RTC_SOWL_PLL_CLKSEL 0x0000C000 395#define AR_RTC_SOWL_PLL_CLKSEL_S 14 396 397#define AR_RTC_RESET_EN 0x00000001 /* Reset RTC bit */ 398 399#define AR_RTC_PM_STATUS_M 0x0000000f /* Pwr Mgmt Status */ 400#ifdef AH_SUPPORT_AR9130 401#define AR_RTC_STATUS_M 0x0000000f /* RTC Status */ 402#else 403#define AR_RTC_STATUS_M 0x0000003f /* RTC Status */ 404#endif /* AH_SUPPORT_AR9130 */ 405#define AR_RTC_STATUS_SHUTDOWN 0x00000001 406#define AR_RTC_STATUS_ON 0x00000002 407#define AR_RTC_STATUS_SLEEP 0x00000004 408#define AR_RTC_STATUS_WAKEUP 0x00000008 409#define AR_RTC_STATUS_COLDRESET 0x00000010 /* Not currently used */ 410#define AR_RTC_STATUS_PLLCHANGE 0x00000020 /* Not currently used */ 411 412#define AR_RTC_SLEEP_DERIVED_CLK 0x2 413 414#define AR_RTC_FORCE_WAKE_EN 0x00000001 /* enable force wake */ 415#define AR_RTC_FORCE_WAKE_ON_INT 0x00000002 /* auto-wake on MAC interrupt */ 416 417#define AR_RTC_PLL_CLKSEL 0x00000300 418#define AR_RTC_PLL_CLKSEL_S 8 419 420/* AR9280: rf long shift registers */ 421#define AR_AN_RF2G1_CH0 0x7810 422#define AR_AN_RF5G1_CH0 0x7818 423#define AR_AN_RF2G1_CH1 0x7834 424#define AR_AN_RF5G1_CH1 0x783C 425#define AR_AN_TOP2 0x7894 426#define AR_AN_SYNTH9 0x7868 427 428#define AR_AN_RF2G1_CH0_OB 0x03800000 429#define AR_AN_RF2G1_CH0_OB_S 23 430#define AR_AN_RF2G1_CH0_DB 0x1C000000 431#define AR_AN_RF2G1_CH0_DB_S 26 432 433#define AR_AN_RF5G1_CH0_OB5 0x00070000 434#define AR_AN_RF5G1_CH0_OB5_S 16 435#define AR_AN_RF5G1_CH0_DB5 0x00380000 436#define AR_AN_RF5G1_CH0_DB5_S 19 437 438#define AR_AN_RF2G1_CH1_OB 0x03800000 439#define AR_AN_RF2G1_CH1_OB_S 23 440#define AR_AN_RF2G1_CH1_DB 0x1C000000 441#define AR_AN_RF2G1_CH1_DB_S 26 442 443#define AR_AN_RF5G1_CH1_OB5 0x00070000 444#define AR_AN_RF5G1_CH1_OB5_S 16 445#define AR_AN_RF5G1_CH1_DB5 0x00380000 446#define AR_AN_RF5G1_CH1_DB5_S 19 447 448#define AR_AN_TOP1 0x7890 449#define AR_AN_TOP1_DACIPMODE 0x00040000 450#define AR_AN_TOP1_DACIPMODE_S 18 451 452#define AR_AN_TOP2_XPABIAS_LVL 0xC0000000 453#define AR_AN_TOP2_XPABIAS_LVL_S 30 454#define AR_AN_TOP2_LOCALBIAS 0x00200000 455#define AR_AN_TOP2_LOCALBIAS_S 21 456#define AR_AN_TOP2_PWDCLKIND 0x00400000 457#define AR_AN_TOP2_PWDCLKIND_S 22 458 459#define AR_AN_SYNTH9_REFDIVA 0xf8000000 460#define AR_AN_SYNTH9_REFDIVA_S 27 461 462#define AR9271_AN_RF2G6_OFFS 0x07f00000 463#define AR9271_AN_RF2G6_OFFS_S 20 464 465/* Sleep control */ 466#define AR5416_SLEEP1_ASSUME_DTIM 0x00080000 467#define AR5416_SLEEP1_CAB_TIMEOUT 0xFFE00000 /* Cab timeout (TU) */ 468#define AR5416_SLEEP1_CAB_TIMEOUT_S 22 469 470#define AR5416_SLEEP2_BEACON_TIMEOUT 0xFFE00000 /* Beacon timeout (TU)*/ 471#define AR5416_SLEEP2_BEACON_TIMEOUT_S 22 472 473/* Sleep Registers */ 474#define AR_SLP32_HALFCLK_LATENCY 0x000FFFFF /* rising <-> falling edge */ 475#define AR_SLP32_ENA 0x00100000 476#define AR_SLP32_TSF_WRITE_STATUS 0x00200000 /* tsf update in progress */ 477 478#define AR_SLP32_WAKE_XTL_TIME 0x0000FFFF /* time to wake crystal */ 479 480#define AR_SLP32_TST_INC 0x000FFFFF 481 482#define AR_SLP_MIB_CLEAR 0x00000001 /* clear pending */ 483#define AR_SLP_MIB_PENDING 0x00000002 /* clear counters */ 484 485#define AR_TIMER_MODE_TBTT 0x00000001 486#define AR_TIMER_MODE_DBA 0x00000002 487#define AR_TIMER_MODE_SWBA 0x00000004 488#define AR_TIMER_MODE_HCF 0x00000008 489#define AR_TIMER_MODE_TIM 0x00000010 490#define AR_TIMER_MODE_DTIM 0x00000020 491#define AR_TIMER_MODE_QUIET 0x00000040 492#define AR_TIMER_MODE_NDP 0x00000080 493#define AR_TIMER_MODE_OVERFLOW_INDEX 0x00000700 494#define AR_TIMER_MODE_OVERFLOW_INDEX_S 8 495#define AR_TIMER_MODE_THRESH 0xFFFFF000 496#define AR_TIMER_MODE_THRESH_S 12 497 498/* PCU Misc modes */ 499#define AR_PCU_FORCE_BSSID_MATCH 0x00000001 /* force bssid to match */ 500#define AR_PCU_MIC_NEW_LOC_ENA 0x00000004 /* tx/rx mic keys together */ 501#define AR_PCU_TX_ADD_TSF 0x00000008 /* add tx_tsf + int_tsf */ 502#define AR_PCU_CCK_SIFS_MODE 0x00000010 /* assume 11b sifs */ 503#define AR_PCU_RX_ANT_UPDT 0x00000800 /* KC_RX_ANT_UPDATE */ 504#define AR_PCU_TXOP_TBTT_LIMIT_ENA 0x00001000 /* enforce txop / tbtt */ 505#define AR_PCU_MISS_BCN_IN_SLEEP 0x00004000 /* count bmiss's when sleeping */ 506#define AR_PCU_BUG_12306_FIX_ENA 0x00020000 /* use rx_clear to count sifs */ 507#define AR_PCU_FORCE_QUIET_COLL 0x00040000 /* kill xmit for channel change */ 508#define AR_PCU_BT_ANT_PREVENT_RX 0x00100000 509#define AR_PCU_BT_ANT_PREVENT_RX_S 20 510#define AR_PCU_TBTT_PROTECT 0x00200000 /* no xmit upto tbtt+20 uS */ 511#define AR_PCU_CLEAR_VMF 0x01000000 /* clear vmf mode (fast cc)*/ 512#define AR_PCU_CLEAR_BA_VALID 0x04000000 /* clear ba state */ 513 514#define AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE 0x00000002 515#define AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT 0x00000004 516/* 517 * This bit enables the Multicast search based on both MAC Address and Key ID. 518 * If bit is 0, then Multicast search is based on MAC address only. 519 * For Merlin and above only. 520 */ 521#define AR_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE 0x00000040 522#define AR_PCU_MISC_MODE2_ENABLE_AGGWEP 0x00020000 /* Kiwi or later? */ 523#define AR_PCU_MISC_MODE2_HWWAR1 0x00100000 524#define AR_PCU_MISC_MODE2_HWWAR2 0x02000000 525 526/* For Kiwi */ 527#define AR_MAC_PCU_ASYNC_FIFO_REG3 0x8358 528#define AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL 0x00000400 529#define AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET 0x80000000 530 531/* TSF2. For Kiwi only */ 532#define AR_TSF2_L32 0x8390 533#define AR_TSF2_U32 0x8394 534 535/* MAC Direct Connect Control. For Kiwi only */ 536#define AR_DIRECT_CONNECT 0x83A0 537#define AR_DC_AP_STA_EN 0x00000001 538 539/* GPIO Interrupt */ 540#define AR_INTR_GPIO 0x3FF00000 /* gpio interrupted */ 541#define AR_INTR_GPIO_S 20 542 543#define AR_GPIO_OUT_CTRL 0x000003FF /* 0 = out, 1 = in */ 544#define AR_GPIO_OUT_VAL 0x000FFC00 545#define AR_GPIO_OUT_VAL_S 10 546#define AR_GPIO_INTR_CTRL 0x3FF00000 547#define AR_GPIO_INTR_CTRL_S 20 548 549#define AR_GPIO_IN_VAL 0x0FFFC000 /* pre-9280 */ 550#define AR_GPIO_IN_VAL_S 14 551#define AR928X_GPIO_IN_VAL 0x000FFC00 552#define AR928X_GPIO_IN_VAL_S 10 553#define AR9285_GPIO_IN_VAL 0x00FFF000 554#define AR9285_GPIO_IN_VAL_S 12 555#define AR9287_GPIO_IN_VAL 0x003FF800 556#define AR9287_GPIO_IN_VAL_S 11 557 558#define AR_GPIO_OE_OUT_DRV 0x3 /* 2 bit mask shifted by 2*bitpos */ 559#define AR_GPIO_OE_OUT_DRV_NO 0x0 /* tristate */ 560#define AR_GPIO_OE_OUT_DRV_LOW 0x1 /* drive if low */ 561#define AR_GPIO_OE_OUT_DRV_HI 0x2 /* drive if high */ 562#define AR_GPIO_OE_OUT_DRV_ALL 0x3 /* drive always */ 563 564#define AR_GPIO_INTR_POL_VAL 0x1FFF 565#define AR_GPIO_INTR_POL_VAL_S 0 566 567#define AR_GPIO_JTAG_DISABLE 0x00020000 568 569#define AR_2040_JOINED_RX_CLEAR 0x00000001 /* use ctl + ext rx_clear for cca */ 570 571#define AR_PCU_TXBUF_CTRL_SIZE_MASK 0x7FF 572#define AR_PCU_TXBUF_CTRL_USABLE_SIZE 0x700 573#define AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE 0x380 574 575/* IFS, SIFS, slot, etc for Async FIFO mode (Kiwi) */ 576#define AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR 0x000003AB 577#define AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR 0x16001D56 578#define AR_USEC_ASYNC_FIFO_DUR 0x12e00074 579#define AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR 0x00000420 580#define AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR 0x0000A5EB 581 582/* Used by Kiwi Async FIFO */ 583#define AR_MAC_PCU_LOGIC_ANALYZER 0x8264 584#define AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768 0x20000000 585 586/* Eeprom defines */ 587#define AR_EEPROM_STATUS_DATA_VAL 0x0000ffff 588#define AR_EEPROM_STATUS_DATA_VAL_S 0 589#define AR_EEPROM_STATUS_DATA_BUSY 0x00010000 590#define AR_EEPROM_STATUS_DATA_BUSY_ACCESS 0x00020000 591#define AR_EEPROM_STATUS_DATA_PROT_ACCESS 0x00040000 592#define AR_EEPROM_STATUS_DATA_ABSENT_ACCESS 0x00080000 593 594/* 595 * AR5212 defines the MAC revision mask as 0xF, but both ath9k and 596 * the Atheros HAL define it as 0x7. 597 * 598 * What this means however is AR5416 silicon revisions have 599 * changed. The below macros are for what is contained in the 600 * lower four bits; if the lower three bits are taken into account 601 * the revisions become 1.0 => 0x0, 2.0 => 0x1, 2.2 => 0x2. 602 */ 603 604/* These are the legacy revisions, with a four bit AR_SREV_REVISION mask */ 605#define AR_SREV_REVISION_OWL_10 0x08 606#define AR_SREV_REVISION_OWL_20 0x09 607#define AR_SREV_REVISION_OWL_22 0x0a 608 609#define AR_RAD5133_SREV_MAJOR 0xc0 /* Fowl: 2+5G/3x3 */ 610#define AR_RAD2133_SREV_MAJOR 0xd0 /* Fowl: 2G/3x3 */ 611#define AR_RAD5122_SREV_MAJOR 0xe0 /* Fowl: 5G/2x2 */ 612#define AR_RAD2122_SREV_MAJOR 0xf0 /* Fowl: 2+5G/2x2 */ 613 614/* Test macro for owl 1.0 */ 615#define IS_5416V1(_ah) (AR_SREV_OWL((_ah)) && AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_OWL_10) 616#define IS_5416V2(_ah) (AR_SREV_OWL((_ah)) && AH_PRIVATE((_ah))->ah_macRev >= AR_SREV_REVISION_OWL_20) 617#define IS_5416V2_2(_ah) (AR_SREV_OWL((_ah)) && AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_OWL_22) 618 619/* Misc; compatibility with Atheros HAL */ 620#define AR_SREV_5416_V20_OR_LATER(_ah) (AR_SREV_HOWL((_ah)) || AR_SREV_OWL_20_OR_LATER(_ah)) 621#define AR_SREV_5416_V22_OR_LATER(_ah) (AR_SREV_HOWL((_ah)) || AR_SREV_OWL_22_OR_LATER(_ah)) 622 623/* Expanded Mac Silicon Rev (16 bits starting with Sowl) */ 624#define AR_XSREV_ID 0xFFFFFFFF /* Chip ID */ 625#define AR_XSREV_ID_S 0 626#define AR_XSREV_VERSION 0xFFFC0000 /* Chip version */ 627#define AR_XSREV_VERSION_S 18 628#define AR_XSREV_TYPE 0x0003F000 /* Chip type */ 629#define AR_XSREV_TYPE_S 12 630#define AR_XSREV_TYPE_CHAIN 0x00001000 /* Chain Mode (1:3 chains, 631 * 0:2 chains) */ 632#define AR_XSREV_TYPE_HOST_MODE 0x00002000 /* Host Mode (1:PCI, 0:PCIe) */ 633#define AR_XSREV_REVISION 0x00000F00 634#define AR_XSREV_REVISION_S 8 635 636#define AR_XSREV_VERSION_OWL_PCI 0x0D 637#define AR_XSREV_VERSION_OWL_PCIE 0x0C 638 639 640/* 641 * These are from ath9k/Atheros and assume an AR_SREV version mask 642 * of 0x07, rather than 0x0F which is being used in the FreeBSD HAL. 643 * Thus, don't use these values as they're incorrect here; use 644 * AR_SREV_REVISION_OWL_{10,20,22}. 645 */ 646#if 0 647#define AR_XSREV_REVISION_OWL_10 0 /* Owl 1.0 */ 648#define AR_XSREV_REVISION_OWL_20 1 /* Owl 2.0/2.1 */ 649#define AR_XSREV_REVISION_OWL_22 2 /* Owl 2.2 */ 650#endif 651 652#define AR_XSREV_VERSION_HOWL 0x14 /* Howl (AR9130) */ 653#define AR_XSREV_VERSION_SOWL 0x40 /* Sowl (AR9160) */ 654#define AR_XSREV_REVISION_SOWL_10 0 /* Sowl 1.0 */ 655#define AR_XSREV_REVISION_SOWL_11 1 /* Sowl 1.1 */ 656#define AR_XSREV_VERSION_MERLIN 0x80 /* Merlin Version */ 657#define AR_XSREV_REVISION_MERLIN_10 0 /* Merlin 1.0 */ 658#define AR_XSREV_REVISION_MERLIN_20 1 /* Merlin 2.0 */ 659#define AR_XSREV_REVISION_MERLIN_21 2 /* Merlin 2.1 */ 660#define AR_XSREV_VERSION_KITE 0xC0 /* Kite Version */ 661#define AR_XSREV_REVISION_KITE_10 0 /* Kite 1.0 */ 662#define AR_XSREV_REVISION_KITE_11 1 /* Kite 1.1 */ 663#define AR_XSREV_REVISION_KITE_12 2 /* Kite 1.2 */ 664#define AR_XSREV_VERSION_KIWI 0x180 /* Kiwi (AR9287) */ 665#define AR_XSREV_REVISION_KIWI_10 0 /* Kiwi 1.0 */ 666#define AR_XSREV_REVISION_KIWI_11 1 /* Kiwi 1.1 */ 667#define AR_XSREV_REVISION_KIWI_12 2 /* Kiwi 1.2 */ 668#define AR_XSREV_REVISION_KIWI_13 3 /* Kiwi 1.3 */ 669 670/* Owl (AR5416) */ 671#define AR_SREV_OWL(_ah) \ 672 ((AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_OWL_PCI) || \ 673 (AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_OWL_PCIE)) 674 675#define AR_SREV_OWL_20_OR_LATER(_ah) \ 676 ((AR_SREV_OWL(_ah) && \ 677 AH_PRIVATE((_ah))->ah_macRev >= AR_SREV_REVISION_OWL_20) || \ 678 AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_HOWL) 679 680#define AR_SREV_OWL_22_OR_LATER(_ah) \ 681 ((AR_SREV_OWL(_ah) && \ 682 AH_PRIVATE((_ah))->ah_macRev >= AR_SREV_REVISION_OWL_22) || \ 683 AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_HOWL) 684 685/* Howl (AR9130) */ 686 687#define AR_SREV_HOWL(_ah) \ 688 (AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_HOWL) 689 690#define AR_SREV_9100(_ah) AR_SREV_HOWL(_ah) 691 692/* Sowl (AR9160) */ 693 694#define AR_SREV_SOWL(_ah) \ 695 (AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_SOWL) 696 697#define AR_SREV_SOWL_10_OR_LATER(_ah) \ 698 (AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_SOWL) 699 700#define AR_SREV_SOWL_11(_ah) \ 701 (AR_SREV_SOWL(_ah) && \ 702 AH_PRIVATE((_ah))->ah_macRev == AR_XSREV_REVISION_SOWL_11) 703 704/* Merlin (AR9280) */ 705 706#define AR_SREV_MERLIN(_ah) \ 707 (AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_MERLIN) 708 709#define AR_SREV_MERLIN_10_OR_LATER(_ah) \ 710 (AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_MERLIN) 711 712#define AR_SREV_MERLIN_20(_ah) \ 713 (AR_SREV_MERLIN(_ah) && \ 714 AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_MERLIN_20) 715 716#define AR_SREV_MERLIN_20_OR_LATER(_ah) \ 717 ((AH_PRIVATE((_ah))->ah_macVersion > AR_XSREV_VERSION_MERLIN) || \ 718 (AR_SREV_MERLIN((_ah)) && \ 719 AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_MERLIN_20)) 720 721/* Kite (AR9285) */ 722 723#define AR_SREV_KITE(_ah) \ 724 (AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_KITE) 725 726#define AR_SREV_KITE_10_OR_LATER(_ah) \ 727 (AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_KITE) 728 729#define AR_SREV_KITE_11(_ah) \ 730 (AR_SREV_KITE(ah) && \ 731 AH_PRIVATE((_ah))->ah_macRev == AR_XSREV_REVISION_KITE_11) 732 733#define AR_SREV_KITE_11_OR_LATER(_ah) \ 734 ((AH_PRIVATE((_ah))->ah_macVersion > AR_XSREV_VERSION_KITE) || \ 735 (AR_SREV_KITE((_ah)) && \ 736 AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_KITE_11)) 737 738#define AR_SREV_KITE_12(_ah) \ 739 (AR_SREV_KITE(ah) && \ 740 AH_PRIVATE((_ah))->ah_macRev == AR_XSREV_REVISION_KITE_12) 741 742#define AR_SREV_KITE_12_OR_LATER(_ah) \ 743 ((AH_PRIVATE((_ah))->ah_macVersion > AR_XSREV_VERSION_KITE) || \ 744 (AR_SREV_KITE((_ah)) && \ 745 AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_KITE_12)) 746 747#define AR_SREV_9285E_20(_ah) \ 748 (AR_SREV_KITE_12_OR_LATER(_ah) && \ 749 ((OS_REG_READ(_ah, AR_AN_SYNTH9) & 0x7) == 0x1)) 750 751#define AR_SREV_KIWI(_ah) \ 752 (AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_KIWI) 753 754#define AR_SREV_KIWI_10_OR_LATER(_ah) \ 755 (AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_KIWI) 756 757/* XXX TODO: make these handle macVersion > Kiwi */ 758#define AR_SREV_KIWI_11_OR_LATER(_ah) \ 759 (AR_SREV_KIWI(_ah) && \ 760 AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_KIWI_11) 761 762#define AR_SREV_KIWI_11(_ah) \ 763 (AR_SREV_KIWI(_ah) && \ 764 AH_PRIVATE((_ah))->ah_macRev == AR_XSREV_REVISION_KIWI_11) 765 766#define AR_SREV_KIWI_12(_ah) \ 767 (AR_SREV_KIWI(_ah) && \ 768 AH_PRIVATE((_ah))->ah_macRev == AR_XSREV_REVISION_KIWI_12) 769 770#define AR_SREV_KIWI_12_OR_LATER(_ah) \ 771 (AR_SREV_KIWI(_ah) && \ 772 AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_KIWI_12) 773 774#define AR_SREV_KIWI_13_OR_LATER(_ah) \ 775 (AR_SREV_KIWI(_ah) && \ 776 AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_KIWI_13) 777 778 779/* Not yet implemented chips */ 780#define AR_SREV_9271(_ah) 0 781 782#endif /* _DEV_ATH_AR5416REG_H */ 783