ar5416reg.h revision 221666
1/* 2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar5416/ar5416reg.h 221666 2011-05-08 15:25:22Z adrian $ 18 */ 19#ifndef _DEV_ATH_AR5416REG_H 20#define _DEV_ATH_AR5416REG_H 21 22#include <dev/ath/ath_hal/ar5212/ar5212reg.h> 23 24/* 25 * Register added starting with the AR5416 26 */ 27#define AR_MIRT 0x0020 /* interrupt rate threshold */ 28#define AR_TIMT 0x0028 /* Tx Interrupt mitigation threshold */ 29#define AR_RIMT 0x002C /* Rx Interrupt mitigation threshold */ 30#define AR_GTXTO 0x0064 /* global transmit timeout */ 31#define AR_GTTM 0x0068 /* global transmit timeout mode */ 32#define AR_CST 0x006C /* carrier sense timeout */ 33#define AR_MAC_LED 0x1f04 /* LED control */ 34#define AR_WA 0x4004 /* PCIE work-arounds */ 35#define AR_PCIE_PM_CTRL 0x4014 36#define AR_AHB_MODE 0x4024 /* AHB mode for dma */ 37#define AR_INTR_SYNC_CAUSE_CLR 0x4028 /* clear interrupt */ 38#define AR_INTR_SYNC_CAUSE 0x4028 /* check pending interrupts */ 39#define AR_INTR_SYNC_ENABLE 0x402c /* enable interrupts */ 40#define AR_INTR_ASYNC_MASK 0x4030 /* asynchronous interrupt mask */ 41#define AR_INTR_SYNC_MASK 0x4034 /* synchronous interrupt mask */ 42#define AR_INTR_ASYNC_CAUSE 0x4038 /* check pending interrupts */ 43#define AR_INTR_ASYNC_ENABLE 0x403c /* enable interrupts */ 44#define AR5416_PCIE_SERDES 0x4040 45#define AR5416_PCIE_SERDES2 0x4044 46#define AR_GPIO_IN_OUT 0x4048 /* GPIO input/output register */ 47#define AR_GPIO_OE_OUT 0x404c /* GPIO output enable register */ 48#define AR_GPIO_INTR_POL 0x4050 /* GPIO interrupt polarity */ 49#define AR_GPIO_INPUT_EN_VAL 0x4054 /* GPIO input enable and value */ 50#define AR_GPIO_INPUT_MUX1 0x4058 51#define AR_GPIO_INPUT_MUX2 0x405c 52#define AR_GPIO_OUTPUT_MUX1 0x4060 53#define AR_GPIO_OUTPUT_MUX2 0x4064 54#define AR_GPIO_OUTPUT_MUX3 0x4068 55#define AR_EEPROM_STATUS_DATA 0x407c 56#define AR_OBS 0x4080 57 58#ifdef AH_SUPPORT_AR9130 59#define AR_RTC_BASE 0x20000 60#else 61#define AR_RTC_BASE 0x7000 62#endif /* AH_SUPPORT_AR9130 */ 63 64#define AR_RTC_RC AR_RTC_BASE + 0x00 /* reset control */ 65#define AR_RTC_PLL_CONTROL AR_RTC_BASE + 0x14 66#define AR_RTC_RESET AR_RTC_BASE + 0x40 /* RTC reset register */ 67#define AR_RTC_STATUS AR_RTC_BASE + 0x44 /* system sleep status */ 68#define AR_RTC_SLEEP_CLK AR_RTC_BASE + 0x48 69#define AR_RTC_FORCE_WAKE AR_RTC_BASE + 0x4c /* control MAC force wake */ 70#define AR_RTC_INTR_CAUSE AR_RTC_BASE + 0x50 /* RTC interrupt cause/clear */ 71#define AR_RTC_INTR_ENABLE AR_RTC_BASE + 0x54 /* RTC interrupt enable */ 72#define AR_RTC_INTR_MASK AR_RTC_BASE + 0x58 /* RTC interrupt mask */ 73 74#ifdef AH_SUPPORT_AR9130 75/* RTC_DERIVED_* - only for AR9130 */ 76#define AR_RTC_DERIVED_CLK (AR_RTC_BASE + 0x0038) 77#define AR_RTC_DERIVED_CLK_PERIOD 0x0000fffe 78#define AR_RTC_DERIVED_CLK_PERIOD_S 1 79#endif /* AH_SUPPORT_AR9130 */ 80 81/* AR9280: rf long shift registers */ 82#define AR_AN_RF2G1_CH0 0x7810 83#define AR_AN_RF5G1_CH0 0x7818 84#define AR_AN_RF2G1_CH1 0x7834 85#define AR_AN_RF5G1_CH1 0x783C 86#define AR_AN_TOP2 0x7894 87#define AR_AN_SYNTH9 0x7868 88#define AR9285_AN_RF2G1 0x7820 89#define AR9285_AN_RF2G2 0x7824 90#define AR9285_AN_RF2G3 0x7828 91#define AR9285_AN_RF2G4 0x782C 92#define AR9285_AN_RF2G6 0x7834 93#define AR9285_AN_RF2G7 0x7838 94#define AR9285_AN_RF2G8 0x783C 95#define AR9285_AN_RF2G9 0x7840 96#define AR9285_AN_RXTXBB1 0x7854 97#define AR9285_AN_TOP2 0x7868 98#define AR9285_AN_TOP3 0x786c 99#define AR9285_AN_TOP4 0x7870 100#define AR9285_AN_TOP4_DEFAULT 0x10142c00 101 102#define AR_RESET_TSF 0x8020 103#define AR_RXFIFO_CFG 0x8114 104#define AR_PHY_ERR_1 0x812c 105#define AR_PHY_ERR_MASK_1 0x8130 /* mask for AR_PHY_ERR_1 */ 106#define AR_PHY_ERR_2 0x8134 107#define AR_PHY_ERR_MASK_2 0x8138 /* mask for AR_PHY_ERR_2 */ 108#define AR_TSFOOR_THRESHOLD 0x813c 109#define AR_PHY_ERR_3 0x8168 110#define AR_PHY_ERR_MASK_3 0x816c /* mask for AR_PHY_ERR_3 */ 111#define AR_TXOP_X 0x81ec /* txop for legacy non-qos */ 112#define AR_TXOP_0_3 0x81f0 /* txop for various tid's */ 113#define AR_TXOP_4_7 0x81f4 114#define AR_TXOP_8_11 0x81f8 115#define AR_TXOP_12_15 0x81fc 116/* generic timers based on tsf - all uS */ 117#define AR_NEXT_TBTT 0x8200 118#define AR_NEXT_DBA 0x8204 119#define AR_NEXT_SWBA 0x8208 120#define AR_NEXT_CFP 0x8208 121#define AR_NEXT_HCF 0x820C 122#define AR_NEXT_TIM 0x8210 123#define AR_NEXT_DTIM 0x8214 124#define AR_NEXT_QUIET 0x8218 125#define AR_NEXT_NDP 0x821C 126#define AR5416_BEACON_PERIOD 0x8220 127#define AR_DBA_PERIOD 0x8224 128#define AR_SWBA_PERIOD 0x8228 129#define AR_HCF_PERIOD 0x822C 130#define AR_TIM_PERIOD 0x8230 131#define AR_DTIM_PERIOD 0x8234 132#define AR_QUIET_PERIOD 0x8238 133#define AR_NDP_PERIOD 0x823C 134#define AR_TIMER_MODE 0x8240 135#define AR_SLP32_MODE 0x8244 136#define AR_SLP32_WAKE 0x8248 137#define AR_SLP32_INC 0x824c 138#define AR_SLP_CNT 0x8250 /* 32kHz cycles with mac asleep */ 139#define AR_SLP_CYCLE_CNT 0x8254 /* absolute number of 32kHz cycles */ 140#define AR_SLP_MIB_CTRL 0x8258 141#define AR_2040_MODE 0x8318 142#define AR_EXTRCCNT 0x8328 /* extension channel rx clear count */ 143#define AR_SELFGEN_MASK 0x832c /* rx and cal chain masks */ 144#define AR_PCU_TXBUF_CTRL 0x8340 145#define AR_PCU_MISC_MODE2 0x8344 146 147/* DMA & PCI Registers in PCI space (usable during sleep)*/ 148#define AR_RC_AHB 0x00000001 /* AHB reset */ 149#define AR_RC_APB 0x00000002 /* APB reset */ 150#define AR_RC_HOSTIF 0x00000100 /* host interface reset */ 151 152#define AR_MIRT_VAL 0x0000ffff /* in uS */ 153#define AR_MIRT_VAL_S 16 154 155#define AR_TIMT_LAST 0x0000ffff /* Last packet threshold */ 156#define AR_TIMT_LAST_S 0 157#define AR_TIMT_FIRST 0xffff0000 /* First packet threshold */ 158#define AR_TIMT_FIRST_S 16 159 160#define AR_RIMT_LAST 0x0000ffff /* Last packet threshold */ 161#define AR_RIMT_LAST_S 0 162#define AR_RIMT_FIRST 0xffff0000 /* First packet threshold */ 163#define AR_RIMT_FIRST_S 16 164 165#define AR_GTXTO_TIMEOUT_COUNTER 0x0000FFFF // Mask for timeout counter (in TUs) 166#define AR_GTXTO_TIMEOUT_LIMIT 0xFFFF0000 // Mask for timeout limit (in TUs) 167#define AR_GTXTO_TIMEOUT_LIMIT_S 16 // Shift for timeout limit 168 169#define AR_GTTM_USEC 0x00000001 // usec strobe 170#define AR_GTTM_IGNORE_IDLE 0x00000002 // ignore channel idle 171#define AR_GTTM_RESET_IDLE 0x00000004 // reset counter on channel idle low 172#define AR_GTTM_CST_USEC 0x00000008 // CST usec strobe 173 174#define AR_CST_TIMEOUT_COUNTER 0x0000FFFF // Mask for timeout counter (in TUs) 175#define AR_CST_TIMEOUT_LIMIT 0xFFFF0000 // Mask for timeout limit (in TUs) 176#define AR_CST_TIMEOUT_LIMIT_S 16 // Shift for timeout limit 177 178/* MAC tx DMA size config */ 179#define AR_TXCFG_DMASZ_MASK 0x00000003 180#define AR_TXCFG_DMASZ_4B 0 181#define AR_TXCFG_DMASZ_8B 1 182#define AR_TXCFG_DMASZ_16B 2 183#define AR_TXCFG_DMASZ_32B 3 184#define AR_TXCFG_DMASZ_64B 4 185#define AR_TXCFG_DMASZ_128B 5 186#define AR_TXCFG_DMASZ_256B 6 187#define AR_TXCFG_DMASZ_512B 7 188#define AR_TXCFG_ATIM_TXPOLICY 0x00000800 189 190/* MAC rx DMA size config */ 191#define AR_RXCFG_DMASZ_MASK 0x00000007 192#define AR_RXCFG_DMASZ_4B 0 193#define AR_RXCFG_DMASZ_8B 1 194#define AR_RXCFG_DMASZ_16B 2 195#define AR_RXCFG_DMASZ_32B 3 196#define AR_RXCFG_DMASZ_64B 4 197#define AR_RXCFG_DMASZ_128B 5 198#define AR_RXCFG_DMASZ_256B 6 199#define AR_RXCFG_DMASZ_512B 7 200 201/* MAC Led registers */ 202#define AR_CFG_SCLK_RATE_IND 0x00000003 /* sleep clock indication */ 203#define AR_CFG_SCLK_RATE_IND_S 0 204#define AR_CFG_SCLK_32MHZ 0x00000000 /* Sleep clock rate */ 205#define AR_CFG_SCLK_4MHZ 0x00000001 /* Sleep clock rate */ 206#define AR_CFG_SCLK_1MHZ 0x00000002 /* Sleep clock rate */ 207#define AR_CFG_SCLK_32KHZ 0x00000003 /* Sleep clock rate */ 208#define AR_MAC_LED_BLINK_SLOW 0x00000008 /* LED slowest blink rate mode */ 209#define AR_MAC_LED_BLINK_THRESH_SEL 0x00000070 /* LED blink threshold select */ 210#define AR_MAC_LED_MODE 0x00000380 /* LED mode select */ 211#define AR_MAC_LED_MODE_S 7 212#define AR_MAC_LED_MODE_PROP 0 /* Blink prop to filtered tx/rx */ 213#define AR_MAC_LED_MODE_RPROP 1 /* Blink prop to unfiltered tx/rx */ 214#define AR_MAC_LED_MODE_SPLIT 2 /* Blink power for tx/net for rx */ 215#define AR_MAC_LED_MODE_RAND 3 /* Blink randomly */ 216#define AR_MAC_LED_MODE_POWON 5 /* Power LED on (s/w control) */ 217#define AR_MAC_LED_MODE_NETON 6 /* Network LED on (s/w control) */ 218#define AR_MAC_LED_ASSOC 0x00000c00 219#define AR_MAC_LED_ASSOC_NONE 0x00000000 /* STA is not associated or trying */ 220#define AR_MAC_LED_ASSOC_ACTIVE 0x00000400 /* STA is associated */ 221#define AR_MAC_LED_ASSOC_PEND 0x00000800 /* STA is trying to associate */ 222#define AR_MAC_LED_ASSOC_S 10 223 224#define AR_WA_UNTIE_RESET_EN 0x00008000 /* ena PCI reset to POR */ 225#define AR_WA_RESET_EN 0x00040000 /* ena AR_WA_UNTIE_RESET_EN */ 226#define AR_WA_ANALOG_SHIFT 0x00100000 227#define AR_WA_POR_SHORT 0x00200000 /* PCIE phy reset control */ 228 229#define AR_WA_DEFAULT 0x0000073f 230#define AR9280_WA_DEFAULT 0x0040073f 231#define AR9285_WA_DEFAULT 0x004a05cb 232 233#define AR_PCIE_PM_CTRL_ENA 0x00080000 234 235#define AR_AHB_EXACT_WR_EN 0x00000000 /* write exact bytes */ 236#define AR_AHB_BUF_WR_EN 0x00000001 /* buffer write upto cacheline*/ 237#define AR_AHB_EXACT_RD_EN 0x00000000 /* read exact bytes */ 238#define AR_AHB_CACHELINE_RD_EN 0x00000002 /* read upto end of cacheline */ 239#define AR_AHB_PREFETCH_RD_EN 0x00000004 /* prefetch upto page boundary*/ 240#define AR_AHB_PAGE_SIZE_1K 0x00000000 /* set page-size as 1k */ 241#define AR_AHB_PAGE_SIZE_2K 0x00000008 /* set page-size as 2k */ 242#define AR_AHB_PAGE_SIZE_4K 0x00000010 /* set page-size as 4k */ 243 244/* MAC PCU Registers */ 245#define AR_STA_ID1_PRESERVE_SEQNUM 0x20000000 /* Don't replace seq num */ 246 247/* Extended PCU DIAG_SW control fields */ 248#define AR_DIAG_DUAL_CHAIN_INFO 0x01000000 /* dual chain channel info */ 249#define AR_DIAG_RX_ABORT 0x02000000 /* abort rx */ 250#define AR_DIAG_SATURATE_CCNT 0x04000000 /* sat. cycle cnts (no shift) */ 251#define AR_DIAG_OBS_PT_SEL2 0x08000000 /* observation point sel */ 252#define AR_DIAG_RXCLEAR_CTL_LOW 0x10000000 /* force rx_clear(ctl) low/busy */ 253#define AR_DIAG_RXCLEAR_EXT_LOW 0x20000000 /* force rx_clear(ext) low/busy */ 254 255#define AR_TXOP_X_VAL 0x000000FF 256 257#define AR_RESET_TSF_ONCE 0x01000000 /* reset tsf once; self-clears*/ 258 259/* Interrupts */ 260#define AR_ISR_TXMINTR 0x00080000 /* Maximum interrupt tx rate */ 261#define AR_ISR_RXMINTR 0x01000000 /* Maximum interrupt rx rate */ 262#define AR_ISR_TXINTM 0x40000000 /* Tx int after mitigation */ 263#define AR_ISR_RXINTM 0x80000000 /* Rx int after mitigation */ 264 265#define AR_ISR_S2_CST 0x00400000 /* Carrier sense timeout */ 266#define AR_ISR_S2_GTT 0x00800000 /* Global transmit timeout */ 267#define AR_ISR_S2_TSFOOR 0x40000000 /* RX TSF out of range */ 268 269#define AR_ISR_S5 0x0098 270#define AR_ISR_S5_S 0x00d8 271#define AR_ISR_S5_TIM_TIMER 0x00000010 272 273#define AR_INTR_SPURIOUS 0xffffffff 274#define AR_INTR_RTC_IRQ 0x00000001 /* rtc in shutdown state */ 275#define AR_INTR_MAC_IRQ 0x00000002 /* pending mac interrupt */ 276#define AR_INTR_EEP_PROT_ACCESS 0x00000004 /* eeprom protected access */ 277#define AR_INTR_MAC_AWAKE 0x00020000 /* mac is awake */ 278#define AR_INTR_MAC_ASLEEP 0x00040000 /* mac is asleep */ 279 280/* Interrupt Mask Registers */ 281#define AR_IMR_TXMINTR 0x00080000 /* Maximum interrupt tx rate */ 282#define AR_IMR_RXMINTR 0x01000000 /* Maximum interrupt rx rate */ 283#define AR_IMR_TXINTM 0x40000000 /* Tx int after mitigation */ 284#define AR_IMR_RXINTM 0x80000000 /* Rx int after mitigation */ 285 286#define AR_IMR_S2_CST 0x00400000 /* Carrier sense timeout */ 287#define AR_IMR_S2_GTT 0x00800000 /* Global transmit timeout */ 288 289/* synchronous interrupt signals */ 290#define AR_INTR_SYNC_RTC_IRQ 0x00000001 291#define AR_INTR_SYNC_MAC_IRQ 0x00000002 292#define AR_INTR_SYNC_EEPROM_ILLEGAL_ACCESS 0x00000004 293#define AR_INTR_SYNC_APB_TIMEOUT 0x00000008 294#define AR_INTR_SYNC_PCI_MODE_CONFLICT 0x00000010 295#define AR_INTR_SYNC_HOST1_FATAL 0x00000020 296#define AR_INTR_SYNC_HOST1_PERR 0x00000040 297#define AR_INTR_SYNC_TRCV_FIFO_PERR 0x00000080 298#define AR_INTR_SYNC_RADM_CPL_EP 0x00000100 299#define AR_INTR_SYNC_RADM_CPL_DLLP_ABORT 0x00000200 300#define AR_INTR_SYNC_RADM_CPL_TLP_ABORT 0x00000400 301#define AR_INTR_SYNC_RADM_CPL_ECRC_ERR 0x00000800 302#define AR_INTR_SYNC_RADM_CPL_TIMEOUT 0x00001000 303#define AR_INTR_SYNC_LOCAL_TIMEOUT 0x00002000 304#define AR_INTR_SYNC_PM_ACCESS 0x00004000 305#define AR_INTR_SYNC_MAC_AWAKE 0x00008000 306#define AR_INTR_SYNC_MAC_ASLEEP 0x00010000 307#define AR_INTR_SYNC_MAC_SLEEP_ACCESS 0x00020000 308#define AR_INTR_SYNC_ALL 0x0003FFFF 309 310/* default synchronous interrupt signals enabled */ 311#define AR_INTR_SYNC_DEFAULT \ 312 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR | \ 313 AR_INTR_SYNC_RADM_CPL_EP | AR_INTR_SYNC_RADM_CPL_DLLP_ABORT | \ 314 AR_INTR_SYNC_RADM_CPL_TLP_ABORT | AR_INTR_SYNC_RADM_CPL_ECRC_ERR | \ 315 AR_INTR_SYNC_RADM_CPL_TIMEOUT | AR_INTR_SYNC_LOCAL_TIMEOUT | \ 316 AR_INTR_SYNC_MAC_SLEEP_ACCESS) 317 318#define AR_INTR_SYNC_MASK_GPIO 0xFFFC0000 319#define AR_INTR_SYNC_MASK_GPIO_S 18 320 321#define AR_INTR_SYNC_ENABLE_GPIO 0xFFFC0000 322#define AR_INTR_SYNC_ENABLE_GPIO_S 18 323 324#define AR_INTR_ASYNC_MASK_GPIO 0xFFFC0000 /* async int mask */ 325#define AR_INTR_ASYNC_MASK_GPIO_S 18 326 327#define AR_INTR_ASYNC_CAUSE_GPIO 0xFFFC0000 /* GPIO interrupts */ 328#define AR_INTR_ASYNC_USED (AR_INTR_MAC_IRQ | AR_INTR_ASYNC_CAUSE_GPIO) 329 330#define AR_INTR_ASYNC_ENABLE_GPIO 0xFFFC0000 /* enable interrupts */ 331#define AR_INTR_ASYNC_ENABLE_GPIO_S 18 332 333/* RTC registers */ 334#define AR_RTC_RC_M 0x00000003 335#define AR_RTC_RC_MAC_WARM 0x00000001 336#define AR_RTC_RC_MAC_COLD 0x00000002 337#ifdef AH_SUPPORT_AR9130 338#define AR_RTC_RC_COLD_RESET 0x00000004 339#define AR_RTC_RC_WARM_RESET 0x00000008 340#endif /* AH_SUPPORT_AR9130 */ 341#define AR_RTC_PLL_DIV 0x0000001f 342#define AR_RTC_PLL_DIV_S 0 343#define AR_RTC_PLL_DIV2 0x00000020 344#define AR_RTC_PLL_REFDIV_5 0x000000c0 345 346#define AR_RTC_SOWL_PLL_DIV 0x000003ff 347#define AR_RTC_SOWL_PLL_DIV_S 0 348#define AR_RTC_SOWL_PLL_REFDIV 0x00003C00 349#define AR_RTC_SOWL_PLL_REFDIV_S 10 350#define AR_RTC_SOWL_PLL_CLKSEL 0x0000C000 351#define AR_RTC_SOWL_PLL_CLKSEL_S 14 352 353#define AR_RTC_RESET_EN 0x00000001 /* Reset RTC bit */ 354 355#define AR_RTC_PM_STATUS_M 0x0000000f /* Pwr Mgmt Status */ 356#ifdef AH_SUPPORT_AR9130 357#define AR_RTC_STATUS_M 0x0000000f /* RTC Status */ 358#else 359#define AR_RTC_STATUS_M 0x0000003f /* RTC Status */ 360#endif /* AH_SUPPORT_AR9130 */ 361#define AR_RTC_STATUS_SHUTDOWN 0x00000001 362#define AR_RTC_STATUS_ON 0x00000002 363#define AR_RTC_STATUS_SLEEP 0x00000004 364#define AR_RTC_STATUS_WAKEUP 0x00000008 365#define AR_RTC_STATUS_COLDRESET 0x00000010 /* Not currently used */ 366#define AR_RTC_STATUS_PLLCHANGE 0x00000020 /* Not currently used */ 367 368#define AR_RTC_SLEEP_DERIVED_CLK 0x2 369 370#define AR_RTC_FORCE_WAKE_EN 0x00000001 /* enable force wake */ 371#define AR_RTC_FORCE_WAKE_ON_INT 0x00000002 /* auto-wake on MAC interrupt */ 372 373#define AR_RTC_PLL_CLKSEL 0x00000300 374#define AR_RTC_PLL_CLKSEL_S 8 375 376/* AR9280: rf long shift registers */ 377#define AR_AN_RF2G1_CH0_OB 0x03800000 378#define AR_AN_RF2G1_CH0_OB_S 23 379#define AR_AN_RF2G1_CH0_DB 0x1C000000 380#define AR_AN_RF2G1_CH0_DB_S 26 381 382#define AR_AN_RF5G1_CH0_OB5 0x00070000 383#define AR_AN_RF5G1_CH0_OB5_S 16 384#define AR_AN_RF5G1_CH0_DB5 0x00380000 385#define AR_AN_RF5G1_CH0_DB5_S 19 386 387#define AR_AN_RF2G1_CH1_OB 0x03800000 388#define AR_AN_RF2G1_CH1_OB_S 23 389#define AR_AN_RF2G1_CH1_DB 0x1C000000 390#define AR_AN_RF2G1_CH1_DB_S 26 391 392#define AR_AN_RF5G1_CH1_OB5 0x00070000 393#define AR_AN_RF5G1_CH1_OB5_S 16 394#define AR_AN_RF5G1_CH1_DB5 0x00380000 395#define AR_AN_RF5G1_CH1_DB5_S 19 396 397#define AR_AN_TOP1 0x7890 398#define AR_AN_TOP1_DACIPMODE 0x00040000 399#define AR_AN_TOP1_DACIPMODE_S 18 400 401#define AR_AN_TOP2_XPABIAS_LVL 0xC0000000 402#define AR_AN_TOP2_XPABIAS_LVL_S 30 403#define AR_AN_TOP2_LOCALBIAS 0x00200000 404#define AR_AN_TOP2_LOCALBIAS_S 21 405#define AR_AN_TOP2_PWDCLKIND 0x00400000 406#define AR_AN_TOP2_PWDCLKIND_S 22 407 408#define AR_AN_SYNTH9_REFDIVA 0xf8000000 409#define AR_AN_SYNTH9_REFDIVA_S 27 410 411/* AR9285 Analog registers */ 412#define AR9285_AN_RF2G1_ENPACAL 0x00000800 413#define AR9285_AN_RF2G1_ENPACAL_S 11 414#define AR9285_AN_RF2G1_PDPADRV1 0x02000000 415#define AR9285_AN_RF2G1_PDPADRV1_S 25 416#define AR9285_AN_RF2G1_PDPADRV2 0x01000000 417#define AR9285_AN_RF2G1_PDPADRV2_S 24 418#define AR9285_AN_RF2G1_PDPAOUT 0x00800000 419#define AR9285_AN_RF2G1_PDPAOUT_S 23 420 421#define AR9285_AN_RF2G2_OFFCAL 0x00001000 422#define AR9285_AN_RF2G2_OFFCAL_S 12 423 424#define AR9285_AN_RF2G3_PDVCCOMP 0x02000000 425#define AR9285_AN_RF2G3_PDVCCOMP_S 25 426#define AR9285_AN_RF2G3_OB_0 0x00E00000 427#define AR9285_AN_RF2G3_OB_0_S 21 428#define AR9285_AN_RF2G3_OB_1 0x001C0000 429#define AR9285_AN_RF2G3_OB_1_S 18 430#define AR9285_AN_RF2G3_OB_2 0x00038000 431#define AR9285_AN_RF2G3_OB_2_S 15 432#define AR9285_AN_RF2G3_OB_3 0x00007000 433#define AR9285_AN_RF2G3_OB_3_S 12 434#define AR9285_AN_RF2G3_OB_4 0x00000E00 435#define AR9285_AN_RF2G3_OB_4_S 9 436 437#define AR9285_AN_RF2G3_DB1_0 0x000001C0 438#define AR9285_AN_RF2G3_DB1_0_S 6 439#define AR9285_AN_RF2G3_DB1_1 0x00000038 440#define AR9285_AN_RF2G3_DB1_1_S 3 441#define AR9285_AN_RF2G3_DB1_2 0x00000007 442#define AR9285_AN_RF2G3_DB1_2_S 0 443 444#define AR9285_AN_RF2G4_DB1_3 0xE0000000 445#define AR9285_AN_RF2G4_DB1_3_S 29 446#define AR9285_AN_RF2G4_DB1_4 0x1C000000 447#define AR9285_AN_RF2G4_DB1_4_S 26 448 449#define AR9285_AN_RF2G4_DB2_0 0x03800000 450#define AR9285_AN_RF2G4_DB2_0_S 23 451#define AR9285_AN_RF2G4_DB2_1 0x00700000 452#define AR9285_AN_RF2G4_DB2_1_S 20 453#define AR9285_AN_RF2G4_DB2_2 0x000E0000 454#define AR9285_AN_RF2G4_DB2_2_S 17 455#define AR9285_AN_RF2G4_DB2_3 0x0001C000 456#define AR9285_AN_RF2G4_DB2_3_S 14 457#define AR9285_AN_RF2G4_DB2_4 0x00003800 458#define AR9285_AN_RF2G4_DB2_4_S 11 459 460#define AR9285_AN_RF2G6_CCOMP 0x00007800 461#define AR9285_AN_RF2G6_CCOMP_S 11 462#define AR9285_AN_RF2G6_OFFS 0x03f00000 463#define AR9285_AN_RF2G6_OFFS_S 20 464 465#define AR9271_AN_RF2G6_OFFS 0x07f00000 466#define AR9271_AN_RF2G6_OFFS_S 20 467 468#define AR9285_AN_RF2G7_PWDDB 0x00000002 469#define AR9285_AN_RF2G7_PWDDB_S 1 470#define AR9285_AN_RF2G7_PADRVGN2TAB0 0xE0000000 471#define AR9285_AN_RF2G7_PADRVGN2TAB0_S 29 472 473#define AR9285_AN_RF2G8_PADRVGN2TAB0 0x0001C000 474#define AR9285_AN_RF2G8_PADRVGN2TAB0_S 14 475 476#define AR9285_AN_RXTXBB1_PDRXTXBB1 0x00000020 477#define AR9285_AN_RXTXBB1_PDRXTXBB1_S 5 478#define AR9285_AN_RXTXBB1_PDV2I 0x00000080 479#define AR9285_AN_RXTXBB1_PDV2I_S 7 480#define AR9285_AN_RXTXBB1_PDDACIF 0x00000100 481#define AR9285_AN_RXTXBB1_PDDACIF_S 8 482#define AR9285_AN_RXTXBB1_SPARE9 0x00000001 483#define AR9285_AN_RXTXBB1_SPARE9_S 0 484 485#define AR9285_AN_TOP3_XPABIAS_LVL 0x0000000C 486#define AR9285_AN_TOP3_XPABIAS_LVL_S 2 487#define AR9285_AN_TOP3_PWDDAC 0x00800000 488#define AR9285_AN_TOP3_PWDDAC_S 23 489 490/* Sleep control */ 491#define AR5416_SLEEP1_CAB_TIMEOUT 0xFFE00000 /* Cab timeout (TU) */ 492#define AR5416_SLEEP1_CAB_TIMEOUT_S 22 493 494#define AR5416_SLEEP2_BEACON_TIMEOUT 0xFFE00000 /* Beacon timeout (TU)*/ 495#define AR5416_SLEEP2_BEACON_TIMEOUT_S 22 496 497/* Sleep Registers */ 498#define AR_SLP32_HALFCLK_LATENCY 0x000FFFFF /* rising <-> falling edge */ 499#define AR_SLP32_ENA 0x00100000 500#define AR_SLP32_TSF_WRITE_STATUS 0x00200000 /* tsf update in progress */ 501 502#define AR_SLP32_WAKE_XTL_TIME 0x0000FFFF /* time to wake crystal */ 503 504#define AR_SLP32_TST_INC 0x000FFFFF 505 506#define AR_SLP_MIB_CLEAR 0x00000001 /* clear pending */ 507#define AR_SLP_MIB_PENDING 0x00000002 /* clear counters */ 508 509#define AR_TIMER_MODE_TBTT 0x00000001 510#define AR_TIMER_MODE_DBA 0x00000002 511#define AR_TIMER_MODE_SWBA 0x00000004 512#define AR_TIMER_MODE_HCF 0x00000008 513#define AR_TIMER_MODE_TIM 0x00000010 514#define AR_TIMER_MODE_DTIM 0x00000020 515#define AR_TIMER_MODE_QUIET 0x00000040 516#define AR_TIMER_MODE_NDP 0x00000080 517#define AR_TIMER_MODE_OVERFLOW_INDEX 0x00000700 518#define AR_TIMER_MODE_OVERFLOW_INDEX_S 8 519#define AR_TIMER_MODE_THRESH 0xFFFFF000 520#define AR_TIMER_MODE_THRESH_S 12 521 522/* PCU Misc modes */ 523#define AR_PCU_FORCE_BSSID_MATCH 0x00000001 /* force bssid to match */ 524#define AR_PCU_MIC_NEW_LOC_ENA 0x00000004 /* tx/rx mic keys together */ 525#define AR_PCU_TX_ADD_TSF 0x00000008 /* add tx_tsf + int_tsf */ 526#define AR_PCU_CCK_SIFS_MODE 0x00000010 /* assume 11b sifs */ 527#define AR_PCU_RX_ANT_UPDT 0x00000800 /* KC_RX_ANT_UPDATE */ 528#define AR_PCU_TXOP_TBTT_LIMIT_ENA 0x00001000 /* enforce txop / tbtt */ 529#define AR_PCU_MISS_BCN_IN_SLEEP 0x00004000 /* count bmiss's when sleeping */ 530#define AR_PCU_BUG_12306_FIX_ENA 0x00020000 /* use rx_clear to count sifs */ 531#define AR_PCU_FORCE_QUIET_COLL 0x00040000 /* kill xmit for channel change */ 532#define AR_PCU_TBTT_PROTECT 0x00200000 /* no xmit upto tbtt+20 uS */ 533#define AR_PCU_CLEAR_VMF 0x01000000 /* clear vmf mode (fast cc)*/ 534#define AR_PCU_CLEAR_BA_VALID 0x04000000 /* clear ba state */ 535 536#define AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE 0x00000002 537#define AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT 0x00000004 538/* 539 * This bit enables the Multicast search based on both MAC Address and Key ID. 540 * If bit is 0, then Multicast search is based on MAC address only. 541 * For Merlin and above only. 542 */ 543#define AR_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE 0x00000040 544#define AR_PCU_MISC_MODE2_HWWAR1 0x00100000 545#define AR_PCU_MISC_MODE2_HWWAR2 0x02000000 546 547/* GPIO Interrupt */ 548#define AR_INTR_GPIO 0x3FF00000 /* gpio interrupted */ 549#define AR_INTR_GPIO_S 20 550 551#define AR_GPIO_OUT_CTRL 0x000003FF /* 0 = out, 1 = in */ 552#define AR_GPIO_OUT_VAL 0x000FFC00 553#define AR_GPIO_OUT_VAL_S 10 554#define AR_GPIO_INTR_CTRL 0x3FF00000 555#define AR_GPIO_INTR_CTRL_S 20 556 557#define AR_GPIO_IN_VAL 0x0FFFC000 /* pre-9280 */ 558#define AR_GPIO_IN_VAL_S 14 559#define AR928X_GPIO_IN_VAL 0x000FFC00 560#define AR928X_GPIO_IN_VAL_S 10 561#define AR9285_GPIO_IN_VAL 0x00FFF000 562#define AR9285_GPIO_IN_VAL_S 12 563 564#define AR_GPIO_OE_OUT_DRV 0x3 /* 2 bit mask shifted by 2*bitpos */ 565#define AR_GPIO_OE_OUT_DRV_NO 0x0 /* tristate */ 566#define AR_GPIO_OE_OUT_DRV_LOW 0x1 /* drive if low */ 567#define AR_GPIO_OE_OUT_DRV_HI 0x2 /* drive if high */ 568#define AR_GPIO_OE_OUT_DRV_ALL 0x3 /* drive always */ 569 570#define AR_GPIO_INTR_POL_VAL 0x1FFF 571#define AR_GPIO_INTR_POL_VAL_S 0 572 573#define AR_GPIO_JTAG_DISABLE 0x00020000 574 575#define AR_2040_JOINED_RX_CLEAR 0x00000001 /* use ctl + ext rx_clear for cca */ 576 577#define AR_PCU_TXBUF_CTRL_SIZE_MASK 0x7FF 578#define AR_PCU_TXBUF_CTRL_USABLE_SIZE 0x700 579#define AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE 0x380 580 581/* Eeprom defines */ 582#define AR_EEPROM_STATUS_DATA_VAL 0x0000ffff 583#define AR_EEPROM_STATUS_DATA_VAL_S 0 584#define AR_EEPROM_STATUS_DATA_BUSY 0x00010000 585#define AR_EEPROM_STATUS_DATA_BUSY_ACCESS 0x00020000 586#define AR_EEPROM_STATUS_DATA_PROT_ACCESS 0x00040000 587#define AR_EEPROM_STATUS_DATA_ABSENT_ACCESS 0x00080000 588 589/* 590 * AR5212 defines the MAC revision mask as 0xF, but both ath9k and 591 * the Atheros HAL define it as 0x7. 592 * 593 * What this means however is AR5416 silicon revisions have 594 * changed. The below macros are for what is contained in the 595 * lower four bits; if the lower three bits are taken into account 596 * the revisions become 1.0 => 0x0, 2.0 => 0x1, 2.2 => 0x2. 597 */ 598 599/* These are the legacy revisions, with a four bit AR_SREV_REVISION mask */ 600#define AR_SREV_REVISION_OWL_10 0x08 601#define AR_SREV_REVISION_OWL_20 0x09 602#define AR_SREV_REVISION_OWL_22 0x0a 603 604#define AR_RAD5133_SREV_MAJOR 0xc0 /* Fowl: 2+5G/3x3 */ 605#define AR_RAD2133_SREV_MAJOR 0xd0 /* Fowl: 2G/3x3 */ 606#define AR_RAD5122_SREV_MAJOR 0xe0 /* Fowl: 5G/2x2 */ 607#define AR_RAD2122_SREV_MAJOR 0xf0 /* Fowl: 2+5G/2x2 */ 608 609/* Test macro for owl 1.0 */ 610#define IS_5416V1(_ah) (AR_SREV_OWL((_ah)) && AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_OWL_10) 611#define IS_5416V2(_ah) (AR_SREV_OWL((_ah)) && AH_PRIVATE((_ah))->ah_macRev >= AR_SREV_REVISION_OWL_20) 612#define IS_5416V2_2(_ah) (AR_SREV_OWL((_ah)) && AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_OWL_22) 613 614/* Misc; compatibility with Atheros HAL */ 615#define AR_SREV_5416_V20_OR_LATER(_ah) (AR_SREV_HOWL((_ah)) || AR_SREV_OWL_20_OR_LATER(_ah)) 616#define AR_SREV_5416_V22_OR_LATER(_ah) (AR_SREV_HOWL((_ah)) || AR_SREV_OWL_22_OR_LATER(_ah)) 617 618/* Expanded Mac Silicon Rev (16 bits starting with Sowl) */ 619#define AR_XSREV_ID 0xFFFFFFFF /* Chip ID */ 620#define AR_XSREV_ID_S 0 621#define AR_XSREV_VERSION 0xFFFC0000 /* Chip version */ 622#define AR_XSREV_VERSION_S 18 623#define AR_XSREV_TYPE 0x0003F000 /* Chip type */ 624#define AR_XSREV_TYPE_S 12 625#define AR_XSREV_TYPE_CHAIN 0x00001000 /* Chain Mode (1:3 chains, 626 * 0:2 chains) */ 627#define AR_XSREV_TYPE_HOST_MODE 0x00002000 /* Host Mode (1:PCI, 0:PCIe) */ 628#define AR_XSREV_REVISION 0x00000F00 629#define AR_XSREV_REVISION_S 8 630 631#define AR_XSREV_VERSION_OWL_PCI 0x0D 632#define AR_XSREV_VERSION_OWL_PCIE 0x0C 633 634 635/* 636 * These are from ath9k/Atheros and assume an AR_SREV version mask 637 * of 0x07, rather than 0x0F which is being used in the FreeBSD HAL. 638 * Thus, don't use these values as they're incorrect here; use 639 * AR_SREV_REVISION_OWL_{10,20,22}. 640 */ 641#if 0 642#define AR_XSREV_REVISION_OWL_10 0 /* Owl 1.0 */ 643#define AR_XSREV_REVISION_OWL_20 1 /* Owl 2.0/2.1 */ 644#define AR_XSREV_REVISION_OWL_22 2 /* Owl 2.2 */ 645#endif 646 647#define AR_XSREV_VERSION_HOWL 0x14 /* Howl (AR9130) */ 648#define AR_XSREV_VERSION_SOWL 0x40 /* Sowl (AR9160) */ 649#define AR_XSREV_REVISION_SOWL_10 0 /* Sowl 1.0 */ 650#define AR_XSREV_REVISION_SOWL_11 1 /* Sowl 1.1 */ 651#define AR_XSREV_VERSION_MERLIN 0x80 /* Merlin Version */ 652#define AR_XSREV_REVISION_MERLIN_10 0 /* Merlin 1.0 */ 653#define AR_XSREV_REVISION_MERLIN_20 1 /* Merlin 2.0 */ 654#define AR_XSREV_REVISION_MERLIN_21 2 /* Merlin 2.1 */ 655#define AR_XSREV_VERSION_KITE 0xC0 /* Kite Version */ 656#define AR_XSREV_REVISION_KITE_10 0 /* Kite 1.0 */ 657#define AR_XSREV_REVISION_KITE_11 1 /* Kite 1.1 */ 658#define AR_XSREV_REVISION_KITE_12 2 /* Kite 1.2 */ 659 660/* Owl (AR5416) */ 661#define AR_SREV_OWL(_ah) \ 662 ((AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_OWL_PCI) || \ 663 (AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_OWL_PCIE)) 664 665#define AR_SREV_OWL_20_OR_LATER(_ah) \ 666 ((AR_SREV_OWL(_ah) && \ 667 AH_PRIVATE((_ah))->ah_macRev >= AR_SREV_REVISION_OWL_20) || \ 668 AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_HOWL) 669 670#define AR_SREV_OWL_22_OR_LATER(_ah) \ 671 ((AR_SREV_OWL(_ah) && \ 672 AH_PRIVATE((_ah))->ah_macRev >= AR_SREV_REVISION_OWL_22) || \ 673 AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_HOWL) 674 675/* Howl (AR9130) */ 676 677#define AR_SREV_HOWL(_ah) \ 678 (AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_HOWL) 679 680#define AR_SREV_9100(_ah) AR_SREV_HOWL(_ah) 681 682/* Sowl (AR9160) */ 683 684#define AR_SREV_SOWL(_ah) \ 685 (AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_SOWL) 686 687#define AR_SREV_SOWL_10_OR_LATER(_ah) \ 688 (AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_SOWL) 689 690#define AR_SREV_SOWL_11(_ah) \ 691 (AR_SREV_SOWL(_ah) && \ 692 AH_PRIVATE((_ah))->ah_macRev == AR_XSREV_REVISION_SOWL_11) 693 694/* Merlin (AR9280) */ 695 696#define AR_SREV_MERLIN(_ah) \ 697 (AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_MERLIN) 698 699#define AR_SREV_MERLIN_10_OR_LATER(_ah) \ 700 (AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_MERLIN) 701 702#define AR_SREV_MERLIN_20(_ah) \ 703 (AR_SREV_MERLIN(_ah) && \ 704 AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_MERLIN_20) 705 706#define AR_SREV_MERLIN_20_OR_LATER(_ah) \ 707 ((AH_PRIVATE((_ah))->ah_macVersion > AR_XSREV_VERSION_MERLIN) || \ 708 (AR_SREV_MERLIN((_ah)) && \ 709 AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_MERLIN_20)) 710 711/* Kite (AR9285) */ 712 713#define AR_SREV_KITE(_ah) \ 714 (AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_KITE) 715 716#define AR_SREV_KITE_10_OR_LATER(_ah) \ 717 (AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_KITE) 718 719#define AR_SREV_KITE_11(_ah) \ 720 (AR_SREV_KITE(ah) && \ 721 AH_PRIVATE((_ah))->ah_macRev == AR_XSREV_REVISION_KITE_11) 722 723#define AR_SREV_KITE_11_OR_LATER(_ah) \ 724 ((AH_PRIVATE((_ah))->ah_macVersion > AR_XSREV_VERSION_KITE) || \ 725 (AR_SREV_KITE((_ah)) && \ 726 AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_KITE_11)) 727 728#define AR_SREV_KITE_12(_ah) \ 729 (AR_SREV_KITE(ah) && \ 730 AH_PRIVATE((_ah))->ah_macRev == AR_XSREV_REVISION_KITE_12) 731 732#define AR_SREV_KITE_12_OR_LATER(_ah) \ 733 ((AH_PRIVATE((_ah))->ah_macVersion > AR_XSREV_VERSION_KITE) || \ 734 (AR_SREV_KITE((_ah)) && \ 735 AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_KITE_12)) 736 737#define AR_SREV_9285E_20(_ah) \ 738 (AR_SREV_KITE_12_OR_LATER(_ah) && \ 739 ((OS_REG_READ(_ah, AR_AN_SYNTH9) & 0x7) == 0x1)) 740 741/* Not yet implemented chips */ 742#define AR_SREV_9271(_ah) 0 743#define AR_SREV_9287_11_OR_LATER(_ah) 0 744#define AR_SREV_KIWI_10_OR_LATER(_ah) 0 745 746#endif /* _DEV_ATH_AR5416REG_H */ 747